diff --git a/project/WL468/WL468.uvguix.Felix b/project/WL468/WL468.uvguix.Felix new file mode 100644 index 0000000..27b555c --- /dev/null +++ b/project/WL468/WL468.uvguix.Felix @@ -0,0 +1,1914 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + WL468 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 244 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + C:\Users\songc\Desktop\WLC_Gen3_ISP_V5381_20230915\src\common\tau_dsi_datatype.h + + + + + 1 + 0 + 57 + 1 +
0
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### uVision Project, (C) Keil Software
+ + + + WL468 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM0 + ARM + ARM.CMSIS.5.5.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + WL468_demo + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 1 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin -o .\Objects\@L.bin .\Objects\@L.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 16 + 1 + 1 + 0 + 0 + 4 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x2000 + + + 1 + 0x10000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x70000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\src;..\..\src\board;..\..\src\common;..\..\src\sdk\include;..\..\src\sdk\include\M0;..\..\src\app;..\..\src\app\S8;..\..\src\app\touch;..\..\src\app\module_demo;..\..\src\app\Mi12Lite + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + app + + + main.c + 1 + ..\..\src\app\main.c + + + app_tp_transfer.c + 1 + ..\..\src\app\touch\app_tp_transfer.c + + + app_tp_for_custom_s8.c + 1 + ..\..\src\app\S8\app_tp_for_custom_s8.c + + + s8_demo.c + 1 + ..\..\src\app\S8\s8_demo.c + + + Mi12Lite.c + 1 + ..\..\src\app\Mi12Lite\Mi12Lite.c + + + + + driver + + + CVWL468.lib + 4 + ..\..\src\sdk\CVWL468\lib\CVWL468.lib + + + + + board + + + board.c + 1 + ..\..\src\board\board.c + + + + + startup + + + startup_ARMCM0.s + 2 + ..\..\src\board\startup\startup_ARMCM0.s + + + + + modules_demo + + + demo_hal_crc.c + 1 + ..\..\src\app\module_demo\demo_hal_crc.c + + + demo_hal_dsi_rx.c + 1 + ..\..\src\app\module_demo\demo_hal_dsi_rx.c + + + demo_hal_dsi_tx.c + 1 + ..\..\src\app\module_demo\demo_hal_dsi_tx.c + + + demo_hal_flash.c + 1 + ..\..\src\app\module_demo\demo_hal_flash.c + + + demo_hal_gpio.c + 1 + ..\..\src\app\module_demo\demo_hal_gpio.c + + + demo_hal_i2c.c + 1 + ..\..\src\app\module_demo\demo_hal_i2c.c + + + demo_hal_spi.c + 1 + ..\..\src\app\module_demo\demo_hal_spi.c + + + demo_hal_pwm.c + 1 + ..\..\src\app\module_demo\demo_hal_pwm.c + + + demo_hal_pwr.c + 1 + ..\..\src\app\module_demo\demo_hal_pwr.c + + + demo_hal_swire.c + 1 + ..\..\src\app\module_demo\demo_hal_swire.c + + + demo_hal_uart.c + 1 + ..\..\src\app\module_demo\demo_hal_uart.c + + + demo_hal_wdg.c + 1 + ..\..\src\app\module_demo\demo_hal_wdg.c + + + module_demo_main.c + 1 + ..\..\src\app\module_demo\module_demo_main.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\Device\ARMCM0\startup_ARMCM0.s + + + + + + RTE\Device\ARMCM0\system_ARMCM0.c + + + + + + + + diff --git a/project/WL668/Listings/WL668_P8P_TM667_ICNA3508_20240401.map b/project/WL668/Listings/WL668_P8P_TM667_ICNA3508_20240401.map new file mode 100644 index 0000000..4e265f3 --- /dev/null +++ b/project/WL668/Listings/WL668_P8P_TM667_ICNA3508_20240401.map @@ -0,0 +1,3994 @@ +Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed] + +============================================================================== + +Section Cross References + + main.o(i.main) refers to board.o(i.board_Init) for board_Init + main.o(i.main) refers to p8p_demo.o(i.google_p8p_demo) for google_p8p_demo + main.o(i.main) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.Gpio_swire_output) refers to hal_gpio.o(i.hal_gpio_init_output) for hal_gpio_init_output + p8p_demo.o(i.Gpio_swire_output) refers to tau_delay.o(i.delayMs) for delayMs + p8p_demo.o(i.Gpio_swire_output) refers to hal_gpio.o(i.hal_gpio_set_output_data) for hal_gpio_set_output_data + p8p_demo.o(i.Gpio_swire_output) refers to tau_delay.o(i.delayUs) for delayUs + p8p_demo.o(i.Panel_CCM) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_ccm) for hal_dsi_tx_ctrl_set_ccm + p8p_demo.o(i.REG_51_OFF_output) refers to idiv.o(.text) for __aeabi_idivmod + p8p_demo.o(i.REG_51_OFF_output) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd + p8p_demo.o(i.REG_51_OFF_output) refers to tau_delay.o(i.delayMs) for delayMs + p8p_demo.o(i.ap_dcs_read) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) for hal_dsi_rx_ctrl_send_ack_cmd + p8p_demo.o(i.ap_dcs_read) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) for hal_dsi_rx_ctrl_get_max_ret_size + p8p_demo.o(i.ap_dcs_read) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_dcs_read) refers to p8p_demo.o(.data) for g_rx_ctrl_handle + p8p_demo.o(i.ap_dcs_set_backlight) refers to idiv.o(.text) for __aeabi_idivmod + p8p_demo.o(i.ap_dcs_set_backlight) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd + p8p_demo.o(i.ap_dcs_set_backlight) refers to p8p_demo.o(.data) for rd_51_val + p8p_demo.o(i.ap_dcs_set_display_off) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_dcs_set_display_off) refers to p8p_demo.o(.data) for panel_display_done + p8p_demo.o(i.ap_dcs_set_display_on) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) for hal_dsi_rx_ctrl_pre_init_pps + p8p_demo.o(i.ap_dcs_set_display_on) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) for hal_dsi_rx_ctrl_toggle_resolution + p8p_demo.o(i.ap_dcs_set_display_on) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_dcs_set_display_on) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd + p8p_demo.o(i.ap_dcs_set_display_on) refers to p8p_demo.o(.data) for g_resolution_change + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) for hal_dsi_tx_ctrl_set_tear_mode + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to tau_delay.o(i.delayMs) for delayMs + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to hal_swire.o(i.hal_swire_enable) for hal_swire_enable + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to hal_gpio.o(i.hal_gpio_set_output_data) for hal_gpio_set_output_data + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to hal_gpio.o(i.hal_gpio_set_ap_reset_int) for hal_gpio_set_ap_reset_int + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to p8p_demo.o(.data) for g_tx_ctrl_handle + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to p8p_demo.o(i.ap_rstn_pull_down_cb) for ap_rstn_pull_down_cb + p8p_demo.o(i.ap_dcs_set_exit_idle_mode) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_hw_cmd_filter) for hal_dsi_rx_ctrl_set_hw_cmd_filter + p8p_demo.o(i.ap_dcs_set_exit_idle_mode) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_dcs_set_exit_idle_mode) refers to p8p_demo.o(.data) for sg_exit_idle_mode_flag + p8p_demo.o(i.ap_dcs_set_exit_sleep_mode) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_dcs_set_frame_change) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) for hal_dsi_tx_ctrl_set_tear_mode + p8p_demo.o(i.ap_dcs_set_frame_change) refers to p8p_demo.o(.data) for g_tx_ctrl_handle + p8p_demo.o(i.ap_rstn_pull_down_cb) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_rstn_pull_down_cb) refers to hal_gpio.o(i.hal_gpio_set_ap_reset_int) for hal_gpio_set_ap_reset_int + p8p_demo.o(i.ap_rstn_pull_down_cb) refers to p8p_demo.o(.data) for sg_system_suspend + p8p_demo.o(i.ap_rstn_pull_high_cb) refers to hal_gpio.o(i.hal_gpio_set_ap_reset_int) for hal_gpio_set_ap_reset_int + p8p_demo.o(i.ap_rstn_pull_high_cb) refers to p8p_demo.o(.data) for sg_system_resume + p8p_demo.o(i.ap_set_FPS_53) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd + p8p_demo.o(i.app_display_init) refers to p8p_demo.o(i.app_mipi_rx_init) for app_mipi_rx_init + p8p_demo.o(i.app_display_init) refers to hal_pwr.o(i.hal_pwr_get_vcc_power_ready) for hal_pwr_get_vcc_power_ready + p8p_demo.o(i.app_display_init) refers to p8p_demo.o(i.app_gpio_init) for app_gpio_init + p8p_demo.o(i.app_display_init) refers to hal_swire.o(i.hal_swire_init) for hal_swire_init + p8p_demo.o(i.app_display_init) refers to hal_swire.o(i.hal_swire_set_timer) for hal_swire_set_timer + p8p_demo.o(i.app_display_init) refers to p8p_demo.o(i.app_mipi_tx_init) for app_mipi_tx_init + p8p_demo.o(i.app_display_init) refers to p8p_demo.o(i.app_mipi_tx_start) for app_mipi_tx_start + p8p_demo.o(i.app_gpio_init) refers to hal_gpio.o(i.hal_gpio_config_pad) for hal_gpio_config_pad + p8p_demo.o(i.app_gpio_init) refers to p8p_demo.o(.constdata) for .constdata + p8p_demo.o(i.app_init_panel) refers to p8p_demo.o(i.app_tx_panel_reset) for app_tx_panel_reset + p8p_demo.o(i.app_init_panel) refers to p8p_demo.o(i.send_panel_init_code) for send_panel_init_code + p8p_demo.o(i.app_init_panel) refers to hal_gpio.o(i.hal_gpio_init_output) for hal_gpio_init_output + p8p_demo.o(i.app_init_panel) refers to tau_delay.o(i.delayMs) for delayMs + p8p_demo.o(i.app_init_panel) refers to hal_swire.o(i.hal_swire_enable) for hal_swire_enable + p8p_demo.o(i.app_init_panel) refers to hal_swire.o(i.hal_swire_set_pulse) for hal_swire_set_pulse + p8p_demo.o(i.app_init_panel) refers to p8p_demo.o(.constdata) for panel_init_code + p8p_demo.o(i.app_mipi_rx_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) for hal_dsi_rx_ctrl_create_handle + p8p_demo.o(i.app_mipi_rx_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) for hal_dsi_rx_ctrl_pre_init_pps + p8p_demo.o(i.app_mipi_rx_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) for hal_dsi_rx_ctrl_init + p8p_demo.o(i.app_mipi_rx_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) for hal_dsi_rx_ctrl_start + p8p_demo.o(i.app_mipi_rx_init) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.app_mipi_rx_init) refers to p8p_demo.o(.data) for g_rx_ctrl_handle + p8p_demo.o(i.app_mipi_rx_init) refers to p8p_demo.o(.constdata) for g_cus_rx_dcs_execute_table + p8p_demo.o(i.app_mipi_rx_init) refers to p8p_demo.o(i.ap_dcs_read) for ap_dcs_read + p8p_demo.o(i.app_mipi_rx_init) refers to p8p_demo.o(i.pps_update_handle) for pps_update_handle + p8p_demo.o(i.app_mipi_tx_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) for hal_dsi_tx_ctrl_create_handle + p8p_demo.o(i.app_mipi_tx_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) for hal_dsi_tx_ctrl_init + p8p_demo.o(i.app_mipi_tx_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb) for hal_dsi_tx_ctrl_set_overwrite_rgb + p8p_demo.o(i.app_mipi_tx_init) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.app_mipi_tx_init) refers to p8p_demo.o(.data) for g_tx_ctrl_handle + p8p_demo.o(i.app_mipi_tx_start) refers to p8p_demo.o(i.app_init_panel) for app_init_panel + p8p_demo.o(i.app_mipi_tx_start) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) for hal_dsi_tx_ctrl_start + p8p_demo.o(i.app_mipi_tx_start) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) for hal_dsi_tx_ctrl_set_tear_mode + p8p_demo.o(i.app_mipi_tx_start) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) for hal_dsi_rx_ctrl_pre_init_pps + p8p_demo.o(i.app_mipi_tx_start) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) for hal_dsi_rx_ctrl_toggle_resolution + p8p_demo.o(i.app_mipi_tx_start) refers to tau_delay.o(i.delayMs) for delayMs + p8p_demo.o(i.app_mipi_tx_start) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd + p8p_demo.o(i.app_mipi_tx_start) refers to hal_swire.o(i.hal_swire_set_pulse) for hal_swire_set_pulse + p8p_demo.o(i.app_mipi_tx_start) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.app_mipi_tx_start) refers to p8p_demo.o(.data) for g_tx_ctrl_handle + p8p_demo.o(i.app_system_process) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.app_system_process) refers to p8p_demo.o(i.app_system_suspend) for app_system_suspend + p8p_demo.o(i.app_system_process) refers to p8p_demo.o(i.app_system_resume) for app_system_resume + p8p_demo.o(i.app_system_process) refers to p8p_demo.o(.data) for sg_system_suspend + p8p_demo.o(i.app_system_resume) refers to hal_pwr.o(i.hal_pwr_exit_sleep_mode) for hal_pwr_exit_sleep_mode + p8p_demo.o(i.app_system_resume) refers to p8p_demo.o(i.app_display_init) for app_display_init + p8p_demo.o(i.app_system_resume) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.app_system_suspend) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) for hal_dsi_tx_ctrl_stop + p8p_demo.o(i.app_system_suspend) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) for hal_dsi_tx_ctrl_deinit + p8p_demo.o(i.app_system_suspend) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) for hal_dsi_rx_ctrl_stop + p8p_demo.o(i.app_system_suspend) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) for hal_dsi_rx_ctrl_deinit + p8p_demo.o(i.app_system_suspend) refers to hal_gpio.o(i.hal_gpio_init_output) for hal_gpio_init_output + p8p_demo.o(i.app_system_suspend) refers to hal_swire.o(i.hal_swire_deinit) for hal_swire_deinit + p8p_demo.o(i.app_system_suspend) refers to hal_pwr.o(i.hal_pwr_set_sleep_mode_power) for hal_pwr_set_sleep_mode_power + p8p_demo.o(i.app_system_suspend) refers to hal_gpio.o(i.hal_gpio_set_ap_reset_int) for hal_gpio_set_ap_reset_int + p8p_demo.o(i.app_system_suspend) refers to hal_pwr.o(i.hal_pwr_enter_normal_sleep_mode) for hal_pwr_enter_normal_sleep_mode + p8p_demo.o(i.app_system_suspend) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.app_system_suspend) refers to hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) for hal_pwr_set_stop_sleep_wakeup_pin + p8p_demo.o(i.app_system_suspend) refers to hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode) for hal_pwr_enter_stop_sleep_mode + p8p_demo.o(i.app_system_suspend) refers to hal_pwr.o(i.hal_pwr_enter_deep_sleep_mode) for hal_pwr_enter_deep_sleep_mode + p8p_demo.o(i.app_system_suspend) refers to p8p_demo.o(.data) for g_tx_ctrl_handle + p8p_demo.o(i.app_system_suspend) refers to p8p_demo.o(i.ap_rstn_pull_high_cb) for ap_rstn_pull_high_cb + p8p_demo.o(i.app_tx_panel_reset) refers to hal_gpio.o(i.hal_gpio_set_output_data) for hal_gpio_set_output_data + p8p_demo.o(i.app_tx_panel_reset) refers to tau_delay.o(i.delayMs) for delayMs + p8p_demo.o(i.google_p8p_demo) refers to hal_pwr.o(i.hal_pwr_set_main_power) for hal_pwr_set_main_power + p8p_demo.o(i.google_p8p_demo) refers to p8p_demo.o(i.app_display_init) for app_display_init + p8p_demo.o(i.google_p8p_demo) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.google_p8p_demo) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) for hal_dsi_rx_ctrl_dcs_async_handler + p8p_demo.o(i.google_p8p_demo) refers to p8p_demo.o(i.app_system_process) for app_system_process + p8p_demo.o(i.google_p8p_demo) refers to p8p_demo.o(.data) for g_rx_ctrl_handle + p8p_demo.o(i.pps_update_handle) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) for hal_dsi_tx_ctrl_set_tear_mode + p8p_demo.o(i.pps_update_handle) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) for hal_dsi_rx_ctrl_toggle_resolution + p8p_demo.o(i.pps_update_handle) refers to p8p_demo.o(.data) for g_rx_ctrl_handle + p8p_demo.o(i.send_panel_init_code) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) for hal_dsi_tx_ctrl_write_array_cmd + p8p_demo.o(i.send_panel_init_code) refers to tau_delay.o(i.delayUs) for delayUs + p8p_demo.o(i.soft_te_timer_cb) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) for hal_dsi_tx_ctrl_gen_a_tear_signal + p8p_demo.o(i.soft_te_timer_cb) refers to hal_timer.o(i.hal_timer_start) for hal_timer_start + p8p_demo.o(i.soft_te_timer_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) for hal_dsi_tx_ctrl_set_tear_mode + p8p_demo.o(i.soft_te_timer_init) refers to hal_timer.o(i.hal_timer_init) for hal_timer_init + p8p_demo.o(i.soft_te_timer_init) refers to hal_timer.o(i.hal_timer_start) for hal_timer_start + p8p_demo.o(i.soft_te_timer_init) refers to p8p_demo.o(.data) for g_tx_ctrl_handle + p8p_demo.o(i.soft_te_timer_init) refers to p8p_demo.o(i.soft_te_timer_cb) for soft_te_timer_cb + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_dcs_set_display_on) for ap_dcs_set_display_on + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_dcs_set_display_off) for ap_dcs_set_display_off + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_dcs_set_backlight) for ap_dcs_set_backlight + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_set_FPS_53) for ap_set_FPS_53 + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) for ap_dcs_set_enter_sleep_mode + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_dcs_set_exit_sleep_mode) for ap_dcs_set_exit_sleep_mode + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_dcs_set_frame_change) for ap_dcs_set_frame_change + board.o(i.board_Init) refers to hal_system.o(i.hal_system_init) for hal_system_init + board.o(i.board_Init) refers to tau_log.o(i.tau_log_init) for tau_log_init + startup_armcm0.o(RESET) refers to startup_armcm0.o(STACK) for __initial_sp + startup_armcm0.o(RESET) refers to startup_armcm0.o(.text) for Reset_Handler + startup_armcm0.o(RESET) refers to drv_common.o(i.HardFault_Handler) for HardFault_Handler + startup_armcm0.o(RESET) refers to drv_common.o(i.SysTick_Handler) for SysTick_Handler + startup_armcm0.o(RESET) refers to drv_vidc.o(i.VIDC_IRQn_Handler) for VIDC_IRQn_Handler + startup_armcm0.o(RESET) refers to hal_internal_vsync.o(i.LCDC_IRQn_Handler) for LCDC_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler) for MIPI_RX_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler) for MIPI_TX_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_memc.o(i.MEMC_IRQn_Handler) for MEMC_IRQn_Handler + startup_armcm0.o(RESET) refers to hal_internal_dcs.o(i.VPRE_IRQn_Handler) for VPRE_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_dma.o(i.DMA_IRQn_Handler) for DMA_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_timer.o(i.TIMER0_IRQn_Handler) for TIMER0_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_timer.o(i.TIMER1_IRQn_Handler) for TIMER1_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_timer.o(i.TIMER2_IRQn_Handler) for TIMER2_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_timer.o(i.TIMER3_IRQn_Handler) for TIMER3_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_uart.o(i.UART_IRQn_Handler) for UART_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_rxbr.o(i.VPRE1_IRQn_Handler) for VPRE1_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_swire.o(i.SWIRE_IRQn_Handler) for SWIRE_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.AP_NRESET_IRQn_Handler) for AP_NRESET_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT0_IRQn_Handler) for EXTI_INT0_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT1_IRQn_Handler) for EXTI_INT1_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT2_IRQn_Handler) for EXTI_INT2_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT3_IRQn_Handler) for EXTI_INT3_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT4_IRQn_Handler) for EXTI_INT4_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT5_IRQn_Handler) for EXTI_INT5_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT6_IRQn_Handler) for EXTI_INT6_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT7_IRQn_Handler) for EXTI_INT7_IRQn_Handler + startup_armcm0.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_ack_long_cmd) refers to drv_rxbr.o(i.drv_rxbr_set_ack_pkt_md) for drv_rxbr_set_ack_pkt_md + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_ack_long_cmd) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_lpdt_fifo_status) for drv_dsi_rx_get_lpdt_fifo_status + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) refers to memseta.o(.text) for __aeabi_memclr4 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) refers to dcs_packet_fifo.o(i.dcs_packet_get_fifo_header) for dcs_packet_get_fifo_header + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) refers to dcs_packet_fifo.o(i.dcs_packet_free_fifo_header) for dcs_packet_free_fifo_header + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_rx_state) for hal_internal_vsync_get_rx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_dsc_dec.o(i.drv_dsc_dec_disable) for drv_dsc_dec_disable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) for drv_dsi_rx_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_rxbr.o(i.drv_rxbr_enable_irq) for drv_rxbr_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_vidc.o(i.drv_vidc_enable_irq) for drv_vidc_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_memc.o(i.drv_memc_enable_irq) for drv_memc_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_crgu.o(i.drv_crgu_reset_modules) for drv_crgu_reset_modules + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) for hal_internal_vsync_set_rx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_rxbr.o(i.drv_rxbr_swpxl_clr) for drv_rxbr_swpxl_clr + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_rxbr.o(i.drv_rxbr_set_cmd_filter) for drv_rxbr_set_cmd_filter + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_dsc_dec.o(i.drv_dsc_dec_disable) for drv_dsc_dec_disable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_vidc.o(i.drv_vidc_set_src_parameter) for drv_vidc_set_src_parameter + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_vidc.o(i.drv_vidc_set_scld_step) for drv_vidc_set_scld_step + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_vidc.o(i.drv_vidc_set_pu_ctrl) for drv_vidc_set_pu_ctrl + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_rxbr.o(i.drv_rxbr_set_swpxl_data) for drv_rxbr_set_swpxl_data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_pg_cfg) for drv_dsi_rx_set_ddi_pg_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to drv_crgu.o(i.drv_crgu_get_rxbr_clk) for drv_crgu_get_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to idiv.o(.text) for __aeabi_idivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) for hal_dsi_rx_ctrl_set_rx_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_pg_cfg) for drv_dsi_rx_set_ipi_pg_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to hal_dsi_rx_ctrl.o(.constdata) for .constdata + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to hal_dsi_rx_ctrl.o(.conststring) for .conststring + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_force_video_crtl) refers to drv_dsi_rx.o(i.drv_dsi_rx_force_video_crtl) for drv_dsi_rx_force_video_crtl + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_compressen_en) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en) for drv_dsi_rx_get_compression_en + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_max_ret_size) for drv_dsi_rx_get_max_ret_size + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) for hal_dsi_rx_ctrl_init_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_internal_vsync.o(i.hal_internal_vsync_init_rx) for hal_internal_vsync_init_rx + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) for hal_dsi_rx_ctrl_init_dsi_rx + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) for hal_dsi_rx_ctrl_init_rxbr + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to drv_dsc_dec.o(i.drv_dsc_dec_enable) for drv_dsc_dec_enable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to drv_dsc_dec.o(i.drv_dsc_dec_set_irqen) for drv_dsc_dec_set_irqen + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) for hal_dsi_rx_ctrl_init_vidc + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) for hal_dsi_rx_ctrl_init_memc + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) for hal_internal_vsync_set_rx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to drv_se.o(i.drv_se_start_rx) for drv_se_start_rx + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) refers to drv_pwr.o(i.drv_pwr_set_pll_clk) for drv_pwr_set_pll_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) refers to drv_crgu.o(i.drv_crgu_set_rxbr_clk) for drv_crgu_set_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) refers to drv_crgu.o(i.drv_crgu_set_dsc_clk) for drv_crgu_set_dsc_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) refers to drv_crgu.o(i.drv_crgu_set_vidc_clk) for drv_crgu_set_vidc_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) refers to drv_crgu.o(i.drv_crgu_set_fb_clk) for drv_crgu_set_fb_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_crgu.o(i.drv_crgu_get_rxbr_clk) for drv_crgu_get_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ctrl_cfg) for drv_dsi_rx_set_ctrl_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) for drv_dsi_rx_set_ddi_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) for hal_dsi_rx_ctrl_set_ipi_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) for drv_dsi_rx_set_up_phy + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_lane_swap) for drv_dsi_rx_set_lane_swap + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_crc_en) for drv_dsi_rx_set_ddi_crc_en + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_ycbcr_frmt) for drv_dsi_rx_set_ipi_ycbcr_frmt + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_tear_resp_en) for drv_dsi_rx_set_tear_resp_en + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_inten) for drv_dsi_rx_set_inten + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_check_crc) for drv_dsi_rx_set_check_crc + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_resp_cnt) for drv_dsi_rx_set_resp_cnt + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) for drv_dsi_rx_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) for hal_intl_fb_get_memc_flow_mode + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_data_mode) for drv_memc_set_data_mode + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_ltpo_mode) for drv_memc_set_ltpo_mode + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_rate_transfer_sel) for drv_memc_rate_transfer_sel + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_fs_en_conditions) for drv_memc_set_fs_en_conditions + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_lcdc_st_conditions) for drv_memc_set_lcdc_st_conditions + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_sel_vsync) for drv_memc_sel_vsync + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_vidc_sync_cnt) for drv_memc_set_vidc_sync_cnt + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_tear_waveform) for drv_memc_set_tear_waveform + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_tear_mode) for drv_memc_set_tear_mode + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_double_buffer) for drv_memc_set_double_buffer + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_circ_mode_enable) for drv_memc_set_circ_mode_enable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_active_height) for drv_memc_set_active_height + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_ltpo_pu_thres) for drv_memc_set_ltpo_pu_thres + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_enable_irq) for drv_memc_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_set_color_format) for drv_rxbr_set_color_format + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) for hal_intl_fb_get_memc_flow_mode + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_set_ltpo_drop_th) for drv_rxbr_set_ltpo_drop_th + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) for drv_rxbr_frame_drop_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_set_usr_cfg) for drv_rxbr_set_usr_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_set_usr_col) for drv_rxbr_set_usr_col + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_set_usr_row) for drv_rxbr_set_usr_row + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_hline_rcv_cfg) for drv_rxbr_hline_rcv_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_enable_irq) for drv_rxbr_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) for hal_intl_dcs_set_auto_hw_filter + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_src_parameter) for drv_vidc_set_src_parameter + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_pentile_swap) for drv_vidc_set_pentile_swap + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_dst_parameter) for drv_vidc_set_dst_parameter + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_circ_mode_enable) for drv_vidc_set_circ_mode_enable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_init_module_enable) for drv_vidc_init_module_enable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_dither_config) for drv_vidc_set_dither_config + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_vintp_config) for drv_vidc_set_vintp_config + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_rotation) for drv_vidc_set_rotation + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to dfltui.o(.text) for __aeabi_ui2d + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to dadd.o(.text) for __aeabi_dadd + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_scld_step) for drv_vidc_set_scld_step + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_scld_hcoef0) for drv_vidc_set_scld_hcoef0 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_scld_hcoef1) for drv_vidc_set_scld_hcoef1 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_scld_vcoef0) for drv_vidc_set_scld_vcoef0 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_scld_vcoef1) for drv_vidc_set_scld_vcoef1 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_honly_hinitr) for drv_vidc_set_honly_hinitr + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_honly_hinitb) for drv_vidc_set_honly_hinitb + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_honly_hcoef0) for drv_vidc_set_honly_hcoef0 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_mirror) for drv_vidc_set_mirror + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_pu_ctrl) for drv_vidc_set_pu_ctrl + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_irqen) for drv_vidc_set_irqen + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_enable_irq) for drv_vidc_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to hal_dsi_rx_ctrl.o(.constdata) for .constdata + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_callback) refers to hal_internal_vsync.o(i.hal_internal_sync_register_rx_callback) for hal_internal_sync_register_rx_callback + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_callback) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_callback) refers to drv_vidc.o(i.drv_vidc_set_irq_line) for drv_vidc_set_irq_line + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_callback) refers to drv_vidc.o(i.drv_vidc_set_irqen) for drv_vidc_set_irqen + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_write_cmd_entry) refers to hal_internal_dcs.o(i.hal_intl_dcs_register_write_cmd_entry) for hal_intl_dcs_register_write_cmd_entry + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_release_handle) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) refers to drv_dsi_rx.o(i.drv_dsi_rx_shut_down) for drv_dsi_rx_shut_down + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) for hal_dsi_rx_ctrl_init + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) for hal_dsi_rx_ctrl_start + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) refers to drv_rxbr.o(i.drv_rxbr_set_ack_pkt_header) for drv_rxbr_set_ack_pkt_header + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) refers to hal_dsi_rx_ctrl.o(.conststring) for .conststring + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_ack) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_ack) refers to drv_rxbr.o(i.drv_rxbr_set_cmd_response) for drv_rxbr_set_cmd_response + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_ack) refers to hal_dsi_rx_ctrl.o(.conststring) for .conststring + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_hw_filter) refers to hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) for hal_intl_dcs_set_auto_hw_filter + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_hw_filter) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_check_crc) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_check_crc) for drv_dsi_rx_set_check_crc + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_check_crc) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk) refers to drv_crgu.o(i.drv_crgu_get_rxbr_clk) for drv_crgu_get_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) for drv_dsi_rx_set_ddi_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_hw_cmd_filter) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) refers to drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) for drv_dsi_rx_calc_ipi_tx_delay + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_cfg) for drv_dsi_rx_set_ipi_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_log_level) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_drv_log_level) for drv_dsi_rx_set_drv_log_level + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data) refers to drv_rxbr.o(i.drv_rxbr_sw_reset) for drv_rxbr_sw_reset + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rxbr_clk) for hal_dsi_rx_ctrl_set_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) for hal_intl_svs_update_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to drv_crgu.o(i.drv_crgu_get_rxbr_clk) for drv_crgu_get_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) for drv_dsi_rx_set_ddi_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) for hal_dsi_rx_ctrl_set_ipi_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rxbr_clk) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rxbr_clk) refers to drv_crgu.o(i.drv_crgu_set_rxbr_clk) for drv_crgu_set_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) refers to drv_vidc.o(i.drv_vidc_enable) for drv_vidc_enable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) refers to drv_dsi_rx.o(i.drv_dsi_rx_power_up) for drv_dsi_rx_power_up + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) for hal_internal_vsync_set_rx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) refers to drv_vidc.o(i.drv_vidc_enable) for drv_vidc_enable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) refers to drv_dsi_rx.o(i.drv_dsi_rx_shut_down) for drv_dsi_rx_shut_down + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) for hal_internal_vsync_set_rx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_input_frame_rate) refers to hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) for hal_internal_vsync_toggle_input_frame_rate + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) refers to hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) for hal_internal_sync_input_resolution_change + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to fdiv.o(.text) for __aeabi_fdiv + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to fadd.o(.text) for __aeabi_fadd + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to ffltui.o(.text) for __aeabi_ui2f + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to fmul.o(.text) for __aeabi_fmul + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to f2d.o(.text) for __aeabi_f2d + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to ceil.o(i.ceil) for ceil + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to idiv.o(.text) for __aeabi_idivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) for hal_internal_sync_get_hight_performan_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_shutdown) for drv_dsi_tx_shutdown + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) for hal_dsi_tx_ctrl_init_clk + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg) for drv_dsi_tx_phy_time_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) for drv_dsi_tx_phy_test_setup + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_mode) for drv_dsi_tx_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) for drv_dsi_tx_set_esc_div + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready) for drv_dsi_tx_phy_status_ready + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_powerup) for drv_dsi_tx_powerup + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_crgu.o(i.drv_crgu_reset_modules) for drv_crgu_reset_modules + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) refers to memseta.o(.text) for __aeabi_memclr4 + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to drv_crgu.o(i.drv_crgu_reset_modules) for drv_crgu_reset_modules + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) for hal_internal_vsync_set_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to hal_internal_vsync.o(i.hal_internal_sync_register_lcdc_cb) for hal_internal_sync_register_lcdc_cb + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to memseta.o(.text) for __aeabi_memclr4 + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to drv_vidc.o(i.drv_vidc_enable) for drv_vidc_enable + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to hal_internal_vsync.o(i.hal_internal_sync_set_fb_setting_manual) for hal_internal_sync_set_fb_setting_manual + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) for hal_lcdc_init_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to drv_memc.o(i.drv_memc_set_data_mode) for drv_memc_set_data_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_frame) refers to drv_lcdc.o(i.drv_lcdc_fixed_frame_output) for drv_lcdc_fixed_frame_output + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) refers to drv_memc.o(i.drv_memc_get_tear_mode) for drv_memc_get_tear_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) refers to drv_memc.o(i.drv_memc_set_tear_mode) for drv_memc_set_tear_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) refers to drv_memc.o(i.drv_memc_gen_a_tear_signal) for drv_memc_gen_a_tear_signal + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_internal_vsync.o(i.hal_internal_vsync_init_tx) for hal_internal_vsync_init_tx + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_internal_vsync.o(i.hal_internal_sync_register_lcdc_cb) for hal_internal_sync_register_lcdc_cb + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) for hal_dsi_tx_ctrl_init_clk + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) for hal_dsi_tx_init_timing + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) for hal_dsi_tx_init_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) for hal_lcdc_init_clk + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) for hal_lcdc_init_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready) for drv_dsi_tx_phy_status_ready + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to drv_dsi_tx.o(i.drv_dsi_tx_powerup) for drv_dsi_tx_powerup + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) for hal_internal_vsync_set_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) for hal_nonshadow_func_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_vsync_func_update) for hal_vsync_func_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_overwrite_enable) refers to drv_lcdc.o(i.drv_lcdc_function_enable) for drv_lcdc_function_enable + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_overwrite_enable) refers to drv_lcdc.o(i.drv_lcdc_function_disable) for drv_lcdc_function_disable + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_partial_disp_enable) refers to drv_lcdc.o(i.drv_lcdc_part_display_config) for drv_lcdc_part_display_config + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_partial_disp_enable) refers to drv_lcdc.o(i.drv_lcdc_function_disable) for drv_lcdc_function_disable + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd) refers to memseta.o(.text) for __aeabi_memclr4 + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) for hal_dsi_tx_send_cmd + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) for drv_dsi_tx_get_cmd_status + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_get_payload) for drv_dsi_tx_command_get_payload + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd) refers to memcpya.o(.text) for __aeabi_memcpy + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_release_handle) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_bcs) refers to memcpya.o(.text) for __aeabi_memcpy + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_bcs) refers to hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_req_update) for hal_nonshadow_func_req_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_bcs) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_bcs) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_bcs) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for .ARM.__at_0x1102C + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_cus_sync_line) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) for hal_internal_vsync_set_sync_line + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_cus_sync_line) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_dect) refers to hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_req_update) for hal_nonshadow_func_req_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_dect) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_dect) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_dect) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for .ARM.__at_0x1102C + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_enhance) refers to memcpya.o(.text) for __aeabi_memcpy + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_enhance) refers to hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_req_update) for hal_nonshadow_func_req_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_enhance) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_enhance) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_enhance) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for .ARM.__at_0x1102C + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_endianness) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_escape_clock_div) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_escape_clock_div) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) for drv_dsi_tx_set_esc_div + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_escape_clock_div) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_fc) refers to hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_req_update) for hal_nonshadow_func_req_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_fc) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_fc) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_fc) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for .ARM.__at_0x1102C + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb) refers to drv_lcdc.o(i.drv_lcdc_config_overwrite_rgb) for drv_lcdc_config_overwrite_rgb + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) for hal_internal_vsync_set_tear_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_vpg) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_vpg) for drv_dsi_tx_set_vpg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_vpg) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) for hal_dsi_tx_ctrl_draw_flick + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_dsi_tx.o(i.drv_dsi_tx_shutdown) for drv_dsi_tx_shutdown + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_dsi_tx.o(i.drv_dsi_tx_mode) for drv_dsi_tx_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_dsi_tx.o(i.drv_dsi_tx_config_eotp) for drv_dsi_tx_config_eotp + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg) for drv_dsi_tx_command_mode_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_lcdc.o(i.drv_lcdc_cfg_int_frame) for drv_lcdc_cfg_int_frame + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) for hal_intl_fb_get_memc_flow_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_lcdc.o(i.drv_lcdc_function_enable) for drv_lcdc_function_enable + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_dsi_tx.o(i.drv_dsi_tx_powerup) for drv_dsi_tx_powerup + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_lcdc.o(i.drv_lcdc_enable_shadow_reg) for drv_lcdc_enable_shadow_reg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_start) for hal_lcdc_start + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) for hal_internal_vsync_set_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) refers to drv_lcdc.o(i.drv_lcdc_stop_display) for drv_lcdc_stop_display + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) refers to drv_lcdc.o(i.drv_lcdc_set_int) for drv_lcdc_set_int + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_int) for drv_dsi_tx_set_int + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) refers to drv_dsi_tx.o(i.drv_dsi_tx_shutdown) for drv_dsi_tx_shutdown + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) for hal_internal_vsync_set_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_vporch_bta_opera) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_vporch_bta_opera) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd) for hal_dsi_tx_ctrl_read_cmd + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_vporch_bta_opera) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) for hal_dsi_tx_send_cmd + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) for drv_dsi_tx_get_cmd_status + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) for drv_dsi_tx_command_put_payload + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) for hal_dsi_tx_send_cmd + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) for drv_dsi_tx_get_cmd_status + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) for drv_dsi_tx_command_put_payload + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_video_mode_cfg) for drv_dsi_tx_video_mode_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_bta_ack) for drv_dsi_tx_set_bta_ack + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_dpi_lpcmd_time) for drv_dsi_tx_dpi_lpcmd_time + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg) for drv_dsi_tx_command_mode_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_mode) for drv_dsi_tx_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_lane_mode) for drv_dsi_tx_phy_lane_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_dpi_mode) for drv_dsi_tx_dpi_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_dpi_polarity) for drv_dsi_tx_dpi_polarity + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_response_mode) for drv_dsi_tx_response_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_config_eotp) for drv_dsi_tx_config_eotp + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) for drv_dsi_tx_set_esc_div + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_time_out_div) for drv_dsi_tx_set_time_out_div + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to memseta.o(.text) for __aeabi_memclr4 + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_timeout_cfg) for drv_dsi_tx_timeout_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs) for drv_dsi_tx_phy_clock_lane_req_hs + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp) for drv_dsi_tx_phy_clock_lane_auto_lp + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_config_int) for drv_dsi_tx_config_int + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_int) for drv_dsi_tx_set_int + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) refers to drv_crgu.o(i.drv_crgu_set_dpi_clk) for drv_crgu_set_dpi_clk + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) refers to hal_dsi_tx_ctrl.o(.constdata) for .constdata + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg) for drv_dsi_tx_phy_time_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) for drv_dsi_tx_phy_test_setup + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_timing_info_update) for hal_dsi_tx_timing_info_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) for hal_dsi_tx_cmd_mode_cal_timing + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to drv_dsi_tx.o(i.drv_dsi_tx_edpi_cmd_size) for drv_dsi_tx_edpi_cmd_size + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) for hal_dsi_tx_init_phy_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) for hal_dsi_tx_init_dpi_timing + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) for hal_dsi_tx_vid_mode_cal_timing + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_vid_timing) for hal_dsi_tx_init_vid_timing + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_vid_timing) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_video_chunk) for drv_dsi_tx_set_video_chunk + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_vid_timing) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_video_timing) for drv_dsi_tx_set_video_timing + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) for drv_dsi_tx_get_cmd_status + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_header) for drv_dsi_tx_command_header + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) for drv_dsi_tx_phy_status_stopstate + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_timing_info_update) refers to d2f.o(.text) for __aeabi_d2f + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_timing_info_update) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to ffltui.o(.text) for __aeabi_ui2f + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to fmul.o(.text) for __aeabi_fmul + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to fdiv.o(.text) for __aeabi_fdiv + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to f2d.o(.text) for __aeabi_f2d + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to ceil.o(i.ceil) for ceil + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to idiv.o(.text) for __aeabi_idivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) for hal_internal_sync_get_hight_performan_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to hal_internal_svs.o(i.hal_intl_svs_init_tx) for hal_intl_svs_init_tx + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) for hal_tx_frame_rate_adjust + hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config) refers to drv_lcdc.o(i.drv_lcdc_endianness_config) for drv_lcdc_endianness_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config) refers to drv_lcdc.o(i.drv_lcdc_crop_hact) for drv_lcdc_crop_hact + hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) for hal_lcdc_postproc_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config) for hal_lcdc_displayproc_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) refers to hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info) for hal_intl_fb_get_tx_fb_info + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) for hal_lcdc_timinggen_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) refers to drv_lcdc.o(i.drv_lcdc_config_int) for drv_lcdc_config_int + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) refers to drv_lcdc.o(i.drv_lcdc_set_int) for drv_lcdc_set_int + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to fscalb.o(.text) for __ARM_scalbnf + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to ffltui.o(.text) for __aeabi_ui2f + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to fdiv.o(.text) for __aeabi_fdiv + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to f2d.o(.text) for __aeabi_f2d + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to ceil.o(i.ceil) for ceil + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to drv_crgu.o(i.drv_crgu_set_lcdc_clk) for drv_crgu_set_lcdc_clk + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info) for hal_intl_fb_get_tx_fb_info + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_function_enable) for drv_lcdc_function_enable + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) for hal_lcdc_upscaler_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_function_disable) for drv_lcdc_function_disable + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_fldc_config) for drv_lcdc_fldc_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_bcsa_config) for drv_lcdc_bcsa_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_fc_config) for drv_lcdc_fc_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_edge_dect_config) for drv_lcdc_edge_dect_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_edge_enh_config) for drv_lcdc_edge_enh_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_vintp_mode_config) for drv_lcdc_vintp_mode_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_dith_config) for drv_lcdc_dith_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for .ARM.__at_0x1102C + hal_dsi_tx_ctrl.o(i.hal_lcdc_start) refers to hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) for hal_intl_fb_get_memc_flow_mode + hal_dsi_tx_ctrl.o(i.hal_lcdc_start) refers to drv_lcdc.o(i.drv_lcdc_vid_hw_start) for drv_lcdc_vid_hw_start + hal_dsi_tx_ctrl.o(i.hal_lcdc_start) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_dsi_tx_ctrl.o(i.hal_lcdc_start) refers to drv_lcdc.o(i.drv_lcdc_cmd_start) for drv_lcdc_cmd_start + hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) for hal_internal_vsync_get_sync_line + hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) refers to drv_lcdc.o(i.drv_lcdc_ctrl_flow) for drv_lcdc_ctrl_flow + hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) refers to drv_lcdc.o(i.drv_lcdc_config_src_parameter) for drv_lcdc_config_src_parameter + hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) refers to hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) for hal_intl_fb_get_memc_flow_mode + hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) refers to drv_lcdc.o(i.drv_lcdc_set_prefetch) for drv_lcdc_set_prefetch + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to dfltui.o(.text) for __aeabi_ui2d + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to dadd.o(.text) for __aeabi_dadd + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to drv_lcdc.o(i.drv_lcdc_function_enable) for drv_lcdc_function_enable + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_req_update) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for sg_pq_para + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) refers to drv_lcdc.o(i.drv_lcdc_bcsa_config) for drv_lcdc_bcsa_config + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) refers to drv_lcdc.o(i.drv_lcdc_fc_config) for drv_lcdc_fc_config + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) refers to drv_lcdc.o(i.drv_lcdc_edge_dect_config) for drv_lcdc_edge_dect_config + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) refers to drv_lcdc.o(i.drv_lcdc_edge_enh_config) for drv_lcdc_edge_enh_config + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for sg_pq_para + hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) refers to cfcmple.o(.text) for __aeabi_cfcmple + hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) for hal_dsi_tx_ctrl_init + hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) for hal_internal_vsync_set_tx_state + hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_vsync_func_update) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_vsync_func_update) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_gpio.o(i.hal_gpio_config_pad) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_gpio.o(i.hal_gpio_config_pad) refers to hal_gpio.o(i.hal_gpio_init_input) for hal_gpio_init_input + hal_gpio.o(i.hal_gpio_config_pad) refers to hal_gpio.o(i.hal_gpio_init_output) for hal_gpio_init_output + hal_gpio.o(i.hal_gpio_ctrl_eint) refers to drv_gpio.o(i.drv_gpio_set_int) for drv_gpio_set_int + hal_gpio.o(i.hal_gpio_get_input_data) refers to drv_gpio.o(i.drv_gpio_get_input_data) for drv_gpio_get_input_data + hal_gpio.o(i.hal_gpio_get_pull_state) refers to drv_gpio.o(i.drv_gpio_get_attribute) for drv_gpio_get_attribute + hal_gpio.o(i.hal_gpio_get_pull_state) refers to hal_gpio.o(.constdata) for .constdata + hal_gpio.o(i.hal_gpio_init_eint) refers to drv_gpio.o(i.drv_gpio_set_ioe) for drv_gpio_set_ioe + hal_gpio.o(i.hal_gpio_init_eint) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_gpio.o(i.hal_gpio_init_eint) refers to drv_sys_cfg.o(i.drv_sys_cfg_sel_gpio_group) for drv_sys_cfg_sel_gpio_group + hal_gpio.o(i.hal_gpio_init_eint) refers to drv_sys_cfg.o(i.drv_sys_cfg_sel_int_trig) for drv_sys_cfg_sel_int_trig + hal_gpio.o(i.hal_gpio_init_eint) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + hal_gpio.o(i.hal_gpio_init_input) refers to drv_gpio.o(i.drv_gpio_set_ioe) for drv_gpio_set_ioe + hal_gpio.o(i.hal_gpio_init_input) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_gpio.o(i.hal_gpio_init_output) refers to hal_gpio.o(i.drv_gpio_set_output_data) for drv_gpio_set_output_data + hal_gpio.o(i.hal_gpio_init_output) refers to drv_gpio.o(i.drv_gpio_set_ioe) for drv_gpio_set_ioe + hal_gpio.o(i.hal_gpio_init_output) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_gpio.o(i.hal_gpio_reg_eint_cb) refers to drv_gpio.o(i.drv_gpio_register_callback) for drv_gpio_register_callback + hal_gpio.o(i.hal_gpio_set_ap_reset_int) refers to drv_gpio.o(i.drv_gpio_register_ap_reset_callback) for drv_gpio_register_ap_reset_callback + hal_gpio.o(i.hal_gpio_set_ap_reset_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_trig) for drv_sys_cfg_sel_ap_rst_trig + hal_gpio.o(i.hal_gpio_set_ap_reset_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + hal_gpio.o(i.hal_gpio_set_ap_reset_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + hal_gpio.o(i.hal_gpio_set_driving_strength) refers to drv_gpio.o(i.drv_gpio_get_attribute) for drv_gpio_get_attribute + hal_gpio.o(i.hal_gpio_set_driving_strength) refers to drv_gpio.o(i.drv_gpio_set_attribute) for drv_gpio_set_attribute + hal_gpio.o(i.hal_gpio_set_driving_strength) refers to hal_gpio.o(.constdata) for .constdata + hal_gpio.o(i.hal_gpio_set_high_impedance) refers to drv_gpio.o(i.drv_gpio_set_ioe) for drv_gpio_set_ioe + hal_gpio.o(i.hal_gpio_set_high_impedance) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_gpio.o(i.hal_gpio_set_high_impedance) refers to hal_gpio.o(i.hal_gpio_set_pull_state) for hal_gpio_set_pull_state + hal_gpio.o(i.hal_gpio_set_mode) refers to drv_gpio.o(i.drv_gpio_set_mode) for drv_gpio_set_mode + hal_gpio.o(i.hal_gpio_set_output_data) refers to hal_gpio.o(i.drv_gpio_set_output_data) for drv_gpio_set_output_data + hal_gpio.o(i.hal_gpio_set_pull_state) refers to drv_gpio.o(i.drv_gpio_get_attribute) for drv_gpio_get_attribute + hal_gpio.o(i.hal_gpio_set_pull_state) refers to drv_gpio.o(i.drv_gpio_set_attribute) for drv_gpio_set_attribute + hal_gpio.o(i.hal_gpio_set_pull_state) refers to hal_gpio.o(.constdata) for .constdata + hal_gpio.o(i.hal_gpio_set_schmitt_trigger) refers to drv_gpio.o(i.drv_gpio_get_attribute) for drv_gpio_get_attribute + hal_gpio.o(i.hal_gpio_set_schmitt_trigger) refers to drv_gpio.o(i.drv_gpio_set_attribute) for drv_gpio_set_attribute + hal_gpio.o(i.hal_gpio_set_schmitt_trigger) refers to hal_gpio.o(.constdata) for .constdata + hal_gpio.o(i.hal_gpio_set_slew_rate) refers to drv_gpio.o(i.drv_gpio_get_attribute) for drv_gpio_get_attribute + hal_gpio.o(i.hal_gpio_set_slew_rate) refers to drv_gpio.o(i.drv_gpio_set_attribute) for drv_gpio_set_attribute + hal_gpio.o(i.hal_gpio_set_slew_rate) refers to hal_gpio.o(.constdata) for .constdata + hal_swire.o(i.hal_swire_deinit) refers to drv_swire.o(i.drv_swire_set_int) for drv_swire_set_int + hal_swire.o(i.hal_swire_deinit) refers to drv_swire.o(i.drv_swire_enable) for drv_swire_enable + hal_swire.o(i.hal_swire_deinit) refers to drv_swire.o(i.drv_swire_register_callback) for drv_swire_register_callback + hal_swire.o(i.hal_swire_deinit) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + hal_swire.o(i.hal_swire_deinit) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_swire.o(i.hal_swire_deinit) refers to hal_timer.o(i.hal_timer_deinit) for hal_timer_deinit + hal_swire.o(i.hal_swire_deinit) refers to hal_swire.o(.data) for .data + hal_swire.o(i.hal_swire_enable) refers to drv_swire.o(i.drv_swire_set_power_down) for drv_swire_set_power_down + hal_swire.o(i.hal_swire_enable) refers to drv_swire.o(i.drv_swire_get_pulse_count) for drv_swire_get_pulse_count + hal_swire.o(i.hal_swire_enable) refers to drv_swire.o(i.drv_swire_set_trig_mode) for drv_swire_set_trig_mode + hal_swire.o(i.hal_swire_enable) refers to drv_timer.o(i.drv_timer_enable) for drv_timer_enable + hal_swire.o(i.hal_swire_enable) refers to drv_swire.o(i.drv_swire_set_int) for drv_swire_set_int + hal_swire.o(i.hal_swire_enable) refers to hal_swire.o(.data) for .data + hal_swire.o(i.hal_swire_init) refers to drv_crgu.o(i.drv_crgu_set_clock_div) for drv_crgu_set_clock_div + hal_swire.o(i.hal_swire_init) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_swire.o(i.hal_swire_init) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_swire.o(i.hal_swire_init) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_swire.o(i.hal_swire_init) refers to drv_swire.o(i.drv_swire_set_bit_time) for drv_swire_set_bit_time + hal_swire.o(i.hal_swire_init) refers to drv_swire.o(i.drv_swire_set_power_down) for drv_swire_set_power_down + hal_swire.o(i.hal_swire_init) refers to drv_swire.o(i.drv_swire_enable) for drv_swire_enable + hal_swire.o(i.hal_swire_init) refers to drv_common.o(.data) for g_system_clock + hal_swire.o(i.hal_swire_register_callback) refers to drv_swire.o(i.drv_swire_register_callback) for drv_swire_register_callback + hal_swire.o(i.hal_swire_register_callback) refers to drv_swire.o(i.drv_swire_set_int) for drv_swire_set_int + hal_swire.o(i.hal_swire_set_pulse) refers to drv_swire.o(i.drv_swire_set_trig_mode) for drv_swire_set_trig_mode + hal_swire.o(i.hal_swire_set_pulse) refers to drv_swire.o(i.drv_swire_set_pulse_count) for drv_swire_set_pulse_count + hal_swire.o(i.hal_swire_set_pulse) refers to hal_swire.o(.data) for .data + hal_swire.o(i.hal_swire_set_timer) refers to drv_sys_cfg.o(i.drv_sys_cfg_sel_swire_timer) for drv_sys_cfg_sel_swire_timer + hal_swire.o(i.hal_swire_set_timer) refers to hal_timer.o(i.hal_timer_init) for hal_timer_init + hal_swire.o(i.hal_swire_set_timer) refers to hal_timer.o(i.hal_timer_set_repeat) for hal_timer_set_repeat + hal_swire.o(i.hal_swire_set_timer) refers to drv_timer.o(i.drv_timer_set_compare_val) for drv_timer_set_compare_val + hal_swire.o(i.hal_swire_set_timer) refers to drv_swire.o(i.drv_swire_set_trig_mode) for drv_swire_set_trig_mode + hal_swire.o(i.hal_swire_set_timer) refers to hal_swire.o(.data) for .data + hal_swire.o(i.hal_swire_set_waveform) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_swire.o(i.hal_swire_set_waveform) refers to drv_swire.o(i.drv_swire_set_bit_time) for drv_swire_set_bit_time + hal_swire.o(i.hal_swire_set_waveform) refers to drv_common.o(.data) for g_system_clock + hal_system.o(i.hal_system_disable_systick) refers to drv_common.o(i.drv_common_disable_systick) for drv_common_disable_systick + hal_system.o(i.hal_system_enable_systick) refers to drv_common.o(i.drv_common_enable_systick) for drv_common_enable_systick + hal_system.o(i.hal_system_get_tick) refers to drv_common.o(i.drv_common_get_tick) for drv_common_get_tick + hal_system.o(i.hal_system_idle_mode) refers to drv_common.o(i.drv_common_idle_mode) for drv_common_idle_mode + hal_system.o(i.hal_system_init) refers to drv_pwr.o(i.drv_pwr_set_pll_clk) for drv_pwr_set_pll_clk + hal_system.o(i.hal_system_init) refers to hal_system.o(i.hal_system_updata_sysclk) for hal_system_updata_sysclk + hal_system.o(i.hal_system_init) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_system.o(i.hal_system_init) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_all_int) for drv_sys_cfg_clear_all_int + hal_system.o(i.hal_system_init) refers to drv_common.o(i.drv_common_system_init) for drv_common_system_init + hal_system.o(i.hal_system_init) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_system.o(i.hal_system_register_systick_cb) refers to drv_common.o(i.drv_common_systick_register_cb) for drv_common_systick_register_cb + hal_system.o(i.hal_system_reset_chip) refers to drv_crgu.o(i.drv_crgu_reset_chip) for drv_crgu_reset_chip + hal_system.o(i.hal_system_updata_sysclk) refers to drv_crgu.o(i.drv_crgu_set_ahb_clk) for drv_crgu_set_ahb_clk + hal_system.o(i.hal_system_updata_sysclk) refers to drv_common.o(.data) for g_system_clock + hal_system.o(i.hal_system_updata_sysclk) refers to drv_common.o(.data) for g_system_delay_step + hal_timer.o(i.hal_timer_deinit) refers to drv_timer.o(i.drv_timer_set_int) for drv_timer_set_int + hal_timer.o(i.hal_timer_deinit) refers to drv_timer.o(i.drv_timer_set_repeat) for drv_timer_set_repeat + hal_timer.o(i.hal_timer_deinit) refers to drv_timer.o(i.drv_timer_enable) for drv_timer_enable + hal_timer.o(i.hal_timer_deinit) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + hal_timer.o(i.hal_timer_deinit) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_timer.o(i.hal_timer_get_status) refers to drv_timer.o(i.drv_timer_get_status) for drv_timer_get_status + hal_timer.o(i.hal_timer_init) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_timer.o(i.hal_timer_init) refers to drv_timer.o(i.drv_timer_set_prescaler) for drv_timer_set_prescaler + hal_timer.o(i.hal_timer_set_repeat) refers to drv_timer.o(i.drv_timer_set_repeat) for drv_timer_set_repeat + hal_timer.o(i.hal_timer_start) refers to drv_timer.o(i.drv_timer_register_callback) for drv_timer_register_callback + hal_timer.o(i.hal_timer_start) refers to drv_timer.o(i.drv_timer_set_compare_val) for drv_timer_set_compare_val + hal_timer.o(i.hal_timer_start) refers to drv_timer.o(i.drv_timer_set_int) for drv_timer_set_int + hal_timer.o(i.hal_timer_start) refers to drv_timer.o(i.drv_timer_enable) for drv_timer_enable + hal_timer.o(i.hal_timer_start_ex) refers to drv_timer.o(i.drv_timer_register_callback) for drv_timer_register_callback + hal_timer.o(i.hal_timer_start_ex) refers to drv_timer.o(i.drv_timer_set_compare_val) for drv_timer_set_compare_val + hal_timer.o(i.hal_timer_start_ex) refers to drv_timer.o(i.drv_timer_set_int) for drv_timer_set_int + hal_timer.o(i.hal_timer_start_ex) refers to drv_timer.o(i.drv_timer_enable) for drv_timer_enable + hal_timer.o(i.hal_timer_stop) refers to drv_timer.o(i.drv_timer_enable) for drv_timer_enable + hal_timer.o(i.hal_timer_stop) refers to drv_timer.o(i.drv_timer_set_int) for drv_timer_set_int + hal_timer.o(i.hal_timer_stop) refers to drv_timer.o(i.drv_timer_register_callback) for drv_timer_register_callback + hal_timer.o(i.hal_timer_stop) refers to drv_timer.o(i.drv_timer_set_compare_val) for drv_timer_set_compare_val + hal_pwr.o(i.hal_pwr_elvcc_close) refers to drv_pwr.o(i.drv_pwr_pwmled_electric_current) for drv_pwr_pwmled_electric_current + hal_pwr.o(i.hal_pwr_elvcc_ldo_en) refers to drv_pwr.o(i.drv_pwr_pwmled_electric_current) for drv_pwr_pwmled_electric_current + hal_pwr.o(i.hal_pwr_elvcc_ldo_en) refers to drv_pwr.o(i.drv_pwr_hv_ldo_mode_sel) for drv_pwr_hv_ldo_mode_sel + hal_pwr.o(i.hal_pwr_elvcc_ldo_en) refers to drv_pwr.o(i.drv_pwr_hv_ldo_mode_clock_sel) for drv_pwr_hv_ldo_mode_clock_sel + hal_pwr.o(i.hal_pwr_elvcc_ldo_en) refers to drv_pwr.o(i.drv_pwr_pwmled_driver_current_Big_step) for drv_pwr_pwmled_driver_current_Big_step + hal_pwr.o(i.hal_pwr_elvcc_vol_set) refers to drv_pwr.o(i.drv_pwr_hv_ldo_voltage_set) for drv_pwr_hv_ldo_voltage_set + hal_pwr.o(i.hal_pwr_enter_deep_sleep_mode) refers to drv_pwr.o(i.drv_pwr_set_wakeup_type) for drv_pwr_set_wakeup_type + hal_pwr.o(i.hal_pwr_enter_deep_sleep_mode) refers to drv_pwr.o(i.drv_pwr_enter_deep_sleep_mode) for drv_pwr_enter_deep_sleep_mode + hal_pwr.o(i.hal_pwr_enter_normal_sleep_mode) refers to drv_pwr.o(i.drv_pwr_enter_sleep_mode_ex) for drv_pwr_enter_sleep_mode_ex + hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode) refers to drv_pwr.o(i.drv_pwr_enter_stop_sleep_mode) for drv_pwr_enter_stop_sleep_mode + hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode) refers to hal_pwr.o(.data) for .data + hal_pwr.o(i.hal_pwr_exit_sleep_mode) refers to drv_pwr.o(i.drv_pwr_exit_sleep_mode) for drv_pwr_exit_sleep_mode + hal_pwr.o(i.hal_pwr_get_reset_flag) refers to drv_crgu.o(i.drv_crgu_get_all_reset_flag) for drv_crgu_get_all_reset_flag + hal_pwr.o(i.hal_pwr_get_reset_flag) refers to drv_pwr.o(i.drv_pwr_get_wakeflag) for drv_pwr_get_wakeflag + hal_pwr.o(i.hal_pwr_get_reset_flag) refers to drv_crgu.o(i.drv_crgu_clear_all_reset_flags) for drv_crgu_clear_all_reset_flags + hal_pwr.o(i.hal_pwr_get_vcc_power_ready) refers to drv_pwr.o(i.drv_pwr_get_power_ready_st) for drv_pwr_get_power_ready_st + hal_pwr.o(i.hal_pwr_ldo13s_en) refers to drv_pwr.o(i.drv_pwr_ldo13s_en) for drv_pwr_ldo13s_en + hal_pwr.o(i.hal_pwr_ldo13s_set) refers to drv_pwr.o(i.drv_pwr_ldo13s_set) for drv_pwr_ldo13s_set + hal_pwr.o(i.hal_pwr_ldo18s_en) refers to drv_pwr.o(i.drv_pwr_ldo18s_en) for drv_pwr_ldo18s_en + hal_pwr.o(i.hal_pwr_ldo18s_set) refers to drv_pwr.o(i.drv_pwr_ldo18s_set) for drv_pwr_ldo18s_set + hal_pwr.o(i.hal_pwr_set_main_power) refers to drv_pwr.o(i.drv_pwr_set_digit_power_sel) for drv_pwr_set_digit_power_sel + hal_pwr.o(i.hal_pwr_set_pvd) refers to drv_pwr.o(i.drv_pwr_set_pvd) for drv_pwr_set_pvd + hal_pwr.o(i.hal_pwr_set_sleep_mode_power) refers to drv_pwr.o(i.drv_pwr_set_breath_screen_power_sel) for drv_pwr_set_breath_screen_power_sel + hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) refers to hal_gpio.o(i.hal_gpio_ctrl_eint) for hal_gpio_ctrl_eint + hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) refers to hal_gpio.o(i.hal_gpio_init_eint) for hal_gpio_init_eint + hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) refers to hal_gpio.o(i.hal_gpio_reg_eint_cb) for hal_gpio_reg_eint_cb + hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) refers to hal_gpio.o(i.hal_gpio_set_ap_reset_int) for hal_gpio_set_ap_reset_int + hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) refers to hal_pwr.o(.data) for .data + hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) refers to hal_pwr.o(i.stop_sleep_cb) for stop_sleep_cb + hal_pwr.o(i.hal_pwr_set_vcc_enable) refers to drv_pwr.o(i.drv_pwr_charge_pump_en) for drv_pwr_charge_pump_en + hal_pwr.o(i.stop_sleep_cb) refers to hal_pwr.o(.data) for .data + tau_delay.o(i.delayMs) refers to tau_delay.o(i.delayUs) for delayUs + tau_delay.o(i.delayUs) refers to drv_common.o(.data) for g_system_delay_step + tau_log.o(i.fgetc) refers to hal_uart.o(i.hal_uart_recv_blocking) for hal_uart_recv_blocking + tau_log.o(i.fgetc) refers to hal_system.o(i.hal_system_get_debug_state) for hal_system_get_debug_state + tau_log.o(i.fgetc) refers to hal_system.o(i.hal_system_clear_debug_state) for hal_system_clear_debug_state + tau_log.o(i.fgetc) refers to tau_log.o(.data) for g_log_port + tau_log.o(i.fputc) refers to tau_log.o(i.tau_log_push_log) for tau_log_push_log + tau_log.o(i.fputc) refers to hal_uart.o(i.hal_uart_send_blocking) for hal_uart_send_blocking + tau_log.o(i.fputc) refers to tau_log.o(.data) for g_log_port + tau_log.o(i.tau_log_init) refers to hal_uart.o(i.hal_uart_init) for hal_uart_init + tau_log.o(i.tau_log_init) refers to tau_log.o(.data) for g_log_port + tau_log.o(i.tau_log_printf) refers to memseta.o(.text) for __aeabi_memclr4 + tau_log.o(i.tau_log_printf) refers to strlen.o(.text) for strlen + tau_log.o(i.tau_log_printf) refers to printfa.o(i.__0vsprintf) for vsprintf + tau_log.o(i.tau_log_printf) refers to tau_log.o(i.tau_log_push_log) for tau_log_push_log + tau_log.o(i.tau_log_printf) refers to printfa.o(i.__0printf) for __2printf + tau_log.o(i.tau_log_printf) refers to tau_log.o(.data) for g_log_port + tau_log.o(i.tau_log_printf) refers to tau_log.o(.bss) for g_log_buf + tau_log.o(i.tau_log_push_log) refers to memcpya.o(.text) for __aeabi_memcpy + tau_log.o(i.tau_log_push_log) refers to tau_delay.o(i.delayUs) for delayUs + tau_log.o(.ARM.__at_0x1101C) refers to tau_log.o(.bss) for g_log_buf + hal_uart.o(i.hal_uart0_rx_dma_cb) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart0_tx_dma_cb) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart1_rx_dma_cb) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart1_tx_dma_cb) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart_deinit) refers to drv_uart.o(i.drv_uart_deinit) for drv_uart_deinit + hal_uart.o(i.hal_uart_deinit) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + hal_uart.o(i.hal_uart_deinit) refers to hal_uart.o(.constdata) for .constdata + hal_uart.o(i.hal_uart_dma_path_close) refers to drv_dma.o(i.drv_dma_disable) for drv_dma_disable + hal_uart.o(i.hal_uart_dma_path_close) refers to drv_dma.o(i.drv_dma_deinit) for drv_dma_deinit + hal_uart.o(i.hal_uart_dma_path_close) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_apply_handle) for drv_dma_apply_handle + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_init) for drv_dma_init + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_set_burst) for drv_dma_set_burst + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_register_callback) for drv_dma_register_callback + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_enable_int) for drv_dma_enable_int + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_disable) for drv_dma_disable + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_set_mem_trans_info) for drv_dma_set_mem_trans_info + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_enable) for drv_dma_enable + hal_uart.o(i.hal_uart_dma_recv) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_uart.o(i.hal_uart_dma_recv) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart_dma_recv) refers to hal_uart.o(i.hal_uart0_rx_dma_cb) for hal_uart0_rx_dma_cb + hal_uart.o(i.hal_uart_dma_recv) refers to hal_uart.o(i.hal_uart1_rx_dma_cb) for hal_uart1_rx_dma_cb + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_apply_handle) for drv_dma_apply_handle + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_init) for drv_dma_init + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_set_burst) for drv_dma_set_burst + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_register_callback) for drv_dma_register_callback + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_enable_int) for drv_dma_enable_int + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_disable) for drv_dma_disable + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_set_mem_trans_info) for drv_dma_set_mem_trans_info + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_enable) for drv_dma_enable + hal_uart.o(i.hal_uart_dma_send) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_uart.o(i.hal_uart_dma_send) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart_dma_send) refers to hal_uart.o(i.hal_uart0_tx_dma_cb) for hal_uart0_tx_dma_cb + hal_uart.o(i.hal_uart_dma_send) refers to hal_uart.o(i.hal_uart1_tx_dma_cb) for hal_uart1_tx_dma_cb + hal_uart.o(i.hal_uart_init) refers to memseta.o(.text) for __aeabi_memclr4 + hal_uart.o(i.hal_uart_init) refers to drv_uart.o(i.drv_uart_init) for drv_uart_init + hal_uart.o(i.hal_uart_init) refers to drv_uart.o(i.drv_uart_trans_create_handle) for drv_uart_trans_create_handle + hal_uart.o(i.hal_uart_init) refers to hal_uart.o(.constdata) for .constdata + hal_uart.o(i.hal_uart_init) refers to drv_common.o(.data) for g_system_clock + hal_uart.o(i.hal_uart_init) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart_recv_blocking) refers to drv_uart.o(i.drv_uart_recv_blocking) for drv_uart_recv_blocking + hal_uart.o(i.hal_uart_recv_blocking) refers to hal_uart.o(.constdata) for .constdata + hal_uart.o(i.hal_uart_recv_none_blocking) refers to drv_uart.o(i.drv_uart_recv_none_blocking) for drv_uart_recv_none_blocking + hal_uart.o(i.hal_uart_recv_none_blocking) refers to hal_uart.o(.constdata) for .constdata + hal_uart.o(i.hal_uart_send_blocking) refers to drv_uart.o(i.drv_uart_send_blocking) for drv_uart_send_blocking + hal_uart.o(i.hal_uart_send_blocking) refers to hal_uart.o(.constdata) for .constdata + hal_uart.o(i.hal_uart_send_none_blocking) refers to drv_uart.o(i.drv_uart_send_none_blocking) for drv_uart_send_none_blocking + hal_uart.o(i.hal_uart_send_none_blocking) refers to hal_uart.o(.constdata) for .constdata + hal_internal_vsync.o(i.LCDC_IRQn_Handler) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_vsync.o(i.LCDC_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + hal_internal_vsync.o(i.LCDC_IRQn_Handler) refers to hal_internal_vsync.o(.data) for .data + hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) for hal_intl_fb_cal_fb_info + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to drv_vidc.o(i.drv_vidc_enable) for drv_vidc_enable + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to drv_vidc.o(i.drv_vidc_reset) for drv_vidc_reset + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) for hal_dsi_rx_ctrl_init + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to drv_memc.o(i.drv_memc_set_tear_mode) for drv_memc_set_tear_mode + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) for hal_internal_vsync_get_sync_line + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) for hal_dsi_rx_ctrl_start + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) for hal_dsi_tx_ctrl_gen_a_tear_signal + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to tau_delay.o(i.delayUs) for delayUs + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) for hal_vsync_reset_lcdc_scaler + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_internal_fb.o(.bss) for g_rx_fb_info + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_sync_register_lcdc_cb) refers to hal_internal_vsync.o(.data) for .data + hal_internal_vsync.o(i.hal_internal_sync_register_rx_callback) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_sync_set_fb_setting_manual) refers to hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual) for hal_intl_fb_set_fb_info_manual + hal_internal_vsync.o(i.hal_internal_sync_set_fb_setting_manual) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_deinit) refers to memseta.o(.text) for __aeabi_memclr4 + hal_internal_vsync.o(i.hal_internal_vsync_deinit) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_deinit) refers to hal_internal_fb.o(.bss) for g_rx_fb_info + hal_internal_vsync.o(i.hal_internal_vsync_get_rx_state) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(i.check_mipi_rx_tx_video_info) for check_mipi_rx_tx_video_info + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) for hal_intl_fb_cal_fb_info + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_svs.o(i.hal_intl_svs_init_rx) for hal_intl_svs_init_rx + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_dcs.o(i.hal_intl_dcs_init_sw_fltr) for hal_intl_dcs_init_sw_fltr + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to drv_rxbr.o(i.drv_rxbr_register_irq1_callback) for drv_rxbr_register_irq1_callback + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to drv_vidc.o(i.drv_vidc_register_callback) for drv_vidc_register_callback + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to dcs_packet_fifo.o(i.dcs_packet_fifo_init) for dcs_packet_fifo_init + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(.data) for .data + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(i.soft_gen_te) for soft_gen_te + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(i.soft_gen_te_double_buffer) for soft_gen_te_double_buffer + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(i.rxbr_irq1_callback) for rxbr_irq1_callback + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(i.vidc_callback) for vidc_callback + hal_internal_vsync.o(i.hal_internal_vsync_init_tx) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_internal_vsync.o(i.hal_internal_vsync_init_tx) refers to hal_internal_vsync.o(i.check_mipi_rx_tx_video_info) for check_mipi_rx_tx_video_info + hal_internal_vsync.o(i.hal_internal_vsync_init_tx) refers to memseta.o(.text) for __aeabi_memclr4 + hal_internal_vsync.o(i.hal_internal_vsync_init_tx) refers to hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) for hal_intl_fb_cal_fb_info + hal_internal_vsync.o(i.hal_internal_vsync_init_tx) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) refers to hal_internal_vsync.o(i.hal_internal_vsync_deinit) for hal_internal_vsync_deinit + hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) refers to hal_internal_svs.o(i.hal_intl_svs_deinit_rx) for hal_intl_svs_deinit_rx + hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) refers to ffltui.o(.text) for __aeabi_ui2f + hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) refers to fdiv.o(.text) for __aeabi_fdiv + hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) refers to hal_internal_svs.o(i.hal_intl_svs_set_sync_coef) for hal_intl_svs_set_sync_coef + hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_lcdc.o(i.drv_lcdc_function_disable) for drv_lcdc_function_disable + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_memc.o(i.drv_memc_set_frame_drop_select) for drv_memc_set_frame_drop_select + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_lcdc.o(i.drv_lcdc_function_enable) for drv_lcdc_function_enable + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_memc.o(i.drv_memc_set_tear_mode) for drv_memc_set_tear_mode + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) for hal_internal_vsync_get_sync_line + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_lcdc.o(i.drv_lcdc_set_tear_line) for drv_lcdc_set_tear_line + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_memc.o(i.drv_memc_rate_transfer_sel) for drv_memc_rate_transfer_sel + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_lcdc.o(i.drv_lcdc_config_acc_command_mode) for drv_lcdc_config_acc_command_mode + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to hal_internal_fb.o(.bss) for g_rx_fb_info + hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) refers to hal_internal_vsync.o(i.hal_internal_vsync_deinit) for hal_internal_vsync_deinit + hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) refers to hal_internal_svs.o(i.hal_intl_svs_deinit_tx) for hal_intl_svs_deinit_tx + hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) refers to drv_lcdc.o(i.drv_lcdc_function_disable) for drv_lcdc_function_disable + hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) refers to hal_internal_fb.o(.bss) for g_rx_fb_info + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to hal_internal_svs.o(i.hal_intl_svs_set_input_frate) for hal_intl_svs_set_input_frate + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to drv_memc.o(i.drv_memc_rate_transfer_sel) for drv_memc_rate_transfer_sel + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to drv_memc.o(i.drv_memc_sel_vsync) for drv_memc_sel_vsync + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) for drv_rxbr_frame_drop_cfg + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to drv_rxbr.o(i.drv_rxbr_hline_rcv0_cfg) for drv_rxbr_hline_rcv0_cfg + hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) refers to dfltui.o(.text) for __aeabi_ui2d + hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) refers to dadd.o(.text) for __aeabi_dadd + hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_vsync.o(i.drv_rxbr_get_int_source) for drv_rxbr_get_int_source + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_vsync.o(i.soft_double_buffer_update) for soft_double_buffer_update + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_svs.o(i.hal_intl_svs_handle) for hal_intl_svs_handle + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_vsync.o(i.vpre_err_reset) for vpre_err_reset + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to drv_vidc.o(i.drv_vidc_enable) for drv_vidc_enable + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs) for drv_dsi_tx_phy_clock_lane_req_hs + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to drv_lcdc.o(i.drv_lcdc_cmd_start) for drv_lcdc_cmd_start + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_svs.o(i.hal_intl_svs_set_rx_vtt) for hal_intl_svs_set_rx_vtt + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) for drv_rxbr_clear_pkt_buffer + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_fb.o(.bss) for g_rx_fb_info + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_vsync.o(.conststring) for .conststring + hal_internal_vsync.o(i.soft_double_buffer_update) refers to hal_internal_fb.o(.bss) for g_rx_fb_info + hal_internal_vsync.o(i.soft_gen_te) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.soft_gen_te) refers to hal_internal_vsync.o(.data) for .data + hal_internal_vsync.o(i.soft_gen_te_double_buffer) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.soft_gen_te_double_buffer) refers to hal_internal_vsync.o(.data) for .data + hal_internal_vsync.o(i.vidc_callback) refers to drv_vidc.o(i.drv_vidc_get_int_source) for drv_vidc_get_int_source + hal_internal_vsync.o(i.vidc_callback) refers to drv_lcdc.o(i.drv_lcdc_function_disable) for drv_lcdc_function_disable + hal_internal_vsync.o(i.vidc_callback) refers to drv_vidc.o(i.drv_vidc_set_irqen) for drv_vidc_set_irqen + hal_internal_vsync.o(i.vidc_callback) refers to drv_vidc.o(i.drv_vidc_clear_irq) for drv_vidc_clear_irq + hal_internal_vsync.o(i.vidc_callback) refers to drv_vidc.o(i.drv_vidc_get_irq_status) for drv_vidc_get_irq_status + hal_internal_vsync.o(i.vidc_callback) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_vsync.o(i.vidc_callback) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.vidc_callback) refers to hal_internal_vsync.o(.conststring) for .conststring + hal_internal_vsync.o(i.vpre_err_reset) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + hal_internal_vsync.o(i.vpre_err_reset) refers to drv_vidc.o(i.drv_vidc_reset) for drv_vidc_reset + hal_internal_vsync.o(i.vpre_err_reset) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to hal_internal_dcs.o(i.drv_rxbr_get_status0) for drv_rxbr_get_status0 + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) for hal_intl_dcs_rx_receive_packet + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to drv_dsc_dec.o(i.drv_dsc_dec_get_nslc) for drv_dsc_dec_get_nslc + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to drv_crgu.o(i.drv_crgu_set_dsc_clk) for drv_crgu_set_dsc_clk + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to hal_internal_dcs.o(.data) for .data + hal_internal_dcs.o(i.check_pkt_buf_rev) refers to hal_internal_dcs.o(i.drv_rxbr_get_status0) for drv_rxbr_get_status0 + hal_internal_dcs.o(i.check_pkt_buf_rev) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_dcs.o(i.check_pkt_buf_rev) refers to drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) for drv_rxbr_clear_pkt_buffer + hal_internal_dcs.o(i.check_pkt_buf_rev) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_dcs.o(i.hal_intl_dcs_init_sw_fltr) refers to hal_internal_dcs.o(.bss) for .bss + hal_internal_dcs.o(i.hal_intl_dcs_init_sw_fltr) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_dcs.o(i.hal_intl_dcs_register_write_cmd_entry) refers to hal_internal_dcs.o(.data) for .data + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to hal_internal_dcs.o(i.hal_intl_dcs_sw_filter_handle) for hal_intl_dcs_sw_filter_handle + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to dcs_packet_fifo.o(i.dcs_packet_fifo_alloc) for dcs_packet_fifo_alloc + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) for hal_dsi_rx_ctrl_dcs_async_handler + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_ddi_crc_en) for drv_dsi_rx_get_ddi_crc_en + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to hal_internal_dcs.o(i.check_pkt_buf_rev) for check_pkt_buf_rev + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) for drv_dsi_tx_command_put_payload + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to hal_internal_dcs.o(.data) for .data + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to hal_internal_dcs.o(.conststring) for .conststring + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) refers to hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) for hal_intl_dcs_rx_get_dcs_packet_data + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) refers to hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) for hal_intl_dcs_rx_receive_pps + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) refers to drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) for drv_rxbr_clear_pkt_buffer + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to memseta.o(.text) for __aeabi_memclr4 + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) for drv_rxbr_clear_pkt_buffer + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to hal_internal_dcs.o(i.check_pkt_buf_rev) for check_pkt_buf_rev + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en) for drv_dsi_rx_get_compression_en + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to drv_dsc_dec.o(i.drv_dsc_dec_enable) for drv_dsc_dec_enable + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to hal_internal_dcs.o(.conststring) for .conststring + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) refers to memseta.o(.text) for __aeabi_memset + hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) refers to drv_rxbr.o(i.drv_rxbr_set_filter_regs) for drv_rxbr_set_filter_regs + hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) refers to hal_internal_dcs.o(.bss) for .bss + hal_internal_dcs.o(i.hal_intl_dcs_set_dcs_direct_mode) refers to hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) for hal_intl_dcs_set_auto_hw_filter + hal_internal_dcs.o(i.hal_intl_dcs_set_dcs_direct_mode) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_dcs.o(i.hal_intl_dcs_sw_filter_handle) refers to hal_internal_dcs.o(.data) for .data + hal_internal_dcs.o(i.hal_intl_dcs_sw_filter_handle) refers to hal_internal_dcs.o(.bss) for .bss + hal_internal_dcs.o(.data) refers to hal_internal_dcs.o(.bss) for g_imm_buffer + hal_internal_fb.o(i.ha_intl_fb_check_pu_size) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_fb.o(i.ha_intl_fb_check_pu_size) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to memseta.o(.text) for __aeabi_memclr4 + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to hal_internal_fb.o(i.hal_intl_fb_flow_control_adapter) for hal_intl_fb_flow_control_adapter + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to hal_internal_fb.o(i.hal_intl_fb_check_bandwidth) for hal_intl_fb_check_bandwidth + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to hal_internal_fb.o(i.ha_intl_fb_check_pu_size) for ha_intl_fb_check_pu_size + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to hal_internal_fb.o(i.hal_intl_fb_edge_resize) for hal_intl_fb_edge_resize + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_check_bandwidth) refers to hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) for hal_internal_sync_get_hight_performan_mode + hal_internal_fb.o(i.hal_intl_fb_check_bandwidth) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_fb.o(i.hal_intl_fb_check_bandwidth) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_fb.o(i.hal_intl_fb_edge_resize) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_fb.o(i.hal_intl_fb_edge_resize) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_flow_control_adapter) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_get_user_flow) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual) refers to hal_internal_fb.o(.conststring) for .conststring + hal_internal_svs.o(i.hal_intl_svs_deinit_rx) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_internal_svs.o(i.hal_intl_svs_deinit_rx) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_deinit_rx) refers to hal_internal_svs.o(i.svs_wait_start) for svs_wait_start + hal_internal_svs.o(i.hal_intl_svs_deinit_tx) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_handle) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_init_rx) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_internal_svs.o(i.hal_intl_svs_init_rx) refers to memseta.o(.text) for __aeabi_memclr4 + hal_internal_svs.o(i.hal_intl_svs_init_rx) refers to hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) for hal_intl_svs_update_rxbr_clk + hal_internal_svs.o(i.hal_intl_svs_init_rx) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_svs.o(i.hal_intl_svs_init_rx) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_init_rx) refers to hal_internal_svs.o(i.svs_wait_start) for svs_wait_start + hal_internal_svs.o(i.hal_intl_svs_init_tx) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_set_input_frate) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_internal_svs.o(i.hal_intl_svs_set_input_frate) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_svs.o(i.hal_intl_svs_set_input_frate) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_set_input_frate) refers to hal_internal_svs.o(i.svs_wait_start) for svs_wait_start + hal_internal_svs.o(i.hal_intl_svs_set_input_frate) refers to hal_internal_svs.o(i.svs_wait_fr_stab) for svs_wait_fr_stab + hal_internal_svs.o(i.hal_intl_svs_set_rx_vtt) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_set_sync_coef) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) refers to drv_crgu.o(i.drv_crgu_get_rxbr_clk) for drv_crgu_get_rxbr_clk + hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) refers to dfltui.o(.text) for __aeabi_ui2d + hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) refers to dmul.o(.text) for __aeabi_dmul + hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.svs_direct_mode_setting) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_svs.o(i.svs_direct_mode_setting) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_internal_svs.o(i.svs_direct_mode_setting) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_svs.o(i.svs_direct_mode_setting) refers to drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg) for drv_rxbr_hline_rcv1_cfg + hal_internal_svs.o(i.svs_direct_mode_setting) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.svs_get_rel_intv) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_svs.o(i.svs_get_rel_intv) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.svs_sync_handle) refers to hal_internal_svs.o(i.svs_get_rel_intv) for svs_get_rel_intv + hal_internal_svs.o(i.svs_sync_handle) refers to ffltui.o(.text) for __aeabi_ui2f + hal_internal_svs.o(i.svs_sync_handle) refers to fdiv.o(.text) for __aeabi_fdiv + hal_internal_svs.o(i.svs_sync_handle) refers to fmul.o(.text) for __aeabi_fmul + hal_internal_svs.o(i.svs_sync_handle) refers to f2d.o(.text) for __aeabi_f2d + hal_internal_svs.o(i.svs_sync_handle) refers to dadd.o(.text) for __aeabi_dadd + hal_internal_svs.o(i.svs_sync_handle) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_internal_svs.o(i.svs_sync_handle) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.svs_wait_fr_stab) refers to hal_internal_svs.o(i.svs_get_rel_intv) for svs_get_rel_intv + hal_internal_svs.o(i.svs_wait_fr_stab) refers to drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) for drv_rxbr_frame_drop_cfg + hal_internal_svs.o(i.svs_wait_fr_stab) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_svs.o(i.svs_wait_fr_stab) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_svs.o(i.svs_wait_fr_stab) refers to ffltui.o(.text) for __aeabi_ui2f + hal_internal_svs.o(i.svs_wait_fr_stab) refers to fmul.o(.text) for __aeabi_fmul + hal_internal_svs.o(i.svs_wait_fr_stab) refers to ffixui.o(.text) for __aeabi_f2uiz + hal_internal_svs.o(i.svs_wait_fr_stab) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.svs_wait_fr_stab) refers to hal_internal_svs.o(i.svs_sync_handle) for svs_sync_handle + hal_internal_svs.o(i.svs_wait_start) refers to hal_internal_svs.o(i.svs_get_rel_intv) for svs_get_rel_intv + hal_internal_svs.o(i.svs_wait_start) refers to drv_crgu.o(i.drv_crgu_get_rxbr_clk) for drv_crgu_get_rxbr_clk + hal_internal_svs.o(i.svs_wait_start) refers to ffltui.o(.text) for __aeabi_ui2f + hal_internal_svs.o(i.svs_wait_start) refers to fdiv.o(.text) for __aeabi_fdiv + hal_internal_svs.o(i.svs_wait_start) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_internal_svs.o(i.svs_wait_start) refers to fmul.o(.text) for __aeabi_fmul + hal_internal_svs.o(i.svs_wait_start) refers to f2d.o(.text) for __aeabi_f2d + hal_internal_svs.o(i.svs_wait_start) refers to ceil.o(i.ceil) for ceil + hal_internal_svs.o(i.svs_wait_start) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_internal_svs.o(i.svs_wait_start) refers to hal_internal_svs.o(i.svs_direct_mode_setting) for svs_direct_mode_setting + hal_internal_svs.o(i.svs_wait_start) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_svs.o(i.svs_wait_start) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_internal_svs.o(i.svs_wait_start) refers to drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg) for drv_rxbr_hline_rcv1_cfg + hal_internal_svs.o(i.svs_wait_start) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.svs_wait_start) refers to hal_internal_svs.o(i.svs_wait_fr_stab) for svs_wait_fr_stab + drv_common.o(i.HardFault_Handler) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_common.o(i.SysTick_Handler) refers to drv_common.o(.data) for .data + drv_common.o(i.drv_common_enable_systick) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_common.o(i.drv_common_enable_systick) refers to drv_common.o(.data) for .data + drv_common.o(i.drv_common_get_tick) refers to drv_common.o(.data) for .data + drv_common.o(i.drv_common_system_init) refers to drv_se.o(i.drv_se_init) for drv_se_init + drv_common.o(i.drv_common_systick_register_cb) refers to drv_common.o(.data) for .data + drv_crgu.o(i.drv_crgu_get_rxbr_clk) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_crgu.o(i.drv_crgu_get_system_clk) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_dsc_dec.o(i.drv_dsc_dec_enable) refers to drv_se.o(i.drv_se_set_dsc) for drv_se_set_dsc + drv_gpio.o(i.AP_NRESET_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_gpio.o(i.AP_NRESET_IRQn_Handler) refers to drv_gpio.o(.data) for .data + drv_gpio.o(i.EXTI_INT0_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT1_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT2_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT3_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT4_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT5_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT6_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT7_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.drv_gpio_handle_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_gpio.o(i.drv_gpio_handle_int) refers to drv_gpio.o(.bss) for .bss + drv_gpio.o(i.drv_gpio_register_ap_reset_callback) refers to drv_gpio.o(.data) for .data + drv_gpio.o(i.drv_gpio_register_callback) refers to drv_gpio.o(.bss) for .bss + drv_gpio.o(i.drv_gpio_set_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_pwr.o(i.drv_pwr_analog_pwm_en) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_elvcc_pwm_en) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_elvcc_pwm_en) refers to tau_delay.o(i.delayMs) for delayMs + drv_pwr.o(i.drv_pwr_enter_sleep_mode) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_enter_sleep_mode) refers to drv_pwr.o(i.drv_pwr_por_mode_flag) for drv_pwr_por_mode_flag + drv_pwr.o(i.drv_pwr_enter_stop_sleep_mode) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_exit_sleep_mode) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_hv_ldo_mode_clock_sel) refers to drv_pwr.o(i.drv_pwr_hv_ldo_10M_clock) for drv_pwr_hv_ldo_10M_clock + drv_pwr.o(i.drv_pwr_pwm_output_pwm_led) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_set_breath_screen_power_sel) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_set_digit_power_sel) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_set_system_clk) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_set_wakeup_type) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_swire.o(i.SWIRE_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_swire.o(i.SWIRE_IRQn_Handler) refers to drv_swire.o(.data) for .data + drv_swire.o(i.drv_swire_register_callback) refers to drv_swire.o(.data) for .data + drv_swire.o(i.drv_swire_set_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_sys_cfg.o(i.drv_sys_cfg_sel_dma_req) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_timer.o(i.TIMER0_IRQn_Handler) refers to drv_timer.o(i.drv_timer_handle_interrupt) for drv_timer_handle_interrupt + drv_timer.o(i.TIMER1_IRQn_Handler) refers to drv_timer.o(i.drv_timer_handle_interrupt) for drv_timer_handle_interrupt + drv_timer.o(i.TIMER2_IRQn_Handler) refers to drv_timer.o(i.drv_timer_handle_interrupt) for drv_timer_handle_interrupt + drv_timer.o(i.TIMER3_IRQn_Handler) refers to drv_timer.o(i.drv_timer_handle_interrupt) for drv_timer_handle_interrupt + drv_timer.o(i.drv_timer_clear_status_flags) refers to drv_timer.o(i.drv_timer_get_instance) for drv_timer_get_instance + drv_timer.o(i.drv_timer_clear_status_flags) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_timer.o(i.drv_timer_enable) refers to drv_timer.o(i.drv_timer_get_instance) for drv_timer_get_instance + drv_timer.o(i.drv_timer_get_instance) refers to drv_timer.o(.data) for .data + drv_timer.o(i.drv_timer_get_status) refers to drv_timer.o(i.drv_timer_get_instance) for drv_timer_get_instance + drv_timer.o(i.drv_timer_handle_interrupt) refers to drv_timer.o(i.drv_timer_clear_status_flags) for drv_timer_clear_status_flags + drv_timer.o(i.drv_timer_handle_interrupt) refers to drv_timer.o(i.drv_timer_set_int) for drv_timer_set_int + drv_timer.o(i.drv_timer_handle_interrupt) refers to drv_timer.o(i.drv_timer_set_compare_val) for drv_timer_set_compare_val + drv_timer.o(i.drv_timer_handle_interrupt) refers to drv_timer.o(.data) for .data + drv_timer.o(i.drv_timer_register_callback) refers to drv_timer.o(.data) for .data + drv_timer.o(i.drv_timer_set_compare_val) refers to drv_timer.o(i.drv_timer_get_instance) for drv_timer_get_instance + drv_timer.o(i.drv_timer_set_compare_val) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_timer.o(i.drv_timer_set_compare_val) refers to drv_timer.o(.data) for .data + drv_timer.o(i.drv_timer_set_compare_val) refers to drv_common.o(.data) for g_system_clock + drv_timer.o(i.drv_timer_set_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_timer.o(i.drv_timer_set_prescaler) refers to drv_timer.o(i.drv_timer_get_instance) for drv_timer_get_instance + drv_timer.o(i.drv_timer_set_prescaler) refers to drv_timer.o(.data) for .data + drv_timer.o(i.drv_timer_set_repeat) refers to drv_timer.o(.data) for .data + dcs_packet_fifo.o(i.dcs_packet_fifo_alloc) refers to dcs_packet_fifo.o(.bss) for .bss + dcs_packet_fifo.o(i.dcs_packet_fifo_init) refers to dcs_packet_fifo.o(.bss) for .bss + dcs_packet_fifo.o(i.dcs_packet_free_fifo_header) refers to dcs_packet_fifo.o(.bss) for .bss + dcs_packet_fifo.o(i.dcs_packet_get_fifo_header) refers to dcs_packet_fifo.o(.bss) for .bss + dcs_packet_fifo.o(i.dcs_packet_get_fifo_size) refers to dcs_packet_fifo.o(.bss) for .bss + drv_se.o(i.drv_se_init) refers to drv_efuse.o(i.drv_efuse_enter_inactive) for drv_efuse_enter_inactive + drv_se.o(i.drv_se_init) refers to drv_efuse.o(i.drv_efuse_read) for drv_efuse_read + drv_se.o(i.drv_se_init) refers to drv_se.o(.data) for .data + drv_se.o(i.drv_se_set_dsc) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_se.o(i.drv_se_set_dsc) refers to drv_se.o(.data) for .data + drv_se.o(i.drv_se_set_lcdc) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_se.o(i.drv_se_set_lcdc) refers to drv_se.o(.data) for .data + drv_se.o(i.drv_se_set_memc) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_se.o(i.drv_se_set_memc) refers to drv_se.o(.data) for .data + drv_se.o(i.drv_se_set_rxbr) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_se.o(i.drv_se_set_rxbr) refers to drv_se.o(.data) for .data + drv_se.o(i.drv_se_set_vidc) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_se.o(i.drv_se_set_vidc) refers to drv_se.o(.data) for .data + drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler) refers to drv_dsi_rx.o(.data) for .data + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp) for drv_dsi_rx_get_color_bpp + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to ffltui.o(.text) for __aeabi_ui2f + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to fdiv.o(.text) for __aeabi_fdiv + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to fmul.o(.text) for __aeabi_fmul + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_color_pcc) for drv_dsi_rx_get_color_pcc + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to fadd.o(.text) for __aeabi_fadd + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to cfrcmple.o(.text) for __aeabi_cfrcmple + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to f2d.o(.text) for __aeabi_f2d + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to dadd.o(.text) for __aeabi_dadd + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to dfixui.o(.text) for __aeabi_d2uiz + drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_dsi_rx.o(i.drv_dsi_rx_get_phy_stopstate) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_dsi_rx.o(i.drv_dsi_rx_set_drv_log_level) refers to drv_dsi_rx.o(.data) for .data + drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) refers to drv_phy_common.o(i.drv_phy_test_clear) for drv_phy_test_clear + drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) refers to drv_phy_common.o(i.drv_phy_test_lock) for drv_phy_test_lock + drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ulpsactivenot) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) refers to drv_dsi_tx.o(i.drv_tx_phy_test_enter) for drv_tx_phy_test_enter + drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) refers to drv_phy_common.o(i.drv_phy_test_clear) for drv_phy_test_clear + drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) refers to drv_dsi_tx.o(i.drv_tx_phy_test_write_code) for drv_tx_phy_test_write_code + drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) refers to drv_dsi_tx.o(i.drv_tx_phy_test_exit) for drv_tx_phy_test_exit + drv_dsi_tx.o(i.drv_dsi_tx_phy_trigger) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) for drv_dsi_tx_phy_status_stopstate + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_enter) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) for drv_dsi_tx_phy_status_stopstate + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_enter) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_pll_lock) for drv_dsi_tx_phy_status_pll_lock + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_enter) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ulpsactivenot) for drv_dsi_tx_phy_status_ulpsactivenot + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_enter) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_exit) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_exit) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ulpsactivenot) for drv_dsi_tx_phy_status_ulpsactivenot + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_exit) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_pll_lock) for drv_dsi_tx_phy_status_pll_lock + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_exit) refers to drv_dsi_tx.o(i.drv_dsi_tx_version) for drv_dsi_tx_version + drv_dsi_tx.o(i.drv_dsi_tx_set_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_dsi_tx.o(i.drv_dsi_tx_set_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_lcdc.o(i.drv_lcdc_clear_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_lcdc.o(i.drv_lcdc_cmd_start) refers to drv_se.o(i.drv_se_set_lcdc) for drv_se_set_lcdc + drv_lcdc.o(i.drv_lcdc_ctrl_flow) refers to drv_lcdc.o(i.drv_lcdc_function_enable) for drv_lcdc_function_enable + drv_lcdc.o(i.drv_lcdc_part_display_config) refers to drv_lcdc.o(i.drv_lcdc_pixel_value_config) for drv_lcdc_pixel_value_config + drv_lcdc.o(i.drv_lcdc_set_int) refers to drv_lcdc.o(i.drv_lcdc_clear_int) for drv_lcdc_clear_int + drv_lcdc.o(i.drv_lcdc_set_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_lcdc.o(i.drv_lcdc_vid_hw_start) refers to drv_se.o(i.drv_se_set_lcdc) for drv_se_set_lcdc + drv_memc.o(i.MEMC_IRQn_Handler) refers to drv_memc.o(i.drv_memc_get_status) for drv_memc_get_status + drv_memc.o(i.MEMC_IRQn_Handler) refers to drv_memc.o(i.drv_memc_clear_status) for drv_memc_clear_status + drv_memc.o(i.MEMC_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_memc.o(i.drv_memc_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_memc.o(i.drv_memc_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_memc.o(i.drv_memc_rate_transfer_sel) refers to drv_se.o(i.drv_se_set_memc) for drv_se_set_memc + drv_memc.o(i.drv_memc_set_ltpo_mode) refers to drv_se.o(i.drv_se_set_memc) for drv_se_set_memc + drv_rxbr.o(i.VPRE1_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_rxbr.o(i.VPRE1_IRQn_Handler) refers to drv_rxbr.o(.data) for .data + drv_rxbr.o(i.drv_rxbr_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_rxbr.o(i.drv_rxbr_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_rxbr.o(i.drv_rxbr_enable_irq) refers to drv_rxbr.o(i.__NVIC_EnableIRQ) for __NVIC_EnableIRQ + drv_rxbr.o(i.drv_rxbr_enable_irq) refers to drv_rxbr.o(i.__NVIC_DisableIRQ) for __NVIC_DisableIRQ + drv_rxbr.o(i.drv_rxbr_register_irq0_callback) refers to drv_rxbr.o(.data) for .data + drv_rxbr.o(i.drv_rxbr_register_irq1_callback) refers to drv_rxbr.o(.data) for .data + drv_rxbr.o(i.drv_rxbr_set_cmd_filter) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_rxbr.o(i.drv_rxbr_set_cmd_response) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_rxbr.o(i.drv_rxbr_set_color_format) refers to drv_se.o(i.drv_se_set_rxbr) for drv_se_set_rxbr + drv_rxbr.o(i.drv_rxbr_soft_reset) refers to tau_delay.o(i.delayMs) for delayMs + drv_rxbr.o(i.drv_rxbr_sw_reset) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + drv_rxbr.o(i.drv_rxbr_sw_reset) refers to drv_vidc.o(i.drv_vidc_reset) for drv_vidc_reset + drv_vidc.o(i.VIDC_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_vidc.o(i.VIDC_IRQn_Handler) refers to drv_vidc.o(.data) for .data + drv_vidc.o(i.drv_vidc_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_vidc.o(i.drv_vidc_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_vidc.o(i.drv_vidc_register_callback) refers to drv_vidc.o(.data) for .data + drv_vidc.o(i.drv_vidc_set_src_parameter) refers to drv_se.o(i.drv_se_set_vidc) for drv_se_set_vidc + drv_dma.o(i.DMA_IRQn_Handler) refers to drv_dma.o(i.drv_dma_get_int_source) for drv_dma_get_int_source + drv_dma.o(i.DMA_IRQn_Handler) refers to drv_dma.o(i.drv_dma_clear_status) for drv_dma_clear_status + drv_dma.o(i.DMA_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_dma.o(i.DMA_IRQn_Handler) refers to drv_dma.o(.bss) for .bss + drv_dma.o(i.DMA_IRQn_Handler) refers to drv_dma.o(.data) for .data + drv_dma.o(i.drv_dma_apply_handle) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_dma.o(i.drv_dma_apply_handle) refers to drv_dma.o(.data) for .data + drv_dma.o(i.drv_dma_apply_handle) refers to drv_dma.o(.constdata) for .constdata + drv_dma.o(i.drv_dma_deinit) refers to drv_dma.o(i.drv_dma_disable_int) for drv_dma_disable_int + drv_dma.o(i.drv_dma_disable_int) refers to drv_dma.o(i.drv_dma_int_list_delete) for drv_dma_int_list_delete + drv_dma.o(i.drv_dma_disable_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_dma.o(i.drv_dma_enable_int) refers to drv_dma.o(i.drv_dma_int_list_inset) for drv_dma_int_list_inset + drv_dma.o(i.drv_dma_enable_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_dma.o(i.drv_dma_init) refers to drv_per_common.o(i.drv_per_set_clock) for drv_per_set_clock + drv_dma.o(i.drv_dma_init) refers to drv_dma.o(i.drv_dma_update_handle_setting) for drv_dma_update_handle_setting + drv_dma.o(i.drv_dma_int_list_delete) refers to drv_dma.o(.bss) for .bss + drv_dma.o(i.drv_dma_int_list_inset) refers to drv_dma.o(.bss) for .bss + drv_dma.o(i.drv_dma_update_handle_setting) refers to drv_sys_cfg.o(i.drv_sys_cfg_sel_dma_req) for drv_sys_cfg_sel_dma_req + drv_dma.o(i.drv_dma_update_req_by_default) refers to drv_dma.o(i.drv_dma_update_handle_setting) for drv_dma_update_handle_setting + drv_dma.o(i.drv_dma_update_req_by_default) refers to drv_dma.o(.constdata) for .constdata + drv_uart.o(i.UART_IRQn_Handler) refers to drv_uart.o(i.drv_uart_int_trans_handle) for drv_uart_int_trans_handle + drv_uart.o(i.UART_IRQn_Handler) refers to drv_uart.o(i.drv_uart_config_int) for drv_uart_config_int + drv_uart.o(i.UART_IRQn_Handler) refers to drv_uart.o(i.drv_uart_abort_recv) for drv_uart_abort_recv + drv_uart.o(i.UART_IRQn_Handler) refers to drv_uart.o(i.drv_uart_abort_send) for drv_uart_abort_send + drv_uart.o(i.UART_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_uart.o(i.UART_IRQn_Handler) refers to drv_uart.o(.constdata) for .constdata + drv_uart.o(i.UART_IRQn_Handler) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_abort_recv) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_abort_recv) refers to drv_uart.o(i.drv_uart_config_int) for drv_uart_config_int + drv_uart.o(i.drv_uart_abort_recv) refers to drv_uart.o(i.drv_uart_reset_rx_fifo) for drv_uart_reset_rx_fifo + drv_uart.o(i.drv_uart_abort_recv) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_abort_send) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_abort_send) refers to drv_uart.o(i.drv_uart_config_int) for drv_uart_config_int + drv_uart.o(i.drv_uart_abort_send) refers to drv_uart.o(i.drv_uart_reset_tx_fifo) for drv_uart_reset_tx_fifo + drv_uart.o(i.drv_uart_abort_send) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_deinit) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_deinit) refers to drv_uart.o(i.drv_uart_enable_clk) for drv_uart_enable_clk + drv_uart.o(i.drv_uart_deinit) refers to memseta.o(.text) for __aeabi_memclr4 + drv_uart.o(i.drv_uart_deinit) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_enable_clk) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + drv_uart.o(i.drv_uart_enable_int) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_enable_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_uart.o(i.drv_uart_get_def_cfg) refers to memseta.o(.text) for __aeabi_memclr4 + drv_uart.o(i.drv_uart_get_def_cfg) refers to drv_common.o(.data) for g_system_clock + drv_uart.o(i.drv_uart_get_instance) refers to drv_uart.o(.constdata) for .constdata + drv_uart.o(i.drv_uart_init) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_init) refers to drv_uart.o(i.drv_uart_enable_clk) for drv_uart_enable_clk + drv_uart.o(i.drv_uart_init) refers to drv_uart.o(i.drv_uart_set_baud_rate) for drv_uart_set_baud_rate + drv_uart.o(i.drv_uart_init) refers to drv_uart.o(i.drv_uart_enable_int) for drv_uart_enable_int + drv_uart.o(i.drv_uart_int_trans_handle) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_recv_none_blocking) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_recv_none_blocking) refers to drv_uart.o(i.drv_uart_config_int) for drv_uart_config_int + drv_uart.o(i.drv_uart_recv_none_blocking) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_reset_rx_fifo) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_reset_tx_fifo) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_send_none_blocking) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_send_none_blocking) refers to drv_uart.o(i.drv_uart_config_int) for drv_uart_config_int + drv_uart.o(i.drv_uart_send_none_blocking) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_set_baud_rate) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_uart.o(i.drv_uart_trans_create_handle) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_trans_create_handle) refers to memseta.o(.text) for __aeabi_memclr4 + drv_uart.o(i.drv_uart_trans_create_handle) refers to drv_uart.o(.bss) for .bss + drv_efuse.o(i.drv_efuse_enter_inactive) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + drv_efuse.o(i.drv_efuse_enter_inactive) refers to drv_efuse.o(i.drv_efuse_int_enable) for drv_efuse_int_enable + drv_efuse.o(i.drv_efuse_read) refers to drv_pwr.o(i.drv_pwr_efuse_pd) for drv_pwr_efuse_pd + drv_efuse.o(i.drv_efuse_read) refers to drv_efuse.o(i.drv_efuse_read_req) for drv_efuse_read_req + drv_efuse.o(i.drv_efuse_write) refers to drv_pwr.o(i.drv_pwr_efuse_pd) for drv_pwr_efuse_pd + drv_efuse.o(i.drv_efuse_write) refers to drv_efuse.o(i.drv_efuse_write_req) for drv_efuse_write_req + drv_efuse.o(i.drv_efuse_write_read_req_clear) refers to drv_efuse.o(i.drv_efuse_write_req) for drv_efuse_write_req + drv_efuse.o(i.drv_efuse_write_read_req_clear) refers to drv_efuse.o(i.drv_efuse_read_req) for drv_efuse_read_req + drv_per_common.o(i.drv_per_get_system_clk) refers to drv_crgu.o(i.drv_crgu_get_system_clk) for drv_crgu_get_system_clk + drv_per_common.o(i.drv_per_reset_module) refers to drv_crgu.o(i.drv_crgu_reset_modules) for drv_crgu_reset_modules + drv_per_common.o(i.drv_per_set_clock) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + ceil.o(i.__softfp_ceil) refers (Special) to iusefp.o(.text) for __I$use$fp + ceil.o(i.__softfp_ceil) refers to ceil.o(i.ceil) for ceil + ceil.o(i.ceil) refers (Special) to iusefp.o(.text) for __I$use$fp + ceil.o(i.ceil) refers to dadd.o(.text) for __aeabi_dadd + ceil.o(i.ceil) refers to cdrcmple.o(.text) for __aeabi_cdrcmple + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk + idiv.o(.text) refers to uidiv.o(.text) for __aeabi_uidivmod + printfb.o(i.__0fprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0fprintf$bare) refers to tau_log.o(i.fputc) for fputc + printfb.o(i.__0printf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0printf$bare) refers to tau_log.o(i.fputc) for fputc + printfb.o(i.__0printf$bare) refers to stdout.o(.data) for __stdout + printfb.o(i.__0snprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0snprintf$bare) refers to printfb.o(i._snputc) for _snputc + printfb.o(i.__0sprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0sprintf$bare) refers to printfb.o(i._sputc) for _sputc + printfb.o(i.__0vfprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vfprintf$bare) refers to tau_log.o(i.fputc) for fputc + printfb.o(i.__0vprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vprintf$bare) refers to tau_log.o(i.fputc) for fputc + printfb.o(i.__0vprintf$bare) refers to stdout.o(.data) for __stdout + printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._snputc) for _snputc + printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._sputc) for _sputc + printf0.o(i.__0fprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0fprintf$0) refers to tau_log.o(i.fputc) for fputc + printf0.o(i.__0printf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0printf$0) refers to tau_log.o(i.fputc) for fputc + printf0.o(i.__0printf$0) refers to stdout.o(.data) for __stdout + printf0.o(i.__0snprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0snprintf$0) refers to printf0.o(i._snputc) for _snputc + printf0.o(i.__0sprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0sprintf$0) refers to printf0.o(i._sputc) for _sputc + printf0.o(i.__0vfprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vfprintf$0) refers to tau_log.o(i.fputc) for fputc + printf0.o(i.__0vprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vprintf$0) refers to tau_log.o(i.fputc) for fputc + printf0.o(i.__0vprintf$0) refers to stdout.o(.data) for __stdout + printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._snputc) for _snputc + printf0.o(i.__0vsprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vsprintf$0) refers to printf0.o(i._sputc) for _sputc + printf1.o(i.__0fprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0fprintf$1) refers to tau_log.o(i.fputc) for fputc + printf1.o(i.__0printf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0printf$1) refers to tau_log.o(i.fputc) for fputc + printf1.o(i.__0printf$1) refers to stdout.o(.data) for __stdout + printf1.o(i.__0snprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0snprintf$1) refers to printf1.o(i._snputc) for _snputc + printf1.o(i.__0sprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0sprintf$1) refers to printf1.o(i._sputc) for _sputc + printf1.o(i.__0vfprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vfprintf$1) refers to tau_log.o(i.fputc) for fputc + printf1.o(i.__0vprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vprintf$1) refers to tau_log.o(i.fputc) for fputc + printf1.o(i.__0vprintf$1) refers to stdout.o(.data) for __stdout + printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._snputc) for _snputc + printf1.o(i.__0vsprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vsprintf$1) refers to printf1.o(i._sputc) for _sputc + printf1.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf2.o(i.__0fprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0fprintf$2) refers to tau_log.o(i.fputc) for fputc + printf2.o(i.__0printf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0printf$2) refers to tau_log.o(i.fputc) for fputc + printf2.o(i.__0printf$2) refers to stdout.o(.data) for __stdout + printf2.o(i.__0snprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0snprintf$2) refers to printf2.o(i._snputc) for _snputc + printf2.o(i.__0sprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0sprintf$2) refers to printf2.o(i._sputc) for _sputc + printf2.o(i.__0vfprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vfprintf$2) refers to tau_log.o(i.fputc) for fputc + printf2.o(i.__0vprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vprintf$2) refers to tau_log.o(i.fputc) for fputc + printf2.o(i.__0vprintf$2) refers to stdout.o(.data) for __stdout + printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._snputc) for _snputc + printf2.o(i.__0vsprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vsprintf$2) refers to printf2.o(i._sputc) for _sputc + printf3.o(i.__0fprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0fprintf$3) refers to tau_log.o(i.fputc) for fputc + printf3.o(i.__0printf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0printf$3) refers to tau_log.o(i.fputc) for fputc + printf3.o(i.__0printf$3) refers to stdout.o(.data) for __stdout + printf3.o(i.__0snprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0snprintf$3) refers to printf3.o(i._snputc) for _snputc + printf3.o(i.__0sprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0sprintf$3) refers to printf3.o(i._sputc) for _sputc + printf3.o(i.__0vfprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vfprintf$3) refers to tau_log.o(i.fputc) for fputc + printf3.o(i.__0vprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vprintf$3) refers to tau_log.o(i.fputc) for fputc + printf3.o(i.__0vprintf$3) refers to stdout.o(.data) for __stdout + printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._snputc) for _snputc + printf3.o(i.__0vsprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vsprintf$3) refers to printf3.o(i._sputc) for _sputc + printf3.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf4.o(i.__0fprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0fprintf$4) refers to tau_log.o(i.fputc) for fputc + printf4.o(i.__0printf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0printf$4) refers to tau_log.o(i.fputc) for fputc + printf4.o(i.__0printf$4) refers to stdout.o(.data) for __stdout + printf4.o(i.__0snprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0snprintf$4) refers to printf4.o(i._snputc) for _snputc + printf4.o(i.__0sprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0sprintf$4) refers to printf4.o(i._sputc) for _sputc + printf4.o(i.__0vfprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vfprintf$4) refers to tau_log.o(i.fputc) for fputc + printf4.o(i.__0vprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vprintf$4) refers to tau_log.o(i.fputc) for fputc + printf4.o(i.__0vprintf$4) refers to stdout.o(.data) for __stdout + printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._snputc) for _snputc + printf4.o(i.__0vsprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vsprintf$4) refers to printf4.o(i._sputc) for _sputc + printf4.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf5.o(i.__0fprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0fprintf$5) refers to tau_log.o(i.fputc) for fputc + printf5.o(i.__0printf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0printf$5) refers to tau_log.o(i.fputc) for fputc + printf5.o(i.__0printf$5) refers to stdout.o(.data) for __stdout + printf5.o(i.__0snprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0snprintf$5) refers to printf5.o(i._snputc) for _snputc + printf5.o(i.__0sprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0sprintf$5) refers to printf5.o(i._sputc) for _sputc + printf5.o(i.__0vfprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vfprintf$5) refers to tau_log.o(i.fputc) for fputc + printf5.o(i.__0vprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vprintf$5) refers to tau_log.o(i.fputc) for fputc + printf5.o(i.__0vprintf$5) refers to stdout.o(.data) for __stdout + printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._snputc) for _snputc + printf5.o(i.__0vsprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vsprintf$5) refers to printf5.o(i._sputc) for _sputc + printf5.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf6.o(i.__0fprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0fprintf$6) refers to tau_log.o(i.fputc) for fputc + printf6.o(i.__0printf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0printf$6) refers to tau_log.o(i.fputc) for fputc + printf6.o(i.__0printf$6) refers to stdout.o(.data) for __stdout + printf6.o(i.__0snprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0snprintf$6) refers to printf6.o(i._snputc) for _snputc + printf6.o(i.__0sprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0sprintf$6) refers to printf6.o(i._sputc) for _sputc + printf6.o(i.__0vfprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vfprintf$6) refers to tau_log.o(i.fputc) for fputc + printf6.o(i.__0vprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vprintf$6) refers to tau_log.o(i.fputc) for fputc + printf6.o(i.__0vprintf$6) refers to stdout.o(.data) for __stdout + printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._snputc) for _snputc + printf6.o(i.__0vsprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vsprintf$6) refers to printf6.o(i._sputc) for _sputc + printf6.o(i._printf_core) refers to printf6.o(i._printf_pre_padding) for _printf_pre_padding + printf6.o(i._printf_core) refers to printf6.o(i._printf_post_padding) for _printf_post_padding + printf6.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf7.o(i.__0fprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0fprintf$7) refers to tau_log.o(i.fputc) for fputc + printf7.o(i.__0printf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0printf$7) refers to tau_log.o(i.fputc) for fputc + printf7.o(i.__0printf$7) refers to stdout.o(.data) for __stdout + printf7.o(i.__0snprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0snprintf$7) refers to printf7.o(i._snputc) for _snputc + printf7.o(i.__0sprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0sprintf$7) refers to printf7.o(i._sputc) for _sputc + printf7.o(i.__0vfprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vfprintf$7) refers to tau_log.o(i.fputc) for fputc + printf7.o(i.__0vprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vprintf$7) refers to tau_log.o(i.fputc) for fputc + printf7.o(i.__0vprintf$7) refers to stdout.o(.data) for __stdout + printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._snputc) for _snputc + printf7.o(i.__0vsprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vsprintf$7) refers to printf7.o(i._sputc) for _sputc + printf7.o(i._printf_core) refers to printf7.o(i._printf_pre_padding) for _printf_pre_padding + printf7.o(i._printf_core) refers to printf7.o(i._printf_post_padding) for _printf_post_padding + printf7.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf8.o(i.__0fprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0fprintf$8) refers to tau_log.o(i.fputc) for fputc + printf8.o(i.__0printf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0printf$8) refers to tau_log.o(i.fputc) for fputc + printf8.o(i.__0printf$8) refers to stdout.o(.data) for __stdout + printf8.o(i.__0snprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0snprintf$8) refers to printf8.o(i._snputc) for _snputc + printf8.o(i.__0sprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0sprintf$8) refers to printf8.o(i._sputc) for _sputc + printf8.o(i.__0vfprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vfprintf$8) refers to tau_log.o(i.fputc) for fputc + printf8.o(i.__0vprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vprintf$8) refers to tau_log.o(i.fputc) for fputc + printf8.o(i.__0vprintf$8) refers to stdout.o(.data) for __stdout + printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._snputc) for _snputc + printf8.o(i.__0vsprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vsprintf$8) refers to printf8.o(i._sputc) for _sputc + printf8.o(i._printf_core) refers to printf8.o(i._printf_pre_padding) for _printf_pre_padding + printf8.o(i._printf_core) refers to printf8.o(i._printf_post_padding) for _printf_post_padding + printf8.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i.__0fprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0fprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0fprintf) refers to tau_log.o(i.fputc) for fputc + printfa.o(i.__0printf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0printf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0printf) refers to tau_log.o(i.fputc) for fputc + printfa.o(i.__0printf) refers to stdout.o(.data) for __stdout + printfa.o(i.__0snprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0snprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0snprintf) refers to printfa.o(i._snputc) for _snputc + printfa.o(i.__0sprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0sprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0sprintf) refers to printfa.o(i._sputc) for _sputc + printfa.o(i.__0vfprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vfprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vfprintf) refers to tau_log.o(i.fputc) for fputc + printfa.o(i.__0vprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vprintf) refers to tau_log.o(i.fputc) for fputc + printfa.o(i.__0vprintf) refers to stdout.o(.data) for __stdout + printfa.o(i.__0vsnprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vsnprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vsnprintf) refers to printfa.o(i._snputc) for _snputc + printfa.o(i.__0vsprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vsprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vsprintf) refers to printfa.o(i._sputc) for _sputc + printfa.o(i._fp_digits) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._fp_digits) refers to dmul.o(.text) for __aeabi_dmul + printfa.o(i._fp_digits) refers to ddiv.o(.text) for __aeabi_ddiv + printfa.o(i._fp_digits) refers to cdrcmple.o(.text) for __aeabi_cdrcmple + printfa.o(i._fp_digits) refers to dadd.o(.text) for __aeabi_dadd + printfa.o(i._fp_digits) refers to dfixul.o(.text) for __aeabi_d2ulz + printfa.o(i._fp_digits) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i._printf_core) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._printf_core) refers to printfa.o(i._printf_pre_padding) for _printf_pre_padding + printfa.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i._printf_core) refers to printfa.o(i._printf_post_padding) for _printf_post_padding + printfa.o(i._printf_core) refers to printfa.o(i._fp_digits) for _fp_digits + printfa.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printfa.o(i._printf_post_padding) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._printf_pre_padding) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._snputc) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._sputc) refers (Special) to iusefp.o(.text) for __I$use$fp + fadd.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + fadd.o(.text) refers to fepilogue.o(.text) for _float_epilogue + fmul.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + fdiv.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + fdiv.o(.text) refers to fepilogue.o(.text) for _float_round + fscalb.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dadd.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dadd.o(.text) refers to llshl.o(.text) for __aeabi_llsl + dadd.o(.text) refers to llsshr.o(.text) for __aeabi_lasr + dadd.o(.text) refers to depilogue.o(.text) for _double_epilogue + dmul.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dmul.o(.text) refers to depilogue.o(.text) for _double_epilogue + ffltui.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + ffltui.o(.text) refers to fepilogue.o(.text) for _float_epilogue + dfltui.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dfltui.o(.text) refers to depilogue.o(.text) for _double_epilogue + ffixui.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dfixui.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dfixui.o(.text) refers to llushr.o(.text) for __aeabi_llsr + f2d.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + d2f.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + d2f.o(.text) refers to fepilogue.o(.text) for _float_round + cfcmple.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + cfrcmple.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000 + entry2.o(.ARM.Collect$$$$00002712) refers to startup_armcm0.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to startup_armcm0.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main + entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload + entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main + entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main + uldiv.o(.text) refers to llushr.o(.text) for __aeabi_llsr + uldiv.o(.text) refers to llshl.o(.text) for __aeabi_llsl + depilogue.o(.text) refers to depilogue.o(i.__ARM_clz) for __ARM_clz + depilogue.o(.text) refers to llshl.o(.text) for __aeabi_llsl + depilogue.o(.text) refers to llushr.o(.text) for __aeabi_llsr + ddiv.o(.text) refers to depilogue.o(.text) for _double_round + dfixul.o(.text) refers to llushr.o(.text) for __aeabi_llsr + dfixul.o(.text) refers to llshl.o(.text) for __aeabi_llsl + init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload + + +============================================================================== + +Removing Unused input sections from the image. + + Removing main.o(.rev16_text), (4 bytes). + Removing main.o(.revsh_text), (4 bytes). + Removing p8p_demo.o(.rev16_text), (4 bytes). + Removing p8p_demo.o(.revsh_text), (4 bytes). + Removing p8p_demo.o(i.Gpio_swire_output), (80 bytes). + Removing p8p_demo.o(i.Panel_CCM), (42 bytes). + Removing p8p_demo.o(i.REG_51_OFF_output), (60 bytes). + Removing p8p_demo.o(i.ap_dcs_set_exit_idle_mode), (104 bytes). + Removing p8p_demo.o(i.soft_te_timer_cb), (28 bytes). + Removing p8p_demo.o(i.soft_te_timer_init), (40 bytes). + Removing board.o(.rev16_text), (4 bytes). + Removing board.o(.revsh_text), (4 bytes). + Removing startup_armcm0.o(HEAP), (3072 bytes). + Removing hal_dsi_rx_ctrl.o(.rev16_text), (4 bytes). + Removing hal_dsi_rx_ctrl.o(.revsh_text), (4 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_ack_long_cmd), (220 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_ack_short_cmd), (28 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init), (320 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern), (260 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_force_video_crtl), (12 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_compressen_en), (8 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_callback), (52 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_write_cmd_entry), (10 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_release_handle), (40 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart), (68 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_ack), (176 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_hw_filter), (28 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_check_crc), (24 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk), (32 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_hw_cmd_filter), (44 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_log_level), (8 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data), (240 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk), (72 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rxbr_clk), (56 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_input_frame_rate), (10 bytes). + Removing hal_dsi_tx_ctrl.o(.rev16_text), (4 bytes). + Removing hal_dsi_tx_ctrl.o(.revsh_text), (4 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode), (112 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick), (244 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_frame), (12 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_get_disp_line), (12 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_overwrite_enable), (22 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_partial_disp_enable), (70 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd), (128 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_release_handle), (32 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_bcs), (60 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_ccm), (8 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_cus_sync_line), (36 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_dect), (60 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_enhance), (60 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_endianness), (12 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_escape_clock_div), (52 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_fc), (60 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_vpg), (28 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_vporch_bta_opera), (68 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_req_update), (16 bytes). + Removing hal_gpio.o(.rev16_text), (4 bytes). + Removing hal_gpio.o(.revsh_text), (4 bytes). + Removing hal_gpio.o(i.hal_gpio_get_input_data), (18 bytes). + Removing hal_gpio.o(i.hal_gpio_get_int_type), (20 bytes). + Removing hal_gpio.o(i.hal_gpio_get_pull_state), (40 bytes). + Removing hal_gpio.o(i.hal_gpio_set_driving_strength), (44 bytes). + Removing hal_gpio.o(i.hal_gpio_set_high_impedance), (32 bytes). + Removing hal_gpio.o(i.hal_gpio_set_pull_state), (72 bytes). + Removing hal_gpio.o(i.hal_gpio_set_schmitt_trigger), (52 bytes). + Removing hal_gpio.o(i.hal_gpio_set_slew_rate), (52 bytes). + Removing hal_gpio.o(.constdata), (78 bytes). + Removing hal_swire.o(.rev16_text), (4 bytes). + Removing hal_swire.o(.revsh_text), (4 bytes). + Removing hal_swire.o(i.hal_swire_register_callback), (22 bytes). + Removing hal_swire.o(i.hal_swire_set_waveform), (92 bytes). + Removing hal_system.o(.rev16_text), (4 bytes). + Removing hal_system.o(.revsh_text), (4 bytes). + Removing hal_system.o(i.hal_system_clear_debug_state), (10 bytes). + Removing hal_system.o(i.hal_system_disable_systick), (8 bytes). + Removing hal_system.o(i.hal_system_enable_systick), (8 bytes). + Removing hal_system.o(i.hal_system_get_debug_state), (8 bytes). + Removing hal_system.o(i.hal_system_get_tick), (8 bytes). + Removing hal_system.o(i.hal_system_idle_mode), (8 bytes). + Removing hal_system.o(i.hal_system_register_systick_cb), (8 bytes). + Removing hal_system.o(i.hal_system_reset_chip), (10 bytes). + Removing hal_timer.o(.rev16_text), (4 bytes). + Removing hal_timer.o(.revsh_text), (4 bytes). + Removing hal_timer.o(i.hal_timer_get_status), (8 bytes). + Removing hal_timer.o(i.hal_timer_start), (48 bytes). + Removing hal_timer.o(i.hal_timer_start_ex), (42 bytes). + Removing hal_timer.o(i.hal_timer_stop), (40 bytes). + Removing hal_pwr.o(.rev16_text), (4 bytes). + Removing hal_pwr.o(.revsh_text), (4 bytes). + Removing hal_pwr.o(i.hal_pwr_elvcc_close), (10 bytes). + Removing hal_pwr.o(i.hal_pwr_elvcc_ldo_en), (46 bytes). + Removing hal_pwr.o(i.hal_pwr_elvcc_vol_set), (8 bytes). + Removing hal_pwr.o(i.hal_pwr_get_reset_flag), (66 bytes). + Removing hal_pwr.o(i.hal_pwr_ldo13s_en), (8 bytes). + Removing hal_pwr.o(i.hal_pwr_ldo13s_set), (8 bytes). + Removing hal_pwr.o(i.hal_pwr_ldo18s_en), (8 bytes). + Removing hal_pwr.o(i.hal_pwr_ldo18s_set), (8 bytes). + Removing hal_pwr.o(i.hal_pwr_set_pvd), (8 bytes). + Removing hal_pwr.o(i.hal_pwr_set_vcc_enable), (8 bytes). + Removing tau_delay.o(.rev16_text), (4 bytes). + Removing tau_delay.o(.revsh_text), (4 bytes). + Removing tau_log.o(.rev16_text), (4 bytes). + Removing tau_log.o(.revsh_text), (4 bytes). + Removing tau_log.o(i.fgetc), (72 bytes). + Removing hal_uart.o(.rev16_text), (4 bytes). + Removing hal_uart.o(.revsh_text), (4 bytes). + Removing hal_uart.o(i.hal_uart0_rx_dma_cb), (20 bytes). + Removing hal_uart.o(i.hal_uart0_tx_dma_cb), (36 bytes). + Removing hal_uart.o(i.hal_uart1_rx_dma_cb), (20 bytes). + Removing hal_uart.o(i.hal_uart1_tx_dma_cb), (36 bytes). + Removing hal_uart.o(i.hal_uart_deinit), (48 bytes). + Removing hal_uart.o(i.hal_uart_dma_path_close), (92 bytes). + Removing hal_uart.o(i.hal_uart_dma_recv), (276 bytes). + Removing hal_uart.o(i.hal_uart_dma_send), (280 bytes). + Removing hal_uart.o(i.hal_uart_recv_blocking), (28 bytes). + Removing hal_uart.o(i.hal_uart_recv_none_blocking), (28 bytes). + Removing hal_uart.o(i.hal_uart_send_none_blocking), (28 bytes). + Removing hal_internal_vsync.o(.rev16_text), (4 bytes). + Removing hal_internal_vsync.o(.revsh_text), (4 bytes). + Removing hal_internal_vsync.o(i.hal_internal_sync_cmd_mode_rcv_te), (2 bytes). + Removing hal_internal_vsync.o(i.hal_internal_sync_register_rx_callback), (28 bytes). + Removing hal_internal_vsync.o(i.hal_internal_sync_set_fb_setting_manual), (28 bytes). + Removing hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line), (60 bytes). + Removing hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate), (134 bytes). + Removing hal_internal_vsync.o(.data), (4 bytes). + Removing hal_internal_dcs.o(.rev16_text), (4 bytes). + Removing hal_internal_dcs.o(.revsh_text), (4 bytes). + Removing hal_internal_dcs.o(i.hal_intl_dcs_register_write_cmd_entry), (12 bytes). + Removing hal_internal_dcs.o(i.hal_intl_dcs_set_dcs_direct_mode), (44 bytes). + Removing hal_internal_fb.o(.rev16_text), (4 bytes). + Removing hal_internal_fb.o(.revsh_text), (4 bytes). + Removing hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual), (480 bytes). + Removing hal_internal_fb.o(.conststring), (152 bytes). + Removing hal_internal_svs.o(.rev16_text), (4 bytes). + Removing hal_internal_svs.o(.revsh_text), (4 bytes). + Removing hal_internal_svs.o(i.hal_intl_svs_set_input_frate), (112 bytes). + Removing hal_internal_svs.o(i.hal_intl_svs_set_sync_coef), (12 bytes). + Removing drv_common.o(.rev16_text), (4 bytes). + Removing drv_common.o(.revsh_text), (4 bytes). + Removing drv_common.o(i.drv_common_disable_systick), (20 bytes). + Removing drv_common.o(i.drv_common_enable_systick), (88 bytes). + Removing drv_common.o(i.drv_common_get_tick), (12 bytes). + Removing drv_common.o(i.drv_common_idle_mode), (40 bytes). + Removing drv_common.o(i.drv_common_systick_register_cb), (12 bytes). + Removing drv_crgu.o(.rev16_text), (4 bytes). + Removing drv_crgu.o(.revsh_text), (4 bytes). + Removing drv_crgu.o(i.drv_crgu_clear_all_reset_flags), (12 bytes). + Removing drv_crgu.o(i.drv_crgu_clear_reset_flag), (20 bytes). + Removing drv_crgu.o(i.drv_crgu_get_all_reset_flag), (12 bytes). + Removing drv_crgu.o(i.drv_crgu_get_reset_flag), (24 bytes). + Removing drv_crgu.o(i.drv_crgu_get_system_clk), (104 bytes). + Removing drv_crgu.o(i.drv_crgu_reset_chip), (24 bytes). + Removing drv_crgu.o(i.drv_crgu_set_clock_src), (16 bytes). + Removing drv_dsc_dec.o(.rev16_text), (4 bytes). + Removing drv_dsc_dec.o(.revsh_text), (4 bytes). + Removing drv_gpio.o(.rev16_text), (4 bytes). + Removing drv_gpio.o(.revsh_text), (4 bytes). + Removing drv_gpio.o(i.drv_gpio_get_attribute), (16 bytes). + Removing drv_gpio.o(i.drv_gpio_get_input_data), (24 bytes). + Removing drv_gpio.o(i.drv_gpio_set_attribute), (28 bytes). + Removing drv_pwr.o(.rev16_text), (4 bytes). + Removing drv_pwr.o(.revsh_text), (4 bytes). + Removing drv_pwr.o(i.drv_pwr_10bit_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_analog_pwm_en), (44 bytes). + Removing drv_pwr.o(i.drv_pwr_charge_pump_en), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_close_iov18_tp18), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_dsc_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_elvcc_pwm_en), (124 bytes). + Removing drv_pwr.o(i.drv_pwr_enter_sleep_mode), (152 bytes). + Removing drv_pwr.o(i.drv_pwr_exit_sleep_mode_ex), (40 bytes). + Removing drv_pwr.o(i.drv_pwr_fb_pd), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_get_wakeflag), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_get_write_lock_st), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_hf_frm_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_hv_ldo_10M_clock), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_hv_ldo_mode_clock_sel), (60 bytes). + Removing drv_pwr.o(i.drv_pwr_hv_ldo_mode_sel), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_hv_ldo_voltage_set), (44 bytes). + Removing drv_pwr.o(i.drv_pwr_ldo11d_trim), (36 bytes). + Removing drv_pwr.o(i.drv_pwr_ldo13s_en), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_ldo13s_set), (44 bytes). + Removing drv_pwr.o(i.drv_pwr_ldo15_trim), (36 bytes). + Removing drv_pwr.o(i.drv_pwr_ldo18s_en), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_ldo18s_set), (44 bytes). + Removing drv_pwr.o(i.drv_pwr_ltpo_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_osc32k_trim), (36 bytes). + Removing drv_pwr.o(i.drv_pwr_osc80m_trim), (36 bytes). + Removing drv_pwr.o(i.drv_pwr_p3k_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_por_mode_flag), (32 bytes). + Removing drv_pwr.o(i.drv_pwr_power_in), (44 bytes). + Removing drv_pwr.o(i.drv_pwr_power_ready_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_power_sel), (44 bytes). + Removing drv_pwr.o(i.drv_pwr_pwm_output_pwm_led), (56 bytes). + Removing drv_pwr.o(i.drv_pwr_pwmled_driver_current_Big_step), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_pwmled_driver_current_small_step), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_pwmled_electric_current), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_pwmled_open_drain), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_ram_pd_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_read_boot_chipst), (12 bytes). + Removing drv_pwr.o(i.drv_pwr_read_chipcfg), (12 bytes). + Removing drv_pwr.o(i.drv_pwr_rgbr_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_set_ap_rst_mode), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_set_ldo11_mode), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_set_ldo15_mode), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_set_pvd), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_set_pvd_mode), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_set_system_clk), (32 bytes). + Removing drv_pwr.o(i.drv_pwr_sw_tp18_en), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_wakeflag_get), (16 bytes). + Removing drv_swire.o(.rev16_text), (4 bytes). + Removing drv_swire.o(.revsh_text), (4 bytes). + Removing drv_sys_cfg.o(.rev16_text), (4 bytes). + Removing drv_sys_cfg.o(.revsh_text), (4 bytes). + Removing drv_sys_cfg.o(i.drv_sys_cfg_sel_dma_req), (128 bytes). + Removing drv_timer.o(.rev16_text), (4 bytes). + Removing drv_timer.o(.revsh_text), (4 bytes). + Removing drv_timer.o(i.drv_timer_get_status), (38 bytes). + Removing drv_timer.o(i.drv_timer_register_callback), (20 bytes). + Removing dcs_packet_fifo.o(.rev16_text), (4 bytes). + Removing dcs_packet_fifo.o(.revsh_text), (4 bytes). + Removing dcs_packet_fifo.o(i.dcs_packet_get_fifo_size), (16 bytes). + Removing drv_se.o(.rev16_text), (4 bytes). + Removing drv_se.o(.revsh_text), (4 bytes). + Removing drv_dsi_rx.o(.rev16_text), (4 bytes). + Removing drv_dsi_rx.o(.revsh_text), (4 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_force_video_crtl), (28 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_get_lpdt_fifo_status), (16 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_get_phy_stopstate), (68 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_get_version), (12 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_pg_cfg), (24 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_set_drv_log_level), (12 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_pg_cfg), (48 bytes). + Removing drv_dsi_tx.o(.rev16_text), (4 bytes). + Removing drv_dsi_tx.o(.revsh_text), (4 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_command_get_payload), (12 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_force_interrupt), (12 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_get_phy_status), (12 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_forcepll), (16 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_start), (24 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_status_pll_lock), (16 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ulpsactivenot), (68 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_trigger), (92 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_enter), (296 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_exit), (228 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_sdf_3d), (32 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_set_bta), (28 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_set_vpg), (100 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_version), (12 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_vid_shadow), (20 bytes). + Removing drv_dsi_tx.o(i.drv_tx_phy_test_clear), (16 bytes). + Removing drv_dsi_tx.o(i.drv_tx_phy_test_lock), (32 bytes). + Removing drv_dsi_tx.o(i.drv_tx_phy_test_read), (16 bytes). + Removing drv_lcdc.o(.rev16_text), (4 bytes). + Removing drv_lcdc.o(.revsh_text), (4 bytes). + Removing drv_lcdc.o(i.drv_lcdc_clear_irq), (16 bytes). + Removing drv_lcdc.o(i.drv_lcdc_dpisignal_output_ctrl), (44 bytes). + Removing drv_lcdc.o(i.drv_lcdc_fixed_frame_output), (56 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_dpbuf_num), (12 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_dpi_status), (16 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_frame_clk_count), (16 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_int_en_status), (12 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_int_status), (12 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_line_status), (12 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_rgb2pen_subpixel), (16 bytes). + Removing drv_lcdc.o(i.drv_lcdc_part_display_config), (52 bytes). + Removing drv_lcdc.o(i.drv_lcdc_pixel_value_config), (32 bytes). + Removing drv_lcdc.o(i.drv_lcdc_rd_st_line_config), (28 bytes). + Removing drv_lcdc.o(i.drv_lcdc_software_reset), (16 bytes). + Removing drv_lcdc.o(i.drv_lcdc_update_shadow_reg), (16 bytes). + Removing drv_lcdc.o(i.drv_lcdc_vid_sw_start), (56 bytes). + Removing drv_memc.o(.rev16_text), (4 bytes). + Removing drv_memc.o(.revsh_text), (4 bytes). + Removing drv_memc.o(i.drv_memc_set_db_frm_time), (20 bytes). + Removing drv_memc.o(i.drv_memc_set_db_int_frame), (36 bytes). + Removing drv_memc.o(i.drv_memc_set_double_buffer_reverse), (24 bytes). + Removing drv_memc.o(i.drv_memc_set_fb_pri), (44 bytes). + Removing drv_memc.o(i.drv_memc_set_fb_remaining_line_trigger), (20 bytes). + Removing drv_memc.o(i.drv_memc_set_inten), (28 bytes). + Removing drv_memc.o(i.drv_memc_set_read_trigger_line), (24 bytes). + Removing drv_memc.o(i.drv_memc_set_te_ind), (20 bytes). + Removing drv_memc.o(i.drv_memc_set_tear_hwclr), (24 bytes). + Removing drv_memc.o(i.drv_memc_set_vidc_fb_arb), (20 bytes). + Removing drv_memc.o(i.drv_memc_set_write_trigger_line), (24 bytes). + Removing drv_rxbr.o(.rev16_text), (4 bytes). + Removing drv_rxbr.o(.revsh_text), (4 bytes). + Removing drv_rxbr.o(i.drv_rxbr_clr_swp_cnt), (16 bytes). + Removing drv_rxbr.o(i.drv_rxbr_dsc_flush), (24 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_col_addr), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_cur_hline_rcv_cnt), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_frame_data_interval), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_hline_dcat), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_ipi_vsync_interval), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_page_addr), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_pix_fmt), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_swpxl_cnt), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_hline_rcv0_cfg), (20 bytes). + Removing drv_rxbr.o(i.drv_rxbr_register_irq0_callback), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_ack_pkt_md), (28 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_cmd_filter), (320 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_cmd_response), (324 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_col_addr), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_compress), (32 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_data_catch_hline), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_page_addr), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_swpxl_data), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_tmpdith_bp), (28 bytes). + Removing drv_rxbr.o(i.drv_rxbr_soft_reset), (32 bytes). + Removing drv_rxbr.o(i.drv_rxbr_sw_reset), (164 bytes). + Removing drv_rxbr.o(i.drv_rxbr_swpxl_clr), (32 bytes). + Removing drv_vidc.o(.rev16_text), (4 bytes). + Removing drv_vidc.o(.revsh_text), (4 bytes). + Removing drv_vidc.o(i.drv_vidc_clear_status0), (20 bytes). + Removing drv_vidc.o(i.drv_vidc_debug_cap_pixel), (28 bytes). + Removing drv_vidc.o(i.drv_vidc_debug_signal_frame), (36 bytes). + Removing drv_vidc.o(i.drv_vidc_get_status0), (24 bytes). + Removing drv_vidc.o(i.drv_vidc_get_status1), (24 bytes). + Removing drv_vidc.o(i.drv_vidc_get_status2), (12 bytes). + Removing drv_vidc.o(i.drv_vidc_set_dsc_thresh), (12 bytes). + Removing drv_vidc.o(i.drv_vidc_set_frmst_latency), (20 bytes). + Removing drv_vidc.o(i.drv_vidc_set_inff_thresh), (12 bytes). + Removing drv_vidc.o(i.drv_vidc_set_irq_line), (24 bytes). + Removing drv_vidc.o(i.drv_vidc_set_module_enable), (28 bytes). + Removing drv_vidc.o(i.drv_vidc_set_outff_thresh), (12 bytes). + Removing drv_vidc.o(i.drv_vidc_update_src_format), (20 bytes). + Removing drv_dma.o(.rev16_text), (4 bytes). + Removing drv_dma.o(.revsh_text), (4 bytes). + Removing drv_dma.o(i.drv_dma_apply_handle), (304 bytes). + Removing drv_dma.o(i.drv_dma_deinit), (52 bytes). + Removing drv_dma.o(i.drv_dma_disable), (20 bytes). + Removing drv_dma.o(i.drv_dma_disable_int), (40 bytes). + Removing drv_dma.o(i.drv_dma_enable), (36 bytes). + Removing drv_dma.o(i.drv_dma_enable_int), (68 bytes). + Removing drv_dma.o(i.drv_dma_get_remaining_trans_num), (20 bytes). + Removing drv_dma.o(i.drv_dma_get_status), (20 bytes). + Removing drv_dma.o(i.drv_dma_init), (22 bytes). + Removing drv_dma.o(i.drv_dma_int_list_delete), (88 bytes). + Removing drv_dma.o(i.drv_dma_int_list_inset), (48 bytes). + Removing drv_dma.o(i.drv_dma_register_callback), (4 bytes). + Removing drv_dma.o(i.drv_dma_reset), (36 bytes). + Removing drv_dma.o(i.drv_dma_set_bitwide), (56 bytes). + Removing drv_dma.o(i.drv_dma_set_burst), (20 bytes). + Removing drv_dma.o(i.drv_dma_set_circle_mode), (40 bytes). + Removing drv_dma.o(i.drv_dma_set_dir), (40 bytes). + Removing drv_dma.o(i.drv_dma_set_increment), (72 bytes). + Removing drv_dma.o(i.drv_dma_set_mem_trans_info), (40 bytes). + Removing drv_dma.o(i.drv_dma_set_mem_trans_offset), (24 bytes). + Removing drv_dma.o(i.drv_dma_set_per_address), (20 bytes). + Removing drv_dma.o(i.drv_dma_set_priority), (32 bytes). + Removing drv_dma.o(i.drv_dma_set_tran_int_cnt), (28 bytes). + Removing drv_dma.o(i.drv_dma_update_handle_setting), (148 bytes). + Removing drv_dma.o(i.drv_dma_update_req_by_default), (40 bytes). + Removing drv_dma.o(.constdata), (136 bytes). + Removing drv_uart.o(.rev16_text), (4 bytes). + Removing drv_uart.o(.revsh_text), (4 bytes). + Removing drv_uart.o(i.drv_uart_deinit), (60 bytes). + Removing drv_uart.o(i.drv_uart_get_def_cfg), (72 bytes). + Removing drv_uart.o(i.drv_uart_recv_blocking), (48 bytes). + Removing drv_uart.o(i.drv_uart_recv_none_blocking), (60 bytes). + Removing drv_uart.o(i.drv_uart_send_none_blocking), (60 bytes). + Removing drv_efuse.o(.rev16_text), (4 bytes). + Removing drv_efuse.o(.revsh_text), (4 bytes). + Removing drv_efuse.o(i.drv_efuse_crc_cal), (128 bytes). + Removing drv_efuse.o(i.drv_efuse_get_default_config), (26 bytes). + Removing drv_efuse.o(i.drv_efuse_int_disable), (12 bytes). + Removing drv_efuse.o(i.drv_efuse_write), (56 bytes). + Removing drv_efuse.o(i.drv_efuse_write_read_req_clear), (22 bytes). + Removing drv_efuse.o(i.drv_efuse_write_req), (22 bytes). + Removing drv_phy_common.o(.rev16_text), (4 bytes). + Removing drv_phy_common.o(.revsh_text), (4 bytes). + Removing drv_per_common.o(.rev16_text), (4 bytes). + Removing drv_per_common.o(.revsh_text), (4 bytes). + Removing drv_per_common.o(i.drv_per_get_system_clk), (8 bytes). + Removing drv_per_common.o(i.drv_per_reset_module), (14 bytes). + Removing drv_per_common.o(i.drv_per_set_clock), (14 bytes). + +374 unused section(s) (total 17522 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/../cmprslib/zerorunl2.c 0x00000000 Number 0 __dczerorl2.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 uidiv.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 idiv.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 uldiv.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llsshr.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llushr.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llshl.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf8.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printfa.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf3.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf1.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printfb.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf0.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf2.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf4.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf6.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf7.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf5.o ABSOLUTE + ../clib/microlib/printf/stubs.s 0x00000000 Number 0 stubs.o ABSOLUTE + ../clib/microlib/stdio/streams.c 0x00000000 Number 0 stdout.o ABSOLUTE + ../clib/microlib/string/memcpy.c 0x00000000 Number 0 memcpyb.o ABSOLUTE + ../clib/microlib/string/memcpy.c 0x00000000 Number 0 memcpya.o ABSOLUTE + ../clib/microlib/string/memset.c 0x00000000 Number 0 memseta.o ABSOLUTE + ../clib/microlib/string/strlen.c 0x00000000 Number 0 strlen.o ABSOLUTE + ../clib/microlib/stubs.s 0x00000000 Number 0 iusefp.o ABSOLUTE + ../fplib/microlib/d2f.c 0x00000000 Number 0 d2f.o ABSOLUTE + ../fplib/microlib/f2d.c 0x00000000 Number 0 f2d.o ABSOLUTE + ../fplib/microlib/fpadd.c 0x00000000 Number 0 fadd.o ABSOLUTE + ../fplib/microlib/fpadd.c 0x00000000 Number 0 dadd.o ABSOLUTE + ../fplib/microlib/fpdiv.c 0x00000000 Number 0 fdiv.o ABSOLUTE + ../fplib/microlib/fpdiv.c 0x00000000 Number 0 ddiv.o ABSOLUTE + ../fplib/microlib/fpepilogue.c 0x00000000 Number 0 depilogue.o ABSOLUTE + ../fplib/microlib/fpepilogue.c 0x00000000 Number 0 fepilogue.o ABSOLUTE + ../fplib/microlib/fpfix.c 0x00000000 Number 0 dfixul.o ABSOLUTE + ../fplib/microlib/fpfix.c 0x00000000 Number 0 dfixui.o ABSOLUTE + ../fplib/microlib/fpfix.c 0x00000000 Number 0 ffixui.o ABSOLUTE + ../fplib/microlib/fpflt.c 0x00000000 Number 0 ffltui.o ABSOLUTE + ../fplib/microlib/fpflt.c 0x00000000 Number 0 dfltui.o ABSOLUTE + ../fplib/microlib/fpmul.c 0x00000000 Number 0 fmul.o ABSOLUTE + ../fplib/microlib/fpmul.c 0x00000000 Number 0 dmul.o ABSOLUTE + ../fplib/microlib/fpscalb.c 0x00000000 Number 0 fscalb.o ABSOLUTE + ../mathlib/ceil.c 0x00000000 Number 0 ceil.o ABSOLUTE + ..\..\..\src\common\tau_delay.c 0x00000000 Number 0 tau_delay.o ABSOLUTE + ..\..\..\src\common\tau_log.c 0x00000000 Number 0 tau_log.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_common.c 0x00000000 Number 0 drv_common.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_crgu.c 0x00000000 Number 0 drv_crgu.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_dma.c 0x00000000 Number 0 drv_dma.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_dsc_dec.c 0x00000000 Number 0 drv_dsc_dec.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_dsi_rx.c 0x00000000 Number 0 drv_dsi_rx.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_dsi_tx.c 0x00000000 Number 0 drv_dsi_tx.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_efuse.c 0x00000000 Number 0 drv_efuse.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_gpio.c 0x00000000 Number 0 drv_gpio.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_lcdc.c 0x00000000 Number 0 drv_lcdc.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_memc.c 0x00000000 Number 0 drv_memc.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_per_common.c 0x00000000 Number 0 drv_per_common.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_phy_common.c 0x00000000 Number 0 drv_phy_common.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_pwr.c 0x00000000 Number 0 drv_pwr.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_rxbr.c 0x00000000 Number 0 drv_rxbr.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_swire.c 0x00000000 Number 0 drv_swire.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_sys_cfg.c 0x00000000 Number 0 drv_sys_cfg.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_timer.c 0x00000000 Number 0 drv_timer.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_uart.c 0x00000000 Number 0 drv_uart.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_vidc.c 0x00000000 Number 0 drv_vidc.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_dsi_rx_ctrl.c 0x00000000 Number 0 hal_dsi_rx_ctrl.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_dsi_tx_ctrl.c 0x00000000 Number 0 hal_dsi_tx_ctrl.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_gpio.c 0x00000000 Number 0 hal_gpio.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_pwr.c 0x00000000 Number 0 hal_pwr.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_swire.c 0x00000000 Number 0 hal_swire.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_system.c 0x00000000 Number 0 hal_system.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_timer.c 0x00000000 Number 0 hal_timer.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_uart.c 0x00000000 Number 0 hal_uart.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\internal\dcs_packet_fifo.c 0x00000000 Number 0 dcs_packet_fifo.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\internal\hal_internal_dcs.c 0x00000000 Number 0 hal_internal_dcs.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\internal\hal_internal_fb.c 0x00000000 Number 0 hal_internal_fb.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\internal\hal_internal_svs.c 0x00000000 Number 0 hal_internal_svs.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\internal\hal_internal_vsync.c 0x00000000 Number 0 hal_internal_vsync.o ABSOLUTE + ..\..\..\src\driver\cuckoo\src\drv_se.c 0x00000000 Number 0 drv_se.o ABSOLUTE + ..\..\src\app\P8P\p8p_demo.c 0x00000000 Number 0 p8p_demo.o ABSOLUTE + ..\..\src\app\main.c 0x00000000 Number 0 main.o ABSOLUTE + ..\..\src\board\board.c 0x00000000 Number 0 board.o ABSOLUTE + ..\..\src\board\startup\startup_ARMCM0.s 0x00000000 Number 0 startup_armcm0.o ABSOLUTE + ..\\..\\..\\src\\common\\tau_delay.c 0x00000000 Number 0 tau_delay.o ABSOLUTE + ..\\..\\..\\src\\common\\tau_log.c 0x00000000 Number 0 tau_log.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_common.c 0x00000000 Number 0 drv_common.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_crgu.c 0x00000000 Number 0 drv_crgu.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_dma.c 0x00000000 Number 0 drv_dma.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_dsc_dec.c 0x00000000 Number 0 drv_dsc_dec.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_dsi_rx.c 0x00000000 Number 0 drv_dsi_rx.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_dsi_tx.c 0x00000000 Number 0 drv_dsi_tx.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_efuse.c 0x00000000 Number 0 drv_efuse.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_gpio.c 0x00000000 Number 0 drv_gpio.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_lcdc.c 0x00000000 Number 0 drv_lcdc.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_memc.c 0x00000000 Number 0 drv_memc.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_per_common.c 0x00000000 Number 0 drv_per_common.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_phy_common.c 0x00000000 Number 0 drv_phy_common.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_pwr.c 0x00000000 Number 0 drv_pwr.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_rxbr.c 0x00000000 Number 0 drv_rxbr.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_swire.c 0x00000000 Number 0 drv_swire.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_sys_cfg.c 0x00000000 Number 0 drv_sys_cfg.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_timer.c 0x00000000 Number 0 drv_timer.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_uart.c 0x00000000 Number 0 drv_uart.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_vidc.c 0x00000000 Number 0 drv_vidc.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_dsi_rx_ctrl.c 0x00000000 Number 0 hal_dsi_rx_ctrl.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_dsi_tx_ctrl.c 0x00000000 Number 0 hal_dsi_tx_ctrl.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_gpio.c 0x00000000 Number 0 hal_gpio.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_pwr.c 0x00000000 Number 0 hal_pwr.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_swire.c 0x00000000 Number 0 hal_swire.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_system.c 0x00000000 Number 0 hal_system.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_timer.c 0x00000000 Number 0 hal_timer.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_uart.c 0x00000000 Number 0 hal_uart.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\internal\\dcs_packet_fifo.c 0x00000000 Number 0 dcs_packet_fifo.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\internal\\hal_internal_dcs.c 0x00000000 Number 0 hal_internal_dcs.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\internal\\hal_internal_fb.c 0x00000000 Number 0 hal_internal_fb.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\internal\\hal_internal_svs.c 0x00000000 Number 0 hal_internal_svs.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\internal\\hal_internal_vsync.c 0x00000000 Number 0 hal_internal_vsync.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\src\\drv_se.c 0x00000000 Number 0 drv_se.o ABSOLUTE + ..\\..\\src\\app\\P8P\\p8p_demo.c 0x00000000 Number 0 p8p_demo.o ABSOLUTE + ..\\..\\src\\app\\main.c 0x00000000 Number 0 main.o ABSOLUTE + ..\\..\\src\\board\\board.c 0x00000000 Number 0 board.o ABSOLUTE + cdrcmple.s 0x00000000 Number 0 cdrcmple.o ABSOLUTE + cfcmple.s 0x00000000 Number 0 cfcmple.o ABSOLUTE + cfrcmple.s 0x00000000 Number 0 cfrcmple.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE + init.s 0x00000000 Number 0 init.o ABSOLUTE + RESET 0x00010000 Section 192 startup_armcm0.o(RESET) + .ARM.Collect$$$$00000000 0x000100c0 Section 0 entry.o(.ARM.Collect$$$$00000000) + .ARM.Collect$$$$00000001 0x000100c0 Section 4 entry2.o(.ARM.Collect$$$$00000001) + .ARM.Collect$$$$00000004 0x000100c4 Section 4 entry5.o(.ARM.Collect$$$$00000004) + .ARM.Collect$$$$00000008 0x000100c8 Section 0 entry7b.o(.ARM.Collect$$$$00000008) + .ARM.Collect$$$$0000000A 0x000100c8 Section 0 entry8b.o(.ARM.Collect$$$$0000000A) + .ARM.Collect$$$$0000000B 0x000100c8 Section 8 entry9a.o(.ARM.Collect$$$$0000000B) + .ARM.Collect$$$$0000000D 0x000100d0 Section 0 entry10a.o(.ARM.Collect$$$$0000000D) + .ARM.Collect$$$$0000000F 0x000100d0 Section 0 entry11a.o(.ARM.Collect$$$$0000000F) + .ARM.Collect$$$$00002712 0x000100d0 Section 4 entry2.o(.ARM.Collect$$$$00002712) + __lit__00000000 0x000100d0 Data 4 entry2.o(.ARM.Collect$$$$00002712) + .text 0x000100d4 Section 120 startup_armcm0.o(.text) + .text 0x0001014c Section 0 uidiv.o(.text) + .text 0x00010178 Section 0 idiv.o(.text) + .text 0x000101a0 Section 0 memcpya.o(.text) + .text 0x000101c4 Section 0 memseta.o(.text) + .text 0x000101e8 Section 0 strlen.o(.text) + .text 0x000101f6 Section 0 fadd.o(.text) + .text 0x000102a8 Section 0 fmul.o(.text) + .text 0x00010322 Section 0 fdiv.o(.text) + .text 0x0001039e Section 0 fscalb.o(.text) + .text 0x000103b8 Section 0 dadd.o(.text) + .text 0x0001051c Section 0 dmul.o(.text) + .text 0x000105ec Section 0 ffltui.o(.text) + .text 0x000105fc Section 0 dfltui.o(.text) + .text 0x00010618 Section 0 ffixui.o(.text) + .text 0x00010640 Section 0 dfixui.o(.text) + .text 0x0001067c Section 0 f2d.o(.text) + .text 0x000106a4 Section 0 d2f.o(.text) + .text 0x000106dc Section 20 cfcmple.o(.text) + .text 0x000106f0 Section 20 cfrcmple.o(.text) + .text 0x00010704 Section 0 uldiv.o(.text) + .text 0x00010764 Section 0 llshl.o(.text) + .text 0x00010784 Section 0 llushr.o(.text) + .text 0x000107a6 Section 0 llsshr.o(.text) + .text 0x000107cc Section 0 iusefp.o(.text) + .text 0x000107cc Section 0 fepilogue.o(.text) + .text 0x0001084e Section 0 depilogue.o(.text) + .text 0x0001090c Section 0 ddiv.o(.text) + .text 0x000109fc Section 0 dfixul.o(.text) + .text 0x00010a3c Section 40 cdrcmple.o(.text) + .text 0x00010a64 Section 36 init.o(.text) + .text 0x00010a88 Section 0 __dczerorl2.o(.text) + i.AP_NRESET_IRQn_Handler 0x00010ae0 Section 0 drv_gpio.o(i.AP_NRESET_IRQn_Handler) + i.DMA_IRQn_Handler 0x00010afc Section 0 drv_dma.o(i.DMA_IRQn_Handler) + i.EXTI_INT0_IRQn_Handler 0x00010b58 Section 0 drv_gpio.o(i.EXTI_INT0_IRQn_Handler) + i.EXTI_INT1_IRQn_Handler 0x00010b62 Section 0 drv_gpio.o(i.EXTI_INT1_IRQn_Handler) + i.EXTI_INT2_IRQn_Handler 0x00010b6c Section 0 drv_gpio.o(i.EXTI_INT2_IRQn_Handler) + i.EXTI_INT3_IRQn_Handler 0x00010b76 Section 0 drv_gpio.o(i.EXTI_INT3_IRQn_Handler) + i.EXTI_INT4_IRQn_Handler 0x00010b80 Section 0 drv_gpio.o(i.EXTI_INT4_IRQn_Handler) + i.EXTI_INT5_IRQn_Handler 0x00010b8a Section 0 drv_gpio.o(i.EXTI_INT5_IRQn_Handler) + i.EXTI_INT6_IRQn_Handler 0x00010b94 Section 0 drv_gpio.o(i.EXTI_INT6_IRQn_Handler) + i.EXTI_INT7_IRQn_Handler 0x00010b9e Section 0 drv_gpio.o(i.EXTI_INT7_IRQn_Handler) + i.HardFault_Handler 0x00010ba8 Section 0 drv_common.o(i.HardFault_Handler) + i.LCDC_IRQn_Handler 0x00010bf0 Section 0 hal_internal_vsync.o(i.LCDC_IRQn_Handler) + i.MEMC_IRQn_Handler 0x00010cf0 Section 0 drv_memc.o(i.MEMC_IRQn_Handler) + i.MIPI_TX_IRQn_Handler 0x00010d8c Section 0 drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler) + i.SWIRE_IRQn_Handler 0x00010e44 Section 0 drv_swire.o(i.SWIRE_IRQn_Handler) + i.SysTick_Handler 0x00010e74 Section 0 drv_common.o(i.SysTick_Handler) + i.TIMER0_IRQn_Handler 0x00010e8c Section 0 drv_timer.o(i.TIMER0_IRQn_Handler) + i.TIMER1_IRQn_Handler 0x00010e96 Section 0 drv_timer.o(i.TIMER1_IRQn_Handler) + i.TIMER2_IRQn_Handler 0x00010ea0 Section 0 drv_timer.o(i.TIMER2_IRQn_Handler) + i.TIMER3_IRQn_Handler 0x00010eaa Section 0 drv_timer.o(i.TIMER3_IRQn_Handler) + i.VIDC_IRQn_Handler 0x00010eb4 Section 0 drv_vidc.o(i.VIDC_IRQn_Handler) + i.VPRE1_IRQn_Handler 0x00010ed0 Section 0 drv_rxbr.o(i.VPRE1_IRQn_Handler) + i.VPRE_IRQn_Handler 0x00010eec Section 0 hal_internal_dcs.o(i.VPRE_IRQn_Handler) + i.__0printf 0x00010f68 Section 0 printfa.o(i.__0printf) + i.__0vsprintf 0x00010f88 Section 0 printfa.o(i.__0vsprintf) + i.__ARM_clz 0x00010fac Section 0 depilogue.o(i.__ARM_clz) + i.__ARM_common_switch8 0x00010fda Section 0 hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) + i.__scatterload_null 0x00010ff4 Section 2 handlers.o(i.__scatterload_null) + i._sputc 0x00010ff6 Section 0 printfa.o(i._sputc) + _sputc 0x00010ff7 Thumb Code 10 printfa.o(i._sputc) + .ARM.__at_0x11000 0x00011000 Section 28 drv_common.o(.ARM.__at_0x11000) + .ARM.__at_0x1101C 0x0001101c Section 16 tau_log.o(.ARM.__at_0x1101C) + .ARM.__at_0x1102C 0x0001102c Section 22 hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) + i.MIPI_RX_IRQn_Handler 0x00011044 Section 0 drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler) + i.UART_IRQn_Handler 0x000113a8 Section 0 drv_uart.o(i.UART_IRQn_Handler) + i.__NVIC_DisableIRQ 0x00011528 Section 0 drv_rxbr.o(i.__NVIC_DisableIRQ) + __NVIC_DisableIRQ 0x00011529 Thumb Code 26 drv_rxbr.o(i.__NVIC_DisableIRQ) + i.__NVIC_EnableIRQ 0x00011548 Section 0 drv_rxbr.o(i.__NVIC_EnableIRQ) + __NVIC_EnableIRQ 0x00011549 Thumb Code 18 drv_rxbr.o(i.__NVIC_EnableIRQ) + i.__scatterload_copy 0x00011560 Section 14 handlers.o(i.__scatterload_copy) + i.__scatterload_zeroinit 0x0001156e Section 14 handlers.o(i.__scatterload_zeroinit) + i._fp_digits 0x0001157c Section 0 printfa.o(i._fp_digits) + _fp_digits 0x0001157d Thumb Code 344 printfa.o(i._fp_digits) + i._printf_core 0x000116f0 Section 0 printfa.o(i._printf_core) + _printf_core 0x000116f1 Thumb Code 1754 printfa.o(i._printf_core) + i._printf_post_padding 0x00011ddc Section 0 printfa.o(i._printf_post_padding) + _printf_post_padding 0x00011ddd Thumb Code 32 printfa.o(i._printf_post_padding) + i._printf_pre_padding 0x00011dfc Section 0 printfa.o(i._printf_pre_padding) + _printf_pre_padding 0x00011dfd Thumb Code 44 printfa.o(i._printf_pre_padding) + i.ap_dcs_read 0x00011e28 Section 0 p8p_demo.o(i.ap_dcs_read) + ap_dcs_read 0x00011e29 Thumb Code 280 p8p_demo.o(i.ap_dcs_read) + i.ap_dcs_set_backlight 0x00011f6c Section 0 p8p_demo.o(i.ap_dcs_set_backlight) + ap_dcs_set_backlight 0x00011f6d Thumb Code 146 p8p_demo.o(i.ap_dcs_set_backlight) + i.ap_dcs_set_display_off 0x00012010 Section 0 p8p_demo.o(i.ap_dcs_set_display_off) + ap_dcs_set_display_off 0x00012011 Thumb Code 34 p8p_demo.o(i.ap_dcs_set_display_off) + i.ap_dcs_set_display_on 0x00012058 Section 0 p8p_demo.o(i.ap_dcs_set_display_on) + ap_dcs_set_display_on 0x00012059 Thumb Code 90 p8p_demo.o(i.ap_dcs_set_display_on) + i.ap_dcs_set_enter_sleep_mode 0x000120f8 Section 0 p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) + ap_dcs_set_enter_sleep_mode 0x000120f9 Thumb Code 104 p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) + i.ap_dcs_set_exit_sleep_mode 0x0001218c Section 0 p8p_demo.o(i.ap_dcs_set_exit_sleep_mode) + ap_dcs_set_exit_sleep_mode 0x0001218d Thumb Code 28 p8p_demo.o(i.ap_dcs_set_exit_sleep_mode) + i.ap_dcs_set_frame_change 0x000121cc Section 0 p8p_demo.o(i.ap_dcs_set_frame_change) + ap_dcs_set_frame_change 0x000121cd Thumb Code 46 p8p_demo.o(i.ap_dcs_set_frame_change) + i.ap_rstn_pull_down_cb 0x00012200 Section 0 p8p_demo.o(i.ap_rstn_pull_down_cb) + ap_rstn_pull_down_cb 0x00012201 Thumb Code 38 p8p_demo.o(i.ap_rstn_pull_down_cb) + i.ap_rstn_pull_high_cb 0x00012258 Section 0 p8p_demo.o(i.ap_rstn_pull_high_cb) + ap_rstn_pull_high_cb 0x00012259 Thumb Code 22 p8p_demo.o(i.ap_rstn_pull_high_cb) + i.ap_set_FPS_53 0x00012274 Section 0 p8p_demo.o(i.ap_set_FPS_53) + ap_set_FPS_53 0x00012275 Thumb Code 74 p8p_demo.o(i.ap_set_FPS_53) + i.app_display_init 0x000122be Section 0 p8p_demo.o(i.app_display_init) + i.app_gpio_init 0x000122ec Section 0 p8p_demo.o(i.app_gpio_init) + i.app_init_panel 0x00012308 Section 0 p8p_demo.o(i.app_init_panel) + app_init_panel 0x00012309 Thumb Code 42 p8p_demo.o(i.app_init_panel) + i.app_mipi_rx_init 0x0001233c Section 0 p8p_demo.o(i.app_mipi_rx_init) + app_mipi_rx_init 0x0001233d Thumb Code 232 p8p_demo.o(i.app_mipi_rx_init) + i.app_mipi_tx_init 0x0001245c Section 0 p8p_demo.o(i.app_mipi_tx_init) + app_mipi_tx_init 0x0001245d Thumb Code 214 p8p_demo.o(i.app_mipi_tx_init) + i.app_mipi_tx_start 0x0001255c Section 0 p8p_demo.o(i.app_mipi_tx_start) + app_mipi_tx_start 0x0001255d Thumb Code 118 p8p_demo.o(i.app_mipi_tx_start) + i.app_system_process 0x00012608 Section 0 p8p_demo.o(i.app_system_process) + app_system_process 0x00012609 Thumb Code 60 p8p_demo.o(i.app_system_process) + i.app_system_resume 0x00012674 Section 0 p8p_demo.o(i.app_system_resume) + app_system_resume 0x00012675 Thumb Code 30 p8p_demo.o(i.app_system_resume) + i.app_system_suspend 0x000126b8 Section 0 p8p_demo.o(i.app_system_suspend) + app_system_suspend 0x000126b9 Thumb Code 202 p8p_demo.o(i.app_system_suspend) + i.app_tx_panel_reset 0x00012848 Section 0 p8p_demo.o(i.app_tx_panel_reset) + app_tx_panel_reset 0x00012849 Thumb Code 46 p8p_demo.o(i.app_tx_panel_reset) + i.board_Init 0x00012878 Section 0 board.o(i.board_Init) + i.ceil 0x00012890 Section 0 ceil.o(i.ceil) + i.check_mipi_rx_tx_video_info 0x00012958 Section 0 hal_internal_vsync.o(i.check_mipi_rx_tx_video_info) + check_mipi_rx_tx_video_info 0x00012959 Thumb Code 44 hal_internal_vsync.o(i.check_mipi_rx_tx_video_info) + i.check_pkt_buf_rev 0x00012984 Section 0 hal_internal_dcs.o(i.check_pkt_buf_rev) + check_pkt_buf_rev 0x00012985 Thumb Code 84 hal_internal_dcs.o(i.check_pkt_buf_rev) + i.dcs_packet_fifo_alloc 0x00012a0c Section 0 dcs_packet_fifo.o(i.dcs_packet_fifo_alloc) + i.dcs_packet_fifo_init 0x00012a64 Section 0 dcs_packet_fifo.o(i.dcs_packet_fifo_init) + i.dcs_packet_free_fifo_header 0x00012a7c Section 0 dcs_packet_fifo.o(i.dcs_packet_free_fifo_header) + i.dcs_packet_get_fifo_header 0x00012ac0 Section 0 dcs_packet_fifo.o(i.dcs_packet_get_fifo_header) + i.delayMs 0x00012ae4 Section 0 tau_delay.o(i.delayMs) + i.delayUs 0x00012afc Section 0 tau_delay.o(i.delayUs) + i.drv_common_system_init 0x00012b28 Section 0 drv_common.o(i.drv_common_system_init) + i.drv_crgu_enable_clock 0x00012b30 Section 0 drv_crgu.o(i.drv_crgu_enable_clock) + i.drv_crgu_get_rxbr_clk 0x00012b6c Section 0 drv_crgu.o(i.drv_crgu_get_rxbr_clk) + i.drv_crgu_reset_modules 0x00012bd4 Section 0 drv_crgu.o(i.drv_crgu_reset_modules) + i.drv_crgu_set_ahb_clk 0x00012be4 Section 0 drv_crgu.o(i.drv_crgu_set_ahb_clk) + i.drv_crgu_set_clock_div 0x00012c0c Section 0 drv_crgu.o(i.drv_crgu_set_clock_div) + i.drv_crgu_set_dpi_clk 0x00012c1c Section 0 drv_crgu.o(i.drv_crgu_set_dpi_clk) + i.drv_crgu_set_dsc_clk 0x00012c58 Section 0 drv_crgu.o(i.drv_crgu_set_dsc_clk) + i.drv_crgu_set_fb_clk 0x00012c90 Section 0 drv_crgu.o(i.drv_crgu_set_fb_clk) + i.drv_crgu_set_lcdc_clk 0x00012cb8 Section 0 drv_crgu.o(i.drv_crgu_set_lcdc_clk) + i.drv_crgu_set_reset 0x00012ce0 Section 0 drv_crgu.o(i.drv_crgu_set_reset) + i.drv_crgu_set_rxbr_clk 0x00012cf8 Section 0 drv_crgu.o(i.drv_crgu_set_rxbr_clk) + i.drv_crgu_set_vidc_clk 0x00012d20 Section 0 drv_crgu.o(i.drv_crgu_set_vidc_clk) + i.drv_dma_clear_status 0x00012d48 Section 0 drv_dma.o(i.drv_dma_clear_status) + i.drv_dma_get_int_source 0x00012d60 Section 0 drv_dma.o(i.drv_dma_get_int_source) + drv_dma_get_int_source 0x00012d61 Thumb Code 16 drv_dma.o(i.drv_dma_get_int_source) + i.drv_dsc_dec_disable 0x00012d74 Section 0 drv_dsc_dec.o(i.drv_dsc_dec_disable) + i.drv_dsc_dec_enable 0x00012d90 Section 0 drv_dsc_dec.o(i.drv_dsc_dec_enable) + i.drv_dsc_dec_get_nslc 0x00012dc8 Section 0 drv_dsc_dec.o(i.drv_dsc_dec_get_nslc) + i.drv_dsc_dec_set_irqen 0x00012de8 Section 0 drv_dsc_dec.o(i.drv_dsc_dec_set_irqen) + i.drv_dsi_rx_calc_ipi_tx_delay 0x00012e04 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) + i.drv_dsi_rx_enable_irq 0x00012f10 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) + i.drv_dsi_rx_get_color_bpp 0x00012f50 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp) + drv_dsi_rx_get_color_bpp 0x00012f51 Thumb Code 62 drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp) + i.drv_dsi_rx_get_color_pcc 0x00012fa0 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_color_pcc) + drv_dsi_rx_get_color_pcc 0x00012fa1 Thumb Code 24 drv_dsi_rx.o(i.drv_dsi_rx_get_color_pcc) + i.drv_dsi_rx_get_compression_en 0x00012fbc Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en) + i.drv_dsi_rx_get_ddi_crc_en 0x00012fcc Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_ddi_crc_en) + i.drv_dsi_rx_get_max_ret_size 0x00012fdc Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_max_ret_size) + i.drv_dsi_rx_power_up 0x00012fe8 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_power_up) + i.drv_dsi_rx_set_check_crc 0x00013000 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_check_crc) + i.drv_dsi_rx_set_ctrl_cfg 0x0001301c Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ctrl_cfg) + i.drv_dsi_rx_set_ddi_cfg 0x00013040 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) + i.drv_dsi_rx_set_ddi_crc_en 0x00013050 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_crc_en) + i.drv_dsi_rx_set_inten 0x0001306c Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_inten) + i.drv_dsi_rx_set_ipi_cfg 0x00013078 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_cfg) + i.drv_dsi_rx_set_ipi_ycbcr_frmt 0x00013088 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_ycbcr_frmt) + i.drv_dsi_rx_set_lane_swap 0x000130a4 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_lane_swap) + i.drv_dsi_rx_set_resp_cnt 0x000130b8 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_resp_cnt) + i.drv_dsi_rx_set_tear_resp_en 0x000130dc Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_tear_resp_en) + i.drv_dsi_rx_set_up_phy 0x000130f8 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) + i.drv_dsi_rx_shut_down 0x000131f8 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_shut_down) + i.drv_dsi_tx_command_header 0x00013210 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_command_header) + i.drv_dsi_tx_command_mode_cfg 0x00013228 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg) + i.drv_dsi_tx_command_put_payload 0x00013280 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) + i.drv_dsi_tx_config_eotp 0x0001328c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_config_eotp) + i.drv_dsi_tx_config_int 0x000132ac Section 0 drv_dsi_tx.o(i.drv_dsi_tx_config_int) + i.drv_dsi_tx_dpi_lpcmd_time 0x000132b8 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_dpi_lpcmd_time) + i.drv_dsi_tx_dpi_mode 0x000132c8 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_dpi_mode) + i.drv_dsi_tx_dpi_polarity 0x000132d8 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_dpi_polarity) + i.drv_dsi_tx_edpi_cmd_size 0x000132fc Section 0 drv_dsi_tx.o(i.drv_dsi_tx_edpi_cmd_size) + i.drv_dsi_tx_get_cmd_status 0x00013308 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) + i.drv_dsi_tx_mode 0x00013314 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_mode) + i.drv_dsi_tx_phy_clock_lane_auto_lp 0x00013320 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp) + i.drv_dsi_tx_phy_clock_lane_req_hs 0x0001333c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs) + i.drv_dsi_tx_phy_lane_mode 0x0001335c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_lane_mode) + i.drv_dsi_tx_phy_status_ready 0x0001336c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready) + i.drv_dsi_tx_phy_status_stopstate 0x000133d4 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) + i.drv_dsi_tx_phy_test_setup 0x00013418 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) + i.drv_dsi_tx_phy_time_cfg 0x00013568 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg) + i.drv_dsi_tx_powerup 0x00013588 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_powerup) + i.drv_dsi_tx_response_mode 0x00013594 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_response_mode) + i.drv_dsi_tx_set_bta_ack 0x000135b8 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_bta_ack) + i.drv_dsi_tx_set_esc_div 0x000135d4 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) + i.drv_dsi_tx_set_int 0x000135e8 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_int) + i.drv_dsi_tx_set_time_out_div 0x00013628 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_time_out_div) + i.drv_dsi_tx_set_video_chunk 0x00013640 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_video_chunk) + i.drv_dsi_tx_set_video_timing 0x00013654 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_video_timing) + i.drv_dsi_tx_shutdown 0x00013678 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_shutdown) + i.drv_dsi_tx_timeout_cfg 0x00013684 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_timeout_cfg) + i.drv_dsi_tx_video_mode_cfg 0x000136b0 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_cfg) + i.drv_efuse_enter_inactive 0x00013798 Section 0 drv_efuse.o(i.drv_efuse_enter_inactive) + i.drv_efuse_int_enable 0x000137ce Section 0 drv_efuse.o(i.drv_efuse_int_enable) + i.drv_efuse_read 0x000137da Section 0 drv_efuse.o(i.drv_efuse_read) + i.drv_efuse_read_req 0x00013814 Section 0 drv_efuse.o(i.drv_efuse_read_req) + i.drv_gpio_handle_int 0x0001382c Section 0 drv_gpio.o(i.drv_gpio_handle_int) + drv_gpio_handle_int 0x0001382d Thumb Code 30 drv_gpio.o(i.drv_gpio_handle_int) + i.drv_gpio_register_ap_reset_callback 0x00013850 Section 0 drv_gpio.o(i.drv_gpio_register_ap_reset_callback) + i.drv_gpio_register_callback 0x0001385c Section 0 drv_gpio.o(i.drv_gpio_register_callback) + i.drv_gpio_set_int 0x00013870 Section 0 drv_gpio.o(i.drv_gpio_set_int) + i.drv_gpio_set_ioe 0x000138b4 Section 0 drv_gpio.o(i.drv_gpio_set_ioe) + i.drv_gpio_set_mode 0x000138d4 Section 0 drv_gpio.o(i.drv_gpio_set_mode) + i.drv_gpio_set_output_data 0x000138e8 Section 0 hal_gpio.o(i.drv_gpio_set_output_data) + drv_gpio_set_output_data 0x000138e9 Thumb Code 26 hal_gpio.o(i.drv_gpio_set_output_data) + i.drv_lcdc_bcsa_config 0x00013908 Section 0 drv_lcdc.o(i.drv_lcdc_bcsa_config) + i.drv_lcdc_cfg_int_frame 0x00013930 Section 0 drv_lcdc.o(i.drv_lcdc_cfg_int_frame) + i.drv_lcdc_clear_int 0x0001395c Section 0 drv_lcdc.o(i.drv_lcdc_clear_int) + drv_lcdc_clear_int 0x0001395d Thumb Code 20 drv_lcdc.o(i.drv_lcdc_clear_int) + i.drv_lcdc_cmd_start 0x00013974 Section 0 drv_lcdc.o(i.drv_lcdc_cmd_start) + i.drv_lcdc_config_acc_command_mode 0x000139a8 Section 0 drv_lcdc.o(i.drv_lcdc_config_acc_command_mode) + i.drv_lcdc_config_int 0x000139bc Section 0 drv_lcdc.o(i.drv_lcdc_config_int) + i.drv_lcdc_config_int_single 0x000139f4 Section 0 drv_lcdc.o(i.drv_lcdc_config_int_single) + i.drv_lcdc_config_overwrite_rgb 0x00013a1c Section 0 drv_lcdc.o(i.drv_lcdc_config_overwrite_rgb) + i.drv_lcdc_config_src_parameter 0x00013a34 Section 0 drv_lcdc.o(i.drv_lcdc_config_src_parameter) + i.drv_lcdc_crop_hact 0x00013a84 Section 0 drv_lcdc.o(i.drv_lcdc_crop_hact) + i.drv_lcdc_ctrl_flow 0x00013a94 Section 0 drv_lcdc.o(i.drv_lcdc_ctrl_flow) + i.drv_lcdc_dith_config 0x00013acc Section 0 drv_lcdc.o(i.drv_lcdc_dith_config) + i.drv_lcdc_edge_dect_config 0x00013afc Section 0 drv_lcdc.o(i.drv_lcdc_edge_dect_config) + i.drv_lcdc_edge_enh_config 0x00013b38 Section 0 drv_lcdc.o(i.drv_lcdc_edge_enh_config) + i.drv_lcdc_enable_shadow_reg 0x00013b9c Section 0 drv_lcdc.o(i.drv_lcdc_enable_shadow_reg) + i.drv_lcdc_endianness_config 0x00013bc0 Section 0 drv_lcdc.o(i.drv_lcdc_endianness_config) + i.drv_lcdc_fc_config 0x00013bdc Section 0 drv_lcdc.o(i.drv_lcdc_fc_config) + i.drv_lcdc_fldc_config 0x00013bfc Section 0 drv_lcdc.o(i.drv_lcdc_fldc_config) + i.drv_lcdc_function_disable 0x00013c20 Section 0 drv_lcdc.o(i.drv_lcdc_function_disable) + i.drv_lcdc_function_enable 0x00013c44 Section 0 drv_lcdc.o(i.drv_lcdc_function_enable) + i.drv_lcdc_set_int 0x00013c68 Section 0 drv_lcdc.o(i.drv_lcdc_set_int) + i.drv_lcdc_set_prefetch 0x00013ca4 Section 0 drv_lcdc.o(i.drv_lcdc_set_prefetch) + i.drv_lcdc_set_tear_line 0x00013cc0 Section 0 drv_lcdc.o(i.drv_lcdc_set_tear_line) + i.drv_lcdc_stop_display 0x00013cdc Section 0 drv_lcdc.o(i.drv_lcdc_stop_display) + i.drv_lcdc_vid_hw_start 0x00013cec Section 0 drv_lcdc.o(i.drv_lcdc_vid_hw_start) + i.drv_lcdc_vintp_mode_config 0x00013d28 Section 0 drv_lcdc.o(i.drv_lcdc_vintp_mode_config) + i.drv_memc_clear_status 0x00013d40 Section 0 drv_memc.o(i.drv_memc_clear_status) + i.drv_memc_enable_irq 0x00013d54 Section 0 drv_memc.o(i.drv_memc_enable_irq) + i.drv_memc_gen_a_tear_signal 0x00013d94 Section 0 drv_memc.o(i.drv_memc_gen_a_tear_signal) + i.drv_memc_get_status 0x00013da4 Section 0 drv_memc.o(i.drv_memc_get_status) + i.drv_memc_get_tear_mode 0x00013dbc Section 0 drv_memc.o(i.drv_memc_get_tear_mode) + i.drv_memc_rate_transfer_sel 0x00013dcc Section 0 drv_memc.o(i.drv_memc_rate_transfer_sel) + i.drv_memc_sel_vsync 0x00013de8 Section 0 drv_memc.o(i.drv_memc_sel_vsync) + i.drv_memc_set_active_height 0x00013dfc Section 0 drv_memc.o(i.drv_memc_set_active_height) + i.drv_memc_set_circ_mode_enable 0x00013e14 Section 0 drv_memc.o(i.drv_memc_set_circ_mode_enable) + i.drv_memc_set_data_mode 0x00013e30 Section 0 drv_memc.o(i.drv_memc_set_data_mode) + i.drv_memc_set_double_buffer 0x00013e44 Section 0 drv_memc.o(i.drv_memc_set_double_buffer) + i.drv_memc_set_frame_drop_select 0x00013e5c Section 0 drv_memc.o(i.drv_memc_set_frame_drop_select) + i.drv_memc_set_fs_en_conditions 0x00013e78 Section 0 drv_memc.o(i.drv_memc_set_fs_en_conditions) + i.drv_memc_set_lcdc_st_conditions 0x00013e90 Section 0 drv_memc.o(i.drv_memc_set_lcdc_st_conditions) + i.drv_memc_set_ltpo_mode 0x00013eac Section 0 drv_memc.o(i.drv_memc_set_ltpo_mode) + i.drv_memc_set_ltpo_pu_thres 0x00013ecc Section 0 drv_memc.o(i.drv_memc_set_ltpo_pu_thres) + i.drv_memc_set_tear_mode 0x00013ee4 Section 0 drv_memc.o(i.drv_memc_set_tear_mode) + i.drv_memc_set_tear_waveform 0x00013ef8 Section 0 drv_memc.o(i.drv_memc_set_tear_waveform) + i.drv_memc_set_vidc_sync_cnt 0x00013f24 Section 0 drv_memc.o(i.drv_memc_set_vidc_sync_cnt) + i.drv_phy_test_clear 0x00013f38 Section 0 drv_phy_common.o(i.drv_phy_test_clear) + i.drv_phy_test_lock 0x00013f48 Section 0 drv_phy_common.o(i.drv_phy_test_lock) + i.drv_pwr_efuse_pd 0x00013f60 Section 0 drv_pwr.o(i.drv_pwr_efuse_pd) + i.drv_pwr_enter_deep_sleep_mode 0x00013f90 Section 0 drv_pwr.o(i.drv_pwr_enter_deep_sleep_mode) + i.drv_pwr_enter_sleep_mode_ex 0x00013fdc Section 0 drv_pwr.o(i.drv_pwr_enter_sleep_mode_ex) + i.drv_pwr_enter_stop_sleep_mode 0x00014010 Section 0 drv_pwr.o(i.drv_pwr_enter_stop_sleep_mode) + i.drv_pwr_exit_sleep_mode 0x000140a8 Section 0 drv_pwr.o(i.drv_pwr_exit_sleep_mode) + i.drv_pwr_get_power_ready_st 0x000140d0 Section 0 drv_pwr.o(i.drv_pwr_get_power_ready_st) + i.drv_pwr_set_breath_screen_power_sel 0x000140e0 Section 0 drv_pwr.o(i.drv_pwr_set_breath_screen_power_sel) + i.drv_pwr_set_digit_power_sel 0x00014108 Section 0 drv_pwr.o(i.drv_pwr_set_digit_power_sel) + i.drv_pwr_set_pll_clk 0x00014130 Section 0 drv_pwr.o(i.drv_pwr_set_pll_clk) + i.drv_pwr_set_wakeup_type 0x00014164 Section 0 drv_pwr.o(i.drv_pwr_set_wakeup_type) + i.drv_pwr_write_lock 0x00014190 Section 0 drv_pwr.o(i.drv_pwr_write_lock) + i.drv_rxbr_clear_pkt_buffer 0x000141b0 Section 0 drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) + i.drv_rxbr_clear_status0 0x000141c0 Section 0 drv_rxbr.o(i.drv_rxbr_clear_status0) + i.drv_rxbr_enable_irq 0x000141cc Section 0 drv_rxbr.o(i.drv_rxbr_enable_irq) + i.drv_rxbr_frame_drop_cfg 0x00014228 Section 0 drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) + i.drv_rxbr_get_int_source 0x00014244 Section 0 hal_internal_vsync.o(i.drv_rxbr_get_int_source) + drv_rxbr_get_int_source 0x00014245 Thumb Code 20 hal_internal_vsync.o(i.drv_rxbr_get_int_source) + i.drv_rxbr_get_status0 0x0001425c Section 0 hal_internal_dcs.o(i.drv_rxbr_get_status0) + drv_rxbr_get_status0 0x0001425d Thumb Code 20 hal_internal_dcs.o(i.drv_rxbr_get_status0) + i.drv_rxbr_hline_rcv1_cfg 0x00014274 Section 0 drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg) + i.drv_rxbr_hline_rcv_cfg 0x00014288 Section 0 drv_rxbr.o(i.drv_rxbr_hline_rcv_cfg) + i.drv_rxbr_register_irq1_callback 0x00014298 Section 0 drv_rxbr.o(i.drv_rxbr_register_irq1_callback) + i.drv_rxbr_set_ack_pkt_header 0x000142a4 Section 0 drv_rxbr.o(i.drv_rxbr_set_ack_pkt_header) + i.drv_rxbr_set_color_format 0x000142bc Section 0 drv_rxbr.o(i.drv_rxbr_set_color_format) + i.drv_rxbr_set_filter_regs 0x000142d8 Section 0 drv_rxbr.o(i.drv_rxbr_set_filter_regs) + i.drv_rxbr_set_inten 0x000142fc Section 0 drv_rxbr.o(i.drv_rxbr_set_inten) + i.drv_rxbr_set_ltpo_drop_th 0x00014318 Section 0 drv_rxbr.o(i.drv_rxbr_set_ltpo_drop_th) + i.drv_rxbr_set_usr_cfg 0x00014330 Section 0 drv_rxbr.o(i.drv_rxbr_set_usr_cfg) + i.drv_rxbr_set_usr_col 0x00014370 Section 0 drv_rxbr.o(i.drv_rxbr_set_usr_col) + i.drv_rxbr_set_usr_row 0x00014380 Section 0 drv_rxbr.o(i.drv_rxbr_set_usr_row) + i.drv_se_init 0x00014390 Section 0 drv_se.o(i.drv_se_init) + i.drv_se_set_dsc 0x00014408 Section 0 drv_se.o(i.drv_se_set_dsc) + i.drv_se_set_lcdc 0x000144dc Section 0 drv_se.o(i.drv_se_set_lcdc) + i.drv_se_set_memc 0x00014564 Section 0 drv_se.o(i.drv_se_set_memc) + i.drv_se_set_rxbr 0x000145f4 Section 0 drv_se.o(i.drv_se_set_rxbr) + i.drv_se_set_vidc 0x000146c4 Section 0 drv_se.o(i.drv_se_set_vidc) + i.drv_se_start_rx 0x00014770 Section 0 drv_se.o(i.drv_se_start_rx) + i.drv_swire_enable 0x00014784 Section 0 drv_swire.o(i.drv_swire_enable) + i.drv_swire_get_pulse_count 0x000147a0 Section 0 drv_swire.o(i.drv_swire_get_pulse_count) + i.drv_swire_register_callback 0x000147ac Section 0 drv_swire.o(i.drv_swire_register_callback) + i.drv_swire_set_bit_time 0x000147b8 Section 0 drv_swire.o(i.drv_swire_set_bit_time) + i.drv_swire_set_int 0x000147d0 Section 0 drv_swire.o(i.drv_swire_set_int) + i.drv_swire_set_power_down 0x00014818 Section 0 drv_swire.o(i.drv_swire_set_power_down) + i.drv_swire_set_pulse_count 0x00014834 Section 0 drv_swire.o(i.drv_swire_set_pulse_count) + i.drv_swire_set_trig_mode 0x00014840 Section 0 drv_swire.o(i.drv_swire_set_trig_mode) + i.drv_sys_cfg_clear_all_int 0x0001485c Section 0 drv_sys_cfg.o(i.drv_sys_cfg_clear_all_int) + i.drv_sys_cfg_clear_pending 0x00014868 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) + i.drv_sys_cfg_sel_ap_rst_trig 0x00014890 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_trig) + i.drv_sys_cfg_sel_gpio_group 0x000148b4 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_sel_gpio_group) + i.drv_sys_cfg_sel_int_trig 0x000148d8 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_sel_int_trig) + i.drv_sys_cfg_sel_swire_timer 0x000148fc Section 0 drv_sys_cfg.o(i.drv_sys_cfg_sel_swire_timer) + i.drv_sys_cfg_set_int 0x00014914 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_set_int) + i.drv_timer_clear_status_flags 0x00014938 Section 0 drv_timer.o(i.drv_timer_clear_status_flags) + drv_timer_clear_status_flags 0x00014939 Thumb Code 26 drv_timer.o(i.drv_timer_clear_status_flags) + i.drv_timer_enable 0x00014952 Section 0 drv_timer.o(i.drv_timer_enable) + i.drv_timer_get_instance 0x00014974 Section 0 drv_timer.o(i.drv_timer_get_instance) + i.drv_timer_handle_interrupt 0x00014984 Section 0 drv_timer.o(i.drv_timer_handle_interrupt) + drv_timer_handle_interrupt 0x00014985 Thumb Code 54 drv_timer.o(i.drv_timer_handle_interrupt) + i.drv_timer_set_compare_val 0x000149c0 Section 0 drv_timer.o(i.drv_timer_set_compare_val) + i.drv_timer_set_int 0x00014a00 Section 0 drv_timer.o(i.drv_timer_set_int) + i.drv_timer_set_prescaler 0x00014a48 Section 0 drv_timer.o(i.drv_timer_set_prescaler) + i.drv_timer_set_repeat 0x00014a70 Section 0 drv_timer.o(i.drv_timer_set_repeat) + i.drv_tx_phy_test_enter 0x00014a80 Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_enter) + i.drv_tx_phy_test_exit 0x00014aa0 Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_exit) + i.drv_tx_phy_test_write_code 0x00014ac0 Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_write_code) + i.drv_uart_abort_recv 0x00014ae8 Section 0 drv_uart.o(i.drv_uart_abort_recv) + i.drv_uart_abort_send 0x00014b1c Section 0 drv_uart.o(i.drv_uart_abort_send) + i.drv_uart_config_int 0x00014b50 Section 0 drv_uart.o(i.drv_uart_config_int) + i.drv_uart_enable_clk 0x00014b64 Section 0 drv_uart.o(i.drv_uart_enable_clk) + drv_uart_enable_clk 0x00014b65 Thumb Code 24 drv_uart.o(i.drv_uart_enable_clk) + i.drv_uart_enable_int 0x00014b7c Section 0 drv_uart.o(i.drv_uart_enable_int) + i.drv_uart_get_instance 0x00014bd8 Section 0 drv_uart.o(i.drv_uart_get_instance) + i.drv_uart_init 0x00014c00 Section 0 drv_uart.o(i.drv_uart_init) + i.drv_uart_int_trans_handle 0x00014cd0 Section 0 drv_uart.o(i.drv_uart_int_trans_handle) + drv_uart_int_trans_handle 0x00014cd1 Thumb Code 54 drv_uart.o(i.drv_uart_int_trans_handle) + i.drv_uart_reset_rx_fifo 0x00014d0c Section 0 drv_uart.o(i.drv_uart_reset_rx_fifo) + i.drv_uart_reset_tx_fifo 0x00014d28 Section 0 drv_uart.o(i.drv_uart_reset_tx_fifo) + i.drv_uart_send_blocking 0x00014d44 Section 0 drv_uart.o(i.drv_uart_send_blocking) + i.drv_uart_set_baud_rate 0x00014d5e Section 0 drv_uart.o(i.drv_uart_set_baud_rate) + i.drv_uart_trans_create_handle 0x00014db4 Section 0 drv_uart.o(i.drv_uart_trans_create_handle) + i.drv_vidc_clear_irq 0x00014e00 Section 0 drv_vidc.o(i.drv_vidc_clear_irq) + i.drv_vidc_enable 0x00014e10 Section 0 drv_vidc.o(i.drv_vidc_enable) + i.drv_vidc_enable_irq 0x00014e30 Section 0 drv_vidc.o(i.drv_vidc_enable_irq) + i.drv_vidc_get_int_source 0x00014e70 Section 0 drv_vidc.o(i.drv_vidc_get_int_source) + i.drv_vidc_get_irq_status 0x00014e9c Section 0 drv_vidc.o(i.drv_vidc_get_irq_status) + i.drv_vidc_init_module_enable 0x00014eb4 Section 0 drv_vidc.o(i.drv_vidc_init_module_enable) + i.drv_vidc_register_callback 0x00014ee0 Section 0 drv_vidc.o(i.drv_vidc_register_callback) + i.drv_vidc_reset 0x00014eec Section 0 drv_vidc.o(i.drv_vidc_reset) + i.drv_vidc_set_circ_mode_enable 0x00014ef8 Section 0 drv_vidc.o(i.drv_vidc_set_circ_mode_enable) + i.drv_vidc_set_dither_config 0x00014f14 Section 0 drv_vidc.o(i.drv_vidc_set_dither_config) + i.drv_vidc_set_dst_parameter 0x00014f4c Section 0 drv_vidc.o(i.drv_vidc_set_dst_parameter) + i.drv_vidc_set_honly_hcoef0 0x00014fa8 Section 0 drv_vidc.o(i.drv_vidc_set_honly_hcoef0) + i.drv_vidc_set_honly_hinitb 0x00014fb4 Section 0 drv_vidc.o(i.drv_vidc_set_honly_hinitb) + i.drv_vidc_set_honly_hinitr 0x00014fe0 Section 0 drv_vidc.o(i.drv_vidc_set_honly_hinitr) + i.drv_vidc_set_irqen 0x00015010 Section 0 drv_vidc.o(i.drv_vidc_set_irqen) + i.drv_vidc_set_mirror 0x0001502c Section 0 drv_vidc.o(i.drv_vidc_set_mirror) + i.drv_vidc_set_pentile_swap 0x00015040 Section 0 drv_vidc.o(i.drv_vidc_set_pentile_swap) + i.drv_vidc_set_pu_ctrl 0x0001505c Section 0 drv_vidc.o(i.drv_vidc_set_pu_ctrl) + i.drv_vidc_set_rotation 0x00015068 Section 0 drv_vidc.o(i.drv_vidc_set_rotation) + i.drv_vidc_set_scld_hcoef0 0x00015080 Section 0 drv_vidc.o(i.drv_vidc_set_scld_hcoef0) + i.drv_vidc_set_scld_hcoef1 0x0001508c Section 0 drv_vidc.o(i.drv_vidc_set_scld_hcoef1) + i.drv_vidc_set_scld_step 0x00015098 Section 0 drv_vidc.o(i.drv_vidc_set_scld_step) + i.drv_vidc_set_scld_vcoef0 0x000150ac Section 0 drv_vidc.o(i.drv_vidc_set_scld_vcoef0) + i.drv_vidc_set_scld_vcoef1 0x000150b8 Section 0 drv_vidc.o(i.drv_vidc_set_scld_vcoef1) + i.drv_vidc_set_src_parameter 0x000150c4 Section 0 drv_vidc.o(i.drv_vidc_set_src_parameter) + i.drv_vidc_set_vintp_config 0x000150e4 Section 0 drv_vidc.o(i.drv_vidc_set_vintp_config) + i.fputc 0x0001511c Section 0 tau_log.o(i.fputc) + i.google_p8p_demo 0x00015150 Section 0 p8p_demo.o(i.google_p8p_demo) + i.ha_intl_fb_check_pu_size 0x000151b0 Section 0 hal_internal_fb.o(i.ha_intl_fb_check_pu_size) + ha_intl_fb_check_pu_size 0x000151b1 Thumb Code 58 hal_internal_fb.o(i.ha_intl_fb_check_pu_size) + i.hal_dsi_rx_ctrl_create_handle 0x000151f0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) + i.hal_dsi_rx_ctrl_dcs_async_handler 0x00015230 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) + i.hal_dsi_rx_ctrl_deinit 0x00015270 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) + i.hal_dsi_rx_ctrl_get_max_ret_size 0x00015304 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) + i.hal_dsi_rx_ctrl_init 0x00015324 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) + i.hal_dsi_rx_ctrl_init_clk 0x000153d0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) + hal_dsi_rx_ctrl_init_clk 0x000153d1 Thumb Code 222 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) + i.hal_dsi_rx_ctrl_init_dsi_rx 0x000154d0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) + hal_dsi_rx_ctrl_init_dsi_rx 0x000154d1 Thumb Code 218 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) + i.hal_dsi_rx_ctrl_init_memc 0x000155c8 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) + hal_dsi_rx_ctrl_init_memc 0x000155c9 Thumb Code 294 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) + i.hal_dsi_rx_ctrl_init_rxbr 0x000156f4 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) + hal_dsi_rx_ctrl_init_rxbr 0x000156f5 Thumb Code 314 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) + i.hal_dsi_rx_ctrl_init_vidc 0x0001583c Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) + hal_dsi_rx_ctrl_init_vidc 0x0001583d Thumb Code 624 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) + i.hal_dsi_rx_ctrl_pre_init_pps 0x00015abc Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) + i.hal_dsi_rx_ctrl_send_ack_cmd 0x00015af4 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) + i.hal_dsi_rx_ctrl_set_ipi_cfg 0x00015be4 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) + hal_dsi_rx_ctrl_set_ipi_cfg 0x00015be5 Thumb Code 48 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) + i.hal_dsi_rx_ctrl_start 0x00015c14 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) + i.hal_dsi_rx_ctrl_stop 0x00015c44 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) + i.hal_dsi_rx_ctrl_toggle_resolution 0x00015c74 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) + i.hal_dsi_tx_cmd_mode_cal_timing 0x00015c94 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) + hal_dsi_tx_cmd_mode_cal_timing 0x00015c95 Thumb Code 506 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) + i.hal_dsi_tx_ctrl_create_handle 0x00015f10 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) + i.hal_dsi_tx_ctrl_deinit 0x00015f48 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) + i.hal_dsi_tx_ctrl_gen_a_tear_signal 0x00015fbc Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) + i.hal_dsi_tx_ctrl_init 0x00015fe0 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) + i.hal_dsi_tx_ctrl_init_clk 0x0001605c Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) + hal_dsi_tx_ctrl_init_clk 0x0001605d Thumb Code 12 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) + i.hal_dsi_tx_ctrl_set_overwrite_rgb 0x0001606c Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb) + i.hal_dsi_tx_ctrl_set_tear_mode 0x00016074 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) + i.hal_dsi_tx_ctrl_start 0x00016080 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) + i.hal_dsi_tx_ctrl_stop 0x000160fc Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) + i.hal_dsi_tx_ctrl_write_array_cmd 0x00016134 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) + i.hal_dsi_tx_ctrl_write_cmd 0x00016228 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) + i.hal_dsi_tx_init_cfg 0x000162f8 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) + hal_dsi_tx_init_cfg 0x000162f9 Thumb Code 258 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) + i.hal_dsi_tx_init_dpi_timing 0x00016404 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) + hal_dsi_tx_init_dpi_timing 0x00016405 Thumb Code 46 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) + i.hal_dsi_tx_init_phy_cfg 0x0001643c Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) + hal_dsi_tx_init_phy_cfg 0x0001643d Thumb Code 22 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) + i.hal_dsi_tx_init_timing 0x00016452 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) + hal_dsi_tx_init_timing 0x00016453 Thumb Code 82 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) + i.hal_dsi_tx_init_vid_timing 0x000164a4 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_vid_timing) + hal_dsi_tx_init_vid_timing 0x000164a5 Thumb Code 70 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_vid_timing) + i.hal_dsi_tx_send_cmd 0x000164f8 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) + hal_dsi_tx_send_cmd 0x000164f9 Thumb Code 58 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) + i.hal_dsi_tx_timing_info_update 0x00016538 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_timing_info_update) + hal_dsi_tx_timing_info_update 0x00016539 Thumb Code 142 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_timing_info_update) + i.hal_dsi_tx_vid_mode_cal_timing 0x000165cc Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) + hal_dsi_tx_vid_mode_cal_timing 0x000165cd Thumb Code 766 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) + i.hal_gpio_config_pad 0x000168dc Section 0 hal_gpio.o(i.hal_gpio_config_pad) + i.hal_gpio_ctrl_eint 0x00016918 Section 0 hal_gpio.o(i.hal_gpio_ctrl_eint) + i.hal_gpio_init_eint 0x00016930 Section 0 hal_gpio.o(i.hal_gpio_init_eint) + i.hal_gpio_init_input 0x00016970 Section 0 hal_gpio.o(i.hal_gpio_init_input) + i.hal_gpio_init_output 0x00016986 Section 0 hal_gpio.o(i.hal_gpio_init_output) + i.hal_gpio_reg_eint_cb 0x000169a4 Section 0 hal_gpio.o(i.hal_gpio_reg_eint_cb) + i.hal_gpio_set_ap_reset_int 0x000169c0 Section 0 hal_gpio.o(i.hal_gpio_set_ap_reset_int) + i.hal_gpio_set_mode 0x00016a10 Section 0 hal_gpio.o(i.hal_gpio_set_mode) + i.hal_gpio_set_output_data 0x00016a74 Section 0 hal_gpio.o(i.hal_gpio_set_output_data) + i.hal_internal_sync_get_hight_performan_mode 0x00016a7c Section 0 hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) + i.hal_internal_sync_input_resolution_change 0x00016a8c Section 0 hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) + i.hal_internal_sync_register_lcdc_cb 0x00016c40 Section 0 hal_internal_vsync.o(i.hal_internal_sync_register_lcdc_cb) + i.hal_internal_vsync_deinit 0x00016c4c Section 0 hal_internal_vsync.o(i.hal_internal_vsync_deinit) + i.hal_internal_vsync_get_rx_state 0x00016c6c Section 0 hal_internal_vsync.o(i.hal_internal_vsync_get_rx_state) + i.hal_internal_vsync_get_sync_line 0x00016c78 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) + i.hal_internal_vsync_get_tx_state 0x00016c8c Section 0 hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) + i.hal_internal_vsync_init_rx 0x00016c98 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_init_rx) + i.hal_internal_vsync_init_tx 0x00016d70 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_init_tx) + i.hal_internal_vsync_set_rx_state 0x00016e38 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) + i.hal_internal_vsync_set_tear_mode 0x00016e58 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) + i.hal_internal_vsync_set_tx_state 0x00016f70 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) + i.hal_intl_dcs_init_sw_fltr 0x00016fdc Section 0 hal_internal_dcs.o(i.hal_intl_dcs_init_sw_fltr) + i.hal_intl_dcs_rx_get_dcs_packet_data 0x00017048 Section 0 hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) + hal_intl_dcs_rx_get_dcs_packet_data 0x00017049 Thumb Code 806 hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) + i.hal_intl_dcs_rx_receive_packet 0x00017494 Section 0 hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) + hal_intl_dcs_rx_receive_packet 0x00017495 Thumb Code 122 hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) + i.hal_intl_dcs_rx_receive_pps 0x0001751c Section 0 hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) + hal_intl_dcs_rx_receive_pps 0x0001751d Thumb Code 268 hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) + i.hal_intl_dcs_set_auto_hw_filter 0x00017690 Section 0 hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) + i.hal_intl_dcs_sw_filter_handle 0x0001771c Section 0 hal_internal_dcs.o(i.hal_intl_dcs_sw_filter_handle) + hal_intl_dcs_sw_filter_handle 0x0001771d Thumb Code 36 hal_internal_dcs.o(i.hal_intl_dcs_sw_filter_handle) + i.hal_intl_fb_cal_fb_info 0x00017748 Section 0 hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) + i.hal_intl_fb_check_bandwidth 0x00017a38 Section 0 hal_internal_fb.o(i.hal_intl_fb_check_bandwidth) + hal_intl_fb_check_bandwidth 0x00017a39 Thumb Code 92 hal_internal_fb.o(i.hal_intl_fb_check_bandwidth) + i.hal_intl_fb_edge_resize 0x00017a9c Section 0 hal_internal_fb.o(i.hal_intl_fb_edge_resize) + hal_intl_fb_edge_resize 0x00017a9d Thumb Code 214 hal_internal_fb.o(i.hal_intl_fb_edge_resize) + i.hal_intl_fb_flow_control_adapter 0x00017b78 Section 0 hal_internal_fb.o(i.hal_intl_fb_flow_control_adapter) + hal_intl_fb_flow_control_adapter 0x00017b79 Thumb Code 94 hal_internal_fb.o(i.hal_intl_fb_flow_control_adapter) + i.hal_intl_fb_get_memc_flow_mode 0x00017bdc Section 0 hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) + i.hal_intl_fb_get_rx_fb_info 0x00017be8 Section 0 hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) + i.hal_intl_fb_get_tx_fb_info 0x00017bf8 Section 0 hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info) + i.hal_intl_fb_get_user_flow 0x00017c08 Section 0 hal_internal_fb.o(i.hal_intl_fb_get_user_flow) + i.hal_intl_svs_deinit_rx 0x00017c14 Section 0 hal_internal_svs.o(i.hal_intl_svs_deinit_rx) + i.hal_intl_svs_deinit_tx 0x00017c3c Section 0 hal_internal_svs.o(i.hal_intl_svs_deinit_tx) + i.hal_intl_svs_handle 0x00017c4c Section 0 hal_internal_svs.o(i.hal_intl_svs_handle) + i.hal_intl_svs_init_rx 0x00017c70 Section 0 hal_internal_svs.o(i.hal_intl_svs_init_rx) + i.hal_intl_svs_init_tx 0x00017cf0 Section 0 hal_internal_svs.o(i.hal_intl_svs_init_tx) + i.hal_intl_svs_set_rx_vtt 0x00017d04 Section 0 hal_internal_svs.o(i.hal_intl_svs_set_rx_vtt) + i.hal_intl_svs_update_rxbr_clk 0x00017d10 Section 0 hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) + i.hal_lcdc_displayproc_config 0x00017d58 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config) + i.hal_lcdc_init_cfg 0x00017dc8 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) + hal_lcdc_init_cfg 0x00017dc9 Thumb Code 62 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) + i.hal_lcdc_init_clk 0x00017e06 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) + hal_lcdc_init_clk 0x00017e07 Thumb Code 112 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) + i.hal_lcdc_postproc_config 0x00017e78 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) + i.hal_lcdc_start 0x00017fa0 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_start) + hal_lcdc_start 0x00017fa1 Thumb Code 36 hal_dsi_tx_ctrl.o(i.hal_lcdc_start) + i.hal_lcdc_timinggen_config 0x00017fc4 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) + hal_lcdc_timinggen_config 0x00017fc5 Thumb Code 60 hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) + i.hal_lcdc_upscaler_config 0x00018000 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) + i.hal_nonshadow_func_update 0x000180e0 Section 0 hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) + i.hal_pwr_enter_deep_sleep_mode 0x0001819c Section 0 hal_pwr.o(i.hal_pwr_enter_deep_sleep_mode) + i.hal_pwr_enter_normal_sleep_mode 0x000181c6 Section 0 hal_pwr.o(i.hal_pwr_enter_normal_sleep_mode) + i.hal_pwr_enter_stop_sleep_mode 0x000181d0 Section 0 hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode) + i.hal_pwr_exit_sleep_mode 0x00018234 Section 0 hal_pwr.o(i.hal_pwr_exit_sleep_mode) + i.hal_pwr_get_vcc_power_ready 0x0001823e Section 0 hal_pwr.o(i.hal_pwr_get_vcc_power_ready) + i.hal_pwr_set_main_power 0x00018246 Section 0 hal_pwr.o(i.hal_pwr_set_main_power) + i.hal_pwr_set_sleep_mode_power 0x0001824e Section 0 hal_pwr.o(i.hal_pwr_set_sleep_mode_power) + i.hal_pwr_set_stop_sleep_wakeup_pin 0x00018258 Section 0 hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) + i.hal_swire_deinit 0x000182bc Section 0 hal_swire.o(i.hal_swire_deinit) + i.hal_swire_enable 0x000182fc Section 0 hal_swire.o(i.hal_swire_enable) + i.hal_swire_init 0x00018358 Section 0 hal_swire.o(i.hal_swire_init) + i.hal_swire_set_pulse 0x000183b0 Section 0 hal_swire.o(i.hal_swire_set_pulse) + i.hal_swire_set_timer 0x000183d4 Section 0 hal_swire.o(i.hal_swire_set_timer) + i.hal_system_init 0x00018414 Section 0 hal_system.o(i.hal_system_init) + i.hal_system_updata_sysclk 0x000184f8 Section 0 hal_system.o(i.hal_system_updata_sysclk) + i.hal_timer_deinit 0x00018548 Section 0 hal_timer.o(i.hal_timer_deinit) + i.hal_timer_init 0x00018578 Section 0 hal_timer.o(i.hal_timer_init) + i.hal_timer_set_repeat 0x00018594 Section 0 hal_timer.o(i.hal_timer_set_repeat) + i.hal_tx_frame_rate_adjust 0x0001859c Section 0 hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) + hal_tx_frame_rate_adjust 0x0001859d Thumb Code 44 hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) + i.hal_uart_init 0x000185cc Section 0 hal_uart.o(i.hal_uart_init) + i.hal_uart_send_blocking 0x00018660 Section 0 hal_uart.o(i.hal_uart_send_blocking) + i.hal_vsync_func_update 0x0001867c Section 0 hal_dsi_tx_ctrl.o(i.hal_vsync_func_update) + i.hal_vsync_reset_lcdc_scaler 0x00018694 Section 0 hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) + i.main 0x00018760 Section 0 main.o(i.main) + i.pps_update_handle 0x000187a0 Section 0 p8p_demo.o(i.pps_update_handle) + pps_update_handle 0x000187a1 Thumb Code 110 p8p_demo.o(i.pps_update_handle) + i.rxbr_irq1_callback 0x0001881c Section 0 hal_internal_vsync.o(i.rxbr_irq1_callback) + rxbr_irq1_callback 0x0001881d Thumb Code 466 hal_internal_vsync.o(i.rxbr_irq1_callback) + i.send_panel_init_code 0x00018ad4 Section 0 p8p_demo.o(i.send_panel_init_code) + send_panel_init_code 0x00018ad5 Thumb Code 58 p8p_demo.o(i.send_panel_init_code) + i.soft_double_buffer_update 0x00018b10 Section 0 hal_internal_vsync.o(i.soft_double_buffer_update) + soft_double_buffer_update 0x00018b11 Thumb Code 56 hal_internal_vsync.o(i.soft_double_buffer_update) + i.soft_gen_te 0x00018b54 Section 0 hal_internal_vsync.o(i.soft_gen_te) + soft_gen_te 0x00018b55 Thumb Code 102 hal_internal_vsync.o(i.soft_gen_te) + i.soft_gen_te_double_buffer 0x00018bd0 Section 0 hal_internal_vsync.o(i.soft_gen_te_double_buffer) + soft_gen_te_double_buffer 0x00018bd1 Thumb Code 122 hal_internal_vsync.o(i.soft_gen_te_double_buffer) + i.stop_sleep_cb 0x00018c64 Section 0 hal_pwr.o(i.stop_sleep_cb) + stop_sleep_cb 0x00018c65 Thumb Code 18 hal_pwr.o(i.stop_sleep_cb) + i.svs_direct_mode_setting 0x00018c7c Section 0 hal_internal_svs.o(i.svs_direct_mode_setting) + svs_direct_mode_setting 0x00018c7d Thumb Code 154 hal_internal_svs.o(i.svs_direct_mode_setting) + i.svs_get_rel_intv 0x00018d28 Section 0 hal_internal_svs.o(i.svs_get_rel_intv) + svs_get_rel_intv 0x00018d29 Thumb Code 20 hal_internal_svs.o(i.svs_get_rel_intv) + i.svs_sync_handle 0x00018d44 Section 0 hal_internal_svs.o(i.svs_sync_handle) + svs_sync_handle 0x00018d45 Thumb Code 158 hal_internal_svs.o(i.svs_sync_handle) + i.svs_wait_fr_stab 0x00018df4 Section 0 hal_internal_svs.o(i.svs_wait_fr_stab) + svs_wait_fr_stab 0x00018df5 Thumb Code 148 hal_internal_svs.o(i.svs_wait_fr_stab) + i.svs_wait_start 0x00018ec0 Section 0 hal_internal_svs.o(i.svs_wait_start) + svs_wait_start 0x00018ec1 Thumb Code 250 hal_internal_svs.o(i.svs_wait_start) + i.tau_log_init 0x00018fcc Section 0 tau_log.o(i.tau_log_init) + i.tau_log_printf 0x00019000 Section 0 tau_log.o(i.tau_log_printf) + i.tau_log_push_log 0x00019084 Section 0 tau_log.o(i.tau_log_push_log) + i.vidc_callback 0x000190fc Section 0 hal_internal_vsync.o(i.vidc_callback) + vidc_callback 0x000190fd Thumb Code 150 hal_internal_vsync.o(i.vidc_callback) + i.vpre_err_reset 0x000191b0 Section 0 hal_internal_vsync.o(i.vpre_err_reset) + vpre_err_reset 0x000191b1 Thumb Code 254 hal_internal_vsync.o(i.vpre_err_reset) + .constdata 0x000192c8 Section 8376 p8p_demo.o(.constdata) + g_cus_rx_dcs_execute_table 0x000192c8 Data 96 p8p_demo.o(.constdata) + .constdata 0x0001b380 Section 40 hal_dsi_rx_ctrl.o(.constdata) + .constdata 0x0001b3a8 Section 28 hal_dsi_tx_ctrl.o(.constdata) + .constdata 0x0001b3c4 Section 48 hal_uart.o(.constdata) + .constdata 0x0001b3f4 Section 16 drv_uart.o(.constdata) + .conststring 0x0001b404 Section 66 hal_dsi_rx_ctrl.o(.conststring) + .conststring 0x0001b448 Section 144 hal_internal_vsync.o(.conststring) + .conststring 0x0001b4d8 Section 142 hal_internal_dcs.o(.conststring) + .data 0x00070000 Section 287 p8p_demo.o(.data) + g_rx_ctrl_handle 0x00070000 Data 4 p8p_demo.o(.data) + g_tx_ctrl_handle 0x00070004 Data 4 p8p_demo.o(.data) + panel_display_done 0x00070008 Data 1 p8p_demo.o(.data) + sg_system_resume 0x00070009 Data 1 p8p_demo.o(.data) + sg_system_suspend 0x0007000a Data 1 p8p_demo.o(.data) + sg_exit_idle_mode_flag 0x0007000b Data 1 p8p_demo.o(.data) + g_resolution_change 0x0007000c Data 1 p8p_demo.o(.data) + pps_renew_flag 0x00070010 Data 4 p8p_demo.o(.data) + pwr_rst_flag 0x00070014 Data 4 p8p_demo.o(.data) + reg53_E8_fg 0x0007011e Data 1 p8p_demo.o(.data) + .data 0x00070120 Section 36 hal_dsi_rx_ctrl.o(.data) + g_hw_auto_filter 0x00070120 Data 1 hal_dsi_rx_ctrl.o(.data) + g_crc_check_enable 0x00070121 Data 1 hal_dsi_rx_ctrl.o(.data) + g_esc_clk 0x00070124 Data 4 hal_dsi_rx_ctrl.o(.data) + g_before_draw_col 0x00070128 Data 4 hal_dsi_rx_ctrl.o(.data) + g_before_draw_page 0x0007012c Data 4 hal_dsi_rx_ctrl.o(.data) + pre_step 0x00070130 Data 4 hal_dsi_rx_ctrl.o(.data) + pre_cmd_filter 0x00070134 Data 4 hal_dsi_rx_ctrl.o(.data) + pre_x 0x00070138 Data 4 hal_dsi_rx_ctrl.o(.data) + pre_y 0x0007013c Data 4 hal_dsi_rx_ctrl.o(.data) + pre_value 0x00070140 Data 4 hal_dsi_rx_ctrl.o(.data) + .data 0x00070144 Section 92 hal_dsi_tx_ctrl.o(.data) + sg_bta_vsync_flag 0x00070144 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_vsync_flag 0x00070145 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_enter_sleep_cmd 0x00070146 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_fldc_cg_mode 0x00070147 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_bypass_scl_fir 0x00070148 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_honly_bypass_fir 0x00070149 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_bypass_bcs 0x0007014a Data 1 hal_dsi_tx_ctrl.o(.data) + sg_bypass_enhc 0x0007014b Data 1 hal_dsi_tx_ctrl.o(.data) + sg_bypass_edge_dect 0x0007014c Data 1 hal_dsi_tx_ctrl.o(.data) + sg_bypass_edge_enh 0x0007014d Data 1 hal_dsi_tx_ctrl.o(.data) + sg_bypass_dith 0x0007014e Data 1 hal_dsi_tx_ctrl.o(.data) + sg_dith_judge 0x0007014f Data 1 hal_dsi_tx_ctrl.o(.data) + sg_endianness 0x00070150 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_test_pattern_en 0x00070151 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_dith_judge_thr 0x00070154 Data 4 hal_dsi_tx_ctrl.o(.data) + sg_ccm_para 0x00070158 Data 36 hal_dsi_tx_ctrl.o(.data) + sg_honly_para 0x0007017c Data 36 hal_dsi_tx_ctrl.o(.data) + .data 0x000701a0 Section 2 hal_swire.o(.data) + sg_swire_timer 0x000701a0 Data 1 hal_swire.o(.data) + sg_swire_repeat 0x000701a1 Data 1 hal_swire.o(.data) + .data 0x000701a4 Section 8 hal_pwr.o(.data) + sg_wake_up_io 0x000701a4 Data 1 hal_pwr.o(.data) + sg_stop_sleep_wakeup_int 0x000701a8 Data 4 hal_pwr.o(.data) + .data 0x000701ac Section 1 tau_log.o(.data) + g_log_port 0x000701ac Data 1 tau_log.o(.data) + .data 0x000701b0 Section 24 hal_uart.o(.data) + sg_dma_callback 0x000701c0 Data 4 hal_uart.o(.data) + sg_user_data 0x000701c4 Data 4 hal_uart.o(.data) + .data 0x000701c8 Section 16 hal_internal_vsync.o(.data) + s_te_refine_mode 0x000701c8 Data 1 hal_internal_vsync.o(.data) + s_double_buffer 0x000701c9 Data 1 hal_internal_vsync.o(.data) + .data 0x000701d8 Section 40 hal_internal_dcs.o(.data) + pre_nslc 0x000701d8 Data 4 hal_internal_dcs.o(.data) + g_imm_packet 0x000701dc Data 24 hal_internal_dcs.o(.data) + g_cus_rx_write_cmd_handle 0x000701f4 Data 12 hal_internal_dcs.o(.data) + .data 0x00070200 Section 12 drv_common.o(.data) + s_my_tick 0x00070200 Data 4 drv_common.o(.data) + .data 0x0007020c Section 1 drv_common.o(.data) + .data 0x00070210 Section 4 drv_gpio.o(.data) + g_ap_reset_cb 0x00070210 Data 4 drv_gpio.o(.data) + .data 0x00070214 Section 4 drv_swire.o(.data) + sg_drv_swire_cb 0x00070214 Data 4 drv_swire.o(.data) + .data 0x00070218 Section 80 drv_timer.o(.data) + sg_timer_info 0x00070218 Data 80 drv_timer.o(.data) + .data 0x00070268 Section 4 drv_se.o(.data) + chip_info 0x00070268 Data 4 drv_se.o(.data) + .data 0x0007026c Section 1 drv_dsi_rx.o(.data) + sg_rx_drv_level 0x0007026c Data 1 drv_dsi_rx.o(.data) + .data 0x00070270 Section 8 drv_rxbr.o(.data) + .data 0x00070278 Section 4 drv_vidc.o(.data) + .data 0x0007027c Section 400 drv_dma.o(.data) + sg_dma_handle 0x0007027c Data 256 drv_dma.o(.data) + .data 0x0007040c Section 4 stdout.o(.data) + .bss 0x00070410 Section 208 hal_dsi_rx_ctrl.o(.bss) + g_rx_ctrl_handle 0x00070410 Data 208 hal_dsi_rx_ctrl.o(.bss) + .bss 0x000704e0 Section 184 hal_dsi_tx_ctrl.o(.bss) + g_tx_ctrl_handle 0x000704e0 Data 92 hal_dsi_tx_ctrl.o(.bss) + sg_dsi_tx_param 0x0007053c Data 92 hal_dsi_tx_ctrl.o(.bss) + .bss 0x00070598 Section 256 tau_log.o(.bss) + g_log_buf 0x00070598 Data 256 tau_log.o(.bss) + .bss 0x00070698 Section 40 hal_internal_vsync.o(.bss) + .bss 0x000706c0 Section 2048 hal_internal_dcs.o(.bss) + .bss 0x00070ec0 Section 255 hal_internal_dcs.o(.bss) + g_imm_buffer 0x00070ec0 Data 255 hal_internal_dcs.o(.bss) + .bss 0x00070fc0 Section 68 hal_internal_fb.o(.bss) + .bss 0x00071004 Section 68 hal_internal_svs.o(.bss) + sg_sys_handler 0x00071004 Data 68 hal_internal_svs.o(.bss) + .bss 0x00071048 Section 64 drv_gpio.o(.bss) + s_gpio_cb 0x00071048 Data 64 drv_gpio.o(.bss) + .bss 0x00071088 Section 4204 dcs_packet_fifo.o(.bss) + .bss 0x000720f4 Section 16 drv_dma.o(.bss) + sg_dma_int_list 0x000720f4 Data 16 drv_dma.o(.bss) + .bss 0x00072104 Section 96 drv_uart.o(.bss) + sg_uart_userdata 0x00072104 Data 96 drv_uart.o(.bss) + STACK 0x00072168 Section 4096 startup_armcm0.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$IEEEJ$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE + _printf_a 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_c 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_charcount 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_d 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_e 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_f 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_flags 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_fp_dec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_fp_hex 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_g 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_i 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_int_dec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_l 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_lc 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_ll 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_lld 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_lli 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_llo 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_llu 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_llx 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_longlong_dec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_longlong_hex 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_longlong_oct 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_ls 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_mbtowc 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_n 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_o 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_p 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_percent 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_pre_padding 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_return_value 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_s 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_sizespec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_str 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_truncate_signed 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_truncate_unsigned 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_u 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_wc 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_wctomb 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_widthprec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_x 0x00000000 Number 0 stubs.o ABSOLUTE + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _microlib_exit - Undefined Weak Reference + __Vectors_Size 0x000000c0 Number 0 startup_armcm0.o ABSOLUTE + __Vectors 0x00010000 Data 4 startup_armcm0.o(RESET) + __Vectors_End 0x000100c0 Data 0 startup_armcm0.o(RESET) + __main 0x000100c1 Thumb Code 0 entry.o(.ARM.Collect$$$$00000000) + _main_stk 0x000100c1 Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001) + _main_scatterload 0x000100c5 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + __main_after_scatterload 0x000100c9 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + _main_clock 0x000100c9 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008) + _main_cpp_init 0x000100c9 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A) + _main_init 0x000100c9 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B) + __rt_final_cpp 0x000100d1 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000D) + __rt_final_exit 0x000100d1 Thumb Code 0 entry11a.o(.ARM.Collect$$$$0000000F) + Reset_Handler 0x000100d5 Thumb Code 28 startup_armcm0.o(.text) + NMI_Handler 0x000100f1 Thumb Code 2 startup_armcm0.o(.text) + SVC_Handler 0x000100f5 Thumb Code 2 startup_armcm0.o(.text) + PendSV_Handler 0x000100f7 Thumb Code 2 startup_armcm0.o(.text) + FLSCTRL_IRQn_Handler 0x00010107 Thumb Code 2 startup_armcm0.o(.text) + WDG_IRQn_Handler 0x00010113 Thumb Code 2 startup_armcm0.o(.text) + I2C0_IRQn_Handler 0x00010117 Thumb Code 2 startup_armcm0.o(.text) + I2C1_IRQn_Handler 0x00010119 Thumb Code 2 startup_armcm0.o(.text) + SPIS_IRQn_Handler 0x0001011b Thumb Code 2 startup_armcm0.o(.text) + SPIM_IRQn_Handler 0x0001011d Thumb Code 2 startup_armcm0.o(.text) + I2C2_IRQn_Handler 0x00010121 Thumb Code 2 startup_armcm0.o(.text) + OTP_IRQn_Handler 0x00010123 Thumb Code 2 startup_armcm0.o(.text) + PVD_IRQn_Handler 0x00010127 Thumb Code 2 startup_armcm0.o(.text) + __aeabi_uidiv 0x0001014d Thumb Code 0 uidiv.o(.text) + __aeabi_uidivmod 0x0001014d Thumb Code 44 uidiv.o(.text) + __aeabi_idiv 0x00010179 Thumb Code 0 idiv.o(.text) + __aeabi_idivmod 0x00010179 Thumb Code 40 idiv.o(.text) + __aeabi_memcpy 0x000101a1 Thumb Code 36 memcpya.o(.text) + __aeabi_memcpy4 0x000101a1 Thumb Code 0 memcpya.o(.text) + __aeabi_memcpy8 0x000101a1 Thumb Code 0 memcpya.o(.text) + __aeabi_memset 0x000101c5 Thumb Code 14 memseta.o(.text) + __aeabi_memset4 0x000101c5 Thumb Code 0 memseta.o(.text) + __aeabi_memset8 0x000101c5 Thumb Code 0 memseta.o(.text) + __aeabi_memclr 0x000101d3 Thumb Code 4 memseta.o(.text) + __aeabi_memclr4 0x000101d3 Thumb Code 0 memseta.o(.text) + __aeabi_memclr8 0x000101d3 Thumb Code 0 memseta.o(.text) + _memset$wrapper 0x000101d7 Thumb Code 18 memseta.o(.text) + strlen 0x000101e9 Thumb Code 14 strlen.o(.text) + __aeabi_fadd 0x000101f7 Thumb Code 162 fadd.o(.text) + __aeabi_fsub 0x00010299 Thumb Code 8 fadd.o(.text) + __aeabi_frsub 0x000102a1 Thumb Code 8 fadd.o(.text) + __aeabi_fmul 0x000102a9 Thumb Code 122 fmul.o(.text) + __aeabi_fdiv 0x00010323 Thumb Code 124 fdiv.o(.text) + __ARM_scalbnf 0x0001039f Thumb Code 24 fscalb.o(.text) + scalbnf 0x0001039f Thumb Code 0 fscalb.o(.text) + __aeabi_dadd 0x000103b9 Thumb Code 328 dadd.o(.text) + __aeabi_dsub 0x00010501 Thumb Code 12 dadd.o(.text) + __aeabi_drsub 0x0001050d Thumb Code 12 dadd.o(.text) + __aeabi_dmul 0x0001051d Thumb Code 202 dmul.o(.text) + __aeabi_ui2f 0x000105ed Thumb Code 14 ffltui.o(.text) + __aeabi_ui2d 0x000105fd Thumb Code 24 dfltui.o(.text) + __aeabi_f2uiz 0x00010619 Thumb Code 40 ffixui.o(.text) + __aeabi_d2uiz 0x00010641 Thumb Code 50 dfixui.o(.text) + __aeabi_f2d 0x0001067d Thumb Code 40 f2d.o(.text) + __aeabi_d2f 0x000106a5 Thumb Code 56 d2f.o(.text) + __aeabi_cfcmpeq 0x000106dd Thumb Code 0 cfcmple.o(.text) + __aeabi_cfcmple 0x000106dd Thumb Code 20 cfcmple.o(.text) + __aeabi_cfrcmple 0x000106f1 Thumb Code 20 cfrcmple.o(.text) + __aeabi_uldivmod 0x00010705 Thumb Code 96 uldiv.o(.text) + __aeabi_llsl 0x00010765 Thumb Code 32 llshl.o(.text) + _ll_shift_l 0x00010765 Thumb Code 0 llshl.o(.text) + __aeabi_llsr 0x00010785 Thumb Code 34 llushr.o(.text) + _ll_ushift_r 0x00010785 Thumb Code 0 llushr.o(.text) + __aeabi_lasr 0x000107a7 Thumb Code 38 llsshr.o(.text) + _ll_sshift_r 0x000107a7 Thumb Code 0 llsshr.o(.text) + __I$use$fp 0x000107cd Thumb Code 0 iusefp.o(.text) + _float_round 0x000107cd Thumb Code 16 fepilogue.o(.text) + _float_epilogue 0x000107dd Thumb Code 114 fepilogue.o(.text) + _double_round 0x0001084f Thumb Code 26 depilogue.o(.text) + _double_epilogue 0x00010869 Thumb Code 164 depilogue.o(.text) + __aeabi_ddiv 0x0001090d Thumb Code 234 ddiv.o(.text) + __aeabi_d2ulz 0x000109fd Thumb Code 54 dfixul.o(.text) + __aeabi_cdrcmple 0x00010a3d Thumb Code 38 cdrcmple.o(.text) + __scatterload 0x00010a65 Thumb Code 28 init.o(.text) + __scatterload_rt2 0x00010a65 Thumb Code 0 init.o(.text) + __decompress 0x00010a89 Thumb Code 0 __dczerorl2.o(.text) + __decompress1 0x00010a89 Thumb Code 86 __dczerorl2.o(.text) + AP_NRESET_IRQn_Handler 0x00010ae1 Thumb Code 22 drv_gpio.o(i.AP_NRESET_IRQn_Handler) + DMA_IRQn_Handler 0x00010afd Thumb Code 78 drv_dma.o(i.DMA_IRQn_Handler) + EXTI_INT0_IRQn_Handler 0x00010b59 Thumb Code 10 drv_gpio.o(i.EXTI_INT0_IRQn_Handler) + EXTI_INT1_IRQn_Handler 0x00010b63 Thumb Code 10 drv_gpio.o(i.EXTI_INT1_IRQn_Handler) + EXTI_INT2_IRQn_Handler 0x00010b6d Thumb Code 10 drv_gpio.o(i.EXTI_INT2_IRQn_Handler) + EXTI_INT3_IRQn_Handler 0x00010b77 Thumb Code 10 drv_gpio.o(i.EXTI_INT3_IRQn_Handler) + EXTI_INT4_IRQn_Handler 0x00010b81 Thumb Code 10 drv_gpio.o(i.EXTI_INT4_IRQn_Handler) + EXTI_INT5_IRQn_Handler 0x00010b8b Thumb Code 10 drv_gpio.o(i.EXTI_INT5_IRQn_Handler) + EXTI_INT6_IRQn_Handler 0x00010b95 Thumb Code 10 drv_gpio.o(i.EXTI_INT6_IRQn_Handler) + EXTI_INT7_IRQn_Handler 0x00010b9f Thumb Code 10 drv_gpio.o(i.EXTI_INT7_IRQn_Handler) + HardFault_Handler 0x00010ba9 Thumb Code 14 drv_common.o(i.HardFault_Handler) + LCDC_IRQn_Handler 0x00010bf1 Thumb Code 118 hal_internal_vsync.o(i.LCDC_IRQn_Handler) + MEMC_IRQn_Handler 0x00010cf1 Thumb Code 154 drv_memc.o(i.MEMC_IRQn_Handler) + MIPI_TX_IRQn_Handler 0x00010d8d Thumb Code 70 drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler) + SWIRE_IRQn_Handler 0x00010e45 Thumb Code 38 drv_swire.o(i.SWIRE_IRQn_Handler) + SysTick_Handler 0x00010e75 Thumb Code 20 drv_common.o(i.SysTick_Handler) + TIMER0_IRQn_Handler 0x00010e8d Thumb Code 10 drv_timer.o(i.TIMER0_IRQn_Handler) + TIMER1_IRQn_Handler 0x00010e97 Thumb Code 10 drv_timer.o(i.TIMER1_IRQn_Handler) + TIMER2_IRQn_Handler 0x00010ea1 Thumb Code 10 drv_timer.o(i.TIMER2_IRQn_Handler) + TIMER3_IRQn_Handler 0x00010eab Thumb Code 10 drv_timer.o(i.TIMER3_IRQn_Handler) + VIDC_IRQn_Handler 0x00010eb5 Thumb Code 22 drv_vidc.o(i.VIDC_IRQn_Handler) + VPRE1_IRQn_Handler 0x00010ed1 Thumb Code 22 drv_rxbr.o(i.VPRE1_IRQn_Handler) + VPRE_IRQn_Handler 0x00010eed Thumb Code 116 hal_internal_dcs.o(i.VPRE_IRQn_Handler) + __0printf 0x00010f69 Thumb Code 24 printfa.o(i.__0printf) + __1printf 0x00010f69 Thumb Code 0 printfa.o(i.__0printf) + __2printf 0x00010f69 Thumb Code 0 printfa.o(i.__0printf) + __c89printf 0x00010f69 Thumb Code 0 printfa.o(i.__0printf) + printf 0x00010f69 Thumb Code 0 printfa.o(i.__0printf) + __0vsprintf 0x00010f89 Thumb Code 30 printfa.o(i.__0vsprintf) + __1vsprintf 0x00010f89 Thumb Code 0 printfa.o(i.__0vsprintf) + __2vsprintf 0x00010f89 Thumb Code 0 printfa.o(i.__0vsprintf) + __c89vsprintf 0x00010f89 Thumb Code 0 printfa.o(i.__0vsprintf) + vsprintf 0x00010f89 Thumb Code 0 printfa.o(i.__0vsprintf) + __ARM_clz 0x00010fad Thumb Code 46 depilogue.o(i.__ARM_clz) + __ARM_common_switch8 0x00010fdb Thumb Code 26 hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) + __scatterload_null 0x00010ff5 Thumb Code 2 handlers.o(i.__scatterload_null) + s_RAM_CK 0x00011000 Data 28 drv_common.o(.ARM.__at_0x11000) + g_tau_log 0x0001101c Data 16 tau_log.o(.ARM.__at_0x1101C) + sg_pq_para 0x0001102c Data 22 hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) + MIPI_RX_IRQn_Handler 0x00011045 Thumb Code 354 drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler) + UART_IRQn_Handler 0x000113a9 Thumb Code 364 drv_uart.o(i.UART_IRQn_Handler) + __scatterload_copy 0x00011561 Thumb Code 14 handlers.o(i.__scatterload_copy) + __scatterload_zeroinit 0x0001156f Thumb Code 14 handlers.o(i.__scatterload_zeroinit) + app_display_init 0x000122bf Thumb Code 44 p8p_demo.o(i.app_display_init) + app_gpio_init 0x000122ed Thumb Code 22 p8p_demo.o(i.app_gpio_init) + board_Init 0x00012879 Thumb Code 20 board.o(i.board_Init) + ceil 0x00012891 Thumb Code 180 ceil.o(i.ceil) + dcs_packet_fifo_alloc 0x00012a0d Thumb Code 80 dcs_packet_fifo.o(i.dcs_packet_fifo_alloc) + dcs_packet_fifo_init 0x00012a65 Thumb Code 18 dcs_packet_fifo.o(i.dcs_packet_fifo_init) + dcs_packet_free_fifo_header 0x00012a7d Thumb Code 60 dcs_packet_fifo.o(i.dcs_packet_free_fifo_header) + dcs_packet_get_fifo_header 0x00012ac1 Thumb Code 26 dcs_packet_fifo.o(i.dcs_packet_get_fifo_header) + delayMs 0x00012ae5 Thumb Code 24 tau_delay.o(i.delayMs) + delayUs 0x00012afd Thumb Code 40 tau_delay.o(i.delayUs) + drv_common_system_init 0x00012b29 Thumb Code 8 drv_common.o(i.drv_common_system_init) + drv_crgu_enable_clock 0x00012b31 Thumb Code 54 drv_crgu.o(i.drv_crgu_enable_clock) + drv_crgu_get_rxbr_clk 0x00012b6d Thumb Code 70 drv_crgu.o(i.drv_crgu_get_rxbr_clk) + drv_crgu_reset_modules 0x00012bd5 Thumb Code 10 drv_crgu.o(i.drv_crgu_reset_modules) + drv_crgu_set_ahb_clk 0x00012be5 Thumb Code 34 drv_crgu.o(i.drv_crgu_set_ahb_clk) + drv_crgu_set_clock_div 0x00012c0d Thumb Code 12 drv_crgu.o(i.drv_crgu_set_clock_div) + drv_crgu_set_dpi_clk 0x00012c1d Thumb Code 54 drv_crgu.o(i.drv_crgu_set_dpi_clk) + drv_crgu_set_dsc_clk 0x00012c59 Thumb Code 52 drv_crgu.o(i.drv_crgu_set_dsc_clk) + drv_crgu_set_fb_clk 0x00012c91 Thumb Code 34 drv_crgu.o(i.drv_crgu_set_fb_clk) + drv_crgu_set_lcdc_clk 0x00012cb9 Thumb Code 36 drv_crgu.o(i.drv_crgu_set_lcdc_clk) + drv_crgu_set_reset 0x00012ce1 Thumb Code 20 drv_crgu.o(i.drv_crgu_set_reset) + drv_crgu_set_rxbr_clk 0x00012cf9 Thumb Code 34 drv_crgu.o(i.drv_crgu_set_rxbr_clk) + drv_crgu_set_vidc_clk 0x00012d21 Thumb Code 36 drv_crgu.o(i.drv_crgu_set_vidc_clk) + drv_dma_clear_status 0x00012d49 Thumb Code 20 drv_dma.o(i.drv_dma_clear_status) + drv_dsc_dec_disable 0x00012d75 Thumb Code 20 drv_dsc_dec.o(i.drv_dsc_dec_disable) + drv_dsc_dec_enable 0x00012d91 Thumb Code 44 drv_dsc_dec.o(i.drv_dsc_dec_enable) + drv_dsc_dec_get_nslc 0x00012dc9 Thumb Code 22 drv_dsc_dec.o(i.drv_dsc_dec_get_nslc) + drv_dsc_dec_set_irqen 0x00012de9 Thumb Code 24 drv_dsc_dec.o(i.drv_dsc_dec_set_irqen) + drv_dsi_rx_calc_ipi_tx_delay 0x00012e05 Thumb Code 252 drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) + drv_dsi_rx_enable_irq 0x00012f11 Thumb Code 58 drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) + drv_dsi_rx_get_compression_en 0x00012fbd Thumb Code 10 drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en) + drv_dsi_rx_get_ddi_crc_en 0x00012fcd Thumb Code 10 drv_dsi_rx.o(i.drv_dsi_rx_get_ddi_crc_en) + drv_dsi_rx_get_max_ret_size 0x00012fdd Thumb Code 8 drv_dsi_rx.o(i.drv_dsi_rx_get_max_ret_size) + drv_dsi_rx_power_up 0x00012fe9 Thumb Code 14 drv_dsi_rx.o(i.drv_dsi_rx_power_up) + drv_dsi_rx_set_check_crc 0x00013001 Thumb Code 24 drv_dsi_rx.o(i.drv_dsi_rx_set_check_crc) + drv_dsi_rx_set_ctrl_cfg 0x0001301d Thumb Code 32 drv_dsi_rx.o(i.drv_dsi_rx_set_ctrl_cfg) + drv_dsi_rx_set_ddi_cfg 0x00013041 Thumb Code 10 drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) + drv_dsi_rx_set_ddi_crc_en 0x00013051 Thumb Code 24 drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_crc_en) + drv_dsi_rx_set_inten 0x0001306d Thumb Code 8 drv_dsi_rx.o(i.drv_dsi_rx_set_inten) + drv_dsi_rx_set_ipi_cfg 0x00013079 Thumb Code 12 drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_cfg) + drv_dsi_rx_set_ipi_ycbcr_frmt 0x00013089 Thumb Code 24 drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_ycbcr_frmt) + drv_dsi_rx_set_lane_swap 0x000130a5 Thumb Code 16 drv_dsi_rx.o(i.drv_dsi_rx_set_lane_swap) + drv_dsi_rx_set_resp_cnt 0x000130b9 Thumb Code 32 drv_dsi_rx.o(i.drv_dsi_rx_set_resp_cnt) + drv_dsi_rx_set_tear_resp_en 0x000130dd Thumb Code 24 drv_dsi_rx.o(i.drv_dsi_rx_set_tear_resp_en) + drv_dsi_rx_set_up_phy 0x000130f9 Thumb Code 224 drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) + drv_dsi_rx_shut_down 0x000131f9 Thumb Code 14 drv_dsi_rx.o(i.drv_dsi_rx_shut_down) + drv_dsi_tx_command_header 0x00013211 Thumb Code 18 drv_dsi_tx.o(i.drv_dsi_tx_command_header) + drv_dsi_tx_command_mode_cfg 0x00013229 Thumb Code 82 drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg) + drv_dsi_tx_command_put_payload 0x00013281 Thumb Code 6 drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) + drv_dsi_tx_config_eotp 0x0001328d Thumb Code 26 drv_dsi_tx.o(i.drv_dsi_tx_config_eotp) + drv_dsi_tx_config_int 0x000132ad Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_config_int) + drv_dsi_tx_dpi_lpcmd_time 0x000132b9 Thumb Code 10 drv_dsi_tx.o(i.drv_dsi_tx_dpi_lpcmd_time) + drv_dsi_tx_dpi_mode 0x000132c9 Thumb Code 12 drv_dsi_tx.o(i.drv_dsi_tx_dpi_mode) + drv_dsi_tx_dpi_polarity 0x000132d9 Thumb Code 32 drv_dsi_tx.o(i.drv_dsi_tx_dpi_polarity) + drv_dsi_tx_edpi_cmd_size 0x000132fd Thumb Code 6 drv_dsi_tx.o(i.drv_dsi_tx_edpi_cmd_size) + drv_dsi_tx_get_cmd_status 0x00013309 Thumb Code 6 drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) + drv_dsi_tx_mode 0x00013315 Thumb Code 6 drv_dsi_tx.o(i.drv_dsi_tx_mode) + drv_dsi_tx_phy_clock_lane_auto_lp 0x00013321 Thumb Code 24 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp) + drv_dsi_tx_phy_clock_lane_req_hs 0x0001333d Thumb Code 26 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs) + drv_dsi_tx_phy_lane_mode 0x0001335d Thumb Code 12 drv_dsi_tx.o(i.drv_dsi_tx_phy_lane_mode) + drv_dsi_tx_phy_status_ready 0x0001336d Thumb Code 100 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready) + drv_dsi_tx_phy_status_stopstate 0x000133d5 Thumb Code 62 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) + drv_dsi_tx_phy_test_setup 0x00013419 Thumb Code 314 drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) + drv_dsi_tx_phy_time_cfg 0x00013569 Thumb Code 28 drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg) + drv_dsi_tx_powerup 0x00013589 Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_powerup) + drv_dsi_tx_response_mode 0x00013595 Thumb Code 30 drv_dsi_tx.o(i.drv_dsi_tx_response_mode) + drv_dsi_tx_set_bta_ack 0x000135b9 Thumb Code 24 drv_dsi_tx.o(i.drv_dsi_tx_set_bta_ack) + drv_dsi_tx_set_esc_div 0x000135d5 Thumb Code 14 drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) + drv_dsi_tx_set_int 0x000135e9 Thumb Code 58 drv_dsi_tx.o(i.drv_dsi_tx_set_int) + drv_dsi_tx_set_time_out_div 0x00013629 Thumb Code 18 drv_dsi_tx.o(i.drv_dsi_tx_set_time_out_div) + drv_dsi_tx_set_video_chunk 0x00013641 Thumb Code 14 drv_dsi_tx.o(i.drv_dsi_tx_set_video_chunk) + drv_dsi_tx_set_video_timing 0x00013655 Thumb Code 30 drv_dsi_tx.o(i.drv_dsi_tx_set_video_timing) + drv_dsi_tx_shutdown 0x00013679 Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_shutdown) + drv_dsi_tx_timeout_cfg 0x00013685 Thumb Code 38 drv_dsi_tx.o(i.drv_dsi_tx_timeout_cfg) + drv_dsi_tx_video_mode_cfg 0x000136b1 Thumb Code 226 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_cfg) + drv_efuse_enter_inactive 0x00013799 Thumb Code 54 drv_efuse.o(i.drv_efuse_enter_inactive) + drv_efuse_int_enable 0x000137cf Thumb Code 12 drv_efuse.o(i.drv_efuse_int_enable) + drv_efuse_read 0x000137db Thumb Code 58 drv_efuse.o(i.drv_efuse_read) + drv_efuse_read_req 0x00013815 Thumb Code 24 drv_efuse.o(i.drv_efuse_read_req) + drv_gpio_register_ap_reset_callback 0x00013851 Thumb Code 6 drv_gpio.o(i.drv_gpio_register_ap_reset_callback) + drv_gpio_register_callback 0x0001385d Thumb Code 14 drv_gpio.o(i.drv_gpio_register_callback) + drv_gpio_set_int 0x00013871 Thumb Code 62 drv_gpio.o(i.drv_gpio_set_int) + drv_gpio_set_ioe 0x000138b5 Thumb Code 26 drv_gpio.o(i.drv_gpio_set_ioe) + drv_gpio_set_mode 0x000138d5 Thumb Code 16 drv_gpio.o(i.drv_gpio_set_mode) + drv_lcdc_bcsa_config 0x00013909 Thumb Code 30 drv_lcdc.o(i.drv_lcdc_bcsa_config) + drv_lcdc_cfg_int_frame 0x00013931 Thumb Code 34 drv_lcdc.o(i.drv_lcdc_cfg_int_frame) + drv_lcdc_cmd_start 0x00013975 Thumb Code 46 drv_lcdc.o(i.drv_lcdc_cmd_start) + drv_lcdc_config_acc_command_mode 0x000139a9 Thumb Code 14 drv_lcdc.o(i.drv_lcdc_config_acc_command_mode) + drv_lcdc_config_int 0x000139bd Thumb Code 50 drv_lcdc.o(i.drv_lcdc_config_int) + drv_lcdc_config_int_single 0x000139f5 Thumb Code 34 drv_lcdc.o(i.drv_lcdc_config_int_single) + drv_lcdc_config_overwrite_rgb 0x00013a1d Thumb Code 18 drv_lcdc.o(i.drv_lcdc_config_overwrite_rgb) + drv_lcdc_config_src_parameter 0x00013a35 Thumb Code 72 drv_lcdc.o(i.drv_lcdc_config_src_parameter) + drv_lcdc_crop_hact 0x00013a85 Thumb Code 10 drv_lcdc.o(i.drv_lcdc_crop_hact) + drv_lcdc_ctrl_flow 0x00013a95 Thumb Code 50 drv_lcdc.o(i.drv_lcdc_ctrl_flow) + drv_lcdc_dith_config 0x00013acd Thumb Code 40 drv_lcdc.o(i.drv_lcdc_dith_config) + drv_lcdc_edge_dect_config 0x00013afd Thumb Code 50 drv_lcdc.o(i.drv_lcdc_edge_dect_config) + drv_lcdc_edge_enh_config 0x00013b39 Thumb Code 86 drv_lcdc.o(i.drv_lcdc_edge_enh_config) + drv_lcdc_enable_shadow_reg 0x00013b9d Thumb Code 32 drv_lcdc.o(i.drv_lcdc_enable_shadow_reg) + drv_lcdc_endianness_config 0x00013bc1 Thumb Code 24 drv_lcdc.o(i.drv_lcdc_endianness_config) + drv_lcdc_fc_config 0x00013bdd Thumb Code 24 drv_lcdc.o(i.drv_lcdc_fc_config) + drv_lcdc_fldc_config 0x00013bfd Thumb Code 32 drv_lcdc.o(i.drv_lcdc_fldc_config) + drv_lcdc_function_disable 0x00013c21 Thumb Code 30 drv_lcdc.o(i.drv_lcdc_function_disable) + drv_lcdc_function_enable 0x00013c45 Thumb Code 30 drv_lcdc.o(i.drv_lcdc_function_enable) + drv_lcdc_set_int 0x00013c69 Thumb Code 54 drv_lcdc.o(i.drv_lcdc_set_int) + drv_lcdc_set_prefetch 0x00013ca5 Thumb Code 24 drv_lcdc.o(i.drv_lcdc_set_prefetch) + drv_lcdc_set_tear_line 0x00013cc1 Thumb Code 24 drv_lcdc.o(i.drv_lcdc_set_tear_line) + drv_lcdc_stop_display 0x00013cdd Thumb Code 12 drv_lcdc.o(i.drv_lcdc_stop_display) + drv_lcdc_vid_hw_start 0x00013ced Thumb Code 56 drv_lcdc.o(i.drv_lcdc_vid_hw_start) + drv_lcdc_vintp_mode_config 0x00013d29 Thumb Code 18 drv_lcdc.o(i.drv_lcdc_vintp_mode_config) + drv_memc_clear_status 0x00013d41 Thumb Code 14 drv_memc.o(i.drv_memc_clear_status) + drv_memc_enable_irq 0x00013d55 Thumb Code 58 drv_memc.o(i.drv_memc_enable_irq) + drv_memc_gen_a_tear_signal 0x00013d95 Thumb Code 12 drv_memc.o(i.drv_memc_gen_a_tear_signal) + drv_memc_get_status 0x00013da5 Thumb Code 20 drv_memc.o(i.drv_memc_get_status) + drv_memc_get_tear_mode 0x00013dbd Thumb Code 10 drv_memc.o(i.drv_memc_get_tear_mode) + drv_memc_rate_transfer_sel 0x00013dcd Thumb Code 22 drv_memc.o(i.drv_memc_rate_transfer_sel) + drv_memc_sel_vsync 0x00013de9 Thumb Code 16 drv_memc.o(i.drv_memc_sel_vsync) + drv_memc_set_active_height 0x00013dfd Thumb Code 16 drv_memc.o(i.drv_memc_set_active_height) + drv_memc_set_circ_mode_enable 0x00013e15 Thumb Code 24 drv_memc.o(i.drv_memc_set_circ_mode_enable) + drv_memc_set_data_mode 0x00013e31 Thumb Code 14 drv_memc.o(i.drv_memc_set_data_mode) + drv_memc_set_double_buffer 0x00013e45 Thumb Code 18 drv_memc.o(i.drv_memc_set_double_buffer) + drv_memc_set_frame_drop_select 0x00013e5d Thumb Code 24 drv_memc.o(i.drv_memc_set_frame_drop_select) + drv_memc_set_fs_en_conditions 0x00013e79 Thumb Code 18 drv_memc.o(i.drv_memc_set_fs_en_conditions) + drv_memc_set_lcdc_st_conditions 0x00013e91 Thumb Code 20 drv_memc.o(i.drv_memc_set_lcdc_st_conditions) + drv_memc_set_ltpo_mode 0x00013ead Thumb Code 28 drv_memc.o(i.drv_memc_set_ltpo_mode) + drv_memc_set_ltpo_pu_thres 0x00013ecd Thumb Code 18 drv_memc.o(i.drv_memc_set_ltpo_pu_thres) + drv_memc_set_tear_mode 0x00013ee5 Thumb Code 16 drv_memc.o(i.drv_memc_set_tear_mode) + drv_memc_set_tear_waveform 0x00013ef9 Thumb Code 36 drv_memc.o(i.drv_memc_set_tear_waveform) + drv_memc_set_vidc_sync_cnt 0x00013f25 Thumb Code 16 drv_memc.o(i.drv_memc_set_vidc_sync_cnt) + drv_phy_test_clear 0x00013f39 Thumb Code 16 drv_phy_common.o(i.drv_phy_test_clear) + drv_phy_test_lock 0x00013f49 Thumb Code 24 drv_phy_common.o(i.drv_phy_test_lock) + drv_pwr_efuse_pd 0x00013f61 Thumb Code 36 drv_pwr.o(i.drv_pwr_efuse_pd) + drv_pwr_enter_deep_sleep_mode 0x00013f91 Thumb Code 60 drv_pwr.o(i.drv_pwr_enter_deep_sleep_mode) + drv_pwr_enter_sleep_mode_ex 0x00013fdd Thumb Code 34 drv_pwr.o(i.drv_pwr_enter_sleep_mode_ex) + drv_pwr_enter_stop_sleep_mode 0x00014011 Thumb Code 132 drv_pwr.o(i.drv_pwr_enter_stop_sleep_mode) + drv_pwr_exit_sleep_mode 0x000140a9 Thumb Code 32 drv_pwr.o(i.drv_pwr_exit_sleep_mode) + drv_pwr_get_power_ready_st 0x000140d1 Thumb Code 10 drv_pwr.o(i.drv_pwr_get_power_ready_st) + drv_pwr_set_breath_screen_power_sel 0x000140e1 Thumb Code 34 drv_pwr.o(i.drv_pwr_set_breath_screen_power_sel) + drv_pwr_set_digit_power_sel 0x00014109 Thumb Code 34 drv_pwr.o(i.drv_pwr_set_digit_power_sel) + drv_pwr_set_pll_clk 0x00014131 Thumb Code 30 drv_pwr.o(i.drv_pwr_set_pll_clk) + drv_pwr_set_wakeup_type 0x00014165 Thumb Code 40 drv_pwr.o(i.drv_pwr_set_wakeup_type) + drv_pwr_write_lock 0x00014191 Thumb Code 18 drv_pwr.o(i.drv_pwr_write_lock) + drv_rxbr_clear_pkt_buffer 0x000141b1 Thumb Code 12 drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) + drv_rxbr_clear_status0 0x000141c1 Thumb Code 6 drv_rxbr.o(i.drv_rxbr_clear_status0) + drv_rxbr_enable_irq 0x000141cd Thumb Code 90 drv_rxbr.o(i.drv_rxbr_enable_irq) + drv_rxbr_frame_drop_cfg 0x00014229 Thumb Code 18 drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) + drv_rxbr_hline_rcv1_cfg 0x00014275 Thumb Code 14 drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg) + drv_rxbr_hline_rcv_cfg 0x00014289 Thumb Code 10 drv_rxbr.o(i.drv_rxbr_hline_rcv_cfg) + drv_rxbr_register_irq1_callback 0x00014299 Thumb Code 6 drv_rxbr.o(i.drv_rxbr_register_irq1_callback) + drv_rxbr_set_ack_pkt_header 0x000142a5 Thumb Code 18 drv_rxbr.o(i.drv_rxbr_set_ack_pkt_header) + drv_rxbr_set_color_format 0x000142bd Thumb Code 24 drv_rxbr.o(i.drv_rxbr_set_color_format) + drv_rxbr_set_filter_regs 0x000142d9 Thumb Code 32 drv_rxbr.o(i.drv_rxbr_set_filter_regs) + drv_rxbr_set_inten 0x000142fd Thumb Code 22 drv_rxbr.o(i.drv_rxbr_set_inten) + drv_rxbr_set_ltpo_drop_th 0x00014319 Thumb Code 18 drv_rxbr.o(i.drv_rxbr_set_ltpo_drop_th) + drv_rxbr_set_usr_cfg 0x00014331 Thumb Code 56 drv_rxbr.o(i.drv_rxbr_set_usr_cfg) + drv_rxbr_set_usr_col 0x00014371 Thumb Code 10 drv_rxbr.o(i.drv_rxbr_set_usr_col) + drv_rxbr_set_usr_row 0x00014381 Thumb Code 10 drv_rxbr.o(i.drv_rxbr_set_usr_row) + drv_se_init 0x00014391 Thumb Code 106 drv_se.o(i.drv_se_init) + drv_se_set_dsc 0x00014409 Thumb Code 162 drv_se.o(i.drv_se_set_dsc) + drv_se_set_lcdc 0x000144dd Thumb Code 88 drv_se.o(i.drv_se_set_lcdc) + drv_se_set_memc 0x00014565 Thumb Code 96 drv_se.o(i.drv_se_set_memc) + drv_se_set_rxbr 0x000145f5 Thumb Code 158 drv_se.o(i.drv_se_set_rxbr) + drv_se_set_vidc 0x000146c5 Thumb Code 122 drv_se.o(i.drv_se_set_vidc) + drv_se_start_rx 0x00014771 Thumb Code 16 drv_se.o(i.drv_se_start_rx) + drv_swire_enable 0x00014785 Thumb Code 24 drv_swire.o(i.drv_swire_enable) + drv_swire_get_pulse_count 0x000147a1 Thumb Code 6 drv_swire.o(i.drv_swire_get_pulse_count) + drv_swire_register_callback 0x000147ad Thumb Code 6 drv_swire.o(i.drv_swire_register_callback) + drv_swire_set_bit_time 0x000147b9 Thumb Code 18 drv_swire.o(i.drv_swire_set_bit_time) + drv_swire_set_int 0x000147d1 Thumb Code 64 drv_swire.o(i.drv_swire_set_int) + drv_swire_set_power_down 0x00014819 Thumb Code 24 drv_swire.o(i.drv_swire_set_power_down) + drv_swire_set_pulse_count 0x00014835 Thumb Code 6 drv_swire.o(i.drv_swire_set_pulse_count) + drv_swire_set_trig_mode 0x00014841 Thumb Code 24 drv_swire.o(i.drv_swire_set_trig_mode) + drv_sys_cfg_clear_all_int 0x0001485d Thumb Code 8 drv_sys_cfg.o(i.drv_sys_cfg_clear_all_int) + drv_sys_cfg_clear_pending 0x00014869 Thumb Code 32 drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) + drv_sys_cfg_sel_ap_rst_trig 0x00014891 Thumb Code 30 drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_trig) + drv_sys_cfg_sel_gpio_group 0x000148b5 Thumb Code 30 drv_sys_cfg.o(i.drv_sys_cfg_sel_gpio_group) + drv_sys_cfg_sel_int_trig 0x000148d9 Thumb Code 32 drv_sys_cfg.o(i.drv_sys_cfg_sel_int_trig) + drv_sys_cfg_sel_swire_timer 0x000148fd Thumb Code 18 drv_sys_cfg.o(i.drv_sys_cfg_sel_swire_timer) + drv_sys_cfg_set_int 0x00014915 Thumb Code 30 drv_sys_cfg.o(i.drv_sys_cfg_set_int) + drv_timer_enable 0x00014953 Thumb Code 32 drv_timer.o(i.drv_timer_enable) + drv_timer_get_instance 0x00014975 Thumb Code 10 drv_timer.o(i.drv_timer_get_instance) + drv_timer_set_compare_val 0x000149c1 Thumb Code 50 drv_timer.o(i.drv_timer_set_compare_val) + drv_timer_set_int 0x00014a01 Thumb Code 68 drv_timer.o(i.drv_timer_set_int) + drv_timer_set_prescaler 0x00014a49 Thumb Code 36 drv_timer.o(i.drv_timer_set_prescaler) + drv_timer_set_repeat 0x00014a71 Thumb Code 12 drv_timer.o(i.drv_timer_set_repeat) + drv_tx_phy_test_enter 0x00014a81 Thumb Code 28 drv_dsi_tx.o(i.drv_tx_phy_test_enter) + drv_tx_phy_test_exit 0x00014aa1 Thumb Code 28 drv_dsi_tx.o(i.drv_tx_phy_test_exit) + drv_tx_phy_test_write_code 0x00014ac1 Thumb Code 34 drv_dsi_tx.o(i.drv_tx_phy_test_write_code) + drv_uart_abort_recv 0x00014ae9 Thumb Code 46 drv_uart.o(i.drv_uart_abort_recv) + drv_uart_abort_send 0x00014b1d Thumb Code 46 drv_uart.o(i.drv_uart_abort_send) + drv_uart_config_int 0x00014b51 Thumb Code 20 drv_uart.o(i.drv_uart_config_int) + drv_uart_enable_int 0x00014b7d Thumb Code 84 drv_uart.o(i.drv_uart_enable_int) + drv_uart_get_instance 0x00014bd9 Thumb Code 36 drv_uart.o(i.drv_uart_get_instance) + drv_uart_init 0x00014c01 Thumb Code 206 drv_uart.o(i.drv_uart_init) + drv_uart_reset_rx_fifo 0x00014d0d Thumb Code 28 drv_uart.o(i.drv_uart_reset_rx_fifo) + drv_uart_reset_tx_fifo 0x00014d29 Thumb Code 28 drv_uart.o(i.drv_uart_reset_tx_fifo) + drv_uart_send_blocking 0x00014d45 Thumb Code 26 drv_uart.o(i.drv_uart_send_blocking) + drv_uart_set_baud_rate 0x00014d5f Thumb Code 84 drv_uart.o(i.drv_uart_set_baud_rate) + drv_uart_trans_create_handle 0x00014db5 Thumb Code 72 drv_uart.o(i.drv_uart_trans_create_handle) + drv_vidc_clear_irq 0x00014e01 Thumb Code 10 drv_vidc.o(i.drv_vidc_clear_irq) + drv_vidc_enable 0x00014e11 Thumb Code 26 drv_vidc.o(i.drv_vidc_enable) + drv_vidc_enable_irq 0x00014e31 Thumb Code 58 drv_vidc.o(i.drv_vidc_enable_irq) + drv_vidc_get_int_source 0x00014e71 Thumb Code 40 drv_vidc.o(i.drv_vidc_get_int_source) + drv_vidc_get_irq_status 0x00014e9d Thumb Code 20 drv_vidc.o(i.drv_vidc_get_irq_status) + drv_vidc_init_module_enable 0x00014eb5 Thumb Code 36 drv_vidc.o(i.drv_vidc_init_module_enable) + drv_vidc_register_callback 0x00014ee1 Thumb Code 6 drv_vidc.o(i.drv_vidc_register_callback) + drv_vidc_reset 0x00014eed Thumb Code 8 drv_vidc.o(i.drv_vidc_reset) + drv_vidc_set_circ_mode_enable 0x00014ef9 Thumb Code 24 drv_vidc.o(i.drv_vidc_set_circ_mode_enable) + drv_vidc_set_dither_config 0x00014f15 Thumb Code 50 drv_vidc.o(i.drv_vidc_set_dither_config) + drv_vidc_set_dst_parameter 0x00014f4d Thumb Code 86 drv_vidc.o(i.drv_vidc_set_dst_parameter) + drv_vidc_set_honly_hcoef0 0x00014fa9 Thumb Code 6 drv_vidc.o(i.drv_vidc_set_honly_hcoef0) + drv_vidc_set_honly_hinitb 0x00014fb5 Thumb Code 38 drv_vidc.o(i.drv_vidc_set_honly_hinitb) + drv_vidc_set_honly_hinitr 0x00014fe1 Thumb Code 42 drv_vidc.o(i.drv_vidc_set_honly_hinitr) + drv_vidc_set_irqen 0x00015011 Thumb Code 22 drv_vidc.o(i.drv_vidc_set_irqen) + drv_vidc_set_mirror 0x0001502d Thumb Code 16 drv_vidc.o(i.drv_vidc_set_mirror) + drv_vidc_set_pentile_swap 0x00015041 Thumb Code 20 drv_vidc.o(i.drv_vidc_set_pentile_swap) + drv_vidc_set_pu_ctrl 0x0001505d Thumb Code 6 drv_vidc.o(i.drv_vidc_set_pu_ctrl) + drv_vidc_set_rotation 0x00015069 Thumb Code 18 drv_vidc.o(i.drv_vidc_set_rotation) + drv_vidc_set_scld_hcoef0 0x00015081 Thumb Code 6 drv_vidc.o(i.drv_vidc_set_scld_hcoef0) + drv_vidc_set_scld_hcoef1 0x0001508d Thumb Code 6 drv_vidc.o(i.drv_vidc_set_scld_hcoef1) + drv_vidc_set_scld_step 0x00015099 Thumb Code 14 drv_vidc.o(i.drv_vidc_set_scld_step) + drv_vidc_set_scld_vcoef0 0x000150ad Thumb Code 6 drv_vidc.o(i.drv_vidc_set_scld_vcoef0) + drv_vidc_set_scld_vcoef1 0x000150b9 Thumb Code 6 drv_vidc.o(i.drv_vidc_set_scld_vcoef1) + drv_vidc_set_src_parameter 0x000150c5 Thumb Code 28 drv_vidc.o(i.drv_vidc_set_src_parameter) + drv_vidc_set_vintp_config 0x000150e5 Thumb Code 52 drv_vidc.o(i.drv_vidc_set_vintp_config) + fputc 0x0001511d Thumb Code 42 tau_log.o(i.fputc) + google_p8p_demo 0x00015151 Thumb Code 48 p8p_demo.o(i.google_p8p_demo) + hal_dsi_rx_ctrl_create_handle 0x000151f1 Thumb Code 60 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) + hal_dsi_rx_ctrl_dcs_async_handler 0x00015231 Thumb Code 60 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) + hal_dsi_rx_ctrl_deinit 0x00015271 Thumb Code 132 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) + hal_dsi_rx_ctrl_get_max_ret_size 0x00015305 Thumb Code 28 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) + hal_dsi_rx_ctrl_init 0x00015325 Thumb Code 158 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) + hal_dsi_rx_ctrl_pre_init_pps 0x00015abd Thumb Code 50 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) + hal_dsi_rx_ctrl_send_ack_cmd 0x00015af5 Thumb Code 210 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) + hal_dsi_rx_ctrl_start 0x00015c15 Thumb Code 42 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) + hal_dsi_rx_ctrl_stop 0x00015c45 Thumb Code 42 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) + hal_dsi_rx_ctrl_toggle_resolution 0x00015c75 Thumb Code 28 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) + hal_dsi_tx_ctrl_create_handle 0x00015f11 Thumb Code 48 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) + hal_dsi_tx_ctrl_deinit 0x00015f49 Thumb Code 102 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) + hal_dsi_tx_ctrl_gen_a_tear_signal 0x00015fbd Thumb Code 34 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) + hal_dsi_tx_ctrl_init 0x00015fe1 Thumb Code 110 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) + hal_dsi_tx_ctrl_set_overwrite_rgb 0x0001606d Thumb Code 8 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb) + hal_dsi_tx_ctrl_set_tear_mode 0x00016075 Thumb Code 10 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) + hal_dsi_tx_ctrl_start 0x00016081 Thumb Code 116 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) + hal_dsi_tx_ctrl_stop 0x000160fd Thumb Code 52 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) + hal_dsi_tx_ctrl_write_array_cmd 0x00016135 Thumb Code 238 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) + hal_dsi_tx_ctrl_write_cmd 0x00016229 Thumb Code 202 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) + hal_gpio_config_pad 0x000168dd Thumb Code 58 hal_gpio.o(i.hal_gpio_config_pad) + hal_gpio_ctrl_eint 0x00016919 Thumb Code 18 hal_gpio.o(i.hal_gpio_ctrl_eint) + hal_gpio_init_eint 0x00016931 Thumb Code 58 hal_gpio.o(i.hal_gpio_init_eint) + hal_gpio_init_input 0x00016971 Thumb Code 22 hal_gpio.o(i.hal_gpio_init_input) + hal_gpio_init_output 0x00016987 Thumb Code 28 hal_gpio.o(i.hal_gpio_init_output) + hal_gpio_reg_eint_cb 0x000169a5 Thumb Code 22 hal_gpio.o(i.hal_gpio_reg_eint_cb) + hal_gpio_set_ap_reset_int 0x000169c1 Thumb Code 76 hal_gpio.o(i.hal_gpio_set_ap_reset_int) + hal_gpio_set_mode 0x00016a11 Thumb Code 94 hal_gpio.o(i.hal_gpio_set_mode) + hal_gpio_set_output_data 0x00016a75 Thumb Code 8 hal_gpio.o(i.hal_gpio_set_output_data) + hal_internal_sync_get_hight_performan_mode 0x00016a7d Thumb Code 10 hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) + hal_internal_sync_input_resolution_change 0x00016a8d Thumb Code 330 hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) + hal_internal_sync_register_lcdc_cb 0x00016c41 Thumb Code 8 hal_internal_vsync.o(i.hal_internal_sync_register_lcdc_cb) + hal_internal_vsync_deinit 0x00016c4d Thumb Code 22 hal_internal_vsync.o(i.hal_internal_vsync_deinit) + hal_internal_vsync_get_rx_state 0x00016c6d Thumb Code 6 hal_internal_vsync.o(i.hal_internal_vsync_get_rx_state) + hal_internal_vsync_get_sync_line 0x00016c79 Thumb Code 16 hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) + hal_internal_vsync_get_tx_state 0x00016c8d Thumb Code 6 hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) + hal_internal_vsync_init_rx 0x00016c99 Thumb Code 190 hal_internal_vsync.o(i.hal_internal_vsync_init_rx) + hal_internal_vsync_init_tx 0x00016d71 Thumb Code 194 hal_internal_vsync.o(i.hal_internal_vsync_init_tx) + hal_internal_vsync_set_rx_state 0x00016e39 Thumb Code 28 hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) + hal_internal_vsync_set_tear_mode 0x00016e59 Thumb Code 262 hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) + hal_internal_vsync_set_tx_state 0x00016f71 Thumb Code 92 hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) + hal_intl_dcs_init_sw_fltr 0x00016fdd Thumb Code 90 hal_internal_dcs.o(i.hal_intl_dcs_init_sw_fltr) + hal_intl_dcs_set_auto_hw_filter 0x00017691 Thumb Code 130 hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) + hal_intl_fb_cal_fb_info 0x00017749 Thumb Code 738 hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) + hal_intl_fb_get_memc_flow_mode 0x00017bdd Thumb Code 6 hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) + hal_intl_fb_get_rx_fb_info 0x00017be9 Thumb Code 12 hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) + hal_intl_fb_get_tx_fb_info 0x00017bf9 Thumb Code 12 hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info) + hal_intl_fb_get_user_flow 0x00017c09 Thumb Code 6 hal_internal_fb.o(i.hal_intl_fb_get_user_flow) + hal_intl_svs_deinit_rx 0x00017c15 Thumb Code 32 hal_internal_svs.o(i.hal_intl_svs_deinit_rx) + hal_intl_svs_deinit_tx 0x00017c3d Thumb Code 10 hal_internal_svs.o(i.hal_intl_svs_deinit_tx) + hal_intl_svs_handle 0x00017c4d Thumb Code 24 hal_internal_svs.o(i.hal_intl_svs_handle) + hal_intl_svs_init_rx 0x00017c71 Thumb Code 120 hal_internal_svs.o(i.hal_intl_svs_init_rx) + hal_intl_svs_init_tx 0x00017cf1 Thumb Code 16 hal_internal_svs.o(i.hal_intl_svs_init_tx) + hal_intl_svs_set_rx_vtt 0x00017d05 Thumb Code 6 hal_internal_svs.o(i.hal_intl_svs_set_rx_vtt) + hal_intl_svs_update_rxbr_clk 0x00017d11 Thumb Code 52 hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) + hal_lcdc_displayproc_config 0x00017d59 Thumb Code 94 hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config) + hal_lcdc_postproc_config 0x00017e79 Thumb Code 276 hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) + hal_lcdc_upscaler_config 0x00018001 Thumb Code 202 hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) + hal_nonshadow_func_update 0x000180e1 Thumb Code 180 hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) + hal_pwr_enter_deep_sleep_mode 0x0001819d Thumb Code 42 hal_pwr.o(i.hal_pwr_enter_deep_sleep_mode) + hal_pwr_enter_normal_sleep_mode 0x000181c7 Thumb Code 8 hal_pwr.o(i.hal_pwr_enter_normal_sleep_mode) + hal_pwr_enter_stop_sleep_mode 0x000181d1 Thumb Code 88 hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode) + hal_pwr_exit_sleep_mode 0x00018235 Thumb Code 10 hal_pwr.o(i.hal_pwr_exit_sleep_mode) + hal_pwr_get_vcc_power_ready 0x0001823f Thumb Code 8 hal_pwr.o(i.hal_pwr_get_vcc_power_ready) + hal_pwr_set_main_power 0x00018247 Thumb Code 8 hal_pwr.o(i.hal_pwr_set_main_power) + hal_pwr_set_sleep_mode_power 0x0001824f Thumb Code 8 hal_pwr.o(i.hal_pwr_set_sleep_mode_power) + hal_pwr_set_stop_sleep_wakeup_pin 0x00018259 Thumb Code 86 hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) + hal_swire_deinit 0x000182bd Thumb Code 60 hal_swire.o(i.hal_swire_deinit) + hal_swire_enable 0x000182fd Thumb Code 86 hal_swire.o(i.hal_swire_enable) + hal_swire_init 0x00018359 Thumb Code 74 hal_swire.o(i.hal_swire_init) + hal_swire_set_pulse 0x000183b1 Thumb Code 32 hal_swire.o(i.hal_swire_set_pulse) + hal_swire_set_timer 0x000183d5 Thumb Code 60 hal_swire.o(i.hal_swire_set_timer) + hal_system_init 0x00018415 Thumb Code 192 hal_system.o(i.hal_system_init) + hal_system_updata_sysclk 0x000184f9 Thumb Code 60 hal_system.o(i.hal_system_updata_sysclk) + hal_timer_deinit 0x00018549 Thumb Code 48 hal_timer.o(i.hal_timer_deinit) + hal_timer_init 0x00018579 Thumb Code 28 hal_timer.o(i.hal_timer_init) + hal_timer_set_repeat 0x00018595 Thumb Code 8 hal_timer.o(i.hal_timer_set_repeat) + hal_uart_init 0x000185cd Thumb Code 134 hal_uart.o(i.hal_uart_init) + hal_uart_send_blocking 0x00018661 Thumb Code 24 hal_uart.o(i.hal_uart_send_blocking) + hal_vsync_func_update 0x0001867d Thumb Code 18 hal_dsi_tx_ctrl.o(i.hal_vsync_func_update) + hal_vsync_reset_lcdc_scaler 0x00018695 Thumb Code 188 hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) + main 0x00018761 Thumb Code 32 main.o(i.main) + tau_log_init 0x00018fcd Thumb Code 48 tau_log.o(i.tau_log_init) + tau_log_printf 0x00019001 Thumb Code 116 tau_log.o(i.tau_log_printf) + tau_log_push_log 0x00019085 Thumb Code 118 tau_log.o(i.tau_log_push_log) + panel_init_code 0x00019328 Data 8262 p8p_demo.o(.constdata) + Region$$Table$$Base 0x0001b568 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x0001b588 Number 0 anon$$obj.o(Region$$Table) + rd_51_val 0x00070018 Data 2 p8p_demo.o(.data) + rd_51_val2 0x0007001a Data 2 p8p_demo.o(.data) + pps 0x0007001c Data 128 p8p_demo.o(.data) + pps_fhd 0x0007009c Data 128 p8p_demo.o(.data) + value_51H 0x0007011c Data 1 p8p_demo.o(.data) + value_51L 0x0007011d Data 1 p8p_demo.o(.data) + sg_uart0_tx_handle 0x000701b0 Data 4 hal_uart.o(.data) + sg_uart0_rx_handle 0x000701b4 Data 4 hal_uart.o(.data) + sg_uart1_tx_handle 0x000701b8 Data 4 hal_uart.o(.data) + sg_uart1_rx_handle 0x000701bc Data 4 hal_uart.o(.data) + g_sof_gen_te_func 0x000701cc Data 4 hal_internal_vsync.o(.data) + hal_internal_vsync_handle_callback 0x000701d0 Data 4 hal_internal_vsync.o(.data) + hal_internal_disp_end_handle_callback 0x000701d4 Data 4 hal_internal_vsync.o(.data) + g_systick_cb_func 0x00070204 Data 4 drv_common.o(.data) + g_system_clock 0x00070208 Data 4 drv_common.o(.data) + g_system_delay_step 0x0007020c Data 1 drv_common.o(.data) + g_int_rxbr_irq0_cb_func 0x00070270 Data 4 drv_rxbr.o(.data) + g_int_rxbr_irq1_cb_func 0x00070274 Data 4 drv_rxbr.o(.data) + g_int_vidc_cb_func 0x00070278 Data 4 drv_vidc.o(.data) + dma_req_map 0x0007037c Data 144 drv_dma.o(.data) + __stdout 0x0007040c Data 4 stdout.o(.data) + g_vsync_handle 0x00070698 Data 40 hal_internal_vsync.o(.bss) + g_dcs_execute_table 0x000706c0 Data 2048 hal_internal_dcs.o(.bss) + g_rx_fb_info 0x00070fc0 Data 68 hal_internal_fb.o(.bss) + g_packet_fifo 0x00071088 Data 4204 dcs_packet_fifo.o(.bss) + __stack_limit 0x00072168 Data 0 startup_armcm0.o(STACK) + __initial_sp 0x00073168 Data 0 startup_armcm0.o(STACK) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x000100c1 + + Load Region LR_IROM2 (Base: 0x00010000, Size: 0x0000b998, Max: 0x00010000, ABSOLUTE, COMPRESSED[0x0000b6f4]) + + Execution Region ER_IROM2 (Exec base: 0x00010000, Load base: 0x00010000, Size: 0x0000b588, Max: 0x00010000, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x00010000 0x00010000 0x000000c0 Data RO 323 RESET startup_armcm0.o + 0x000100c0 0x000100c0 0x00000000 Code RO 1866 * .ARM.Collect$$$$00000000 mc_p.l(entry.o) + 0x000100c0 0x000100c0 0x00000004 Code RO 2170 .ARM.Collect$$$$00000001 mc_p.l(entry2.o) + 0x000100c4 0x000100c4 0x00000004 Code RO 2173 .ARM.Collect$$$$00000004 mc_p.l(entry5.o) + 0x000100c8 0x000100c8 0x00000000 Code RO 2175 .ARM.Collect$$$$00000008 mc_p.l(entry7b.o) + 0x000100c8 0x000100c8 0x00000000 Code RO 2177 .ARM.Collect$$$$0000000A mc_p.l(entry8b.o) + 0x000100c8 0x000100c8 0x00000008 Code RO 2178 .ARM.Collect$$$$0000000B mc_p.l(entry9a.o) + 0x000100d0 0x000100d0 0x00000000 Code RO 2180 .ARM.Collect$$$$0000000D mc_p.l(entry10a.o) + 0x000100d0 0x000100d0 0x00000000 Code RO 2182 .ARM.Collect$$$$0000000F mc_p.l(entry11a.o) + 0x000100d0 0x000100d0 0x00000004 Code RO 2171 .ARM.Collect$$$$00002712 mc_p.l(entry2.o) + 0x000100d4 0x000100d4 0x00000078 Code RO 324 .text startup_armcm0.o + 0x0001014c 0x0001014c 0x0000002c Code RO 1869 .text mc_p.l(uidiv.o) + 0x00010178 0x00010178 0x00000028 Code RO 1871 .text mc_p.l(idiv.o) + 0x000101a0 0x000101a0 0x00000024 Code RO 1873 .text mc_p.l(memcpya.o) + 0x000101c4 0x000101c4 0x00000024 Code RO 1875 .text mc_p.l(memseta.o) + 0x000101e8 0x000101e8 0x0000000e Code RO 1877 .text mc_p.l(strlen.o) + 0x000101f6 0x000101f6 0x000000b2 Code RO 2142 .text mf_p.l(fadd.o) + 0x000102a8 0x000102a8 0x0000007a Code RO 2144 .text mf_p.l(fmul.o) + 0x00010322 0x00010322 0x0000007c Code RO 2146 .text mf_p.l(fdiv.o) + 0x0001039e 0x0001039e 0x00000018 Code RO 2148 .text mf_p.l(fscalb.o) + 0x000103b6 0x000103b6 0x00000002 PAD + 0x000103b8 0x000103b8 0x00000164 Code RO 2150 .text mf_p.l(dadd.o) + 0x0001051c 0x0001051c 0x000000d0 Code RO 2152 .text mf_p.l(dmul.o) + 0x000105ec 0x000105ec 0x0000000e Code RO 2154 .text mf_p.l(ffltui.o) + 0x000105fa 0x000105fa 0x00000002 PAD + 0x000105fc 0x000105fc 0x0000001c Code RO 2156 .text mf_p.l(dfltui.o) + 0x00010618 0x00010618 0x00000028 Code RO 2158 .text mf_p.l(ffixui.o) + 0x00010640 0x00010640 0x0000003c Code RO 2160 .text mf_p.l(dfixui.o) + 0x0001067c 0x0001067c 0x00000028 Code RO 2162 .text mf_p.l(f2d.o) + 0x000106a4 0x000106a4 0x00000038 Code RO 2164 .text mf_p.l(d2f.o) + 0x000106dc 0x000106dc 0x00000014 Code RO 2166 .text mf_p.l(cfcmple.o) + 0x000106f0 0x000106f0 0x00000014 Code RO 2168 .text mf_p.l(cfrcmple.o) + 0x00010704 0x00010704 0x00000060 Code RO 2185 .text mc_p.l(uldiv.o) + 0x00010764 0x00010764 0x00000020 Code RO 2187 .text mc_p.l(llshl.o) + 0x00010784 0x00010784 0x00000022 Code RO 2189 .text mc_p.l(llushr.o) + 0x000107a6 0x000107a6 0x00000026 Code RO 2191 .text mc_p.l(llsshr.o) + 0x000107cc 0x000107cc 0x00000000 Code RO 2193 .text mc_p.l(iusefp.o) + 0x000107cc 0x000107cc 0x00000082 Code RO 2194 .text mf_p.l(fepilogue.o) + 0x0001084e 0x0001084e 0x000000be Code RO 2196 .text mf_p.l(depilogue.o) + 0x0001090c 0x0001090c 0x000000f0 Code RO 2200 .text mf_p.l(ddiv.o) + 0x000109fc 0x000109fc 0x00000040 Code RO 2202 .text mf_p.l(dfixul.o) + 0x00010a3c 0x00010a3c 0x00000028 Code RO 2204 .text mf_p.l(cdrcmple.o) + 0x00010a64 0x00010a64 0x00000024 Code RO 2206 .text mc_p.l(init.o) + 0x00010a88 0x00010a88 0x00000056 Code RO 2216 .text mc_p.l(__dczerorl2.o) + 0x00010ade 0x00010ade 0x00000002 PAD + 0x00010ae0 0x00010ae0 0x0000001c Code RO 948 i.AP_NRESET_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010afc 0x00010afc 0x0000005c Code RO 1715 i.DMA_IRQn_Handler CVWL668.lib(drv_dma.o) + 0x00010b58 0x00010b58 0x0000000a Code RO 949 i.EXTI_INT0_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010b62 0x00010b62 0x0000000a Code RO 950 i.EXTI_INT1_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010b6c 0x00010b6c 0x0000000a Code RO 951 i.EXTI_INT2_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010b76 0x00010b76 0x0000000a Code RO 952 i.EXTI_INT3_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010b80 0x00010b80 0x0000000a Code RO 953 i.EXTI_INT4_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010b8a 0x00010b8a 0x0000000a Code RO 954 i.EXTI_INT5_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010b94 0x00010b94 0x0000000a Code RO 955 i.EXTI_INT6_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010b9e 0x00010b9e 0x0000000a Code RO 956 i.EXTI_INT7_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010ba8 0x00010ba8 0x00000048 Code RO 871 i.HardFault_Handler CVWL668.lib(drv_common.o) + 0x00010bf0 0x00010bf0 0x00000100 Code RO 720 i.LCDC_IRQn_Handler CVWL668.lib(hal_internal_vsync.o) + 0x00010cf0 0x00010cf0 0x0000009a Code RO 1475 i.MEMC_IRQn_Handler CVWL668.lib(drv_memc.o) + 0x00010d8a 0x00010d8a 0x00000002 PAD + 0x00010d8c 0x00010d8c 0x000000b8 Code RO 1281 i.MIPI_TX_IRQn_Handler CVWL668.lib(drv_dsi_tx.o) + 0x00010e44 0x00010e44 0x00000030 Code RO 1110 i.SWIRE_IRQn_Handler CVWL668.lib(drv_swire.o) + 0x00010e74 0x00010e74 0x00000018 Code RO 872 i.SysTick_Handler CVWL668.lib(drv_common.o) + 0x00010e8c 0x00010e8c 0x0000000a Code RO 1153 i.TIMER0_IRQn_Handler CVWL668.lib(drv_timer.o) + 0x00010e96 0x00010e96 0x0000000a Code RO 1154 i.TIMER1_IRQn_Handler CVWL668.lib(drv_timer.o) + 0x00010ea0 0x00010ea0 0x0000000a Code RO 1155 i.TIMER2_IRQn_Handler CVWL668.lib(drv_timer.o) + 0x00010eaa 0x00010eaa 0x0000000a Code RO 1156 i.TIMER3_IRQn_Handler CVWL668.lib(drv_timer.o) + 0x00010eb4 0x00010eb4 0x0000001c Code RO 1630 i.VIDC_IRQn_Handler CVWL668.lib(drv_vidc.o) + 0x00010ed0 0x00010ed0 0x0000001c Code RO 1541 i.VPRE1_IRQn_Handler CVWL668.lib(drv_rxbr.o) + 0x00010eec 0x00010eec 0x0000007c Code RO 782 i.VPRE_IRQn_Handler CVWL668.lib(hal_internal_dcs.o) + 0x00010f68 0x00010f68 0x00000020 Code RO 2114 i.__0printf mc_p.l(printfa.o) + 0x00010f88 0x00010f88 0x00000024 Code RO 2120 i.__0vsprintf mc_p.l(printfa.o) + 0x00010fac 0x00010fac 0x0000002e Code RO 2198 i.__ARM_clz mf_p.l(depilogue.o) + 0x00010fda 0x00010fda 0x0000001a Code RO 408 i.__ARM_common_switch8 CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00010ff4 0x00010ff4 0x00000002 Code RO 2211 i.__scatterload_null mc_p.l(handlers.o) + 0x00010ff6 0x00010ff6 0x0000000a Code RO 2126 i._sputc mc_p.l(printfa.o) + 0x00011000 0x00011000 0x0000001c Data RO 879 .ARM.__at_0x11000 CVWL668.lib(drv_common.o) + 0x0001101c 0x0001101c 0x00000010 Data RO 676 .ARM.__at_0x1101C CVWL668.lib(tau_log.o) + 0x0001102c 0x0001102c 0x00000016 Data RO 461 .ARM.__at_0x1102C CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00011042 0x00011042 0x00000002 PAD + 0x00011044 0x00011044 0x00000364 Code RO 1220 i.MIPI_RX_IRQn_Handler CVWL668.lib(drv_dsi_rx.o) + 0x000113a8 0x000113a8 0x00000180 Code RO 1778 i.UART_IRQn_Handler CVWL668.lib(drv_uart.o) + 0x00011528 0x00011528 0x00000020 Code RO 1542 i.__NVIC_DisableIRQ CVWL668.lib(drv_rxbr.o) + 0x00011548 0x00011548 0x00000018 Code RO 1543 i.__NVIC_EnableIRQ CVWL668.lib(drv_rxbr.o) + 0x00011560 0x00011560 0x0000000e Code RO 2210 i.__scatterload_copy mc_p.l(handlers.o) + 0x0001156e 0x0001156e 0x0000000e Code RO 2212 i.__scatterload_zeroinit mc_p.l(handlers.o) + 0x0001157c 0x0001157c 0x00000174 Code RO 2121 i._fp_digits mc_p.l(printfa.o) + 0x000116f0 0x000116f0 0x000006ec Code RO 2122 i._printf_core mc_p.l(printfa.o) + 0x00011ddc 0x00011ddc 0x00000020 Code RO 2123 i._printf_post_padding mc_p.l(printfa.o) + 0x00011dfc 0x00011dfc 0x0000002c Code RO 2124 i._printf_pre_padding mc_p.l(printfa.o) + 0x00011e28 0x00011e28 0x00000144 Code RO 95 i.ap_dcs_read p8p_demo.o + 0x00011f6c 0x00011f6c 0x000000a4 Code RO 96 i.ap_dcs_set_backlight p8p_demo.o + 0x00012010 0x00012010 0x00000048 Code RO 97 i.ap_dcs_set_display_off p8p_demo.o + 0x00012058 0x00012058 0x000000a0 Code RO 98 i.ap_dcs_set_display_on p8p_demo.o + 0x000120f8 0x000120f8 0x00000094 Code RO 99 i.ap_dcs_set_enter_sleep_mode p8p_demo.o + 0x0001218c 0x0001218c 0x00000040 Code RO 101 i.ap_dcs_set_exit_sleep_mode p8p_demo.o + 0x000121cc 0x000121cc 0x00000034 Code RO 102 i.ap_dcs_set_frame_change p8p_demo.o + 0x00012200 0x00012200 0x00000058 Code RO 103 i.ap_rstn_pull_down_cb p8p_demo.o + 0x00012258 0x00012258 0x0000001c Code RO 104 i.ap_rstn_pull_high_cb p8p_demo.o + 0x00012274 0x00012274 0x0000004a Code RO 105 i.ap_set_FPS_53 p8p_demo.o + 0x000122be 0x000122be 0x0000002c Code RO 106 i.app_display_init p8p_demo.o + 0x000122ea 0x000122ea 0x00000002 PAD + 0x000122ec 0x000122ec 0x0000001c Code RO 107 i.app_gpio_init p8p_demo.o + 0x00012308 0x00012308 0x00000034 Code RO 108 i.app_init_panel p8p_demo.o + 0x0001233c 0x0001233c 0x00000120 Code RO 109 i.app_mipi_rx_init p8p_demo.o + 0x0001245c 0x0001245c 0x00000100 Code RO 110 i.app_mipi_tx_init p8p_demo.o + 0x0001255c 0x0001255c 0x000000ac Code RO 111 i.app_mipi_tx_start p8p_demo.o + 0x00012608 0x00012608 0x0000006c Code RO 112 i.app_system_process p8p_demo.o + 0x00012674 0x00012674 0x00000044 Code RO 113 i.app_system_resume p8p_demo.o + 0x000126b8 0x000126b8 0x00000190 Code RO 114 i.app_system_suspend p8p_demo.o + 0x00012848 0x00012848 0x0000002e Code RO 115 i.app_tx_panel_reset p8p_demo.o + 0x00012876 0x00012876 0x00000002 PAD + 0x00012878 0x00012878 0x00000018 Code RO 297 i.board_Init board.o + 0x00012890 0x00012890 0x000000c8 Code RO 1863 i.ceil m_ps.l(ceil.o) + 0x00012958 0x00012958 0x0000002c Code RO 721 i.check_mipi_rx_tx_video_info CVWL668.lib(hal_internal_vsync.o) + 0x00012984 0x00012984 0x00000088 Code RO 783 i.check_pkt_buf_rev CVWL668.lib(hal_internal_dcs.o) + 0x00012a0c 0x00012a0c 0x00000058 Code RO 1186 i.dcs_packet_fifo_alloc CVWL668.lib(dcs_packet_fifo.o) + 0x00012a64 0x00012a64 0x00000018 Code RO 1187 i.dcs_packet_fifo_init CVWL668.lib(dcs_packet_fifo.o) + 0x00012a7c 0x00012a7c 0x00000044 Code RO 1188 i.dcs_packet_free_fifo_header CVWL668.lib(dcs_packet_fifo.o) + 0x00012ac0 0x00012ac0 0x00000024 Code RO 1189 i.dcs_packet_get_fifo_header CVWL668.lib(dcs_packet_fifo.o) + 0x00012ae4 0x00012ae4 0x00000018 Code RO 663 i.delayMs CVWL668.lib(tau_delay.o) + 0x00012afc 0x00012afc 0x0000002c Code RO 664 i.delayUs CVWL668.lib(tau_delay.o) + 0x00012b28 0x00012b28 0x00000008 Code RO 877 i.drv_common_system_init CVWL668.lib(drv_common.o) + 0x00012b30 0x00012b30 0x0000003c Code RO 896 i.drv_crgu_enable_clock CVWL668.lib(drv_crgu.o) + 0x00012b6c 0x00012b6c 0x00000068 Code RO 899 i.drv_crgu_get_rxbr_clk CVWL668.lib(drv_crgu.o) + 0x00012bd4 0x00012bd4 0x00000010 Code RO 902 i.drv_crgu_reset_modules CVWL668.lib(drv_crgu.o) + 0x00012be4 0x00012be4 0x00000028 Code RO 903 i.drv_crgu_set_ahb_clk CVWL668.lib(drv_crgu.o) + 0x00012c0c 0x00012c0c 0x00000010 Code RO 904 i.drv_crgu_set_clock_div CVWL668.lib(drv_crgu.o) + 0x00012c1c 0x00012c1c 0x0000003c Code RO 906 i.drv_crgu_set_dpi_clk CVWL668.lib(drv_crgu.o) + 0x00012c58 0x00012c58 0x00000038 Code RO 907 i.drv_crgu_set_dsc_clk CVWL668.lib(drv_crgu.o) + 0x00012c90 0x00012c90 0x00000028 Code RO 908 i.drv_crgu_set_fb_clk CVWL668.lib(drv_crgu.o) + 0x00012cb8 0x00012cb8 0x00000028 Code RO 909 i.drv_crgu_set_lcdc_clk CVWL668.lib(drv_crgu.o) + 0x00012ce0 0x00012ce0 0x00000018 Code RO 910 i.drv_crgu_set_reset CVWL668.lib(drv_crgu.o) + 0x00012cf8 0x00012cf8 0x00000028 Code RO 911 i.drv_crgu_set_rxbr_clk CVWL668.lib(drv_crgu.o) + 0x00012d20 0x00012d20 0x00000028 Code RO 912 i.drv_crgu_set_vidc_clk CVWL668.lib(drv_crgu.o) + 0x00012d48 0x00012d48 0x00000018 Code RO 1717 i.drv_dma_clear_status CVWL668.lib(drv_dma.o) + 0x00012d60 0x00012d60 0x00000014 Code RO 1723 i.drv_dma_get_int_source CVWL668.lib(drv_dma.o) + 0x00012d74 0x00012d74 0x0000001c Code RO 936 i.drv_dsc_dec_disable CVWL668.lib(drv_dsc_dec.o) + 0x00012d90 0x00012d90 0x00000038 Code RO 937 i.drv_dsc_dec_enable CVWL668.lib(drv_dsc_dec.o) + 0x00012dc8 0x00012dc8 0x00000020 Code RO 938 i.drv_dsc_dec_get_nslc CVWL668.lib(drv_dsc_dec.o) + 0x00012de8 0x00012de8 0x0000001c Code RO 939 i.drv_dsc_dec_set_irqen CVWL668.lib(drv_dsc_dec.o) + 0x00012e04 0x00012e04 0x0000010c Code RO 1221 i.drv_dsi_rx_calc_ipi_tx_delay CVWL668.lib(drv_dsi_rx.o) + 0x00012f10 0x00012f10 0x00000040 Code RO 1222 i.drv_dsi_rx_enable_irq CVWL668.lib(drv_dsi_rx.o) + 0x00012f50 0x00012f50 0x00000050 Code RO 1224 i.drv_dsi_rx_get_color_bpp CVWL668.lib(drv_dsi_rx.o) + 0x00012fa0 0x00012fa0 0x0000001c Code RO 1225 i.drv_dsi_rx_get_color_pcc CVWL668.lib(drv_dsi_rx.o) + 0x00012fbc 0x00012fbc 0x00000010 Code RO 1226 i.drv_dsi_rx_get_compression_en CVWL668.lib(drv_dsi_rx.o) + 0x00012fcc 0x00012fcc 0x00000010 Code RO 1227 i.drv_dsi_rx_get_ddi_crc_en CVWL668.lib(drv_dsi_rx.o) + 0x00012fdc 0x00012fdc 0x0000000c Code RO 1229 i.drv_dsi_rx_get_max_ret_size CVWL668.lib(drv_dsi_rx.o) + 0x00012fe8 0x00012fe8 0x00000018 Code RO 1232 i.drv_dsi_rx_power_up CVWL668.lib(drv_dsi_rx.o) + 0x00013000 0x00013000 0x0000001c Code RO 1233 i.drv_dsi_rx_set_check_crc CVWL668.lib(drv_dsi_rx.o) + 0x0001301c 0x0001301c 0x00000024 Code RO 1234 i.drv_dsi_rx_set_ctrl_cfg CVWL668.lib(drv_dsi_rx.o) + 0x00013040 0x00013040 0x00000010 Code RO 1235 i.drv_dsi_rx_set_ddi_cfg CVWL668.lib(drv_dsi_rx.o) + 0x00013050 0x00013050 0x0000001c Code RO 1236 i.drv_dsi_rx_set_ddi_crc_en CVWL668.lib(drv_dsi_rx.o) + 0x0001306c 0x0001306c 0x0000000c Code RO 1239 i.drv_dsi_rx_set_inten CVWL668.lib(drv_dsi_rx.o) + 0x00013078 0x00013078 0x00000010 Code RO 1240 i.drv_dsi_rx_set_ipi_cfg CVWL668.lib(drv_dsi_rx.o) + 0x00013088 0x00013088 0x0000001c Code RO 1242 i.drv_dsi_rx_set_ipi_ycbcr_frmt CVWL668.lib(drv_dsi_rx.o) + 0x000130a4 0x000130a4 0x00000014 Code RO 1243 i.drv_dsi_rx_set_lane_swap CVWL668.lib(drv_dsi_rx.o) + 0x000130b8 0x000130b8 0x00000024 Code RO 1244 i.drv_dsi_rx_set_resp_cnt CVWL668.lib(drv_dsi_rx.o) + 0x000130dc 0x000130dc 0x0000001c Code RO 1245 i.drv_dsi_rx_set_tear_resp_en CVWL668.lib(drv_dsi_rx.o) + 0x000130f8 0x000130f8 0x00000100 Code RO 1246 i.drv_dsi_rx_set_up_phy CVWL668.lib(drv_dsi_rx.o) + 0x000131f8 0x000131f8 0x00000018 Code RO 1247 i.drv_dsi_rx_shut_down CVWL668.lib(drv_dsi_rx.o) + 0x00013210 0x00013210 0x00000018 Code RO 1283 i.drv_dsi_tx_command_header CVWL668.lib(drv_dsi_tx.o) + 0x00013228 0x00013228 0x00000058 Code RO 1284 i.drv_dsi_tx_command_mode_cfg CVWL668.lib(drv_dsi_tx.o) + 0x00013280 0x00013280 0x0000000c Code RO 1285 i.drv_dsi_tx_command_put_payload CVWL668.lib(drv_dsi_tx.o) + 0x0001328c 0x0001328c 0x00000020 Code RO 1286 i.drv_dsi_tx_config_eotp CVWL668.lib(drv_dsi_tx.o) + 0x000132ac 0x000132ac 0x0000000c Code RO 1287 i.drv_dsi_tx_config_int CVWL668.lib(drv_dsi_tx.o) + 0x000132b8 0x000132b8 0x00000010 Code RO 1288 i.drv_dsi_tx_dpi_lpcmd_time CVWL668.lib(drv_dsi_tx.o) + 0x000132c8 0x000132c8 0x00000010 Code RO 1289 i.drv_dsi_tx_dpi_mode CVWL668.lib(drv_dsi_tx.o) + 0x000132d8 0x000132d8 0x00000024 Code RO 1290 i.drv_dsi_tx_dpi_polarity CVWL668.lib(drv_dsi_tx.o) + 0x000132fc 0x000132fc 0x0000000c Code RO 1291 i.drv_dsi_tx_edpi_cmd_size CVWL668.lib(drv_dsi_tx.o) + 0x00013308 0x00013308 0x0000000c Code RO 1293 i.drv_dsi_tx_get_cmd_status CVWL668.lib(drv_dsi_tx.o) + 0x00013314 0x00013314 0x0000000c Code RO 1295 i.drv_dsi_tx_mode CVWL668.lib(drv_dsi_tx.o) + 0x00013320 0x00013320 0x0000001c Code RO 1296 i.drv_dsi_tx_phy_clock_lane_auto_lp CVWL668.lib(drv_dsi_tx.o) + 0x0001333c 0x0001333c 0x00000020 Code RO 1297 i.drv_dsi_tx_phy_clock_lane_req_hs CVWL668.lib(drv_dsi_tx.o) + 0x0001335c 0x0001335c 0x00000010 Code RO 1299 i.drv_dsi_tx_phy_lane_mode CVWL668.lib(drv_dsi_tx.o) + 0x0001336c 0x0001336c 0x00000068 Code RO 1302 i.drv_dsi_tx_phy_status_ready CVWL668.lib(drv_dsi_tx.o) + 0x000133d4 0x000133d4 0x00000044 Code RO 1303 i.drv_dsi_tx_phy_status_stopstate CVWL668.lib(drv_dsi_tx.o) + 0x00013418 0x00013418 0x00000150 Code RO 1305 i.drv_dsi_tx_phy_test_setup CVWL668.lib(drv_dsi_tx.o) + 0x00013568 0x00013568 0x00000020 Code RO 1306 i.drv_dsi_tx_phy_time_cfg CVWL668.lib(drv_dsi_tx.o) + 0x00013588 0x00013588 0x0000000c Code RO 1310 i.drv_dsi_tx_powerup CVWL668.lib(drv_dsi_tx.o) + 0x00013594 0x00013594 0x00000024 Code RO 1311 i.drv_dsi_tx_response_mode CVWL668.lib(drv_dsi_tx.o) + 0x000135b8 0x000135b8 0x0000001c Code RO 1314 i.drv_dsi_tx_set_bta_ack CVWL668.lib(drv_dsi_tx.o) + 0x000135d4 0x000135d4 0x00000014 Code RO 1315 i.drv_dsi_tx_set_esc_div CVWL668.lib(drv_dsi_tx.o) + 0x000135e8 0x000135e8 0x00000040 Code RO 1316 i.drv_dsi_tx_set_int CVWL668.lib(drv_dsi_tx.o) + 0x00013628 0x00013628 0x00000018 Code RO 1317 i.drv_dsi_tx_set_time_out_div CVWL668.lib(drv_dsi_tx.o) + 0x00013640 0x00013640 0x00000014 Code RO 1318 i.drv_dsi_tx_set_video_chunk CVWL668.lib(drv_dsi_tx.o) + 0x00013654 0x00013654 0x00000024 Code RO 1319 i.drv_dsi_tx_set_video_timing CVWL668.lib(drv_dsi_tx.o) + 0x00013678 0x00013678 0x0000000c Code RO 1321 i.drv_dsi_tx_shutdown CVWL668.lib(drv_dsi_tx.o) + 0x00013684 0x00013684 0x0000002c Code RO 1322 i.drv_dsi_tx_timeout_cfg CVWL668.lib(drv_dsi_tx.o) + 0x000136b0 0x000136b0 0x000000e8 Code RO 1325 i.drv_dsi_tx_video_mode_cfg CVWL668.lib(drv_dsi_tx.o) + 0x00013798 0x00013798 0x00000036 Code RO 1823 i.drv_efuse_enter_inactive CVWL668.lib(drv_efuse.o) + 0x000137ce 0x000137ce 0x0000000c Code RO 1826 i.drv_efuse_int_enable CVWL668.lib(drv_efuse.o) + 0x000137da 0x000137da 0x0000003a Code RO 1827 i.drv_efuse_read CVWL668.lib(drv_efuse.o) + 0x00013814 0x00013814 0x00000018 Code RO 1828 i.drv_efuse_read_req CVWL668.lib(drv_efuse.o) + 0x0001382c 0x0001382c 0x00000024 Code RO 959 i.drv_gpio_handle_int CVWL668.lib(drv_gpio.o) + 0x00013850 0x00013850 0x0000000c Code RO 960 i.drv_gpio_register_ap_reset_callback CVWL668.lib(drv_gpio.o) + 0x0001385c 0x0001385c 0x00000014 Code RO 961 i.drv_gpio_register_callback CVWL668.lib(drv_gpio.o) + 0x00013870 0x00013870 0x00000044 Code RO 963 i.drv_gpio_set_int CVWL668.lib(drv_gpio.o) + 0x000138b4 0x000138b4 0x00000020 Code RO 964 i.drv_gpio_set_ioe CVWL668.lib(drv_gpio.o) + 0x000138d4 0x000138d4 0x00000014 Code RO 965 i.drv_gpio_set_mode CVWL668.lib(drv_gpio.o) + 0x000138e8 0x000138e8 0x00000020 Code RO 518 i.drv_gpio_set_output_data CVWL668.lib(hal_gpio.o) + 0x00013908 0x00013908 0x00000028 Code RO 1387 i.drv_lcdc_bcsa_config CVWL668.lib(drv_lcdc.o) + 0x00013930 0x00013930 0x0000002c Code RO 1388 i.drv_lcdc_cfg_int_frame CVWL668.lib(drv_lcdc.o) + 0x0001395c 0x0001395c 0x00000018 Code RO 1389 i.drv_lcdc_clear_int CVWL668.lib(drv_lcdc.o) + 0x00013974 0x00013974 0x00000034 Code RO 1391 i.drv_lcdc_cmd_start CVWL668.lib(drv_lcdc.o) + 0x000139a8 0x000139a8 0x00000014 Code RO 1392 i.drv_lcdc_config_acc_command_mode CVWL668.lib(drv_lcdc.o) + 0x000139bc 0x000139bc 0x00000038 Code RO 1393 i.drv_lcdc_config_int CVWL668.lib(drv_lcdc.o) + 0x000139f4 0x000139f4 0x00000028 Code RO 1394 i.drv_lcdc_config_int_single CVWL668.lib(drv_lcdc.o) + 0x00013a1c 0x00013a1c 0x00000018 Code RO 1395 i.drv_lcdc_config_overwrite_rgb CVWL668.lib(drv_lcdc.o) + 0x00013a34 0x00013a34 0x00000050 Code RO 1396 i.drv_lcdc_config_src_parameter CVWL668.lib(drv_lcdc.o) + 0x00013a84 0x00013a84 0x00000010 Code RO 1397 i.drv_lcdc_crop_hact CVWL668.lib(drv_lcdc.o) + 0x00013a94 0x00013a94 0x00000038 Code RO 1398 i.drv_lcdc_ctrl_flow CVWL668.lib(drv_lcdc.o) + 0x00013acc 0x00013acc 0x00000030 Code RO 1399 i.drv_lcdc_dith_config CVWL668.lib(drv_lcdc.o) + 0x00013afc 0x00013afc 0x0000003c Code RO 1401 i.drv_lcdc_edge_dect_config CVWL668.lib(drv_lcdc.o) + 0x00013b38 0x00013b38 0x00000064 Code RO 1402 i.drv_lcdc_edge_enh_config CVWL668.lib(drv_lcdc.o) + 0x00013b9c 0x00013b9c 0x00000024 Code RO 1403 i.drv_lcdc_enable_shadow_reg CVWL668.lib(drv_lcdc.o) + 0x00013bc0 0x00013bc0 0x0000001c Code RO 1404 i.drv_lcdc_endianness_config CVWL668.lib(drv_lcdc.o) + 0x00013bdc 0x00013bdc 0x00000020 Code RO 1405 i.drv_lcdc_fc_config CVWL668.lib(drv_lcdc.o) + 0x00013bfc 0x00013bfc 0x00000024 Code RO 1407 i.drv_lcdc_fldc_config CVWL668.lib(drv_lcdc.o) + 0x00013c20 0x00013c20 0x00000024 Code RO 1408 i.drv_lcdc_function_disable CVWL668.lib(drv_lcdc.o) + 0x00013c44 0x00013c44 0x00000024 Code RO 1409 i.drv_lcdc_function_enable CVWL668.lib(drv_lcdc.o) + 0x00013c68 0x00013c68 0x0000003c Code RO 1420 i.drv_lcdc_set_int CVWL668.lib(drv_lcdc.o) + 0x00013ca4 0x00013ca4 0x0000001c Code RO 1421 i.drv_lcdc_set_prefetch CVWL668.lib(drv_lcdc.o) + 0x00013cc0 0x00013cc0 0x0000001c Code RO 1422 i.drv_lcdc_set_tear_line CVWL668.lib(drv_lcdc.o) + 0x00013cdc 0x00013cdc 0x00000010 Code RO 1424 i.drv_lcdc_stop_display CVWL668.lib(drv_lcdc.o) + 0x00013cec 0x00013cec 0x0000003c Code RO 1426 i.drv_lcdc_vid_hw_start CVWL668.lib(drv_lcdc.o) + 0x00013d28 0x00013d28 0x00000018 Code RO 1428 i.drv_lcdc_vintp_mode_config CVWL668.lib(drv_lcdc.o) + 0x00013d40 0x00013d40 0x00000014 Code RO 1476 i.drv_memc_clear_status CVWL668.lib(drv_memc.o) + 0x00013d54 0x00013d54 0x00000040 Code RO 1477 i.drv_memc_enable_irq CVWL668.lib(drv_memc.o) + 0x00013d94 0x00013d94 0x00000010 Code RO 1478 i.drv_memc_gen_a_tear_signal CVWL668.lib(drv_memc.o) + 0x00013da4 0x00013da4 0x00000018 Code RO 1479 i.drv_memc_get_status CVWL668.lib(drv_memc.o) + 0x00013dbc 0x00013dbc 0x00000010 Code RO 1480 i.drv_memc_get_tear_mode CVWL668.lib(drv_memc.o) + 0x00013dcc 0x00013dcc 0x0000001c Code RO 1481 i.drv_memc_rate_transfer_sel CVWL668.lib(drv_memc.o) + 0x00013de8 0x00013de8 0x00000014 Code RO 1482 i.drv_memc_sel_vsync CVWL668.lib(drv_memc.o) + 0x00013dfc 0x00013dfc 0x00000018 Code RO 1483 i.drv_memc_set_active_height CVWL668.lib(drv_memc.o) + 0x00013e14 0x00013e14 0x0000001c Code RO 1484 i.drv_memc_set_circ_mode_enable CVWL668.lib(drv_memc.o) + 0x00013e30 0x00013e30 0x00000014 Code RO 1485 i.drv_memc_set_data_mode CVWL668.lib(drv_memc.o) + 0x00013e44 0x00013e44 0x00000018 Code RO 1488 i.drv_memc_set_double_buffer CVWL668.lib(drv_memc.o) + 0x00013e5c 0x00013e5c 0x0000001c Code RO 1492 i.drv_memc_set_frame_drop_select CVWL668.lib(drv_memc.o) + 0x00013e78 0x00013e78 0x00000018 Code RO 1493 i.drv_memc_set_fs_en_conditions CVWL668.lib(drv_memc.o) + 0x00013e90 0x00013e90 0x0000001c Code RO 1495 i.drv_memc_set_lcdc_st_conditions CVWL668.lib(drv_memc.o) + 0x00013eac 0x00013eac 0x00000020 Code RO 1496 i.drv_memc_set_ltpo_mode CVWL668.lib(drv_memc.o) + 0x00013ecc 0x00013ecc 0x00000018 Code RO 1497 i.drv_memc_set_ltpo_pu_thres CVWL668.lib(drv_memc.o) + 0x00013ee4 0x00013ee4 0x00000014 Code RO 1501 i.drv_memc_set_tear_mode CVWL668.lib(drv_memc.o) + 0x00013ef8 0x00013ef8 0x0000002c Code RO 1502 i.drv_memc_set_tear_waveform CVWL668.lib(drv_memc.o) + 0x00013f24 0x00013f24 0x00000014 Code RO 1504 i.drv_memc_set_vidc_sync_cnt CVWL668.lib(drv_memc.o) + 0x00013f38 0x00013f38 0x00000010 Code RO 1846 i.drv_phy_test_clear CVWL668.lib(drv_phy_common.o) + 0x00013f48 0x00013f48 0x00000018 Code RO 1847 i.drv_phy_test_lock CVWL668.lib(drv_phy_common.o) + 0x00013f60 0x00013f60 0x00000030 Code RO 995 i.drv_pwr_efuse_pd CVWL668.lib(drv_pwr.o) + 0x00013f90 0x00013f90 0x0000004c Code RO 997 i.drv_pwr_enter_deep_sleep_mode CVWL668.lib(drv_pwr.o) + 0x00013fdc 0x00013fdc 0x00000034 Code RO 999 i.drv_pwr_enter_sleep_mode_ex CVWL668.lib(drv_pwr.o) + 0x00014010 0x00014010 0x00000098 Code RO 1000 i.drv_pwr_enter_stop_sleep_mode CVWL668.lib(drv_pwr.o) + 0x000140a8 0x000140a8 0x00000028 Code RO 1001 i.drv_pwr_exit_sleep_mode CVWL668.lib(drv_pwr.o) + 0x000140d0 0x000140d0 0x00000010 Code RO 1004 i.drv_pwr_get_power_ready_st CVWL668.lib(drv_pwr.o) + 0x000140e0 0x000140e0 0x00000028 Code RO 1036 i.drv_pwr_set_breath_screen_power_sel CVWL668.lib(drv_pwr.o) + 0x00014108 0x00014108 0x00000028 Code RO 1037 i.drv_pwr_set_digit_power_sel CVWL668.lib(drv_pwr.o) + 0x00014130 0x00014130 0x00000034 Code RO 1040 i.drv_pwr_set_pll_clk CVWL668.lib(drv_pwr.o) + 0x00014164 0x00014164 0x0000002c Code RO 1044 i.drv_pwr_set_wakeup_type CVWL668.lib(drv_pwr.o) + 0x00014190 0x00014190 0x00000020 Code RO 1047 i.drv_pwr_write_lock CVWL668.lib(drv_pwr.o) + 0x000141b0 0x000141b0 0x00000010 Code RO 1544 i.drv_rxbr_clear_pkt_buffer CVWL668.lib(drv_rxbr.o) + 0x000141c0 0x000141c0 0x0000000c Code RO 1545 i.drv_rxbr_clear_status0 CVWL668.lib(drv_rxbr.o) + 0x000141cc 0x000141cc 0x0000005a Code RO 1548 i.drv_rxbr_enable_irq CVWL668.lib(drv_rxbr.o) + 0x00014226 0x00014226 0x00000002 PAD + 0x00014228 0x00014228 0x0000001c Code RO 1549 i.drv_rxbr_frame_drop_cfg CVWL668.lib(drv_rxbr.o) + 0x00014244 0x00014244 0x00000018 Code RO 722 i.drv_rxbr_get_int_source CVWL668.lib(hal_internal_vsync.o) + 0x0001425c 0x0001425c 0x00000018 Code RO 784 i.drv_rxbr_get_status0 CVWL668.lib(hal_internal_dcs.o) + 0x00014274 0x00014274 0x00000014 Code RO 1559 i.drv_rxbr_hline_rcv1_cfg CVWL668.lib(drv_rxbr.o) + 0x00014288 0x00014288 0x00000010 Code RO 1560 i.drv_rxbr_hline_rcv_cfg CVWL668.lib(drv_rxbr.o) + 0x00014298 0x00014298 0x0000000c Code RO 1562 i.drv_rxbr_register_irq1_callback CVWL668.lib(drv_rxbr.o) + 0x000142a4 0x000142a4 0x00000018 Code RO 1563 i.drv_rxbr_set_ack_pkt_header CVWL668.lib(drv_rxbr.o) + 0x000142bc 0x000142bc 0x0000001c Code RO 1568 i.drv_rxbr_set_color_format CVWL668.lib(drv_rxbr.o) + 0x000142d8 0x000142d8 0x00000024 Code RO 1571 i.drv_rxbr_set_filter_regs CVWL668.lib(drv_rxbr.o) + 0x000142fc 0x000142fc 0x0000001c Code RO 1572 i.drv_rxbr_set_inten CVWL668.lib(drv_rxbr.o) + 0x00014318 0x00014318 0x00000018 Code RO 1573 i.drv_rxbr_set_ltpo_drop_th CVWL668.lib(drv_rxbr.o) + 0x00014330 0x00014330 0x00000040 Code RO 1577 i.drv_rxbr_set_usr_cfg CVWL668.lib(drv_rxbr.o) + 0x00014370 0x00014370 0x00000010 Code RO 1578 i.drv_rxbr_set_usr_col CVWL668.lib(drv_rxbr.o) + 0x00014380 0x00014380 0x00000010 Code RO 1579 i.drv_rxbr_set_usr_row CVWL668.lib(drv_rxbr.o) + 0x00014390 0x00014390 0x00000078 Code RO 1201 i.drv_se_init CVWL668.lib(drv_se.o) + 0x00014408 0x00014408 0x000000d4 Code RO 1202 i.drv_se_set_dsc CVWL668.lib(drv_se.o) + 0x000144dc 0x000144dc 0x00000088 Code RO 1203 i.drv_se_set_lcdc CVWL668.lib(drv_se.o) + 0x00014564 0x00014564 0x00000090 Code RO 1204 i.drv_se_set_memc CVWL668.lib(drv_se.o) + 0x000145f4 0x000145f4 0x000000d0 Code RO 1205 i.drv_se_set_rxbr CVWL668.lib(drv_se.o) + 0x000146c4 0x000146c4 0x000000ac Code RO 1206 i.drv_se_set_vidc CVWL668.lib(drv_se.o) + 0x00014770 0x00014770 0x00000014 Code RO 1207 i.drv_se_start_rx CVWL668.lib(drv_se.o) + 0x00014784 0x00014784 0x0000001c Code RO 1111 i.drv_swire_enable CVWL668.lib(drv_swire.o) + 0x000147a0 0x000147a0 0x0000000c Code RO 1112 i.drv_swire_get_pulse_count CVWL668.lib(drv_swire.o) + 0x000147ac 0x000147ac 0x0000000c Code RO 1113 i.drv_swire_register_callback CVWL668.lib(drv_swire.o) + 0x000147b8 0x000147b8 0x00000018 Code RO 1114 i.drv_swire_set_bit_time CVWL668.lib(drv_swire.o) + 0x000147d0 0x000147d0 0x00000048 Code RO 1115 i.drv_swire_set_int CVWL668.lib(drv_swire.o) + 0x00014818 0x00014818 0x0000001c Code RO 1116 i.drv_swire_set_power_down CVWL668.lib(drv_swire.o) + 0x00014834 0x00014834 0x0000000c Code RO 1117 i.drv_swire_set_pulse_count CVWL668.lib(drv_swire.o) + 0x00014840 0x00014840 0x0000001c Code RO 1118 i.drv_swire_set_trig_mode CVWL668.lib(drv_swire.o) + 0x0001485c 0x0001485c 0x0000000c Code RO 1133 i.drv_sys_cfg_clear_all_int CVWL668.lib(drv_sys_cfg.o) + 0x00014868 0x00014868 0x00000028 Code RO 1134 i.drv_sys_cfg_clear_pending CVWL668.lib(drv_sys_cfg.o) + 0x00014890 0x00014890 0x00000024 Code RO 1135 i.drv_sys_cfg_sel_ap_rst_trig CVWL668.lib(drv_sys_cfg.o) + 0x000148b4 0x000148b4 0x00000024 Code RO 1137 i.drv_sys_cfg_sel_gpio_group CVWL668.lib(drv_sys_cfg.o) + 0x000148d8 0x000148d8 0x00000024 Code RO 1138 i.drv_sys_cfg_sel_int_trig CVWL668.lib(drv_sys_cfg.o) + 0x000148fc 0x000148fc 0x00000018 Code RO 1139 i.drv_sys_cfg_sel_swire_timer CVWL668.lib(drv_sys_cfg.o) + 0x00014914 0x00014914 0x00000024 Code RO 1140 i.drv_sys_cfg_set_int CVWL668.lib(drv_sys_cfg.o) + 0x00014938 0x00014938 0x0000001a Code RO 1157 i.drv_timer_clear_status_flags CVWL668.lib(drv_timer.o) + 0x00014952 0x00014952 0x00000020 Code RO 1158 i.drv_timer_enable CVWL668.lib(drv_timer.o) + 0x00014972 0x00014972 0x00000002 PAD + 0x00014974 0x00014974 0x00000010 Code RO 1159 i.drv_timer_get_instance CVWL668.lib(drv_timer.o) + 0x00014984 0x00014984 0x0000003c Code RO 1161 i.drv_timer_handle_interrupt CVWL668.lib(drv_timer.o) + 0x000149c0 0x000149c0 0x00000040 Code RO 1163 i.drv_timer_set_compare_val CVWL668.lib(drv_timer.o) + 0x00014a00 0x00014a00 0x00000048 Code RO 1164 i.drv_timer_set_int CVWL668.lib(drv_timer.o) + 0x00014a48 0x00014a48 0x00000028 Code RO 1165 i.drv_timer_set_prescaler CVWL668.lib(drv_timer.o) + 0x00014a70 0x00014a70 0x00000010 Code RO 1166 i.drv_timer_set_repeat CVWL668.lib(drv_timer.o) + 0x00014a80 0x00014a80 0x00000020 Code RO 1327 i.drv_tx_phy_test_enter CVWL668.lib(drv_dsi_tx.o) + 0x00014aa0 0x00014aa0 0x00000020 Code RO 1328 i.drv_tx_phy_test_exit CVWL668.lib(drv_dsi_tx.o) + 0x00014ac0 0x00014ac0 0x00000028 Code RO 1331 i.drv_tx_phy_test_write_code CVWL668.lib(drv_dsi_tx.o) + 0x00014ae8 0x00014ae8 0x00000034 Code RO 1779 i.drv_uart_abort_recv CVWL668.lib(drv_uart.o) + 0x00014b1c 0x00014b1c 0x00000034 Code RO 1780 i.drv_uart_abort_send CVWL668.lib(drv_uart.o) + 0x00014b50 0x00014b50 0x00000014 Code RO 1781 i.drv_uart_config_int CVWL668.lib(drv_uart.o) + 0x00014b64 0x00014b64 0x00000018 Code RO 1783 i.drv_uart_enable_clk CVWL668.lib(drv_uart.o) + 0x00014b7c 0x00014b7c 0x0000005c Code RO 1784 i.drv_uart_enable_int CVWL668.lib(drv_uart.o) + 0x00014bd8 0x00014bd8 0x00000028 Code RO 1786 i.drv_uart_get_instance CVWL668.lib(drv_uart.o) + 0x00014c00 0x00014c00 0x000000ce Code RO 1787 i.drv_uart_init CVWL668.lib(drv_uart.o) + 0x00014cce 0x00014cce 0x00000002 PAD + 0x00014cd0 0x00014cd0 0x0000003c Code RO 1788 i.drv_uart_int_trans_handle CVWL668.lib(drv_uart.o) + 0x00014d0c 0x00014d0c 0x0000001c Code RO 1791 i.drv_uart_reset_rx_fifo CVWL668.lib(drv_uart.o) + 0x00014d28 0x00014d28 0x0000001c Code RO 1792 i.drv_uart_reset_tx_fifo CVWL668.lib(drv_uart.o) + 0x00014d44 0x00014d44 0x0000001a Code RO 1793 i.drv_uart_send_blocking CVWL668.lib(drv_uart.o) + 0x00014d5e 0x00014d5e 0x00000054 Code RO 1795 i.drv_uart_set_baud_rate CVWL668.lib(drv_uart.o) + 0x00014db2 0x00014db2 0x00000002 PAD + 0x00014db4 0x00014db4 0x0000004c Code RO 1796 i.drv_uart_trans_create_handle CVWL668.lib(drv_uart.o) + 0x00014e00 0x00014e00 0x00000010 Code RO 1631 i.drv_vidc_clear_irq CVWL668.lib(drv_vidc.o) + 0x00014e10 0x00014e10 0x00000020 Code RO 1635 i.drv_vidc_enable CVWL668.lib(drv_vidc.o) + 0x00014e30 0x00014e30 0x00000040 Code RO 1636 i.drv_vidc_enable_irq CVWL668.lib(drv_vidc.o) + 0x00014e70 0x00014e70 0x0000002c Code RO 1637 i.drv_vidc_get_int_source CVWL668.lib(drv_vidc.o) + 0x00014e9c 0x00014e9c 0x00000018 Code RO 1638 i.drv_vidc_get_irq_status CVWL668.lib(drv_vidc.o) + 0x00014eb4 0x00014eb4 0x0000002c Code RO 1642 i.drv_vidc_init_module_enable CVWL668.lib(drv_vidc.o) + 0x00014ee0 0x00014ee0 0x0000000c Code RO 1643 i.drv_vidc_register_callback CVWL668.lib(drv_vidc.o) + 0x00014eec 0x00014eec 0x0000000c Code RO 1644 i.drv_vidc_reset CVWL668.lib(drv_vidc.o) + 0x00014ef8 0x00014ef8 0x0000001c Code RO 1645 i.drv_vidc_set_circ_mode_enable CVWL668.lib(drv_vidc.o) + 0x00014f14 0x00014f14 0x00000038 Code RO 1646 i.drv_vidc_set_dither_config CVWL668.lib(drv_vidc.o) + 0x00014f4c 0x00014f4c 0x0000005c Code RO 1648 i.drv_vidc_set_dst_parameter CVWL668.lib(drv_vidc.o) + 0x00014fa8 0x00014fa8 0x0000000c Code RO 1650 i.drv_vidc_set_honly_hcoef0 CVWL668.lib(drv_vidc.o) + 0x00014fb4 0x00014fb4 0x0000002c Code RO 1651 i.drv_vidc_set_honly_hinitb CVWL668.lib(drv_vidc.o) + 0x00014fe0 0x00014fe0 0x00000030 Code RO 1652 i.drv_vidc_set_honly_hinitr CVWL668.lib(drv_vidc.o) + 0x00015010 0x00015010 0x0000001c Code RO 1655 i.drv_vidc_set_irqen CVWL668.lib(drv_vidc.o) + 0x0001502c 0x0001502c 0x00000014 Code RO 1656 i.drv_vidc_set_mirror CVWL668.lib(drv_vidc.o) + 0x00015040 0x00015040 0x0000001c Code RO 1659 i.drv_vidc_set_pentile_swap CVWL668.lib(drv_vidc.o) + 0x0001505c 0x0001505c 0x0000000c Code RO 1660 i.drv_vidc_set_pu_ctrl CVWL668.lib(drv_vidc.o) + 0x00015068 0x00015068 0x00000018 Code RO 1661 i.drv_vidc_set_rotation CVWL668.lib(drv_vidc.o) + 0x00015080 0x00015080 0x0000000c Code RO 1662 i.drv_vidc_set_scld_hcoef0 CVWL668.lib(drv_vidc.o) + 0x0001508c 0x0001508c 0x0000000c Code RO 1663 i.drv_vidc_set_scld_hcoef1 CVWL668.lib(drv_vidc.o) + 0x00015098 0x00015098 0x00000014 Code RO 1664 i.drv_vidc_set_scld_step CVWL668.lib(drv_vidc.o) + 0x000150ac 0x000150ac 0x0000000c Code RO 1665 i.drv_vidc_set_scld_vcoef0 CVWL668.lib(drv_vidc.o) + 0x000150b8 0x000150b8 0x0000000c Code RO 1666 i.drv_vidc_set_scld_vcoef1 CVWL668.lib(drv_vidc.o) + 0x000150c4 0x000150c4 0x00000020 Code RO 1667 i.drv_vidc_set_src_parameter CVWL668.lib(drv_vidc.o) + 0x000150e4 0x000150e4 0x00000038 Code RO 1668 i.drv_vidc_set_vintp_config CVWL668.lib(drv_vidc.o) + 0x0001511c 0x0001511c 0x00000034 Code RO 672 i.fputc CVWL668.lib(tau_log.o) + 0x00015150 0x00015150 0x00000060 Code RO 116 i.google_p8p_demo p8p_demo.o + 0x000151b0 0x000151b0 0x00000040 Code RO 812 i.ha_intl_fb_check_pu_size CVWL668.lib(hal_internal_fb.o) + 0x000151f0 0x000151f0 0x00000040 Code RO 332 i.hal_dsi_rx_ctrl_create_handle CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015230 0x00015230 0x00000040 Code RO 333 i.hal_dsi_rx_ctrl_dcs_async_handler CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015270 0x00015270 0x00000094 Code RO 334 i.hal_dsi_rx_ctrl_deinit CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015304 0x00015304 0x00000020 Code RO 339 i.hal_dsi_rx_ctrl_get_max_ret_size CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015324 0x00015324 0x000000ac Code RO 340 i.hal_dsi_rx_ctrl_init CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x000153d0 0x000153d0 0x00000100 Code RO 341 i.hal_dsi_rx_ctrl_init_clk CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x000154d0 0x000154d0 0x000000f8 Code RO 342 i.hal_dsi_rx_ctrl_init_dsi_rx CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x000155c8 0x000155c8 0x0000012c Code RO 343 i.hal_dsi_rx_ctrl_init_memc CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x000156f4 0x000156f4 0x00000148 Code RO 344 i.hal_dsi_rx_ctrl_init_rxbr CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x0001583c 0x0001583c 0x00000280 Code RO 345 i.hal_dsi_rx_ctrl_init_vidc CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015abc 0x00015abc 0x00000038 Code RO 346 i.hal_dsi_rx_ctrl_pre_init_pps CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015af4 0x00015af4 0x000000f0 Code RO 351 i.hal_dsi_rx_ctrl_send_ack_cmd CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015be4 0x00015be4 0x00000030 Code RO 357 i.hal_dsi_rx_ctrl_set_ipi_cfg CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015c14 0x00015c14 0x00000030 Code RO 362 i.hal_dsi_rx_ctrl_start CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015c44 0x00015c44 0x00000030 Code RO 363 i.hal_dsi_rx_ctrl_stop CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015c74 0x00015c74 0x00000020 Code RO 365 i.hal_dsi_rx_ctrl_toggle_resolution CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015c94 0x00015c94 0x0000027c Code RO 412 i.hal_dsi_tx_cmd_mode_cal_timing CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00015f10 0x00015f10 0x00000038 Code RO 414 i.hal_dsi_tx_ctrl_create_handle CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00015f48 0x00015f48 0x00000074 Code RO 415 i.hal_dsi_tx_ctrl_deinit CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00015fbc 0x00015fbc 0x00000022 Code RO 418 i.hal_dsi_tx_ctrl_gen_a_tear_signal CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00015fde 0x00015fde 0x00000002 PAD + 0x00015fe0 0x00015fe0 0x0000007c Code RO 420 i.hal_dsi_tx_ctrl_init CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001605c 0x0001605c 0x00000010 Code RO 421 i.hal_dsi_tx_ctrl_init_clk CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001606c 0x0001606c 0x00000008 Code RO 434 i.hal_dsi_tx_ctrl_set_overwrite_rgb CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00016074 0x00016074 0x0000000a Code RO 435 i.hal_dsi_tx_ctrl_set_tear_mode CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001607e 0x0001607e 0x00000002 PAD + 0x00016080 0x00016080 0x0000007c Code RO 437 i.hal_dsi_tx_ctrl_start CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000160fc 0x000160fc 0x00000038 Code RO 438 i.hal_dsi_tx_ctrl_stop CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00016134 0x00016134 0x000000f4 Code RO 440 i.hal_dsi_tx_ctrl_write_array_cmd CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00016228 0x00016228 0x000000d0 Code RO 441 i.hal_dsi_tx_ctrl_write_cmd CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000162f8 0x000162f8 0x0000010c Code RO 442 i.hal_dsi_tx_init_cfg CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00016404 0x00016404 0x00000038 Code RO 443 i.hal_dsi_tx_init_dpi_timing CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001643c 0x0001643c 0x00000016 Code RO 444 i.hal_dsi_tx_init_phy_cfg CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00016452 0x00016452 0x00000052 Code RO 445 i.hal_dsi_tx_init_timing CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000164a4 0x000164a4 0x00000054 Code RO 446 i.hal_dsi_tx_init_vid_timing CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000164f8 0x000164f8 0x00000040 Code RO 447 i.hal_dsi_tx_send_cmd CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00016538 0x00016538 0x00000094 Code RO 448 i.hal_dsi_tx_timing_info_update CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000165cc 0x000165cc 0x00000310 Code RO 449 i.hal_dsi_tx_vid_mode_cal_timing CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000168dc 0x000168dc 0x0000003a Code RO 519 i.hal_gpio_config_pad CVWL668.lib(hal_gpio.o) + 0x00016916 0x00016916 0x00000002 PAD + 0x00016918 0x00016918 0x00000018 Code RO 520 i.hal_gpio_ctrl_eint CVWL668.lib(hal_gpio.o) + 0x00016930 0x00016930 0x00000040 Code RO 524 i.hal_gpio_init_eint CVWL668.lib(hal_gpio.o) + 0x00016970 0x00016970 0x00000016 Code RO 525 i.hal_gpio_init_input CVWL668.lib(hal_gpio.o) + 0x00016986 0x00016986 0x0000001c Code RO 526 i.hal_gpio_init_output CVWL668.lib(hal_gpio.o) + 0x000169a2 0x000169a2 0x00000002 PAD + 0x000169a4 0x000169a4 0x0000001c Code RO 527 i.hal_gpio_reg_eint_cb CVWL668.lib(hal_gpio.o) + 0x000169c0 0x000169c0 0x00000050 Code RO 528 i.hal_gpio_set_ap_reset_int CVWL668.lib(hal_gpio.o) + 0x00016a10 0x00016a10 0x00000064 Code RO 531 i.hal_gpio_set_mode CVWL668.lib(hal_gpio.o) + 0x00016a74 0x00016a74 0x00000008 Code RO 532 i.hal_gpio_set_output_data CVWL668.lib(hal_gpio.o) + 0x00016a7c 0x00016a7c 0x00000010 Code RO 724 i.hal_internal_sync_get_hight_performan_mode CVWL668.lib(hal_internal_vsync.o) + 0x00016a8c 0x00016a8c 0x000001b4 Code RO 725 i.hal_internal_sync_input_resolution_change CVWL668.lib(hal_internal_vsync.o) + 0x00016c40 0x00016c40 0x0000000c Code RO 726 i.hal_internal_sync_register_lcdc_cb CVWL668.lib(hal_internal_vsync.o) + 0x00016c4c 0x00016c4c 0x00000020 Code RO 729 i.hal_internal_vsync_deinit CVWL668.lib(hal_internal_vsync.o) + 0x00016c6c 0x00016c6c 0x0000000c Code RO 730 i.hal_internal_vsync_get_rx_state CVWL668.lib(hal_internal_vsync.o) + 0x00016c78 0x00016c78 0x00000014 Code RO 731 i.hal_internal_vsync_get_sync_line CVWL668.lib(hal_internal_vsync.o) + 0x00016c8c 0x00016c8c 0x0000000c Code RO 732 i.hal_internal_vsync_get_tx_state CVWL668.lib(hal_internal_vsync.o) + 0x00016c98 0x00016c98 0x000000d8 Code RO 733 i.hal_internal_vsync_init_rx CVWL668.lib(hal_internal_vsync.o) + 0x00016d70 0x00016d70 0x000000c8 Code RO 734 i.hal_internal_vsync_init_tx CVWL668.lib(hal_internal_vsync.o) + 0x00016e38 0x00016e38 0x00000020 Code RO 735 i.hal_internal_vsync_set_rx_state CVWL668.lib(hal_internal_vsync.o) + 0x00016e58 0x00016e58 0x00000118 Code RO 737 i.hal_internal_vsync_set_tear_mode CVWL668.lib(hal_internal_vsync.o) + 0x00016f70 0x00016f70 0x0000006c Code RO 738 i.hal_internal_vsync_set_tx_state CVWL668.lib(hal_internal_vsync.o) + 0x00016fdc 0x00016fdc 0x0000006c Code RO 785 i.hal_intl_dcs_init_sw_fltr CVWL668.lib(hal_internal_dcs.o) + 0x00017048 0x00017048 0x0000044c Code RO 787 i.hal_intl_dcs_rx_get_dcs_packet_data CVWL668.lib(hal_internal_dcs.o) + 0x00017494 0x00017494 0x00000088 Code RO 788 i.hal_intl_dcs_rx_receive_packet CVWL668.lib(hal_internal_dcs.o) + 0x0001751c 0x0001751c 0x00000174 Code RO 789 i.hal_intl_dcs_rx_receive_pps CVWL668.lib(hal_internal_dcs.o) + 0x00017690 0x00017690 0x0000008c Code RO 790 i.hal_intl_dcs_set_auto_hw_filter CVWL668.lib(hal_internal_dcs.o) + 0x0001771c 0x0001771c 0x0000002c Code RO 792 i.hal_intl_dcs_sw_filter_handle CVWL668.lib(hal_internal_dcs.o) + 0x00017748 0x00017748 0x000002f0 Code RO 813 i.hal_intl_fb_cal_fb_info CVWL668.lib(hal_internal_fb.o) + 0x00017a38 0x00017a38 0x00000064 Code RO 814 i.hal_intl_fb_check_bandwidth CVWL668.lib(hal_internal_fb.o) + 0x00017a9c 0x00017a9c 0x000000dc Code RO 815 i.hal_intl_fb_edge_resize CVWL668.lib(hal_internal_fb.o) + 0x00017b78 0x00017b78 0x00000064 Code RO 816 i.hal_intl_fb_flow_control_adapter CVWL668.lib(hal_internal_fb.o) + 0x00017bdc 0x00017bdc 0x0000000c Code RO 817 i.hal_intl_fb_get_memc_flow_mode CVWL668.lib(hal_internal_fb.o) + 0x00017be8 0x00017be8 0x00000010 Code RO 818 i.hal_intl_fb_get_rx_fb_info CVWL668.lib(hal_internal_fb.o) + 0x00017bf8 0x00017bf8 0x00000010 Code RO 819 i.hal_intl_fb_get_tx_fb_info CVWL668.lib(hal_internal_fb.o) + 0x00017c08 0x00017c08 0x0000000c Code RO 820 i.hal_intl_fb_get_user_flow CVWL668.lib(hal_internal_fb.o) + 0x00017c14 0x00017c14 0x00000028 Code RO 838 i.hal_intl_svs_deinit_rx CVWL668.lib(hal_internal_svs.o) + 0x00017c3c 0x00017c3c 0x00000010 Code RO 839 i.hal_intl_svs_deinit_tx CVWL668.lib(hal_internal_svs.o) + 0x00017c4c 0x00017c4c 0x00000024 Code RO 840 i.hal_intl_svs_handle CVWL668.lib(hal_internal_svs.o) + 0x00017c70 0x00017c70 0x00000080 Code RO 841 i.hal_intl_svs_init_rx CVWL668.lib(hal_internal_svs.o) + 0x00017cf0 0x00017cf0 0x00000014 Code RO 842 i.hal_intl_svs_init_tx CVWL668.lib(hal_internal_svs.o) + 0x00017d04 0x00017d04 0x0000000c Code RO 844 i.hal_intl_svs_set_rx_vtt CVWL668.lib(hal_internal_svs.o) + 0x00017d10 0x00017d10 0x00000048 Code RO 846 i.hal_intl_svs_update_rxbr_clk CVWL668.lib(hal_internal_svs.o) + 0x00017d58 0x00017d58 0x00000070 Code RO 450 i.hal_lcdc_displayproc_config CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00017dc8 0x00017dc8 0x0000003e Code RO 451 i.hal_lcdc_init_cfg CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00017e06 0x00017e06 0x00000070 Code RO 452 i.hal_lcdc_init_clk CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00017e76 0x00017e76 0x00000002 PAD + 0x00017e78 0x00017e78 0x00000128 Code RO 453 i.hal_lcdc_postproc_config CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00017fa0 0x00017fa0 0x00000024 Code RO 454 i.hal_lcdc_start CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00017fc4 0x00017fc4 0x0000003c Code RO 455 i.hal_lcdc_timinggen_config CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00018000 0x00018000 0x000000e0 Code RO 456 i.hal_lcdc_upscaler_config CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000180e0 0x000180e0 0x000000bc Code RO 458 i.hal_nonshadow_func_update CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001819c 0x0001819c 0x0000002a Code RO 623 i.hal_pwr_enter_deep_sleep_mode CVWL668.lib(hal_pwr.o) + 0x000181c6 0x000181c6 0x00000008 Code RO 624 i.hal_pwr_enter_normal_sleep_mode CVWL668.lib(hal_pwr.o) + 0x000181ce 0x000181ce 0x00000002 PAD + 0x000181d0 0x000181d0 0x00000064 Code RO 625 i.hal_pwr_enter_stop_sleep_mode CVWL668.lib(hal_pwr.o) + 0x00018234 0x00018234 0x0000000a Code RO 626 i.hal_pwr_exit_sleep_mode CVWL668.lib(hal_pwr.o) + 0x0001823e 0x0001823e 0x00000008 Code RO 628 i.hal_pwr_get_vcc_power_ready CVWL668.lib(hal_pwr.o) + 0x00018246 0x00018246 0x00000008 Code RO 633 i.hal_pwr_set_main_power CVWL668.lib(hal_pwr.o) + 0x0001824e 0x0001824e 0x00000008 Code RO 635 i.hal_pwr_set_sleep_mode_power CVWL668.lib(hal_pwr.o) + 0x00018256 0x00018256 0x00000002 PAD + 0x00018258 0x00018258 0x00000064 Code RO 636 i.hal_pwr_set_stop_sleep_wakeup_pin CVWL668.lib(hal_pwr.o) + 0x000182bc 0x000182bc 0x00000040 Code RO 559 i.hal_swire_deinit CVWL668.lib(hal_swire.o) + 0x000182fc 0x000182fc 0x0000005c Code RO 560 i.hal_swire_enable CVWL668.lib(hal_swire.o) + 0x00018358 0x00018358 0x00000058 Code RO 561 i.hal_swire_init CVWL668.lib(hal_swire.o) + 0x000183b0 0x000183b0 0x00000024 Code RO 563 i.hal_swire_set_pulse CVWL668.lib(hal_swire.o) + 0x000183d4 0x000183d4 0x00000040 Code RO 564 i.hal_swire_set_timer CVWL668.lib(hal_swire.o) + 0x00018414 0x00018414 0x000000e4 Code RO 584 i.hal_system_init CVWL668.lib(hal_system.o) + 0x000184f8 0x000184f8 0x00000050 Code RO 587 i.hal_system_updata_sysclk CVWL668.lib(hal_system.o) + 0x00018548 0x00018548 0x00000030 Code RO 602 i.hal_timer_deinit CVWL668.lib(hal_timer.o) + 0x00018578 0x00018578 0x0000001c Code RO 604 i.hal_timer_init CVWL668.lib(hal_timer.o) + 0x00018594 0x00018594 0x00000008 Code RO 605 i.hal_timer_set_repeat CVWL668.lib(hal_timer.o) + 0x0001859c 0x0001859c 0x00000030 Code RO 459 i.hal_tx_frame_rate_adjust CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000185cc 0x000185cc 0x00000094 Code RO 696 i.hal_uart_init CVWL668.lib(hal_uart.o) + 0x00018660 0x00018660 0x0000001c Code RO 699 i.hal_uart_send_blocking CVWL668.lib(hal_uart.o) + 0x0001867c 0x0001867c 0x00000018 Code RO 460 i.hal_vsync_func_update CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00018694 0x00018694 0x000000cc Code RO 740 i.hal_vsync_reset_lcdc_scaler CVWL668.lib(hal_internal_vsync.o) + 0x00018760 0x00018760 0x00000040 Code RO 3 i.main main.o + 0x000187a0 0x000187a0 0x0000007c Code RO 117 i.pps_update_handle p8p_demo.o + 0x0001881c 0x0001881c 0x000002b8 Code RO 741 i.rxbr_irq1_callback CVWL668.lib(hal_internal_vsync.o) + 0x00018ad4 0x00018ad4 0x0000003a Code RO 118 i.send_panel_init_code p8p_demo.o + 0x00018b0e 0x00018b0e 0x00000002 PAD + 0x00018b10 0x00018b10 0x00000044 Code RO 742 i.soft_double_buffer_update CVWL668.lib(hal_internal_vsync.o) + 0x00018b54 0x00018b54 0x0000007c Code RO 743 i.soft_gen_te CVWL668.lib(hal_internal_vsync.o) + 0x00018bd0 0x00018bd0 0x00000094 Code RO 744 i.soft_gen_te_double_buffer CVWL668.lib(hal_internal_vsync.o) + 0x00018c64 0x00018c64 0x00000018 Code RO 638 i.stop_sleep_cb CVWL668.lib(hal_pwr.o) + 0x00018c7c 0x00018c7c 0x000000ac Code RO 847 i.svs_direct_mode_setting CVWL668.lib(hal_internal_svs.o) + 0x00018d28 0x00018d28 0x0000001c Code RO 848 i.svs_get_rel_intv CVWL668.lib(hal_internal_svs.o) + 0x00018d44 0x00018d44 0x000000b0 Code RO 849 i.svs_sync_handle CVWL668.lib(hal_internal_svs.o) + 0x00018df4 0x00018df4 0x000000cc Code RO 850 i.svs_wait_fr_stab CVWL668.lib(hal_internal_svs.o) + 0x00018ec0 0x00018ec0 0x0000010c Code RO 851 i.svs_wait_start CVWL668.lib(hal_internal_svs.o) + 0x00018fcc 0x00018fcc 0x00000034 Code RO 673 i.tau_log_init CVWL668.lib(tau_log.o) + 0x00019000 0x00019000 0x00000084 Code RO 674 i.tau_log_printf CVWL668.lib(tau_log.o) + 0x00019084 0x00019084 0x00000076 Code RO 675 i.tau_log_push_log CVWL668.lib(tau_log.o) + 0x000190fa 0x000190fa 0x00000002 PAD + 0x000190fc 0x000190fc 0x000000b4 Code RO 745 i.vidc_callback CVWL668.lib(hal_internal_vsync.o) + 0x000191b0 0x000191b0 0x00000118 Code RO 746 i.vpre_err_reset CVWL668.lib(hal_internal_vsync.o) + 0x000192c8 0x000192c8 0x000020b8 Data RO 121 .constdata p8p_demo.o + 0x0001b380 0x0001b380 0x00000028 Data RO 367 .constdata CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x0001b3a8 0x0001b3a8 0x0000001c Data RO 463 .constdata CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001b3c4 0x0001b3c4 0x00000030 Data RO 701 .constdata CVWL668.lib(hal_uart.o) + 0x0001b3f4 0x0001b3f4 0x00000010 Data RO 1798 .constdata CVWL668.lib(drv_uart.o) + 0x0001b404 0x0001b404 0x00000042 Data RO 368 .conststring CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x0001b446 0x0001b446 0x00000002 PAD + 0x0001b448 0x0001b448 0x00000090 Data RO 748 .conststring CVWL668.lib(hal_internal_vsync.o) + 0x0001b4d8 0x0001b4d8 0x0000008e Data RO 795 .conststring CVWL668.lib(hal_internal_dcs.o) + 0x0001b566 0x0001b566 0x00000002 PAD + 0x0001b568 0x0001b568 0x00000020 Data RO 2208 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Exec base: 0x00070000, Load base: 0x0001b588, Size: 0x00003168, Max: 0x00008000, ABSOLUTE, COMPRESSED[0x0000016c]) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x00070000 COMPRESSED 0x0000011f Data RW 122 .data p8p_demo.o + 0x0007011f COMPRESSED 0x00000001 PAD + 0x00070120 COMPRESSED 0x00000024 Data RW 369 .data CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00070144 COMPRESSED 0x0000005c Data RW 464 .data CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000701a0 COMPRESSED 0x00000002 Data RW 566 .data CVWL668.lib(hal_swire.o) + 0x000701a2 COMPRESSED 0x00000002 PAD + 0x000701a4 COMPRESSED 0x00000008 Data RW 639 .data CVWL668.lib(hal_pwr.o) + 0x000701ac COMPRESSED 0x00000001 Data RW 678 .data CVWL668.lib(tau_log.o) + 0x000701ad COMPRESSED 0x00000003 PAD + 0x000701b0 COMPRESSED 0x00000018 Data RW 702 .data CVWL668.lib(hal_uart.o) + 0x000701c8 COMPRESSED 0x00000010 Data RW 749 .data CVWL668.lib(hal_internal_vsync.o) + 0x000701d8 COMPRESSED 0x00000028 Data RW 796 .data CVWL668.lib(hal_internal_dcs.o) + 0x00070200 COMPRESSED 0x0000000c Data RW 880 .data CVWL668.lib(drv_common.o) + 0x0007020c COMPRESSED 0x00000001 Data RW 881 .data CVWL668.lib(drv_common.o) + 0x0007020d COMPRESSED 0x00000003 PAD + 0x00070210 COMPRESSED 0x00000004 Data RW 967 .data CVWL668.lib(drv_gpio.o) + 0x00070214 COMPRESSED 0x00000004 Data RW 1119 .data CVWL668.lib(drv_swire.o) + 0x00070218 COMPRESSED 0x00000050 Data RW 1167 .data CVWL668.lib(drv_timer.o) + 0x00070268 COMPRESSED 0x00000004 Data RW 1208 .data CVWL668.lib(drv_se.o) + 0x0007026c COMPRESSED 0x00000001 Data RW 1248 .data CVWL668.lib(drv_dsi_rx.o) + 0x0007026d COMPRESSED 0x00000003 PAD + 0x00070270 COMPRESSED 0x00000008 Data RW 1583 .data CVWL668.lib(drv_rxbr.o) + 0x00070278 COMPRESSED 0x00000004 Data RW 1670 .data CVWL668.lib(drv_vidc.o) + 0x0007027c COMPRESSED 0x00000190 Data RW 1745 .data CVWL668.lib(drv_dma.o) + 0x0007040c COMPRESSED 0x00000004 Data RW 2184 .data mc_p.l(stdout.o) + 0x00070410 - 0x000000d0 Zero RW 366 .bss CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x000704e0 - 0x000000b8 Zero RW 462 .bss CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00070598 - 0x00000100 Zero RW 677 .bss CVWL668.lib(tau_log.o) + 0x00070698 - 0x00000028 Zero RW 747 .bss CVWL668.lib(hal_internal_vsync.o) + 0x000706c0 - 0x00000800 Zero RW 793 .bss CVWL668.lib(hal_internal_dcs.o) + 0x00070ec0 - 0x000000ff Zero RW 794 .bss CVWL668.lib(hal_internal_dcs.o) + 0x00070fbf COMPRESSED 0x00000001 PAD + 0x00070fc0 - 0x00000044 Zero RW 822 .bss CVWL668.lib(hal_internal_fb.o) + 0x00071004 - 0x00000044 Zero RW 852 .bss CVWL668.lib(hal_internal_svs.o) + 0x00071048 - 0x00000040 Zero RW 966 .bss CVWL668.lib(drv_gpio.o) + 0x00071088 - 0x0000106c Zero RW 1191 .bss CVWL668.lib(dcs_packet_fifo.o) + 0x000720f4 - 0x00000010 Zero RW 1743 .bss CVWL668.lib(drv_dma.o) + 0x00072104 - 0x00000060 Zero RW 1797 .bss CVWL668.lib(drv_uart.o) + 0x00072164 COMPRESSED 0x00000004 PAD + 0x00072168 - 0x00001000 Zero RW 321 STACK startup_armcm0.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 24 4 0 0 0 577 board.o + 64 32 0 0 0 10471 main.o + 2914 826 8376 287 0 31016 p8p_demo.o + 120 18 192 0 4096 2164 startup_armcm0.o + + ---------------------------------------------------------------------- + 3128 880 8600 288 4096 44228 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 6 0 0 1 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 216 32 0 0 4204 252 dcs_packet_fifo.o + 104 62 28 13 0 192 drv_common.o + 536 90 0 0 0 792 drv_crgu.o + 136 22 0 400 16 196 drv_dma.o + 144 34 0 0 0 248 drv_dsc_dec.o + 1904 682 0 1 0 1340 drv_dsi_rx.o + 1704 306 0 0 0 2036 drv_dsi_tx.o + 148 0 0 0 0 260 drv_efuse.o + 296 40 0 4 64 1000 drv_gpio.o + 1080 166 0 0 0 1620 drv_lcdc.o + 658 104 0 0 0 1240 drv_memc.o + 40 0 0 0 0 120 drv_phy_common.o + 592 132 0 0 0 716 drv_pwr.o + 514 102 0 8 0 1120 drv_rxbr.o + 1012 264 0 4 0 492 drv_se.o + 264 54 0 4 0 560 drv_swire.o + 220 40 0 0 0 428 drv_sys_cfg.o + 366 38 0 80 0 816 drv_timer.o + 1172 54 16 0 96 980 drv_uart.o + 824 152 0 4 0 1700 drv_vidc.o + 2750 202 106 36 208 1256 hal_dsi_rx_ctrl.o + 4302 336 50 92 184 2212 hal_dsi_tx_ctrl.o + 444 34 0 0 0 688 hal_gpio.o + 2184 512 142 40 2303 656 hal_internal_dcs.o + 1292 60 0 0 68 688 hal_internal_fb.o + 1172 182 0 0 68 840 hal_internal_svs.o + 3400 716 144 16 40 1564 hal_internal_vsync.o + 308 32 0 8 0 616 hal_pwr.o + 344 32 0 2 0 348 hal_swire.o + 308 56 0 0 0 136 hal_system.o + 84 0 0 0 0 204 hal_timer.o + 176 18 48 24 0 144 hal_uart.o + 68 4 0 0 0 136 tau_delay.o + 354 30 16 1 256 320 tau_log.o + 200 20 0 0 0 76 ceil.o + 86 0 0 0 0 0 __dczerorl2.o + 0 0 0 0 0 0 entry.o + 0 0 0 0 0 0 entry10a.o + 0 0 0 0 0 0 entry11a.o + 8 4 0 0 0 0 entry2.o + 4 0 0 0 0 0 entry5.o + 0 0 0 0 0 0 entry7b.o + 0 0 0 0 0 0 entry8b.o + 8 4 0 0 0 0 entry9a.o + 30 0 0 0 0 0 handlers.o + 40 0 0 0 0 72 idiv.o + 36 8 0 0 0 68 init.o + 0 0 0 0 0 0 iusefp.o + 32 0 0 0 0 68 llshl.o + 38 0 0 0 0 68 llsshr.o + 34 0 0 0 0 68 llushr.o + 36 0 0 0 0 60 memcpya.o + 36 0 0 0 0 100 memseta.o + 2298 104 0 0 0 544 printfa.o + 0 0 0 4 0 0 stdout.o + 14 0 0 0 0 60 strlen.o + 44 0 0 0 0 72 uidiv.o + 96 0 0 0 0 84 uldiv.o + 40 2 0 0 0 68 cdrcmple.o + 20 0 0 0 0 68 cfcmple.o + 20 0 0 0 0 68 cfrcmple.o + 56 0 0 0 0 68 d2f.o + 356 4 0 0 0 140 dadd.o + 240 6 0 0 0 84 ddiv.o + 236 0 0 0 0 216 depilogue.o + 60 10 0 0 0 68 dfixui.o + 64 10 0 0 0 68 dfixul.o + 28 4 0 0 0 68 dfltui.o + 208 6 0 0 0 88 dmul.o + 40 0 0 0 0 60 f2d.o + 178 0 0 0 0 108 fadd.o + 124 0 0 0 0 72 fdiv.o + 130 0 0 0 0 144 fepilogue.o + 40 0 0 0 0 60 ffixui.o + 14 0 0 0 0 68 ffltui.o + 122 0 0 0 0 72 fmul.o + 24 0 0 0 0 60 fscalb.o + + ---------------------------------------------------------------------- + 34188 4770 556 752 7512 28904 Library Totals + 32 0 6 11 5 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 29116 4588 550 737 7507 25916 CVWL668.lib + 200 20 0 0 0 76 m_ps.l + 2840 120 0 4 0 1264 mc_p.l + 2000 42 0 0 0 1648 mf_p.l + + ---------------------------------------------------------------------- + 34188 4770 556 752 7512 28904 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 37316 5650 9156 1040 11608 53796 Grand Totals + 37316 5650 9156 364 11608 53796 ELF Image Totals (compressed) + 37316 5650 9156 364 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 46472 ( 45.38kB) + Total RW Size (RW Data + ZI Data) 12648 ( 12.35kB) + Total ROM Size (Code + RO Data + RW Data) 46836 ( 45.74kB) + +============================================================================== + diff --git a/project/WL668/Listings/WL668_P8P_TM667_ICNA3508_20240407.map b/project/WL668/Listings/WL668_P8P_TM667_ICNA3508_20240407.map new file mode 100644 index 0000000..6e36ac6 --- /dev/null +++ b/project/WL668/Listings/WL668_P8P_TM667_ICNA3508_20240407.map @@ -0,0 +1,4044 @@ +Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed] + +============================================================================== + +Section Cross References + + main.o(i.main) refers to board.o(i.board_Init) for board_Init + main.o(i.main) refers to p8p_demo.o(i.google_p8p_demo) for google_p8p_demo + main.o(i.main) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.Gpio_swire_output) refers to hal_gpio.o(i.hal_gpio_init_output) for hal_gpio_init_output + p8p_demo.o(i.Gpio_swire_output) refers to tau_delay.o(i.delayMs) for delayMs + p8p_demo.o(i.Gpio_swire_output) refers to hal_gpio.o(i.hal_gpio_set_output_data) for hal_gpio_set_output_data + p8p_demo.o(i.Gpio_swire_output) refers to tau_delay.o(i.delayUs) for delayUs + p8p_demo.o(i.Panel_CCM) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_ccm) for hal_dsi_tx_ctrl_set_ccm + p8p_demo.o(i.REG_51_OFF_output) refers to idiv.o(.text) for __aeabi_idivmod + p8p_demo.o(i.REG_51_OFF_output) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd + p8p_demo.o(i.REG_51_OFF_output) refers to tau_delay.o(i.delayMs) for delayMs + p8p_demo.o(i.ap_dcs_read) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) for hal_dsi_rx_ctrl_send_ack_cmd + p8p_demo.o(i.ap_dcs_read) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) for hal_dsi_rx_ctrl_get_max_ret_size + p8p_demo.o(i.ap_dcs_read) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_dcs_read) refers to p8p_demo.o(.data) for g_rx_ctrl_handle + p8p_demo.o(i.ap_dcs_set_backlight) refers to idiv.o(.text) for __aeabi_idivmod + p8p_demo.o(i.ap_dcs_set_backlight) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd + p8p_demo.o(i.ap_dcs_set_backlight) refers to p8p_demo.o(.data) for rd_51_val + p8p_demo.o(i.ap_dcs_set_display_off) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_dcs_set_display_off) refers to p8p_demo.o(.data) for panel_display_done + p8p_demo.o(i.ap_dcs_set_display_on) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) for hal_dsi_rx_ctrl_pre_init_pps + p8p_demo.o(i.ap_dcs_set_display_on) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) for hal_dsi_rx_ctrl_toggle_resolution + p8p_demo.o(i.ap_dcs_set_display_on) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_dcs_set_display_on) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd + p8p_demo.o(i.ap_dcs_set_display_on) refers to p8p_demo.o(.data) for g_resolution_change + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) for hal_dsi_tx_ctrl_set_tear_mode + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to tau_delay.o(i.delayMs) for delayMs + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to hal_swire.o(i.hal_swire_enable) for hal_swire_enable + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to hal_gpio.o(i.hal_gpio_set_output_data) for hal_gpio_set_output_data + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to hal_gpio.o(i.hal_gpio_set_ap_reset_int) for hal_gpio_set_ap_reset_int + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to p8p_demo.o(.data) for g_tx_ctrl_handle + p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) refers to p8p_demo.o(i.ap_rstn_pull_down_cb) for ap_rstn_pull_down_cb + p8p_demo.o(i.ap_dcs_set_exit_idle_mode) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_hw_cmd_filter) for hal_dsi_rx_ctrl_set_hw_cmd_filter + p8p_demo.o(i.ap_dcs_set_exit_idle_mode) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_dcs_set_exit_idle_mode) refers to p8p_demo.o(.data) for sg_exit_idle_mode_flag + p8p_demo.o(i.ap_dcs_set_exit_sleep_mode) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_dcs_set_frame_change) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) for hal_dsi_tx_ctrl_set_tear_mode + p8p_demo.o(i.ap_dcs_set_frame_change) refers to p8p_demo.o(.data) for g_tx_ctrl_handle + p8p_demo.o(i.ap_rstn_pull_down_cb) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.ap_rstn_pull_down_cb) refers to hal_gpio.o(i.hal_gpio_set_ap_reset_int) for hal_gpio_set_ap_reset_int + p8p_demo.o(i.ap_rstn_pull_down_cb) refers to p8p_demo.o(.data) for sg_system_suspend + p8p_demo.o(i.ap_rstn_pull_high_cb) refers to hal_gpio.o(i.hal_gpio_set_ap_reset_int) for hal_gpio_set_ap_reset_int + p8p_demo.o(i.ap_rstn_pull_high_cb) refers to p8p_demo.o(.data) for sg_system_resume + p8p_demo.o(i.ap_set_FPS_53) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd + p8p_demo.o(i.app_display_init) refers to p8p_demo.o(i.app_mipi_rx_init) for app_mipi_rx_init + p8p_demo.o(i.app_display_init) refers to hal_pwr.o(i.hal_pwr_get_vcc_power_ready) for hal_pwr_get_vcc_power_ready + p8p_demo.o(i.app_display_init) refers to p8p_demo.o(i.app_gpio_init) for app_gpio_init + p8p_demo.o(i.app_display_init) refers to hal_swire.o(i.hal_swire_init) for hal_swire_init + p8p_demo.o(i.app_display_init) refers to hal_swire.o(i.hal_swire_set_timer) for hal_swire_set_timer + p8p_demo.o(i.app_display_init) refers to p8p_demo.o(i.app_mipi_tx_init) for app_mipi_tx_init + p8p_demo.o(i.app_display_init) refers to p8p_demo.o(i.app_mipi_tx_start) for app_mipi_tx_start + p8p_demo.o(i.app_gpio_init) refers to hal_gpio.o(i.hal_gpio_config_pad) for hal_gpio_config_pad + p8p_demo.o(i.app_gpio_init) refers to p8p_demo.o(.constdata) for .constdata + p8p_demo.o(i.app_init_panel) refers to p8p_demo.o(i.app_tx_panel_reset) for app_tx_panel_reset + p8p_demo.o(i.app_init_panel) refers to p8p_demo.o(i.send_panel_init_code) for send_panel_init_code + p8p_demo.o(i.app_init_panel) refers to hal_gpio.o(i.hal_gpio_init_output) for hal_gpio_init_output + p8p_demo.o(i.app_init_panel) refers to tau_delay.o(i.delayMs) for delayMs + p8p_demo.o(i.app_init_panel) refers to hal_swire.o(i.hal_swire_enable) for hal_swire_enable + p8p_demo.o(i.app_init_panel) refers to hal_swire.o(i.hal_swire_set_pulse) for hal_swire_set_pulse + p8p_demo.o(i.app_init_panel) refers to p8p_demo.o(.constdata) for panel_init_code + p8p_demo.o(i.app_mipi_rx_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) for hal_dsi_rx_ctrl_create_handle + p8p_demo.o(i.app_mipi_rx_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) for hal_dsi_rx_ctrl_pre_init_pps + p8p_demo.o(i.app_mipi_rx_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) for hal_dsi_rx_ctrl_init + p8p_demo.o(i.app_mipi_rx_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) for hal_dsi_rx_ctrl_start + p8p_demo.o(i.app_mipi_rx_init) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.app_mipi_rx_init) refers to p8p_demo.o(.data) for g_rx_ctrl_handle + p8p_demo.o(i.app_mipi_rx_init) refers to p8p_demo.o(.constdata) for g_cus_rx_dcs_execute_table + p8p_demo.o(i.app_mipi_rx_init) refers to p8p_demo.o(i.ap_dcs_read) for ap_dcs_read + p8p_demo.o(i.app_mipi_rx_init) refers to p8p_demo.o(i.pps_update_handle) for pps_update_handle + p8p_demo.o(i.app_mipi_tx_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) for hal_dsi_tx_ctrl_create_handle + p8p_demo.o(i.app_mipi_tx_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) for hal_dsi_tx_ctrl_init + p8p_demo.o(i.app_mipi_tx_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb) for hal_dsi_tx_ctrl_set_overwrite_rgb + p8p_demo.o(i.app_mipi_tx_init) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.app_mipi_tx_init) refers to p8p_demo.o(.data) for g_tx_ctrl_handle + p8p_demo.o(i.app_mipi_tx_start) refers to p8p_demo.o(i.app_init_panel) for app_init_panel + p8p_demo.o(i.app_mipi_tx_start) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) for hal_dsi_tx_ctrl_start + p8p_demo.o(i.app_mipi_tx_start) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) for hal_dsi_tx_ctrl_set_tear_mode + p8p_demo.o(i.app_mipi_tx_start) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) for hal_dsi_rx_ctrl_pre_init_pps + p8p_demo.o(i.app_mipi_tx_start) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) for hal_dsi_rx_ctrl_toggle_resolution + p8p_demo.o(i.app_mipi_tx_start) refers to tau_delay.o(i.delayMs) for delayMs + p8p_demo.o(i.app_mipi_tx_start) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd + p8p_demo.o(i.app_mipi_tx_start) refers to hal_swire.o(i.hal_swire_set_pulse) for hal_swire_set_pulse + p8p_demo.o(i.app_mipi_tx_start) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.app_mipi_tx_start) refers to p8p_demo.o(.data) for g_tx_ctrl_handle + p8p_demo.o(i.app_system_process) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.app_system_process) refers to p8p_demo.o(i.app_system_suspend) for app_system_suspend + p8p_demo.o(i.app_system_process) refers to p8p_demo.o(i.app_system_resume) for app_system_resume + p8p_demo.o(i.app_system_process) refers to p8p_demo.o(.data) for sg_system_suspend + p8p_demo.o(i.app_system_resume) refers to hal_pwr.o(i.hal_pwr_exit_sleep_mode) for hal_pwr_exit_sleep_mode + p8p_demo.o(i.app_system_resume) refers to p8p_demo.o(i.app_display_init) for app_display_init + p8p_demo.o(i.app_system_resume) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.app_system_suspend) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) for hal_dsi_tx_ctrl_stop + p8p_demo.o(i.app_system_suspend) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) for hal_dsi_tx_ctrl_deinit + p8p_demo.o(i.app_system_suspend) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) for hal_dsi_rx_ctrl_stop + p8p_demo.o(i.app_system_suspend) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) for hal_dsi_rx_ctrl_deinit + p8p_demo.o(i.app_system_suspend) refers to hal_gpio.o(i.hal_gpio_init_output) for hal_gpio_init_output + p8p_demo.o(i.app_system_suspend) refers to hal_swire.o(i.hal_swire_deinit) for hal_swire_deinit + p8p_demo.o(i.app_system_suspend) refers to hal_pwr.o(i.hal_pwr_set_sleep_mode_power) for hal_pwr_set_sleep_mode_power + p8p_demo.o(i.app_system_suspend) refers to hal_gpio.o(i.hal_gpio_set_ap_reset_int) for hal_gpio_set_ap_reset_int + p8p_demo.o(i.app_system_suspend) refers to hal_pwr.o(i.hal_pwr_enter_normal_sleep_mode) for hal_pwr_enter_normal_sleep_mode + p8p_demo.o(i.app_system_suspend) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.app_system_suspend) refers to hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) for hal_pwr_set_stop_sleep_wakeup_pin + p8p_demo.o(i.app_system_suspend) refers to hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode) for hal_pwr_enter_stop_sleep_mode + p8p_demo.o(i.app_system_suspend) refers to hal_pwr.o(i.hal_pwr_enter_deep_sleep_mode) for hal_pwr_enter_deep_sleep_mode + p8p_demo.o(i.app_system_suspend) refers to p8p_demo.o(.data) for g_tx_ctrl_handle + p8p_demo.o(i.app_system_suspend) refers to p8p_demo.o(i.ap_rstn_pull_high_cb) for ap_rstn_pull_high_cb + p8p_demo.o(i.app_tx_panel_reset) refers to hal_gpio.o(i.hal_gpio_set_output_data) for hal_gpio_set_output_data + p8p_demo.o(i.app_tx_panel_reset) refers to tau_delay.o(i.delayMs) for delayMs + p8p_demo.o(i.google_p8p_demo) refers to hal_pwr.o(i.hal_pwr_set_main_power) for hal_pwr_set_main_power + p8p_demo.o(i.google_p8p_demo) refers to p8p_demo.o(i.app_display_init) for app_display_init + p8p_demo.o(i.google_p8p_demo) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + p8p_demo.o(i.google_p8p_demo) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) for hal_dsi_rx_ctrl_dcs_async_handler + p8p_demo.o(i.google_p8p_demo) refers to p8p_demo.o(i.app_system_process) for app_system_process + p8p_demo.o(i.google_p8p_demo) refers to p8p_demo.o(.data) for g_rx_ctrl_handle + p8p_demo.o(i.pps_update_handle) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) for hal_dsi_tx_ctrl_set_tear_mode + p8p_demo.o(i.pps_update_handle) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) for hal_dsi_rx_ctrl_toggle_resolution + p8p_demo.o(i.pps_update_handle) refers to p8p_demo.o(.data) for g_rx_ctrl_handle + p8p_demo.o(i.send_panel_init_code) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) for hal_dsi_tx_ctrl_write_array_cmd + p8p_demo.o(i.send_panel_init_code) refers to tau_delay.o(i.delayUs) for delayUs + p8p_demo.o(i.soft_te_timer_cb) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) for hal_dsi_tx_ctrl_gen_a_tear_signal + p8p_demo.o(i.soft_te_timer_cb) refers to hal_timer.o(i.hal_timer_start) for hal_timer_start + p8p_demo.o(i.soft_te_timer_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) for hal_dsi_tx_ctrl_set_tear_mode + p8p_demo.o(i.soft_te_timer_init) refers to hal_timer.o(i.hal_timer_init) for hal_timer_init + p8p_demo.o(i.soft_te_timer_init) refers to hal_timer.o(i.hal_timer_start) for hal_timer_start + p8p_demo.o(i.soft_te_timer_init) refers to p8p_demo.o(.data) for g_tx_ctrl_handle + p8p_demo.o(i.soft_te_timer_init) refers to p8p_demo.o(i.soft_te_timer_cb) for soft_te_timer_cb + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_dcs_set_display_on) for ap_dcs_set_display_on + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_dcs_set_display_off) for ap_dcs_set_display_off + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_dcs_set_backlight) for ap_dcs_set_backlight + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_set_FPS_53) for ap_set_FPS_53 + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) for ap_dcs_set_enter_sleep_mode + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_dcs_set_exit_sleep_mode) for ap_dcs_set_exit_sleep_mode + p8p_demo.o(.constdata) refers to p8p_demo.o(i.ap_dcs_set_frame_change) for ap_dcs_set_frame_change + board.o(i.board_Init) refers to hal_system.o(i.hal_system_init) for hal_system_init + board.o(i.board_Init) refers to tau_log.o(i.tau_log_init) for tau_log_init + startup_armcm0.o(RESET) refers to startup_armcm0.o(STACK) for __initial_sp + startup_armcm0.o(RESET) refers to startup_armcm0.o(.text) for Reset_Handler + startup_armcm0.o(RESET) refers to drv_common.o(i.HardFault_Handler) for HardFault_Handler + startup_armcm0.o(RESET) refers to drv_common.o(i.SysTick_Handler) for SysTick_Handler + startup_armcm0.o(RESET) refers to drv_vidc.o(i.VIDC_IRQn_Handler) for VIDC_IRQn_Handler + startup_armcm0.o(RESET) refers to hal_internal_vsync.o(i.LCDC_IRQn_Handler) for LCDC_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler) for MIPI_RX_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler) for MIPI_TX_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_memc.o(i.MEMC_IRQn_Handler) for MEMC_IRQn_Handler + startup_armcm0.o(RESET) refers to hal_internal_dcs.o(i.VPRE_IRQn_Handler) for VPRE_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_dma.o(i.DMA_IRQn_Handler) for DMA_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_timer.o(i.TIMER0_IRQn_Handler) for TIMER0_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_timer.o(i.TIMER1_IRQn_Handler) for TIMER1_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_timer.o(i.TIMER2_IRQn_Handler) for TIMER2_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_timer.o(i.TIMER3_IRQn_Handler) for TIMER3_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_uart.o(i.UART_IRQn_Handler) for UART_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_rxbr.o(i.VPRE1_IRQn_Handler) for VPRE1_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_swire.o(i.SWIRE_IRQn_Handler) for SWIRE_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.AP_NRESET_IRQn_Handler) for AP_NRESET_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT0_IRQn_Handler) for EXTI_INT0_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT1_IRQn_Handler) for EXTI_INT1_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT2_IRQn_Handler) for EXTI_INT2_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT3_IRQn_Handler) for EXTI_INT3_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT4_IRQn_Handler) for EXTI_INT4_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT5_IRQn_Handler) for EXTI_INT5_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT6_IRQn_Handler) for EXTI_INT6_IRQn_Handler + startup_armcm0.o(RESET) refers to drv_gpio.o(i.EXTI_INT7_IRQn_Handler) for EXTI_INT7_IRQn_Handler + startup_armcm0.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_ack_long_cmd) refers to drv_rxbr.o(i.drv_rxbr_set_ack_pkt_md) for drv_rxbr_set_ack_pkt_md + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_ack_long_cmd) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_lpdt_fifo_status) for drv_dsi_rx_get_lpdt_fifo_status + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) refers to memseta.o(.text) for __aeabi_memclr4 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) refers to dcs_packet_fifo.o(i.dcs_packet_get_fifo_header) for dcs_packet_get_fifo_header + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) refers to dcs_packet_fifo.o(i.dcs_packet_free_fifo_header) for dcs_packet_free_fifo_header + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_rx_state) for hal_internal_vsync_get_rx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_dsc_dec.o(i.drv_dsc_dec_disable) for drv_dsc_dec_disable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) for drv_dsi_rx_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_rxbr.o(i.drv_rxbr_enable_irq) for drv_rxbr_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_vidc.o(i.drv_vidc_enable_irq) for drv_vidc_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_memc.o(i.drv_memc_enable_irq) for drv_memc_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to drv_crgu.o(i.drv_crgu_reset_modules) for drv_crgu_reset_modules + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) for hal_internal_vsync_set_rx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_line) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_line) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_line) refers to hal_dsi_rx_ctrl.o(i.swap_uint16_t) for swap_uint16_t + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_line) refers to fflti.o(.text) for __aeabi_i2f + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_line) refers to fdiv.o(.text) for __aeabi_fdiv + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_line) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data_ex) for hal_dsi_rx_ctrl_set_pixel_data_ex + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_rxbr.o(i.drv_rxbr_swpxl_clr) for drv_rxbr_swpxl_clr + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_rxbr.o(i.drv_rxbr_set_cmd_filter) for drv_rxbr_set_cmd_filter + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_dsc_dec.o(i.drv_dsc_dec_disable) for drv_dsc_dec_disable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_vidc.o(i.drv_vidc_set_src_parameter) for drv_vidc_set_src_parameter + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_vidc.o(i.drv_vidc_set_scld_step) for drv_vidc_set_scld_step + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_vidc.o(i.drv_vidc_set_pu_ctrl) for drv_vidc_set_pu_ctrl + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to drv_rxbr.o(i.drv_rxbr_set_swpxl_data) for drv_rxbr_set_swpxl_data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_pg_cfg) for drv_dsi_rx_set_ddi_pg_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to drv_crgu.o(i.drv_crgu_get_rxbr_clk) for drv_crgu_get_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to idiv.o(.text) for __aeabi_idivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) for hal_dsi_rx_ctrl_set_rx_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_pg_cfg) for drv_dsi_rx_set_ipi_pg_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to hal_dsi_rx_ctrl.o(.constdata) for .constdata + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern) refers to hal_dsi_rx_ctrl.o(.conststring) for .conststring + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_force_video_crtl) refers to drv_dsi_rx.o(i.drv_dsi_rx_force_video_crtl) for drv_dsi_rx_force_video_crtl + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_cap_pixel_color) refers to drv_vidc.o(i.drv_vidc_get_status2) for drv_vidc_get_status2 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_compressen_en) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en) for drv_dsi_rx_get_compression_en + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_max_ret_size) for drv_dsi_rx_get_max_ret_size + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) for hal_dsi_rx_ctrl_init_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_internal_vsync.o(i.hal_internal_vsync_init_rx) for hal_internal_vsync_init_rx + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) for hal_dsi_rx_ctrl_init_dsi_rx + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) for hal_dsi_rx_ctrl_init_rxbr + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to drv_dsc_dec.o(i.drv_dsc_dec_enable) for drv_dsc_dec_enable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to drv_dsc_dec.o(i.drv_dsc_dec_set_irqen) for drv_dsc_dec_set_irqen + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) for hal_dsi_rx_ctrl_init_vidc + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) for hal_dsi_rx_ctrl_init_memc + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) for hal_internal_vsync_set_rx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to drv_se.o(i.drv_se_start_rx) for drv_se_start_rx + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) refers to drv_pwr.o(i.drv_pwr_set_pll_clk) for drv_pwr_set_pll_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) refers to drv_crgu.o(i.drv_crgu_set_rxbr_clk) for drv_crgu_set_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) refers to drv_crgu.o(i.drv_crgu_set_dsc_clk) for drv_crgu_set_dsc_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) refers to drv_crgu.o(i.drv_crgu_set_vidc_clk) for drv_crgu_set_vidc_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) refers to drv_crgu.o(i.drv_crgu_set_fb_clk) for drv_crgu_set_fb_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_crgu.o(i.drv_crgu_get_rxbr_clk) for drv_crgu_get_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ctrl_cfg) for drv_dsi_rx_set_ctrl_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) for drv_dsi_rx_set_ddi_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) for hal_dsi_rx_ctrl_set_ipi_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) for drv_dsi_rx_set_up_phy + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_lane_swap) for drv_dsi_rx_set_lane_swap + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_crc_en) for drv_dsi_rx_set_ddi_crc_en + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_ycbcr_frmt) for drv_dsi_rx_set_ipi_ycbcr_frmt + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_tear_resp_en) for drv_dsi_rx_set_tear_resp_en + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_inten) for drv_dsi_rx_set_inten + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_check_crc) for drv_dsi_rx_set_check_crc + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_resp_cnt) for drv_dsi_rx_set_resp_cnt + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) for drv_dsi_rx_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) for hal_intl_fb_get_memc_flow_mode + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_data_mode) for drv_memc_set_data_mode + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_ltpo_mode) for drv_memc_set_ltpo_mode + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_rate_transfer_sel) for drv_memc_rate_transfer_sel + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_fs_en_conditions) for drv_memc_set_fs_en_conditions + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_lcdc_st_conditions) for drv_memc_set_lcdc_st_conditions + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_sel_vsync) for drv_memc_sel_vsync + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_vidc_sync_cnt) for drv_memc_set_vidc_sync_cnt + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_tear_waveform) for drv_memc_set_tear_waveform + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_tear_mode) for drv_memc_set_tear_mode + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_double_buffer) for drv_memc_set_double_buffer + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_circ_mode_enable) for drv_memc_set_circ_mode_enable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_active_height) for drv_memc_set_active_height + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_set_ltpo_pu_thres) for drv_memc_set_ltpo_pu_thres + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to drv_memc.o(i.drv_memc_enable_irq) for drv_memc_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_set_color_format) for drv_rxbr_set_color_format + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) for hal_intl_fb_get_memc_flow_mode + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_set_ltpo_drop_th) for drv_rxbr_set_ltpo_drop_th + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) for drv_rxbr_frame_drop_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_set_usr_cfg) for drv_rxbr_set_usr_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_set_usr_col) for drv_rxbr_set_usr_col + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_set_usr_row) for drv_rxbr_set_usr_row + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_hline_rcv_cfg) for drv_rxbr_hline_rcv_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to drv_rxbr.o(i.drv_rxbr_enable_irq) for drv_rxbr_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) for hal_intl_dcs_set_auto_hw_filter + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_src_parameter) for drv_vidc_set_src_parameter + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_pentile_swap) for drv_vidc_set_pentile_swap + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_dst_parameter) for drv_vidc_set_dst_parameter + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_circ_mode_enable) for drv_vidc_set_circ_mode_enable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_init_module_enable) for drv_vidc_init_module_enable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_dither_config) for drv_vidc_set_dither_config + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_vintp_config) for drv_vidc_set_vintp_config + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_rotation) for drv_vidc_set_rotation + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to dfltui.o(.text) for __aeabi_ui2d + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to dadd.o(.text) for __aeabi_dadd + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_scld_step) for drv_vidc_set_scld_step + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_scld_hcoef0) for drv_vidc_set_scld_hcoef0 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_scld_hcoef1) for drv_vidc_set_scld_hcoef1 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_scld_vcoef0) for drv_vidc_set_scld_vcoef0 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_scld_vcoef1) for drv_vidc_set_scld_vcoef1 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_honly_hinitr) for drv_vidc_set_honly_hinitr + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_honly_hinitb) for drv_vidc_set_honly_hinitb + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_honly_hcoef0) for drv_vidc_set_honly_hcoef0 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_mirror) for drv_vidc_set_mirror + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_pu_ctrl) for drv_vidc_set_pu_ctrl + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_set_irqen) for drv_vidc_set_irqen + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to drv_vidc.o(i.drv_vidc_enable_irq) for drv_vidc_enable_irq + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) refers to hal_dsi_rx_ctrl.o(.constdata) for .constdata + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_callback) refers to hal_internal_vsync.o(i.hal_internal_sync_register_rx_callback) for hal_internal_sync_register_rx_callback + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_callback) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_callback) refers to drv_vidc.o(i.drv_vidc_set_irq_line) for drv_vidc_set_irq_line + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_callback) refers to drv_vidc.o(i.drv_vidc_set_irqen) for drv_vidc_set_irqen + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_write_cmd_entry) refers to hal_internal_dcs.o(i.hal_intl_dcs_register_write_cmd_entry) for hal_intl_dcs_register_write_cmd_entry + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_release_handle) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) refers to drv_dsi_rx.o(i.drv_dsi_rx_shut_down) for drv_dsi_rx_shut_down + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) for hal_dsi_rx_ctrl_init + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) for hal_dsi_rx_ctrl_start + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) refers to drv_rxbr.o(i.drv_rxbr_set_ack_pkt_header) for drv_rxbr_set_ack_pkt_header + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) refers to hal_dsi_rx_ctrl.o(.conststring) for .conststring + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_ack) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_ack) refers to drv_rxbr.o(i.drv_rxbr_set_cmd_response) for drv_rxbr_set_cmd_response + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_ack) refers to hal_dsi_rx_ctrl.o(.conststring) for .conststring + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_hw_filter) refers to hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) for hal_intl_dcs_set_auto_hw_filter + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_hw_filter) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cap_pixel_pos) refers to drv_vidc.o(i.drv_vidc_debug_cap_pixel) for drv_vidc_debug_cap_pixel + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_check_crc) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_check_crc) for drv_dsi_rx_set_check_crc + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_check_crc) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk) refers to drv_crgu.o(i.drv_crgu_get_rxbr_clk) for drv_crgu_get_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) for drv_dsi_rx_set_ddi_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_hw_cmd_filter) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) refers to drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) for drv_dsi_rx_calc_ipi_tx_delay + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_cfg) for drv_dsi_rx_set_ipi_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_log_level) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_drv_log_level) for drv_dsi_rx_set_drv_log_level + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data) refers to drv_rxbr.o(i.drv_rxbr_sw_reset) for drv_rxbr_sw_reset + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data_ex) refers to drv_rxbr.o(i.drv_rxbr_sw_reset) for drv_rxbr_sw_reset + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data_ex) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rxbr_clk) for hal_dsi_rx_ctrl_set_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) for hal_intl_svs_update_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to drv_crgu.o(i.drv_crgu_get_rxbr_clk) for drv_crgu_get_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) for drv_dsi_rx_set_ddi_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) for hal_dsi_rx_ctrl_set_ipi_cfg + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk) refers to hal_dsi_rx_ctrl.o(.data) for .data + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rxbr_clk) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rxbr_clk) refers to drv_crgu.o(i.drv_crgu_set_rxbr_clk) for drv_crgu_set_rxbr_clk + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) refers to drv_vidc.o(i.drv_vidc_enable) for drv_vidc_enable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) refers to drv_dsi_rx.o(i.drv_dsi_rx_power_up) for drv_dsi_rx_power_up + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) for hal_internal_vsync_set_rx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) refers to drv_vidc.o(i.drv_vidc_enable) for drv_vidc_enable + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) refers to drv_dsi_rx.o(i.drv_dsi_rx_shut_down) for drv_dsi_rx_shut_down + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) for hal_internal_vsync_set_rx_state + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_input_frame_rate) refers to hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) for hal_internal_vsync_toggle_input_frame_rate + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) refers to hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) for hal_internal_sync_input_resolution_change + hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) refers to hal_dsi_rx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to fdiv.o(.text) for __aeabi_fdiv + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to fadd.o(.text) for __aeabi_fadd + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to ffltui.o(.text) for __aeabi_ui2f + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to fmul.o(.text) for __aeabi_fmul + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to f2d.o(.text) for __aeabi_f2d + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to ceil.o(i.ceil) for ceil + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to idiv.o(.text) for __aeabi_idivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) for hal_internal_sync_get_hight_performan_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_shutdown) for drv_dsi_tx_shutdown + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) for hal_dsi_tx_ctrl_init_clk + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg) for drv_dsi_tx_phy_time_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) for drv_dsi_tx_phy_test_setup + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_mode) for drv_dsi_tx_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_config_eotp) for drv_dsi_tx_config_eotp + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) for drv_dsi_tx_set_esc_div + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready) for drv_dsi_tx_phy_status_ready + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_dsi_tx.o(i.drv_dsi_tx_powerup) for drv_dsi_tx_powerup + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to drv_crgu.o(i.drv_crgu_reset_modules) for drv_crgu_reset_modules + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) refers to memseta.o(.text) for __aeabi_memclr4 + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to drv_crgu.o(i.drv_crgu_reset_modules) for drv_crgu_reset_modules + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) for hal_internal_vsync_set_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to hal_internal_vsync.o(i.hal_internal_sync_register_lcdc_cb) for hal_internal_sync_register_lcdc_cb + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to memseta.o(.text) for __aeabi_memclr4 + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to drv_vidc.o(i.drv_vidc_enable) for drv_vidc_enable + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to hal_internal_vsync.o(i.hal_internal_sync_set_fb_setting_manual) for hal_internal_sync_set_fb_setting_manual + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) for hal_lcdc_init_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to drv_memc.o(i.drv_memc_set_data_mode) for drv_memc_set_data_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_frame) refers to drv_lcdc.o(i.drv_lcdc_fixed_frame_output) for drv_lcdc_fixed_frame_output + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) refers to drv_memc.o(i.drv_memc_get_tear_mode) for drv_memc_get_tear_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) refers to drv_memc.o(i.drv_memc_set_tear_mode) for drv_memc_set_tear_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) refers to drv_memc.o(i.drv_memc_gen_a_tear_signal) for drv_memc_gen_a_tear_signal + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_internal_vsync.o(i.hal_internal_vsync_init_tx) for hal_internal_vsync_init_tx + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_internal_vsync.o(i.hal_internal_sync_register_lcdc_cb) for hal_internal_sync_register_lcdc_cb + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) for hal_dsi_tx_ctrl_init_clk + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) for hal_dsi_tx_init_timing + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) for hal_dsi_tx_init_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) for hal_lcdc_init_clk + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) for hal_lcdc_init_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready) for drv_dsi_tx_phy_status_ready + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to drv_dsi_tx.o(i.drv_dsi_tx_powerup) for drv_dsi_tx_powerup + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) for hal_internal_vsync_set_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) for hal_nonshadow_func_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) refers to hal_dsi_tx_ctrl.o(i.hal_vsync_func_update) for hal_vsync_func_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_overwrite_enable) refers to drv_lcdc.o(i.drv_lcdc_function_enable) for drv_lcdc_function_enable + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_overwrite_enable) refers to drv_lcdc.o(i.drv_lcdc_function_disable) for drv_lcdc_function_disable + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_partial_disp_enable) refers to drv_lcdc.o(i.drv_lcdc_part_display_config) for drv_lcdc_part_display_config + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_partial_disp_enable) refers to drv_lcdc.o(i.drv_lcdc_function_disable) for drv_lcdc_function_disable + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd) refers to memseta.o(.text) for __aeabi_memclr4 + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) for hal_dsi_tx_send_cmd + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) for drv_dsi_tx_get_cmd_status + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_get_payload) for drv_dsi_tx_command_get_payload + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd) refers to memcpya.o(.text) for __aeabi_memcpy + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_release_handle) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_bcs) refers to memcpya.o(.text) for __aeabi_memcpy + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_bcs) refers to hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_req_update) for hal_nonshadow_func_req_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_bcs) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_bcs) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_bcs) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for .ARM.__at_0x1102C + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_cus_sync_line) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) for hal_internal_vsync_set_sync_line + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_cus_sync_line) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_dect) refers to hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_req_update) for hal_nonshadow_func_req_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_dect) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_dect) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_dect) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for .ARM.__at_0x1102C + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_enhance) refers to memcpya.o(.text) for __aeabi_memcpy + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_enhance) refers to hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_req_update) for hal_nonshadow_func_req_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_enhance) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_enhance) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_enhance) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for .ARM.__at_0x1102C + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_endianness) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_escape_clock_div) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_escape_clock_div) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) for drv_dsi_tx_set_esc_div + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_escape_clock_div) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_fc) refers to hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_req_update) for hal_nonshadow_func_req_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_fc) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_fc) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_fc) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for .ARM.__at_0x1102C + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb) refers to drv_lcdc.o(i.drv_lcdc_config_overwrite_rgb) for drv_lcdc_config_overwrite_rgb + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) for hal_internal_vsync_set_tear_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_vpg) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_vpg) for drv_dsi_tx_set_vpg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_vpg) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick) for hal_dsi_tx_ctrl_draw_flick + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_dsi_tx.o(i.drv_dsi_tx_shutdown) for drv_dsi_tx_shutdown + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_dsi_tx.o(i.drv_dsi_tx_mode) for drv_dsi_tx_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp) for drv_dsi_tx_phy_clock_lane_auto_lp + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_dsi_tx.o(i.drv_dsi_tx_config_eotp) for drv_dsi_tx_config_eotp + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg) for drv_dsi_tx_command_mode_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_lcdc.o(i.drv_lcdc_cfg_int_frame) for drv_lcdc_cfg_int_frame + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) for hal_intl_fb_get_memc_flow_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_lcdc.o(i.drv_lcdc_function_enable) for drv_lcdc_function_enable + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_dsi_tx.o(i.drv_dsi_tx_powerup) for drv_dsi_tx_powerup + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to drv_lcdc.o(i.drv_lcdc_enable_shadow_reg) for drv_lcdc_enable_shadow_reg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_start) for hal_lcdc_start + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) for hal_internal_vsync_set_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) refers to drv_lcdc.o(i.drv_lcdc_stop_display) for drv_lcdc_stop_display + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) refers to drv_lcdc.o(i.drv_lcdc_set_int) for drv_lcdc_set_int + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_int) for drv_dsi_tx_set_int + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) refers to drv_dsi_tx.o(i.drv_dsi_tx_shutdown) for drv_dsi_tx_shutdown + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) for hal_internal_vsync_set_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_vporch_bta_opera) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_vporch_bta_opera) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd) for hal_dsi_tx_ctrl_read_cmd + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_vporch_bta_opera) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) for hal_dsi_tx_send_cmd + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) for drv_dsi_tx_get_cmd_status + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) for drv_dsi_tx_command_put_payload + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) for hal_dsi_tx_send_cmd + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) for drv_dsi_tx_get_cmd_status + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) for drv_dsi_tx_command_put_payload + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_video_mode_cfg) for drv_dsi_tx_video_mode_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_bta_ack) for drv_dsi_tx_set_bta_ack + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_dpi_lpcmd_time) for drv_dsi_tx_dpi_lpcmd_time + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg) for drv_dsi_tx_command_mode_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_mode) for drv_dsi_tx_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_lane_mode) for drv_dsi_tx_phy_lane_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_dpi_mode) for drv_dsi_tx_dpi_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_dpi_polarity) for drv_dsi_tx_dpi_polarity + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_response_mode) for drv_dsi_tx_response_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_config_eotp) for drv_dsi_tx_config_eotp + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) for drv_dsi_tx_set_esc_div + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_time_out_div) for drv_dsi_tx_set_time_out_div + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to memseta.o(.text) for __aeabi_memclr4 + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_timeout_cfg) for drv_dsi_tx_timeout_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs) for drv_dsi_tx_phy_clock_lane_req_hs + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp) for drv_dsi_tx_phy_clock_lane_auto_lp + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_config_int) for drv_dsi_tx_config_int + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_int) for drv_dsi_tx_set_int + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) refers to hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) for hal_internal_sync_get_hight_performan_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) refers to drv_crgu.o(i.drv_crgu_set_dpi_clk) for drv_crgu_set_dpi_clk + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) refers to hal_dsi_tx_ctrl.o(.constdata) for .constdata + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg) for drv_dsi_tx_phy_time_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) for drv_dsi_tx_phy_test_setup + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_timing_info_update) for hal_dsi_tx_timing_info_update + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) for hal_dsi_tx_cmd_mode_cal_timing + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to drv_dsi_tx.o(i.drv_dsi_tx_edpi_cmd_size) for drv_dsi_tx_edpi_cmd_size + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) for hal_dsi_tx_init_phy_cfg + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) for hal_dsi_tx_init_dpi_timing + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) for hal_dsi_tx_vid_mode_cal_timing + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_vid_timing) for hal_dsi_tx_init_vid_timing + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_vid_timing) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_video_chunk) for drv_dsi_tx_set_video_chunk + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_vid_timing) refers to drv_dsi_tx.o(i.drv_dsi_tx_set_video_timing) for drv_dsi_tx_set_video_timing + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) for drv_dsi_tx_get_cmd_status + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_header) for drv_dsi_tx_command_header + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) for drv_dsi_tx_phy_status_stopstate + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_timing_info_update) refers to d2f.o(.text) for __aeabi_d2f + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_timing_info_update) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to ffltui.o(.text) for __aeabi_ui2f + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to fmul.o(.text) for __aeabi_fmul + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to fdiv.o(.text) for __aeabi_fdiv + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to f2d.o(.text) for __aeabi_f2d + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to ceil.o(i.ceil) for ceil + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to idiv.o(.text) for __aeabi_idivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) for hal_internal_sync_get_hight_performan_mode + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to hal_internal_svs.o(i.hal_intl_svs_init_tx) for hal_intl_svs_init_tx + hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) refers to hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) for hal_tx_frame_rate_adjust + hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config) refers to drv_lcdc.o(i.drv_lcdc_endianness_config) for drv_lcdc_endianness_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config) refers to drv_lcdc.o(i.drv_lcdc_crop_hact) for drv_lcdc_crop_hact + hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) for hal_lcdc_postproc_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config) for hal_lcdc_displayproc_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) refers to hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info) for hal_intl_fb_get_tx_fb_info + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) for hal_lcdc_timinggen_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) refers to drv_lcdc.o(i.drv_lcdc_config_int) for drv_lcdc_config_int + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) refers to drv_lcdc.o(i.drv_lcdc_set_int) for drv_lcdc_set_int + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to fscalb.o(.text) for __ARM_scalbnf + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to ffltui.o(.text) for __aeabi_ui2f + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to fdiv.o(.text) for __aeabi_fdiv + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to f2d.o(.text) for __aeabi_f2d + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to ceil.o(i.ceil) for ceil + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) refers to drv_crgu.o(i.drv_crgu_set_lcdc_clk) for drv_crgu_set_lcdc_clk + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info) for hal_intl_fb_get_tx_fb_info + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_function_enable) for drv_lcdc_function_enable + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) for hal_lcdc_upscaler_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_function_disable) for drv_lcdc_function_disable + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_fldc_config) for drv_lcdc_fldc_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_bcsa_config) for drv_lcdc_bcsa_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_fc_config) for drv_lcdc_fc_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_edge_dect_config) for drv_lcdc_edge_dect_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_edge_enh_config) for drv_lcdc_edge_enh_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_vintp_mode_config) for drv_lcdc_vintp_mode_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to drv_lcdc.o(i.drv_lcdc_dith_config) for drv_lcdc_dith_config + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for .ARM.__at_0x1102C + hal_dsi_tx_ctrl.o(i.hal_lcdc_start) refers to hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) for hal_intl_fb_get_memc_flow_mode + hal_dsi_tx_ctrl.o(i.hal_lcdc_start) refers to drv_lcdc.o(i.drv_lcdc_vid_hw_start) for drv_lcdc_vid_hw_start + hal_dsi_tx_ctrl.o(i.hal_lcdc_start) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_dsi_tx_ctrl.o(i.hal_lcdc_start) refers to drv_lcdc.o(i.drv_lcdc_cmd_start) for drv_lcdc_cmd_start + hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) for hal_internal_vsync_get_sync_line + hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) refers to drv_lcdc.o(i.drv_lcdc_ctrl_flow) for drv_lcdc_ctrl_flow + hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) refers to drv_lcdc.o(i.drv_lcdc_config_src_parameter) for drv_lcdc_config_src_parameter + hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) refers to hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) for hal_intl_fb_get_memc_flow_mode + hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) refers to drv_lcdc.o(i.drv_lcdc_set_prefetch) for drv_lcdc_set_prefetch + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to dfltui.o(.text) for __aeabi_ui2d + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to dadd.o(.text) for __aeabi_dadd + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to drv_lcdc.o(i.drv_lcdc_function_enable) for drv_lcdc_function_enable + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_req_update) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for sg_pq_para + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) refers to drv_lcdc.o(i.drv_lcdc_bcsa_config) for drv_lcdc_bcsa_config + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) refers to drv_lcdc.o(i.drv_lcdc_fc_config) for drv_lcdc_fc_config + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) refers to drv_lcdc.o(i.drv_lcdc_edge_dect_config) for drv_lcdc_edge_dect_config + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) refers to drv_lcdc.o(i.drv_lcdc_edge_enh_config) for drv_lcdc_edge_enh_config + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) refers to hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) for sg_pq_para + hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) refers to cfcmple.o(.text) for __aeabi_cfcmple + hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) for hal_dsi_tx_ctrl_init + hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) for hal_internal_vsync_set_tx_state + hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) refers to hal_dsi_tx_ctrl.o(.bss) for .bss + hal_dsi_tx_ctrl.o(i.hal_vsync_func_update) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_dsi_tx_ctrl.o(i.hal_vsync_func_update) refers to hal_dsi_tx_ctrl.o(.data) for .data + hal_gpio.o(i.hal_gpio_config_pad) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_gpio.o(i.hal_gpio_config_pad) refers to hal_gpio.o(i.hal_gpio_init_input) for hal_gpio_init_input + hal_gpio.o(i.hal_gpio_config_pad) refers to hal_gpio.o(i.hal_gpio_init_output) for hal_gpio_init_output + hal_gpio.o(i.hal_gpio_ctrl_eint) refers to drv_gpio.o(i.drv_gpio_set_int) for drv_gpio_set_int + hal_gpio.o(i.hal_gpio_get_input_data) refers to drv_gpio.o(i.drv_gpio_get_input_data) for drv_gpio_get_input_data + hal_gpio.o(i.hal_gpio_get_pull_state) refers to drv_gpio.o(i.drv_gpio_get_attribute) for drv_gpio_get_attribute + hal_gpio.o(i.hal_gpio_get_pull_state) refers to hal_gpio.o(.constdata) for .constdata + hal_gpio.o(i.hal_gpio_init_eint) refers to drv_gpio.o(i.drv_gpio_set_ioe) for drv_gpio_set_ioe + hal_gpio.o(i.hal_gpio_init_eint) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_gpio.o(i.hal_gpio_init_eint) refers to drv_sys_cfg.o(i.drv_sys_cfg_sel_gpio_group) for drv_sys_cfg_sel_gpio_group + hal_gpio.o(i.hal_gpio_init_eint) refers to drv_sys_cfg.o(i.drv_sys_cfg_sel_int_trig) for drv_sys_cfg_sel_int_trig + hal_gpio.o(i.hal_gpio_init_eint) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + hal_gpio.o(i.hal_gpio_init_input) refers to drv_gpio.o(i.drv_gpio_set_ioe) for drv_gpio_set_ioe + hal_gpio.o(i.hal_gpio_init_input) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_gpio.o(i.hal_gpio_init_output) refers to hal_gpio.o(i.drv_gpio_set_output_data) for drv_gpio_set_output_data + hal_gpio.o(i.hal_gpio_init_output) refers to drv_gpio.o(i.drv_gpio_set_ioe) for drv_gpio_set_ioe + hal_gpio.o(i.hal_gpio_init_output) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_gpio.o(i.hal_gpio_reg_eint_cb) refers to drv_gpio.o(i.drv_gpio_register_callback) for drv_gpio_register_callback + hal_gpio.o(i.hal_gpio_set_ap_reset_int) refers to drv_gpio.o(i.drv_gpio_register_ap_reset_callback) for drv_gpio_register_ap_reset_callback + hal_gpio.o(i.hal_gpio_set_ap_reset_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_trig) for drv_sys_cfg_sel_ap_rst_trig + hal_gpio.o(i.hal_gpio_set_ap_reset_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + hal_gpio.o(i.hal_gpio_set_ap_reset_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + hal_gpio.o(i.hal_gpio_set_driving_strength) refers to drv_gpio.o(i.drv_gpio_get_attribute) for drv_gpio_get_attribute + hal_gpio.o(i.hal_gpio_set_driving_strength) refers to drv_gpio.o(i.drv_gpio_set_attribute) for drv_gpio_set_attribute + hal_gpio.o(i.hal_gpio_set_driving_strength) refers to hal_gpio.o(.constdata) for .constdata + hal_gpio.o(i.hal_gpio_set_high_impedance) refers to drv_gpio.o(i.drv_gpio_set_ioe) for drv_gpio_set_ioe + hal_gpio.o(i.hal_gpio_set_high_impedance) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_gpio.o(i.hal_gpio_set_high_impedance) refers to hal_gpio.o(i.hal_gpio_set_pull_state) for hal_gpio_set_pull_state + hal_gpio.o(i.hal_gpio_set_mode) refers to drv_gpio.o(i.drv_gpio_set_mode) for drv_gpio_set_mode + hal_gpio.o(i.hal_gpio_set_mode) refers to hal_gpio.o(.constdata) for .constdata + hal_gpio.o(i.hal_gpio_set_output_data) refers to hal_gpio.o(i.drv_gpio_set_output_data) for drv_gpio_set_output_data + hal_gpio.o(i.hal_gpio_set_pull_state) refers to drv_gpio.o(i.drv_gpio_get_attribute) for drv_gpio_get_attribute + hal_gpio.o(i.hal_gpio_set_pull_state) refers to drv_gpio.o(i.drv_gpio_set_attribute) for drv_gpio_set_attribute + hal_gpio.o(i.hal_gpio_set_pull_state) refers to hal_gpio.o(.constdata) for .constdata + hal_gpio.o(i.hal_gpio_set_schmitt_trigger) refers to drv_gpio.o(i.drv_gpio_get_attribute) for drv_gpio_get_attribute + hal_gpio.o(i.hal_gpio_set_schmitt_trigger) refers to drv_gpio.o(i.drv_gpio_set_attribute) for drv_gpio_set_attribute + hal_gpio.o(i.hal_gpio_set_schmitt_trigger) refers to hal_gpio.o(.constdata) for .constdata + hal_gpio.o(i.hal_gpio_set_slew_rate) refers to drv_gpio.o(i.drv_gpio_get_attribute) for drv_gpio_get_attribute + hal_gpio.o(i.hal_gpio_set_slew_rate) refers to drv_gpio.o(i.drv_gpio_set_attribute) for drv_gpio_set_attribute + hal_gpio.o(i.hal_gpio_set_slew_rate) refers to hal_gpio.o(.constdata) for .constdata + hal_swire.o(i.hal_swire_deinit) refers to drv_swire.o(i.drv_swire_set_int) for drv_swire_set_int + hal_swire.o(i.hal_swire_deinit) refers to drv_swire.o(i.drv_swire_enable) for drv_swire_enable + hal_swire.o(i.hal_swire_deinit) refers to drv_swire.o(i.drv_swire_register_callback) for drv_swire_register_callback + hal_swire.o(i.hal_swire_deinit) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + hal_swire.o(i.hal_swire_deinit) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_swire.o(i.hal_swire_deinit) refers to hal_timer.o(i.hal_timer_deinit) for hal_timer_deinit + hal_swire.o(i.hal_swire_deinit) refers to hal_swire.o(.data) for .data + hal_swire.o(i.hal_swire_enable) refers to drv_swire.o(i.drv_swire_set_power_down) for drv_swire_set_power_down + hal_swire.o(i.hal_swire_enable) refers to drv_swire.o(i.drv_swire_get_pulse_count) for drv_swire_get_pulse_count + hal_swire.o(i.hal_swire_enable) refers to drv_swire.o(i.drv_swire_set_trig_mode) for drv_swire_set_trig_mode + hal_swire.o(i.hal_swire_enable) refers to drv_timer.o(i.drv_timer_enable) for drv_timer_enable + hal_swire.o(i.hal_swire_enable) refers to drv_swire.o(i.drv_swire_set_int) for drv_swire_set_int + hal_swire.o(i.hal_swire_enable) refers to hal_swire.o(.data) for .data + hal_swire.o(i.hal_swire_init) refers to drv_crgu.o(i.drv_crgu_set_clock_div) for drv_crgu_set_clock_div + hal_swire.o(i.hal_swire_init) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_swire.o(i.hal_swire_init) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_swire.o(i.hal_swire_init) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_swire.o(i.hal_swire_init) refers to drv_swire.o(i.drv_swire_set_bit_time) for drv_swire_set_bit_time + hal_swire.o(i.hal_swire_init) refers to drv_swire.o(i.drv_swire_set_power_down) for drv_swire_set_power_down + hal_swire.o(i.hal_swire_init) refers to drv_swire.o(i.drv_swire_enable) for drv_swire_enable + hal_swire.o(i.hal_swire_init) refers to drv_common.o(.data) for g_system_clock + hal_swire.o(i.hal_swire_register_callback) refers to drv_swire.o(i.drv_swire_register_callback) for drv_swire_register_callback + hal_swire.o(i.hal_swire_register_callback) refers to drv_swire.o(i.drv_swire_set_int) for drv_swire_set_int + hal_swire.o(i.hal_swire_set_pulse) refers to drv_swire.o(i.drv_swire_set_trig_mode) for drv_swire_set_trig_mode + hal_swire.o(i.hal_swire_set_pulse) refers to drv_swire.o(i.drv_swire_set_pulse_count) for drv_swire_set_pulse_count + hal_swire.o(i.hal_swire_set_pulse) refers to hal_swire.o(.data) for .data + hal_swire.o(i.hal_swire_set_timer) refers to drv_sys_cfg.o(i.drv_sys_cfg_sel_swire_timer) for drv_sys_cfg_sel_swire_timer + hal_swire.o(i.hal_swire_set_timer) refers to hal_timer.o(i.hal_timer_init) for hal_timer_init + hal_swire.o(i.hal_swire_set_timer) refers to hal_timer.o(i.hal_timer_set_repeat) for hal_timer_set_repeat + hal_swire.o(i.hal_swire_set_timer) refers to drv_timer.o(i.drv_timer_set_compare_val) for drv_timer_set_compare_val + hal_swire.o(i.hal_swire_set_timer) refers to drv_swire.o(i.drv_swire_set_trig_mode) for drv_swire_set_trig_mode + hal_swire.o(i.hal_swire_set_timer) refers to hal_swire.o(.data) for .data + hal_swire.o(i.hal_swire_set_waveform) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_swire.o(i.hal_swire_set_waveform) refers to drv_swire.o(i.drv_swire_set_bit_time) for drv_swire_set_bit_time + hal_swire.o(i.hal_swire_set_waveform) refers to drv_common.o(.data) for g_system_clock + hal_system.o(i.hal_system_disable_systick) refers to drv_common.o(i.drv_common_disable_systick) for drv_common_disable_systick + hal_system.o(i.hal_system_enable_systick) refers to drv_common.o(i.drv_common_enable_systick) for drv_common_enable_systick + hal_system.o(i.hal_system_get_tick) refers to drv_common.o(i.drv_common_get_tick) for drv_common_get_tick + hal_system.o(i.hal_system_idle_mode) refers to drv_common.o(i.drv_common_idle_mode) for drv_common_idle_mode + hal_system.o(i.hal_system_init) refers to drv_pwr.o(i.drv_pwr_set_pll_clk) for drv_pwr_set_pll_clk + hal_system.o(i.hal_system_init) refers to hal_system.o(i.hal_system_updata_sysclk) for hal_system_updata_sysclk + hal_system.o(i.hal_system_init) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_system.o(i.hal_system_init) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_all_int) for drv_sys_cfg_clear_all_int + hal_system.o(i.hal_system_init) refers to drv_common.o(i.drv_common_system_init) for drv_common_system_init + hal_system.o(i.hal_system_init) refers to hal_gpio.o(i.hal_gpio_set_mode) for hal_gpio_set_mode + hal_system.o(i.hal_system_register_systick_cb) refers to drv_common.o(i.drv_common_systick_register_cb) for drv_common_systick_register_cb + hal_system.o(i.hal_system_reset_chip) refers to drv_crgu.o(i.drv_crgu_reset_chip) for drv_crgu_reset_chip + hal_system.o(i.hal_system_updata_sysclk) refers to drv_crgu.o(i.drv_crgu_set_ahb_clk) for drv_crgu_set_ahb_clk + hal_system.o(i.hal_system_updata_sysclk) refers to drv_common.o(.data) for g_system_clock + hal_system.o(i.hal_system_updata_sysclk) refers to drv_common.o(.data) for g_system_delay_step + hal_timer.o(i.hal_timer_deinit) refers to drv_timer.o(i.drv_timer_set_int) for drv_timer_set_int + hal_timer.o(i.hal_timer_deinit) refers to drv_timer.o(i.drv_timer_set_repeat) for drv_timer_set_repeat + hal_timer.o(i.hal_timer_deinit) refers to drv_timer.o(i.drv_timer_enable) for drv_timer_enable + hal_timer.o(i.hal_timer_deinit) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + hal_timer.o(i.hal_timer_deinit) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_timer.o(i.hal_timer_get_status) refers to drv_timer.o(i.drv_timer_get_status) for drv_timer_get_status + hal_timer.o(i.hal_timer_init) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_timer.o(i.hal_timer_init) refers to drv_timer.o(i.drv_timer_set_prescaler) for drv_timer_set_prescaler + hal_timer.o(i.hal_timer_set_repeat) refers to drv_timer.o(i.drv_timer_set_repeat) for drv_timer_set_repeat + hal_timer.o(i.hal_timer_start) refers to drv_timer.o(i.drv_timer_register_callback) for drv_timer_register_callback + hal_timer.o(i.hal_timer_start) refers to drv_timer.o(i.drv_timer_set_compare_val) for drv_timer_set_compare_val + hal_timer.o(i.hal_timer_start) refers to drv_timer.o(i.drv_timer_set_int) for drv_timer_set_int + hal_timer.o(i.hal_timer_start) refers to drv_timer.o(i.drv_timer_enable) for drv_timer_enable + hal_timer.o(i.hal_timer_start_ex) refers to drv_timer.o(i.drv_timer_register_callback) for drv_timer_register_callback + hal_timer.o(i.hal_timer_start_ex) refers to drv_timer.o(i.drv_timer_set_compare_val) for drv_timer_set_compare_val + hal_timer.o(i.hal_timer_start_ex) refers to drv_timer.o(i.drv_timer_set_int) for drv_timer_set_int + hal_timer.o(i.hal_timer_start_ex) refers to drv_timer.o(i.drv_timer_enable) for drv_timer_enable + hal_timer.o(i.hal_timer_stop) refers to drv_timer.o(i.drv_timer_enable) for drv_timer_enable + hal_timer.o(i.hal_timer_stop) refers to drv_timer.o(i.drv_timer_set_int) for drv_timer_set_int + hal_timer.o(i.hal_timer_stop) refers to drv_timer.o(i.drv_timer_register_callback) for drv_timer_register_callback + hal_timer.o(i.hal_timer_stop) refers to drv_timer.o(i.drv_timer_set_compare_val) for drv_timer_set_compare_val + hal_pwr.o(i.hal_pwr_elvcc_close) refers to drv_pwr.o(i.drv_pwr_pwmled_electric_current) for drv_pwr_pwmled_electric_current + hal_pwr.o(i.hal_pwr_elvcc_ldo_en) refers to drv_pwr.o(i.drv_pwr_pwmled_electric_current) for drv_pwr_pwmled_electric_current + hal_pwr.o(i.hal_pwr_elvcc_ldo_en) refers to drv_pwr.o(i.drv_pwr_hv_ldo_mode_sel) for drv_pwr_hv_ldo_mode_sel + hal_pwr.o(i.hal_pwr_elvcc_ldo_en) refers to drv_pwr.o(i.drv_pwr_hv_ldo_mode_clock_sel) for drv_pwr_hv_ldo_mode_clock_sel + hal_pwr.o(i.hal_pwr_elvcc_ldo_en) refers to drv_pwr.o(i.drv_pwr_pwmled_driver_current_Big_step) for drv_pwr_pwmled_driver_current_Big_step + hal_pwr.o(i.hal_pwr_elvcc_vol_set) refers to drv_pwr.o(i.drv_pwr_hv_ldo_voltage_set) for drv_pwr_hv_ldo_voltage_set + hal_pwr.o(i.hal_pwr_enter_deep_sleep_mode) refers to drv_pwr.o(i.drv_pwr_set_wakeup_type) for drv_pwr_set_wakeup_type + hal_pwr.o(i.hal_pwr_enter_deep_sleep_mode) refers to drv_pwr.o(i.drv_pwr_enter_deep_sleep_mode) for drv_pwr_enter_deep_sleep_mode + hal_pwr.o(i.hal_pwr_enter_normal_sleep_mode) refers to drv_pwr.o(i.drv_pwr_enter_sleep_mode_ex) for drv_pwr_enter_sleep_mode_ex + hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode) refers to drv_pwr.o(i.drv_pwr_enter_stop_sleep_mode) for drv_pwr_enter_stop_sleep_mode + hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode) refers to hal_pwr.o(.data) for .data + hal_pwr.o(i.hal_pwr_exit_sleep_mode) refers to drv_pwr.o(i.drv_pwr_exit_sleep_mode) for drv_pwr_exit_sleep_mode + hal_pwr.o(i.hal_pwr_get_reset_flag) refers to drv_crgu.o(i.drv_crgu_get_all_reset_flag) for drv_crgu_get_all_reset_flag + hal_pwr.o(i.hal_pwr_get_reset_flag) refers to drv_pwr.o(i.drv_pwr_get_wakeflag) for drv_pwr_get_wakeflag + hal_pwr.o(i.hal_pwr_get_reset_flag) refers to drv_crgu.o(i.drv_crgu_clear_all_reset_flags) for drv_crgu_clear_all_reset_flags + hal_pwr.o(i.hal_pwr_get_vcc_power_ready) refers to drv_pwr.o(i.drv_pwr_get_power_ready_st) for drv_pwr_get_power_ready_st + hal_pwr.o(i.hal_pwr_ldo13s_en) refers to drv_pwr.o(i.drv_pwr_ldo13s_en) for drv_pwr_ldo13s_en + hal_pwr.o(i.hal_pwr_ldo13s_set) refers to drv_pwr.o(i.drv_pwr_ldo13s_set) for drv_pwr_ldo13s_set + hal_pwr.o(i.hal_pwr_ldo18s_en) refers to drv_pwr.o(i.drv_pwr_ldo18s_en) for drv_pwr_ldo18s_en + hal_pwr.o(i.hal_pwr_ldo18s_set) refers to drv_pwr.o(i.drv_pwr_ldo18s_set) for drv_pwr_ldo18s_set + hal_pwr.o(i.hal_pwr_set_main_power) refers to drv_pwr.o(i.drv_pwr_set_digit_power_sel) for drv_pwr_set_digit_power_sel + hal_pwr.o(i.hal_pwr_set_pvd) refers to drv_pwr.o(i.drv_pwr_set_pvd) for drv_pwr_set_pvd + hal_pwr.o(i.hal_pwr_set_sleep_mode_power) refers to drv_pwr.o(i.drv_pwr_set_breath_screen_power_sel) for drv_pwr_set_breath_screen_power_sel + hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) refers to hal_gpio.o(i.hal_gpio_ctrl_eint) for hal_gpio_ctrl_eint + hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) refers to hal_gpio.o(i.hal_gpio_init_eint) for hal_gpio_init_eint + hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) refers to hal_gpio.o(i.hal_gpio_reg_eint_cb) for hal_gpio_reg_eint_cb + hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) refers to hal_gpio.o(i.hal_gpio_set_ap_reset_int) for hal_gpio_set_ap_reset_int + hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) refers to hal_pwr.o(.data) for .data + hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) refers to hal_pwr.o(i.stop_sleep_cb) for stop_sleep_cb + hal_pwr.o(i.hal_pwr_set_vcc_enable) refers to drv_pwr.o(i.drv_pwr_charge_pump_en) for drv_pwr_charge_pump_en + hal_pwr.o(i.hal_pwr_sw_tp18_en) refers to drv_pwr.o(i.drv_pwr_sw_tp18_en) for drv_pwr_sw_tp18_en + hal_pwr.o(i.stop_sleep_cb) refers to hal_pwr.o(.data) for .data + tau_delay.o(i.delayMs) refers to tau_delay.o(i.delayUs) for delayUs + tau_delay.o(i.delayUs) refers to drv_common.o(.data) for g_system_delay_step + tau_log.o(i.fgetc) refers to hal_uart.o(i.hal_uart_recv_blocking) for hal_uart_recv_blocking + tau_log.o(i.fgetc) refers to hal_system.o(i.hal_system_get_debug_state) for hal_system_get_debug_state + tau_log.o(i.fgetc) refers to hal_system.o(i.hal_system_clear_debug_state) for hal_system_clear_debug_state + tau_log.o(i.fgetc) refers to tau_log.o(.data) for g_log_port + tau_log.o(i.fputc) refers to tau_log.o(i.tau_log_push_log) for tau_log_push_log + tau_log.o(i.fputc) refers to hal_uart.o(i.hal_uart_send_blocking) for hal_uart_send_blocking + tau_log.o(i.fputc) refers to tau_log.o(.data) for g_log_port + tau_log.o(i.tau_log_init) refers to hal_uart.o(i.hal_uart_init) for hal_uart_init + tau_log.o(i.tau_log_init) refers to tau_log.o(.data) for g_log_port + tau_log.o(i.tau_log_printf) refers to memseta.o(.text) for __aeabi_memclr4 + tau_log.o(i.tau_log_printf) refers to strlen.o(.text) for strlen + tau_log.o(i.tau_log_printf) refers to printfa.o(i.__0vsprintf) for vsprintf + tau_log.o(i.tau_log_printf) refers to tau_log.o(i.tau_log_push_log) for tau_log_push_log + tau_log.o(i.tau_log_printf) refers to printfa.o(i.__0printf) for __2printf + tau_log.o(i.tau_log_printf) refers to tau_log.o(.data) for g_log_port + tau_log.o(i.tau_log_printf) refers to tau_log.o(.bss) for g_log_buf + tau_log.o(i.tau_log_push_log) refers to memcpya.o(.text) for __aeabi_memcpy + tau_log.o(i.tau_log_push_log) refers to tau_delay.o(i.delayUs) for delayUs + tau_log.o(.ARM.__at_0x1101C) refers to tau_log.o(.bss) for g_log_buf + hal_uart.o(i.hal_uart0_rx_dma_cb) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart0_tx_dma_cb) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart1_rx_dma_cb) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart1_tx_dma_cb) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart_deinit) refers to drv_uart.o(i.drv_uart_deinit) for drv_uart_deinit + hal_uart.o(i.hal_uart_deinit) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + hal_uart.o(i.hal_uart_deinit) refers to hal_uart.o(.constdata) for .constdata + hal_uart.o(i.hal_uart_dma_path_close) refers to drv_dma.o(i.drv_dma_disable) for drv_dma_disable + hal_uart.o(i.hal_uart_dma_path_close) refers to drv_dma.o(i.drv_dma_deinit) for drv_dma_deinit + hal_uart.o(i.hal_uart_dma_path_close) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_apply_handle) for drv_dma_apply_handle + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_init) for drv_dma_init + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_set_burst) for drv_dma_set_burst + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_register_callback) for drv_dma_register_callback + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_enable_int) for drv_dma_enable_int + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_disable) for drv_dma_disable + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_set_mem_trans_info) for drv_dma_set_mem_trans_info + hal_uart.o(i.hal_uart_dma_recv) refers to drv_dma.o(i.drv_dma_enable) for drv_dma_enable + hal_uart.o(i.hal_uart_dma_recv) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_uart.o(i.hal_uart_dma_recv) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart_dma_recv) refers to hal_uart.o(i.hal_uart0_rx_dma_cb) for hal_uart0_rx_dma_cb + hal_uart.o(i.hal_uart_dma_recv) refers to hal_uart.o(i.hal_uart1_rx_dma_cb) for hal_uart1_rx_dma_cb + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_apply_handle) for drv_dma_apply_handle + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_init) for drv_dma_init + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_set_burst) for drv_dma_set_burst + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_register_callback) for drv_dma_register_callback + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_enable_int) for drv_dma_enable_int + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_disable) for drv_dma_disable + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_set_mem_trans_info) for drv_dma_set_mem_trans_info + hal_uart.o(i.hal_uart_dma_send) refers to drv_dma.o(i.drv_dma_enable) for drv_dma_enable + hal_uart.o(i.hal_uart_dma_send) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_uart.o(i.hal_uart_dma_send) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart_dma_send) refers to hal_uart.o(i.hal_uart0_tx_dma_cb) for hal_uart0_tx_dma_cb + hal_uart.o(i.hal_uart_dma_send) refers to hal_uart.o(i.hal_uart1_tx_dma_cb) for hal_uart1_tx_dma_cb + hal_uart.o(i.hal_uart_init) refers to memseta.o(.text) for __aeabi_memclr4 + hal_uart.o(i.hal_uart_init) refers to drv_uart.o(i.drv_uart_init) for drv_uart_init + hal_uart.o(i.hal_uart_init) refers to drv_uart.o(i.drv_uart_trans_create_handle) for drv_uart_trans_create_handle + hal_uart.o(i.hal_uart_init) refers to hal_uart.o(.constdata) for .constdata + hal_uart.o(i.hal_uart_init) refers to drv_common.o(.data) for g_system_clock + hal_uart.o(i.hal_uart_init) refers to hal_uart.o(.data) for .data + hal_uart.o(i.hal_uart_recv_blocking) refers to drv_uart.o(i.drv_uart_recv_blocking) for drv_uart_recv_blocking + hal_uart.o(i.hal_uart_recv_blocking) refers to hal_uart.o(.constdata) for .constdata + hal_uart.o(i.hal_uart_recv_none_blocking) refers to drv_uart.o(i.drv_uart_recv_none_blocking) for drv_uart_recv_none_blocking + hal_uart.o(i.hal_uart_recv_none_blocking) refers to hal_uart.o(.constdata) for .constdata + hal_uart.o(i.hal_uart_send_blocking) refers to drv_uart.o(i.drv_uart_send_blocking) for drv_uart_send_blocking + hal_uart.o(i.hal_uart_send_blocking) refers to hal_uart.o(.constdata) for .constdata + hal_uart.o(i.hal_uart_send_none_blocking) refers to drv_uart.o(i.drv_uart_send_none_blocking) for drv_uart_send_none_blocking + hal_uart.o(i.hal_uart_send_none_blocking) refers to hal_uart.o(.constdata) for .constdata + hal_internal_vsync.o(i.LCDC_IRQn_Handler) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_vsync.o(i.LCDC_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + hal_internal_vsync.o(i.LCDC_IRQn_Handler) refers to hal_internal_vsync.o(.data) for .data + hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) for hal_intl_fb_cal_fb_info + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to drv_vidc.o(i.drv_vidc_enable) for drv_vidc_enable + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to drv_vidc.o(i.drv_vidc_reset) for drv_vidc_reset + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) for hal_dsi_rx_ctrl_init + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) for hal_internal_vsync_set_tear_mode + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) for hal_internal_vsync_get_sync_line + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) for hal_dsi_rx_ctrl_start + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) for hal_dsi_tx_ctrl_gen_a_tear_signal + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to tau_delay.o(i.delayUs) for delayUs + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) for hal_vsync_reset_lcdc_scaler + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_internal_fb.o(.bss) for g_rx_fb_info + hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_sync_register_lcdc_cb) refers to hal_internal_vsync.o(.data) for .data + hal_internal_vsync.o(i.hal_internal_sync_register_rx_callback) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_sync_set_fb_setting_manual) refers to hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual) for hal_intl_fb_set_fb_info_manual + hal_internal_vsync.o(i.hal_internal_sync_set_fb_setting_manual) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_deinit) refers to memseta.o(.text) for __aeabi_memclr4 + hal_internal_vsync.o(i.hal_internal_vsync_deinit) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_deinit) refers to hal_internal_fb.o(.bss) for g_rx_fb_info + hal_internal_vsync.o(i.hal_internal_vsync_get_rx_state) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(i.check_mipi_rx_tx_video_info) for check_mipi_rx_tx_video_info + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) for hal_intl_fb_cal_fb_info + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_svs.o(i.hal_intl_svs_init_rx) for hal_intl_svs_init_rx + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_dcs.o(i.hal_intl_dcs_init_sw_fltr) for hal_intl_dcs_init_sw_fltr + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to drv_rxbr.o(i.drv_rxbr_register_irq1_callback) for drv_rxbr_register_irq1_callback + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to drv_vidc.o(i.drv_vidc_register_callback) for drv_vidc_register_callback + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to dcs_packet_fifo.o(i.dcs_packet_fifo_init) for dcs_packet_fifo_init + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(i.soft_pro_motion_init) for soft_pro_motion_init + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(.data) for .data + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(i.soft_gen_te) for soft_gen_te + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(i.rxbr_irq1_callback) for rxbr_irq1_callback + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(i.vidc_callback) for vidc_callback + hal_internal_vsync.o(i.hal_internal_vsync_init_rx) refers to hal_internal_vsync.o(i.soft_gen_te_double_buffer) for soft_gen_te_double_buffer + hal_internal_vsync.o(i.hal_internal_vsync_init_tx) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_internal_vsync.o(i.hal_internal_vsync_init_tx) refers to hal_internal_vsync.o(i.check_mipi_rx_tx_video_info) for check_mipi_rx_tx_video_info + hal_internal_vsync.o(i.hal_internal_vsync_init_tx) refers to memseta.o(.text) for __aeabi_memclr4 + hal_internal_vsync.o(i.hal_internal_vsync_init_tx) refers to hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) for hal_intl_fb_cal_fb_info + hal_internal_vsync.o(i.hal_internal_vsync_init_tx) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) refers to hal_internal_vsync.o(i.hal_internal_vsync_deinit) for hal_internal_vsync_deinit + hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) refers to hal_internal_svs.o(i.hal_intl_svs_deinit_rx) for hal_intl_svs_deinit_rx + hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) refers to ffltui.o(.text) for __aeabi_ui2f + hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) refers to fdiv.o(.text) for __aeabi_fdiv + hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) refers to hal_internal_svs.o(i.hal_intl_svs_set_sync_coef) for hal_intl_svs_set_sync_coef + hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_memc.o(i.drv_memc_set_tear_mode) for drv_memc_set_tear_mode + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_lcdc.o(i.drv_lcdc_function_disable) for drv_lcdc_function_disable + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_lcdc.o(i.drv_lcdc_config_int_single) for drv_lcdc_config_int_single + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_memc.o(i.drv_memc_set_frame_drop_select) for drv_memc_set_frame_drop_select + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_lcdc.o(i.drv_lcdc_function_enable) for drv_lcdc_function_enable + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) for hal_internal_vsync_get_sync_line + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_lcdc.o(i.drv_lcdc_set_tear_line) for drv_lcdc_set_tear_line + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to idiv.o(.text) for __aeabi_idivmod + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to drv_lcdc.o(i.drv_lcdc_config_acc_command_mode) for drv_lcdc_config_acc_command_mode + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) refers to hal_internal_fb.o(.bss) for g_rx_fb_info + hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) refers to hal_internal_vsync.o(i.hal_internal_vsync_deinit) for hal_internal_vsync_deinit + hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) refers to hal_internal_svs.o(i.hal_intl_svs_deinit_tx) for hal_intl_svs_deinit_tx + hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) refers to drv_lcdc.o(i.drv_lcdc_function_disable) for drv_lcdc_function_disable + hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) refers to hal_internal_vsync.o(i.soft_pro_motion_init) for soft_pro_motion_init + hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to hal_internal_svs.o(i.hal_intl_svs_set_input_frate) for hal_intl_svs_set_input_frate + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to drv_memc.o(i.drv_memc_rate_transfer_sel) for drv_memc_rate_transfer_sel + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to drv_memc.o(i.drv_memc_sel_vsync) for drv_memc_sel_vsync + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) for drv_rxbr_frame_drop_cfg + hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate) refers to drv_rxbr.o(i.drv_rxbr_hline_rcv0_cfg) for drv_rxbr_hline_rcv0_cfg + hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) refers to dfltui.o(.text) for __aeabi_ui2d + hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) refers to dadd.o(.text) for __aeabi_dadd + hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) refers to hal_internal_vsync.o(i.soft_pro_motion_init) for soft_pro_motion_init + hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_vsync.o(i.drv_rxbr_get_int_source) for drv_rxbr_get_int_source + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_vsync.o(i.soft_double_buffer_update) for soft_double_buffer_update + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_svs.o(i.hal_intl_svs_handle) for hal_intl_svs_handle + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_vsync.o(i.vpre_err_reset) for vpre_err_reset + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to drv_vidc.o(i.drv_vidc_enable) for drv_vidc_enable + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs) for drv_dsi_tx_phy_clock_lane_req_hs + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to drv_lcdc.o(i.drv_lcdc_cmd_start) for drv_lcdc_cmd_start + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_svs.o(i.hal_intl_svs_set_rx_vtt) for hal_intl_svs_set_rx_vtt + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) for drv_rxbr_clear_pkt_buffer + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_fb.o(.bss) for g_rx_fb_info + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.rxbr_irq1_callback) refers to hal_internal_vsync.o(.conststring) for .conststring + hal_internal_vsync.o(i.soft_double_buffer_update) refers to hal_internal_fb.o(.bss) for g_rx_fb_info + hal_internal_vsync.o(i.soft_gen_te) refers to hal_internal_vsync.o(i.soft_tear_adjust_line) for soft_tear_adjust_line + hal_internal_vsync.o(i.soft_gen_te) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.soft_gen_te) refers to hal_internal_vsync.o(.data) for .data + hal_internal_vsync.o(i.soft_gen_te_double_buffer) refers to hal_internal_vsync.o(i.soft_tear_adjust_line) for soft_tear_adjust_line + hal_internal_vsync.o(i.soft_gen_te_double_buffer) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.soft_pro_motion_init) refers to memseta.o(.text) for __aeabi_memclr4 + hal_internal_vsync.o(i.soft_pro_motion_init) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.soft_pro_motion_init) refers to hal_internal_fb.o(.bss) for g_rx_fb_info + hal_internal_vsync.o(i.soft_tear_adjust_line) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.vidc_callback) refers to drv_vidc.o(i.drv_vidc_get_int_source) for drv_vidc_get_int_source + hal_internal_vsync.o(i.vidc_callback) refers to drv_lcdc.o(i.drv_lcdc_function_disable) for drv_lcdc_function_disable + hal_internal_vsync.o(i.vidc_callback) refers to drv_vidc.o(i.drv_vidc_set_irqen) for drv_vidc_set_irqen + hal_internal_vsync.o(i.vidc_callback) refers to drv_vidc.o(i.drv_vidc_clear_irq) for drv_vidc_clear_irq + hal_internal_vsync.o(i.vidc_callback) refers to drv_vidc.o(i.drv_vidc_get_irq_status) for drv_vidc_get_irq_status + hal_internal_vsync.o(i.vidc_callback) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_vsync.o(i.vidc_callback) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_vsync.o(i.vidc_callback) refers to hal_internal_vsync.o(.conststring) for .conststring + hal_internal_vsync.o(i.vpre_err_reset) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + hal_internal_vsync.o(i.vpre_err_reset) refers to drv_vidc.o(i.drv_vidc_reset) for drv_vidc_reset + hal_internal_vsync.o(i.vpre_err_reset) refers to hal_internal_vsync.o(.bss) for .bss + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to hal_internal_dcs.o(i.drv_rxbr_get_status0) for drv_rxbr_get_status0 + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) for hal_intl_dcs_rx_receive_packet + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to drv_dsc_dec.o(i.drv_dsc_dec_get_nslc) for drv_dsc_dec_get_nslc + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to drv_crgu.o(i.drv_crgu_set_dsc_clk) for drv_crgu_set_dsc_clk + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + hal_internal_dcs.o(i.VPRE_IRQn_Handler) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_dcs.o(i.check_pkt_buf_rev) refers to hal_internal_dcs.o(i.drv_rxbr_get_status0) for drv_rxbr_get_status0 + hal_internal_dcs.o(i.check_pkt_buf_rev) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_dcs.o(i.check_pkt_buf_rev) refers to drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) for drv_rxbr_clear_pkt_buffer + hal_internal_dcs.o(i.check_pkt_buf_rev) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_dcs.o(i.hal_intl_dcs_init_sw_fltr) refers to hal_internal_dcs.o(.bss) for .bss + hal_internal_dcs.o(i.hal_intl_dcs_init_sw_fltr) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_dcs.o(i.hal_intl_dcs_register_write_cmd_entry) refers to hal_internal_dcs.o(.data) for .data + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to hal_internal_dcs.o(i.hal_intl_dcs_sw_filter_handle) for hal_intl_dcs_sw_filter_handle + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to dcs_packet_fifo.o(i.dcs_packet_fifo_alloc) for dcs_packet_fifo_alloc + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) for hal_dsi_rx_ctrl_dcs_async_handler + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_ddi_crc_en) for drv_dsi_rx_get_ddi_crc_en + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to hal_internal_dcs.o(i.check_pkt_buf_rev) for check_pkt_buf_rev + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) for drv_dsi_tx_command_put_payload + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) refers to hal_internal_dcs.o(.data) for .data + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) refers to hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) for hal_intl_dcs_rx_get_dcs_packet_data + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) refers to hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) for hal_intl_dcs_rx_receive_pps + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) refers to drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) for drv_rxbr_clear_pkt_buffer + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to memseta.o(.text) for __aeabi_memclr4 + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) for drv_rxbr_clear_pkt_buffer + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to hal_internal_dcs.o(i.check_pkt_buf_rev) for check_pkt_buf_rev + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to memcmp.o(.text) for memcmp + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en) for drv_dsi_rx_get_compression_en + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to drv_dsc_dec.o(i.drv_dsc_dec_enable) for drv_dsc_dec_enable + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to hal_internal_dcs.o(.conststring) for .conststring + hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) refers to memseta.o(.text) for __aeabi_memset + hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) refers to drv_rxbr.o(i.drv_rxbr_set_filter_regs) for drv_rxbr_set_filter_regs + hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) refers to hal_internal_dcs.o(.bss) for .bss + hal_internal_dcs.o(i.hal_intl_dcs_set_dcs_direct_mode) refers to hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) for hal_intl_dcs_set_auto_hw_filter + hal_internal_dcs.o(i.hal_intl_dcs_set_dcs_direct_mode) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_dcs.o(i.hal_intl_dcs_sw_filter_handle) refers to hal_internal_dcs.o(.data) for .data + hal_internal_dcs.o(i.hal_intl_dcs_sw_filter_handle) refers to hal_internal_dcs.o(.bss) for .bss + hal_internal_dcs.o(.data) refers to hal_internal_dcs.o(.bss) for g_imm_buffer + hal_internal_fb.o(i.ha_intl_fb_check_pu_size) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_fb.o(i.ha_intl_fb_check_pu_size) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to memseta.o(.text) for __aeabi_memclr4 + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to hal_internal_fb.o(i.hal_intl_fb_flow_control_adapter) for hal_intl_fb_flow_control_adapter + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to hal_internal_fb.o(i.hal_intl_fb_check_bandwidth) for hal_intl_fb_check_bandwidth + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to hal_internal_fb.o(i.ha_intl_fb_check_pu_size) for ha_intl_fb_check_pu_size + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to hal_internal_fb.o(i.hal_intl_fb_edge_resize) for hal_intl_fb_edge_resize + hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_check_bandwidth) refers to hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) for hal_internal_sync_get_hight_performan_mode + hal_internal_fb.o(i.hal_intl_fb_check_bandwidth) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_fb.o(i.hal_intl_fb_check_bandwidth) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_fb.o(i.hal_intl_fb_edge_resize) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_fb.o(i.hal_intl_fb_edge_resize) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_flow_control_adapter) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info) refers to memcpya.o(.text) for __aeabi_memcpy4 + hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_get_user_flow) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual) refers to hal_internal_fb.o(.bss) for .bss + hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual) refers to hal_internal_vsync.o(.bss) for g_vsync_handle + hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual) refers to hal_internal_fb.o(.conststring) for .conststring + hal_internal_svs.o(i.hal_intl_svs_deinit_rx) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_internal_svs.o(i.hal_intl_svs_deinit_rx) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_deinit_rx) refers to hal_internal_svs.o(i.svs_wait_start) for svs_wait_start + hal_internal_svs.o(i.hal_intl_svs_deinit_tx) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_handle) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_init_rx) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_internal_svs.o(i.hal_intl_svs_init_rx) refers to memseta.o(.text) for __aeabi_memclr4 + hal_internal_svs.o(i.hal_intl_svs_init_rx) refers to hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) for hal_intl_svs_update_rxbr_clk + hal_internal_svs.o(i.hal_intl_svs_init_rx) refers to hal_internal_fb.o(i.hal_intl_fb_get_user_flow) for hal_intl_fb_get_user_flow + hal_internal_svs.o(i.hal_intl_svs_init_rx) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_init_rx) refers to hal_internal_svs.o(i.svs_wait_start) for svs_wait_start + hal_internal_svs.o(i.hal_intl_svs_init_tx) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_set_input_frate) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_internal_svs.o(i.hal_intl_svs_set_input_frate) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_svs.o(i.hal_intl_svs_set_input_frate) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_set_input_frate) refers to hal_internal_svs.o(i.svs_wait_start) for svs_wait_start + hal_internal_svs.o(i.hal_intl_svs_set_input_frate) refers to hal_internal_svs.o(i.svs_wait_fr_stab) for svs_wait_fr_stab + hal_internal_svs.o(i.hal_intl_svs_set_rx_vtt) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_set_sync_coef) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) refers to drv_crgu.o(i.drv_crgu_get_rxbr_clk) for drv_crgu_get_rxbr_clk + hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) refers to dfltui.o(.text) for __aeabi_ui2d + hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) refers to dmul.o(.text) for __aeabi_dmul + hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.svs_direct_mode_setting) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_svs.o(i.svs_direct_mode_setting) refers to hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) for hal_intl_fb_get_rx_fb_info + hal_internal_svs.o(i.svs_direct_mode_setting) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_svs.o(i.svs_direct_mode_setting) refers to drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg) for drv_rxbr_hline_rcv1_cfg + hal_internal_svs.o(i.svs_direct_mode_setting) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.svs_get_rel_intv) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_svs.o(i.svs_get_rel_intv) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.svs_sync_handle) refers to hal_internal_svs.o(i.svs_get_rel_intv) for svs_get_rel_intv + hal_internal_svs.o(i.svs_sync_handle) refers to ffltui.o(.text) for __aeabi_ui2f + hal_internal_svs.o(i.svs_sync_handle) refers to fdiv.o(.text) for __aeabi_fdiv + hal_internal_svs.o(i.svs_sync_handle) refers to fmul.o(.text) for __aeabi_fmul + hal_internal_svs.o(i.svs_sync_handle) refers to f2d.o(.text) for __aeabi_f2d + hal_internal_svs.o(i.svs_sync_handle) refers to dadd.o(.text) for __aeabi_dadd + hal_internal_svs.o(i.svs_sync_handle) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_internal_svs.o(i.svs_sync_handle) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.svs_wait_fr_stab) refers to hal_internal_svs.o(i.svs_get_rel_intv) for svs_get_rel_intv + hal_internal_svs.o(i.svs_wait_fr_stab) refers to drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) for drv_rxbr_frame_drop_cfg + hal_internal_svs.o(i.svs_wait_fr_stab) refers to uidiv.o(.text) for __aeabi_uidivmod + hal_internal_svs.o(i.svs_wait_fr_stab) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + hal_internal_svs.o(i.svs_wait_fr_stab) refers to ffltui.o(.text) for __aeabi_ui2f + hal_internal_svs.o(i.svs_wait_fr_stab) refers to fmul.o(.text) for __aeabi_fmul + hal_internal_svs.o(i.svs_wait_fr_stab) refers to ffixui.o(.text) for __aeabi_f2uiz + hal_internal_svs.o(i.svs_wait_fr_stab) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.svs_wait_fr_stab) refers to hal_internal_svs.o(i.svs_sync_handle) for svs_sync_handle + hal_internal_svs.o(i.svs_wait_start) refers to hal_internal_svs.o(i.svs_get_rel_intv) for svs_get_rel_intv + hal_internal_svs.o(i.svs_wait_start) refers to drv_crgu.o(i.drv_crgu_get_rxbr_clk) for drv_crgu_get_rxbr_clk + hal_internal_svs.o(i.svs_wait_start) refers to ffltui.o(.text) for __aeabi_ui2f + hal_internal_svs.o(i.svs_wait_start) refers to fdiv.o(.text) for __aeabi_fdiv + hal_internal_svs.o(i.svs_wait_start) refers to hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) for hal_internal_vsync_get_tx_state + hal_internal_svs.o(i.svs_wait_start) refers to fmul.o(.text) for __aeabi_fmul + hal_internal_svs.o(i.svs_wait_start) refers to f2d.o(.text) for __aeabi_f2d + hal_internal_svs.o(i.svs_wait_start) refers to ceil.o(i.ceil) for ceil + hal_internal_svs.o(i.svs_wait_start) refers to dfixui.o(.text) for __aeabi_d2uiz + hal_internal_svs.o(i.svs_wait_start) refers to hal_internal_svs.o(i.svs_direct_mode_setting) for svs_direct_mode_setting + hal_internal_svs.o(i.svs_wait_start) refers to drv_rxbr.o(i.drv_rxbr_clear_status0) for drv_rxbr_clear_status0 + hal_internal_svs.o(i.svs_wait_start) refers to drv_rxbr.o(i.drv_rxbr_set_inten) for drv_rxbr_set_inten + hal_internal_svs.o(i.svs_wait_start) refers to drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg) for drv_rxbr_hline_rcv1_cfg + hal_internal_svs.o(i.svs_wait_start) refers to hal_internal_svs.o(.bss) for .bss + hal_internal_svs.o(i.svs_wait_start) refers to hal_internal_svs.o(i.svs_wait_fr_stab) for svs_wait_fr_stab + drv_common.o(i.HardFault_Handler) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_common.o(i.SysTick_Handler) refers to drv_common.o(.data) for .data + drv_common.o(i.drv_common_enable_systick) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_common.o(i.drv_common_enable_systick) refers to drv_common.o(.data) for .data + drv_common.o(i.drv_common_get_tick) refers to drv_common.o(.data) for .data + drv_common.o(i.drv_common_system_init) refers to drv_se.o(i.drv_se_init) for drv_se_init + drv_common.o(i.drv_common_systick_register_cb) refers to drv_common.o(.data) for .data + drv_crgu.o(i.drv_crgu_get_rxbr_clk) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_crgu.o(i.drv_crgu_get_system_clk) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_dsc_dec.o(i.drv_dsc_dec_enable) refers to drv_se.o(i.drv_se_set_dsc) for drv_se_set_dsc + drv_gpio.o(i.AP_NRESET_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_gpio.o(i.AP_NRESET_IRQn_Handler) refers to drv_gpio.o(.data) for .data + drv_gpio.o(i.EXTI_INT0_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT1_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT2_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT3_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT4_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT5_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT6_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.EXTI_INT7_IRQn_Handler) refers to drv_gpio.o(i.drv_gpio_handle_int) for drv_gpio_handle_int + drv_gpio.o(i.drv_gpio_handle_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_gpio.o(i.drv_gpio_handle_int) refers to drv_gpio.o(.bss) for .bss + drv_gpio.o(i.drv_gpio_register_ap_reset_callback) refers to drv_gpio.o(.data) for .data + drv_gpio.o(i.drv_gpio_register_callback) refers to drv_gpio.o(.bss) for .bss + drv_gpio.o(i.drv_gpio_set_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_pwr.o(i.drv_pwr_analog_pwm_en) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_elvcc_pwm_en) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_elvcc_pwm_en) refers to tau_delay.o(i.delayMs) for delayMs + drv_pwr.o(i.drv_pwr_enter_sleep_mode) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_enter_sleep_mode) refers to drv_pwr.o(i.drv_pwr_por_mode_flag) for drv_pwr_por_mode_flag + drv_pwr.o(i.drv_pwr_enter_stop_sleep_mode) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_exit_sleep_mode) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_hv_ldo_mode_clock_sel) refers to drv_pwr.o(i.drv_pwr_hv_ldo_10M_clock) for drv_pwr_hv_ldo_10M_clock + drv_pwr.o(i.drv_pwr_pwm_output_pwm_led) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_set_breath_screen_power_sel) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_set_digit_power_sel) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_set_system_clk) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_pwr.o(i.drv_pwr_set_wakeup_type) refers to drv_pwr.o(i.drv_pwr_write_lock) for drv_pwr_write_lock + drv_swire.o(i.SWIRE_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_swire.o(i.SWIRE_IRQn_Handler) refers to drv_swire.o(.data) for .data + drv_swire.o(i.drv_swire_register_callback) refers to drv_swire.o(.data) for .data + drv_swire.o(i.drv_swire_set_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_sys_cfg.o(i.drv_sys_cfg_sel_dma_req) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_timer.o(i.TIMER0_IRQn_Handler) refers to drv_timer.o(i.drv_timer_handle_interrupt) for drv_timer_handle_interrupt + drv_timer.o(i.TIMER1_IRQn_Handler) refers to drv_timer.o(i.drv_timer_handle_interrupt) for drv_timer_handle_interrupt + drv_timer.o(i.TIMER2_IRQn_Handler) refers to drv_timer.o(i.drv_timer_handle_interrupt) for drv_timer_handle_interrupt + drv_timer.o(i.TIMER3_IRQn_Handler) refers to drv_timer.o(i.drv_timer_handle_interrupt) for drv_timer_handle_interrupt + drv_timer.o(i.drv_timer_clear_status_flags) refers to drv_timer.o(i.drv_timer_get_instance) for drv_timer_get_instance + drv_timer.o(i.drv_timer_clear_status_flags) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_timer.o(i.drv_timer_enable) refers to drv_timer.o(i.drv_timer_get_instance) for drv_timer_get_instance + drv_timer.o(i.drv_timer_get_instance) refers to drv_timer.o(.data) for .data + drv_timer.o(i.drv_timer_get_status) refers to drv_timer.o(i.drv_timer_get_instance) for drv_timer_get_instance + drv_timer.o(i.drv_timer_handle_interrupt) refers to drv_timer.o(i.drv_timer_clear_status_flags) for drv_timer_clear_status_flags + drv_timer.o(i.drv_timer_handle_interrupt) refers to drv_timer.o(i.drv_timer_set_int) for drv_timer_set_int + drv_timer.o(i.drv_timer_handle_interrupt) refers to drv_timer.o(i.drv_timer_set_compare_val) for drv_timer_set_compare_val + drv_timer.o(i.drv_timer_handle_interrupt) refers to drv_timer.o(.data) for .data + drv_timer.o(i.drv_timer_register_callback) refers to drv_timer.o(.data) for .data + drv_timer.o(i.drv_timer_set_compare_val) refers to drv_timer.o(i.drv_timer_get_instance) for drv_timer_get_instance + drv_timer.o(i.drv_timer_set_compare_val) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_timer.o(i.drv_timer_set_compare_val) refers to drv_timer.o(.data) for .data + drv_timer.o(i.drv_timer_set_compare_val) refers to drv_common.o(.data) for g_system_clock + drv_timer.o(i.drv_timer_set_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_timer.o(i.drv_timer_set_prescaler) refers to drv_timer.o(i.drv_timer_get_instance) for drv_timer_get_instance + drv_timer.o(i.drv_timer_set_prescaler) refers to drv_timer.o(.data) for .data + drv_timer.o(i.drv_timer_set_repeat) refers to drv_timer.o(.data) for .data + dcs_packet_fifo.o(i.dcs_packet_fifo_alloc) refers to dcs_packet_fifo.o(.bss) for .bss + dcs_packet_fifo.o(i.dcs_packet_fifo_init) refers to dcs_packet_fifo.o(.bss) for .bss + dcs_packet_fifo.o(i.dcs_packet_free_fifo_header) refers to dcs_packet_fifo.o(.bss) for .bss + dcs_packet_fifo.o(i.dcs_packet_get_fifo_header) refers to dcs_packet_fifo.o(.bss) for .bss + dcs_packet_fifo.o(i.dcs_packet_get_fifo_size) refers to dcs_packet_fifo.o(.bss) for .bss + drv_se.o(i.drv_se_init) refers to drv_efuse.o(i.drv_efuse_enter_inactive) for drv_efuse_enter_inactive + drv_se.o(i.drv_se_init) refers to drv_efuse.o(i.drv_efuse_read) for drv_efuse_read + drv_se.o(i.drv_se_init) refers to drv_se.o(.data) for .data + drv_se.o(i.drv_se_set_dsc) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_se.o(i.drv_se_set_dsc) refers to drv_se.o(.data) for .data + drv_se.o(i.drv_se_set_lcdc) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_se.o(i.drv_se_set_lcdc) refers to drv_se.o(.data) for .data + drv_se.o(i.drv_se_set_memc) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_se.o(i.drv_se_set_memc) refers to drv_se.o(.data) for .data + drv_se.o(i.drv_se_set_rxbr) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_se.o(i.drv_se_set_rxbr) refers to drv_se.o(.data) for .data + drv_se.o(i.drv_se_set_vidc) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_se.o(i.drv_se_set_vidc) refers to drv_se.o(.data) for .data + drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler) refers to drv_dsi_rx.o(.data) for .data + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp) for drv_dsi_rx_get_color_bpp + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to ffltui.o(.text) for __aeabi_ui2f + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to fdiv.o(.text) for __aeabi_fdiv + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to fmul.o(.text) for __aeabi_fmul + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to drv_dsi_rx.o(i.drv_dsi_rx_get_color_pcc) for drv_dsi_rx_get_color_pcc + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to fadd.o(.text) for __aeabi_fadd + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to cfrcmple.o(.text) for __aeabi_cfrcmple + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to f2d.o(.text) for __aeabi_f2d + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to dadd.o(.text) for __aeabi_dadd + drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) refers to dfixui.o(.text) for __aeabi_d2uiz + drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_dsi_rx.o(i.drv_dsi_rx_get_phy_stopstate) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_dsi_rx.o(i.drv_dsi_rx_set_drv_log_level) refers to drv_dsi_rx.o(.data) for .data + drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) refers to drv_phy_common.o(i.drv_phy_test_clear) for drv_phy_test_clear + drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) refers to drv_phy_common.o(i.drv_phy_test_lock) for drv_phy_test_lock + drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ulpsactivenot) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) refers to drv_dsi_tx.o(i.drv_tx_phy_test_enter) for drv_tx_phy_test_enter + drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) refers to drv_phy_common.o(i.drv_phy_test_clear) for drv_phy_test_clear + drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) refers to drv_dsi_tx.o(i.drv_tx_phy_test_write_code) for drv_tx_phy_test_write_code + drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) refers to drv_dsi_tx.o(i.drv_tx_phy_test_exit) for drv_tx_phy_test_exit + drv_dsi_tx.o(i.drv_dsi_tx_phy_trigger) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) for drv_dsi_tx_phy_status_stopstate + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_enter) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) for drv_dsi_tx_phy_status_stopstate + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_enter) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_pll_lock) for drv_dsi_tx_phy_status_pll_lock + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_enter) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ulpsactivenot) for drv_dsi_tx_phy_status_ulpsactivenot + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_enter) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_exit) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_exit) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ulpsactivenot) for drv_dsi_tx_phy_status_ulpsactivenot + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_exit) refers to drv_dsi_tx.o(i.drv_dsi_tx_phy_status_pll_lock) for drv_dsi_tx_phy_status_pll_lock + drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_exit) refers to drv_dsi_tx.o(i.drv_dsi_tx_version) for drv_dsi_tx_version + drv_dsi_tx.o(i.drv_dsi_tx_set_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_dsi_tx.o(i.drv_dsi_tx_set_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_lcdc.o(i.drv_lcdc_clear_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_lcdc.o(i.drv_lcdc_cmd_start) refers to drv_se.o(i.drv_se_set_lcdc) for drv_se_set_lcdc + drv_lcdc.o(i.drv_lcdc_ctrl_flow) refers to drv_lcdc.o(i.drv_lcdc_function_enable) for drv_lcdc_function_enable + drv_lcdc.o(i.drv_lcdc_part_display_config) refers to drv_lcdc.o(i.drv_lcdc_pixel_value_config) for drv_lcdc_pixel_value_config + drv_lcdc.o(i.drv_lcdc_set_int) refers to drv_lcdc.o(i.drv_lcdc_clear_int) for drv_lcdc_clear_int + drv_lcdc.o(i.drv_lcdc_set_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_lcdc.o(i.drv_lcdc_vid_hw_start) refers to drv_se.o(i.drv_se_set_lcdc) for drv_se_set_lcdc + drv_memc.o(i.MEMC_IRQn_Handler) refers to drv_memc.o(i.drv_memc_get_status) for drv_memc_get_status + drv_memc.o(i.MEMC_IRQn_Handler) refers to drv_memc.o(i.drv_memc_clear_status) for drv_memc_clear_status + drv_memc.o(i.MEMC_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_memc.o(i.drv_memc_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_memc.o(i.drv_memc_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_memc.o(i.drv_memc_rate_transfer_sel) refers to drv_se.o(i.drv_se_set_memc) for drv_se_set_memc + drv_memc.o(i.drv_memc_set_ltpo_mode) refers to drv_se.o(i.drv_se_set_memc) for drv_se_set_memc + drv_rxbr.o(i.VPRE1_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_rxbr.o(i.VPRE1_IRQn_Handler) refers to drv_rxbr.o(.data) for .data + drv_rxbr.o(i.drv_rxbr_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_rxbr.o(i.drv_rxbr_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_rxbr.o(i.drv_rxbr_enable_irq) refers to drv_rxbr.o(i.__NVIC_EnableIRQ) for __NVIC_EnableIRQ + drv_rxbr.o(i.drv_rxbr_enable_irq) refers to drv_rxbr.o(i.__NVIC_DisableIRQ) for __NVIC_DisableIRQ + drv_rxbr.o(i.drv_rxbr_register_irq0_callback) refers to drv_rxbr.o(.data) for .data + drv_rxbr.o(i.drv_rxbr_register_irq1_callback) refers to drv_rxbr.o(.data) for .data + drv_rxbr.o(i.drv_rxbr_set_cmd_filter) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_rxbr.o(i.drv_rxbr_set_cmd_response) refers to hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) for __ARM_common_switch8 + drv_rxbr.o(i.drv_rxbr_set_color_format) refers to drv_se.o(i.drv_se_set_rxbr) for drv_se_set_rxbr + drv_rxbr.o(i.drv_rxbr_soft_reset) refers to tau_delay.o(i.delayMs) for delayMs + drv_rxbr.o(i.drv_rxbr_sw_reset) refers to drv_crgu.o(i.drv_crgu_set_reset) for drv_crgu_set_reset + drv_rxbr.o(i.drv_rxbr_sw_reset) refers to drv_vidc.o(i.drv_vidc_reset) for drv_vidc_reset + drv_vidc.o(i.VIDC_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_vidc.o(i.VIDC_IRQn_Handler) refers to drv_vidc.o(.data) for .data + drv_vidc.o(i.drv_vidc_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_vidc.o(i.drv_vidc_enable_irq) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_vidc.o(i.drv_vidc_register_callback) refers to drv_vidc.o(.data) for .data + drv_vidc.o(i.drv_vidc_set_src_parameter) refers to drv_se.o(i.drv_se_set_vidc) for drv_se_set_vidc + drv_dma.o(i.DMA_IRQn_Handler) refers to drv_dma.o(i.drv_dma_get_int_source) for drv_dma_get_int_source + drv_dma.o(i.DMA_IRQn_Handler) refers to drv_dma.o(i.drv_dma_clear_status) for drv_dma_clear_status + drv_dma.o(i.DMA_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_dma.o(i.DMA_IRQn_Handler) refers to drv_dma.o(.bss) for .bss + drv_dma.o(i.DMA_IRQn_Handler) refers to drv_dma.o(.data) for .data + drv_dma.o(i.drv_dma_apply_handle) refers to tau_log.o(i.tau_log_printf) for tau_log_printf + drv_dma.o(i.drv_dma_apply_handle) refers to drv_dma.o(.data) for .data + drv_dma.o(i.drv_dma_apply_handle) refers to drv_dma.o(.constdata) for .constdata + drv_dma.o(i.drv_dma_deinit) refers to drv_dma.o(i.drv_dma_disable_int) for drv_dma_disable_int + drv_dma.o(i.drv_dma_disable_int) refers to drv_dma.o(i.drv_dma_int_list_delete) for drv_dma_int_list_delete + drv_dma.o(i.drv_dma_disable_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_dma.o(i.drv_dma_enable_int) refers to drv_dma.o(i.drv_dma_int_list_inset) for drv_dma_int_list_inset + drv_dma.o(i.drv_dma_enable_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_dma.o(i.drv_dma_init) refers to drv_per_common.o(i.drv_per_set_clock) for drv_per_set_clock + drv_dma.o(i.drv_dma_init) refers to drv_dma.o(i.drv_dma_update_handle_setting) for drv_dma_update_handle_setting + drv_dma.o(i.drv_dma_int_list_delete) refers to drv_dma.o(.bss) for .bss + drv_dma.o(i.drv_dma_int_list_inset) refers to drv_dma.o(.bss) for .bss + drv_dma.o(i.drv_dma_update_handle_setting) refers to drv_sys_cfg.o(i.drv_sys_cfg_sel_dma_req) for drv_sys_cfg_sel_dma_req + drv_dma.o(i.drv_dma_update_req_by_default) refers to drv_dma.o(i.drv_dma_update_handle_setting) for drv_dma_update_handle_setting + drv_dma.o(i.drv_dma_update_req_by_default) refers to drv_dma.o(.constdata) for .constdata + drv_uart.o(i.UART_IRQn_Handler) refers to drv_uart.o(i.drv_uart_int_trans_handle) for drv_uart_int_trans_handle + drv_uart.o(i.UART_IRQn_Handler) refers to drv_uart.o(i.drv_uart_config_int) for drv_uart_config_int + drv_uart.o(i.UART_IRQn_Handler) refers to drv_uart.o(i.drv_uart_abort_recv) for drv_uart_abort_recv + drv_uart.o(i.UART_IRQn_Handler) refers to drv_uart.o(i.drv_uart_abort_send) for drv_uart_abort_send + drv_uart.o(i.UART_IRQn_Handler) refers to drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) for drv_sys_cfg_clear_pending + drv_uart.o(i.UART_IRQn_Handler) refers to drv_uart.o(.constdata) for .constdata + drv_uart.o(i.UART_IRQn_Handler) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_abort_recv) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_abort_recv) refers to drv_uart.o(i.drv_uart_config_int) for drv_uart_config_int + drv_uart.o(i.drv_uart_abort_recv) refers to drv_uart.o(i.drv_uart_reset_rx_fifo) for drv_uart_reset_rx_fifo + drv_uart.o(i.drv_uart_abort_recv) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_abort_send) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_abort_send) refers to drv_uart.o(i.drv_uart_config_int) for drv_uart_config_int + drv_uart.o(i.drv_uart_abort_send) refers to drv_uart.o(i.drv_uart_reset_tx_fifo) for drv_uart_reset_tx_fifo + drv_uart.o(i.drv_uart_abort_send) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_deinit) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_deinit) refers to drv_uart.o(i.drv_uart_enable_clk) for drv_uart_enable_clk + drv_uart.o(i.drv_uart_deinit) refers to memseta.o(.text) for __aeabi_memclr4 + drv_uart.o(i.drv_uart_deinit) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_enable_clk) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + drv_uart.o(i.drv_uart_enable_int) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_enable_int) refers to drv_sys_cfg.o(i.drv_sys_cfg_set_int) for drv_sys_cfg_set_int + drv_uart.o(i.drv_uart_get_def_cfg) refers to memseta.o(.text) for __aeabi_memclr4 + drv_uart.o(i.drv_uart_get_def_cfg) refers to drv_common.o(.data) for g_system_clock + drv_uart.o(i.drv_uart_get_instance) refers to drv_uart.o(.constdata) for .constdata + drv_uart.o(i.drv_uart_init) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_init) refers to drv_uart.o(i.drv_uart_enable_clk) for drv_uart_enable_clk + drv_uart.o(i.drv_uart_init) refers to drv_uart.o(i.drv_uart_set_baud_rate) for drv_uart_set_baud_rate + drv_uart.o(i.drv_uart_init) refers to drv_uart.o(i.drv_uart_enable_int) for drv_uart_enable_int + drv_uart.o(i.drv_uart_int_trans_handle) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_recv_none_blocking) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_recv_none_blocking) refers to drv_uart.o(i.drv_uart_config_int) for drv_uart_config_int + drv_uart.o(i.drv_uart_recv_none_blocking) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_reset_rx_fifo) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_reset_tx_fifo) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_send_none_blocking) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_send_none_blocking) refers to drv_uart.o(i.drv_uart_config_int) for drv_uart_config_int + drv_uart.o(i.drv_uart_send_none_blocking) refers to drv_uart.o(.bss) for .bss + drv_uart.o(i.drv_uart_set_baud_rate) refers to uidiv.o(.text) for __aeabi_uidivmod + drv_uart.o(i.drv_uart_trans_create_handle) refers to drv_uart.o(i.drv_uart_get_instance) for drv_uart_get_instance + drv_uart.o(i.drv_uart_trans_create_handle) refers to memseta.o(.text) for __aeabi_memclr4 + drv_uart.o(i.drv_uart_trans_create_handle) refers to drv_uart.o(.bss) for .bss + drv_efuse.o(i.drv_efuse_enter_inactive) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + drv_efuse.o(i.drv_efuse_enter_inactive) refers to drv_efuse.o(i.drv_efuse_int_enable) for drv_efuse_int_enable + drv_efuse.o(i.drv_efuse_read) refers to drv_pwr.o(i.drv_pwr_efuse_pd) for drv_pwr_efuse_pd + drv_efuse.o(i.drv_efuse_read) refers to drv_efuse.o(i.drv_efuse_read_req) for drv_efuse_read_req + drv_efuse.o(i.drv_efuse_write) refers to drv_pwr.o(i.drv_pwr_efuse_pd) for drv_pwr_efuse_pd + drv_efuse.o(i.drv_efuse_write) refers to drv_efuse.o(i.drv_efuse_write_req) for drv_efuse_write_req + drv_efuse.o(i.drv_efuse_write_read_req_clear) refers to drv_efuse.o(i.drv_efuse_write_req) for drv_efuse_write_req + drv_efuse.o(i.drv_efuse_write_read_req_clear) refers to drv_efuse.o(i.drv_efuse_read_req) for drv_efuse_read_req + drv_per_common.o(i.drv_per_get_system_clk) refers to drv_crgu.o(i.drv_crgu_get_system_clk) for drv_crgu_get_system_clk + drv_per_common.o(i.drv_per_reset_module) refers to drv_crgu.o(i.drv_crgu_reset_modules) for drv_crgu_reset_modules + drv_per_common.o(i.drv_per_set_clock) refers to drv_crgu.o(i.drv_crgu_enable_clock) for drv_crgu_enable_clock + ceil.o(i.__softfp_ceil) refers (Special) to iusefp.o(.text) for __I$use$fp + ceil.o(i.__softfp_ceil) refers to ceil.o(i.ceil) for ceil + ceil.o(i.ceil) refers (Special) to iusefp.o(.text) for __I$use$fp + ceil.o(i.ceil) refers to dadd.o(.text) for __aeabi_dadd + ceil.o(i.ceil) refers to cdrcmple.o(.text) for __aeabi_cdrcmple + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk + idiv.o(.text) refers to uidiv.o(.text) for __aeabi_uidivmod + printfb.o(i.__0fprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0fprintf$bare) refers to tau_log.o(i.fputc) for fputc + printfb.o(i.__0printf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0printf$bare) refers to tau_log.o(i.fputc) for fputc + printfb.o(i.__0printf$bare) refers to stdout.o(.data) for __stdout + printfb.o(i.__0snprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0snprintf$bare) refers to printfb.o(i._snputc) for _snputc + printfb.o(i.__0sprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0sprintf$bare) refers to printfb.o(i._sputc) for _sputc + printfb.o(i.__0vfprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vfprintf$bare) refers to tau_log.o(i.fputc) for fputc + printfb.o(i.__0vprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vprintf$bare) refers to tau_log.o(i.fputc) for fputc + printfb.o(i.__0vprintf$bare) refers to stdout.o(.data) for __stdout + printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vsnprintf$bare) refers to printfb.o(i._snputc) for _snputc + printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._printf_core) for _printf_core + printfb.o(i.__0vsprintf$bare) refers to printfb.o(i._sputc) for _sputc + printf0.o(i.__0fprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0fprintf$0) refers to tau_log.o(i.fputc) for fputc + printf0.o(i.__0printf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0printf$0) refers to tau_log.o(i.fputc) for fputc + printf0.o(i.__0printf$0) refers to stdout.o(.data) for __stdout + printf0.o(i.__0snprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0snprintf$0) refers to printf0.o(i._snputc) for _snputc + printf0.o(i.__0sprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0sprintf$0) refers to printf0.o(i._sputc) for _sputc + printf0.o(i.__0vfprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vfprintf$0) refers to tau_log.o(i.fputc) for fputc + printf0.o(i.__0vprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vprintf$0) refers to tau_log.o(i.fputc) for fputc + printf0.o(i.__0vprintf$0) refers to stdout.o(.data) for __stdout + printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vsnprintf$0) refers to printf0.o(i._snputc) for _snputc + printf0.o(i.__0vsprintf$0) refers to printf0.o(i._printf_core) for _printf_core + printf0.o(i.__0vsprintf$0) refers to printf0.o(i._sputc) for _sputc + printf1.o(i.__0fprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0fprintf$1) refers to tau_log.o(i.fputc) for fputc + printf1.o(i.__0printf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0printf$1) refers to tau_log.o(i.fputc) for fputc + printf1.o(i.__0printf$1) refers to stdout.o(.data) for __stdout + printf1.o(i.__0snprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0snprintf$1) refers to printf1.o(i._snputc) for _snputc + printf1.o(i.__0sprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0sprintf$1) refers to printf1.o(i._sputc) for _sputc + printf1.o(i.__0vfprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vfprintf$1) refers to tau_log.o(i.fputc) for fputc + printf1.o(i.__0vprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vprintf$1) refers to tau_log.o(i.fputc) for fputc + printf1.o(i.__0vprintf$1) refers to stdout.o(.data) for __stdout + printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vsnprintf$1) refers to printf1.o(i._snputc) for _snputc + printf1.o(i.__0vsprintf$1) refers to printf1.o(i._printf_core) for _printf_core + printf1.o(i.__0vsprintf$1) refers to printf1.o(i._sputc) for _sputc + printf1.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf2.o(i.__0fprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0fprintf$2) refers to tau_log.o(i.fputc) for fputc + printf2.o(i.__0printf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0printf$2) refers to tau_log.o(i.fputc) for fputc + printf2.o(i.__0printf$2) refers to stdout.o(.data) for __stdout + printf2.o(i.__0snprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0snprintf$2) refers to printf2.o(i._snputc) for _snputc + printf2.o(i.__0sprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0sprintf$2) refers to printf2.o(i._sputc) for _sputc + printf2.o(i.__0vfprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vfprintf$2) refers to tau_log.o(i.fputc) for fputc + printf2.o(i.__0vprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vprintf$2) refers to tau_log.o(i.fputc) for fputc + printf2.o(i.__0vprintf$2) refers to stdout.o(.data) for __stdout + printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vsnprintf$2) refers to printf2.o(i._snputc) for _snputc + printf2.o(i.__0vsprintf$2) refers to printf2.o(i._printf_core) for _printf_core + printf2.o(i.__0vsprintf$2) refers to printf2.o(i._sputc) for _sputc + printf3.o(i.__0fprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0fprintf$3) refers to tau_log.o(i.fputc) for fputc + printf3.o(i.__0printf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0printf$3) refers to tau_log.o(i.fputc) for fputc + printf3.o(i.__0printf$3) refers to stdout.o(.data) for __stdout + printf3.o(i.__0snprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0snprintf$3) refers to printf3.o(i._snputc) for _snputc + printf3.o(i.__0sprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0sprintf$3) refers to printf3.o(i._sputc) for _sputc + printf3.o(i.__0vfprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vfprintf$3) refers to tau_log.o(i.fputc) for fputc + printf3.o(i.__0vprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vprintf$3) refers to tau_log.o(i.fputc) for fputc + printf3.o(i.__0vprintf$3) refers to stdout.o(.data) for __stdout + printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vsnprintf$3) refers to printf3.o(i._snputc) for _snputc + printf3.o(i.__0vsprintf$3) refers to printf3.o(i._printf_core) for _printf_core + printf3.o(i.__0vsprintf$3) refers to printf3.o(i._sputc) for _sputc + printf3.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf4.o(i.__0fprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0fprintf$4) refers to tau_log.o(i.fputc) for fputc + printf4.o(i.__0printf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0printf$4) refers to tau_log.o(i.fputc) for fputc + printf4.o(i.__0printf$4) refers to stdout.o(.data) for __stdout + printf4.o(i.__0snprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0snprintf$4) refers to printf4.o(i._snputc) for _snputc + printf4.o(i.__0sprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0sprintf$4) refers to printf4.o(i._sputc) for _sputc + printf4.o(i.__0vfprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vfprintf$4) refers to tau_log.o(i.fputc) for fputc + printf4.o(i.__0vprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vprintf$4) refers to tau_log.o(i.fputc) for fputc + printf4.o(i.__0vprintf$4) refers to stdout.o(.data) for __stdout + printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vsnprintf$4) refers to printf4.o(i._snputc) for _snputc + printf4.o(i.__0vsprintf$4) refers to printf4.o(i._printf_core) for _printf_core + printf4.o(i.__0vsprintf$4) refers to printf4.o(i._sputc) for _sputc + printf4.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf5.o(i.__0fprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0fprintf$5) refers to tau_log.o(i.fputc) for fputc + printf5.o(i.__0printf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0printf$5) refers to tau_log.o(i.fputc) for fputc + printf5.o(i.__0printf$5) refers to stdout.o(.data) for __stdout + printf5.o(i.__0snprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0snprintf$5) refers to printf5.o(i._snputc) for _snputc + printf5.o(i.__0sprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0sprintf$5) refers to printf5.o(i._sputc) for _sputc + printf5.o(i.__0vfprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vfprintf$5) refers to tau_log.o(i.fputc) for fputc + printf5.o(i.__0vprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vprintf$5) refers to tau_log.o(i.fputc) for fputc + printf5.o(i.__0vprintf$5) refers to stdout.o(.data) for __stdout + printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vsnprintf$5) refers to printf5.o(i._snputc) for _snputc + printf5.o(i.__0vsprintf$5) refers to printf5.o(i._printf_core) for _printf_core + printf5.o(i.__0vsprintf$5) refers to printf5.o(i._sputc) for _sputc + printf5.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf6.o(i.__0fprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0fprintf$6) refers to tau_log.o(i.fputc) for fputc + printf6.o(i.__0printf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0printf$6) refers to tau_log.o(i.fputc) for fputc + printf6.o(i.__0printf$6) refers to stdout.o(.data) for __stdout + printf6.o(i.__0snprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0snprintf$6) refers to printf6.o(i._snputc) for _snputc + printf6.o(i.__0sprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0sprintf$6) refers to printf6.o(i._sputc) for _sputc + printf6.o(i.__0vfprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vfprintf$6) refers to tau_log.o(i.fputc) for fputc + printf6.o(i.__0vprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vprintf$6) refers to tau_log.o(i.fputc) for fputc + printf6.o(i.__0vprintf$6) refers to stdout.o(.data) for __stdout + printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vsnprintf$6) refers to printf6.o(i._snputc) for _snputc + printf6.o(i.__0vsprintf$6) refers to printf6.o(i._printf_core) for _printf_core + printf6.o(i.__0vsprintf$6) refers to printf6.o(i._sputc) for _sputc + printf6.o(i._printf_core) refers to printf6.o(i._printf_pre_padding) for _printf_pre_padding + printf6.o(i._printf_core) refers to printf6.o(i._printf_post_padding) for _printf_post_padding + printf6.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printf7.o(i.__0fprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0fprintf$7) refers to tau_log.o(i.fputc) for fputc + printf7.o(i.__0printf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0printf$7) refers to tau_log.o(i.fputc) for fputc + printf7.o(i.__0printf$7) refers to stdout.o(.data) for __stdout + printf7.o(i.__0snprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0snprintf$7) refers to printf7.o(i._snputc) for _snputc + printf7.o(i.__0sprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0sprintf$7) refers to printf7.o(i._sputc) for _sputc + printf7.o(i.__0vfprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vfprintf$7) refers to tau_log.o(i.fputc) for fputc + printf7.o(i.__0vprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vprintf$7) refers to tau_log.o(i.fputc) for fputc + printf7.o(i.__0vprintf$7) refers to stdout.o(.data) for __stdout + printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vsnprintf$7) refers to printf7.o(i._snputc) for _snputc + printf7.o(i.__0vsprintf$7) refers to printf7.o(i._printf_core) for _printf_core + printf7.o(i.__0vsprintf$7) refers to printf7.o(i._sputc) for _sputc + printf7.o(i._printf_core) refers to printf7.o(i._printf_pre_padding) for _printf_pre_padding + printf7.o(i._printf_core) refers to printf7.o(i._printf_post_padding) for _printf_post_padding + printf7.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printf8.o(i.__0fprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0fprintf$8) refers to tau_log.o(i.fputc) for fputc + printf8.o(i.__0printf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0printf$8) refers to tau_log.o(i.fputc) for fputc + printf8.o(i.__0printf$8) refers to stdout.o(.data) for __stdout + printf8.o(i.__0snprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0snprintf$8) refers to printf8.o(i._snputc) for _snputc + printf8.o(i.__0sprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0sprintf$8) refers to printf8.o(i._sputc) for _sputc + printf8.o(i.__0vfprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vfprintf$8) refers to tau_log.o(i.fputc) for fputc + printf8.o(i.__0vprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vprintf$8) refers to tau_log.o(i.fputc) for fputc + printf8.o(i.__0vprintf$8) refers to stdout.o(.data) for __stdout + printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vsnprintf$8) refers to printf8.o(i._snputc) for _snputc + printf8.o(i.__0vsprintf$8) refers to printf8.o(i._printf_core) for _printf_core + printf8.o(i.__0vsprintf$8) refers to printf8.o(i._sputc) for _sputc + printf8.o(i._printf_core) refers to printf8.o(i._printf_pre_padding) for _printf_pre_padding + printf8.o(i._printf_core) refers to printf8.o(i._printf_post_padding) for _printf_post_padding + printf8.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i.__0fprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0fprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0fprintf) refers to tau_log.o(i.fputc) for fputc + printfa.o(i.__0printf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0printf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0printf) refers to tau_log.o(i.fputc) for fputc + printfa.o(i.__0printf) refers to stdout.o(.data) for __stdout + printfa.o(i.__0snprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0snprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0snprintf) refers to printfa.o(i._snputc) for _snputc + printfa.o(i.__0sprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0sprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0sprintf) refers to printfa.o(i._sputc) for _sputc + printfa.o(i.__0vfprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vfprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vfprintf) refers to tau_log.o(i.fputc) for fputc + printfa.o(i.__0vprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vprintf) refers to tau_log.o(i.fputc) for fputc + printfa.o(i.__0vprintf) refers to stdout.o(.data) for __stdout + printfa.o(i.__0vsnprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vsnprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vsnprintf) refers to printfa.o(i._snputc) for _snputc + printfa.o(i.__0vsprintf) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i.__0vsprintf) refers to printfa.o(i._printf_core) for _printf_core + printfa.o(i.__0vsprintf) refers to printfa.o(i._sputc) for _sputc + printfa.o(i._fp_digits) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._fp_digits) refers to dmul.o(.text) for __aeabi_dmul + printfa.o(i._fp_digits) refers to ddiv.o(.text) for __aeabi_ddiv + printfa.o(i._fp_digits) refers to cdrcmple.o(.text) for __aeabi_cdrcmple + printfa.o(i._fp_digits) refers to dadd.o(.text) for __aeabi_dadd + printfa.o(i._fp_digits) refers to dfixul.o(.text) for __aeabi_d2ulz + printfa.o(i._fp_digits) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i._printf_core) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._printf_core) refers to printfa.o(i._printf_pre_padding) for _printf_pre_padding + printfa.o(i._printf_core) refers to uldiv.o(.text) for __aeabi_uldivmod + printfa.o(i._printf_core) refers to printfa.o(i._printf_post_padding) for _printf_post_padding + printfa.o(i._printf_core) refers to printfa.o(i._fp_digits) for _fp_digits + printfa.o(i._printf_core) refers to uidiv.o(.text) for __aeabi_uidivmod + printfa.o(i._printf_post_padding) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._printf_pre_padding) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._snputc) refers (Special) to iusefp.o(.text) for __I$use$fp + printfa.o(i._sputc) refers (Special) to iusefp.o(.text) for __I$use$fp + fadd.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + fadd.o(.text) refers to fepilogue.o(.text) for _float_epilogue + fmul.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + fdiv.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + fdiv.o(.text) refers to fepilogue.o(.text) for _float_round + fscalb.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dadd.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dadd.o(.text) refers to llshl.o(.text) for __aeabi_llsl + dadd.o(.text) refers to llsshr.o(.text) for __aeabi_lasr + dadd.o(.text) refers to depilogue.o(.text) for _double_epilogue + dmul.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dmul.o(.text) refers to depilogue.o(.text) for _double_epilogue + fflti.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + fflti.o(.text) refers to fepilogue.o(.text) for _float_epilogue + ffltui.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + ffltui.o(.text) refers to fepilogue.o(.text) for _float_epilogue + dfltui.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dfltui.o(.text) refers to depilogue.o(.text) for _double_epilogue + ffixui.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dfixui.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + dfixui.o(.text) refers to llushr.o(.text) for __aeabi_llsr + f2d.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + d2f.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + d2f.o(.text) refers to fepilogue.o(.text) for _float_round + cfcmple.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + cfrcmple.o(.text) refers (Special) to iusefp.o(.text) for __I$use$fp + entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000 + entry2.o(.ARM.Collect$$$$00002712) refers to startup_armcm0.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to startup_armcm0.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main + entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload + entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main + entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main + uldiv.o(.text) refers to llushr.o(.text) for __aeabi_llsr + uldiv.o(.text) refers to llshl.o(.text) for __aeabi_llsl + depilogue.o(.text) refers to depilogue.o(i.__ARM_clz) for __ARM_clz + depilogue.o(.text) refers to llshl.o(.text) for __aeabi_llsl + depilogue.o(.text) refers to llushr.o(.text) for __aeabi_llsr + ddiv.o(.text) refers to depilogue.o(.text) for _double_round + dfixul.o(.text) refers to llushr.o(.text) for __aeabi_llsr + dfixul.o(.text) refers to llshl.o(.text) for __aeabi_llsl + init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload + + +============================================================================== + +Removing Unused input sections from the image. + + Removing main.o(.rev16_text), (4 bytes). + Removing main.o(.revsh_text), (4 bytes). + Removing p8p_demo.o(.rev16_text), (4 bytes). + Removing p8p_demo.o(.revsh_text), (4 bytes). + Removing p8p_demo.o(i.Gpio_swire_output), (80 bytes). + Removing p8p_demo.o(i.Panel_CCM), (42 bytes). + Removing p8p_demo.o(i.REG_51_OFF_output), (60 bytes). + Removing p8p_demo.o(i.ap_dcs_set_exit_idle_mode), (104 bytes). + Removing p8p_demo.o(i.soft_te_timer_cb), (28 bytes). + Removing p8p_demo.o(i.soft_te_timer_init), (40 bytes). + Removing board.o(.rev16_text), (4 bytes). + Removing board.o(.revsh_text), (4 bytes). + Removing startup_armcm0.o(HEAP), (3072 bytes). + Removing hal_dsi_rx_ctrl.o(.rev16_text), (4 bytes). + Removing hal_dsi_rx_ctrl.o(.revsh_text), (4 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_ack_long_cmd), (220 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_ack_short_cmd), (28 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_line), (604 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_draw_mode_init), (320 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_enable_test_pattern), (256 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_force_video_crtl), (12 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_cap_pixel_color), (10 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_compressen_en), (8 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_callback), (66 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_register_write_cmd_entry), (10 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_release_handle), (40 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart), (68 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_ack), (176 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_auto_hw_filter), (28 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cap_pixel_pos), (10 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_check_crc), (24 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk), (32 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_hw_cmd_filter), (44 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_log_level), (8 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data), (240 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_pixel_data_ex), (392 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rx_clk), (72 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rxbr_clk), (56 bytes). + Removing hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_input_frame_rate), (10 bytes). + Removing hal_dsi_rx_ctrl.o(i.swap_uint16_t), (10 bytes). + Removing hal_dsi_tx_ctrl.o(.rev16_text), (4 bytes). + Removing hal_dsi_tx_ctrl.o(.revsh_text), (4 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_cmd_mode), (120 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_draw_flick), (244 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_frame), (12 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_get_disp_line), (12 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_overwrite_enable), (22 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_partial_disp_enable), (70 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_read_cmd), (128 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_release_handle), (32 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_bcs), (60 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_ccm), (8 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_cus_sync_line), (36 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_dect), (60 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_edge_enhance), (60 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_endianness), (12 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_escape_clock_div), (52 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_fc), (60 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_vpg), (28 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_vporch_bta_opera), (68 bytes). + Removing hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_req_update), (16 bytes). + Removing hal_gpio.o(.rev16_text), (4 bytes). + Removing hal_gpio.o(.revsh_text), (4 bytes). + Removing hal_gpio.o(i.hal_gpio_get_input_data), (18 bytes). + Removing hal_gpio.o(i.hal_gpio_get_int_type), (20 bytes). + Removing hal_gpio.o(i.hal_gpio_get_pull_state), (40 bytes). + Removing hal_gpio.o(i.hal_gpio_set_driving_strength), (44 bytes). + Removing hal_gpio.o(i.hal_gpio_set_high_impedance), (32 bytes). + Removing hal_gpio.o(i.hal_gpio_set_pull_state), (72 bytes). + Removing hal_gpio.o(i.hal_gpio_set_schmitt_trigger), (52 bytes). + Removing hal_gpio.o(i.hal_gpio_set_slew_rate), (52 bytes). + Removing hal_swire.o(.rev16_text), (4 bytes). + Removing hal_swire.o(.revsh_text), (4 bytes). + Removing hal_swire.o(i.hal_swire_register_callback), (22 bytes). + Removing hal_swire.o(i.hal_swire_set_waveform), (92 bytes). + Removing hal_system.o(.rev16_text), (4 bytes). + Removing hal_system.o(.revsh_text), (4 bytes). + Removing hal_system.o(i.hal_system_clear_debug_state), (10 bytes). + Removing hal_system.o(i.hal_system_disable_systick), (8 bytes). + Removing hal_system.o(i.hal_system_enable_systick), (8 bytes). + Removing hal_system.o(i.hal_system_get_debug_state), (8 bytes). + Removing hal_system.o(i.hal_system_get_tick), (8 bytes). + Removing hal_system.o(i.hal_system_idle_mode), (8 bytes). + Removing hal_system.o(i.hal_system_register_systick_cb), (8 bytes). + Removing hal_system.o(i.hal_system_reset_chip), (10 bytes). + Removing hal_timer.o(.rev16_text), (4 bytes). + Removing hal_timer.o(.revsh_text), (4 bytes). + Removing hal_timer.o(i.hal_timer_get_status), (8 bytes). + Removing hal_timer.o(i.hal_timer_start), (48 bytes). + Removing hal_timer.o(i.hal_timer_start_ex), (42 bytes). + Removing hal_timer.o(i.hal_timer_stop), (40 bytes). + Removing hal_pwr.o(.rev16_text), (4 bytes). + Removing hal_pwr.o(.revsh_text), (4 bytes). + Removing hal_pwr.o(i.hal_pwr_elvcc_close), (10 bytes). + Removing hal_pwr.o(i.hal_pwr_elvcc_ldo_en), (46 bytes). + Removing hal_pwr.o(i.hal_pwr_elvcc_vol_set), (8 bytes). + Removing hal_pwr.o(i.hal_pwr_get_reset_flag), (66 bytes). + Removing hal_pwr.o(i.hal_pwr_ldo13s_en), (8 bytes). + Removing hal_pwr.o(i.hal_pwr_ldo13s_set), (8 bytes). + Removing hal_pwr.o(i.hal_pwr_ldo18s_en), (8 bytes). + Removing hal_pwr.o(i.hal_pwr_ldo18s_set), (8 bytes). + Removing hal_pwr.o(i.hal_pwr_set_pvd), (8 bytes). + Removing hal_pwr.o(i.hal_pwr_set_vcc_enable), (8 bytes). + Removing hal_pwr.o(i.hal_pwr_sw_tp18_en), (8 bytes). + Removing tau_delay.o(.rev16_text), (4 bytes). + Removing tau_delay.o(.revsh_text), (4 bytes). + Removing tau_log.o(.rev16_text), (4 bytes). + Removing tau_log.o(.revsh_text), (4 bytes). + Removing tau_log.o(i.fgetc), (72 bytes). + Removing hal_uart.o(.rev16_text), (4 bytes). + Removing hal_uart.o(.revsh_text), (4 bytes). + Removing hal_uart.o(i.hal_uart0_rx_dma_cb), (20 bytes). + Removing hal_uart.o(i.hal_uart0_tx_dma_cb), (36 bytes). + Removing hal_uart.o(i.hal_uart1_rx_dma_cb), (20 bytes). + Removing hal_uart.o(i.hal_uart1_tx_dma_cb), (36 bytes). + Removing hal_uart.o(i.hal_uart_deinit), (48 bytes). + Removing hal_uart.o(i.hal_uart_dma_path_close), (92 bytes). + Removing hal_uart.o(i.hal_uart_dma_recv), (276 bytes). + Removing hal_uart.o(i.hal_uart_dma_send), (280 bytes). + Removing hal_uart.o(i.hal_uart_recv_blocking), (28 bytes). + Removing hal_uart.o(i.hal_uart_recv_none_blocking), (28 bytes). + Removing hal_uart.o(i.hal_uart_send_none_blocking), (28 bytes). + Removing hal_internal_vsync.o(.rev16_text), (4 bytes). + Removing hal_internal_vsync.o(.revsh_text), (4 bytes). + Removing hal_internal_vsync.o(i.hal_internal_sync_cmd_mode_rcv_te), (2 bytes). + Removing hal_internal_vsync.o(i.hal_internal_sync_register_rx_callback), (28 bytes). + Removing hal_internal_vsync.o(i.hal_internal_sync_set_fb_setting_manual), (28 bytes). + Removing hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line), (60 bytes). + Removing hal_internal_vsync.o(i.hal_internal_vsync_toggle_input_frame_rate), (134 bytes). + Removing hal_internal_vsync.o(.data), (4 bytes). + Removing hal_internal_dcs.o(.rev16_text), (4 bytes). + Removing hal_internal_dcs.o(.revsh_text), (4 bytes). + Removing hal_internal_dcs.o(i.hal_intl_dcs_register_write_cmd_entry), (12 bytes). + Removing hal_internal_dcs.o(i.hal_intl_dcs_set_dcs_direct_mode), (44 bytes). + Removing hal_internal_fb.o(.rev16_text), (4 bytes). + Removing hal_internal_fb.o(.revsh_text), (4 bytes). + Removing hal_internal_fb.o(i.hal_intl_fb_set_fb_info_manual), (480 bytes). + Removing hal_internal_fb.o(.conststring), (152 bytes). + Removing hal_internal_svs.o(.rev16_text), (4 bytes). + Removing hal_internal_svs.o(.revsh_text), (4 bytes). + Removing hal_internal_svs.o(i.hal_intl_svs_set_input_frate), (112 bytes). + Removing hal_internal_svs.o(i.hal_intl_svs_set_sync_coef), (12 bytes). + Removing drv_common.o(.rev16_text), (4 bytes). + Removing drv_common.o(.revsh_text), (4 bytes). + Removing drv_common.o(i.drv_common_disable_systick), (20 bytes). + Removing drv_common.o(i.drv_common_enable_systick), (88 bytes). + Removing drv_common.o(i.drv_common_get_tick), (12 bytes). + Removing drv_common.o(i.drv_common_idle_mode), (40 bytes). + Removing drv_common.o(i.drv_common_systick_register_cb), (12 bytes). + Removing drv_crgu.o(.rev16_text), (4 bytes). + Removing drv_crgu.o(.revsh_text), (4 bytes). + Removing drv_crgu.o(i.drv_crgu_clear_all_reset_flags), (12 bytes). + Removing drv_crgu.o(i.drv_crgu_clear_reset_flag), (20 bytes). + Removing drv_crgu.o(i.drv_crgu_get_all_reset_flag), (12 bytes). + Removing drv_crgu.o(i.drv_crgu_get_reset_flag), (24 bytes). + Removing drv_crgu.o(i.drv_crgu_get_system_clk), (104 bytes). + Removing drv_crgu.o(i.drv_crgu_reset_chip), (24 bytes). + Removing drv_crgu.o(i.drv_crgu_set_clock_src), (16 bytes). + Removing drv_dsc_dec.o(.rev16_text), (4 bytes). + Removing drv_dsc_dec.o(.revsh_text), (4 bytes). + Removing drv_gpio.o(.rev16_text), (4 bytes). + Removing drv_gpio.o(.revsh_text), (4 bytes). + Removing drv_gpio.o(i.drv_gpio_get_attribute), (16 bytes). + Removing drv_gpio.o(i.drv_gpio_get_input_data), (24 bytes). + Removing drv_gpio.o(i.drv_gpio_set_attribute), (28 bytes). + Removing drv_pwr.o(.rev16_text), (4 bytes). + Removing drv_pwr.o(.revsh_text), (4 bytes). + Removing drv_pwr.o(i.drv_pwr_10bit_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_analog_pwm_en), (44 bytes). + Removing drv_pwr.o(i.drv_pwr_charge_pump_en), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_close_iov18_tp18), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_dsc_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_elvcc_pwm_en), (124 bytes). + Removing drv_pwr.o(i.drv_pwr_enter_sleep_mode), (152 bytes). + Removing drv_pwr.o(i.drv_pwr_exit_sleep_mode_ex), (40 bytes). + Removing drv_pwr.o(i.drv_pwr_fb_pd), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_get_wakeflag), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_get_write_lock_st), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_hf_frm_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_hv_ldo_10M_clock), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_hv_ldo_mode_clock_sel), (60 bytes). + Removing drv_pwr.o(i.drv_pwr_hv_ldo_mode_sel), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_hv_ldo_voltage_set), (44 bytes). + Removing drv_pwr.o(i.drv_pwr_ldo11d_trim), (36 bytes). + Removing drv_pwr.o(i.drv_pwr_ldo13s_en), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_ldo13s_set), (44 bytes). + Removing drv_pwr.o(i.drv_pwr_ldo15_trim), (36 bytes). + Removing drv_pwr.o(i.drv_pwr_ldo18s_en), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_ldo18s_set), (44 bytes). + Removing drv_pwr.o(i.drv_pwr_ltpo_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_osc32k_trim), (36 bytes). + Removing drv_pwr.o(i.drv_pwr_osc80m_trim), (36 bytes). + Removing drv_pwr.o(i.drv_pwr_p3k_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_por_mode_flag), (32 bytes). + Removing drv_pwr.o(i.drv_pwr_power_in), (44 bytes). + Removing drv_pwr.o(i.drv_pwr_power_ready_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_power_sel), (44 bytes). + Removing drv_pwr.o(i.drv_pwr_pwm_output_pwm_led), (56 bytes). + Removing drv_pwr.o(i.drv_pwr_pwmled_driver_current_Big_step), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_pwmled_driver_current_small_step), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_pwmled_electric_current), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_pwmled_open_drain), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_ram_pd_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_read_boot_chipst), (12 bytes). + Removing drv_pwr.o(i.drv_pwr_read_chipcfg), (12 bytes). + Removing drv_pwr.o(i.drv_pwr_rgbr_state_get), (16 bytes). + Removing drv_pwr.o(i.drv_pwr_set_ap_rst_mode), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_set_ldo11_mode), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_set_ldo15_mode), (48 bytes). + Removing drv_pwr.o(i.drv_pwr_set_pvd), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_set_pvd_mode), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_set_system_clk), (32 bytes). + Removing drv_pwr.o(i.drv_pwr_sw_tp18_en), (52 bytes). + Removing drv_pwr.o(i.drv_pwr_wakeflag_get), (16 bytes). + Removing drv_swire.o(.rev16_text), (4 bytes). + Removing drv_swire.o(.revsh_text), (4 bytes). + Removing drv_sys_cfg.o(.rev16_text), (4 bytes). + Removing drv_sys_cfg.o(.revsh_text), (4 bytes). + Removing drv_sys_cfg.o(i.drv_sys_cfg_sel_dma_req), (128 bytes). + Removing drv_timer.o(.rev16_text), (4 bytes). + Removing drv_timer.o(.revsh_text), (4 bytes). + Removing drv_timer.o(i.drv_timer_get_status), (38 bytes). + Removing drv_timer.o(i.drv_timer_register_callback), (20 bytes). + Removing dcs_packet_fifo.o(.rev16_text), (4 bytes). + Removing dcs_packet_fifo.o(.revsh_text), (4 bytes). + Removing dcs_packet_fifo.o(i.dcs_packet_get_fifo_size), (16 bytes). + Removing drv_se.o(.rev16_text), (4 bytes). + Removing drv_se.o(.revsh_text), (4 bytes). + Removing drv_dsi_rx.o(.rev16_text), (4 bytes). + Removing drv_dsi_rx.o(.revsh_text), (4 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_force_video_crtl), (28 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_get_lpdt_fifo_status), (16 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_get_phy_stopstate), (68 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_get_version), (12 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_pg_cfg), (24 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_set_drv_log_level), (12 bytes). + Removing drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_pg_cfg), (48 bytes). + Removing drv_dsi_tx.o(.rev16_text), (4 bytes). + Removing drv_dsi_tx.o(.revsh_text), (4 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_command_get_payload), (12 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_force_interrupt), (12 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_get_phy_status), (12 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_forcepll), (16 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_start), (24 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_status_pll_lock), (16 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ulpsactivenot), (68 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_trigger), (92 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_enter), (296 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_phy_ulps_exit), (228 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_sdf_3d), (32 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_set_bta), (28 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_set_vpg), (100 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_version), (12 bytes). + Removing drv_dsi_tx.o(i.drv_dsi_tx_vid_shadow), (20 bytes). + Removing drv_dsi_tx.o(i.drv_tx_phy_test_clear), (16 bytes). + Removing drv_dsi_tx.o(i.drv_tx_phy_test_lock), (32 bytes). + Removing drv_dsi_tx.o(i.drv_tx_phy_test_read), (16 bytes). + Removing drv_lcdc.o(.rev16_text), (4 bytes). + Removing drv_lcdc.o(.revsh_text), (4 bytes). + Removing drv_lcdc.o(i.drv_lcdc_clear_irq), (16 bytes). + Removing drv_lcdc.o(i.drv_lcdc_dpisignal_output_ctrl), (44 bytes). + Removing drv_lcdc.o(i.drv_lcdc_fixed_frame_output), (56 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_dpbuf_num), (12 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_dpi_status), (16 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_frame_clk_count), (16 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_int_en_status), (12 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_int_status), (12 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_line_status), (12 bytes). + Removing drv_lcdc.o(i.drv_lcdc_get_rgb2pen_subpixel), (16 bytes). + Removing drv_lcdc.o(i.drv_lcdc_part_display_config), (52 bytes). + Removing drv_lcdc.o(i.drv_lcdc_pixel_value_config), (32 bytes). + Removing drv_lcdc.o(i.drv_lcdc_rd_st_line_config), (28 bytes). + Removing drv_lcdc.o(i.drv_lcdc_software_reset), (16 bytes). + Removing drv_lcdc.o(i.drv_lcdc_update_shadow_reg), (16 bytes). + Removing drv_lcdc.o(i.drv_lcdc_vid_sw_start), (56 bytes). + Removing drv_memc.o(.rev16_text), (4 bytes). + Removing drv_memc.o(.revsh_text), (4 bytes). + Removing drv_memc.o(i.drv_memc_set_db_frm_time), (20 bytes). + Removing drv_memc.o(i.drv_memc_set_db_int_frame), (36 bytes). + Removing drv_memc.o(i.drv_memc_set_double_buffer_reverse), (24 bytes). + Removing drv_memc.o(i.drv_memc_set_fb_pri), (44 bytes). + Removing drv_memc.o(i.drv_memc_set_fb_remaining_line_trigger), (20 bytes). + Removing drv_memc.o(i.drv_memc_set_inten), (28 bytes). + Removing drv_memc.o(i.drv_memc_set_read_trigger_line), (24 bytes). + Removing drv_memc.o(i.drv_memc_set_te_ind), (20 bytes). + Removing drv_memc.o(i.drv_memc_set_tear_hwclr), (24 bytes). + Removing drv_memc.o(i.drv_memc_set_vidc_fb_arb), (20 bytes). + Removing drv_memc.o(i.drv_memc_set_write_trigger_line), (24 bytes). + Removing drv_rxbr.o(.rev16_text), (4 bytes). + Removing drv_rxbr.o(.revsh_text), (4 bytes). + Removing drv_rxbr.o(i.drv_rxbr_clr_swp_cnt), (16 bytes). + Removing drv_rxbr.o(i.drv_rxbr_dsc_flush), (24 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_col_addr), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_cur_hline_rcv_cnt), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_frame_data_interval), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_hline_dcat), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_ipi_vsync_interval), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_page_addr), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_pix_fmt), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_get_swpxl_cnt), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_hline_rcv0_cfg), (20 bytes). + Removing drv_rxbr.o(i.drv_rxbr_register_irq0_callback), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_ack_pkt_md), (28 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_cmd_filter), (320 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_cmd_response), (324 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_col_addr), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_compress), (32 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_data_catch_hline), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_page_addr), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_swpxl_data), (12 bytes). + Removing drv_rxbr.o(i.drv_rxbr_set_tmpdith_bp), (28 bytes). + Removing drv_rxbr.o(i.drv_rxbr_soft_reset), (32 bytes). + Removing drv_rxbr.o(i.drv_rxbr_sw_reset), (164 bytes). + Removing drv_rxbr.o(i.drv_rxbr_swpxl_clr), (32 bytes). + Removing drv_vidc.o(.rev16_text), (4 bytes). + Removing drv_vidc.o(.revsh_text), (4 bytes). + Removing drv_vidc.o(i.drv_vidc_clear_status0), (20 bytes). + Removing drv_vidc.o(i.drv_vidc_debug_cap_pixel), (28 bytes). + Removing drv_vidc.o(i.drv_vidc_debug_signal_frame), (36 bytes). + Removing drv_vidc.o(i.drv_vidc_get_status0), (24 bytes). + Removing drv_vidc.o(i.drv_vidc_get_status1), (24 bytes). + Removing drv_vidc.o(i.drv_vidc_get_status2), (12 bytes). + Removing drv_vidc.o(i.drv_vidc_set_dsc_thresh), (12 bytes). + Removing drv_vidc.o(i.drv_vidc_set_frmst_latency), (20 bytes). + Removing drv_vidc.o(i.drv_vidc_set_inff_thresh), (12 bytes). + Removing drv_vidc.o(i.drv_vidc_set_irq_line), (24 bytes). + Removing drv_vidc.o(i.drv_vidc_set_module_enable), (28 bytes). + Removing drv_vidc.o(i.drv_vidc_set_outff_thresh), (12 bytes). + Removing drv_vidc.o(i.drv_vidc_update_src_format), (20 bytes). + Removing drv_dma.o(.rev16_text), (4 bytes). + Removing drv_dma.o(.revsh_text), (4 bytes). + Removing drv_dma.o(i.drv_dma_apply_handle), (304 bytes). + Removing drv_dma.o(i.drv_dma_deinit), (52 bytes). + Removing drv_dma.o(i.drv_dma_disable), (20 bytes). + Removing drv_dma.o(i.drv_dma_disable_int), (40 bytes). + Removing drv_dma.o(i.drv_dma_enable), (36 bytes). + Removing drv_dma.o(i.drv_dma_enable_int), (68 bytes). + Removing drv_dma.o(i.drv_dma_get_remaining_trans_num), (20 bytes). + Removing drv_dma.o(i.drv_dma_get_status), (20 bytes). + Removing drv_dma.o(i.drv_dma_init), (22 bytes). + Removing drv_dma.o(i.drv_dma_int_list_delete), (88 bytes). + Removing drv_dma.o(i.drv_dma_int_list_inset), (48 bytes). + Removing drv_dma.o(i.drv_dma_register_callback), (4 bytes). + Removing drv_dma.o(i.drv_dma_reset), (36 bytes). + Removing drv_dma.o(i.drv_dma_set_bitwide), (56 bytes). + Removing drv_dma.o(i.drv_dma_set_burst), (20 bytes). + Removing drv_dma.o(i.drv_dma_set_circle_mode), (40 bytes). + Removing drv_dma.o(i.drv_dma_set_dir), (40 bytes). + Removing drv_dma.o(i.drv_dma_set_increment), (72 bytes). + Removing drv_dma.o(i.drv_dma_set_mem_trans_info), (40 bytes). + Removing drv_dma.o(i.drv_dma_set_mem_trans_offset), (24 bytes). + Removing drv_dma.o(i.drv_dma_set_per_address), (20 bytes). + Removing drv_dma.o(i.drv_dma_set_priority), (32 bytes). + Removing drv_dma.o(i.drv_dma_set_tran_int_cnt), (28 bytes). + Removing drv_dma.o(i.drv_dma_update_handle_setting), (148 bytes). + Removing drv_dma.o(i.drv_dma_update_req_by_default), (40 bytes). + Removing drv_dma.o(.constdata), (136 bytes). + Removing drv_uart.o(.rev16_text), (4 bytes). + Removing drv_uart.o(.revsh_text), (4 bytes). + Removing drv_uart.o(i.drv_uart_deinit), (60 bytes). + Removing drv_uart.o(i.drv_uart_get_def_cfg), (72 bytes). + Removing drv_uart.o(i.drv_uart_recv_blocking), (48 bytes). + Removing drv_uart.o(i.drv_uart_recv_none_blocking), (60 bytes). + Removing drv_uart.o(i.drv_uart_send_none_blocking), (60 bytes). + Removing drv_efuse.o(.rev16_text), (4 bytes). + Removing drv_efuse.o(.revsh_text), (4 bytes). + Removing drv_efuse.o(i.drv_efuse_crc_cal), (128 bytes). + Removing drv_efuse.o(i.drv_efuse_get_default_config), (26 bytes). + Removing drv_efuse.o(i.drv_efuse_int_disable), (12 bytes). + Removing drv_efuse.o(i.drv_efuse_write), (56 bytes). + Removing drv_efuse.o(i.drv_efuse_write_read_req_clear), (22 bytes). + Removing drv_efuse.o(i.drv_efuse_write_req), (22 bytes). + Removing drv_phy_common.o(.rev16_text), (4 bytes). + Removing drv_phy_common.o(.revsh_text), (4 bytes). + Removing drv_per_common.o(.rev16_text), (4 bytes). + Removing drv_per_common.o(.revsh_text), (4 bytes). + Removing drv_per_common.o(i.drv_per_get_system_clk), (8 bytes). + Removing drv_per_common.o(i.drv_per_reset_module), (14 bytes). + Removing drv_per_common.o(i.drv_per_set_clock), (14 bytes). + Removing fflti.o(.text), (22 bytes). + +380 unused section(s) (total 18518 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/../cmprslib/zerorunl2.c 0x00000000 Number 0 __dczerorl2.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 idiv.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 uidiv.o ABSOLUTE + ../clib/microlib/division.c 0x00000000 Number 0 uldiv.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llshl.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llushr.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llsshr.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printfb.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printfa.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf2.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf8.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf7.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf6.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf0.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf5.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf4.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf3.o ABSOLUTE + ../clib/microlib/printf/printf.c 0x00000000 Number 0 printf1.o ABSOLUTE + ../clib/microlib/printf/stubs.s 0x00000000 Number 0 stubs.o ABSOLUTE + ../clib/microlib/stdio/streams.c 0x00000000 Number 0 stdout.o ABSOLUTE + ../clib/microlib/string/memcmp.c 0x00000000 Number 0 memcmp.o ABSOLUTE + ../clib/microlib/string/memcpy.c 0x00000000 Number 0 memcpyb.o ABSOLUTE + ../clib/microlib/string/memcpy.c 0x00000000 Number 0 memcpya.o ABSOLUTE + ../clib/microlib/string/memset.c 0x00000000 Number 0 memseta.o ABSOLUTE + ../clib/microlib/string/strlen.c 0x00000000 Number 0 strlen.o ABSOLUTE + ../clib/microlib/stubs.s 0x00000000 Number 0 iusefp.o ABSOLUTE + ../fplib/microlib/d2f.c 0x00000000 Number 0 d2f.o ABSOLUTE + ../fplib/microlib/f2d.c 0x00000000 Number 0 f2d.o ABSOLUTE + ../fplib/microlib/fpadd.c 0x00000000 Number 0 fadd.o ABSOLUTE + ../fplib/microlib/fpadd.c 0x00000000 Number 0 dadd.o ABSOLUTE + ../fplib/microlib/fpdiv.c 0x00000000 Number 0 fdiv.o ABSOLUTE + ../fplib/microlib/fpdiv.c 0x00000000 Number 0 ddiv.o ABSOLUTE + ../fplib/microlib/fpepilogue.c 0x00000000 Number 0 depilogue.o ABSOLUTE + ../fplib/microlib/fpepilogue.c 0x00000000 Number 0 fepilogue.o ABSOLUTE + ../fplib/microlib/fpfix.c 0x00000000 Number 0 dfixui.o ABSOLUTE + ../fplib/microlib/fpfix.c 0x00000000 Number 0 ffixui.o ABSOLUTE + ../fplib/microlib/fpfix.c 0x00000000 Number 0 dfixul.o ABSOLUTE + ../fplib/microlib/fpflt.c 0x00000000 Number 0 dfltui.o ABSOLUTE + ../fplib/microlib/fpflt.c 0x00000000 Number 0 ffltui.o ABSOLUTE + ../fplib/microlib/fpflt.c 0x00000000 Number 0 fflti.o ABSOLUTE + ../fplib/microlib/fpmul.c 0x00000000 Number 0 dmul.o ABSOLUTE + ../fplib/microlib/fpmul.c 0x00000000 Number 0 fmul.o ABSOLUTE + ../fplib/microlib/fpscalb.c 0x00000000 Number 0 fscalb.o ABSOLUTE + ../mathlib/ceil.c 0x00000000 Number 0 ceil.o ABSOLUTE + ..\..\..\src\common\tau_delay.c 0x00000000 Number 0 tau_delay.o ABSOLUTE + ..\..\..\src\common\tau_log.c 0x00000000 Number 0 tau_log.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_common.c 0x00000000 Number 0 drv_common.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_crgu.c 0x00000000 Number 0 drv_crgu.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_dma.c 0x00000000 Number 0 drv_dma.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_dsc_dec.c 0x00000000 Number 0 drv_dsc_dec.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_dsi_rx.c 0x00000000 Number 0 drv_dsi_rx.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_dsi_tx.c 0x00000000 Number 0 drv_dsi_tx.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_efuse.c 0x00000000 Number 0 drv_efuse.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_gpio.c 0x00000000 Number 0 drv_gpio.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_lcdc.c 0x00000000 Number 0 drv_lcdc.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_memc.c 0x00000000 Number 0 drv_memc.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_per_common.c 0x00000000 Number 0 drv_per_common.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_phy_common.c 0x00000000 Number 0 drv_phy_common.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_pwr.c 0x00000000 Number 0 drv_pwr.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_rxbr.c 0x00000000 Number 0 drv_rxbr.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_swire.c 0x00000000 Number 0 drv_swire.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_sys_cfg.c 0x00000000 Number 0 drv_sys_cfg.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_timer.c 0x00000000 Number 0 drv_timer.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_uart.c 0x00000000 Number 0 drv_uart.o ABSOLUTE + ..\..\..\src\driver\cuckoo\drv\drv_vidc.c 0x00000000 Number 0 drv_vidc.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_dsi_rx_ctrl.c 0x00000000 Number 0 hal_dsi_rx_ctrl.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_dsi_tx_ctrl.c 0x00000000 Number 0 hal_dsi_tx_ctrl.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_gpio.c 0x00000000 Number 0 hal_gpio.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_pwr.c 0x00000000 Number 0 hal_pwr.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_swire.c 0x00000000 Number 0 hal_swire.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_system.c 0x00000000 Number 0 hal_system.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_timer.c 0x00000000 Number 0 hal_timer.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\hal_uart.c 0x00000000 Number 0 hal_uart.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\internal\dcs_packet_fifo.c 0x00000000 Number 0 dcs_packet_fifo.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\internal\hal_internal_dcs.c 0x00000000 Number 0 hal_internal_dcs.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\internal\hal_internal_fb.c 0x00000000 Number 0 hal_internal_fb.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\internal\hal_internal_svs.c 0x00000000 Number 0 hal_internal_svs.o ABSOLUTE + ..\..\..\src\driver\cuckoo\hal\internal\hal_internal_vsync.c 0x00000000 Number 0 hal_internal_vsync.o ABSOLUTE + ..\..\..\src\driver\cuckoo\src\drv_se.c 0x00000000 Number 0 drv_se.o ABSOLUTE + ..\..\src\app\P8P\p8p_demo.c 0x00000000 Number 0 p8p_demo.o ABSOLUTE + ..\..\src\app\main.c 0x00000000 Number 0 main.o ABSOLUTE + ..\..\src\board\board.c 0x00000000 Number 0 board.o ABSOLUTE + ..\..\src\board\startup\startup_ARMCM0.s 0x00000000 Number 0 startup_armcm0.o ABSOLUTE + ..\\..\\..\\src\\common\\tau_delay.c 0x00000000 Number 0 tau_delay.o ABSOLUTE + ..\\..\\..\\src\\common\\tau_log.c 0x00000000 Number 0 tau_log.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_common.c 0x00000000 Number 0 drv_common.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_crgu.c 0x00000000 Number 0 drv_crgu.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_dma.c 0x00000000 Number 0 drv_dma.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_dsc_dec.c 0x00000000 Number 0 drv_dsc_dec.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_dsi_rx.c 0x00000000 Number 0 drv_dsi_rx.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_dsi_tx.c 0x00000000 Number 0 drv_dsi_tx.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_efuse.c 0x00000000 Number 0 drv_efuse.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_gpio.c 0x00000000 Number 0 drv_gpio.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_lcdc.c 0x00000000 Number 0 drv_lcdc.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_memc.c 0x00000000 Number 0 drv_memc.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_per_common.c 0x00000000 Number 0 drv_per_common.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_phy_common.c 0x00000000 Number 0 drv_phy_common.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_pwr.c 0x00000000 Number 0 drv_pwr.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_rxbr.c 0x00000000 Number 0 drv_rxbr.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_swire.c 0x00000000 Number 0 drv_swire.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_sys_cfg.c 0x00000000 Number 0 drv_sys_cfg.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_timer.c 0x00000000 Number 0 drv_timer.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_uart.c 0x00000000 Number 0 drv_uart.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\drv\\drv_vidc.c 0x00000000 Number 0 drv_vidc.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_dsi_rx_ctrl.c 0x00000000 Number 0 hal_dsi_rx_ctrl.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_dsi_tx_ctrl.c 0x00000000 Number 0 hal_dsi_tx_ctrl.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_gpio.c 0x00000000 Number 0 hal_gpio.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_pwr.c 0x00000000 Number 0 hal_pwr.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_swire.c 0x00000000 Number 0 hal_swire.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_system.c 0x00000000 Number 0 hal_system.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_timer.c 0x00000000 Number 0 hal_timer.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\hal_uart.c 0x00000000 Number 0 hal_uart.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\internal\\dcs_packet_fifo.c 0x00000000 Number 0 dcs_packet_fifo.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\internal\\hal_internal_dcs.c 0x00000000 Number 0 hal_internal_dcs.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\internal\\hal_internal_fb.c 0x00000000 Number 0 hal_internal_fb.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\internal\\hal_internal_svs.c 0x00000000 Number 0 hal_internal_svs.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\hal\\internal\\hal_internal_vsync.c 0x00000000 Number 0 hal_internal_vsync.o ABSOLUTE + ..\\..\\..\\src\\driver\\cuckoo\\src\\drv_se.c 0x00000000 Number 0 drv_se.o ABSOLUTE + ..\\..\\src\\app\\P8P\\p8p_demo.c 0x00000000 Number 0 p8p_demo.o ABSOLUTE + ..\\..\\src\\app\\main.c 0x00000000 Number 0 main.o ABSOLUTE + ..\\..\\src\\board\\board.c 0x00000000 Number 0 board.o ABSOLUTE + cdrcmple.s 0x00000000 Number 0 cdrcmple.o ABSOLUTE + cfcmple.s 0x00000000 Number 0 cfcmple.o ABSOLUTE + cfrcmple.s 0x00000000 Number 0 cfrcmple.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE + init.s 0x00000000 Number 0 init.o ABSOLUTE + RESET 0x00010000 Section 192 startup_armcm0.o(RESET) + .ARM.Collect$$$$00000000 0x000100c0 Section 0 entry.o(.ARM.Collect$$$$00000000) + .ARM.Collect$$$$00000001 0x000100c0 Section 4 entry2.o(.ARM.Collect$$$$00000001) + .ARM.Collect$$$$00000004 0x000100c4 Section 4 entry5.o(.ARM.Collect$$$$00000004) + .ARM.Collect$$$$00000008 0x000100c8 Section 0 entry7b.o(.ARM.Collect$$$$00000008) + .ARM.Collect$$$$0000000A 0x000100c8 Section 0 entry8b.o(.ARM.Collect$$$$0000000A) + .ARM.Collect$$$$0000000B 0x000100c8 Section 8 entry9a.o(.ARM.Collect$$$$0000000B) + .ARM.Collect$$$$0000000D 0x000100d0 Section 0 entry10a.o(.ARM.Collect$$$$0000000D) + .ARM.Collect$$$$0000000F 0x000100d0 Section 0 entry11a.o(.ARM.Collect$$$$0000000F) + .ARM.Collect$$$$00002712 0x000100d0 Section 4 entry2.o(.ARM.Collect$$$$00002712) + __lit__00000000 0x000100d0 Data 4 entry2.o(.ARM.Collect$$$$00002712) + .text 0x000100d4 Section 120 startup_armcm0.o(.text) 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Section 0 llushr.o(.text) + .text 0x000107be Section 0 llsshr.o(.text) + .text 0x000107e4 Section 0 iusefp.o(.text) + .text 0x000107e4 Section 0 fepilogue.o(.text) + .text 0x00010866 Section 0 depilogue.o(.text) + .text 0x00010924 Section 0 ddiv.o(.text) + .text 0x00010a14 Section 0 dfixul.o(.text) + .text 0x00010a54 Section 40 cdrcmple.o(.text) + .text 0x00010a7c Section 36 init.o(.text) + .text 0x00010aa0 Section 0 __dczerorl2.o(.text) + i.AP_NRESET_IRQn_Handler 0x00010af8 Section 0 drv_gpio.o(i.AP_NRESET_IRQn_Handler) + i.DMA_IRQn_Handler 0x00010b14 Section 0 drv_dma.o(i.DMA_IRQn_Handler) + i.EXTI_INT0_IRQn_Handler 0x00010b70 Section 0 drv_gpio.o(i.EXTI_INT0_IRQn_Handler) + i.EXTI_INT1_IRQn_Handler 0x00010b7a Section 0 drv_gpio.o(i.EXTI_INT1_IRQn_Handler) + i.EXTI_INT2_IRQn_Handler 0x00010b84 Section 0 drv_gpio.o(i.EXTI_INT2_IRQn_Handler) + i.EXTI_INT3_IRQn_Handler 0x00010b8e Section 0 drv_gpio.o(i.EXTI_INT3_IRQn_Handler) + i.EXTI_INT4_IRQn_Handler 0x00010b98 Section 0 drv_gpio.o(i.EXTI_INT4_IRQn_Handler) + i.EXTI_INT5_IRQn_Handler 0x00010ba2 Section 0 drv_gpio.o(i.EXTI_INT5_IRQn_Handler) + i.EXTI_INT6_IRQn_Handler 0x00010bac Section 0 drv_gpio.o(i.EXTI_INT6_IRQn_Handler) + i.EXTI_INT7_IRQn_Handler 0x00010bb6 Section 0 drv_gpio.o(i.EXTI_INT7_IRQn_Handler) + i.HardFault_Handler 0x00010bc0 Section 0 drv_common.o(i.HardFault_Handler) + i.LCDC_IRQn_Handler 0x00010c08 Section 0 hal_internal_vsync.o(i.LCDC_IRQn_Handler) + i.MEMC_IRQn_Handler 0x00010d08 Section 0 drv_memc.o(i.MEMC_IRQn_Handler) + i.MIPI_TX_IRQn_Handler 0x00010da4 Section 0 drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler) + i.SWIRE_IRQn_Handler 0x00010e5c Section 0 drv_swire.o(i.SWIRE_IRQn_Handler) + i.SysTick_Handler 0x00010e8c Section 0 drv_common.o(i.SysTick_Handler) + i.TIMER0_IRQn_Handler 0x00010ea4 Section 0 drv_timer.o(i.TIMER0_IRQn_Handler) + i.TIMER1_IRQn_Handler 0x00010eae Section 0 drv_timer.o(i.TIMER1_IRQn_Handler) + i.TIMER2_IRQn_Handler 0x00010eb8 Section 0 drv_timer.o(i.TIMER2_IRQn_Handler) + i.TIMER3_IRQn_Handler 0x00010ec2 Section 0 drv_timer.o(i.TIMER3_IRQn_Handler) + i.VIDC_IRQn_Handler 0x00010ecc Section 0 drv_vidc.o(i.VIDC_IRQn_Handler) + i.VPRE1_IRQn_Handler 0x00010ee8 Section 0 drv_rxbr.o(i.VPRE1_IRQn_Handler) + i.VPRE_IRQn_Handler 0x00010f04 Section 0 hal_internal_dcs.o(i.VPRE_IRQn_Handler) + i.__0printf 0x00010f70 Section 0 printfa.o(i.__0printf) + i.__0vsprintf 0x00010f90 Section 0 printfa.o(i.__0vsprintf) + i.__ARM_clz 0x00010fb4 Section 0 depilogue.o(i.__ARM_clz) + i.__ARM_common_switch8 0x00010fe2 Section 0 hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) + i.__scatterload_null 0x00010ffc Section 2 handlers.o(i.__scatterload_null) + .ARM.__at_0x11000 0x00011000 Section 28 drv_common.o(.ARM.__at_0x11000) + .ARM.__at_0x1101C 0x0001101c Section 16 tau_log.o(.ARM.__at_0x1101C) + .ARM.__at_0x1102C 0x0001102c Section 22 hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) + i.MIPI_RX_IRQn_Handler 0x00011044 Section 0 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i._printf_pre_padding 0x00011dfc Section 0 printfa.o(i._printf_pre_padding) + _printf_pre_padding 0x00011dfd Thumb Code 44 printfa.o(i._printf_pre_padding) + i._sputc 0x00011e28 Section 0 printfa.o(i._sputc) + _sputc 0x00011e29 Thumb Code 10 printfa.o(i._sputc) + i.ap_dcs_read 0x00011e34 Section 0 p8p_demo.o(i.ap_dcs_read) + ap_dcs_read 0x00011e35 Thumb Code 280 p8p_demo.o(i.ap_dcs_read) + i.ap_dcs_set_backlight 0x00011f78 Section 0 p8p_demo.o(i.ap_dcs_set_backlight) + ap_dcs_set_backlight 0x00011f79 Thumb Code 130 p8p_demo.o(i.ap_dcs_set_backlight) + i.ap_dcs_set_display_off 0x0001200c Section 0 p8p_demo.o(i.ap_dcs_set_display_off) + ap_dcs_set_display_off 0x0001200d Thumb Code 34 p8p_demo.o(i.ap_dcs_set_display_off) + i.ap_dcs_set_display_on 0x00012054 Section 0 p8p_demo.o(i.ap_dcs_set_display_on) + ap_dcs_set_display_on 0x00012055 Thumb Code 90 p8p_demo.o(i.ap_dcs_set_display_on) + i.ap_dcs_set_enter_sleep_mode 0x000120f4 Section 0 p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) + ap_dcs_set_enter_sleep_mode 0x000120f5 Thumb Code 104 p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) + i.ap_dcs_set_exit_sleep_mode 0x00012188 Section 0 p8p_demo.o(i.ap_dcs_set_exit_sleep_mode) + ap_dcs_set_exit_sleep_mode 0x00012189 Thumb Code 28 p8p_demo.o(i.ap_dcs_set_exit_sleep_mode) + i.ap_dcs_set_frame_change 0x000121c8 Section 0 p8p_demo.o(i.ap_dcs_set_frame_change) + ap_dcs_set_frame_change 0x000121c9 Thumb Code 46 p8p_demo.o(i.ap_dcs_set_frame_change) + i.ap_rstn_pull_down_cb 0x000121fc Section 0 p8p_demo.o(i.ap_rstn_pull_down_cb) + ap_rstn_pull_down_cb 0x000121fd Thumb Code 38 p8p_demo.o(i.ap_rstn_pull_down_cb) + i.ap_rstn_pull_high_cb 0x00012254 Section 0 p8p_demo.o(i.ap_rstn_pull_high_cb) + ap_rstn_pull_high_cb 0x00012255 Thumb Code 22 p8p_demo.o(i.ap_rstn_pull_high_cb) + i.ap_set_FPS_53 0x00012270 Section 0 p8p_demo.o(i.ap_set_FPS_53) + ap_set_FPS_53 0x00012271 Thumb Code 74 p8p_demo.o(i.ap_set_FPS_53) + i.app_display_init 0x000122ba Section 0 p8p_demo.o(i.app_display_init) + i.app_gpio_init 0x000122e8 Section 0 p8p_demo.o(i.app_gpio_init) + i.app_init_panel 0x00012304 Section 0 p8p_demo.o(i.app_init_panel) + app_init_panel 0x00012305 Thumb Code 42 p8p_demo.o(i.app_init_panel) + i.app_mipi_rx_init 0x00012338 Section 0 p8p_demo.o(i.app_mipi_rx_init) + app_mipi_rx_init 0x00012339 Thumb Code 232 p8p_demo.o(i.app_mipi_rx_init) + i.app_mipi_tx_init 0x00012458 Section 0 p8p_demo.o(i.app_mipi_tx_init) + app_mipi_tx_init 0x00012459 Thumb Code 214 p8p_demo.o(i.app_mipi_tx_init) + i.app_mipi_tx_start 0x00012558 Section 0 p8p_demo.o(i.app_mipi_tx_start) + app_mipi_tx_start 0x00012559 Thumb Code 112 p8p_demo.o(i.app_mipi_tx_start) + i.app_system_process 0x000125fc Section 0 p8p_demo.o(i.app_system_process) + app_system_process 0x000125fd Thumb Code 60 p8p_demo.o(i.app_system_process) + i.app_system_resume 0x00012668 Section 0 p8p_demo.o(i.app_system_resume) + app_system_resume 0x00012669 Thumb Code 30 p8p_demo.o(i.app_system_resume) + i.app_system_suspend 0x000126ac Section 0 p8p_demo.o(i.app_system_suspend) + app_system_suspend 0x000126ad Thumb Code 202 p8p_demo.o(i.app_system_suspend) + i.app_tx_panel_reset 0x0001283c Section 0 p8p_demo.o(i.app_tx_panel_reset) + app_tx_panel_reset 0x0001283d Thumb Code 46 p8p_demo.o(i.app_tx_panel_reset) + i.board_Init 0x0001286c Section 0 board.o(i.board_Init) + i.ceil 0x00012884 Section 0 ceil.o(i.ceil) + i.check_mipi_rx_tx_video_info 0x0001294c Section 0 hal_internal_vsync.o(i.check_mipi_rx_tx_video_info) + check_mipi_rx_tx_video_info 0x0001294d Thumb Code 44 hal_internal_vsync.o(i.check_mipi_rx_tx_video_info) + i.check_pkt_buf_rev 0x00012978 Section 0 hal_internal_dcs.o(i.check_pkt_buf_rev) + check_pkt_buf_rev 0x00012979 Thumb Code 84 hal_internal_dcs.o(i.check_pkt_buf_rev) + i.dcs_packet_fifo_alloc 0x00012a00 Section 0 dcs_packet_fifo.o(i.dcs_packet_fifo_alloc) + i.dcs_packet_fifo_init 0x00012a58 Section 0 dcs_packet_fifo.o(i.dcs_packet_fifo_init) + i.dcs_packet_free_fifo_header 0x00012a70 Section 0 dcs_packet_fifo.o(i.dcs_packet_free_fifo_header) + i.dcs_packet_get_fifo_header 0x00012ab4 Section 0 dcs_packet_fifo.o(i.dcs_packet_get_fifo_header) + i.delayMs 0x00012ad8 Section 0 tau_delay.o(i.delayMs) + i.delayUs 0x00012af0 Section 0 tau_delay.o(i.delayUs) + i.drv_common_system_init 0x00012b1c Section 0 drv_common.o(i.drv_common_system_init) + i.drv_crgu_enable_clock 0x00012b24 Section 0 drv_crgu.o(i.drv_crgu_enable_clock) + i.drv_crgu_get_rxbr_clk 0x00012b60 Section 0 drv_crgu.o(i.drv_crgu_get_rxbr_clk) + i.drv_crgu_reset_modules 0x00012bc8 Section 0 drv_crgu.o(i.drv_crgu_reset_modules) + i.drv_crgu_set_ahb_clk 0x00012bd8 Section 0 drv_crgu.o(i.drv_crgu_set_ahb_clk) + i.drv_crgu_set_clock_div 0x00012c00 Section 0 drv_crgu.o(i.drv_crgu_set_clock_div) + i.drv_crgu_set_dpi_clk 0x00012c10 Section 0 drv_crgu.o(i.drv_crgu_set_dpi_clk) + i.drv_crgu_set_dsc_clk 0x00012c4c Section 0 drv_crgu.o(i.drv_crgu_set_dsc_clk) + i.drv_crgu_set_fb_clk 0x00012c84 Section 0 drv_crgu.o(i.drv_crgu_set_fb_clk) + i.drv_crgu_set_lcdc_clk 0x00012cac Section 0 drv_crgu.o(i.drv_crgu_set_lcdc_clk) + i.drv_crgu_set_reset 0x00012cd4 Section 0 drv_crgu.o(i.drv_crgu_set_reset) + i.drv_crgu_set_rxbr_clk 0x00012cec Section 0 drv_crgu.o(i.drv_crgu_set_rxbr_clk) + i.drv_crgu_set_vidc_clk 0x00012d14 Section 0 drv_crgu.o(i.drv_crgu_set_vidc_clk) + i.drv_dma_clear_status 0x00012d3c Section 0 drv_dma.o(i.drv_dma_clear_status) + i.drv_dma_get_int_source 0x00012d54 Section 0 drv_dma.o(i.drv_dma_get_int_source) + drv_dma_get_int_source 0x00012d55 Thumb Code 16 drv_dma.o(i.drv_dma_get_int_source) + i.drv_dsc_dec_disable 0x00012d68 Section 0 drv_dsc_dec.o(i.drv_dsc_dec_disable) + i.drv_dsc_dec_enable 0x00012d84 Section 0 drv_dsc_dec.o(i.drv_dsc_dec_enable) + i.drv_dsc_dec_get_nslc 0x00012dbc Section 0 drv_dsc_dec.o(i.drv_dsc_dec_get_nslc) + i.drv_dsc_dec_set_irqen 0x00012ddc Section 0 drv_dsc_dec.o(i.drv_dsc_dec_set_irqen) + i.drv_dsi_rx_calc_ipi_tx_delay 0x00012df8 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) + i.drv_dsi_rx_enable_irq 0x00012f04 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) + i.drv_dsi_rx_get_color_bpp 0x00012f44 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp) + drv_dsi_rx_get_color_bpp 0x00012f45 Thumb Code 62 drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp) + i.drv_dsi_rx_get_color_pcc 0x00012f94 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_color_pcc) + drv_dsi_rx_get_color_pcc 0x00012f95 Thumb Code 24 drv_dsi_rx.o(i.drv_dsi_rx_get_color_pcc) + i.drv_dsi_rx_get_compression_en 0x00012fb0 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en) + i.drv_dsi_rx_get_ddi_crc_en 0x00012fc0 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_ddi_crc_en) + i.drv_dsi_rx_get_max_ret_size 0x00012fd0 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_max_ret_size) + i.drv_dsi_rx_power_up 0x00012fdc Section 0 drv_dsi_rx.o(i.drv_dsi_rx_power_up) + i.drv_dsi_rx_set_check_crc 0x00012ff4 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_check_crc) + i.drv_dsi_rx_set_ctrl_cfg 0x00013010 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ctrl_cfg) + i.drv_dsi_rx_set_ddi_cfg 0x00013034 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) + i.drv_dsi_rx_set_ddi_crc_en 0x00013044 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_crc_en) + i.drv_dsi_rx_set_inten 0x00013060 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_inten) + i.drv_dsi_rx_set_ipi_cfg 0x0001306c Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_cfg) + i.drv_dsi_rx_set_ipi_ycbcr_frmt 0x0001307c Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_ycbcr_frmt) + i.drv_dsi_rx_set_lane_swap 0x00013098 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_lane_swap) + i.drv_dsi_rx_set_resp_cnt 0x000130ac Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_resp_cnt) + i.drv_dsi_rx_set_tear_resp_en 0x000130d0 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_tear_resp_en) + i.drv_dsi_rx_set_up_phy 0x000130ec Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) + i.drv_dsi_rx_shut_down 0x000131ec Section 0 drv_dsi_rx.o(i.drv_dsi_rx_shut_down) + i.drv_dsi_tx_command_header 0x00013204 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_command_header) + i.drv_dsi_tx_command_mode_cfg 0x0001321c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg) + i.drv_dsi_tx_command_put_payload 0x00013274 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) + i.drv_dsi_tx_config_eotp 0x00013280 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_config_eotp) + i.drv_dsi_tx_config_int 0x000132a0 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_config_int) + i.drv_dsi_tx_dpi_lpcmd_time 0x000132ac Section 0 drv_dsi_tx.o(i.drv_dsi_tx_dpi_lpcmd_time) + i.drv_dsi_tx_dpi_mode 0x000132bc Section 0 drv_dsi_tx.o(i.drv_dsi_tx_dpi_mode) + i.drv_dsi_tx_dpi_polarity 0x000132cc Section 0 drv_dsi_tx.o(i.drv_dsi_tx_dpi_polarity) + i.drv_dsi_tx_edpi_cmd_size 0x000132f0 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_edpi_cmd_size) + i.drv_dsi_tx_get_cmd_status 0x000132fc Section 0 drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) + i.drv_dsi_tx_mode 0x00013308 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_mode) + i.drv_dsi_tx_phy_clock_lane_auto_lp 0x00013314 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp) + i.drv_dsi_tx_phy_clock_lane_req_hs 0x00013330 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs) + i.drv_dsi_tx_phy_lane_mode 0x00013350 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_lane_mode) + i.drv_dsi_tx_phy_status_ready 0x00013360 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready) + i.drv_dsi_tx_phy_status_stopstate 0x000133c8 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) + i.drv_dsi_tx_phy_test_setup 0x0001340c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) + i.drv_dsi_tx_phy_time_cfg 0x0001355c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg) + i.drv_dsi_tx_powerup 0x0001357c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_powerup) + i.drv_dsi_tx_response_mode 0x00013588 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_response_mode) + i.drv_dsi_tx_set_bta_ack 0x000135ac Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_bta_ack) + i.drv_dsi_tx_set_esc_div 0x000135c8 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) + i.drv_dsi_tx_set_int 0x000135dc Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_int) + i.drv_dsi_tx_set_time_out_div 0x0001361c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_time_out_div) + i.drv_dsi_tx_set_video_chunk 0x00013634 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_video_chunk) + i.drv_dsi_tx_set_video_timing 0x00013648 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_video_timing) + i.drv_dsi_tx_shutdown 0x0001366c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_shutdown) + i.drv_dsi_tx_timeout_cfg 0x00013678 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_timeout_cfg) + i.drv_dsi_tx_video_mode_cfg 0x000136a4 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_cfg) + i.drv_efuse_enter_inactive 0x0001378c Section 0 drv_efuse.o(i.drv_efuse_enter_inactive) + i.drv_efuse_int_enable 0x000137c2 Section 0 drv_efuse.o(i.drv_efuse_int_enable) + i.drv_efuse_read 0x000137ce Section 0 drv_efuse.o(i.drv_efuse_read) + i.drv_efuse_read_req 0x00013808 Section 0 drv_efuse.o(i.drv_efuse_read_req) + i.drv_gpio_handle_int 0x00013820 Section 0 drv_gpio.o(i.drv_gpio_handle_int) + drv_gpio_handle_int 0x00013821 Thumb Code 30 drv_gpio.o(i.drv_gpio_handle_int) + i.drv_gpio_register_ap_reset_callback 0x00013844 Section 0 drv_gpio.o(i.drv_gpio_register_ap_reset_callback) + i.drv_gpio_register_callback 0x00013850 Section 0 drv_gpio.o(i.drv_gpio_register_callback) + i.drv_gpio_set_int 0x00013864 Section 0 drv_gpio.o(i.drv_gpio_set_int) + i.drv_gpio_set_ioe 0x000138a8 Section 0 drv_gpio.o(i.drv_gpio_set_ioe) + i.drv_gpio_set_mode 0x000138c8 Section 0 drv_gpio.o(i.drv_gpio_set_mode) + i.drv_gpio_set_output_data 0x000138dc Section 0 hal_gpio.o(i.drv_gpio_set_output_data) + drv_gpio_set_output_data 0x000138dd Thumb Code 26 hal_gpio.o(i.drv_gpio_set_output_data) + i.drv_lcdc_bcsa_config 0x000138fc Section 0 drv_lcdc.o(i.drv_lcdc_bcsa_config) + i.drv_lcdc_cfg_int_frame 0x00013924 Section 0 drv_lcdc.o(i.drv_lcdc_cfg_int_frame) + i.drv_lcdc_clear_int 0x00013950 Section 0 drv_lcdc.o(i.drv_lcdc_clear_int) + drv_lcdc_clear_int 0x00013951 Thumb Code 20 drv_lcdc.o(i.drv_lcdc_clear_int) + i.drv_lcdc_cmd_start 0x00013968 Section 0 drv_lcdc.o(i.drv_lcdc_cmd_start) + i.drv_lcdc_config_acc_command_mode 0x0001399c Section 0 drv_lcdc.o(i.drv_lcdc_config_acc_command_mode) + i.drv_lcdc_config_int 0x000139b0 Section 0 drv_lcdc.o(i.drv_lcdc_config_int) + i.drv_lcdc_config_int_single 0x000139e8 Section 0 drv_lcdc.o(i.drv_lcdc_config_int_single) + i.drv_lcdc_config_overwrite_rgb 0x00013a10 Section 0 drv_lcdc.o(i.drv_lcdc_config_overwrite_rgb) + i.drv_lcdc_config_src_parameter 0x00013a28 Section 0 drv_lcdc.o(i.drv_lcdc_config_src_parameter) + i.drv_lcdc_crop_hact 0x00013a78 Section 0 drv_lcdc.o(i.drv_lcdc_crop_hact) + i.drv_lcdc_ctrl_flow 0x00013a88 Section 0 drv_lcdc.o(i.drv_lcdc_ctrl_flow) + i.drv_lcdc_dith_config 0x00013ac0 Section 0 drv_lcdc.o(i.drv_lcdc_dith_config) + i.drv_lcdc_edge_dect_config 0x00013af0 Section 0 drv_lcdc.o(i.drv_lcdc_edge_dect_config) + i.drv_lcdc_edge_enh_config 0x00013b2c Section 0 drv_lcdc.o(i.drv_lcdc_edge_enh_config) + i.drv_lcdc_enable_shadow_reg 0x00013b90 Section 0 drv_lcdc.o(i.drv_lcdc_enable_shadow_reg) + i.drv_lcdc_endianness_config 0x00013bb4 Section 0 drv_lcdc.o(i.drv_lcdc_endianness_config) + i.drv_lcdc_fc_config 0x00013bd0 Section 0 drv_lcdc.o(i.drv_lcdc_fc_config) + i.drv_lcdc_fldc_config 0x00013bf0 Section 0 drv_lcdc.o(i.drv_lcdc_fldc_config) + i.drv_lcdc_function_disable 0x00013c14 Section 0 drv_lcdc.o(i.drv_lcdc_function_disable) + i.drv_lcdc_function_enable 0x00013c38 Section 0 drv_lcdc.o(i.drv_lcdc_function_enable) + i.drv_lcdc_set_int 0x00013c5c Section 0 drv_lcdc.o(i.drv_lcdc_set_int) + i.drv_lcdc_set_prefetch 0x00013c98 Section 0 drv_lcdc.o(i.drv_lcdc_set_prefetch) + i.drv_lcdc_set_tear_line 0x00013cb4 Section 0 drv_lcdc.o(i.drv_lcdc_set_tear_line) + i.drv_lcdc_stop_display 0x00013cd0 Section 0 drv_lcdc.o(i.drv_lcdc_stop_display) + i.drv_lcdc_vid_hw_start 0x00013ce0 Section 0 drv_lcdc.o(i.drv_lcdc_vid_hw_start) + i.drv_lcdc_vintp_mode_config 0x00013d1c Section 0 drv_lcdc.o(i.drv_lcdc_vintp_mode_config) + i.drv_memc_clear_status 0x00013d34 Section 0 drv_memc.o(i.drv_memc_clear_status) + i.drv_memc_enable_irq 0x00013d48 Section 0 drv_memc.o(i.drv_memc_enable_irq) + i.drv_memc_gen_a_tear_signal 0x00013d88 Section 0 drv_memc.o(i.drv_memc_gen_a_tear_signal) + i.drv_memc_get_status 0x00013d98 Section 0 drv_memc.o(i.drv_memc_get_status) + i.drv_memc_get_tear_mode 0x00013db0 Section 0 drv_memc.o(i.drv_memc_get_tear_mode) + i.drv_memc_rate_transfer_sel 0x00013dc0 Section 0 drv_memc.o(i.drv_memc_rate_transfer_sel) + i.drv_memc_sel_vsync 0x00013ddc Section 0 drv_memc.o(i.drv_memc_sel_vsync) + i.drv_memc_set_active_height 0x00013df0 Section 0 drv_memc.o(i.drv_memc_set_active_height) + i.drv_memc_set_circ_mode_enable 0x00013e08 Section 0 drv_memc.o(i.drv_memc_set_circ_mode_enable) + i.drv_memc_set_data_mode 0x00013e24 Section 0 drv_memc.o(i.drv_memc_set_data_mode) + i.drv_memc_set_double_buffer 0x00013e38 Section 0 drv_memc.o(i.drv_memc_set_double_buffer) + i.drv_memc_set_frame_drop_select 0x00013e50 Section 0 drv_memc.o(i.drv_memc_set_frame_drop_select) + i.drv_memc_set_fs_en_conditions 0x00013e6c Section 0 drv_memc.o(i.drv_memc_set_fs_en_conditions) + i.drv_memc_set_lcdc_st_conditions 0x00013e84 Section 0 drv_memc.o(i.drv_memc_set_lcdc_st_conditions) + i.drv_memc_set_ltpo_mode 0x00013ea0 Section 0 drv_memc.o(i.drv_memc_set_ltpo_mode) + i.drv_memc_set_ltpo_pu_thres 0x00013ec0 Section 0 drv_memc.o(i.drv_memc_set_ltpo_pu_thres) + i.drv_memc_set_tear_mode 0x00013ed8 Section 0 drv_memc.o(i.drv_memc_set_tear_mode) + i.drv_memc_set_tear_waveform 0x00013eec Section 0 drv_memc.o(i.drv_memc_set_tear_waveform) + i.drv_memc_set_vidc_sync_cnt 0x00013f18 Section 0 drv_memc.o(i.drv_memc_set_vidc_sync_cnt) + i.drv_phy_test_clear 0x00013f2c Section 0 drv_phy_common.o(i.drv_phy_test_clear) + i.drv_phy_test_lock 0x00013f3c Section 0 drv_phy_common.o(i.drv_phy_test_lock) + i.drv_pwr_efuse_pd 0x00013f54 Section 0 drv_pwr.o(i.drv_pwr_efuse_pd) + i.drv_pwr_enter_deep_sleep_mode 0x00013f84 Section 0 drv_pwr.o(i.drv_pwr_enter_deep_sleep_mode) + i.drv_pwr_enter_sleep_mode_ex 0x00013fd0 Section 0 drv_pwr.o(i.drv_pwr_enter_sleep_mode_ex) + i.drv_pwr_enter_stop_sleep_mode 0x00014004 Section 0 drv_pwr.o(i.drv_pwr_enter_stop_sleep_mode) + i.drv_pwr_exit_sleep_mode 0x0001409c Section 0 drv_pwr.o(i.drv_pwr_exit_sleep_mode) + i.drv_pwr_get_power_ready_st 0x000140c4 Section 0 drv_pwr.o(i.drv_pwr_get_power_ready_st) + i.drv_pwr_set_breath_screen_power_sel 0x000140d4 Section 0 drv_pwr.o(i.drv_pwr_set_breath_screen_power_sel) + i.drv_pwr_set_digit_power_sel 0x000140fc Section 0 drv_pwr.o(i.drv_pwr_set_digit_power_sel) + i.drv_pwr_set_pll_clk 0x00014124 Section 0 drv_pwr.o(i.drv_pwr_set_pll_clk) + i.drv_pwr_set_wakeup_type 0x00014158 Section 0 drv_pwr.o(i.drv_pwr_set_wakeup_type) + i.drv_pwr_write_lock 0x00014184 Section 0 drv_pwr.o(i.drv_pwr_write_lock) + i.drv_rxbr_clear_pkt_buffer 0x000141a4 Section 0 drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) + i.drv_rxbr_clear_status0 0x000141b4 Section 0 drv_rxbr.o(i.drv_rxbr_clear_status0) + i.drv_rxbr_enable_irq 0x000141c0 Section 0 drv_rxbr.o(i.drv_rxbr_enable_irq) + i.drv_rxbr_frame_drop_cfg 0x0001421c Section 0 drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) + i.drv_rxbr_get_int_source 0x00014238 Section 0 hal_internal_vsync.o(i.drv_rxbr_get_int_source) + drv_rxbr_get_int_source 0x00014239 Thumb Code 20 hal_internal_vsync.o(i.drv_rxbr_get_int_source) + i.drv_rxbr_get_status0 0x00014250 Section 0 hal_internal_dcs.o(i.drv_rxbr_get_status0) + drv_rxbr_get_status0 0x00014251 Thumb Code 20 hal_internal_dcs.o(i.drv_rxbr_get_status0) + i.drv_rxbr_hline_rcv1_cfg 0x00014268 Section 0 drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg) + i.drv_rxbr_hline_rcv_cfg 0x0001427c Section 0 drv_rxbr.o(i.drv_rxbr_hline_rcv_cfg) + i.drv_rxbr_register_irq1_callback 0x0001428c Section 0 drv_rxbr.o(i.drv_rxbr_register_irq1_callback) + i.drv_rxbr_set_ack_pkt_header 0x00014298 Section 0 drv_rxbr.o(i.drv_rxbr_set_ack_pkt_header) + i.drv_rxbr_set_color_format 0x000142b0 Section 0 drv_rxbr.o(i.drv_rxbr_set_color_format) + i.drv_rxbr_set_filter_regs 0x000142cc Section 0 drv_rxbr.o(i.drv_rxbr_set_filter_regs) + i.drv_rxbr_set_inten 0x000142f0 Section 0 drv_rxbr.o(i.drv_rxbr_set_inten) + i.drv_rxbr_set_ltpo_drop_th 0x0001430c Section 0 drv_rxbr.o(i.drv_rxbr_set_ltpo_drop_th) + i.drv_rxbr_set_usr_cfg 0x00014324 Section 0 drv_rxbr.o(i.drv_rxbr_set_usr_cfg) + i.drv_rxbr_set_usr_col 0x00014364 Section 0 drv_rxbr.o(i.drv_rxbr_set_usr_col) + i.drv_rxbr_set_usr_row 0x00014374 Section 0 drv_rxbr.o(i.drv_rxbr_set_usr_row) + i.drv_se_init 0x00014384 Section 0 drv_se.o(i.drv_se_init) + i.drv_se_set_dsc 0x000143fc Section 0 drv_se.o(i.drv_se_set_dsc) + i.drv_se_set_lcdc 0x000144d0 Section 0 drv_se.o(i.drv_se_set_lcdc) + i.drv_se_set_memc 0x00014558 Section 0 drv_se.o(i.drv_se_set_memc) + i.drv_se_set_rxbr 0x000145c0 Section 0 drv_se.o(i.drv_se_set_rxbr) + i.drv_se_set_vidc 0x00014690 Section 0 drv_se.o(i.drv_se_set_vidc) + i.drv_se_start_rx 0x0001473c Section 0 drv_se.o(i.drv_se_start_rx) + i.drv_swire_enable 0x00014750 Section 0 drv_swire.o(i.drv_swire_enable) + i.drv_swire_get_pulse_count 0x0001476c Section 0 drv_swire.o(i.drv_swire_get_pulse_count) + i.drv_swire_register_callback 0x00014778 Section 0 drv_swire.o(i.drv_swire_register_callback) + i.drv_swire_set_bit_time 0x00014784 Section 0 drv_swire.o(i.drv_swire_set_bit_time) + i.drv_swire_set_int 0x0001479c Section 0 drv_swire.o(i.drv_swire_set_int) + i.drv_swire_set_power_down 0x000147e4 Section 0 drv_swire.o(i.drv_swire_set_power_down) + i.drv_swire_set_pulse_count 0x00014800 Section 0 drv_swire.o(i.drv_swire_set_pulse_count) + i.drv_swire_set_trig_mode 0x0001480c Section 0 drv_swire.o(i.drv_swire_set_trig_mode) + i.drv_sys_cfg_clear_all_int 0x00014828 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_clear_all_int) + i.drv_sys_cfg_clear_pending 0x00014834 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) + i.drv_sys_cfg_sel_ap_rst_trig 0x0001485c Section 0 drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_trig) + i.drv_sys_cfg_sel_gpio_group 0x00014880 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_sel_gpio_group) + i.drv_sys_cfg_sel_int_trig 0x000148a4 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_sel_int_trig) + i.drv_sys_cfg_sel_swire_timer 0x000148c8 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_sel_swire_timer) + i.drv_sys_cfg_set_int 0x000148e0 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_set_int) + i.drv_timer_clear_status_flags 0x00014904 Section 0 drv_timer.o(i.drv_timer_clear_status_flags) + drv_timer_clear_status_flags 0x00014905 Thumb Code 26 drv_timer.o(i.drv_timer_clear_status_flags) + i.drv_timer_enable 0x0001491e Section 0 drv_timer.o(i.drv_timer_enable) + i.drv_timer_get_instance 0x00014940 Section 0 drv_timer.o(i.drv_timer_get_instance) + i.drv_timer_handle_interrupt 0x00014950 Section 0 drv_timer.o(i.drv_timer_handle_interrupt) + drv_timer_handle_interrupt 0x00014951 Thumb Code 54 drv_timer.o(i.drv_timer_handle_interrupt) + i.drv_timer_set_compare_val 0x0001498c Section 0 drv_timer.o(i.drv_timer_set_compare_val) + i.drv_timer_set_int 0x000149cc Section 0 drv_timer.o(i.drv_timer_set_int) + i.drv_timer_set_prescaler 0x00014a14 Section 0 drv_timer.o(i.drv_timer_set_prescaler) + i.drv_timer_set_repeat 0x00014a3c Section 0 drv_timer.o(i.drv_timer_set_repeat) + i.drv_tx_phy_test_enter 0x00014a4c Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_enter) + i.drv_tx_phy_test_exit 0x00014a6c Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_exit) + i.drv_tx_phy_test_write_code 0x00014a8c Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_write_code) + i.drv_uart_abort_recv 0x00014ab4 Section 0 drv_uart.o(i.drv_uart_abort_recv) + i.drv_uart_abort_send 0x00014ae8 Section 0 drv_uart.o(i.drv_uart_abort_send) + i.drv_uart_config_int 0x00014b1c Section 0 drv_uart.o(i.drv_uart_config_int) + i.drv_uart_enable_clk 0x00014b30 Section 0 drv_uart.o(i.drv_uart_enable_clk) + drv_uart_enable_clk 0x00014b31 Thumb Code 24 drv_uart.o(i.drv_uart_enable_clk) + i.drv_uart_enable_int 0x00014b48 Section 0 drv_uart.o(i.drv_uart_enable_int) + i.drv_uart_get_instance 0x00014ba4 Section 0 drv_uart.o(i.drv_uart_get_instance) + i.drv_uart_init 0x00014bcc Section 0 drv_uart.o(i.drv_uart_init) + i.drv_uart_int_trans_handle 0x00014c9c Section 0 drv_uart.o(i.drv_uart_int_trans_handle) + drv_uart_int_trans_handle 0x00014c9d Thumb Code 54 drv_uart.o(i.drv_uart_int_trans_handle) + i.drv_uart_reset_rx_fifo 0x00014cd8 Section 0 drv_uart.o(i.drv_uart_reset_rx_fifo) + i.drv_uart_reset_tx_fifo 0x00014cf4 Section 0 drv_uart.o(i.drv_uart_reset_tx_fifo) + i.drv_uart_send_blocking 0x00014d10 Section 0 drv_uart.o(i.drv_uart_send_blocking) + i.drv_uart_set_baud_rate 0x00014d2a Section 0 drv_uart.o(i.drv_uart_set_baud_rate) + i.drv_uart_trans_create_handle 0x00014d80 Section 0 drv_uart.o(i.drv_uart_trans_create_handle) + i.drv_vidc_clear_irq 0x00014dcc Section 0 drv_vidc.o(i.drv_vidc_clear_irq) + i.drv_vidc_enable 0x00014ddc Section 0 drv_vidc.o(i.drv_vidc_enable) + i.drv_vidc_enable_irq 0x00014dfc Section 0 drv_vidc.o(i.drv_vidc_enable_irq) + i.drv_vidc_get_int_source 0x00014e3c Section 0 drv_vidc.o(i.drv_vidc_get_int_source) + i.drv_vidc_get_irq_status 0x00014e68 Section 0 drv_vidc.o(i.drv_vidc_get_irq_status) + i.drv_vidc_init_module_enable 0x00014e80 Section 0 drv_vidc.o(i.drv_vidc_init_module_enable) + i.drv_vidc_register_callback 0x00014eac Section 0 drv_vidc.o(i.drv_vidc_register_callback) + i.drv_vidc_reset 0x00014eb8 Section 0 drv_vidc.o(i.drv_vidc_reset) + i.drv_vidc_set_circ_mode_enable 0x00014ec4 Section 0 drv_vidc.o(i.drv_vidc_set_circ_mode_enable) + i.drv_vidc_set_dither_config 0x00014ee0 Section 0 drv_vidc.o(i.drv_vidc_set_dither_config) + i.drv_vidc_set_dst_parameter 0x00014f18 Section 0 drv_vidc.o(i.drv_vidc_set_dst_parameter) + i.drv_vidc_set_honly_hcoef0 0x00014f74 Section 0 drv_vidc.o(i.drv_vidc_set_honly_hcoef0) + i.drv_vidc_set_honly_hinitb 0x00014f80 Section 0 drv_vidc.o(i.drv_vidc_set_honly_hinitb) + i.drv_vidc_set_honly_hinitr 0x00014fac Section 0 drv_vidc.o(i.drv_vidc_set_honly_hinitr) + i.drv_vidc_set_irqen 0x00014fdc Section 0 drv_vidc.o(i.drv_vidc_set_irqen) + i.drv_vidc_set_mirror 0x00014ff8 Section 0 drv_vidc.o(i.drv_vidc_set_mirror) + i.drv_vidc_set_pentile_swap 0x0001500c Section 0 drv_vidc.o(i.drv_vidc_set_pentile_swap) + i.drv_vidc_set_pu_ctrl 0x00015028 Section 0 drv_vidc.o(i.drv_vidc_set_pu_ctrl) + i.drv_vidc_set_rotation 0x00015034 Section 0 drv_vidc.o(i.drv_vidc_set_rotation) + i.drv_vidc_set_scld_hcoef0 0x0001504c Section 0 drv_vidc.o(i.drv_vidc_set_scld_hcoef0) + i.drv_vidc_set_scld_hcoef1 0x00015058 Section 0 drv_vidc.o(i.drv_vidc_set_scld_hcoef1) + i.drv_vidc_set_scld_step 0x00015064 Section 0 drv_vidc.o(i.drv_vidc_set_scld_step) + i.drv_vidc_set_scld_vcoef0 0x00015078 Section 0 drv_vidc.o(i.drv_vidc_set_scld_vcoef0) + i.drv_vidc_set_scld_vcoef1 0x00015084 Section 0 drv_vidc.o(i.drv_vidc_set_scld_vcoef1) + i.drv_vidc_set_src_parameter 0x00015090 Section 0 drv_vidc.o(i.drv_vidc_set_src_parameter) + i.drv_vidc_set_vintp_config 0x000150b0 Section 0 drv_vidc.o(i.drv_vidc_set_vintp_config) + i.fputc 0x000150e8 Section 0 tau_log.o(i.fputc) + i.google_p8p_demo 0x0001511c Section 0 p8p_demo.o(i.google_p8p_demo) + i.ha_intl_fb_check_pu_size 0x0001517c Section 0 hal_internal_fb.o(i.ha_intl_fb_check_pu_size) + ha_intl_fb_check_pu_size 0x0001517d Thumb Code 58 hal_internal_fb.o(i.ha_intl_fb_check_pu_size) + i.hal_dsi_rx_ctrl_create_handle 0x000151bc Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) + i.hal_dsi_rx_ctrl_dcs_async_handler 0x000151fc Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) + i.hal_dsi_rx_ctrl_deinit 0x0001523c Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) + i.hal_dsi_rx_ctrl_get_max_ret_size 0x000152d0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) + i.hal_dsi_rx_ctrl_init 0x000152f0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) + i.hal_dsi_rx_ctrl_init_clk 0x0001539c Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) + hal_dsi_rx_ctrl_init_clk 0x0001539d Thumb Code 222 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) + i.hal_dsi_rx_ctrl_init_dsi_rx 0x0001549c Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) + hal_dsi_rx_ctrl_init_dsi_rx 0x0001549d Thumb Code 232 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) + i.hal_dsi_rx_ctrl_init_memc 0x000155a4 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) + hal_dsi_rx_ctrl_init_memc 0x000155a5 Thumb Code 294 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) + i.hal_dsi_rx_ctrl_init_rxbr 0x000156d0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) + hal_dsi_rx_ctrl_init_rxbr 0x000156d1 Thumb Code 314 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) + i.hal_dsi_rx_ctrl_init_vidc 0x00015818 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) + hal_dsi_rx_ctrl_init_vidc 0x00015819 Thumb Code 624 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) + i.hal_dsi_rx_ctrl_pre_init_pps 0x00015a98 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) + i.hal_dsi_rx_ctrl_send_ack_cmd 0x00015ad0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) + i.hal_dsi_rx_ctrl_set_ipi_cfg 0x00015bc0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) + hal_dsi_rx_ctrl_set_ipi_cfg 0x00015bc1 Thumb Code 48 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) + i.hal_dsi_rx_ctrl_start 0x00015bf0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) + i.hal_dsi_rx_ctrl_stop 0x00015c20 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) + i.hal_dsi_rx_ctrl_toggle_resolution 0x00015c50 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) + i.hal_dsi_tx_cmd_mode_cal_timing 0x00015c70 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) + hal_dsi_tx_cmd_mode_cal_timing 0x00015c71 Thumb Code 510 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing) + i.hal_dsi_tx_ctrl_create_handle 0x00015ef0 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) + i.hal_dsi_tx_ctrl_deinit 0x00015f28 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) + i.hal_dsi_tx_ctrl_gen_a_tear_signal 0x00015f9c Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) + i.hal_dsi_tx_ctrl_init 0x00015fc0 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) + i.hal_dsi_tx_ctrl_init_clk 0x0001603c Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) + hal_dsi_tx_ctrl_init_clk 0x0001603d Thumb Code 12 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) + i.hal_dsi_tx_ctrl_set_overwrite_rgb 0x0001604c Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb) + i.hal_dsi_tx_ctrl_set_tear_mode 0x00016054 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) + i.hal_dsi_tx_ctrl_start 0x00016060 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) + i.hal_dsi_tx_ctrl_stop 0x000160f0 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) + i.hal_dsi_tx_ctrl_write_array_cmd 0x00016128 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) + i.hal_dsi_tx_ctrl_write_cmd 0x0001621c Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) + i.hal_dsi_tx_init_cfg 0x000162ec Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) + hal_dsi_tx_init_cfg 0x000162ed Thumb Code 250 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg) + i.hal_dsi_tx_init_dpi_timing 0x000163f0 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) + hal_dsi_tx_init_dpi_timing 0x000163f1 Thumb Code 58 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing) + i.hal_dsi_tx_init_phy_cfg 0x00016434 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) + hal_dsi_tx_init_phy_cfg 0x00016435 Thumb Code 22 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) + i.hal_dsi_tx_init_timing 0x0001644a Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) + hal_dsi_tx_init_timing 0x0001644b Thumb Code 82 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing) + i.hal_dsi_tx_init_vid_timing 0x0001649c Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_vid_timing) + hal_dsi_tx_init_vid_timing 0x0001649d Thumb Code 70 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_vid_timing) + i.hal_dsi_tx_send_cmd 0x000164f0 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) + hal_dsi_tx_send_cmd 0x000164f1 Thumb Code 58 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) + i.hal_dsi_tx_timing_info_update 0x00016530 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_timing_info_update) + hal_dsi_tx_timing_info_update 0x00016531 Thumb Code 142 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_timing_info_update) + i.hal_dsi_tx_vid_mode_cal_timing 0x000165c4 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) + hal_dsi_tx_vid_mode_cal_timing 0x000165c5 Thumb Code 766 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) + i.hal_gpio_config_pad 0x000168d4 Section 0 hal_gpio.o(i.hal_gpio_config_pad) + i.hal_gpio_ctrl_eint 0x00016910 Section 0 hal_gpio.o(i.hal_gpio_ctrl_eint) + i.hal_gpio_init_eint 0x00016928 Section 0 hal_gpio.o(i.hal_gpio_init_eint) + i.hal_gpio_init_input 0x00016968 Section 0 hal_gpio.o(i.hal_gpio_init_input) + i.hal_gpio_init_output 0x0001697e Section 0 hal_gpio.o(i.hal_gpio_init_output) + i.hal_gpio_reg_eint_cb 0x0001699c Section 0 hal_gpio.o(i.hal_gpio_reg_eint_cb) + i.hal_gpio_set_ap_reset_int 0x000169b8 Section 0 hal_gpio.o(i.hal_gpio_set_ap_reset_int) + i.hal_gpio_set_mode 0x00016a08 Section 0 hal_gpio.o(i.hal_gpio_set_mode) + i.hal_gpio_set_output_data 0x00016a68 Section 0 hal_gpio.o(i.hal_gpio_set_output_data) + i.hal_internal_sync_get_hight_performan_mode 0x00016a70 Section 0 hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) + i.hal_internal_sync_input_resolution_change 0x00016a80 Section 0 hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) + i.hal_internal_sync_register_lcdc_cb 0x00016c34 Section 0 hal_internal_vsync.o(i.hal_internal_sync_register_lcdc_cb) + i.hal_internal_vsync_deinit 0x00016c40 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_deinit) + i.hal_internal_vsync_get_rx_state 0x00016c60 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_get_rx_state) + i.hal_internal_vsync_get_sync_line 0x00016c6c Section 0 hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) + i.hal_internal_vsync_get_tx_state 0x00016c80 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) + i.hal_internal_vsync_init_rx 0x00016c8c Section 0 hal_internal_vsync.o(i.hal_internal_vsync_init_rx) + i.hal_internal_vsync_init_tx 0x00016d74 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_init_tx) + i.hal_internal_vsync_set_rx_state 0x00016e3c Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) + i.hal_internal_vsync_set_tear_mode 0x00016e5c Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) + i.hal_internal_vsync_set_tx_state 0x00017048 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) + i.hal_intl_dcs_init_sw_fltr 0x000170a0 Section 0 hal_internal_dcs.o(i.hal_intl_dcs_init_sw_fltr) + i.hal_intl_dcs_rx_get_dcs_packet_data 0x0001710c Section 0 hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) + hal_intl_dcs_rx_get_dcs_packet_data 0x0001710d Thumb Code 782 hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data) + i.hal_intl_dcs_rx_receive_packet 0x0001753c Section 0 hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) + hal_intl_dcs_rx_receive_packet 0x0001753d Thumb Code 122 hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet) + i.hal_intl_dcs_rx_receive_pps 0x000175c4 Section 0 hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) + hal_intl_dcs_rx_receive_pps 0x000175c5 Thumb Code 266 hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps) + i.hal_intl_dcs_set_auto_hw_filter 0x00017738 Section 0 hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) + i.hal_intl_dcs_sw_filter_handle 0x000177c4 Section 0 hal_internal_dcs.o(i.hal_intl_dcs_sw_filter_handle) + hal_intl_dcs_sw_filter_handle 0x000177c5 Thumb Code 36 hal_internal_dcs.o(i.hal_intl_dcs_sw_filter_handle) + i.hal_intl_fb_cal_fb_info 0x000177f0 Section 0 hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) + i.hal_intl_fb_check_bandwidth 0x00017b08 Section 0 hal_internal_fb.o(i.hal_intl_fb_check_bandwidth) + hal_intl_fb_check_bandwidth 0x00017b09 Thumb Code 92 hal_internal_fb.o(i.hal_intl_fb_check_bandwidth) + i.hal_intl_fb_edge_resize 0x00017b6c Section 0 hal_internal_fb.o(i.hal_intl_fb_edge_resize) + hal_intl_fb_edge_resize 0x00017b6d Thumb Code 214 hal_internal_fb.o(i.hal_intl_fb_edge_resize) + i.hal_intl_fb_flow_control_adapter 0x00017c48 Section 0 hal_internal_fb.o(i.hal_intl_fb_flow_control_adapter) + hal_intl_fb_flow_control_adapter 0x00017c49 Thumb Code 110 hal_internal_fb.o(i.hal_intl_fb_flow_control_adapter) + i.hal_intl_fb_get_memc_flow_mode 0x00017cbc Section 0 hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) + i.hal_intl_fb_get_rx_fb_info 0x00017cc8 Section 0 hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) + i.hal_intl_fb_get_tx_fb_info 0x00017cd8 Section 0 hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info) + i.hal_intl_fb_get_user_flow 0x00017ce8 Section 0 hal_internal_fb.o(i.hal_intl_fb_get_user_flow) + i.hal_intl_svs_deinit_rx 0x00017cf4 Section 0 hal_internal_svs.o(i.hal_intl_svs_deinit_rx) + i.hal_intl_svs_deinit_tx 0x00017d1c Section 0 hal_internal_svs.o(i.hal_intl_svs_deinit_tx) + i.hal_intl_svs_handle 0x00017d2c Section 0 hal_internal_svs.o(i.hal_intl_svs_handle) + i.hal_intl_svs_init_rx 0x00017d50 Section 0 hal_internal_svs.o(i.hal_intl_svs_init_rx) + i.hal_intl_svs_init_tx 0x00017dd0 Section 0 hal_internal_svs.o(i.hal_intl_svs_init_tx) + i.hal_intl_svs_set_rx_vtt 0x00017de4 Section 0 hal_internal_svs.o(i.hal_intl_svs_set_rx_vtt) + i.hal_intl_svs_update_rxbr_clk 0x00017df0 Section 0 hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) + i.hal_lcdc_displayproc_config 0x00017e38 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config) + i.hal_lcdc_init_cfg 0x00017ea8 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) + hal_lcdc_init_cfg 0x00017ea9 Thumb Code 62 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) + i.hal_lcdc_init_clk 0x00017ee6 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) + hal_lcdc_init_clk 0x00017ee7 Thumb Code 112 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) + i.hal_lcdc_postproc_config 0x00017f58 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) + i.hal_lcdc_start 0x00018080 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_start) + hal_lcdc_start 0x00018081 Thumb Code 36 hal_dsi_tx_ctrl.o(i.hal_lcdc_start) + i.hal_lcdc_timinggen_config 0x000180a4 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) + hal_lcdc_timinggen_config 0x000180a5 Thumb Code 60 hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config) + i.hal_lcdc_upscaler_config 0x000180e0 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) + i.hal_nonshadow_func_update 0x000181c0 Section 0 hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) + i.hal_pwr_enter_deep_sleep_mode 0x0001827c Section 0 hal_pwr.o(i.hal_pwr_enter_deep_sleep_mode) + i.hal_pwr_enter_normal_sleep_mode 0x000182a6 Section 0 hal_pwr.o(i.hal_pwr_enter_normal_sleep_mode) + i.hal_pwr_enter_stop_sleep_mode 0x000182b0 Section 0 hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode) + i.hal_pwr_exit_sleep_mode 0x00018314 Section 0 hal_pwr.o(i.hal_pwr_exit_sleep_mode) + i.hal_pwr_get_vcc_power_ready 0x0001831e Section 0 hal_pwr.o(i.hal_pwr_get_vcc_power_ready) + i.hal_pwr_set_main_power 0x00018326 Section 0 hal_pwr.o(i.hal_pwr_set_main_power) + i.hal_pwr_set_sleep_mode_power 0x0001832e Section 0 hal_pwr.o(i.hal_pwr_set_sleep_mode_power) + i.hal_pwr_set_stop_sleep_wakeup_pin 0x00018338 Section 0 hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) + i.hal_swire_deinit 0x0001839c Section 0 hal_swire.o(i.hal_swire_deinit) + i.hal_swire_enable 0x000183dc Section 0 hal_swire.o(i.hal_swire_enable) + i.hal_swire_init 0x00018438 Section 0 hal_swire.o(i.hal_swire_init) + i.hal_swire_set_pulse 0x00018490 Section 0 hal_swire.o(i.hal_swire_set_pulse) + i.hal_swire_set_timer 0x000184b4 Section 0 hal_swire.o(i.hal_swire_set_timer) + i.hal_system_init 0x000184f4 Section 0 hal_system.o(i.hal_system_init) + i.hal_system_updata_sysclk 0x000185d8 Section 0 hal_system.o(i.hal_system_updata_sysclk) + i.hal_timer_deinit 0x00018628 Section 0 hal_timer.o(i.hal_timer_deinit) + i.hal_timer_init 0x00018658 Section 0 hal_timer.o(i.hal_timer_init) + i.hal_timer_set_repeat 0x00018674 Section 0 hal_timer.o(i.hal_timer_set_repeat) + i.hal_tx_frame_rate_adjust 0x0001867c Section 0 hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) + hal_tx_frame_rate_adjust 0x0001867d Thumb Code 44 hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) + i.hal_uart_init 0x000186ac Section 0 hal_uart.o(i.hal_uart_init) + i.hal_uart_send_blocking 0x00018740 Section 0 hal_uart.o(i.hal_uart_send_blocking) + i.hal_vsync_func_update 0x0001875c Section 0 hal_dsi_tx_ctrl.o(i.hal_vsync_func_update) + i.hal_vsync_reset_lcdc_scaler 0x00018774 Section 0 hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) + i.main 0x00018854 Section 0 main.o(i.main) + i.pps_update_handle 0x00018894 Section 0 p8p_demo.o(i.pps_update_handle) + pps_update_handle 0x00018895 Thumb Code 110 p8p_demo.o(i.pps_update_handle) + i.rxbr_irq1_callback 0x00018910 Section 0 hal_internal_vsync.o(i.rxbr_irq1_callback) + rxbr_irq1_callback 0x00018911 Thumb Code 496 hal_internal_vsync.o(i.rxbr_irq1_callback) + i.send_panel_init_code 0x00018c04 Section 0 p8p_demo.o(i.send_panel_init_code) + send_panel_init_code 0x00018c05 Thumb Code 58 p8p_demo.o(i.send_panel_init_code) + i.soft_double_buffer_update 0x00018c40 Section 0 hal_internal_vsync.o(i.soft_double_buffer_update) + soft_double_buffer_update 0x00018c41 Thumb Code 56 hal_internal_vsync.o(i.soft_double_buffer_update) + i.soft_gen_te 0x00018c84 Section 0 hal_internal_vsync.o(i.soft_gen_te) + soft_gen_te 0x00018c85 Thumb Code 86 hal_internal_vsync.o(i.soft_gen_te) + i.soft_gen_te_double_buffer 0x00018cf0 Section 0 hal_internal_vsync.o(i.soft_gen_te_double_buffer) + soft_gen_te_double_buffer 0x00018cf1 Thumb Code 202 hal_internal_vsync.o(i.soft_gen_te_double_buffer) + i.soft_pro_motion_init 0x00018dd0 Section 0 hal_internal_vsync.o(i.soft_pro_motion_init) + soft_pro_motion_init 0x00018dd1 Thumb Code 46 hal_internal_vsync.o(i.soft_pro_motion_init) + i.soft_tear_adjust_line 0x00018e08 Section 0 hal_internal_vsync.o(i.soft_tear_adjust_line) + soft_tear_adjust_line 0x00018e09 Thumb Code 26 hal_internal_vsync.o(i.soft_tear_adjust_line) + i.stop_sleep_cb 0x00018e2c Section 0 hal_pwr.o(i.stop_sleep_cb) + stop_sleep_cb 0x00018e2d Thumb Code 18 hal_pwr.o(i.stop_sleep_cb) + i.svs_direct_mode_setting 0x00018e44 Section 0 hal_internal_svs.o(i.svs_direct_mode_setting) + svs_direct_mode_setting 0x00018e45 Thumb Code 154 hal_internal_svs.o(i.svs_direct_mode_setting) + i.svs_get_rel_intv 0x00018ef0 Section 0 hal_internal_svs.o(i.svs_get_rel_intv) + svs_get_rel_intv 0x00018ef1 Thumb Code 20 hal_internal_svs.o(i.svs_get_rel_intv) + i.svs_sync_handle 0x00018f0c Section 0 hal_internal_svs.o(i.svs_sync_handle) + svs_sync_handle 0x00018f0d Thumb Code 158 hal_internal_svs.o(i.svs_sync_handle) + i.svs_wait_fr_stab 0x00018fbc Section 0 hal_internal_svs.o(i.svs_wait_fr_stab) + svs_wait_fr_stab 0x00018fbd Thumb Code 148 hal_internal_svs.o(i.svs_wait_fr_stab) + i.svs_wait_start 0x00019088 Section 0 hal_internal_svs.o(i.svs_wait_start) + svs_wait_start 0x00019089 Thumb Code 250 hal_internal_svs.o(i.svs_wait_start) + i.tau_log_init 0x00019194 Section 0 tau_log.o(i.tau_log_init) + i.tau_log_printf 0x000191c8 Section 0 tau_log.o(i.tau_log_printf) + i.tau_log_push_log 0x0001924c Section 0 tau_log.o(i.tau_log_push_log) + i.vidc_callback 0x000192c4 Section 0 hal_internal_vsync.o(i.vidc_callback) + vidc_callback 0x000192c5 Thumb Code 150 hal_internal_vsync.o(i.vidc_callback) + i.vpre_err_reset 0x00019378 Section 0 hal_internal_vsync.o(i.vpre_err_reset) + vpre_err_reset 0x00019379 Thumb Code 254 hal_internal_vsync.o(i.vpre_err_reset) + .constdata 0x00019490 Section 8380 p8p_demo.o(.constdata) + g_cus_rx_dcs_execute_table 0x00019490 Data 96 p8p_demo.o(.constdata) + .constdata 0x0001b54c Section 40 hal_dsi_rx_ctrl.o(.constdata) + .constdata 0x0001b574 Section 28 hal_dsi_tx_ctrl.o(.constdata) + .constdata 0x0001b590 Section 182 hal_gpio.o(.constdata) + s_gpio_map 0x0001b590 Data 104 hal_gpio.o(.constdata) + s_gpio_perf 0x0001b5f8 Data 78 hal_gpio.o(.constdata) + .constdata 0x0001b648 Section 48 hal_uart.o(.constdata) + .constdata 0x0001b678 Section 16 drv_uart.o(.constdata) + .conststring 0x0001b688 Section 66 hal_dsi_rx_ctrl.o(.conststring) + .conststring 0x0001b6cc Section 144 hal_internal_vsync.o(.conststring) + .conststring 0x0001b75c Section 70 hal_internal_dcs.o(.conststring) + .data 0x00070000 Section 287 p8p_demo.o(.data) + g_rx_ctrl_handle 0x00070000 Data 4 p8p_demo.o(.data) + g_tx_ctrl_handle 0x00070004 Data 4 p8p_demo.o(.data) + panel_display_done 0x00070008 Data 1 p8p_demo.o(.data) + sg_system_resume 0x00070009 Data 1 p8p_demo.o(.data) + sg_system_suspend 0x0007000a Data 1 p8p_demo.o(.data) + sg_exit_idle_mode_flag 0x0007000b Data 1 p8p_demo.o(.data) + g_resolution_change 0x0007000c Data 1 p8p_demo.o(.data) + pps_renew_flag 0x00070010 Data 4 p8p_demo.o(.data) + pwr_rst_flag 0x00070014 Data 4 p8p_demo.o(.data) + reg53_E8_fg 0x0007011e Data 1 p8p_demo.o(.data) + .data 0x00070120 Section 48 hal_dsi_rx_ctrl.o(.data) + g_hw_auto_filter 0x00070120 Data 1 hal_dsi_rx_ctrl.o(.data) + g_crc_check_enable 0x00070121 Data 1 hal_dsi_rx_ctrl.o(.data) + g_esc_clk 0x00070124 Data 4 hal_dsi_rx_ctrl.o(.data) + g_before_draw_col 0x00070128 Data 4 hal_dsi_rx_ctrl.o(.data) + g_before_draw_page 0x0007012c Data 4 hal_dsi_rx_ctrl.o(.data) + pre_step 0x00070130 Data 4 hal_dsi_rx_ctrl.o(.data) + pre_cmd_filter 0x00070134 Data 4 hal_dsi_rx_ctrl.o(.data) + pre_x 0x00070138 Data 4 hal_dsi_rx_ctrl.o(.data) + pre_y 0x0007013c Data 4 hal_dsi_rx_ctrl.o(.data) + pre_value 0x00070140 Data 4 hal_dsi_rx_ctrl.o(.data) + pre_x 0x00070144 Data 4 hal_dsi_rx_ctrl.o(.data) + pre_y 0x00070148 Data 4 hal_dsi_rx_ctrl.o(.data) + pre_value 0x0007014c Data 4 hal_dsi_rx_ctrl.o(.data) + .data 0x00070150 Section 92 hal_dsi_tx_ctrl.o(.data) + sg_bta_vsync_flag 0x00070150 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_vsync_flag 0x00070151 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_enter_sleep_cmd 0x00070152 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_fldc_cg_mode 0x00070153 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_bypass_scl_fir 0x00070154 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_honly_bypass_fir 0x00070155 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_bypass_bcs 0x00070156 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_bypass_enhc 0x00070157 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_bypass_edge_dect 0x00070158 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_bypass_edge_enh 0x00070159 Data 1 hal_dsi_tx_ctrl.o(.data) + sg_bypass_dith 0x0007015a Data 1 hal_dsi_tx_ctrl.o(.data) + sg_dith_judge 0x0007015b Data 1 hal_dsi_tx_ctrl.o(.data) + sg_endianness 0x0007015c Data 1 hal_dsi_tx_ctrl.o(.data) + sg_test_pattern_en 0x0007015d Data 1 hal_dsi_tx_ctrl.o(.data) + sg_dith_judge_thr 0x00070160 Data 4 hal_dsi_tx_ctrl.o(.data) + sg_ccm_para 0x00070164 Data 36 hal_dsi_tx_ctrl.o(.data) + sg_honly_para 0x00070188 Data 36 hal_dsi_tx_ctrl.o(.data) + .data 0x000701ac Section 2 hal_swire.o(.data) + sg_swire_timer 0x000701ac Data 1 hal_swire.o(.data) + sg_swire_repeat 0x000701ad Data 1 hal_swire.o(.data) + .data 0x000701b0 Section 8 hal_pwr.o(.data) + sg_wake_up_io 0x000701b0 Data 1 hal_pwr.o(.data) + sg_stop_sleep_wakeup_int 0x000701b4 Data 4 hal_pwr.o(.data) + .data 0x000701b8 Section 1 tau_log.o(.data) + g_log_port 0x000701b8 Data 1 tau_log.o(.data) + .data 0x000701bc Section 24 hal_uart.o(.data) + sg_dma_callback 0x000701cc Data 4 hal_uart.o(.data) + sg_user_data 0x000701d0 Data 4 hal_uart.o(.data) + .data 0x000701d4 Section 16 hal_internal_vsync.o(.data) + s_te_refine_mode 0x000701d4 Data 1 hal_internal_vsync.o(.data) + .data 0x000701e4 Section 36 hal_internal_dcs.o(.data) + g_imm_packet 0x000701e4 Data 24 hal_internal_dcs.o(.data) + g_cus_rx_write_cmd_handle 0x000701fc Data 12 hal_internal_dcs.o(.data) + .data 0x00070208 Section 12 drv_common.o(.data) + s_my_tick 0x00070208 Data 4 drv_common.o(.data) + .data 0x00070214 Section 1 drv_common.o(.data) + .data 0x00070218 Section 4 drv_gpio.o(.data) + g_ap_reset_cb 0x00070218 Data 4 drv_gpio.o(.data) + .data 0x0007021c Section 4 drv_swire.o(.data) + sg_drv_swire_cb 0x0007021c Data 4 drv_swire.o(.data) + .data 0x00070220 Section 80 drv_timer.o(.data) + sg_timer_info 0x00070220 Data 80 drv_timer.o(.data) + .data 0x00070270 Section 4 drv_se.o(.data) + chip_info 0x00070270 Data 4 drv_se.o(.data) + .data 0x00070274 Section 1 drv_dsi_rx.o(.data) + sg_rx_drv_level 0x00070274 Data 1 drv_dsi_rx.o(.data) + .data 0x00070278 Section 8 drv_rxbr.o(.data) + .data 0x00070280 Section 4 drv_vidc.o(.data) + .data 0x00070284 Section 400 drv_dma.o(.data) + sg_dma_handle 0x00070284 Data 256 drv_dma.o(.data) + .data 0x00070414 Section 4 stdout.o(.data) + .bss 0x00070418 Section 208 hal_dsi_rx_ctrl.o(.bss) + g_rx_ctrl_handle 0x00070418 Data 208 hal_dsi_rx_ctrl.o(.bss) + .bss 0x000704e8 Section 184 hal_dsi_tx_ctrl.o(.bss) + g_tx_ctrl_handle 0x000704e8 Data 92 hal_dsi_tx_ctrl.o(.bss) + sg_dsi_tx_param 0x00070544 Data 92 hal_dsi_tx_ctrl.o(.bss) + .bss 0x000705a0 Section 256 tau_log.o(.bss) + g_log_buf 0x000705a0 Data 256 tau_log.o(.bss) + .bss 0x000706a0 Section 68 hal_internal_vsync.o(.bss) + .bss 0x000706e4 Section 2048 hal_internal_dcs.o(.bss) + .bss 0x00070ee4 Section 255 hal_internal_dcs.o(.bss) + g_imm_buffer 0x00070ee4 Data 255 hal_internal_dcs.o(.bss) + .bss 0x00070fe4 Section 68 hal_internal_fb.o(.bss) + .bss 0x00071028 Section 68 hal_internal_svs.o(.bss) + sg_sys_handler 0x00071028 Data 68 hal_internal_svs.o(.bss) + .bss 0x0007106c Section 64 drv_gpio.o(.bss) + s_gpio_cb 0x0007106c Data 64 drv_gpio.o(.bss) + .bss 0x000710ac Section 4204 dcs_packet_fifo.o(.bss) + .bss 0x00072118 Section 16 drv_dma.o(.bss) + sg_dma_int_list 0x00072118 Data 16 drv_dma.o(.bss) + .bss 0x00072128 Section 96 drv_uart.o(.bss) + sg_uart_userdata 0x00072128 Data 96 drv_uart.o(.bss) + STACK 0x00072188 Section 4096 startup_armcm0.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$IEEEJ$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE + _printf_a 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_c 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_charcount 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_d 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_e 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_f 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_flags 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_fp_dec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_fp_hex 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_g 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_i 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_int_dec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_l 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_lc 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_ll 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_lld 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_lli 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_llo 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_llu 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_llx 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_longlong_dec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_longlong_hex 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_longlong_oct 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_ls 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_mbtowc 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_n 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_o 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_p 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_percent 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_pre_padding 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_return_value 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_s 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_sizespec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_str 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_truncate_signed 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_truncate_unsigned 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_u 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_wc 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_wctomb 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_widthprec 0x00000000 Number 0 stubs.o ABSOLUTE + _printf_x 0x00000000 Number 0 stubs.o ABSOLUTE + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _microlib_exit - Undefined Weak Reference + __Vectors_Size 0x000000c0 Number 0 startup_armcm0.o ABSOLUTE + __Vectors 0x00010000 Data 4 startup_armcm0.o(RESET) + __Vectors_End 0x000100c0 Data 0 startup_armcm0.o(RESET) + __main 0x000100c1 Thumb Code 0 entry.o(.ARM.Collect$$$$00000000) + _main_stk 0x000100c1 Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001) + _main_scatterload 0x000100c5 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + __main_after_scatterload 0x000100c9 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + _main_clock 0x000100c9 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008) + _main_cpp_init 0x000100c9 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A) + _main_init 0x000100c9 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B) + __rt_final_cpp 0x000100d1 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000D) + __rt_final_exit 0x000100d1 Thumb Code 0 entry11a.o(.ARM.Collect$$$$0000000F) + Reset_Handler 0x000100d5 Thumb Code 28 startup_armcm0.o(.text) + NMI_Handler 0x000100f1 Thumb Code 2 startup_armcm0.o(.text) + SVC_Handler 0x000100f5 Thumb Code 2 startup_armcm0.o(.text) + PendSV_Handler 0x000100f7 Thumb Code 2 startup_armcm0.o(.text) + FLSCTRL_IRQn_Handler 0x00010107 Thumb Code 2 startup_armcm0.o(.text) + WDG_IRQn_Handler 0x00010113 Thumb Code 2 startup_armcm0.o(.text) + I2C0_IRQn_Handler 0x00010117 Thumb Code 2 startup_armcm0.o(.text) + I2C1_IRQn_Handler 0x00010119 Thumb Code 2 startup_armcm0.o(.text) + SPIS_IRQn_Handler 0x0001011b Thumb Code 2 startup_armcm0.o(.text) + SPIM_IRQn_Handler 0x0001011d Thumb Code 2 startup_armcm0.o(.text) + I2C2_IRQn_Handler 0x00010121 Thumb Code 2 startup_armcm0.o(.text) + OTP_IRQn_Handler 0x00010123 Thumb Code 2 startup_armcm0.o(.text) + PVD_IRQn_Handler 0x00010127 Thumb Code 2 startup_armcm0.o(.text) + __aeabi_uidiv 0x0001014d Thumb Code 0 uidiv.o(.text) + __aeabi_uidivmod 0x0001014d Thumb Code 44 uidiv.o(.text) + __aeabi_idiv 0x00010179 Thumb Code 0 idiv.o(.text) + __aeabi_idivmod 0x00010179 Thumb Code 40 idiv.o(.text) + __aeabi_memcpy 0x000101a1 Thumb Code 36 memcpya.o(.text) + __aeabi_memcpy4 0x000101a1 Thumb Code 0 memcpya.o(.text) + __aeabi_memcpy8 0x000101a1 Thumb Code 0 memcpya.o(.text) + __aeabi_memset 0x000101c5 Thumb Code 14 memseta.o(.text) + __aeabi_memset4 0x000101c5 Thumb Code 0 memseta.o(.text) + __aeabi_memset8 0x000101c5 Thumb Code 0 memseta.o(.text) + __aeabi_memclr 0x000101d3 Thumb Code 4 memseta.o(.text) + __aeabi_memclr4 0x000101d3 Thumb Code 0 memseta.o(.text) + __aeabi_memclr8 0x000101d3 Thumb Code 0 memseta.o(.text) + _memset$wrapper 0x000101d7 Thumb Code 18 memseta.o(.text) + strlen 0x000101e9 Thumb Code 14 strlen.o(.text) + memcmp 0x000101f7 Thumb Code 26 memcmp.o(.text) + __aeabi_fadd 0x00010211 Thumb Code 162 fadd.o(.text) + __aeabi_fsub 0x000102b3 Thumb Code 8 fadd.o(.text) + __aeabi_frsub 0x000102bb Thumb Code 8 fadd.o(.text) + __aeabi_fmul 0x000102c3 Thumb Code 122 fmul.o(.text) + __aeabi_fdiv 0x0001033d Thumb Code 124 fdiv.o(.text) + __ARM_scalbnf 0x000103b9 Thumb Code 24 fscalb.o(.text) + scalbnf 0x000103b9 Thumb Code 0 fscalb.o(.text) + __aeabi_dadd 0x000103d1 Thumb Code 328 dadd.o(.text) + __aeabi_dsub 0x00010519 Thumb Code 12 dadd.o(.text) + __aeabi_drsub 0x00010525 Thumb Code 12 dadd.o(.text) + __aeabi_dmul 0x00010535 Thumb Code 202 dmul.o(.text) + __aeabi_ui2f 0x00010605 Thumb Code 14 ffltui.o(.text) + __aeabi_ui2d 0x00010615 Thumb Code 24 dfltui.o(.text) + __aeabi_f2uiz 0x00010631 Thumb Code 40 ffixui.o(.text) + __aeabi_d2uiz 0x00010659 Thumb Code 50 dfixui.o(.text) + __aeabi_f2d 0x00010695 Thumb Code 40 f2d.o(.text) + __aeabi_d2f 0x000106bd Thumb Code 56 d2f.o(.text) + __aeabi_cfcmpeq 0x000106f5 Thumb Code 0 cfcmple.o(.text) + __aeabi_cfcmple 0x000106f5 Thumb Code 20 cfcmple.o(.text) + __aeabi_cfrcmple 0x00010709 Thumb Code 20 cfrcmple.o(.text) + __aeabi_uldivmod 0x0001071d Thumb Code 96 uldiv.o(.text) + __aeabi_llsl 0x0001077d Thumb Code 32 llshl.o(.text) + _ll_shift_l 0x0001077d Thumb Code 0 llshl.o(.text) + __aeabi_llsr 0x0001079d Thumb Code 34 llushr.o(.text) + _ll_ushift_r 0x0001079d Thumb Code 0 llushr.o(.text) + __aeabi_lasr 0x000107bf Thumb Code 38 llsshr.o(.text) + _ll_sshift_r 0x000107bf Thumb Code 0 llsshr.o(.text) + __I$use$fp 0x000107e5 Thumb Code 0 iusefp.o(.text) + _float_round 0x000107e5 Thumb Code 16 fepilogue.o(.text) + _float_epilogue 0x000107f5 Thumb Code 114 fepilogue.o(.text) + _double_round 0x00010867 Thumb Code 26 depilogue.o(.text) + _double_epilogue 0x00010881 Thumb Code 164 depilogue.o(.text) + __aeabi_ddiv 0x00010925 Thumb Code 234 ddiv.o(.text) + __aeabi_d2ulz 0x00010a15 Thumb Code 54 dfixul.o(.text) + __aeabi_cdrcmple 0x00010a55 Thumb Code 38 cdrcmple.o(.text) + __scatterload 0x00010a7d Thumb Code 28 init.o(.text) + __scatterload_rt2 0x00010a7d Thumb Code 0 init.o(.text) + __decompress 0x00010aa1 Thumb Code 0 __dczerorl2.o(.text) + __decompress1 0x00010aa1 Thumb Code 86 __dczerorl2.o(.text) + AP_NRESET_IRQn_Handler 0x00010af9 Thumb Code 22 drv_gpio.o(i.AP_NRESET_IRQn_Handler) + DMA_IRQn_Handler 0x00010b15 Thumb Code 78 drv_dma.o(i.DMA_IRQn_Handler) + EXTI_INT0_IRQn_Handler 0x00010b71 Thumb Code 10 drv_gpio.o(i.EXTI_INT0_IRQn_Handler) + EXTI_INT1_IRQn_Handler 0x00010b7b Thumb Code 10 drv_gpio.o(i.EXTI_INT1_IRQn_Handler) + EXTI_INT2_IRQn_Handler 0x00010b85 Thumb Code 10 drv_gpio.o(i.EXTI_INT2_IRQn_Handler) + EXTI_INT3_IRQn_Handler 0x00010b8f Thumb Code 10 drv_gpio.o(i.EXTI_INT3_IRQn_Handler) + EXTI_INT4_IRQn_Handler 0x00010b99 Thumb Code 10 drv_gpio.o(i.EXTI_INT4_IRQn_Handler) + EXTI_INT5_IRQn_Handler 0x00010ba3 Thumb Code 10 drv_gpio.o(i.EXTI_INT5_IRQn_Handler) + EXTI_INT6_IRQn_Handler 0x00010bad Thumb Code 10 drv_gpio.o(i.EXTI_INT6_IRQn_Handler) + EXTI_INT7_IRQn_Handler 0x00010bb7 Thumb Code 10 drv_gpio.o(i.EXTI_INT7_IRQn_Handler) + HardFault_Handler 0x00010bc1 Thumb Code 14 drv_common.o(i.HardFault_Handler) + LCDC_IRQn_Handler 0x00010c09 Thumb Code 118 hal_internal_vsync.o(i.LCDC_IRQn_Handler) + MEMC_IRQn_Handler 0x00010d09 Thumb Code 154 drv_memc.o(i.MEMC_IRQn_Handler) + MIPI_TX_IRQn_Handler 0x00010da5 Thumb Code 70 drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler) + SWIRE_IRQn_Handler 0x00010e5d Thumb Code 38 drv_swire.o(i.SWIRE_IRQn_Handler) + SysTick_Handler 0x00010e8d Thumb Code 20 drv_common.o(i.SysTick_Handler) + TIMER0_IRQn_Handler 0x00010ea5 Thumb Code 10 drv_timer.o(i.TIMER0_IRQn_Handler) + TIMER1_IRQn_Handler 0x00010eaf Thumb Code 10 drv_timer.o(i.TIMER1_IRQn_Handler) + TIMER2_IRQn_Handler 0x00010eb9 Thumb Code 10 drv_timer.o(i.TIMER2_IRQn_Handler) + TIMER3_IRQn_Handler 0x00010ec3 Thumb Code 10 drv_timer.o(i.TIMER3_IRQn_Handler) + VIDC_IRQn_Handler 0x00010ecd Thumb Code 22 drv_vidc.o(i.VIDC_IRQn_Handler) + VPRE1_IRQn_Handler 0x00010ee9 Thumb Code 22 drv_rxbr.o(i.VPRE1_IRQn_Handler) + VPRE_IRQn_Handler 0x00010f05 Thumb Code 104 hal_internal_dcs.o(i.VPRE_IRQn_Handler) + __0printf 0x00010f71 Thumb Code 24 printfa.o(i.__0printf) + __1printf 0x00010f71 Thumb Code 0 printfa.o(i.__0printf) + __2printf 0x00010f71 Thumb Code 0 printfa.o(i.__0printf) + __c89printf 0x00010f71 Thumb Code 0 printfa.o(i.__0printf) + printf 0x00010f71 Thumb Code 0 printfa.o(i.__0printf) + __0vsprintf 0x00010f91 Thumb Code 30 printfa.o(i.__0vsprintf) + __1vsprintf 0x00010f91 Thumb Code 0 printfa.o(i.__0vsprintf) + __2vsprintf 0x00010f91 Thumb Code 0 printfa.o(i.__0vsprintf) + __c89vsprintf 0x00010f91 Thumb Code 0 printfa.o(i.__0vsprintf) + vsprintf 0x00010f91 Thumb Code 0 printfa.o(i.__0vsprintf) + __ARM_clz 0x00010fb5 Thumb Code 46 depilogue.o(i.__ARM_clz) + __ARM_common_switch8 0x00010fe3 Thumb Code 26 hal_dsi_rx_ctrl.o(i.__ARM_common_switch8) + __scatterload_null 0x00010ffd Thumb Code 2 handlers.o(i.__scatterload_null) + s_RAM_CK 0x00011000 Data 28 drv_common.o(.ARM.__at_0x11000) + g_tau_log 0x0001101c Data 16 tau_log.o(.ARM.__at_0x1101C) + sg_pq_para 0x0001102c Data 22 hal_dsi_tx_ctrl.o(.ARM.__at_0x1102C) + MIPI_RX_IRQn_Handler 0x00011045 Thumb Code 354 drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler) + UART_IRQn_Handler 0x000113a9 Thumb Code 364 drv_uart.o(i.UART_IRQn_Handler) + __scatterload_copy 0x00011561 Thumb Code 14 handlers.o(i.__scatterload_copy) + __scatterload_zeroinit 0x0001156f Thumb Code 14 handlers.o(i.__scatterload_zeroinit) + app_display_init 0x000122bb Thumb Code 44 p8p_demo.o(i.app_display_init) + app_gpio_init 0x000122e9 Thumb Code 22 p8p_demo.o(i.app_gpio_init) + board_Init 0x0001286d Thumb Code 20 board.o(i.board_Init) + ceil 0x00012885 Thumb Code 180 ceil.o(i.ceil) + dcs_packet_fifo_alloc 0x00012a01 Thumb Code 80 dcs_packet_fifo.o(i.dcs_packet_fifo_alloc) + dcs_packet_fifo_init 0x00012a59 Thumb Code 18 dcs_packet_fifo.o(i.dcs_packet_fifo_init) + dcs_packet_free_fifo_header 0x00012a71 Thumb Code 60 dcs_packet_fifo.o(i.dcs_packet_free_fifo_header) + dcs_packet_get_fifo_header 0x00012ab5 Thumb Code 26 dcs_packet_fifo.o(i.dcs_packet_get_fifo_header) + delayMs 0x00012ad9 Thumb Code 24 tau_delay.o(i.delayMs) + delayUs 0x00012af1 Thumb Code 40 tau_delay.o(i.delayUs) + drv_common_system_init 0x00012b1d Thumb Code 8 drv_common.o(i.drv_common_system_init) + drv_crgu_enable_clock 0x00012b25 Thumb Code 54 drv_crgu.o(i.drv_crgu_enable_clock) + drv_crgu_get_rxbr_clk 0x00012b61 Thumb Code 70 drv_crgu.o(i.drv_crgu_get_rxbr_clk) + drv_crgu_reset_modules 0x00012bc9 Thumb Code 10 drv_crgu.o(i.drv_crgu_reset_modules) + drv_crgu_set_ahb_clk 0x00012bd9 Thumb Code 34 drv_crgu.o(i.drv_crgu_set_ahb_clk) + drv_crgu_set_clock_div 0x00012c01 Thumb Code 12 drv_crgu.o(i.drv_crgu_set_clock_div) + drv_crgu_set_dpi_clk 0x00012c11 Thumb Code 54 drv_crgu.o(i.drv_crgu_set_dpi_clk) + drv_crgu_set_dsc_clk 0x00012c4d Thumb Code 52 drv_crgu.o(i.drv_crgu_set_dsc_clk) + drv_crgu_set_fb_clk 0x00012c85 Thumb Code 34 drv_crgu.o(i.drv_crgu_set_fb_clk) + drv_crgu_set_lcdc_clk 0x00012cad Thumb Code 36 drv_crgu.o(i.drv_crgu_set_lcdc_clk) + drv_crgu_set_reset 0x00012cd5 Thumb Code 20 drv_crgu.o(i.drv_crgu_set_reset) + drv_crgu_set_rxbr_clk 0x00012ced Thumb Code 34 drv_crgu.o(i.drv_crgu_set_rxbr_clk) + drv_crgu_set_vidc_clk 0x00012d15 Thumb Code 36 drv_crgu.o(i.drv_crgu_set_vidc_clk) + drv_dma_clear_status 0x00012d3d Thumb Code 20 drv_dma.o(i.drv_dma_clear_status) + drv_dsc_dec_disable 0x00012d69 Thumb Code 20 drv_dsc_dec.o(i.drv_dsc_dec_disable) + drv_dsc_dec_enable 0x00012d85 Thumb Code 44 drv_dsc_dec.o(i.drv_dsc_dec_enable) + drv_dsc_dec_get_nslc 0x00012dbd Thumb Code 22 drv_dsc_dec.o(i.drv_dsc_dec_get_nslc) + drv_dsc_dec_set_irqen 0x00012ddd Thumb Code 24 drv_dsc_dec.o(i.drv_dsc_dec_set_irqen) + drv_dsi_rx_calc_ipi_tx_delay 0x00012df9 Thumb Code 252 drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) + drv_dsi_rx_enable_irq 0x00012f05 Thumb Code 58 drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) + drv_dsi_rx_get_compression_en 0x00012fb1 Thumb Code 10 drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en) + drv_dsi_rx_get_ddi_crc_en 0x00012fc1 Thumb Code 10 drv_dsi_rx.o(i.drv_dsi_rx_get_ddi_crc_en) + drv_dsi_rx_get_max_ret_size 0x00012fd1 Thumb Code 8 drv_dsi_rx.o(i.drv_dsi_rx_get_max_ret_size) + drv_dsi_rx_power_up 0x00012fdd Thumb Code 14 drv_dsi_rx.o(i.drv_dsi_rx_power_up) + drv_dsi_rx_set_check_crc 0x00012ff5 Thumb Code 24 drv_dsi_rx.o(i.drv_dsi_rx_set_check_crc) + drv_dsi_rx_set_ctrl_cfg 0x00013011 Thumb Code 32 drv_dsi_rx.o(i.drv_dsi_rx_set_ctrl_cfg) + drv_dsi_rx_set_ddi_cfg 0x00013035 Thumb Code 10 drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) + drv_dsi_rx_set_ddi_crc_en 0x00013045 Thumb Code 24 drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_crc_en) + drv_dsi_rx_set_inten 0x00013061 Thumb Code 8 drv_dsi_rx.o(i.drv_dsi_rx_set_inten) + drv_dsi_rx_set_ipi_cfg 0x0001306d Thumb Code 12 drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_cfg) + drv_dsi_rx_set_ipi_ycbcr_frmt 0x0001307d Thumb Code 24 drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_ycbcr_frmt) + drv_dsi_rx_set_lane_swap 0x00013099 Thumb Code 16 drv_dsi_rx.o(i.drv_dsi_rx_set_lane_swap) + drv_dsi_rx_set_resp_cnt 0x000130ad Thumb Code 32 drv_dsi_rx.o(i.drv_dsi_rx_set_resp_cnt) + drv_dsi_rx_set_tear_resp_en 0x000130d1 Thumb Code 24 drv_dsi_rx.o(i.drv_dsi_rx_set_tear_resp_en) + drv_dsi_rx_set_up_phy 0x000130ed Thumb Code 224 drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) + drv_dsi_rx_shut_down 0x000131ed Thumb Code 14 drv_dsi_rx.o(i.drv_dsi_rx_shut_down) + drv_dsi_tx_command_header 0x00013205 Thumb Code 18 drv_dsi_tx.o(i.drv_dsi_tx_command_header) + drv_dsi_tx_command_mode_cfg 0x0001321d Thumb Code 82 drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg) + drv_dsi_tx_command_put_payload 0x00013275 Thumb Code 6 drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) + drv_dsi_tx_config_eotp 0x00013281 Thumb Code 26 drv_dsi_tx.o(i.drv_dsi_tx_config_eotp) + drv_dsi_tx_config_int 0x000132a1 Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_config_int) + drv_dsi_tx_dpi_lpcmd_time 0x000132ad Thumb Code 10 drv_dsi_tx.o(i.drv_dsi_tx_dpi_lpcmd_time) + drv_dsi_tx_dpi_mode 0x000132bd Thumb Code 12 drv_dsi_tx.o(i.drv_dsi_tx_dpi_mode) + drv_dsi_tx_dpi_polarity 0x000132cd Thumb Code 32 drv_dsi_tx.o(i.drv_dsi_tx_dpi_polarity) + drv_dsi_tx_edpi_cmd_size 0x000132f1 Thumb Code 6 drv_dsi_tx.o(i.drv_dsi_tx_edpi_cmd_size) + drv_dsi_tx_get_cmd_status 0x000132fd Thumb Code 6 drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) + drv_dsi_tx_mode 0x00013309 Thumb Code 6 drv_dsi_tx.o(i.drv_dsi_tx_mode) + drv_dsi_tx_phy_clock_lane_auto_lp 0x00013315 Thumb Code 24 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp) + drv_dsi_tx_phy_clock_lane_req_hs 0x00013331 Thumb Code 26 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs) + drv_dsi_tx_phy_lane_mode 0x00013351 Thumb Code 12 drv_dsi_tx.o(i.drv_dsi_tx_phy_lane_mode) + drv_dsi_tx_phy_status_ready 0x00013361 Thumb Code 100 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready) + drv_dsi_tx_phy_status_stopstate 0x000133c9 Thumb Code 62 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) + drv_dsi_tx_phy_test_setup 0x0001340d Thumb Code 314 drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) + drv_dsi_tx_phy_time_cfg 0x0001355d Thumb Code 28 drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg) + drv_dsi_tx_powerup 0x0001357d Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_powerup) + drv_dsi_tx_response_mode 0x00013589 Thumb Code 30 drv_dsi_tx.o(i.drv_dsi_tx_response_mode) + drv_dsi_tx_set_bta_ack 0x000135ad Thumb Code 24 drv_dsi_tx.o(i.drv_dsi_tx_set_bta_ack) + drv_dsi_tx_set_esc_div 0x000135c9 Thumb Code 14 drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) + drv_dsi_tx_set_int 0x000135dd Thumb Code 58 drv_dsi_tx.o(i.drv_dsi_tx_set_int) + drv_dsi_tx_set_time_out_div 0x0001361d Thumb Code 18 drv_dsi_tx.o(i.drv_dsi_tx_set_time_out_div) + drv_dsi_tx_set_video_chunk 0x00013635 Thumb Code 14 drv_dsi_tx.o(i.drv_dsi_tx_set_video_chunk) + drv_dsi_tx_set_video_timing 0x00013649 Thumb Code 30 drv_dsi_tx.o(i.drv_dsi_tx_set_video_timing) + drv_dsi_tx_shutdown 0x0001366d Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_shutdown) + drv_dsi_tx_timeout_cfg 0x00013679 Thumb Code 38 drv_dsi_tx.o(i.drv_dsi_tx_timeout_cfg) + drv_dsi_tx_video_mode_cfg 0x000136a5 Thumb Code 226 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_cfg) + drv_efuse_enter_inactive 0x0001378d Thumb Code 54 drv_efuse.o(i.drv_efuse_enter_inactive) + drv_efuse_int_enable 0x000137c3 Thumb Code 12 drv_efuse.o(i.drv_efuse_int_enable) + drv_efuse_read 0x000137cf Thumb Code 58 drv_efuse.o(i.drv_efuse_read) + drv_efuse_read_req 0x00013809 Thumb Code 24 drv_efuse.o(i.drv_efuse_read_req) + drv_gpio_register_ap_reset_callback 0x00013845 Thumb Code 6 drv_gpio.o(i.drv_gpio_register_ap_reset_callback) + drv_gpio_register_callback 0x00013851 Thumb Code 14 drv_gpio.o(i.drv_gpio_register_callback) + drv_gpio_set_int 0x00013865 Thumb Code 62 drv_gpio.o(i.drv_gpio_set_int) + drv_gpio_set_ioe 0x000138a9 Thumb Code 26 drv_gpio.o(i.drv_gpio_set_ioe) + drv_gpio_set_mode 0x000138c9 Thumb Code 16 drv_gpio.o(i.drv_gpio_set_mode) + drv_lcdc_bcsa_config 0x000138fd Thumb Code 30 drv_lcdc.o(i.drv_lcdc_bcsa_config) + drv_lcdc_cfg_int_frame 0x00013925 Thumb Code 34 drv_lcdc.o(i.drv_lcdc_cfg_int_frame) + drv_lcdc_cmd_start 0x00013969 Thumb Code 46 drv_lcdc.o(i.drv_lcdc_cmd_start) + drv_lcdc_config_acc_command_mode 0x0001399d Thumb Code 14 drv_lcdc.o(i.drv_lcdc_config_acc_command_mode) + drv_lcdc_config_int 0x000139b1 Thumb Code 50 drv_lcdc.o(i.drv_lcdc_config_int) + drv_lcdc_config_int_single 0x000139e9 Thumb Code 34 drv_lcdc.o(i.drv_lcdc_config_int_single) + drv_lcdc_config_overwrite_rgb 0x00013a11 Thumb Code 18 drv_lcdc.o(i.drv_lcdc_config_overwrite_rgb) + drv_lcdc_config_src_parameter 0x00013a29 Thumb Code 72 drv_lcdc.o(i.drv_lcdc_config_src_parameter) + drv_lcdc_crop_hact 0x00013a79 Thumb Code 10 drv_lcdc.o(i.drv_lcdc_crop_hact) + drv_lcdc_ctrl_flow 0x00013a89 Thumb Code 50 drv_lcdc.o(i.drv_lcdc_ctrl_flow) + drv_lcdc_dith_config 0x00013ac1 Thumb Code 40 drv_lcdc.o(i.drv_lcdc_dith_config) + drv_lcdc_edge_dect_config 0x00013af1 Thumb Code 50 drv_lcdc.o(i.drv_lcdc_edge_dect_config) + drv_lcdc_edge_enh_config 0x00013b2d Thumb Code 86 drv_lcdc.o(i.drv_lcdc_edge_enh_config) + drv_lcdc_enable_shadow_reg 0x00013b91 Thumb Code 32 drv_lcdc.o(i.drv_lcdc_enable_shadow_reg) + drv_lcdc_endianness_config 0x00013bb5 Thumb Code 24 drv_lcdc.o(i.drv_lcdc_endianness_config) + drv_lcdc_fc_config 0x00013bd1 Thumb Code 24 drv_lcdc.o(i.drv_lcdc_fc_config) + drv_lcdc_fldc_config 0x00013bf1 Thumb Code 32 drv_lcdc.o(i.drv_lcdc_fldc_config) + drv_lcdc_function_disable 0x00013c15 Thumb Code 30 drv_lcdc.o(i.drv_lcdc_function_disable) + drv_lcdc_function_enable 0x00013c39 Thumb Code 30 drv_lcdc.o(i.drv_lcdc_function_enable) + drv_lcdc_set_int 0x00013c5d Thumb Code 54 drv_lcdc.o(i.drv_lcdc_set_int) + drv_lcdc_set_prefetch 0x00013c99 Thumb Code 24 drv_lcdc.o(i.drv_lcdc_set_prefetch) + drv_lcdc_set_tear_line 0x00013cb5 Thumb Code 24 drv_lcdc.o(i.drv_lcdc_set_tear_line) + drv_lcdc_stop_display 0x00013cd1 Thumb Code 12 drv_lcdc.o(i.drv_lcdc_stop_display) + drv_lcdc_vid_hw_start 0x00013ce1 Thumb Code 56 drv_lcdc.o(i.drv_lcdc_vid_hw_start) + drv_lcdc_vintp_mode_config 0x00013d1d Thumb Code 18 drv_lcdc.o(i.drv_lcdc_vintp_mode_config) + drv_memc_clear_status 0x00013d35 Thumb Code 14 drv_memc.o(i.drv_memc_clear_status) + drv_memc_enable_irq 0x00013d49 Thumb Code 58 drv_memc.o(i.drv_memc_enable_irq) + drv_memc_gen_a_tear_signal 0x00013d89 Thumb Code 12 drv_memc.o(i.drv_memc_gen_a_tear_signal) + drv_memc_get_status 0x00013d99 Thumb Code 20 drv_memc.o(i.drv_memc_get_status) + drv_memc_get_tear_mode 0x00013db1 Thumb Code 10 drv_memc.o(i.drv_memc_get_tear_mode) + drv_memc_rate_transfer_sel 0x00013dc1 Thumb Code 22 drv_memc.o(i.drv_memc_rate_transfer_sel) + drv_memc_sel_vsync 0x00013ddd Thumb Code 16 drv_memc.o(i.drv_memc_sel_vsync) + drv_memc_set_active_height 0x00013df1 Thumb Code 16 drv_memc.o(i.drv_memc_set_active_height) + drv_memc_set_circ_mode_enable 0x00013e09 Thumb Code 24 drv_memc.o(i.drv_memc_set_circ_mode_enable) + drv_memc_set_data_mode 0x00013e25 Thumb Code 14 drv_memc.o(i.drv_memc_set_data_mode) + drv_memc_set_double_buffer 0x00013e39 Thumb Code 18 drv_memc.o(i.drv_memc_set_double_buffer) + drv_memc_set_frame_drop_select 0x00013e51 Thumb Code 24 drv_memc.o(i.drv_memc_set_frame_drop_select) + drv_memc_set_fs_en_conditions 0x00013e6d Thumb Code 18 drv_memc.o(i.drv_memc_set_fs_en_conditions) + drv_memc_set_lcdc_st_conditions 0x00013e85 Thumb Code 20 drv_memc.o(i.drv_memc_set_lcdc_st_conditions) + drv_memc_set_ltpo_mode 0x00013ea1 Thumb Code 28 drv_memc.o(i.drv_memc_set_ltpo_mode) + drv_memc_set_ltpo_pu_thres 0x00013ec1 Thumb Code 18 drv_memc.o(i.drv_memc_set_ltpo_pu_thres) + drv_memc_set_tear_mode 0x00013ed9 Thumb Code 16 drv_memc.o(i.drv_memc_set_tear_mode) + drv_memc_set_tear_waveform 0x00013eed Thumb Code 36 drv_memc.o(i.drv_memc_set_tear_waveform) + drv_memc_set_vidc_sync_cnt 0x00013f19 Thumb Code 16 drv_memc.o(i.drv_memc_set_vidc_sync_cnt) + drv_phy_test_clear 0x00013f2d Thumb Code 16 drv_phy_common.o(i.drv_phy_test_clear) + drv_phy_test_lock 0x00013f3d Thumb Code 24 drv_phy_common.o(i.drv_phy_test_lock) + drv_pwr_efuse_pd 0x00013f55 Thumb Code 36 drv_pwr.o(i.drv_pwr_efuse_pd) + drv_pwr_enter_deep_sleep_mode 0x00013f85 Thumb Code 60 drv_pwr.o(i.drv_pwr_enter_deep_sleep_mode) + drv_pwr_enter_sleep_mode_ex 0x00013fd1 Thumb Code 34 drv_pwr.o(i.drv_pwr_enter_sleep_mode_ex) + drv_pwr_enter_stop_sleep_mode 0x00014005 Thumb Code 132 drv_pwr.o(i.drv_pwr_enter_stop_sleep_mode) + drv_pwr_exit_sleep_mode 0x0001409d Thumb Code 32 drv_pwr.o(i.drv_pwr_exit_sleep_mode) + drv_pwr_get_power_ready_st 0x000140c5 Thumb Code 10 drv_pwr.o(i.drv_pwr_get_power_ready_st) + drv_pwr_set_breath_screen_power_sel 0x000140d5 Thumb Code 34 drv_pwr.o(i.drv_pwr_set_breath_screen_power_sel) + drv_pwr_set_digit_power_sel 0x000140fd Thumb Code 34 drv_pwr.o(i.drv_pwr_set_digit_power_sel) + drv_pwr_set_pll_clk 0x00014125 Thumb Code 30 drv_pwr.o(i.drv_pwr_set_pll_clk) + drv_pwr_set_wakeup_type 0x00014159 Thumb Code 40 drv_pwr.o(i.drv_pwr_set_wakeup_type) + drv_pwr_write_lock 0x00014185 Thumb Code 18 drv_pwr.o(i.drv_pwr_write_lock) + drv_rxbr_clear_pkt_buffer 0x000141a5 Thumb Code 12 drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) + drv_rxbr_clear_status0 0x000141b5 Thumb Code 6 drv_rxbr.o(i.drv_rxbr_clear_status0) + drv_rxbr_enable_irq 0x000141c1 Thumb Code 90 drv_rxbr.o(i.drv_rxbr_enable_irq) + drv_rxbr_frame_drop_cfg 0x0001421d Thumb Code 18 drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) + drv_rxbr_hline_rcv1_cfg 0x00014269 Thumb Code 14 drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg) + drv_rxbr_hline_rcv_cfg 0x0001427d Thumb Code 10 drv_rxbr.o(i.drv_rxbr_hline_rcv_cfg) + drv_rxbr_register_irq1_callback 0x0001428d Thumb Code 6 drv_rxbr.o(i.drv_rxbr_register_irq1_callback) + drv_rxbr_set_ack_pkt_header 0x00014299 Thumb Code 18 drv_rxbr.o(i.drv_rxbr_set_ack_pkt_header) + drv_rxbr_set_color_format 0x000142b1 Thumb Code 24 drv_rxbr.o(i.drv_rxbr_set_color_format) + drv_rxbr_set_filter_regs 0x000142cd Thumb Code 32 drv_rxbr.o(i.drv_rxbr_set_filter_regs) + drv_rxbr_set_inten 0x000142f1 Thumb Code 22 drv_rxbr.o(i.drv_rxbr_set_inten) + drv_rxbr_set_ltpo_drop_th 0x0001430d Thumb Code 18 drv_rxbr.o(i.drv_rxbr_set_ltpo_drop_th) + drv_rxbr_set_usr_cfg 0x00014325 Thumb Code 56 drv_rxbr.o(i.drv_rxbr_set_usr_cfg) + drv_rxbr_set_usr_col 0x00014365 Thumb Code 10 drv_rxbr.o(i.drv_rxbr_set_usr_col) + drv_rxbr_set_usr_row 0x00014375 Thumb Code 10 drv_rxbr.o(i.drv_rxbr_set_usr_row) + drv_se_init 0x00014385 Thumb Code 106 drv_se.o(i.drv_se_init) + drv_se_set_dsc 0x000143fd Thumb Code 162 drv_se.o(i.drv_se_set_dsc) + drv_se_set_lcdc 0x000144d1 Thumb Code 88 drv_se.o(i.drv_se_set_lcdc) + drv_se_set_memc 0x00014559 Thumb Code 54 drv_se.o(i.drv_se_set_memc) + drv_se_set_rxbr 0x000145c1 Thumb Code 158 drv_se.o(i.drv_se_set_rxbr) + drv_se_set_vidc 0x00014691 Thumb Code 122 drv_se.o(i.drv_se_set_vidc) + drv_se_start_rx 0x0001473d Thumb Code 16 drv_se.o(i.drv_se_start_rx) + drv_swire_enable 0x00014751 Thumb Code 24 drv_swire.o(i.drv_swire_enable) + drv_swire_get_pulse_count 0x0001476d Thumb Code 6 drv_swire.o(i.drv_swire_get_pulse_count) + drv_swire_register_callback 0x00014779 Thumb Code 6 drv_swire.o(i.drv_swire_register_callback) + drv_swire_set_bit_time 0x00014785 Thumb Code 18 drv_swire.o(i.drv_swire_set_bit_time) + drv_swire_set_int 0x0001479d Thumb Code 64 drv_swire.o(i.drv_swire_set_int) + drv_swire_set_power_down 0x000147e5 Thumb Code 24 drv_swire.o(i.drv_swire_set_power_down) + drv_swire_set_pulse_count 0x00014801 Thumb Code 6 drv_swire.o(i.drv_swire_set_pulse_count) + drv_swire_set_trig_mode 0x0001480d Thumb Code 24 drv_swire.o(i.drv_swire_set_trig_mode) + drv_sys_cfg_clear_all_int 0x00014829 Thumb Code 8 drv_sys_cfg.o(i.drv_sys_cfg_clear_all_int) + drv_sys_cfg_clear_pending 0x00014835 Thumb Code 32 drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) + drv_sys_cfg_sel_ap_rst_trig 0x0001485d Thumb Code 30 drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_trig) + drv_sys_cfg_sel_gpio_group 0x00014881 Thumb Code 30 drv_sys_cfg.o(i.drv_sys_cfg_sel_gpio_group) + drv_sys_cfg_sel_int_trig 0x000148a5 Thumb Code 32 drv_sys_cfg.o(i.drv_sys_cfg_sel_int_trig) + drv_sys_cfg_sel_swire_timer 0x000148c9 Thumb Code 18 drv_sys_cfg.o(i.drv_sys_cfg_sel_swire_timer) + drv_sys_cfg_set_int 0x000148e1 Thumb Code 30 drv_sys_cfg.o(i.drv_sys_cfg_set_int) + drv_timer_enable 0x0001491f Thumb Code 32 drv_timer.o(i.drv_timer_enable) + drv_timer_get_instance 0x00014941 Thumb Code 10 drv_timer.o(i.drv_timer_get_instance) + drv_timer_set_compare_val 0x0001498d Thumb Code 50 drv_timer.o(i.drv_timer_set_compare_val) + drv_timer_set_int 0x000149cd Thumb Code 68 drv_timer.o(i.drv_timer_set_int) + drv_timer_set_prescaler 0x00014a15 Thumb Code 36 drv_timer.o(i.drv_timer_set_prescaler) + drv_timer_set_repeat 0x00014a3d Thumb Code 12 drv_timer.o(i.drv_timer_set_repeat) + drv_tx_phy_test_enter 0x00014a4d Thumb Code 28 drv_dsi_tx.o(i.drv_tx_phy_test_enter) + drv_tx_phy_test_exit 0x00014a6d Thumb Code 28 drv_dsi_tx.o(i.drv_tx_phy_test_exit) + drv_tx_phy_test_write_code 0x00014a8d Thumb Code 34 drv_dsi_tx.o(i.drv_tx_phy_test_write_code) + drv_uart_abort_recv 0x00014ab5 Thumb Code 46 drv_uart.o(i.drv_uart_abort_recv) + drv_uart_abort_send 0x00014ae9 Thumb Code 46 drv_uart.o(i.drv_uart_abort_send) + drv_uart_config_int 0x00014b1d Thumb Code 20 drv_uart.o(i.drv_uart_config_int) + drv_uart_enable_int 0x00014b49 Thumb Code 84 drv_uart.o(i.drv_uart_enable_int) + drv_uart_get_instance 0x00014ba5 Thumb Code 36 drv_uart.o(i.drv_uart_get_instance) + drv_uart_init 0x00014bcd Thumb Code 206 drv_uart.o(i.drv_uart_init) + drv_uart_reset_rx_fifo 0x00014cd9 Thumb Code 28 drv_uart.o(i.drv_uart_reset_rx_fifo) + drv_uart_reset_tx_fifo 0x00014cf5 Thumb Code 28 drv_uart.o(i.drv_uart_reset_tx_fifo) + drv_uart_send_blocking 0x00014d11 Thumb Code 26 drv_uart.o(i.drv_uart_send_blocking) + drv_uart_set_baud_rate 0x00014d2b Thumb Code 84 drv_uart.o(i.drv_uart_set_baud_rate) + drv_uart_trans_create_handle 0x00014d81 Thumb Code 72 drv_uart.o(i.drv_uart_trans_create_handle) + drv_vidc_clear_irq 0x00014dcd Thumb Code 10 drv_vidc.o(i.drv_vidc_clear_irq) + drv_vidc_enable 0x00014ddd Thumb Code 26 drv_vidc.o(i.drv_vidc_enable) + drv_vidc_enable_irq 0x00014dfd Thumb Code 58 drv_vidc.o(i.drv_vidc_enable_irq) + drv_vidc_get_int_source 0x00014e3d Thumb Code 40 drv_vidc.o(i.drv_vidc_get_int_source) + drv_vidc_get_irq_status 0x00014e69 Thumb Code 20 drv_vidc.o(i.drv_vidc_get_irq_status) + drv_vidc_init_module_enable 0x00014e81 Thumb Code 36 drv_vidc.o(i.drv_vidc_init_module_enable) + drv_vidc_register_callback 0x00014ead Thumb Code 6 drv_vidc.o(i.drv_vidc_register_callback) + drv_vidc_reset 0x00014eb9 Thumb Code 8 drv_vidc.o(i.drv_vidc_reset) + drv_vidc_set_circ_mode_enable 0x00014ec5 Thumb Code 24 drv_vidc.o(i.drv_vidc_set_circ_mode_enable) + drv_vidc_set_dither_config 0x00014ee1 Thumb Code 50 drv_vidc.o(i.drv_vidc_set_dither_config) + drv_vidc_set_dst_parameter 0x00014f19 Thumb Code 86 drv_vidc.o(i.drv_vidc_set_dst_parameter) + drv_vidc_set_honly_hcoef0 0x00014f75 Thumb Code 6 drv_vidc.o(i.drv_vidc_set_honly_hcoef0) + drv_vidc_set_honly_hinitb 0x00014f81 Thumb Code 38 drv_vidc.o(i.drv_vidc_set_honly_hinitb) + drv_vidc_set_honly_hinitr 0x00014fad Thumb Code 42 drv_vidc.o(i.drv_vidc_set_honly_hinitr) + drv_vidc_set_irqen 0x00014fdd Thumb Code 22 drv_vidc.o(i.drv_vidc_set_irqen) + drv_vidc_set_mirror 0x00014ff9 Thumb Code 16 drv_vidc.o(i.drv_vidc_set_mirror) + drv_vidc_set_pentile_swap 0x0001500d Thumb Code 20 drv_vidc.o(i.drv_vidc_set_pentile_swap) + drv_vidc_set_pu_ctrl 0x00015029 Thumb Code 6 drv_vidc.o(i.drv_vidc_set_pu_ctrl) + drv_vidc_set_rotation 0x00015035 Thumb Code 18 drv_vidc.o(i.drv_vidc_set_rotation) + drv_vidc_set_scld_hcoef0 0x0001504d Thumb Code 6 drv_vidc.o(i.drv_vidc_set_scld_hcoef0) + drv_vidc_set_scld_hcoef1 0x00015059 Thumb Code 6 drv_vidc.o(i.drv_vidc_set_scld_hcoef1) + drv_vidc_set_scld_step 0x00015065 Thumb Code 14 drv_vidc.o(i.drv_vidc_set_scld_step) + drv_vidc_set_scld_vcoef0 0x00015079 Thumb Code 6 drv_vidc.o(i.drv_vidc_set_scld_vcoef0) + drv_vidc_set_scld_vcoef1 0x00015085 Thumb Code 6 drv_vidc.o(i.drv_vidc_set_scld_vcoef1) + drv_vidc_set_src_parameter 0x00015091 Thumb Code 28 drv_vidc.o(i.drv_vidc_set_src_parameter) + drv_vidc_set_vintp_config 0x000150b1 Thumb Code 52 drv_vidc.o(i.drv_vidc_set_vintp_config) + fputc 0x000150e9 Thumb Code 42 tau_log.o(i.fputc) + google_p8p_demo 0x0001511d Thumb Code 48 p8p_demo.o(i.google_p8p_demo) + hal_dsi_rx_ctrl_create_handle 0x000151bd Thumb Code 60 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) + hal_dsi_rx_ctrl_dcs_async_handler 0x000151fd Thumb Code 60 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler) + hal_dsi_rx_ctrl_deinit 0x0001523d Thumb Code 132 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit) + hal_dsi_rx_ctrl_get_max_ret_size 0x000152d1 Thumb Code 28 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) + hal_dsi_rx_ctrl_init 0x000152f1 Thumb Code 158 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) + hal_dsi_rx_ctrl_pre_init_pps 0x00015a99 Thumb Code 50 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) + hal_dsi_rx_ctrl_send_ack_cmd 0x00015ad1 Thumb Code 210 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) + hal_dsi_rx_ctrl_start 0x00015bf1 Thumb Code 42 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) + hal_dsi_rx_ctrl_stop 0x00015c21 Thumb Code 42 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop) + hal_dsi_rx_ctrl_toggle_resolution 0x00015c51 Thumb Code 28 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) + hal_dsi_tx_ctrl_create_handle 0x00015ef1 Thumb Code 48 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) + hal_dsi_tx_ctrl_deinit 0x00015f29 Thumb Code 102 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit) + hal_dsi_tx_ctrl_gen_a_tear_signal 0x00015f9d Thumb Code 34 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal) + hal_dsi_tx_ctrl_init 0x00015fc1 Thumb Code 110 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) + hal_dsi_tx_ctrl_set_overwrite_rgb 0x0001604d Thumb Code 8 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb) + hal_dsi_tx_ctrl_set_tear_mode 0x00016055 Thumb Code 10 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode) + hal_dsi_tx_ctrl_start 0x00016061 Thumb Code 134 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) + hal_dsi_tx_ctrl_stop 0x000160f1 Thumb Code 52 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop) + hal_dsi_tx_ctrl_write_array_cmd 0x00016129 Thumb Code 238 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) + hal_dsi_tx_ctrl_write_cmd 0x0001621d Thumb Code 202 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) + hal_gpio_config_pad 0x000168d5 Thumb Code 58 hal_gpio.o(i.hal_gpio_config_pad) + hal_gpio_ctrl_eint 0x00016911 Thumb Code 18 hal_gpio.o(i.hal_gpio_ctrl_eint) + hal_gpio_init_eint 0x00016929 Thumb Code 58 hal_gpio.o(i.hal_gpio_init_eint) + hal_gpio_init_input 0x00016969 Thumb Code 22 hal_gpio.o(i.hal_gpio_init_input) + hal_gpio_init_output 0x0001697f Thumb Code 28 hal_gpio.o(i.hal_gpio_init_output) + hal_gpio_reg_eint_cb 0x0001699d Thumb Code 22 hal_gpio.o(i.hal_gpio_reg_eint_cb) + hal_gpio_set_ap_reset_int 0x000169b9 Thumb Code 76 hal_gpio.o(i.hal_gpio_set_ap_reset_int) + hal_gpio_set_mode 0x00016a09 Thumb Code 92 hal_gpio.o(i.hal_gpio_set_mode) + hal_gpio_set_output_data 0x00016a69 Thumb Code 8 hal_gpio.o(i.hal_gpio_set_output_data) + hal_internal_sync_get_hight_performan_mode 0x00016a71 Thumb Code 10 hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) + hal_internal_sync_input_resolution_change 0x00016a81 Thumb Code 336 hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) + hal_internal_sync_register_lcdc_cb 0x00016c35 Thumb Code 8 hal_internal_vsync.o(i.hal_internal_sync_register_lcdc_cb) + hal_internal_vsync_deinit 0x00016c41 Thumb Code 22 hal_internal_vsync.o(i.hal_internal_vsync_deinit) + hal_internal_vsync_get_rx_state 0x00016c61 Thumb Code 6 hal_internal_vsync.o(i.hal_internal_vsync_get_rx_state) + hal_internal_vsync_get_sync_line 0x00016c6d Thumb Code 16 hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) + hal_internal_vsync_get_tx_state 0x00016c81 Thumb Code 6 hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) + hal_internal_vsync_init_rx 0x00016c8d Thumb Code 206 hal_internal_vsync.o(i.hal_internal_vsync_init_rx) + hal_internal_vsync_init_tx 0x00016d75 Thumb Code 194 hal_internal_vsync.o(i.hal_internal_vsync_init_tx) + hal_internal_vsync_set_rx_state 0x00016e3d Thumb Code 28 hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) + hal_internal_vsync_set_tear_mode 0x00016e5d Thumb Code 424 hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) + hal_internal_vsync_set_tx_state 0x00017049 Thumb Code 78 hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) + hal_intl_dcs_init_sw_fltr 0x000170a1 Thumb Code 90 hal_internal_dcs.o(i.hal_intl_dcs_init_sw_fltr) + hal_intl_dcs_set_auto_hw_filter 0x00017739 Thumb Code 130 hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter) + hal_intl_fb_cal_fb_info 0x000177f1 Thumb Code 780 hal_internal_fb.o(i.hal_intl_fb_cal_fb_info) + hal_intl_fb_get_memc_flow_mode 0x00017cbd Thumb Code 6 hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode) + hal_intl_fb_get_rx_fb_info 0x00017cc9 Thumb Code 12 hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info) + hal_intl_fb_get_tx_fb_info 0x00017cd9 Thumb Code 12 hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info) + hal_intl_fb_get_user_flow 0x00017ce9 Thumb Code 6 hal_internal_fb.o(i.hal_intl_fb_get_user_flow) + hal_intl_svs_deinit_rx 0x00017cf5 Thumb Code 32 hal_internal_svs.o(i.hal_intl_svs_deinit_rx) + hal_intl_svs_deinit_tx 0x00017d1d Thumb Code 10 hal_internal_svs.o(i.hal_intl_svs_deinit_tx) + hal_intl_svs_handle 0x00017d2d Thumb Code 24 hal_internal_svs.o(i.hal_intl_svs_handle) + hal_intl_svs_init_rx 0x00017d51 Thumb Code 120 hal_internal_svs.o(i.hal_intl_svs_init_rx) + hal_intl_svs_init_tx 0x00017dd1 Thumb Code 16 hal_internal_svs.o(i.hal_intl_svs_init_tx) + hal_intl_svs_set_rx_vtt 0x00017de5 Thumb Code 6 hal_internal_svs.o(i.hal_intl_svs_set_rx_vtt) + hal_intl_svs_update_rxbr_clk 0x00017df1 Thumb Code 52 hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk) + hal_lcdc_displayproc_config 0x00017e39 Thumb Code 94 hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config) + hal_lcdc_postproc_config 0x00017f59 Thumb Code 276 hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config) + hal_lcdc_upscaler_config 0x000180e1 Thumb Code 202 hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config) + hal_nonshadow_func_update 0x000181c1 Thumb Code 180 hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) + hal_pwr_enter_deep_sleep_mode 0x0001827d Thumb Code 42 hal_pwr.o(i.hal_pwr_enter_deep_sleep_mode) + hal_pwr_enter_normal_sleep_mode 0x000182a7 Thumb Code 8 hal_pwr.o(i.hal_pwr_enter_normal_sleep_mode) + hal_pwr_enter_stop_sleep_mode 0x000182b1 Thumb Code 88 hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode) + hal_pwr_exit_sleep_mode 0x00018315 Thumb Code 10 hal_pwr.o(i.hal_pwr_exit_sleep_mode) + hal_pwr_get_vcc_power_ready 0x0001831f Thumb Code 8 hal_pwr.o(i.hal_pwr_get_vcc_power_ready) + hal_pwr_set_main_power 0x00018327 Thumb Code 8 hal_pwr.o(i.hal_pwr_set_main_power) + hal_pwr_set_sleep_mode_power 0x0001832f Thumb Code 8 hal_pwr.o(i.hal_pwr_set_sleep_mode_power) + hal_pwr_set_stop_sleep_wakeup_pin 0x00018339 Thumb Code 86 hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) + hal_swire_deinit 0x0001839d Thumb Code 60 hal_swire.o(i.hal_swire_deinit) + hal_swire_enable 0x000183dd Thumb Code 86 hal_swire.o(i.hal_swire_enable) + hal_swire_init 0x00018439 Thumb Code 74 hal_swire.o(i.hal_swire_init) + hal_swire_set_pulse 0x00018491 Thumb Code 32 hal_swire.o(i.hal_swire_set_pulse) + hal_swire_set_timer 0x000184b5 Thumb Code 60 hal_swire.o(i.hal_swire_set_timer) + hal_system_init 0x000184f5 Thumb Code 192 hal_system.o(i.hal_system_init) + hal_system_updata_sysclk 0x000185d9 Thumb Code 60 hal_system.o(i.hal_system_updata_sysclk) + hal_timer_deinit 0x00018629 Thumb Code 48 hal_timer.o(i.hal_timer_deinit) + hal_timer_init 0x00018659 Thumb Code 28 hal_timer.o(i.hal_timer_init) + hal_timer_set_repeat 0x00018675 Thumb Code 8 hal_timer.o(i.hal_timer_set_repeat) + hal_uart_init 0x000186ad Thumb Code 134 hal_uart.o(i.hal_uart_init) + hal_uart_send_blocking 0x00018741 Thumb Code 24 hal_uart.o(i.hal_uart_send_blocking) + hal_vsync_func_update 0x0001875d Thumb Code 18 hal_dsi_tx_ctrl.o(i.hal_vsync_func_update) + hal_vsync_reset_lcdc_scaler 0x00018775 Thumb Code 206 hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler) + main 0x00018855 Thumb Code 32 main.o(i.main) + tau_log_init 0x00019195 Thumb Code 48 tau_log.o(i.tau_log_init) + tau_log_printf 0x000191c9 Thumb Code 116 tau_log.o(i.tau_log_printf) + tau_log_push_log 0x0001924d Thumb Code 118 tau_log.o(i.tau_log_push_log) + panel_init_code 0x000194f0 Data 8268 p8p_demo.o(.constdata) + Region$$Table$$Base 0x0001b7a4 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x0001b7c4 Number 0 anon$$obj.o(Region$$Table) + rd_51_val 0x00070018 Data 2 p8p_demo.o(.data) + rd_51_val2 0x0007001a Data 2 p8p_demo.o(.data) + pps 0x0007001c Data 128 p8p_demo.o(.data) + pps_fhd 0x0007009c Data 128 p8p_demo.o(.data) + value_51H 0x0007011c Data 1 p8p_demo.o(.data) + value_51L 0x0007011d Data 1 p8p_demo.o(.data) + sg_uart0_tx_handle 0x000701bc Data 4 hal_uart.o(.data) + sg_uart0_rx_handle 0x000701c0 Data 4 hal_uart.o(.data) + sg_uart1_tx_handle 0x000701c4 Data 4 hal_uart.o(.data) + sg_uart1_rx_handle 0x000701c8 Data 4 hal_uart.o(.data) + g_sof_gen_te_func 0x000701d8 Data 4 hal_internal_vsync.o(.data) + hal_internal_vsync_handle_callback 0x000701dc Data 4 hal_internal_vsync.o(.data) + hal_internal_disp_end_handle_callback 0x000701e0 Data 4 hal_internal_vsync.o(.data) + g_systick_cb_func 0x0007020c Data 4 drv_common.o(.data) + g_system_clock 0x00070210 Data 4 drv_common.o(.data) + g_system_delay_step 0x00070214 Data 1 drv_common.o(.data) + g_int_rxbr_irq0_cb_func 0x00070278 Data 4 drv_rxbr.o(.data) + g_int_rxbr_irq1_cb_func 0x0007027c Data 4 drv_rxbr.o(.data) + g_int_vidc_cb_func 0x00070280 Data 4 drv_vidc.o(.data) + dma_req_map 0x00070384 Data 144 drv_dma.o(.data) + __stdout 0x00070414 Data 4 stdout.o(.data) + g_vsync_handle 0x000706a0 Data 40 hal_internal_vsync.o(.bss) + sg_pro_motion_handle 0x000706c8 Data 28 hal_internal_vsync.o(.bss) + g_dcs_execute_table 0x000706e4 Data 2048 hal_internal_dcs.o(.bss) + g_rx_fb_info 0x00070fe4 Data 68 hal_internal_fb.o(.bss) + g_packet_fifo 0x000710ac Data 4204 dcs_packet_fifo.o(.bss) + __stack_limit 0x00072188 Data 0 startup_armcm0.o(STACK) + __initial_sp 0x00073188 Data 0 startup_armcm0.o(STACK) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x000100c1 + + Load Region LR_IROM2 (Base: 0x00010000, Size: 0x0000bbdc, Max: 0x00010000, ABSOLUTE, COMPRESSED[0x0000b930]) + + Execution Region ER_IROM2 (Exec base: 0x00010000, Load base: 0x00010000, Size: 0x0000b7c4, Max: 0x00010000, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x00010000 0x00010000 0x000000c0 Data RO 323 RESET startup_armcm0.o + 0x000100c0 0x000100c0 0x00000000 Code RO 1882 * .ARM.Collect$$$$00000000 mc_p.l(entry.o) + 0x000100c0 0x000100c0 0x00000004 Code RO 2190 .ARM.Collect$$$$00000001 mc_p.l(entry2.o) + 0x000100c4 0x000100c4 0x00000004 Code RO 2193 .ARM.Collect$$$$00000004 mc_p.l(entry5.o) + 0x000100c8 0x000100c8 0x00000000 Code RO 2195 .ARM.Collect$$$$00000008 mc_p.l(entry7b.o) + 0x000100c8 0x000100c8 0x00000000 Code RO 2197 .ARM.Collect$$$$0000000A mc_p.l(entry8b.o) + 0x000100c8 0x000100c8 0x00000008 Code RO 2198 .ARM.Collect$$$$0000000B mc_p.l(entry9a.o) + 0x000100d0 0x000100d0 0x00000000 Code RO 2200 .ARM.Collect$$$$0000000D mc_p.l(entry10a.o) + 0x000100d0 0x000100d0 0x00000000 Code RO 2202 .ARM.Collect$$$$0000000F mc_p.l(entry11a.o) + 0x000100d0 0x000100d0 0x00000004 Code RO 2191 .ARM.Collect$$$$00002712 mc_p.l(entry2.o) + 0x000100d4 0x000100d4 0x00000078 Code RO 324 .text startup_armcm0.o + 0x0001014c 0x0001014c 0x0000002c Code RO 1885 .text mc_p.l(uidiv.o) + 0x00010178 0x00010178 0x00000028 Code RO 1887 .text mc_p.l(idiv.o) + 0x000101a0 0x000101a0 0x00000024 Code RO 1889 .text mc_p.l(memcpya.o) + 0x000101c4 0x000101c4 0x00000024 Code RO 1891 .text mc_p.l(memseta.o) + 0x000101e8 0x000101e8 0x0000000e Code RO 1893 .text mc_p.l(strlen.o) + 0x000101f6 0x000101f6 0x0000001a Code RO 1895 .text mc_p.l(memcmp.o) + 0x00010210 0x00010210 0x000000b2 Code RO 2160 .text mf_p.l(fadd.o) + 0x000102c2 0x000102c2 0x0000007a Code RO 2162 .text mf_p.l(fmul.o) + 0x0001033c 0x0001033c 0x0000007c Code RO 2164 .text mf_p.l(fdiv.o) + 0x000103b8 0x000103b8 0x00000018 Code RO 2166 .text mf_p.l(fscalb.o) + 0x000103d0 0x000103d0 0x00000164 Code RO 2168 .text mf_p.l(dadd.o) + 0x00010534 0x00010534 0x000000d0 Code RO 2170 .text mf_p.l(dmul.o) + 0x00010604 0x00010604 0x0000000e Code RO 2174 .text mf_p.l(ffltui.o) + 0x00010612 0x00010612 0x00000002 PAD + 0x00010614 0x00010614 0x0000001c Code RO 2176 .text mf_p.l(dfltui.o) + 0x00010630 0x00010630 0x00000028 Code RO 2178 .text mf_p.l(ffixui.o) + 0x00010658 0x00010658 0x0000003c Code RO 2180 .text mf_p.l(dfixui.o) + 0x00010694 0x00010694 0x00000028 Code RO 2182 .text mf_p.l(f2d.o) + 0x000106bc 0x000106bc 0x00000038 Code RO 2184 .text mf_p.l(d2f.o) + 0x000106f4 0x000106f4 0x00000014 Code RO 2186 .text mf_p.l(cfcmple.o) + 0x00010708 0x00010708 0x00000014 Code RO 2188 .text mf_p.l(cfrcmple.o) + 0x0001071c 0x0001071c 0x00000060 Code RO 2205 .text mc_p.l(uldiv.o) + 0x0001077c 0x0001077c 0x00000020 Code RO 2207 .text mc_p.l(llshl.o) + 0x0001079c 0x0001079c 0x00000022 Code RO 2209 .text mc_p.l(llushr.o) + 0x000107be 0x000107be 0x00000026 Code RO 2211 .text mc_p.l(llsshr.o) + 0x000107e4 0x000107e4 0x00000000 Code RO 2213 .text mc_p.l(iusefp.o) + 0x000107e4 0x000107e4 0x00000082 Code RO 2214 .text mf_p.l(fepilogue.o) + 0x00010866 0x00010866 0x000000be Code RO 2216 .text mf_p.l(depilogue.o) + 0x00010924 0x00010924 0x000000f0 Code RO 2220 .text mf_p.l(ddiv.o) + 0x00010a14 0x00010a14 0x00000040 Code RO 2222 .text mf_p.l(dfixul.o) + 0x00010a54 0x00010a54 0x00000028 Code RO 2224 .text mf_p.l(cdrcmple.o) + 0x00010a7c 0x00010a7c 0x00000024 Code RO 2226 .text mc_p.l(init.o) + 0x00010aa0 0x00010aa0 0x00000056 Code RO 2236 .text mc_p.l(__dczerorl2.o) + 0x00010af6 0x00010af6 0x00000002 PAD + 0x00010af8 0x00010af8 0x0000001c Code RO 964 i.AP_NRESET_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010b14 0x00010b14 0x0000005c Code RO 1731 i.DMA_IRQn_Handler CVWL668.lib(drv_dma.o) + 0x00010b70 0x00010b70 0x0000000a Code RO 965 i.EXTI_INT0_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010b7a 0x00010b7a 0x0000000a Code RO 966 i.EXTI_INT1_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010b84 0x00010b84 0x0000000a Code RO 967 i.EXTI_INT2_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010b8e 0x00010b8e 0x0000000a Code RO 968 i.EXTI_INT3_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010b98 0x00010b98 0x0000000a Code RO 969 i.EXTI_INT4_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010ba2 0x00010ba2 0x0000000a Code RO 970 i.EXTI_INT5_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010bac 0x00010bac 0x0000000a Code RO 971 i.EXTI_INT6_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010bb6 0x00010bb6 0x0000000a Code RO 972 i.EXTI_INT7_IRQn_Handler CVWL668.lib(drv_gpio.o) + 0x00010bc0 0x00010bc0 0x00000048 Code RO 887 i.HardFault_Handler CVWL668.lib(drv_common.o) + 0x00010c08 0x00010c08 0x00000100 Code RO 732 i.LCDC_IRQn_Handler CVWL668.lib(hal_internal_vsync.o) + 0x00010d08 0x00010d08 0x0000009a Code RO 1491 i.MEMC_IRQn_Handler CVWL668.lib(drv_memc.o) + 0x00010da2 0x00010da2 0x00000002 PAD + 0x00010da4 0x00010da4 0x000000b8 Code RO 1297 i.MIPI_TX_IRQn_Handler CVWL668.lib(drv_dsi_tx.o) + 0x00010e5c 0x00010e5c 0x00000030 Code RO 1126 i.SWIRE_IRQn_Handler CVWL668.lib(drv_swire.o) + 0x00010e8c 0x00010e8c 0x00000018 Code RO 888 i.SysTick_Handler CVWL668.lib(drv_common.o) + 0x00010ea4 0x00010ea4 0x0000000a Code RO 1169 i.TIMER0_IRQn_Handler CVWL668.lib(drv_timer.o) + 0x00010eae 0x00010eae 0x0000000a Code RO 1170 i.TIMER1_IRQn_Handler CVWL668.lib(drv_timer.o) + 0x00010eb8 0x00010eb8 0x0000000a Code RO 1171 i.TIMER2_IRQn_Handler CVWL668.lib(drv_timer.o) + 0x00010ec2 0x00010ec2 0x0000000a Code RO 1172 i.TIMER3_IRQn_Handler CVWL668.lib(drv_timer.o) + 0x00010ecc 0x00010ecc 0x0000001c Code RO 1646 i.VIDC_IRQn_Handler CVWL668.lib(drv_vidc.o) + 0x00010ee8 0x00010ee8 0x0000001c Code RO 1557 i.VPRE1_IRQn_Handler CVWL668.lib(drv_rxbr.o) + 0x00010f04 0x00010f04 0x0000006c Code RO 798 i.VPRE_IRQn_Handler CVWL668.lib(hal_internal_dcs.o) + 0x00010f70 0x00010f70 0x00000020 Code RO 2132 i.__0printf mc_p.l(printfa.o) + 0x00010f90 0x00010f90 0x00000024 Code RO 2138 i.__0vsprintf mc_p.l(printfa.o) + 0x00010fb4 0x00010fb4 0x0000002e Code RO 2218 i.__ARM_clz mf_p.l(depilogue.o) + 0x00010fe2 0x00010fe2 0x0000001a Code RO 418 i.__ARM_common_switch8 CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00010ffc 0x00010ffc 0x00000002 Code RO 2231 i.__scatterload_null mc_p.l(handlers.o) + 0x00010ffe 0x00010ffe 0x00000002 PAD + 0x00011000 0x00011000 0x0000001c Data RO 895 .ARM.__at_0x11000 CVWL668.lib(drv_common.o) + 0x0001101c 0x0001101c 0x00000010 Data RO 688 .ARM.__at_0x1101C CVWL668.lib(tau_log.o) + 0x0001102c 0x0001102c 0x00000016 Data RO 471 .ARM.__at_0x1102C CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00011042 0x00011042 0x00000002 PAD + 0x00011044 0x00011044 0x00000364 Code RO 1236 i.MIPI_RX_IRQn_Handler CVWL668.lib(drv_dsi_rx.o) + 0x000113a8 0x000113a8 0x00000180 Code RO 1794 i.UART_IRQn_Handler CVWL668.lib(drv_uart.o) + 0x00011528 0x00011528 0x00000020 Code RO 1558 i.__NVIC_DisableIRQ CVWL668.lib(drv_rxbr.o) + 0x00011548 0x00011548 0x00000018 Code RO 1559 i.__NVIC_EnableIRQ CVWL668.lib(drv_rxbr.o) + 0x00011560 0x00011560 0x0000000e Code RO 2230 i.__scatterload_copy mc_p.l(handlers.o) + 0x0001156e 0x0001156e 0x0000000e Code RO 2232 i.__scatterload_zeroinit mc_p.l(handlers.o) + 0x0001157c 0x0001157c 0x00000174 Code RO 2139 i._fp_digits mc_p.l(printfa.o) + 0x000116f0 0x000116f0 0x000006ec Code RO 2140 i._printf_core mc_p.l(printfa.o) + 0x00011ddc 0x00011ddc 0x00000020 Code RO 2141 i._printf_post_padding mc_p.l(printfa.o) + 0x00011dfc 0x00011dfc 0x0000002c Code RO 2142 i._printf_pre_padding mc_p.l(printfa.o) + 0x00011e28 0x00011e28 0x0000000a Code RO 2144 i._sputc mc_p.l(printfa.o) + 0x00011e32 0x00011e32 0x00000002 PAD + 0x00011e34 0x00011e34 0x00000144 Code RO 95 i.ap_dcs_read p8p_demo.o + 0x00011f78 0x00011f78 0x00000094 Code RO 96 i.ap_dcs_set_backlight p8p_demo.o + 0x0001200c 0x0001200c 0x00000048 Code RO 97 i.ap_dcs_set_display_off p8p_demo.o + 0x00012054 0x00012054 0x000000a0 Code RO 98 i.ap_dcs_set_display_on p8p_demo.o + 0x000120f4 0x000120f4 0x00000094 Code RO 99 i.ap_dcs_set_enter_sleep_mode p8p_demo.o + 0x00012188 0x00012188 0x00000040 Code RO 101 i.ap_dcs_set_exit_sleep_mode p8p_demo.o + 0x000121c8 0x000121c8 0x00000034 Code RO 102 i.ap_dcs_set_frame_change p8p_demo.o + 0x000121fc 0x000121fc 0x00000058 Code RO 103 i.ap_rstn_pull_down_cb p8p_demo.o + 0x00012254 0x00012254 0x0000001c Code RO 104 i.ap_rstn_pull_high_cb p8p_demo.o + 0x00012270 0x00012270 0x0000004a Code RO 105 i.ap_set_FPS_53 p8p_demo.o + 0x000122ba 0x000122ba 0x0000002c Code RO 106 i.app_display_init p8p_demo.o + 0x000122e6 0x000122e6 0x00000002 PAD + 0x000122e8 0x000122e8 0x0000001c Code RO 107 i.app_gpio_init p8p_demo.o + 0x00012304 0x00012304 0x00000034 Code RO 108 i.app_init_panel p8p_demo.o + 0x00012338 0x00012338 0x00000120 Code RO 109 i.app_mipi_rx_init p8p_demo.o + 0x00012458 0x00012458 0x00000100 Code RO 110 i.app_mipi_tx_init p8p_demo.o + 0x00012558 0x00012558 0x000000a4 Code RO 111 i.app_mipi_tx_start p8p_demo.o + 0x000125fc 0x000125fc 0x0000006c Code RO 112 i.app_system_process p8p_demo.o + 0x00012668 0x00012668 0x00000044 Code RO 113 i.app_system_resume p8p_demo.o + 0x000126ac 0x000126ac 0x00000190 Code RO 114 i.app_system_suspend p8p_demo.o + 0x0001283c 0x0001283c 0x0000002e Code RO 115 i.app_tx_panel_reset p8p_demo.o + 0x0001286a 0x0001286a 0x00000002 PAD + 0x0001286c 0x0001286c 0x00000018 Code RO 297 i.board_Init board.o + 0x00012884 0x00012884 0x000000c8 Code RO 1879 i.ceil m_ps.l(ceil.o) + 0x0001294c 0x0001294c 0x0000002c Code RO 733 i.check_mipi_rx_tx_video_info CVWL668.lib(hal_internal_vsync.o) + 0x00012978 0x00012978 0x00000088 Code RO 799 i.check_pkt_buf_rev CVWL668.lib(hal_internal_dcs.o) + 0x00012a00 0x00012a00 0x00000058 Code RO 1202 i.dcs_packet_fifo_alloc CVWL668.lib(dcs_packet_fifo.o) + 0x00012a58 0x00012a58 0x00000018 Code RO 1203 i.dcs_packet_fifo_init CVWL668.lib(dcs_packet_fifo.o) + 0x00012a70 0x00012a70 0x00000044 Code RO 1204 i.dcs_packet_free_fifo_header CVWL668.lib(dcs_packet_fifo.o) + 0x00012ab4 0x00012ab4 0x00000024 Code RO 1205 i.dcs_packet_get_fifo_header CVWL668.lib(dcs_packet_fifo.o) + 0x00012ad8 0x00012ad8 0x00000018 Code RO 675 i.delayMs CVWL668.lib(tau_delay.o) + 0x00012af0 0x00012af0 0x0000002c Code RO 676 i.delayUs CVWL668.lib(tau_delay.o) + 0x00012b1c 0x00012b1c 0x00000008 Code RO 893 i.drv_common_system_init CVWL668.lib(drv_common.o) + 0x00012b24 0x00012b24 0x0000003c Code RO 912 i.drv_crgu_enable_clock CVWL668.lib(drv_crgu.o) + 0x00012b60 0x00012b60 0x00000068 Code RO 915 i.drv_crgu_get_rxbr_clk CVWL668.lib(drv_crgu.o) + 0x00012bc8 0x00012bc8 0x00000010 Code RO 918 i.drv_crgu_reset_modules CVWL668.lib(drv_crgu.o) + 0x00012bd8 0x00012bd8 0x00000028 Code RO 919 i.drv_crgu_set_ahb_clk CVWL668.lib(drv_crgu.o) + 0x00012c00 0x00012c00 0x00000010 Code RO 920 i.drv_crgu_set_clock_div CVWL668.lib(drv_crgu.o) + 0x00012c10 0x00012c10 0x0000003c Code RO 922 i.drv_crgu_set_dpi_clk CVWL668.lib(drv_crgu.o) + 0x00012c4c 0x00012c4c 0x00000038 Code RO 923 i.drv_crgu_set_dsc_clk CVWL668.lib(drv_crgu.o) + 0x00012c84 0x00012c84 0x00000028 Code RO 924 i.drv_crgu_set_fb_clk CVWL668.lib(drv_crgu.o) + 0x00012cac 0x00012cac 0x00000028 Code RO 925 i.drv_crgu_set_lcdc_clk CVWL668.lib(drv_crgu.o) + 0x00012cd4 0x00012cd4 0x00000018 Code RO 926 i.drv_crgu_set_reset CVWL668.lib(drv_crgu.o) + 0x00012cec 0x00012cec 0x00000028 Code RO 927 i.drv_crgu_set_rxbr_clk CVWL668.lib(drv_crgu.o) + 0x00012d14 0x00012d14 0x00000028 Code RO 928 i.drv_crgu_set_vidc_clk CVWL668.lib(drv_crgu.o) + 0x00012d3c 0x00012d3c 0x00000018 Code RO 1733 i.drv_dma_clear_status CVWL668.lib(drv_dma.o) + 0x00012d54 0x00012d54 0x00000014 Code RO 1739 i.drv_dma_get_int_source CVWL668.lib(drv_dma.o) + 0x00012d68 0x00012d68 0x0000001c Code RO 952 i.drv_dsc_dec_disable CVWL668.lib(drv_dsc_dec.o) + 0x00012d84 0x00012d84 0x00000038 Code RO 953 i.drv_dsc_dec_enable CVWL668.lib(drv_dsc_dec.o) + 0x00012dbc 0x00012dbc 0x00000020 Code RO 954 i.drv_dsc_dec_get_nslc CVWL668.lib(drv_dsc_dec.o) + 0x00012ddc 0x00012ddc 0x0000001c Code RO 955 i.drv_dsc_dec_set_irqen CVWL668.lib(drv_dsc_dec.o) + 0x00012df8 0x00012df8 0x0000010c Code RO 1237 i.drv_dsi_rx_calc_ipi_tx_delay CVWL668.lib(drv_dsi_rx.o) + 0x00012f04 0x00012f04 0x00000040 Code RO 1238 i.drv_dsi_rx_enable_irq CVWL668.lib(drv_dsi_rx.o) + 0x00012f44 0x00012f44 0x00000050 Code RO 1240 i.drv_dsi_rx_get_color_bpp CVWL668.lib(drv_dsi_rx.o) + 0x00012f94 0x00012f94 0x0000001c Code RO 1241 i.drv_dsi_rx_get_color_pcc CVWL668.lib(drv_dsi_rx.o) + 0x00012fb0 0x00012fb0 0x00000010 Code RO 1242 i.drv_dsi_rx_get_compression_en CVWL668.lib(drv_dsi_rx.o) + 0x00012fc0 0x00012fc0 0x00000010 Code RO 1243 i.drv_dsi_rx_get_ddi_crc_en CVWL668.lib(drv_dsi_rx.o) + 0x00012fd0 0x00012fd0 0x0000000c Code RO 1245 i.drv_dsi_rx_get_max_ret_size CVWL668.lib(drv_dsi_rx.o) + 0x00012fdc 0x00012fdc 0x00000018 Code RO 1248 i.drv_dsi_rx_power_up CVWL668.lib(drv_dsi_rx.o) + 0x00012ff4 0x00012ff4 0x0000001c Code RO 1249 i.drv_dsi_rx_set_check_crc CVWL668.lib(drv_dsi_rx.o) + 0x00013010 0x00013010 0x00000024 Code RO 1250 i.drv_dsi_rx_set_ctrl_cfg CVWL668.lib(drv_dsi_rx.o) + 0x00013034 0x00013034 0x00000010 Code RO 1251 i.drv_dsi_rx_set_ddi_cfg CVWL668.lib(drv_dsi_rx.o) + 0x00013044 0x00013044 0x0000001c Code RO 1252 i.drv_dsi_rx_set_ddi_crc_en CVWL668.lib(drv_dsi_rx.o) + 0x00013060 0x00013060 0x0000000c Code RO 1255 i.drv_dsi_rx_set_inten CVWL668.lib(drv_dsi_rx.o) + 0x0001306c 0x0001306c 0x00000010 Code RO 1256 i.drv_dsi_rx_set_ipi_cfg CVWL668.lib(drv_dsi_rx.o) + 0x0001307c 0x0001307c 0x0000001c Code RO 1258 i.drv_dsi_rx_set_ipi_ycbcr_frmt CVWL668.lib(drv_dsi_rx.o) + 0x00013098 0x00013098 0x00000014 Code RO 1259 i.drv_dsi_rx_set_lane_swap CVWL668.lib(drv_dsi_rx.o) + 0x000130ac 0x000130ac 0x00000024 Code RO 1260 i.drv_dsi_rx_set_resp_cnt CVWL668.lib(drv_dsi_rx.o) + 0x000130d0 0x000130d0 0x0000001c Code RO 1261 i.drv_dsi_rx_set_tear_resp_en CVWL668.lib(drv_dsi_rx.o) + 0x000130ec 0x000130ec 0x00000100 Code RO 1262 i.drv_dsi_rx_set_up_phy CVWL668.lib(drv_dsi_rx.o) + 0x000131ec 0x000131ec 0x00000018 Code RO 1263 i.drv_dsi_rx_shut_down CVWL668.lib(drv_dsi_rx.o) + 0x00013204 0x00013204 0x00000018 Code RO 1299 i.drv_dsi_tx_command_header CVWL668.lib(drv_dsi_tx.o) + 0x0001321c 0x0001321c 0x00000058 Code RO 1300 i.drv_dsi_tx_command_mode_cfg CVWL668.lib(drv_dsi_tx.o) + 0x00013274 0x00013274 0x0000000c Code RO 1301 i.drv_dsi_tx_command_put_payload CVWL668.lib(drv_dsi_tx.o) + 0x00013280 0x00013280 0x00000020 Code RO 1302 i.drv_dsi_tx_config_eotp CVWL668.lib(drv_dsi_tx.o) + 0x000132a0 0x000132a0 0x0000000c Code RO 1303 i.drv_dsi_tx_config_int CVWL668.lib(drv_dsi_tx.o) + 0x000132ac 0x000132ac 0x00000010 Code RO 1304 i.drv_dsi_tx_dpi_lpcmd_time CVWL668.lib(drv_dsi_tx.o) + 0x000132bc 0x000132bc 0x00000010 Code RO 1305 i.drv_dsi_tx_dpi_mode CVWL668.lib(drv_dsi_tx.o) + 0x000132cc 0x000132cc 0x00000024 Code RO 1306 i.drv_dsi_tx_dpi_polarity CVWL668.lib(drv_dsi_tx.o) + 0x000132f0 0x000132f0 0x0000000c Code RO 1307 i.drv_dsi_tx_edpi_cmd_size CVWL668.lib(drv_dsi_tx.o) + 0x000132fc 0x000132fc 0x0000000c Code RO 1309 i.drv_dsi_tx_get_cmd_status CVWL668.lib(drv_dsi_tx.o) + 0x00013308 0x00013308 0x0000000c Code RO 1311 i.drv_dsi_tx_mode CVWL668.lib(drv_dsi_tx.o) + 0x00013314 0x00013314 0x0000001c Code RO 1312 i.drv_dsi_tx_phy_clock_lane_auto_lp CVWL668.lib(drv_dsi_tx.o) + 0x00013330 0x00013330 0x00000020 Code RO 1313 i.drv_dsi_tx_phy_clock_lane_req_hs CVWL668.lib(drv_dsi_tx.o) + 0x00013350 0x00013350 0x00000010 Code RO 1315 i.drv_dsi_tx_phy_lane_mode CVWL668.lib(drv_dsi_tx.o) + 0x00013360 0x00013360 0x00000068 Code RO 1318 i.drv_dsi_tx_phy_status_ready CVWL668.lib(drv_dsi_tx.o) + 0x000133c8 0x000133c8 0x00000044 Code RO 1319 i.drv_dsi_tx_phy_status_stopstate CVWL668.lib(drv_dsi_tx.o) + 0x0001340c 0x0001340c 0x00000150 Code RO 1321 i.drv_dsi_tx_phy_test_setup CVWL668.lib(drv_dsi_tx.o) + 0x0001355c 0x0001355c 0x00000020 Code RO 1322 i.drv_dsi_tx_phy_time_cfg CVWL668.lib(drv_dsi_tx.o) + 0x0001357c 0x0001357c 0x0000000c Code RO 1326 i.drv_dsi_tx_powerup CVWL668.lib(drv_dsi_tx.o) + 0x00013588 0x00013588 0x00000024 Code RO 1327 i.drv_dsi_tx_response_mode CVWL668.lib(drv_dsi_tx.o) + 0x000135ac 0x000135ac 0x0000001c Code RO 1330 i.drv_dsi_tx_set_bta_ack CVWL668.lib(drv_dsi_tx.o) + 0x000135c8 0x000135c8 0x00000014 Code RO 1331 i.drv_dsi_tx_set_esc_div CVWL668.lib(drv_dsi_tx.o) + 0x000135dc 0x000135dc 0x00000040 Code RO 1332 i.drv_dsi_tx_set_int CVWL668.lib(drv_dsi_tx.o) + 0x0001361c 0x0001361c 0x00000018 Code RO 1333 i.drv_dsi_tx_set_time_out_div CVWL668.lib(drv_dsi_tx.o) + 0x00013634 0x00013634 0x00000014 Code RO 1334 i.drv_dsi_tx_set_video_chunk CVWL668.lib(drv_dsi_tx.o) + 0x00013648 0x00013648 0x00000024 Code RO 1335 i.drv_dsi_tx_set_video_timing CVWL668.lib(drv_dsi_tx.o) + 0x0001366c 0x0001366c 0x0000000c Code RO 1337 i.drv_dsi_tx_shutdown CVWL668.lib(drv_dsi_tx.o) + 0x00013678 0x00013678 0x0000002c Code RO 1338 i.drv_dsi_tx_timeout_cfg CVWL668.lib(drv_dsi_tx.o) + 0x000136a4 0x000136a4 0x000000e8 Code RO 1341 i.drv_dsi_tx_video_mode_cfg CVWL668.lib(drv_dsi_tx.o) + 0x0001378c 0x0001378c 0x00000036 Code RO 1839 i.drv_efuse_enter_inactive CVWL668.lib(drv_efuse.o) + 0x000137c2 0x000137c2 0x0000000c Code RO 1842 i.drv_efuse_int_enable CVWL668.lib(drv_efuse.o) + 0x000137ce 0x000137ce 0x0000003a Code RO 1843 i.drv_efuse_read CVWL668.lib(drv_efuse.o) + 0x00013808 0x00013808 0x00000018 Code RO 1844 i.drv_efuse_read_req CVWL668.lib(drv_efuse.o) + 0x00013820 0x00013820 0x00000024 Code RO 975 i.drv_gpio_handle_int CVWL668.lib(drv_gpio.o) + 0x00013844 0x00013844 0x0000000c Code RO 976 i.drv_gpio_register_ap_reset_callback CVWL668.lib(drv_gpio.o) + 0x00013850 0x00013850 0x00000014 Code RO 977 i.drv_gpio_register_callback CVWL668.lib(drv_gpio.o) + 0x00013864 0x00013864 0x00000044 Code RO 979 i.drv_gpio_set_int CVWL668.lib(drv_gpio.o) + 0x000138a8 0x000138a8 0x00000020 Code RO 980 i.drv_gpio_set_ioe CVWL668.lib(drv_gpio.o) + 0x000138c8 0x000138c8 0x00000014 Code RO 981 i.drv_gpio_set_mode CVWL668.lib(drv_gpio.o) + 0x000138dc 0x000138dc 0x00000020 Code RO 528 i.drv_gpio_set_output_data CVWL668.lib(hal_gpio.o) + 0x000138fc 0x000138fc 0x00000028 Code RO 1403 i.drv_lcdc_bcsa_config CVWL668.lib(drv_lcdc.o) + 0x00013924 0x00013924 0x0000002c Code RO 1404 i.drv_lcdc_cfg_int_frame CVWL668.lib(drv_lcdc.o) + 0x00013950 0x00013950 0x00000018 Code RO 1405 i.drv_lcdc_clear_int CVWL668.lib(drv_lcdc.o) + 0x00013968 0x00013968 0x00000034 Code RO 1407 i.drv_lcdc_cmd_start CVWL668.lib(drv_lcdc.o) + 0x0001399c 0x0001399c 0x00000014 Code RO 1408 i.drv_lcdc_config_acc_command_mode CVWL668.lib(drv_lcdc.o) + 0x000139b0 0x000139b0 0x00000038 Code RO 1409 i.drv_lcdc_config_int CVWL668.lib(drv_lcdc.o) + 0x000139e8 0x000139e8 0x00000028 Code RO 1410 i.drv_lcdc_config_int_single CVWL668.lib(drv_lcdc.o) + 0x00013a10 0x00013a10 0x00000018 Code RO 1411 i.drv_lcdc_config_overwrite_rgb CVWL668.lib(drv_lcdc.o) + 0x00013a28 0x00013a28 0x00000050 Code RO 1412 i.drv_lcdc_config_src_parameter CVWL668.lib(drv_lcdc.o) + 0x00013a78 0x00013a78 0x00000010 Code RO 1413 i.drv_lcdc_crop_hact CVWL668.lib(drv_lcdc.o) + 0x00013a88 0x00013a88 0x00000038 Code RO 1414 i.drv_lcdc_ctrl_flow CVWL668.lib(drv_lcdc.o) + 0x00013ac0 0x00013ac0 0x00000030 Code RO 1415 i.drv_lcdc_dith_config CVWL668.lib(drv_lcdc.o) + 0x00013af0 0x00013af0 0x0000003c Code RO 1417 i.drv_lcdc_edge_dect_config CVWL668.lib(drv_lcdc.o) + 0x00013b2c 0x00013b2c 0x00000064 Code RO 1418 i.drv_lcdc_edge_enh_config CVWL668.lib(drv_lcdc.o) + 0x00013b90 0x00013b90 0x00000024 Code RO 1419 i.drv_lcdc_enable_shadow_reg CVWL668.lib(drv_lcdc.o) + 0x00013bb4 0x00013bb4 0x0000001c Code RO 1420 i.drv_lcdc_endianness_config CVWL668.lib(drv_lcdc.o) + 0x00013bd0 0x00013bd0 0x00000020 Code RO 1421 i.drv_lcdc_fc_config CVWL668.lib(drv_lcdc.o) + 0x00013bf0 0x00013bf0 0x00000024 Code RO 1423 i.drv_lcdc_fldc_config CVWL668.lib(drv_lcdc.o) + 0x00013c14 0x00013c14 0x00000024 Code RO 1424 i.drv_lcdc_function_disable CVWL668.lib(drv_lcdc.o) + 0x00013c38 0x00013c38 0x00000024 Code RO 1425 i.drv_lcdc_function_enable CVWL668.lib(drv_lcdc.o) + 0x00013c5c 0x00013c5c 0x0000003c Code RO 1436 i.drv_lcdc_set_int CVWL668.lib(drv_lcdc.o) + 0x00013c98 0x00013c98 0x0000001c Code RO 1437 i.drv_lcdc_set_prefetch CVWL668.lib(drv_lcdc.o) + 0x00013cb4 0x00013cb4 0x0000001c Code RO 1438 i.drv_lcdc_set_tear_line CVWL668.lib(drv_lcdc.o) + 0x00013cd0 0x00013cd0 0x00000010 Code RO 1440 i.drv_lcdc_stop_display CVWL668.lib(drv_lcdc.o) + 0x00013ce0 0x00013ce0 0x0000003c Code RO 1442 i.drv_lcdc_vid_hw_start CVWL668.lib(drv_lcdc.o) + 0x00013d1c 0x00013d1c 0x00000018 Code RO 1444 i.drv_lcdc_vintp_mode_config CVWL668.lib(drv_lcdc.o) + 0x00013d34 0x00013d34 0x00000014 Code RO 1492 i.drv_memc_clear_status CVWL668.lib(drv_memc.o) + 0x00013d48 0x00013d48 0x00000040 Code RO 1493 i.drv_memc_enable_irq CVWL668.lib(drv_memc.o) + 0x00013d88 0x00013d88 0x00000010 Code RO 1494 i.drv_memc_gen_a_tear_signal CVWL668.lib(drv_memc.o) + 0x00013d98 0x00013d98 0x00000018 Code RO 1495 i.drv_memc_get_status CVWL668.lib(drv_memc.o) + 0x00013db0 0x00013db0 0x00000010 Code RO 1496 i.drv_memc_get_tear_mode CVWL668.lib(drv_memc.o) + 0x00013dc0 0x00013dc0 0x0000001c Code RO 1497 i.drv_memc_rate_transfer_sel CVWL668.lib(drv_memc.o) + 0x00013ddc 0x00013ddc 0x00000014 Code RO 1498 i.drv_memc_sel_vsync CVWL668.lib(drv_memc.o) + 0x00013df0 0x00013df0 0x00000018 Code RO 1499 i.drv_memc_set_active_height CVWL668.lib(drv_memc.o) + 0x00013e08 0x00013e08 0x0000001c Code RO 1500 i.drv_memc_set_circ_mode_enable CVWL668.lib(drv_memc.o) + 0x00013e24 0x00013e24 0x00000014 Code RO 1501 i.drv_memc_set_data_mode CVWL668.lib(drv_memc.o) + 0x00013e38 0x00013e38 0x00000018 Code RO 1504 i.drv_memc_set_double_buffer CVWL668.lib(drv_memc.o) + 0x00013e50 0x00013e50 0x0000001c Code RO 1508 i.drv_memc_set_frame_drop_select CVWL668.lib(drv_memc.o) + 0x00013e6c 0x00013e6c 0x00000018 Code RO 1509 i.drv_memc_set_fs_en_conditions CVWL668.lib(drv_memc.o) + 0x00013e84 0x00013e84 0x0000001c Code RO 1511 i.drv_memc_set_lcdc_st_conditions CVWL668.lib(drv_memc.o) + 0x00013ea0 0x00013ea0 0x00000020 Code RO 1512 i.drv_memc_set_ltpo_mode CVWL668.lib(drv_memc.o) + 0x00013ec0 0x00013ec0 0x00000018 Code RO 1513 i.drv_memc_set_ltpo_pu_thres CVWL668.lib(drv_memc.o) + 0x00013ed8 0x00013ed8 0x00000014 Code RO 1517 i.drv_memc_set_tear_mode CVWL668.lib(drv_memc.o) + 0x00013eec 0x00013eec 0x0000002c Code RO 1518 i.drv_memc_set_tear_waveform CVWL668.lib(drv_memc.o) + 0x00013f18 0x00013f18 0x00000014 Code RO 1520 i.drv_memc_set_vidc_sync_cnt CVWL668.lib(drv_memc.o) + 0x00013f2c 0x00013f2c 0x00000010 Code RO 1862 i.drv_phy_test_clear CVWL668.lib(drv_phy_common.o) + 0x00013f3c 0x00013f3c 0x00000018 Code RO 1863 i.drv_phy_test_lock CVWL668.lib(drv_phy_common.o) + 0x00013f54 0x00013f54 0x00000030 Code RO 1011 i.drv_pwr_efuse_pd CVWL668.lib(drv_pwr.o) + 0x00013f84 0x00013f84 0x0000004c Code RO 1013 i.drv_pwr_enter_deep_sleep_mode CVWL668.lib(drv_pwr.o) + 0x00013fd0 0x00013fd0 0x00000034 Code RO 1015 i.drv_pwr_enter_sleep_mode_ex CVWL668.lib(drv_pwr.o) + 0x00014004 0x00014004 0x00000098 Code RO 1016 i.drv_pwr_enter_stop_sleep_mode CVWL668.lib(drv_pwr.o) + 0x0001409c 0x0001409c 0x00000028 Code RO 1017 i.drv_pwr_exit_sleep_mode CVWL668.lib(drv_pwr.o) + 0x000140c4 0x000140c4 0x00000010 Code RO 1020 i.drv_pwr_get_power_ready_st CVWL668.lib(drv_pwr.o) + 0x000140d4 0x000140d4 0x00000028 Code RO 1052 i.drv_pwr_set_breath_screen_power_sel CVWL668.lib(drv_pwr.o) + 0x000140fc 0x000140fc 0x00000028 Code RO 1053 i.drv_pwr_set_digit_power_sel CVWL668.lib(drv_pwr.o) + 0x00014124 0x00014124 0x00000034 Code RO 1056 i.drv_pwr_set_pll_clk CVWL668.lib(drv_pwr.o) + 0x00014158 0x00014158 0x0000002c Code RO 1060 i.drv_pwr_set_wakeup_type CVWL668.lib(drv_pwr.o) + 0x00014184 0x00014184 0x00000020 Code RO 1063 i.drv_pwr_write_lock CVWL668.lib(drv_pwr.o) + 0x000141a4 0x000141a4 0x00000010 Code RO 1560 i.drv_rxbr_clear_pkt_buffer CVWL668.lib(drv_rxbr.o) + 0x000141b4 0x000141b4 0x0000000c Code RO 1561 i.drv_rxbr_clear_status0 CVWL668.lib(drv_rxbr.o) + 0x000141c0 0x000141c0 0x0000005a Code RO 1564 i.drv_rxbr_enable_irq CVWL668.lib(drv_rxbr.o) + 0x0001421a 0x0001421a 0x00000002 PAD + 0x0001421c 0x0001421c 0x0000001c Code RO 1565 i.drv_rxbr_frame_drop_cfg CVWL668.lib(drv_rxbr.o) + 0x00014238 0x00014238 0x00000018 Code RO 734 i.drv_rxbr_get_int_source CVWL668.lib(hal_internal_vsync.o) + 0x00014250 0x00014250 0x00000018 Code RO 800 i.drv_rxbr_get_status0 CVWL668.lib(hal_internal_dcs.o) + 0x00014268 0x00014268 0x00000014 Code RO 1575 i.drv_rxbr_hline_rcv1_cfg CVWL668.lib(drv_rxbr.o) + 0x0001427c 0x0001427c 0x00000010 Code RO 1576 i.drv_rxbr_hline_rcv_cfg CVWL668.lib(drv_rxbr.o) + 0x0001428c 0x0001428c 0x0000000c Code RO 1578 i.drv_rxbr_register_irq1_callback CVWL668.lib(drv_rxbr.o) + 0x00014298 0x00014298 0x00000018 Code RO 1579 i.drv_rxbr_set_ack_pkt_header CVWL668.lib(drv_rxbr.o) + 0x000142b0 0x000142b0 0x0000001c Code RO 1584 i.drv_rxbr_set_color_format CVWL668.lib(drv_rxbr.o) + 0x000142cc 0x000142cc 0x00000024 Code RO 1587 i.drv_rxbr_set_filter_regs CVWL668.lib(drv_rxbr.o) + 0x000142f0 0x000142f0 0x0000001c Code RO 1588 i.drv_rxbr_set_inten CVWL668.lib(drv_rxbr.o) + 0x0001430c 0x0001430c 0x00000018 Code RO 1589 i.drv_rxbr_set_ltpo_drop_th CVWL668.lib(drv_rxbr.o) + 0x00014324 0x00014324 0x00000040 Code RO 1593 i.drv_rxbr_set_usr_cfg CVWL668.lib(drv_rxbr.o) + 0x00014364 0x00014364 0x00000010 Code RO 1594 i.drv_rxbr_set_usr_col CVWL668.lib(drv_rxbr.o) + 0x00014374 0x00014374 0x00000010 Code RO 1595 i.drv_rxbr_set_usr_row CVWL668.lib(drv_rxbr.o) + 0x00014384 0x00014384 0x00000078 Code RO 1217 i.drv_se_init CVWL668.lib(drv_se.o) + 0x000143fc 0x000143fc 0x000000d4 Code RO 1218 i.drv_se_set_dsc CVWL668.lib(drv_se.o) + 0x000144d0 0x000144d0 0x00000088 Code RO 1219 i.drv_se_set_lcdc CVWL668.lib(drv_se.o) + 0x00014558 0x00014558 0x00000068 Code RO 1220 i.drv_se_set_memc CVWL668.lib(drv_se.o) + 0x000145c0 0x000145c0 0x000000d0 Code RO 1221 i.drv_se_set_rxbr CVWL668.lib(drv_se.o) + 0x00014690 0x00014690 0x000000ac Code RO 1222 i.drv_se_set_vidc CVWL668.lib(drv_se.o) + 0x0001473c 0x0001473c 0x00000014 Code RO 1223 i.drv_se_start_rx CVWL668.lib(drv_se.o) + 0x00014750 0x00014750 0x0000001c Code RO 1127 i.drv_swire_enable CVWL668.lib(drv_swire.o) + 0x0001476c 0x0001476c 0x0000000c Code RO 1128 i.drv_swire_get_pulse_count CVWL668.lib(drv_swire.o) + 0x00014778 0x00014778 0x0000000c Code RO 1129 i.drv_swire_register_callback CVWL668.lib(drv_swire.o) + 0x00014784 0x00014784 0x00000018 Code RO 1130 i.drv_swire_set_bit_time CVWL668.lib(drv_swire.o) + 0x0001479c 0x0001479c 0x00000048 Code RO 1131 i.drv_swire_set_int CVWL668.lib(drv_swire.o) + 0x000147e4 0x000147e4 0x0000001c Code RO 1132 i.drv_swire_set_power_down CVWL668.lib(drv_swire.o) + 0x00014800 0x00014800 0x0000000c Code RO 1133 i.drv_swire_set_pulse_count CVWL668.lib(drv_swire.o) + 0x0001480c 0x0001480c 0x0000001c Code RO 1134 i.drv_swire_set_trig_mode CVWL668.lib(drv_swire.o) + 0x00014828 0x00014828 0x0000000c Code RO 1149 i.drv_sys_cfg_clear_all_int CVWL668.lib(drv_sys_cfg.o) + 0x00014834 0x00014834 0x00000028 Code RO 1150 i.drv_sys_cfg_clear_pending CVWL668.lib(drv_sys_cfg.o) + 0x0001485c 0x0001485c 0x00000024 Code RO 1151 i.drv_sys_cfg_sel_ap_rst_trig CVWL668.lib(drv_sys_cfg.o) + 0x00014880 0x00014880 0x00000024 Code RO 1153 i.drv_sys_cfg_sel_gpio_group CVWL668.lib(drv_sys_cfg.o) + 0x000148a4 0x000148a4 0x00000024 Code RO 1154 i.drv_sys_cfg_sel_int_trig CVWL668.lib(drv_sys_cfg.o) + 0x000148c8 0x000148c8 0x00000018 Code RO 1155 i.drv_sys_cfg_sel_swire_timer CVWL668.lib(drv_sys_cfg.o) + 0x000148e0 0x000148e0 0x00000024 Code RO 1156 i.drv_sys_cfg_set_int CVWL668.lib(drv_sys_cfg.o) + 0x00014904 0x00014904 0x0000001a Code RO 1173 i.drv_timer_clear_status_flags CVWL668.lib(drv_timer.o) + 0x0001491e 0x0001491e 0x00000020 Code RO 1174 i.drv_timer_enable CVWL668.lib(drv_timer.o) + 0x0001493e 0x0001493e 0x00000002 PAD + 0x00014940 0x00014940 0x00000010 Code RO 1175 i.drv_timer_get_instance CVWL668.lib(drv_timer.o) + 0x00014950 0x00014950 0x0000003c Code RO 1177 i.drv_timer_handle_interrupt CVWL668.lib(drv_timer.o) + 0x0001498c 0x0001498c 0x00000040 Code RO 1179 i.drv_timer_set_compare_val CVWL668.lib(drv_timer.o) + 0x000149cc 0x000149cc 0x00000048 Code RO 1180 i.drv_timer_set_int CVWL668.lib(drv_timer.o) + 0x00014a14 0x00014a14 0x00000028 Code RO 1181 i.drv_timer_set_prescaler CVWL668.lib(drv_timer.o) + 0x00014a3c 0x00014a3c 0x00000010 Code RO 1182 i.drv_timer_set_repeat CVWL668.lib(drv_timer.o) + 0x00014a4c 0x00014a4c 0x00000020 Code RO 1343 i.drv_tx_phy_test_enter CVWL668.lib(drv_dsi_tx.o) + 0x00014a6c 0x00014a6c 0x00000020 Code RO 1344 i.drv_tx_phy_test_exit CVWL668.lib(drv_dsi_tx.o) + 0x00014a8c 0x00014a8c 0x00000028 Code RO 1347 i.drv_tx_phy_test_write_code CVWL668.lib(drv_dsi_tx.o) + 0x00014ab4 0x00014ab4 0x00000034 Code RO 1795 i.drv_uart_abort_recv CVWL668.lib(drv_uart.o) + 0x00014ae8 0x00014ae8 0x00000034 Code RO 1796 i.drv_uart_abort_send CVWL668.lib(drv_uart.o) + 0x00014b1c 0x00014b1c 0x00000014 Code RO 1797 i.drv_uart_config_int CVWL668.lib(drv_uart.o) + 0x00014b30 0x00014b30 0x00000018 Code RO 1799 i.drv_uart_enable_clk CVWL668.lib(drv_uart.o) + 0x00014b48 0x00014b48 0x0000005c Code RO 1800 i.drv_uart_enable_int CVWL668.lib(drv_uart.o) + 0x00014ba4 0x00014ba4 0x00000028 Code RO 1802 i.drv_uart_get_instance CVWL668.lib(drv_uart.o) + 0x00014bcc 0x00014bcc 0x000000ce Code RO 1803 i.drv_uart_init CVWL668.lib(drv_uart.o) + 0x00014c9a 0x00014c9a 0x00000002 PAD + 0x00014c9c 0x00014c9c 0x0000003c Code RO 1804 i.drv_uart_int_trans_handle CVWL668.lib(drv_uart.o) + 0x00014cd8 0x00014cd8 0x0000001c Code RO 1807 i.drv_uart_reset_rx_fifo CVWL668.lib(drv_uart.o) + 0x00014cf4 0x00014cf4 0x0000001c Code RO 1808 i.drv_uart_reset_tx_fifo CVWL668.lib(drv_uart.o) + 0x00014d10 0x00014d10 0x0000001a Code RO 1809 i.drv_uart_send_blocking CVWL668.lib(drv_uart.o) + 0x00014d2a 0x00014d2a 0x00000054 Code RO 1811 i.drv_uart_set_baud_rate CVWL668.lib(drv_uart.o) + 0x00014d7e 0x00014d7e 0x00000002 PAD + 0x00014d80 0x00014d80 0x0000004c Code RO 1812 i.drv_uart_trans_create_handle CVWL668.lib(drv_uart.o) + 0x00014dcc 0x00014dcc 0x00000010 Code RO 1647 i.drv_vidc_clear_irq CVWL668.lib(drv_vidc.o) + 0x00014ddc 0x00014ddc 0x00000020 Code RO 1651 i.drv_vidc_enable CVWL668.lib(drv_vidc.o) + 0x00014dfc 0x00014dfc 0x00000040 Code RO 1652 i.drv_vidc_enable_irq CVWL668.lib(drv_vidc.o) + 0x00014e3c 0x00014e3c 0x0000002c Code RO 1653 i.drv_vidc_get_int_source CVWL668.lib(drv_vidc.o) + 0x00014e68 0x00014e68 0x00000018 Code RO 1654 i.drv_vidc_get_irq_status CVWL668.lib(drv_vidc.o) + 0x00014e80 0x00014e80 0x0000002c Code RO 1658 i.drv_vidc_init_module_enable CVWL668.lib(drv_vidc.o) + 0x00014eac 0x00014eac 0x0000000c Code RO 1659 i.drv_vidc_register_callback CVWL668.lib(drv_vidc.o) + 0x00014eb8 0x00014eb8 0x0000000c Code RO 1660 i.drv_vidc_reset CVWL668.lib(drv_vidc.o) + 0x00014ec4 0x00014ec4 0x0000001c Code RO 1661 i.drv_vidc_set_circ_mode_enable CVWL668.lib(drv_vidc.o) + 0x00014ee0 0x00014ee0 0x00000038 Code RO 1662 i.drv_vidc_set_dither_config CVWL668.lib(drv_vidc.o) + 0x00014f18 0x00014f18 0x0000005c Code RO 1664 i.drv_vidc_set_dst_parameter CVWL668.lib(drv_vidc.o) + 0x00014f74 0x00014f74 0x0000000c Code RO 1666 i.drv_vidc_set_honly_hcoef0 CVWL668.lib(drv_vidc.o) + 0x00014f80 0x00014f80 0x0000002c Code RO 1667 i.drv_vidc_set_honly_hinitb CVWL668.lib(drv_vidc.o) + 0x00014fac 0x00014fac 0x00000030 Code RO 1668 i.drv_vidc_set_honly_hinitr CVWL668.lib(drv_vidc.o) + 0x00014fdc 0x00014fdc 0x0000001c Code RO 1671 i.drv_vidc_set_irqen CVWL668.lib(drv_vidc.o) + 0x00014ff8 0x00014ff8 0x00000014 Code RO 1672 i.drv_vidc_set_mirror CVWL668.lib(drv_vidc.o) + 0x0001500c 0x0001500c 0x0000001c Code RO 1675 i.drv_vidc_set_pentile_swap CVWL668.lib(drv_vidc.o) + 0x00015028 0x00015028 0x0000000c Code RO 1676 i.drv_vidc_set_pu_ctrl CVWL668.lib(drv_vidc.o) + 0x00015034 0x00015034 0x00000018 Code RO 1677 i.drv_vidc_set_rotation CVWL668.lib(drv_vidc.o) + 0x0001504c 0x0001504c 0x0000000c Code RO 1678 i.drv_vidc_set_scld_hcoef0 CVWL668.lib(drv_vidc.o) + 0x00015058 0x00015058 0x0000000c Code RO 1679 i.drv_vidc_set_scld_hcoef1 CVWL668.lib(drv_vidc.o) + 0x00015064 0x00015064 0x00000014 Code RO 1680 i.drv_vidc_set_scld_step CVWL668.lib(drv_vidc.o) + 0x00015078 0x00015078 0x0000000c Code RO 1681 i.drv_vidc_set_scld_vcoef0 CVWL668.lib(drv_vidc.o) + 0x00015084 0x00015084 0x0000000c Code RO 1682 i.drv_vidc_set_scld_vcoef1 CVWL668.lib(drv_vidc.o) + 0x00015090 0x00015090 0x00000020 Code RO 1683 i.drv_vidc_set_src_parameter CVWL668.lib(drv_vidc.o) + 0x000150b0 0x000150b0 0x00000038 Code RO 1684 i.drv_vidc_set_vintp_config CVWL668.lib(drv_vidc.o) + 0x000150e8 0x000150e8 0x00000034 Code RO 684 i.fputc CVWL668.lib(tau_log.o) + 0x0001511c 0x0001511c 0x00000060 Code RO 116 i.google_p8p_demo p8p_demo.o + 0x0001517c 0x0001517c 0x00000040 Code RO 828 i.ha_intl_fb_check_pu_size CVWL668.lib(hal_internal_fb.o) + 0x000151bc 0x000151bc 0x00000040 Code RO 332 i.hal_dsi_rx_ctrl_create_handle CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x000151fc 0x000151fc 0x00000040 Code RO 333 i.hal_dsi_rx_ctrl_dcs_async_handler CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x0001523c 0x0001523c 0x00000094 Code RO 334 i.hal_dsi_rx_ctrl_deinit CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x000152d0 0x000152d0 0x00000020 Code RO 341 i.hal_dsi_rx_ctrl_get_max_ret_size CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x000152f0 0x000152f0 0x000000ac Code RO 342 i.hal_dsi_rx_ctrl_init CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x0001539c 0x0001539c 0x00000100 Code RO 343 i.hal_dsi_rx_ctrl_init_clk CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x0001549c 0x0001549c 0x00000108 Code RO 344 i.hal_dsi_rx_ctrl_init_dsi_rx CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x000155a4 0x000155a4 0x0000012c Code RO 345 i.hal_dsi_rx_ctrl_init_memc CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x000156d0 0x000156d0 0x00000148 Code RO 346 i.hal_dsi_rx_ctrl_init_rxbr CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015818 0x00015818 0x00000280 Code RO 347 i.hal_dsi_rx_ctrl_init_vidc CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015a98 0x00015a98 0x00000038 Code RO 348 i.hal_dsi_rx_ctrl_pre_init_pps CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015ad0 0x00015ad0 0x000000f0 Code RO 353 i.hal_dsi_rx_ctrl_send_ack_cmd CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015bc0 0x00015bc0 0x00000030 Code RO 360 i.hal_dsi_rx_ctrl_set_ipi_cfg CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015bf0 0x00015bf0 0x00000030 Code RO 366 i.hal_dsi_rx_ctrl_start CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015c20 0x00015c20 0x00000030 Code RO 367 i.hal_dsi_rx_ctrl_stop CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015c50 0x00015c50 0x00000020 Code RO 369 i.hal_dsi_rx_ctrl_toggle_resolution CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00015c70 0x00015c70 0x00000280 Code RO 422 i.hal_dsi_tx_cmd_mode_cal_timing CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00015ef0 0x00015ef0 0x00000038 Code RO 424 i.hal_dsi_tx_ctrl_create_handle CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00015f28 0x00015f28 0x00000074 Code RO 425 i.hal_dsi_tx_ctrl_deinit CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00015f9c 0x00015f9c 0x00000022 Code RO 428 i.hal_dsi_tx_ctrl_gen_a_tear_signal CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00015fbe 0x00015fbe 0x00000002 PAD + 0x00015fc0 0x00015fc0 0x0000007c Code RO 430 i.hal_dsi_tx_ctrl_init CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001603c 0x0001603c 0x00000010 Code RO 431 i.hal_dsi_tx_ctrl_init_clk CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001604c 0x0001604c 0x00000008 Code RO 444 i.hal_dsi_tx_ctrl_set_overwrite_rgb CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00016054 0x00016054 0x0000000a Code RO 445 i.hal_dsi_tx_ctrl_set_tear_mode CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001605e 0x0001605e 0x00000002 PAD + 0x00016060 0x00016060 0x00000090 Code RO 447 i.hal_dsi_tx_ctrl_start CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000160f0 0x000160f0 0x00000038 Code RO 448 i.hal_dsi_tx_ctrl_stop CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00016128 0x00016128 0x000000f4 Code RO 450 i.hal_dsi_tx_ctrl_write_array_cmd CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001621c 0x0001621c 0x000000d0 Code RO 451 i.hal_dsi_tx_ctrl_write_cmd CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000162ec 0x000162ec 0x00000104 Code RO 452 i.hal_dsi_tx_init_cfg CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000163f0 0x000163f0 0x00000044 Code RO 453 i.hal_dsi_tx_init_dpi_timing CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00016434 0x00016434 0x00000016 Code RO 454 i.hal_dsi_tx_init_phy_cfg CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001644a 0x0001644a 0x00000052 Code RO 455 i.hal_dsi_tx_init_timing CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001649c 0x0001649c 0x00000054 Code RO 456 i.hal_dsi_tx_init_vid_timing CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000164f0 0x000164f0 0x00000040 Code RO 457 i.hal_dsi_tx_send_cmd CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00016530 0x00016530 0x00000094 Code RO 458 i.hal_dsi_tx_timing_info_update CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000165c4 0x000165c4 0x00000310 Code RO 459 i.hal_dsi_tx_vid_mode_cal_timing CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000168d4 0x000168d4 0x0000003a Code RO 529 i.hal_gpio_config_pad CVWL668.lib(hal_gpio.o) + 0x0001690e 0x0001690e 0x00000002 PAD + 0x00016910 0x00016910 0x00000018 Code RO 530 i.hal_gpio_ctrl_eint CVWL668.lib(hal_gpio.o) + 0x00016928 0x00016928 0x00000040 Code RO 534 i.hal_gpio_init_eint CVWL668.lib(hal_gpio.o) + 0x00016968 0x00016968 0x00000016 Code RO 535 i.hal_gpio_init_input CVWL668.lib(hal_gpio.o) + 0x0001697e 0x0001697e 0x0000001c Code RO 536 i.hal_gpio_init_output CVWL668.lib(hal_gpio.o) + 0x0001699a 0x0001699a 0x00000002 PAD + 0x0001699c 0x0001699c 0x0000001c Code RO 537 i.hal_gpio_reg_eint_cb CVWL668.lib(hal_gpio.o) + 0x000169b8 0x000169b8 0x00000050 Code RO 538 i.hal_gpio_set_ap_reset_int CVWL668.lib(hal_gpio.o) + 0x00016a08 0x00016a08 0x00000060 Code RO 541 i.hal_gpio_set_mode CVWL668.lib(hal_gpio.o) + 0x00016a68 0x00016a68 0x00000008 Code RO 542 i.hal_gpio_set_output_data CVWL668.lib(hal_gpio.o) + 0x00016a70 0x00016a70 0x00000010 Code RO 736 i.hal_internal_sync_get_hight_performan_mode CVWL668.lib(hal_internal_vsync.o) + 0x00016a80 0x00016a80 0x000001b4 Code RO 737 i.hal_internal_sync_input_resolution_change CVWL668.lib(hal_internal_vsync.o) + 0x00016c34 0x00016c34 0x0000000c Code RO 738 i.hal_internal_sync_register_lcdc_cb CVWL668.lib(hal_internal_vsync.o) + 0x00016c40 0x00016c40 0x00000020 Code RO 741 i.hal_internal_vsync_deinit CVWL668.lib(hal_internal_vsync.o) + 0x00016c60 0x00016c60 0x0000000c Code RO 742 i.hal_internal_vsync_get_rx_state CVWL668.lib(hal_internal_vsync.o) + 0x00016c6c 0x00016c6c 0x00000014 Code RO 743 i.hal_internal_vsync_get_sync_line CVWL668.lib(hal_internal_vsync.o) + 0x00016c80 0x00016c80 0x0000000c Code RO 744 i.hal_internal_vsync_get_tx_state CVWL668.lib(hal_internal_vsync.o) + 0x00016c8c 0x00016c8c 0x000000e8 Code RO 745 i.hal_internal_vsync_init_rx CVWL668.lib(hal_internal_vsync.o) + 0x00016d74 0x00016d74 0x000000c8 Code RO 746 i.hal_internal_vsync_init_tx CVWL668.lib(hal_internal_vsync.o) + 0x00016e3c 0x00016e3c 0x00000020 Code RO 747 i.hal_internal_vsync_set_rx_state CVWL668.lib(hal_internal_vsync.o) + 0x00016e5c 0x00016e5c 0x000001ec Code RO 749 i.hal_internal_vsync_set_tear_mode CVWL668.lib(hal_internal_vsync.o) + 0x00017048 0x00017048 0x00000058 Code RO 750 i.hal_internal_vsync_set_tx_state CVWL668.lib(hal_internal_vsync.o) + 0x000170a0 0x000170a0 0x0000006c Code RO 801 i.hal_intl_dcs_init_sw_fltr CVWL668.lib(hal_internal_dcs.o) + 0x0001710c 0x0001710c 0x00000430 Code RO 803 i.hal_intl_dcs_rx_get_dcs_packet_data CVWL668.lib(hal_internal_dcs.o) + 0x0001753c 0x0001753c 0x00000088 Code RO 804 i.hal_intl_dcs_rx_receive_packet CVWL668.lib(hal_internal_dcs.o) + 0x000175c4 0x000175c4 0x00000174 Code RO 805 i.hal_intl_dcs_rx_receive_pps CVWL668.lib(hal_internal_dcs.o) + 0x00017738 0x00017738 0x0000008c Code RO 806 i.hal_intl_dcs_set_auto_hw_filter CVWL668.lib(hal_internal_dcs.o) + 0x000177c4 0x000177c4 0x0000002c Code RO 808 i.hal_intl_dcs_sw_filter_handle CVWL668.lib(hal_internal_dcs.o) + 0x000177f0 0x000177f0 0x00000318 Code RO 829 i.hal_intl_fb_cal_fb_info CVWL668.lib(hal_internal_fb.o) + 0x00017b08 0x00017b08 0x00000064 Code RO 830 i.hal_intl_fb_check_bandwidth CVWL668.lib(hal_internal_fb.o) + 0x00017b6c 0x00017b6c 0x000000dc Code RO 831 i.hal_intl_fb_edge_resize CVWL668.lib(hal_internal_fb.o) + 0x00017c48 0x00017c48 0x00000074 Code RO 832 i.hal_intl_fb_flow_control_adapter CVWL668.lib(hal_internal_fb.o) + 0x00017cbc 0x00017cbc 0x0000000c Code RO 833 i.hal_intl_fb_get_memc_flow_mode CVWL668.lib(hal_internal_fb.o) + 0x00017cc8 0x00017cc8 0x00000010 Code RO 834 i.hal_intl_fb_get_rx_fb_info CVWL668.lib(hal_internal_fb.o) + 0x00017cd8 0x00017cd8 0x00000010 Code RO 835 i.hal_intl_fb_get_tx_fb_info CVWL668.lib(hal_internal_fb.o) + 0x00017ce8 0x00017ce8 0x0000000c Code RO 836 i.hal_intl_fb_get_user_flow CVWL668.lib(hal_internal_fb.o) + 0x00017cf4 0x00017cf4 0x00000028 Code RO 854 i.hal_intl_svs_deinit_rx CVWL668.lib(hal_internal_svs.o) + 0x00017d1c 0x00017d1c 0x00000010 Code RO 855 i.hal_intl_svs_deinit_tx CVWL668.lib(hal_internal_svs.o) + 0x00017d2c 0x00017d2c 0x00000024 Code RO 856 i.hal_intl_svs_handle CVWL668.lib(hal_internal_svs.o) + 0x00017d50 0x00017d50 0x00000080 Code RO 857 i.hal_intl_svs_init_rx CVWL668.lib(hal_internal_svs.o) + 0x00017dd0 0x00017dd0 0x00000014 Code RO 858 i.hal_intl_svs_init_tx CVWL668.lib(hal_internal_svs.o) + 0x00017de4 0x00017de4 0x0000000c Code RO 860 i.hal_intl_svs_set_rx_vtt CVWL668.lib(hal_internal_svs.o) + 0x00017df0 0x00017df0 0x00000048 Code RO 862 i.hal_intl_svs_update_rxbr_clk CVWL668.lib(hal_internal_svs.o) + 0x00017e38 0x00017e38 0x00000070 Code RO 460 i.hal_lcdc_displayproc_config CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00017ea8 0x00017ea8 0x0000003e Code RO 461 i.hal_lcdc_init_cfg CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00017ee6 0x00017ee6 0x00000070 Code RO 462 i.hal_lcdc_init_clk CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00017f56 0x00017f56 0x00000002 PAD + 0x00017f58 0x00017f58 0x00000128 Code RO 463 i.hal_lcdc_postproc_config CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00018080 0x00018080 0x00000024 Code RO 464 i.hal_lcdc_start CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000180a4 0x000180a4 0x0000003c Code RO 465 i.hal_lcdc_timinggen_config CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000180e0 0x000180e0 0x000000e0 Code RO 466 i.hal_lcdc_upscaler_config CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000181c0 0x000181c0 0x000000bc Code RO 468 i.hal_nonshadow_func_update CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001827c 0x0001827c 0x0000002a Code RO 633 i.hal_pwr_enter_deep_sleep_mode CVWL668.lib(hal_pwr.o) + 0x000182a6 0x000182a6 0x00000008 Code RO 634 i.hal_pwr_enter_normal_sleep_mode CVWL668.lib(hal_pwr.o) + 0x000182ae 0x000182ae 0x00000002 PAD + 0x000182b0 0x000182b0 0x00000064 Code RO 635 i.hal_pwr_enter_stop_sleep_mode CVWL668.lib(hal_pwr.o) + 0x00018314 0x00018314 0x0000000a Code RO 636 i.hal_pwr_exit_sleep_mode CVWL668.lib(hal_pwr.o) + 0x0001831e 0x0001831e 0x00000008 Code RO 638 i.hal_pwr_get_vcc_power_ready CVWL668.lib(hal_pwr.o) + 0x00018326 0x00018326 0x00000008 Code RO 643 i.hal_pwr_set_main_power CVWL668.lib(hal_pwr.o) + 0x0001832e 0x0001832e 0x00000008 Code RO 645 i.hal_pwr_set_sleep_mode_power CVWL668.lib(hal_pwr.o) + 0x00018336 0x00018336 0x00000002 PAD + 0x00018338 0x00018338 0x00000064 Code RO 646 i.hal_pwr_set_stop_sleep_wakeup_pin CVWL668.lib(hal_pwr.o) + 0x0001839c 0x0001839c 0x00000040 Code RO 569 i.hal_swire_deinit CVWL668.lib(hal_swire.o) + 0x000183dc 0x000183dc 0x0000005c Code RO 570 i.hal_swire_enable CVWL668.lib(hal_swire.o) + 0x00018438 0x00018438 0x00000058 Code RO 571 i.hal_swire_init CVWL668.lib(hal_swire.o) + 0x00018490 0x00018490 0x00000024 Code RO 573 i.hal_swire_set_pulse CVWL668.lib(hal_swire.o) + 0x000184b4 0x000184b4 0x00000040 Code RO 574 i.hal_swire_set_timer CVWL668.lib(hal_swire.o) + 0x000184f4 0x000184f4 0x000000e4 Code RO 594 i.hal_system_init CVWL668.lib(hal_system.o) + 0x000185d8 0x000185d8 0x00000050 Code RO 597 i.hal_system_updata_sysclk CVWL668.lib(hal_system.o) + 0x00018628 0x00018628 0x00000030 Code RO 612 i.hal_timer_deinit CVWL668.lib(hal_timer.o) + 0x00018658 0x00018658 0x0000001c Code RO 614 i.hal_timer_init CVWL668.lib(hal_timer.o) + 0x00018674 0x00018674 0x00000008 Code RO 615 i.hal_timer_set_repeat CVWL668.lib(hal_timer.o) + 0x0001867c 0x0001867c 0x00000030 Code RO 469 i.hal_tx_frame_rate_adjust CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000186ac 0x000186ac 0x00000094 Code RO 708 i.hal_uart_init CVWL668.lib(hal_uart.o) + 0x00018740 0x00018740 0x0000001c Code RO 711 i.hal_uart_send_blocking CVWL668.lib(hal_uart.o) + 0x0001875c 0x0001875c 0x00000018 Code RO 470 i.hal_vsync_func_update CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x00018774 0x00018774 0x000000e0 Code RO 752 i.hal_vsync_reset_lcdc_scaler CVWL668.lib(hal_internal_vsync.o) + 0x00018854 0x00018854 0x00000040 Code RO 3 i.main main.o + 0x00018894 0x00018894 0x0000007c Code RO 117 i.pps_update_handle p8p_demo.o + 0x00018910 0x00018910 0x000002f4 Code RO 753 i.rxbr_irq1_callback CVWL668.lib(hal_internal_vsync.o) + 0x00018c04 0x00018c04 0x0000003a Code RO 118 i.send_panel_init_code p8p_demo.o + 0x00018c3e 0x00018c3e 0x00000002 PAD + 0x00018c40 0x00018c40 0x00000044 Code RO 754 i.soft_double_buffer_update CVWL668.lib(hal_internal_vsync.o) + 0x00018c84 0x00018c84 0x0000006c Code RO 755 i.soft_gen_te CVWL668.lib(hal_internal_vsync.o) + 0x00018cf0 0x00018cf0 0x000000e0 Code RO 756 i.soft_gen_te_double_buffer CVWL668.lib(hal_internal_vsync.o) + 0x00018dd0 0x00018dd0 0x00000038 Code RO 757 i.soft_pro_motion_init CVWL668.lib(hal_internal_vsync.o) + 0x00018e08 0x00018e08 0x00000024 Code RO 758 i.soft_tear_adjust_line CVWL668.lib(hal_internal_vsync.o) + 0x00018e2c 0x00018e2c 0x00000018 Code RO 649 i.stop_sleep_cb CVWL668.lib(hal_pwr.o) + 0x00018e44 0x00018e44 0x000000ac Code RO 863 i.svs_direct_mode_setting CVWL668.lib(hal_internal_svs.o) + 0x00018ef0 0x00018ef0 0x0000001c Code RO 864 i.svs_get_rel_intv CVWL668.lib(hal_internal_svs.o) + 0x00018f0c 0x00018f0c 0x000000b0 Code RO 865 i.svs_sync_handle CVWL668.lib(hal_internal_svs.o) + 0x00018fbc 0x00018fbc 0x000000cc Code RO 866 i.svs_wait_fr_stab CVWL668.lib(hal_internal_svs.o) + 0x00019088 0x00019088 0x0000010c Code RO 867 i.svs_wait_start CVWL668.lib(hal_internal_svs.o) + 0x00019194 0x00019194 0x00000034 Code RO 685 i.tau_log_init CVWL668.lib(tau_log.o) + 0x000191c8 0x000191c8 0x00000084 Code RO 686 i.tau_log_printf CVWL668.lib(tau_log.o) + 0x0001924c 0x0001924c 0x00000076 Code RO 687 i.tau_log_push_log CVWL668.lib(tau_log.o) + 0x000192c2 0x000192c2 0x00000002 PAD + 0x000192c4 0x000192c4 0x000000b4 Code RO 759 i.vidc_callback CVWL668.lib(hal_internal_vsync.o) + 0x00019378 0x00019378 0x00000118 Code RO 760 i.vpre_err_reset CVWL668.lib(hal_internal_vsync.o) + 0x00019490 0x00019490 0x000020bc Data RO 121 .constdata p8p_demo.o + 0x0001b54c 0x0001b54c 0x00000028 Data RO 372 .constdata CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x0001b574 0x0001b574 0x0000001c Data RO 473 .constdata CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x0001b590 0x0001b590 0x000000b6 Data RO 546 .constdata CVWL668.lib(hal_gpio.o) + 0x0001b646 0x0001b646 0x00000002 PAD + 0x0001b648 0x0001b648 0x00000030 Data RO 713 .constdata CVWL668.lib(hal_uart.o) + 0x0001b678 0x0001b678 0x00000010 Data RO 1814 .constdata CVWL668.lib(drv_uart.o) + 0x0001b688 0x0001b688 0x00000042 Data RO 373 .conststring CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x0001b6ca 0x0001b6ca 0x00000002 PAD + 0x0001b6cc 0x0001b6cc 0x00000090 Data RO 762 .conststring CVWL668.lib(hal_internal_vsync.o) + 0x0001b75c 0x0001b75c 0x00000046 Data RO 811 .conststring CVWL668.lib(hal_internal_dcs.o) + 0x0001b7a2 0x0001b7a2 0x00000002 PAD + 0x0001b7a4 0x0001b7a4 0x00000020 Data RO 2228 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Exec base: 0x00070000, Load base: 0x0001b7c4, Size: 0x00003188, Max: 0x00008000, ABSOLUTE, COMPRESSED[0x0000016c]) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x00070000 COMPRESSED 0x0000011f Data RW 122 .data p8p_demo.o + 0x0007011f COMPRESSED 0x00000001 PAD + 0x00070120 COMPRESSED 0x00000030 Data RW 374 .data CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x00070150 COMPRESSED 0x0000005c Data RW 474 .data CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000701ac COMPRESSED 0x00000002 Data RW 576 .data CVWL668.lib(hal_swire.o) + 0x000701ae COMPRESSED 0x00000002 PAD + 0x000701b0 COMPRESSED 0x00000008 Data RW 650 .data CVWL668.lib(hal_pwr.o) + 0x000701b8 COMPRESSED 0x00000001 Data RW 690 .data CVWL668.lib(tau_log.o) + 0x000701b9 COMPRESSED 0x00000003 PAD + 0x000701bc COMPRESSED 0x00000018 Data RW 714 .data CVWL668.lib(hal_uart.o) + 0x000701d4 COMPRESSED 0x00000010 Data RW 763 .data CVWL668.lib(hal_internal_vsync.o) + 0x000701e4 COMPRESSED 0x00000024 Data RW 812 .data CVWL668.lib(hal_internal_dcs.o) + 0x00070208 COMPRESSED 0x0000000c Data RW 896 .data CVWL668.lib(drv_common.o) + 0x00070214 COMPRESSED 0x00000001 Data RW 897 .data CVWL668.lib(drv_common.o) + 0x00070215 COMPRESSED 0x00000003 PAD + 0x00070218 COMPRESSED 0x00000004 Data RW 983 .data CVWL668.lib(drv_gpio.o) + 0x0007021c COMPRESSED 0x00000004 Data RW 1135 .data CVWL668.lib(drv_swire.o) + 0x00070220 COMPRESSED 0x00000050 Data RW 1183 .data CVWL668.lib(drv_timer.o) + 0x00070270 COMPRESSED 0x00000004 Data RW 1224 .data CVWL668.lib(drv_se.o) + 0x00070274 COMPRESSED 0x00000001 Data RW 1264 .data CVWL668.lib(drv_dsi_rx.o) + 0x00070275 COMPRESSED 0x00000003 PAD + 0x00070278 COMPRESSED 0x00000008 Data RW 1599 .data CVWL668.lib(drv_rxbr.o) + 0x00070280 COMPRESSED 0x00000004 Data RW 1686 .data CVWL668.lib(drv_vidc.o) + 0x00070284 COMPRESSED 0x00000190 Data RW 1761 .data CVWL668.lib(drv_dma.o) + 0x00070414 COMPRESSED 0x00000004 Data RW 2204 .data mc_p.l(stdout.o) + 0x00070418 - 0x000000d0 Zero RW 371 .bss CVWL668.lib(hal_dsi_rx_ctrl.o) + 0x000704e8 - 0x000000b8 Zero RW 472 .bss CVWL668.lib(hal_dsi_tx_ctrl.o) + 0x000705a0 - 0x00000100 Zero RW 689 .bss CVWL668.lib(tau_log.o) + 0x000706a0 - 0x00000044 Zero RW 761 .bss CVWL668.lib(hal_internal_vsync.o) + 0x000706e4 - 0x00000800 Zero RW 809 .bss CVWL668.lib(hal_internal_dcs.o) + 0x00070ee4 - 0x000000ff Zero RW 810 .bss CVWL668.lib(hal_internal_dcs.o) + 0x00070fe3 COMPRESSED 0x00000001 PAD + 0x00070fe4 - 0x00000044 Zero RW 838 .bss CVWL668.lib(hal_internal_fb.o) + 0x00071028 - 0x00000044 Zero RW 868 .bss CVWL668.lib(hal_internal_svs.o) + 0x0007106c - 0x00000040 Zero RW 982 .bss CVWL668.lib(drv_gpio.o) + 0x000710ac - 0x0000106c Zero RW 1207 .bss CVWL668.lib(dcs_packet_fifo.o) + 0x00072118 - 0x00000010 Zero RW 1759 .bss CVWL668.lib(drv_dma.o) + 0x00072128 - 0x00000060 Zero RW 1813 .bss CVWL668.lib(drv_uart.o) + 0x00072188 - 0x00001000 Zero RW 321 STACK startup_armcm0.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 24 4 0 0 0 577 board.o + 64 32 0 0 0 10471 main.o + 2890 824 8380 287 0 31276 p8p_demo.o + 120 18 192 0 4096 2164 startup_armcm0.o + + ---------------------------------------------------------------------- + 3104 878 8604 288 4096 44488 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 6 0 0 1 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 216 32 0 0 4204 252 dcs_packet_fifo.o + 104 62 28 13 0 192 drv_common.o + 536 90 0 0 0 792 drv_crgu.o + 136 22 0 400 16 196 drv_dma.o + 144 34 0 0 0 248 drv_dsc_dec.o + 1904 682 0 1 0 1340 drv_dsi_rx.o + 1704 306 0 0 0 2036 drv_dsi_tx.o + 148 0 0 0 0 260 drv_efuse.o + 296 40 0 4 64 1000 drv_gpio.o + 1080 166 0 0 0 1620 drv_lcdc.o + 658 104 0 0 0 1240 drv_memc.o + 40 0 0 0 0 120 drv_phy_common.o + 592 132 0 0 0 716 drv_pwr.o + 514 102 0 8 0 1120 drv_rxbr.o + 972 266 0 4 0 488 drv_se.o + 264 54 0 4 0 560 drv_swire.o + 220 40 0 0 0 428 drv_sys_cfg.o + 366 38 0 80 0 816 drv_timer.o + 1172 54 16 0 96 980 drv_uart.o + 824 152 0 4 0 1700 drv_vidc.o + 2766 204 106 48 208 1256 hal_dsi_rx_ctrl.o + 4330 338 50 92 184 2212 hal_dsi_tx_ctrl.o + 440 32 182 0 0 688 hal_gpio.o + 2140 506 70 36 2303 652 hal_internal_dcs.o + 1348 58 0 0 68 700 hal_internal_fb.o + 1172 182 0 0 68 840 hal_internal_svs.o + 3840 802 144 16 68 1688 hal_internal_vsync.o + 308 32 0 8 0 616 hal_pwr.o + 344 32 0 2 0 348 hal_swire.o + 308 56 0 0 0 136 hal_system.o + 84 0 0 0 0 204 hal_timer.o + 176 18 48 24 0 144 hal_uart.o + 68 4 0 0 0 136 tau_delay.o + 354 30 16 1 256 320 tau_log.o + 200 20 0 0 0 76 ceil.o + 86 0 0 0 0 0 __dczerorl2.o + 0 0 0 0 0 0 entry.o + 0 0 0 0 0 0 entry10a.o + 0 0 0 0 0 0 entry11a.o + 8 4 0 0 0 0 entry2.o + 4 0 0 0 0 0 entry5.o + 0 0 0 0 0 0 entry7b.o + 0 0 0 0 0 0 entry8b.o + 8 4 0 0 0 0 entry9a.o + 30 0 0 0 0 0 handlers.o + 40 0 0 0 0 72 idiv.o + 36 8 0 0 0 68 init.o + 0 0 0 0 0 0 iusefp.o + 32 0 0 0 0 68 llshl.o + 38 0 0 0 0 68 llsshr.o + 34 0 0 0 0 68 llushr.o + 26 0 0 0 0 72 memcmp.o + 36 0 0 0 0 60 memcpya.o + 36 0 0 0 0 100 memseta.o + 2298 104 0 0 0 544 printfa.o + 0 0 0 4 0 0 stdout.o + 14 0 0 0 0 60 strlen.o + 44 0 0 0 0 72 uidiv.o + 96 0 0 0 0 84 uldiv.o + 40 2 0 0 0 68 cdrcmple.o + 20 0 0 0 0 68 cfcmple.o + 20 0 0 0 0 68 cfrcmple.o + 56 0 0 0 0 68 d2f.o + 356 4 0 0 0 140 dadd.o + 240 6 0 0 0 84 ddiv.o + 236 0 0 0 0 216 depilogue.o + 60 10 0 0 0 68 dfixui.o + 64 10 0 0 0 68 dfixul.o + 28 4 0 0 0 68 dfltui.o + 208 6 0 0 0 88 dmul.o + 40 0 0 0 0 60 f2d.o + 178 0 0 0 0 108 fadd.o + 124 0 0 0 0 72 fdiv.o + 130 0 0 0 0 144 fepilogue.o + 40 0 0 0 0 60 ffixui.o + 14 0 0 0 0 68 ffltui.o + 122 0 0 0 0 72 fmul.o + 24 0 0 0 0 60 fscalb.o + + ---------------------------------------------------------------------- + 34668 4852 668 760 7536 29104 Library Totals + 34 0 8 11 1 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 29568 4670 660 745 7535 26044 CVWL668.lib + 200 20 0 0 0 76 m_ps.l + 2866 120 0 4 0 1336 mc_p.l + 2000 42 0 0 0 1648 mf_p.l + + ---------------------------------------------------------------------- + 34668 4852 668 760 7536 29104 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 37772 5730 9272 1048 11632 54124 Grand Totals + 37772 5730 9272 364 11632 54124 ELF Image Totals (compressed) + 37772 5730 9272 364 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 47044 ( 45.94kB) + Total RW Size (RW Data + ZI Data) 12680 ( 12.38kB) + Total ROM Size (Code + RO Data + RW Data) 47408 ( 46.30kB) + +============================================================================== + diff --git a/project/WL668/Listings/board._ip b/project/WL668/Listings/board._ip new file mode 100644 index 0000000..5880e20 --- /dev/null +++ b/project/WL668/Listings/board._ip @@ -0,0 +1,6 @@ +..\..\src\board\board.c -E --c99 --gnu -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I ..\..\src -I ..\..\src\board -I ..\..\src\common -I ..\..\src\sdk\include -I ..\..\src\sdk\include\M0 -I ..\..\src\app -I ..\..\src\app\S8 -I ..\..\src\app\touch -I ..\..\src\app\module_demo -I ..\..\src\app\P8P +-I.\RTE\_WL668 +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include +-D__UVISION_VERSION="528" -D_RTE_ -DARMCM0 +-o .\listings\board.i --list_dir ".\\Listings\\" --list \ No newline at end of file diff --git a/project/WL668/Listings/board.i b/project/WL668/Listings/board.i new file mode 100644 index 0000000..de24ffc --- /dev/null +++ b/project/WL668/Listings/board.i @@ -0,0 +1,4677 @@ +# 1 "..\\..\\src\\board\\board.c" + + + + + + + + + +# 1 "..\\..\\src\\board\\board.h" + + + + + + + + + + + + + + + + + + +void board_Init(void); + +# 11 "..\\..\\src\\board\\board.c" +# 1 "..\\..\\src\\sdk\\include\\hal_system.h" + + + + + + + + + + + + + + +# 1 "..\\..\\src\\common\\tau_common.h" + + + + + + + + + + + + + + + + +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + + + + + + + + + +# 27 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + + + +# 46 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + +typedef signed char int8_t; +typedef signed short int int16_t; +typedef signed int int32_t; +typedef signed __int64 int64_t; + + +typedef unsigned char uint8_t; +typedef unsigned short int uint16_t; +typedef unsigned int uint32_t; +typedef unsigned __int64 uint64_t; + + + + + +typedef signed char int_least8_t; +typedef signed short int int_least16_t; +typedef signed int int_least32_t; +typedef signed __int64 int_least64_t; + + +typedef unsigned char uint_least8_t; +typedef unsigned short int uint_least16_t; +typedef unsigned int uint_least32_t; +typedef unsigned __int64 uint_least64_t; + + + + +typedef signed int int_fast8_t; +typedef signed int int_fast16_t; +typedef signed int int_fast32_t; +typedef signed __int64 int_fast64_t; + + +typedef unsigned int uint_fast8_t; +typedef unsigned int uint_fast16_t; +typedef unsigned int uint_fast32_t; +typedef unsigned __int64 uint_fast64_t; + + + + + + +typedef signed int intptr_t; +typedef unsigned int uintptr_t; + + + +typedef signed long long intmax_t; +typedef unsigned long long uintmax_t; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 216 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + + + + + + + + + +# 241 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 305 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + +# 18 "..\\..\\src\\common\\tau_common.h" +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 61 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + +# 75 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 112 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + + + + + + + + + +extern __attribute__((__pcs__("aapcs"))) unsigned __ARM_dcmp4(double , double ); +extern __attribute__((__pcs__("aapcs"))) unsigned __ARM_fcmp4(float , float ); + + + + + + + +extern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassifyf(float ); +extern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassify(double ); + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinitef(float __x) +{ + return (((*(unsigned *)&(__x)) >> 23) & 0xff) != 0xff; +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinite(double __x) +{ + return (((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff) != 0x7ff; +} + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinff(float __x) +{ + return ((*(unsigned *)&(__x)) << 1) == 0xff000000; +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinf(double __x) +{ + return (((*(1 + (unsigned *)&(__x))) << 1) == 0xffe00000) && ((*(unsigned *)&(__x)) == 0); +} + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreaterf(float __x, float __y) +{ + unsigned __f = __ARM_fcmp4(__x, __y) >> 28; + return (__f == 8) || (__f == 2); +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreater(double __x, double __y) +{ + unsigned __f = __ARM_dcmp4(__x, __y) >> 28; + return (__f == 8) || (__f == 2); +} + + + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnanf(float __x) +{ + return (0x7f800000 - ((*(unsigned *)&(__x)) & 0x7fffffff)) >> 31; +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnan(double __x) +{ + unsigned __xf = (*(1 + (unsigned *)&(__x))) | (((*(unsigned *)&(__x)) == 0) ? 0 : 1); + return (0x7ff00000 - (__xf & 0x7fffffff)) >> 31; +} + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormalf(float __x) +{ + unsigned __xe = ((*(unsigned *)&(__x)) >> 23) & 0xff; + return (__xe != 0xff) && (__xe != 0); +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormal(double __x) +{ + unsigned __xe = ((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff; + return (__xe != 0x7ff) && (__xe != 0); +} + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbitf(float __x) +{ + return (*(unsigned *)&(__x)) >> 31; +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbit(double __x) +{ + return (*(1 + (unsigned *)&(__x))) >> 31; +} + + + + + + + + + + +# 230 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + typedef float float_t; + typedef double double_t; +# 251 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + +extern const int math_errhandling; +# 261 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + +extern __declspec(__nothrow) double acos(double ); + + + +extern __declspec(__nothrow) double asin(double ); + + + + + +extern __declspec(__nothrow) __attribute__((const)) double atan(double ); + + + +extern __declspec(__nothrow) double atan2(double , double ); + + + + + +extern __declspec(__nothrow) double cos(double ); + + + + +extern __declspec(__nothrow) double sin(double ); + + + + + +extern void __use_accurate_range_reduction(void); + + + +extern __declspec(__nothrow) double tan(double ); + + + + + +extern __declspec(__nothrow) double cosh(double ); + + + + +extern __declspec(__nothrow) double sinh(double ); + + + + + + +extern __declspec(__nothrow) __attribute__((const)) double tanh(double ); + + + +extern __declspec(__nothrow) double exp(double ); + + + + + + +extern __declspec(__nothrow) double frexp(double , int * ) __attribute__((__nonnull__(2))); + + + + + + + +extern __declspec(__nothrow) double ldexp(double , int ); + + + + +extern __declspec(__nothrow) double log(double ); + + + + + +extern __declspec(__nothrow) double log10(double ); + + + +extern __declspec(__nothrow) double modf(double , double * ) __attribute__((__nonnull__(2))); + + + + + +extern __declspec(__nothrow) double pow(double , double ); + + + + + + +extern __declspec(__nothrow) double sqrt(double ); + + + + + + + + static __inline double _sqrt(double __x) { return sqrt(__x); } + + + + + static __inline float _sqrtf(float __x) { return (float)sqrt(__x); } + + + + + + + +extern __declspec(__nothrow) __attribute__((const)) double ceil(double ); + + +extern __declspec(__nothrow) __attribute__((const)) double fabs(double ); + + + +extern __declspec(__nothrow) __attribute__((const)) double floor(double ); + + + +extern __declspec(__nothrow) double fmod(double , double ); + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) double acosh(double ); + + + +extern __declspec(__nothrow) double asinh(double ); + + + +extern __declspec(__nothrow) double atanh(double ); + + + +extern __declspec(__nothrow) double cbrt(double ); + + + +static __inline __declspec(__nothrow) __attribute__((const)) double copysign(double __x, double __y) + + + +{ + (*(1 + (unsigned *)&(__x))) = ((*(1 + (unsigned *)&(__x))) & 0x7fffffff) | ((*(1 + (unsigned *)&(__y))) & 0x80000000); + return __x; +} +static __inline __declspec(__nothrow) __attribute__((const)) float copysignf(float __x, float __y) + + + +{ + (*(unsigned *)&(__x)) = ((*(unsigned *)&(__x)) & 0x7fffffff) | ((*(unsigned *)&(__y)) & 0x80000000); + return __x; +} +extern __declspec(__nothrow) double erf(double ); + + + +extern __declspec(__nothrow) double erfc(double ); + + + +extern __declspec(__nothrow) double expm1(double ); + + + + + + + + + + + + + + + +# 479 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + +extern __declspec(__nothrow) double hypot(double , double ); + + + + + + +extern __declspec(__nothrow) int ilogb(double ); + + + +extern __declspec(__nothrow) int ilogbf(float ); + + + +extern __declspec(__nothrow) int ilogbl(long double ); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) double lgamma (double ); + + + + +extern __declspec(__nothrow) double log1p(double ); + + + +extern __declspec(__nothrow) double logb(double ); + + + +extern __declspec(__nothrow) float logbf(float ); + + + +extern __declspec(__nothrow) long double logbl(long double ); + + + +extern __declspec(__nothrow) double nextafter(double , double ); + + + + +extern __declspec(__nothrow) float nextafterf(float , float ); + + + + +extern __declspec(__nothrow) long double nextafterl(long double , long double ); + + + + +extern __declspec(__nothrow) double nexttoward(double , long double ); + + + + +extern __declspec(__nothrow) float nexttowardf(float , long double ); + + + + +extern __declspec(__nothrow) long double nexttowardl(long double , long double ); + + + + +extern __declspec(__nothrow) double remainder(double , double ); + + + +extern __declspec(__nothrow) __attribute__((const)) double rint(double ); + + + +extern __declspec(__nothrow) double scalbln(double , long int ); + + + +extern __declspec(__nothrow) float scalblnf(float , long int ); + + + +extern __declspec(__nothrow) long double scalblnl(long double , long int ); + + + +extern __declspec(__nothrow) double scalbn(double , int ); + + + +extern __declspec(__nothrow) float scalbnf(float , int ); + + + +extern __declspec(__nothrow) long double scalbnl(long double , int ); + + + + + + + + + + + + + + +extern __declspec(__nothrow) __attribute__((const)) float _fabsf(float); +static __inline __declspec(__nothrow) __attribute__((const)) float fabsf(float __f) { return _fabsf(__f); } +extern __declspec(__nothrow) float sinf(float ); +extern __declspec(__nothrow) float cosf(float ); +extern __declspec(__nothrow) float tanf(float ); +extern __declspec(__nothrow) float acosf(float ); +extern __declspec(__nothrow) float asinf(float ); +extern __declspec(__nothrow) float atanf(float ); +extern __declspec(__nothrow) float atan2f(float , float ); +extern __declspec(__nothrow) float sinhf(float ); +extern __declspec(__nothrow) float coshf(float ); +extern __declspec(__nothrow) float tanhf(float ); +extern __declspec(__nothrow) float expf(float ); +extern __declspec(__nothrow) float logf(float ); +extern __declspec(__nothrow) float log10f(float ); +extern __declspec(__nothrow) float powf(float , float ); +extern __declspec(__nothrow) float sqrtf(float ); +extern __declspec(__nothrow) float ldexpf(float , int ); +extern __declspec(__nothrow) float frexpf(float , int * ) __attribute__((__nonnull__(2))); +extern __declspec(__nothrow) __attribute__((const)) float ceilf(float ); +extern __declspec(__nothrow) __attribute__((const)) float floorf(float ); +extern __declspec(__nothrow) float fmodf(float , float ); +extern __declspec(__nothrow) float modff(float , float * ) __attribute__((__nonnull__(2))); + + + + + + + + + + + + + + + + + +__declspec(__nothrow) long double acosl(long double ); +__declspec(__nothrow) long double asinl(long double ); +__declspec(__nothrow) long double atanl(long double ); +__declspec(__nothrow) long double atan2l(long double , long double ); +__declspec(__nothrow) long double ceill(long double ); +__declspec(__nothrow) long double cosl(long double ); +__declspec(__nothrow) long double coshl(long double ); +__declspec(__nothrow) long double expl(long double ); +__declspec(__nothrow) long double fabsl(long double ); +__declspec(__nothrow) long double floorl(long double ); +__declspec(__nothrow) long double fmodl(long double , long double ); +__declspec(__nothrow) long double frexpl(long double , int* ) __attribute__((__nonnull__(2))); +__declspec(__nothrow) long double ldexpl(long double , int ); +__declspec(__nothrow) long double logl(long double ); +__declspec(__nothrow) long double log10l(long double ); +__declspec(__nothrow) long double modfl(long double , long double * ) __attribute__((__nonnull__(2))); +__declspec(__nothrow) long double powl(long double , long double ); +__declspec(__nothrow) long double sinl(long double ); +__declspec(__nothrow) long double sinhl(long double ); +__declspec(__nothrow) long double sqrtl(long double ); +__declspec(__nothrow) long double tanl(long double ); +__declspec(__nothrow) long double tanhl(long double ); + + + + + + +extern __declspec(__nothrow) float acoshf(float ); +__declspec(__nothrow) long double acoshl(long double ); +extern __declspec(__nothrow) float asinhf(float ); +__declspec(__nothrow) long double asinhl(long double ); +extern __declspec(__nothrow) float atanhf(float ); +__declspec(__nothrow) long double atanhl(long double ); +__declspec(__nothrow) long double copysignl(long double , long double ); +extern __declspec(__nothrow) float cbrtf(float ); +__declspec(__nothrow) long double cbrtl(long double ); +extern __declspec(__nothrow) float erff(float ); +__declspec(__nothrow) long double erfl(long double ); +extern __declspec(__nothrow) float erfcf(float ); +__declspec(__nothrow) long double erfcl(long double ); +extern __declspec(__nothrow) float expm1f(float ); +__declspec(__nothrow) long double expm1l(long double ); +extern __declspec(__nothrow) float log1pf(float ); +__declspec(__nothrow) long double log1pl(long double ); +extern __declspec(__nothrow) float hypotf(float , float ); +__declspec(__nothrow) long double hypotl(long double , long double ); +extern __declspec(__nothrow) float lgammaf(float ); +__declspec(__nothrow) long double lgammal(long double ); +extern __declspec(__nothrow) float remainderf(float , float ); +__declspec(__nothrow) long double remainderl(long double , long double ); +extern __declspec(__nothrow) float rintf(float ); +__declspec(__nothrow) long double rintl(long double ); + + + + + + + +extern __declspec(__nothrow) double exp2(double ); +extern __declspec(__nothrow) float exp2f(float ); +__declspec(__nothrow) long double exp2l(long double ); +extern __declspec(__nothrow) double fdim(double , double ); +extern __declspec(__nothrow) float fdimf(float , float ); +__declspec(__nothrow) long double fdiml(long double , long double ); +# 803 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" +extern __declspec(__nothrow) double fma(double , double , double ); +extern __declspec(__nothrow) float fmaf(float , float , float ); + +static __inline __declspec(__nothrow) long double fmal(long double __x, long double __y, long double __z) { return (long double)fma((double)__x, (double)__y, (double)__z); } + + +extern __declspec(__nothrow) __attribute__((const)) double fmax(double , double ); +extern __declspec(__nothrow) __attribute__((const)) float fmaxf(float , float ); +__declspec(__nothrow) long double fmaxl(long double , long double ); +extern __declspec(__nothrow) __attribute__((const)) double fmin(double , double ); +extern __declspec(__nothrow) __attribute__((const)) float fminf(float , float ); +__declspec(__nothrow) long double fminl(long double , long double ); +extern __declspec(__nothrow) double log2(double ); +extern __declspec(__nothrow) float log2f(float ); +__declspec(__nothrow) long double log2l(long double ); +extern __declspec(__nothrow) long lrint(double ); +extern __declspec(__nothrow) long lrintf(float ); + +static __inline __declspec(__nothrow) long lrintl(long double __x) { return lrint((double)__x); } + + +extern __declspec(__nothrow) long long llrint(double ); +extern __declspec(__nothrow) long long llrintf(float ); + +static __inline __declspec(__nothrow) long long llrintl(long double __x) { return llrint((double)__x); } + + +extern __declspec(__nothrow) long lround(double ); +extern __declspec(__nothrow) long lroundf(float ); + +static __inline __declspec(__nothrow) long lroundl(long double __x) { return lround((double)__x); } + + +extern __declspec(__nothrow) long long llround(double ); +extern __declspec(__nothrow) long long llroundf(float ); + +static __inline __declspec(__nothrow) long long llroundl(long double __x) { return llround((double)__x); } + + +extern __declspec(__nothrow) __attribute__((const)) double nan(const char * ); +extern __declspec(__nothrow) __attribute__((const)) float nanf(const char * ); + +static __inline __declspec(__nothrow) __attribute__((const)) long double nanl(const char *__t) { return (long double)nan(__t); } +# 856 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" +extern __declspec(__nothrow) __attribute__((const)) double nearbyint(double ); +extern __declspec(__nothrow) __attribute__((const)) float nearbyintf(float ); +__declspec(__nothrow) long double nearbyintl(long double ); +extern double remquo(double , double , int * ); +extern float remquof(float , float , int * ); + +static __inline long double remquol(long double __x, long double __y, int *__q) { return (long double)remquo((double)__x, (double)__y, __q); } + + +extern __declspec(__nothrow) __attribute__((const)) double round(double ); +extern __declspec(__nothrow) __attribute__((const)) float roundf(float ); +__declspec(__nothrow) long double roundl(long double ); +extern __declspec(__nothrow) double tgamma(double ); +extern __declspec(__nothrow) float tgammaf(float ); +__declspec(__nothrow) long double tgammal(long double ); +extern __declspec(__nothrow) __attribute__((const)) double trunc(double ); +extern __declspec(__nothrow) __attribute__((const)) float truncf(float ); +__declspec(__nothrow) long double truncl(long double ); + + + + + + +# 896 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + +# 1087 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + + + +# 1317 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + +# 19 "..\\..\\src\\common\\tau_common.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 75 "..\\..\\src\\common\\tau_common.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef uint32_t status_t; + + +typedef void (*fcb_type)(void *data); + +typedef void (*uart_trans_cb)(status_t status, void *user_data); + +typedef void (*flash_trans_cb)(status_t status, void *user_data); +# 16 "..\\..\\src\\sdk\\include\\hal_system.h" +# 1 "..\\..\\src\\sdk\\include\\hal_gpio.h" + + + + + + + + + + + + + + + +# 1 "..\\..\\src\\common\\tau_device_datatype.h" + + + + + + + + + + + + + + + + + + +# 20 "..\\..\\src\\common\\tau_device_datatype.h" +# 21 "..\\..\\src\\common\\tau_device_datatype.h" + + + + + + + + + + + + + + + +enum _status_groups +{ + STATUS_GROUP_GENERIC = 0, + STATUS_GROUP_I2C = 1, + STATUS_GROUP_UART = 2, + STATUS_GROUP_SPI = 3, + STATUS_GROUP_TIMER = 4, +}; + + +enum _generic_status +{ + STATUS_SUCCESS = ((((STATUS_GROUP_GENERIC)*100) + (0))), + STATUS_FAIL = ((((STATUS_GROUP_GENERIC)*100) + (1))), + STATUS_READ_ONLY = ((((STATUS_GROUP_GENERIC)*100) + (2))), + STATUS_OUT_OF_RANGE = ((((STATUS_GROUP_GENERIC)*100) + (3))), + STATUS_INVALID_ARGUMENT = ((((STATUS_GROUP_GENERIC)*100) + (4))), + STATUS_TIME_OUT = ((((STATUS_GROUP_GENERIC)*100) + (5))), + STATUS_NO_TRANSFER_IN_PROGRESS = ((((STATUS_GROUP_GENERIC)*100) + (6))), +}; + + + + + +typedef enum +{ + STATUS_UART_TX_BUSY = ((((STATUS_GROUP_UART)*100) + (0))), + STATUS_UART_RX_BUSY = ((((STATUS_GROUP_UART)*100) + (1))), + STATUS_UART_TX_IDLE = ((((STATUS_GROUP_UART)*100) + (2))), + STATUS_UART_RX_IDLE = ((((STATUS_GROUP_UART)*100) + (3))), + STATUS_UART_TX_ERR = ((((STATUS_GROUP_UART)*100) + (7))), + STATUS_UART_RX_ERR = ((((STATUS_GROUP_UART)*100) + (9))), + STATUS_UART_RX_RING_BUFF_OVERRUN = ((((STATUS_GROUP_UART)*100) + (8))), + STATUS_UART_NOISE_ERR = ((((STATUS_GROUP_UART)*100) + (10))), + STATUS_UART_FRAMING_ERR = ((((STATUS_GROUP_UART)*100) + (11))), + STATUS_UART_PARITY_ERR = ((((STATUS_GROUP_UART)*100) + (12))), + STATUS_UART_BAUDRATE_NOT_SPT = ((((STATUS_GROUP_UART)*100) + (13))), +} uart_status_e; + + + + +typedef enum +{ + STATUS_TIMER_IDLE = ((((STATUS_GROUP_TIMER)*100) + (0))), + STATUS_TIMER_RUNNING = ((((STATUS_GROUP_TIMER)*100) + (1))), + STATUS_TIMER_TIMEOUT = ((((STATUS_GROUP_TIMER)*100) + (2))), +} timer_status_e; + + + + +typedef enum +{ + DETECT_HIGH_LVL = 0, + DETECT_LOW_LVL, + DETECT_RISING_EDGE, + DETECT_FALLING_EDGE, + DETECT_DOUBLE_EDGE +} sys_cfg_trigger_e; + + + + +typedef enum +{ + TIMER_NUM0 = 0, + TIMER_NUM1, + TIMER_NUM2, + TIMER_NUM3, + TIMER_NUM_MAX +} timer_num_e; + + + + +typedef enum +{ + GPIO_INT_EXTI_INT0 = 0, + GPIO_INT_EXTI_INT1, + GPIO_INT_EXTI_INT2, + GPIO_INT_EXTI_INT3, + GPIO_INT_EXTI_INT4, + GPIO_INT_EXTI_INT5, + GPIO_INT_EXTI_INT6, + GPIO_INT_EXTI_INT7, + GPIO_INT_MAX +} gpio_int_e; + + +typedef enum _pwm_int_type +{ + PWM_INT_HIGH_OVERFLOW = 0, + PWM_INT_LOW_OVERFLOW, + PWM_INT_TOTAL_OVERFLOW, + PWM_INT_HIGH_DONE, + PWM_INT_LOW_DONE, + PWM_INT_TOTAL_DONE, + PWM_INT_MAX +} pwm_int_type_e; + + + + +typedef enum +{ + I2C_SELECT_0 = 0, + I2C_SELECT_1, +} i2c_select_e; + + + + + +typedef enum _i2c_rate +{ + I2C_RATE_STANDARD = 1, + I2C_RATE_FAST, + I2C_RATE_HIGH, +} i2c_rate_e; + + + + + +typedef enum +{ + I2C_INDEX_0, + I2C_INDEX_1, + I2C_INDEX_2, + I2C_INDEX_MAX +} i2c_index_e; + + + + + +typedef enum +{ + AHB_DMA_CH0, + AHB_DMA_CH1, + AHB_DMA_CH2, + AHB_DMA_CH3, + AHB_DMA_CH4, + AHB_DMA_CH5, + AHB_DMA_CH6, + AHB_DMA_CH7, + AHB_DMA_CH_NUM +} dma_channel_type_e; + + + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} function_state_e; + + + + +typedef enum +{ + CRC_REV_NO_TRANSPOSE = 0, + CRC_REV_ONLY_BITS_TRANSPOSE, + CRC_REV_BOTH_TRANSPOSE, + CRC_REV_ONLY_BYTES_TRANSPOSE, +} crc_reversal_type_e; + + + + +typedef enum +{ + CRC_FXOR_DISABLE = 0, + CRC_FXOR_ENABLE, +} crc_fxor_function_e; + + + + +typedef enum +{ + CRC_16_BIT_PROTOCOL = 0, + CRC_32_BIT_PROTOCOL, +} crc_protocol_type_e; + + + + + + + +# 17 "..\\..\\src\\sdk\\include\\hal_gpio.h" +# 18 "..\\..\\src\\sdk\\include\\hal_gpio.h" + + + + + + + +typedef enum +{ + + IO_PAD_GPIO0 = 0, + IO_PAD_GPIO1, + IO_PAD_GPIO2, + IO_PAD_GPIO3, + IO_PAD_GPIO4, + IO_PAD_GPIO5, + IO_PAD_GPIO6, + IO_PAD_GPIO7, + IO_PAD_GPIO8, + IO_PAD_GPIO9, + IO_PAD_GPIO10, + IO_PAD_GPIO11, + IO_PAD_GPIO12, + IO_PAD_GPIO13, + IO_PAD_GPIO14, + IO_PAD_GPIO15, + IO_PAD_GPIO16, + IO_PAD_GPIO17, + IO_PAD_GPIO18, + IO_PAD_GPIO19, + IO_PAD_GPIO20, + IO_PAD_GPIO21, + IO_PAD_GPIO22, + IO_PAD_GPIO23, + IO_PAD_GPIO24, + IO_PAD_GPIO25, + + + IO_PAD_AP_SPIS_MISO = IO_PAD_GPIO0, + IO_PAD_AP_SPIS_MOSI = IO_PAD_GPIO1, + IO_PAD_AP_INT = IO_PAD_GPIO2, + IO_PAD_AP_TE = IO_PAD_GPIO3, + IO_PAD_AP_SWIRE = IO_PAD_GPIO4, + IO_PAD_TD_SPIM_MISO = IO_PAD_GPIO5, + IO_PAD_TD_SPIM_MOSI = IO_PAD_GPIO6, + IO_PAD_TD_RSTN = IO_PAD_GPIO7, + IO_PAD_AP_PWMEN = IO_PAD_GPIO8, + IO_PAD_AP_SPIS_CLK = IO_PAD_GPIO9, + IO_PAD_AP_SPIS_CSN = IO_PAD_GPIO10, + IO_PAD_TD_FC_CLK = IO_PAD_GPIO11, + IO_PAD_TD_FC_CSN = IO_PAD_GPIO12, + IO_PAD_TD_FC_IO0 = IO_PAD_GPIO13, + IO_PAD_TD_FC_IO1 = IO_PAD_GPIO14, + IO_PAD_SWD_CLK = IO_PAD_GPIO15, + IO_PAD_SWD_DIO = IO_PAD_GPIO16, + IO_PAD_AP_RSTN = IO_PAD_GPIO17, + IO_PAD_UART0_TX = IO_PAD_GPIO18, + IO_PAD_TD_SPIM_CLK = IO_PAD_GPIO19, + IO_PAD_TD_SPIM_CSN = IO_PAD_GPIO20, + IO_PAD_AP_TPRSTN = IO_PAD_GPIO21, + IO_PAD_TD_INT = IO_PAD_GPIO22, + IO_PAD_TD_TP_RESX = IO_PAD_GPIO23, + IO_PAD_UART1_TX = IO_PAD_GPIO24, + IO_PAD_UART0_RX = IO_PAD_GPIO25, + + IO_PAD_MAX, + + + + IO_PIN_1 = IO_PAD_SWD_CLK, + IO_PIN_2 = IO_PAD_UART0_TX, + IO_PIN_3 = IO_PAD_SWD_DIO, + IO_PIN_4 = IO_PAD_TD_SPIM_MOSI, + IO_PIN_5 = IO_PAD_TD_SPIM_CLK, + IO_PIN_6 = IO_PAD_TD_SPIM_CSN, + IO_PIN_7 = IO_PAD_TD_SPIM_MISO, + IO_PIN_8 = IO_PAD_TD_RSTN, + IO_PIN_9 = IO_PAD_TD_FC_CSN, + IO_PIN_10 = IO_PAD_TD_FC_CLK, + IO_PIN_11 = IO_PAD_TD_FC_IO0, + IO_PIN_12 = IO_PAD_TD_FC_IO1, + IO_PIN_13 = IO_PAD_TD_TP_RESX, + IO_PIN_14 = IO_PAD_UART1_TX, + IO_PIN_15 = IO_PAD_AP_SWIRE, + IO_PIN_16 = IO_PAD_AP_INT, + IO_PIN_17 = IO_PAD_AP_PWMEN, + IO_PIN_18 = IO_PAD_AP_TPRSTN, + + IO_PIN_29 = IO_PAD_AP_TE, + IO_PIN_30 = IO_PAD_AP_SPIS_MISO, + IO_PIN_31 = IO_PAD_AP_SPIS_CSN, + IO_PIN_32 = IO_PAD_AP_SPIS_CLK, + IO_PIN_33 = IO_PAD_AP_SPIS_MOSI, + IO_PIN_34 = IO_PAD_AP_RSTN, + IO_PIN_35 = IO_PAD_TD_INT, + IO_PIN_36 = IO_PAD_UART0_RX, + +} io_pad_e; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef enum +{ + PIN1_MODE_SWDCLK = 0, + PIN1_MODE_GPIO15 = 2, +} pin1_mode_e; + + + + + +typedef enum +{ + PIN2_MODE_UART0_TX = 0, + PIN2_MODE_PWMO = 1, + PIN2_MODE_GPIO18 = 2, + PIN2_MODE_PWMI = 3, + PIN2_MODE_TEAR1 = 4, +} pin2_mode_e; + + + + +typedef enum +{ + PIN3_MODE_SWDIO = 0, + PIN3_MODE_GPIO16 = 2, +} pin3_mode_e; + + + + + +typedef enum +{ + PIN4_MODE_SPIM_MOSI = 0, + PIN4_MODE_I2C02_SDA = 1, + PIN4_MODE_GPIO6 = 2, + PIN4_MODE_UART0_TX = 3, +} pin4_mode_e; + + + + +typedef enum +{ + PIN5_MODE_SPIM_SCLK = 0, + PIN5_MODE_I2C1_SCL = 1, + PIN5_MODE_GPIO19 = 2, +} pin5_mode_e; + + + + +typedef enum +{ + PIN6_MODE_SPIM_CSN = 0, + PIN6_MODE_I2C1_SDA = 1, + PIN6_MODE_GPIO20 = 2, +} pin6_mode_e; + + + + +typedef enum +{ + PIN7_MODE_SPIM_MISO = 0, + PIN7_MODE_I2C02_SCL = 1, + PIN7_MODE_GPIO5 = 2, +} pin7_mode_e; + + + + +typedef enum +{ + PIN8_MODE_GPIO7 = 2, + PIN8_MODE_I2C02_SDA = 3, +} pin8_mode_e; + + + + +typedef enum +{ + PIN9_MODE_TSPIS_CSN = 0, + PIN9_MODE_GPIO12 = 2, +} pin9_mode_e; + + + + +typedef enum +{ + PIN10_MODE_TSPIS_CLK = 0, + PIN10_MODE_GPIO11 = 2, +} pin10_mode_e; + + + + + +typedef enum +{ + PIN11_MODE_TSPIS_IO0 = 0, + PIN11_MODE_GPIO13 = 2, + PIN11_MODE_I2C02_SDA = 3, +} pin11_mode_e; + + + + +typedef enum +{ + PIN12_MODE_TSPIS_IO1 = 0, + PIN12_MODE_GPIO14 = 2, + PIN12_MODE_I2C02_SCL = 3, +} pin12_mode_e; + + + + +typedef enum +{ + PIN13_MODE_GPIO23 = 2, + PIN13_MODE_PWMO = 3, + PIN13_MODE_UART1_RX = 4, +} pin13_mode_e; + + + + +typedef enum +{ + PIN14_MODE_GPIO24 = 2, + PIN14_MODE_UART0_RX = 3, + PIN14_MODE_UART1_TX = 4, +} pin14_mode_e; + + + + + + +typedef enum +{ + PIN15_MODE_SWIRE = 0, + PIN15_MODE_PWMO = 1, + PIN15_MODE_GPIO4 = 2, +} pin15_mode_e; + + + + +typedef enum +{ + PIN16_MODE_GPIO2 = 2, +} pin16_mode_e; + + + + +typedef enum +{ + PIN17_MODE_UART0_RX = 1, + PIN17_MODE_GPIO8 = 2, + PIN17_MODE_PWMO = 3, +} pin17_mode_e; + + + + +typedef enum +{ + PIN18_MODE_UART0_RX = 0, + PIN18_MODE_GPIO21 = 2, + PIN18_MODE_I2C02_SCL = 3, +} pin18_mode_e; + + + + + + + +typedef enum +{ + PIN29_MODE_JTAG_TRSTN = 0, + PIN29_MODE_TEAR = 1, + PIN29_MODE_GPIO3 = 2, +} pin29_mode_e; + + + + + +typedef enum +{ + PIN30_MODE_JTAG_TDO = 0, + PIN30_MODE_SPIS_MISO = 1, + PIN30_MODE_GPIO0 = 2, + PIN30_MODE_UART0_RX = 3, + PIN30_MODE_I2C1_SCL = 6, +} pin30_mode_e; + + + + +typedef enum +{ + PIN31_MODE_JTAG_TMS = 0, + PIN31_MODE_SPIS_CSN = 1, + PIN31_MODE_GPIO10 = 2, + PIN31_MODE_I2C02_SDA = 3, +} pin31_mode_e; + + + + +typedef enum +{ + PIN32_MODE_JTAG_TCK = 0, + PIN32_MODE_SPIS_SCLK = 1, + PIN32_MODE_GPIO9 = 2, + PIN32_MODE_I2C02_SCL = 3, +} pin32_mode_e; + + + + +typedef enum +{ + PIN33_MODE_JTAG_TDI = 0, + PIN33_MODE_SPIS_MOSI = 1, + PIN33_MODE_GPIO1 = 2, + PIN33_MODE_UART0_TX = 3, + PIN33_MODE_I2C1_SDA_0 = 6, +} pin33_mode_e; + + + + +typedef enum +{ + PIN34_MODE_GPIO17 = 2, +} pin34_mode_e; + + + + + +typedef enum +{ + PIN35_MODE_GPIO22 = 2, +} pin35_mode_e; + + + + + +typedef enum +{ + PIN36_MODE_UART0_RX = 0, + PIN36_MODE_PWMO = 1, + PIN36_MODE_GPIO25 = 2, +} pin36_mode_e; + + + + + + + +typedef enum +{ + IO_MODE_INTER_FC_CLK = 0, + IO_MODE_TSPIS_CLK_EN = 2, +} pad_sfc_clk_mode_e; + + + + +typedef enum +{ + IO_MODE_INTER_FC_CSN = 0, + IO_MODE_TSPIS_CSN_EN = 2, +} pad_sfc_csn_mode_e; + + + + +typedef enum +{ + IO_MODE_INTER_FC_IO0 = 0, + IO_MODE_TSPIS_IO0_EN = 2, +} pad_sfc_io0_mode_e; + + + + +typedef enum +{ + IO_MODE_INTER_FC_IO1 = 0, + IO_MODE_TSPIS_IO1_EN = 2, +} pad_sfc_io1_mode_e; + + + + +typedef enum +{ + IO_SLEW_RATE_SLOW = 0, + IO_SLEW_RATE_FAST = 1, +} pad_slew_rate_e; + + + + + + + +typedef enum +{ + IO_IOE_INPUT = 0, + IO_IOE_OUTPUT, + IO_IOE_NONE +} gpio_ioe_e; + + + + +typedef enum +{ + IO_LVL_LOW = 0, + IO_LVL_HIGH, + IO_LVL_NONE +} gpio_level_e; + + + + + + + +typedef struct +{ + io_pad_e pad; + uint8_t mode; + gpio_ioe_e ioe; + gpio_level_e lvl; +} io_pad_attr_t; + + + + + + + + + + + + + + +void hal_gpio_init_eint(io_pad_e pad, sys_cfg_trigger_e trig); + + + + + + + + +void hal_gpio_reg_eint_cb(io_pad_e pad, fcb_type cb_func); + + + + + + + +void hal_gpio_ctrl_eint(io_pad_e pad, _Bool state); + + + + + + +gpio_int_e hal_gpio_get_int_type(io_pad_e pad); + + + + + + + +void hal_gpio_init_output(io_pad_e pad, gpio_level_e lvl); + + + + + + + +void hal_gpio_set_output_data(io_pad_e pad, gpio_level_e lvl); + + + + + + +void hal_gpio_init_input(io_pad_e pad); + + + + + + +gpio_level_e hal_gpio_get_input_data(io_pad_e pad); + + + + + + + +void hal_gpio_set_mode(io_pad_e pad, uint8_t mode); + + + + + + +void hal_gpio_set_high_impedance(io_pad_e pad); + + + + + + + + +void hal_gpio_get_pull_state(io_pad_e pad, _Bool *up_enable, _Bool *down_enable); + + + + + + + + +void hal_gpio_set_pull_state(io_pad_e pad, _Bool up_enable, _Bool down_enable); + + + + + + + +void hal_gpio_set_schmitt_trigger(io_pad_e pad, _Bool st_enable); + + + + + + + +void hal_gpio_set_driving_strength(io_pad_e pad, uint8_t strength); + + + + + + + +void hal_gpio_set_slew_rate(io_pad_e pad, pad_slew_rate_e rate); + + + + + + + + +void hal_gpio_set_ap_reset_int(_Bool enable, fcb_type cb_func, sys_cfg_trigger_e trig); + + + + + + + +void hal_gpio_config_pad(io_pad_attr_t *attrs, uint8_t size); + +# 17 "..\\..\\src\\sdk\\include\\hal_system.h" +# 1 "..\\..\\src\\common\\tau_log.h" + + + + + + + + + + + + + + + + +# 18 "..\\..\\src\\common\\tau_log.h" +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 38 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" + + + + + + + typedef unsigned int size_t; +# 54 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" + + + + +extern __declspec(__nothrow) void *memcpy(void * __restrict , + const void * __restrict , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + +extern __declspec(__nothrow) void *memmove(void * , + const void * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + +extern __declspec(__nothrow) char *strcpy(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); + + + + + + +extern __declspec(__nothrow) char *strncpy(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + +extern __declspec(__nothrow) char *strcat(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); + + + + + + +extern __declspec(__nothrow) char *strncat(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) int memcmp(const void * , const void * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + +extern __declspec(__nothrow) int strcmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + +extern __declspec(__nothrow) int strncmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + +extern __declspec(__nothrow) int strcasecmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + +extern __declspec(__nothrow) int strncasecmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + +extern __declspec(__nothrow) int strcoll(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + +extern __declspec(__nothrow) size_t strxfrm(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(2))); + + + + + + + + + + + + + + + + + +# 193 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) void *memchr(const void * , int , size_t ) __attribute__((__nonnull__(1))); + + + + + + + + + +# 209 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) char *strchr(const char * , int ) __attribute__((__nonnull__(1))); + + + + + + + + +extern __declspec(__nothrow) size_t strcspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + +# 232 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) char *strpbrk(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + + +# 247 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) char *strrchr(const char * , int ) __attribute__((__nonnull__(1))); + + + + + + + + + +extern __declspec(__nothrow) size_t strspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + +# 270 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) char *strstr(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + + + +extern __declspec(__nothrow) char *strtok(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(2))); +extern __declspec(__nothrow) char *_strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); + +extern __declspec(__nothrow) char *strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) void *memset(void * , int , size_t ) __attribute__((__nonnull__(1))); + + + + + +extern __declspec(__nothrow) char *strerror(int ); + + + + + + + +extern __declspec(__nothrow) size_t strlen(const char * ) __attribute__((__nonnull__(1))); + + + + + + +extern __declspec(__nothrow) size_t strlcpy(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) size_t strlcat(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) void _membitcpybl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpybb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpyhl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpyhb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpywl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpywb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovebl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovebb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovehl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovehb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovewl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovewb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 502 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" + + + + + +# 19 "..\\..\\src\\common\\tau_log.h" +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdarg.h" + + + + + + + + + + + + + + + + + + + +# 27 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdarg.h" + + + + + + + + + + + + +# 57 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdarg.h" + typedef struct __va_list { void *__ap; } va_list; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + typedef va_list __gnuc_va_list; + + + + + + +# 147 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdarg.h" + + + +# 20 "..\\..\\src\\common\\tau_log.h" +# 1 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef enum IRQn +{ + + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + + VIDC_IRQn = 0, + LCDC_IRQn = 1, + MIPI_RX_IRQn = 2, + MIPI_TX_IRQn = 3, + MEMC_IRQn = 4, + VPRE_IRQn = 5, + FLSCTRL_IRQn = 6, + DMA_IRQn = 7, + TIMER0_IRQn = 8, + TIMER1_IRQn = 9, + TIMER2_IRQn = 10, + TIMER3_IRQn = 11, + WDG_IRQn = 12, + UART_IRQn = 13, + I2C0_IRQn = 14, + I2C1_IRQn = 15, + SPIS_IRQn = 16, + SPIM_IRQn = 17, + VPRE1_IRQn = 18, + I2C2_IRQn = 19, + OTP_IRQn = 20, + SWIRE_IRQn = 21, + PVD_IRQn = 22, + AP_NRESET_IRQn = 23, + EXTI_INT0_IRQn = 24, + EXTI_INT1_IRQn = 25, + EXTI_INT2_IRQn = 26, + EXTI_INT3_IRQn = 27, + EXTI_INT4_IRQn = 28, + EXTI_INT5_IRQn = 29, + EXTI_INT6_IRQn = 30, + EXTI_INT7_IRQn = 31 + +} IRQn_Type; + + + + + + + + +#pragma push +#pragma anon_unions +# 107 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + + + + + + + + + + + + +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 35 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_version.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 64 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + +# 114 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_compiler.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 29 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_compiler.h" + + + + +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 107 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + +static __inline uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __asm("control"); + return(__regControl); +} + + + + + + + +static __inline void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __asm("control"); + __regControl = control; +} + + + + + + + +static __inline uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __asm("ipsr"); + return(__regIPSR); +} + + + + + + + +static __inline uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __asm("apsr"); + return(__regAPSR); +} + + + + + + + +static __inline uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __asm("xpsr"); + return(__regXPSR); +} + + + + + + + +static __inline uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __asm("psp"); + return(__regProcessStackPointer); +} + + + + + + + +static __inline void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __asm("psp"); + __regProcessStackPointer = topOfProcStack; +} + + + + + + + +static __inline uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __asm("msp"); + return(__regMainStackPointer); +} + + + + + + + +static __inline void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __asm("msp"); + __regMainStackPointer = topOfMainStack; +} + + + + + + + +static __inline uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __asm("primask"); + return(__regPriMask); +} + + + + + + + +static __inline void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __asm("primask"); + __regPriMask = (priMask); +} + + +# 342 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + + + + + +static __inline uint32_t __get_FPSCR(void) +{ + + + + + + return(0U); + +} + + + + + + + +static __inline void __set_FPSCR(uint32_t fpscr) +{ + + + + + + (void)fpscr; + +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +__attribute__((section(".rev16_text"))) static __inline __asm uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + + + + + + + + + +__attribute__((section(".revsh_text"))) static __inline __asm int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +__attribute__((always_inline)) static __inline uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U * 8U) - 1U; + + result = value; + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; + return result; +} + + + + + + + + + + + + +# 732 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + + + + + + +__attribute__((always_inline)) static __inline int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + + + + + + + + +__attribute__((always_inline)) static __inline uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + + + + + + + + + + + + + +# 866 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + +# 35 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_compiler.h" + + + + + +# 268 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_compiler.h" + + + + +# 116 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + +# 150 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + +# 166 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef union +{ + struct + { + uint32_t _reserved0:28; + uint32_t V:1; + uint32_t C:1; + uint32_t Z:1; + uint32_t N:1; + } b; + uint32_t w; +} APSR_Type; + + + + + + + + + + + + + + + + + + +typedef union +{ + struct + { + uint32_t ISR:9; + uint32_t _reserved0:23; + } b; + uint32_t w; +} IPSR_Type; + + + + + + + + + +typedef union +{ + struct + { + uint32_t ISR:9; + uint32_t _reserved0:15; + uint32_t T:1; + uint32_t _reserved1:3; + uint32_t V:1; + uint32_t C:1; + uint32_t Z:1; + uint32_t N:1; + } b; + uint32_t w; +} xPSR_Type; + + + + + + + + + + + + + + + + + + + + + + + + +typedef union +{ + struct + { + uint32_t _reserved0:1; + uint32_t SPSEL:1; + uint32_t _reserved1:30; + } b; + uint32_t w; +} CONTROL_Type; + + + + + + + + + + + + + + + + + + +typedef struct +{ + volatile uint32_t ISER[1U]; + uint32_t RESERVED0[31U]; + volatile uint32_t ICER[1U]; + uint32_t RESERVED1[31U]; + volatile uint32_t ISPR[1U]; + uint32_t RESERVED2[31U]; + volatile uint32_t ICPR[1U]; + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + volatile uint32_t IP[8U]; +} NVIC_Type; + + + + + + + + + + + + + + +typedef struct +{ + volatile const uint32_t CPUID; + volatile uint32_t ICSR; + uint32_t RESERVED0; + volatile uint32_t AIRCR; + volatile uint32_t SCR; + volatile uint32_t CCR; + uint32_t RESERVED1; + volatile uint32_t SHP[2U]; + volatile uint32_t SHCSR; +} SCB_Type; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef struct +{ + volatile uint32_t CTRL; + volatile uint32_t LOAD; + volatile uint32_t VAL; + volatile const uint32_t CALIB; +} SysTick_Type; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 583 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + +# 598 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + + + + + + + +static __inline void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + + + + + + + + + +static __inline uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + + + + + + + +static __inline void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); + do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U); + } +} + + + + + + + + + + +static __inline uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + + + + + + + +static __inline void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + + + + + + + +static __inline void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + + + + + + + + + + +static __inline void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] = ((uint32_t)(((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | + (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); + } + else + { + ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] = ((uint32_t)(((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | + (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); + } +} + + + + + + + + + + + +static __inline uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[ ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); + } + else + { + return((uint32_t)(((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); + } +} + + + + + + + + + + + + + +static __inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + + + + + + + + + + + + +static __inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + + + + + + + + + + +static __inline void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + 16) * 4)) = vector; +} + + + + + + + + + + +static __inline uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + 16) * 4)); +} + + + + + + +__declspec(noreturn) static __inline void __NVIC_SystemReset(void) +{ + do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); + + ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR = ((0x5FAUL << 16U) | + (1UL << 2U)); + do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); + + for(;;) + { + __nop(); + } +} + + + + + + + + + + + + + + + + + + + + +static __inline uint32_t SCB_GetFPUType(void) +{ + return 0U; +} + + + + + + + + + + + + + + + + + + + + + + + + + + + +static __inline uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > (0xFFFFFFUL )) + { + return (1UL); + } + + ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->LOAD = (uint32_t)(ticks - 1UL); + __NVIC_SetPriority (SysTick_IRQn, (1UL << 2U) - 1UL); + ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->VAL = 0UL; + ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL = (1UL << 2U) | + (1UL << 1U) | + (1UL ); + return (0UL); +} + + + + + + + + + + + + + + +# 122 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\Device\\ARM\\ARMCM0\\Include\\system_ARMCM0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern uint32_t SystemCoreClock; + + + + + + + +extern void SystemInit (void); + + + + + + + +extern void SystemCoreClockUpdate (void); + + + + + +# 123 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + +#pragma pop +# 142 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + +# 167 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + +# 179 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + + + +# 21 "..\\..\\src\\common\\tau_log.h" + + + + +# 31 "..\\..\\src\\common\\tau_log.h" + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef enum +{ + kLOG_LEVEL_DBG = 0, + kLOG_LEVEL_INF, + kLOG_LEVEL_ERR, + kLOG_LEVEL_NONE +} log_level_e; + + + + + +typedef enum +{ + LOG_PORT_UART0, + LOG_PORT_UART1, + LOG_PORT_SWD, + LOG_PORT_UNKNOWN +} log_port_e; + + + + + + + + + + + + + + +void tau_log_init(uint32_t baud_rate, log_port_e log_port); + + + + + + + +void tau_log_printf(log_level_e log_lv, const char *fmt, ...); + +# 18 "..\\..\\src\\sdk\\include\\hal_system.h" + + + + + + + + + + + +typedef enum +{ + HAL_SYSCLK_80M = 80000000, + HAL_SYSCLK_100M = 100000000, + HAL_SYSCLK_150M = 150000000 +} hal_system_clk_e; + + + + + + + + + + + + + + +void hal_system_init(hal_system_clk_e sysclk); + + + + + + +void hal_system_idle_mode(_Bool disable_systick); + + + + + + +void hal_system_register_systick_cb(fcb_type cb_func); + + + + + + +_Bool hal_system_enable_systick(uint8_t ms); + + + + + + +_Bool hal_system_disable_systick(void); + + + + + + +uint32_t hal_system_get_tick(void); + + + + + + +void hal_system_reset_chip(void); + + + + + + +uint32_t hal_system_get_debug_state(void); + + + + + + +void hal_system_clear_debug_state(void); + + + + + + +_Bool hal_system_updata_sysclk(hal_system_clk_e sysclk); + +# 12 "..\\..\\src\\board\\board.c" +# 13 "..\\..\\src\\board\\board.c" +# 14 "..\\..\\src\\board\\board.c" +# 15 "..\\..\\src\\board\\board.c" + + + + + + +void board_Init(void) +{ + + hal_system_init(HAL_SYSCLK_80M); + + + tau_log_init(115200, LOG_PORT_UART0); + + + +} diff --git a/project/WL668/Listings/board.lst b/project/WL668/Listings/board.lst new file mode 100644 index 0000000..2645d9f --- /dev/null +++ b/project/WL668/Listings/board.lst @@ -0,0 +1,6596 @@ +L 1 "..\..\src\board\board.c" +N/******************************************************************************* +N* +N* +N* File: board.c +N* Description 板级文件 +N* Version V0.1 +N* Date 2023-07-23 +N* Author lzy +N*******************************************************************************/ +N#include "board.h" +L 1 "..\..\src\board\board.h" 1 +N/******************************************************************************* +N* +N* +N* File: board.h +N* Description: baord 初始化头文件 +N* Version: V0.1 +N* Date: 2020-01-08 +N* Author: lzy +N *******************************************************************************/ +N +N#ifndef __BOARD_H__ +N#define __BOARD_H__ +N +N/** +N* @brief 系统板级初始化,配置系统时钟,调试log输出 +N* @param none +N* @retval none +N*/ +Nvoid board_Init(void); +N +N#endif +L 11 "..\..\src\board\board.c" 2 +N#include "hal_system.h" +L 1 "..\..\src\sdk\include\hal_system.h" 1 +N/******************************************************************************* +N* +N* +N* File: hal_system.h +N* Description hal 通用系统接口头文件 +N* Version V0.1 +N* Date 2021-05-21 +N* Author lzy +N *******************************************************************************/ +N#ifndef __HAL_SYSTEM_H__ +N#define __HAL_SYSTEM_H__ +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_common.h" +L 1 "..\..\src\common\tau_common.h" 1 +N/******************************************************************************* +N* +N* +N* File: tau_common.h +N* Description 通用数据类型相关定义头文件 +N* Version V0.1 +N* Date 2020-09-07 +N* Author lzy +N *******************************************************************************/ +N +N#ifndef __TAU_COMMON_H +N#define __TAU_COMMON_H +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "stdint.h" +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h" 1 +N/* Copyright (C) ARM Ltd., 1999,2014 */ +N/* All rights reserved */ +N +N/* +N * RCS $Revision$ +N * Checkin $Date$ +N * Revising $Author: agrant $ +N */ +N +N#ifndef __stdint_h +N#define __stdint_h +N#define __ARMCLIB_VERSION 5060037 +N +N #ifdef __INT64_TYPE__ +S /* armclang predefines '__INT64_TYPE__' and '__INT64_C_SUFFIX__' */ +S #define __INT64 __INT64_TYPE__ +N #else +N /* armcc has builtin '__int64' which can be used in --strict mode */ +N #define __INT64 __int64 +N #define __INT64_C_SUFFIX__ ll +N #endif +N #define __PASTE2(x, y) x ## y +N #define __PASTE(x, y) __PASTE2(x, y) +N #define __INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__)) +N #define __UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__)) +N #if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__)) +X #if 0L || (1L && !0L) +N /* armclang and non-strict armcc allow 'long long' in system headers */ +N #define __LONGLONG long long +N #else +S /* strict armcc has '__int64' */ +S #define __LONGLONG __int64 +N #endif +N +N #ifndef __STDINT_DECLS +N #define __STDINT_DECLS +N +N #undef __CLIBNS +N +N #ifdef __cplusplus +S namespace std { +S #define __CLIBNS std:: +S extern "C" { +N #else +N #define __CLIBNS +N #endif /* __cplusplus */ +N +N +N/* +N * 'signed' is redundant below, except for 'signed char' and if +N * the typedef is used to declare a bitfield. +N */ +N +N /* 7.18.1.1 */ +N +N /* exact-width signed integer types */ +Ntypedef signed char int8_t; +Ntypedef signed short int int16_t; +Ntypedef signed int int32_t; +Ntypedef signed __INT64 int64_t; +Xtypedef signed __int64 int64_t; +N +N /* exact-width unsigned integer types */ +Ntypedef unsigned char uint8_t; +Ntypedef unsigned short int uint16_t; +Ntypedef unsigned int uint32_t; +Ntypedef unsigned __INT64 uint64_t; +Xtypedef unsigned __int64 uint64_t; +N +N /* 7.18.1.2 */ +N +N /* smallest type of at least n bits */ +N /* minimum-width signed integer types */ +Ntypedef signed char int_least8_t; +Ntypedef signed short int int_least16_t; +Ntypedef signed int int_least32_t; +Ntypedef signed __INT64 int_least64_t; +Xtypedef signed __int64 int_least64_t; +N +N /* minimum-width unsigned integer types */ +Ntypedef unsigned char uint_least8_t; +Ntypedef unsigned short int uint_least16_t; +Ntypedef unsigned int uint_least32_t; +Ntypedef unsigned __INT64 uint_least64_t; +Xtypedef unsigned __int64 uint_least64_t; +N +N /* 7.18.1.3 */ +N +N /* fastest minimum-width signed integer types */ +Ntypedef signed int int_fast8_t; +Ntypedef signed int int_fast16_t; +Ntypedef signed int int_fast32_t; +Ntypedef signed __INT64 int_fast64_t; +Xtypedef signed __int64 int_fast64_t; +N +N /* fastest minimum-width unsigned integer types */ +Ntypedef unsigned int uint_fast8_t; +Ntypedef unsigned int uint_fast16_t; +Ntypedef unsigned int uint_fast32_t; +Ntypedef unsigned __INT64 uint_fast64_t; +Xtypedef unsigned __int64 uint_fast64_t; +N +N /* 7.18.1.4 integer types capable of holding object pointers */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +Stypedef signed __INT64 intptr_t; +Stypedef unsigned __INT64 uintptr_t; +N#else +Ntypedef signed int intptr_t; +Ntypedef unsigned int uintptr_t; +N#endif +N +N /* 7.18.1.5 greatest-width integer types */ +Ntypedef signed __LONGLONG intmax_t; +Xtypedef signed long long intmax_t; +Ntypedef unsigned __LONGLONG uintmax_t; +Xtypedef unsigned long long uintmax_t; +N +N +N#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) +X#if !0L || 0L +N +N /* 7.18.2.1 */ +N +N /* minimum values of exact-width signed integer types */ +N#define INT8_MIN -128 +N#define INT16_MIN -32768 +N#define INT32_MIN (~0x7fffffff) /* -2147483648 is unsigned */ +N#define INT64_MIN __INT64_C(~0x7fffffffffffffff) /* -9223372036854775808 is unsigned */ +N +N /* maximum values of exact-width signed integer types */ +N#define INT8_MAX 127 +N#define INT16_MAX 32767 +N#define INT32_MAX 2147483647 +N#define INT64_MAX __INT64_C(9223372036854775807) +N +N /* maximum values of exact-width unsigned integer types */ +N#define UINT8_MAX 255 +N#define UINT16_MAX 65535 +N#define UINT32_MAX 4294967295u +N#define UINT64_MAX __UINT64_C(18446744073709551615) +N +N /* 7.18.2.2 */ +N +N /* minimum values of minimum-width signed integer types */ +N#define INT_LEAST8_MIN -128 +N#define INT_LEAST16_MIN -32768 +N#define INT_LEAST32_MIN (~0x7fffffff) +N#define INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff) +N +N /* maximum values of minimum-width signed integer types */ +N#define INT_LEAST8_MAX 127 +N#define INT_LEAST16_MAX 32767 +N#define INT_LEAST32_MAX 2147483647 +N#define INT_LEAST64_MAX __INT64_C(9223372036854775807) +N +N /* maximum values of minimum-width unsigned integer types */ +N#define UINT_LEAST8_MAX 255 +N#define UINT_LEAST16_MAX 65535 +N#define UINT_LEAST32_MAX 4294967295u +N#define UINT_LEAST64_MAX __UINT64_C(18446744073709551615) +N +N /* 7.18.2.3 */ +N +N /* minimum values of fastest minimum-width signed integer types */ +N#define INT_FAST8_MIN (~0x7fffffff) +N#define INT_FAST16_MIN (~0x7fffffff) +N#define INT_FAST32_MIN (~0x7fffffff) +N#define INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff) +N +N /* maximum values of fastest minimum-width signed integer types */ +N#define INT_FAST8_MAX 2147483647 +N#define INT_FAST16_MAX 2147483647 +N#define INT_FAST32_MAX 2147483647 +N#define INT_FAST64_MAX __INT64_C(9223372036854775807) +N +N /* maximum values of fastest minimum-width unsigned integer types */ +N#define UINT_FAST8_MAX 4294967295u +N#define UINT_FAST16_MAX 4294967295u +N#define UINT_FAST32_MAX 4294967295u +N#define UINT_FAST64_MAX __UINT64_C(18446744073709551615) +N +N /* 7.18.2.4 */ +N +N /* minimum value of pointer-holding signed integer type */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define INTPTR_MIN INT64_MIN +N#else +N#define INTPTR_MIN INT32_MIN +N#endif +N +N /* maximum value of pointer-holding signed integer type */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define INTPTR_MAX INT64_MAX +N#else +N#define INTPTR_MAX INT32_MAX +N#endif +N +N /* maximum value of pointer-holding unsigned integer type */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define UINTPTR_MAX UINT64_MAX +N#else +N#define UINTPTR_MAX UINT32_MAX +N#endif +N +N /* 7.18.2.5 */ +N +N /* minimum value of greatest-width signed integer type */ +N#define INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) +N +N /* maximum value of greatest-width signed integer type */ +N#define INTMAX_MAX __ESCAPE__(9223372036854775807ll) +N +N /* maximum value of greatest-width unsigned integer type */ +N#define UINTMAX_MAX __ESCAPE__(18446744073709551615ull) +N +N /* 7.18.3 */ +N +N /* limits of ptrdiff_t */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define PTRDIFF_MIN INT64_MIN +S#define PTRDIFF_MAX INT64_MAX +N#else +N#define PTRDIFF_MIN INT32_MIN +N#define PTRDIFF_MAX INT32_MAX +N#endif +N +N /* limits of sig_atomic_t */ +N#define SIG_ATOMIC_MIN (~0x7fffffff) +N#define SIG_ATOMIC_MAX 2147483647 +N +N /* limit of size_t */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define SIZE_MAX UINT64_MAX +N#else +N#define SIZE_MAX UINT32_MAX +N#endif +N +N /* limits of wchar_t */ +N /* NB we have to undef and redef because they're defined in both +N * stdint.h and wchar.h */ +N#undef WCHAR_MIN +N#undef WCHAR_MAX +N +N#if defined(__WCHAR32) || (defined(__ARM_SIZEOF_WCHAR_T) && __ARM_SIZEOF_WCHAR_T == 4) +X#if 0L || (0L && __ARM_SIZEOF_WCHAR_T == 4) +S #define WCHAR_MIN 0 +S #define WCHAR_MAX 0xffffffffU +N#else +N #define WCHAR_MIN 0 +N #define WCHAR_MAX 65535 +N#endif +N +N /* limits of wint_t */ +N#define WINT_MIN (~0x7fffffff) +N#define WINT_MAX 2147483647 +N +N#endif /* __STDC_LIMIT_MACROS */ +N +N#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) +X#if !0L || 0L +N +N /* 7.18.4.1 macros for minimum-width integer constants */ +N#define INT8_C(x) (x) +N#define INT16_C(x) (x) +N#define INT32_C(x) (x) +N#define INT64_C(x) __INT64_C(x) +N +N#define UINT8_C(x) (x ## u) +N#define UINT16_C(x) (x ## u) +N#define UINT32_C(x) (x ## u) +N#define UINT64_C(x) __UINT64_C(x) +N +N /* 7.18.4.2 macros for greatest-width integer constants */ +N#define INTMAX_C(x) __ESCAPE__(x ## ll) +N#define UINTMAX_C(x) __ESCAPE__(x ## ull) +N +N#endif /* __STDC_CONSTANT_MACROS */ +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif /* __cplusplus */ +N #endif /* __STDINT_DECLS */ +N +N #ifdef __cplusplus +S #ifndef __STDINT_NO_EXPORTS +S using ::std::int8_t; +S using ::std::int16_t; +S using ::std::int32_t; +S using ::std::int64_t; +S using ::std::uint8_t; +S using ::std::uint16_t; +S using ::std::uint32_t; +S using ::std::uint64_t; +S using ::std::int_least8_t; +S using ::std::int_least16_t; +S using ::std::int_least32_t; +S using ::std::int_least64_t; +S using ::std::uint_least8_t; +S using ::std::uint_least16_t; +S using ::std::uint_least32_t; +S using ::std::uint_least64_t; +S using ::std::int_fast8_t; +S using ::std::int_fast16_t; +S using ::std::int_fast32_t; +S using ::std::int_fast64_t; +S using ::std::uint_fast8_t; +S using ::std::uint_fast16_t; +S using ::std::uint_fast32_t; +S using ::std::uint_fast64_t; +S using ::std::intptr_t; +S using ::std::uintptr_t; +S using ::std::intmax_t; +S using ::std::uintmax_t; +S #endif +N #endif /* __cplusplus */ +N +N#undef __INT64 +N#undef __LONGLONG +N +N#endif /* __stdint_h */ +N +N/* end of stdint.h */ +L 18 "..\..\src\common\tau_common.h" 2 +N#include "math.h" +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h" 1 +N/* +N * math.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.5 +N * Copyright (C) Codemist Ltd., 1988 +N * Copyright 1991-1998,2004-2006,2014 ARM Limited. All rights reserved +N */ +N +N/* +N * RCS $Revision$ Codemist 0.03 +N * Checkin $Date$ +N * Revising $Author: statham $ +N */ +N +N/* +N * Parts of this file are based upon fdlibm: +N * +N * ==================================================== +N * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. +N * +N * Developed at SunSoft, a Sun Microsystems, Inc. business. +N * Permission to use, copy, modify, and distribute this +N * software is freely granted, provided that this notice +N * is preserved. +N * ==================================================== +N */ +N +N#ifndef __math_h +N#define __math_h +N#define __ARMCLIB_VERSION 5060037 +N +N#if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__)) +X#if 0L || (1L && !0L) +N /* armclang and non-strict armcc allow 'long long' in system headers */ +N #define __LONGLONG long long +N#else +S /* strict armcc has '__int64' */ +S #define __LONGLONG __int64 +N#endif +N +N/* +N * Some of these declarations are new in C99. To access them in C++ +N * you can use -D__USE_C99_MATH (or -D__USE_C99_ALL). +N */ +N#ifndef __USE_C99_MATH +N #if defined(__USE_C99_ALL) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) +X #if 0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus) +N #define __USE_C99_MATH 1 +N #endif +N#endif +N +N#define _ARMABI __declspec(__nothrow) +N#ifdef __TARGET_ARCH_AARCH64 +S# define _ARMABI_SOFTFP __declspec(__nothrow) +N#else +N# define _ARMABI_SOFTFP __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) +N# define __HAVE_LONGDOUBLE 1 +N#endif +N#define _ARMABI_PURE __declspec(__nothrow) __attribute__((const)) +N#ifdef __FP_FENV_EXCEPTIONS +S# define _ARMABI_FPEXCEPT _ARMABI +N#else +N# define _ARMABI_FPEXCEPT _ARMABI __attribute__((const)) +N#endif +N +N#ifdef __cplusplus +S#define _ARMABI_INLINE inline +S#define _ARMABI_INLINE_DEF inline +N#elif defined __GNUC__ || defined _USE_STATIC_INLINE +X#elif 1L || 0L +N#define _ARMABI_INLINE static __inline +N#define _ARMABI_INLINE_DEF static __inline +N#elif (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) +X#elif (1L && 199901L <= 199901L) +S#define _ARMABI_INLINE inline +S#define _ARMABI_INLINE_DEF static inline +S#else +S#define _ARMABI_INLINE __inline +S#define _ARMABI_INLINE_DEF __inline +N#endif +N +N#ifdef __TARGET_ARCH_AARCH64 +S# define _SOFTFP +N#else +N# define _SOFTFP __attribute__((__pcs__("aapcs"))) +N#endif +N +N /* +N * If the compiler supports signalling nans as per N965 then it +N * will define __SUPPORT_SNAN__, in which case a user may define +N * _WANT_SNAN in order to obtain the nans function, as well as the +N * FP_NANS and FP_NANQ classification macros. +N */ +N#if defined(__SUPPORT_SNAN__) && defined(_WANT_SNAN) +X#if 0L && 0L +S#pragma import(__use_snan) +N#endif +N +N/* +N * Macros for our inline functions down below. +N * unsigned& __FLT(float x) - returns the bit pattern of x +N * unsigned& __HI(double x) - returns the bit pattern of the high part of x +N * (high part has exponent & sign bit in it) +N * unsigned& __LO(double x) - returns the bit pattern of the low part of x +N * +N * We can assign to __FLT, __HI, and __LO and the appropriate bits get set in +N * the floating point variable used. +N * +N * __HI & __LO are affected by the endianness and the target FPU. +N */ +N#define __FLT(x) (*(unsigned *)&(x)) +N#if defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN) +X#if 0L || 0L +S# define __LO(x) (*(1 + (unsigned *)&(x))) +S# define __HI(x) (*(unsigned *)&(x)) +N#else /* !defined(__ARM_BIG_ENDIAN) && !defined(__BIG_ENDIAN) */ +N# define __HI(x) (*(1 + (unsigned *)&(x))) +N# define __LO(x) (*(unsigned *)&(x)) +N#endif /* !defined(__ARM_BIG_ENDIAN) && !defined(__BIG_ENDIAN) */ +N +N# ifndef __MATH_DECLS +N# define __MATH_DECLS +N +N +N/* +N * A set of functions that we don't actually want to put in the standard +N * namespace ever. These are all called by the C99 macros. As they're +N * not specified by any standard they can't belong in ::std::. The +N * macro #defines are below amongst the standard function declarations. +N * We only include these if we actually need them later on +N */ +N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +X#if !0L || 1L +N# ifdef __cplusplus +S extern "C" { +N# endif /* __cplusplus */ +N +Nextern _SOFTFP unsigned __ARM_dcmp4(double /*x*/, double /*y*/); +Xextern __attribute__((__pcs__("aapcs"))) unsigned __ARM_dcmp4(double , double ); +Nextern _SOFTFP unsigned __ARM_fcmp4(float /*x*/, float /*y*/); +Xextern __attribute__((__pcs__("aapcs"))) unsigned __ARM_fcmp4(float , float ); +N /* +N * Compare x and y and return the CPSR in r0. These means we can test for +N * result types with bit pattern matching. +N * +N * These are a copy of the declarations in rt_fp.h keep in sync. +N */ +N +Nextern _ARMABI_SOFTFP int __ARM_fpclassifyf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassifyf(float ); +Nextern _ARMABI_SOFTFP int __ARM_fpclassify(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassify(double ); +N /* Classify x into NaN, infinite, normal, subnormal, zero */ +N /* Used by fpclassify macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isfinitef(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinitef(float __x) +N{ +N return ((__FLT(__x) >> 23) & 0xff) != 0xff; +X return (((*(unsigned *)&(__x)) >> 23) & 0xff) != 0xff; +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isfinite(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinite(double __x) +N{ +N return ((__HI(__x) >> 20) & 0x7ff) != 0x7ff; +X return (((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff) != 0x7ff; +N} +N /* Return 1 if __x is finite, 0 otherwise */ +N /* Used by isfinite macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isinff(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinff(float __x) +N{ +N return (__FLT(__x) << 1) == 0xff000000; +X return ((*(unsigned *)&(__x)) << 1) == 0xff000000; +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isinf(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinf(double __x) +N{ +N return ((__HI(__x) << 1) == 0xffe00000) && (__LO(__x) == 0); +X return (((*(1 + (unsigned *)&(__x))) << 1) == 0xffe00000) && ((*(unsigned *)&(__x)) == 0); +N} +N /* Return 1 if __x is infinite, 0 otherwise */ +N /* Used by isinf macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_islessgreaterf(float __x, float __y) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreaterf(float __x, float __y) +N{ +N unsigned __f = __ARM_fcmp4(__x, __y) >> 28; +N return (__f == 8) || (__f == 2); /* Just N set or Just Z set */ +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_islessgreater(double __x, double __y) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreater(double __x, double __y) +N{ +N unsigned __f = __ARM_dcmp4(__x, __y) >> 28; +N return (__f == 8) || (__f == 2); /* Just N set or Just Z set */ +N} +N /* +N * Compare __x and __y and return 1 if __x < __y or __x > __y, 0 otherwise +N * Used by islessgreater macro +N */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnanf(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnanf(float __x) +N{ +N return (0x7f800000 - (__FLT(__x) & 0x7fffffff)) >> 31; +X return (0x7f800000 - ((*(unsigned *)&(__x)) & 0x7fffffff)) >> 31; +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnan(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnan(double __x) +N{ +N unsigned __xf = __HI(__x) | ((__LO(__x) == 0) ? 0 : 1); +X unsigned __xf = (*(1 + (unsigned *)&(__x))) | (((*(unsigned *)&(__x)) == 0) ? 0 : 1); +N return (0x7ff00000 - (__xf & 0x7fffffff)) >> 31; +N} +N /* Return 1 if __x is a NaN, 0 otherwise */ +N /* Used by isnan macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnormalf(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormalf(float __x) +N{ +N unsigned __xe = (__FLT(__x) >> 23) & 0xff; +X unsigned __xe = ((*(unsigned *)&(__x)) >> 23) & 0xff; +N return (__xe != 0xff) && (__xe != 0); +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnormal(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormal(double __x) +N{ +N unsigned __xe = (__HI(__x) >> 20) & 0x7ff; +X unsigned __xe = ((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff; +N return (__xe != 0x7ff) && (__xe != 0); +N} +N /* Return 1 if __x is a normalised number, 0 otherwise */ +N /* used by isnormal macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_signbitf(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbitf(float __x) +N{ +N return __FLT(__x) >> 31; +X return (*(unsigned *)&(__x)) >> 31; +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_signbit(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbit(double __x) +N{ +N return __HI(__x) >> 31; +X return (*(1 + (unsigned *)&(__x))) >> 31; +N} +N /* Return signbit of __x */ +N /* Used by signbit macro */ +N +N# ifdef __cplusplus +S } /* extern "C" */ +N# endif /* __cplusplus */ +N#endif /* Strict ANSI */ +N +N# undef __CLIBNS +N +N# ifdef __cplusplus +S namespace std { +S# define __CLIBNS ::std:: +S extern "C" { +N# else +N# define __CLIBNS +N# endif /* __cplusplus */ +N +N +N#ifndef __has_builtin +N #define __has_builtin(x) 0 +N#endif +N +N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +X#if !0L || 1L +N /* C99 additions */ +N typedef float float_t; +N typedef double double_t; +N#if __has_builtin(__builtin_inf) +X#if 0 +S# define HUGE_VALF __builtin_inff() +S# define HUGE_VALL __builtin_infl() +S# define INFINITY __builtin_inff() +S# define NAN __builtin_nanf("") +N# else +N# define HUGE_VALF ((float)__INFINITY__) +N# define HUGE_VALL ((long double)__INFINITY__) +N# define INFINITY ((float)__INFINITY__) +N# define NAN (__ESCAPE__(0f_7FC00000)) +N#endif +N +N# define MATH_ERRNO 1 +N# define MATH_ERREXCEPT 2 +Nextern const int math_errhandling; +N#endif +N#if __has_builtin(__builtin_inf) +X#if 0 +S# define HUGE_VAL __builtin_inf() +N#else +N# define HUGE_VAL ((double)__INFINITY__) +N#endif +N +Nextern _ARMABI double acos(double /*x*/); +Xextern __declspec(__nothrow) double acos(double ); +N /* computes the principal value of the arc cosine of x */ +N /* a domain error occurs for arguments not in the range -1 to 1 */ +N /* Returns: the arc cosine in the range 0 to Pi. */ +Nextern _ARMABI double asin(double /*x*/); +Xextern __declspec(__nothrow) double asin(double ); +N /* computes the principal value of the arc sine of x */ +N /* a domain error occurs for arguments not in the range -1 to 1 */ +N /* and -HUGE_VAL is returned. */ +N /* Returns: the arc sine in the range -Pi/2 to Pi/2. */ +N +Nextern _ARMABI_PURE double atan(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double atan(double ); +N /* computes the principal value of the arc tangent of x */ +N /* Returns: the arc tangent in the range -Pi/2 to Pi/2. */ +N +Nextern _ARMABI double atan2(double /*y*/, double /*x*/); +Xextern __declspec(__nothrow) double atan2(double , double ); +N /* computes the principal value of the arc tangent of y/x, using the */ +N /* signs of both arguments to determine the quadrant of the return value */ +N /* a domain error occurs if both args are zero, and -HUGE_VAL returned. */ +N /* Returns: the arc tangent of y/x, in the range -Pi to Pi. */ +N +Nextern _ARMABI double cos(double /*x*/); +Xextern __declspec(__nothrow) double cos(double ); +N /* computes the cosine of x (measured in radians). A large magnitude */ +N /* argument may yield a result with little or no significance. */ +N /* a domain error occurs for infinite input (C 7.12.1 footnote 196). */ +N /* Returns: the cosine value. */ +Nextern _ARMABI double sin(double /*x*/); +Xextern __declspec(__nothrow) double sin(double ); +N /* computes the sine of x (measured in radians). A large magnitude */ +N /* argument may yield a result with little or no significance. */ +N /* a domain error occurs for infinite input (C 7.12.1 footnote 196). */ +N /* Returns: the sine value. */ +N +Nextern void __use_accurate_range_reduction(void); +N /* reference this to select the larger, slower, but more accurate */ +N /* range reduction in sin, cos and tan */ +N +Nextern _ARMABI double tan(double /*x*/); +Xextern __declspec(__nothrow) double tan(double ); +N /* computes the tangent of x (measured in radians). A large magnitude */ +N /* argument may yield a result with little or no significance */ +N /* Returns: the tangent value. */ +N /* if range error; returns HUGE_VAL. */ +N +Nextern _ARMABI double cosh(double /*x*/); +Xextern __declspec(__nothrow) double cosh(double ); +N /* computes the hyperbolic cosine of x. A range error occurs if the */ +N /* magnitude of x is too large. */ +N /* Returns: the hyperbolic cosine value. */ +N /* if range error; returns HUGE_VAL. */ +Nextern _ARMABI double sinh(double /*x*/); +Xextern __declspec(__nothrow) double sinh(double ); +N /* computes the hyperbolic sine of x. A range error occurs if the */ +N /* magnitude of x is too large. */ +N /* Returns: the hyperbolic sine value. */ +N /* if range error; returns -HUGE_VAL or HUGE_VAL depending */ +N /* on the sign of the argument */ +N +Nextern _ARMABI_PURE double tanh(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double tanh(double ); +N /* computes the hyperbolic tangent of x. */ +N /* Returns: the hyperbolic tangent value. */ +N +Nextern _ARMABI double exp(double /*x*/); +Xextern __declspec(__nothrow) double exp(double ); +N /* computes the exponential function of x. A range error occurs if the */ +N /* magnitude of x is too large. */ +N /* Returns: the exponential value. */ +N /* if underflow range error; 0 is returned. */ +N /* if overflow range error; HUGE_VAL is returned. */ +N +Nextern _ARMABI double frexp(double /*value*/, int * /*exp*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) double frexp(double , int * ) __attribute__((__nonnull__(2))); +N /* breaks a floating-point number into a normalised fraction and an */ +N /* integral power of 2. It stores the integer in the int object pointed */ +N /* to by exp. */ +N /* Returns: the value x, such that x is a double with magnitude in the */ +N /* interval 0.5 to 1.0 or zero, and value equals x times 2 raised to the */ +N /* power *exp. If value is zero, both parts of the result are zero. */ +N +Nextern _ARMABI double ldexp(double /*x*/, int /*exp*/); +Xextern __declspec(__nothrow) double ldexp(double , int ); +N /* multiplies a floating-point number by an integral power of 2. */ +N /* A range error may occur. */ +N /* Returns: the value of x times 2 raised to the power of exp. */ +N /* if range error; HUGE_VAL is returned. */ +Nextern _ARMABI double log(double /*x*/); +Xextern __declspec(__nothrow) double log(double ); +N /* computes the natural logarithm of x. A domain error occurs if the */ +N /* argument is negative, and -HUGE_VAL is returned. A range error occurs */ +N /* if the argument is zero. */ +N /* Returns: the natural logarithm. */ +N /* if range error; -HUGE_VAL is returned. */ +Nextern _ARMABI double log10(double /*x*/); +Xextern __declspec(__nothrow) double log10(double ); +N /* computes the base-ten logarithm of x. A domain error occurs if the */ +N /* argument is negative. A range error occurs if the argument is zero. */ +N /* Returns: the base-ten logarithm. */ +Nextern _ARMABI double modf(double /*value*/, double * /*iptr*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) double modf(double , double * ) __attribute__((__nonnull__(2))); +N /* breaks the argument value into integral and fraction parts, each of */ +N /* which has the same sign as the argument. It stores the integral part */ +N /* as a double in the object pointed to by iptr. */ +N /* Returns: the signed fractional part of value. */ +N +Nextern _ARMABI double pow(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double pow(double , double ); +N /* computes x raised to the power of y. A domain error occurs if x is */ +N /* zero and y is less than or equal to zero, or if x is negative and y */ +N /* is not an integer, and -HUGE_VAL returned. A range error may occur. */ +N /* Returns: the value of x raised to the power of y. */ +N /* if underflow range error; 0 is returned. */ +N /* if overflow range error; HUGE_VAL is returned. */ +Nextern _ARMABI double sqrt(double /*x*/); +Xextern __declspec(__nothrow) double sqrt(double ); +N /* computes the non-negative square root of x. A domain error occurs */ +N /* if the argument is negative, and -HUGE_VAL returned. */ +N /* Returns: the value of the square root. */ +N +N#if defined(__TARGET_FPU_VFP_DOUBLE) && !defined(__TARGET_FPU_SOFTVFP) +X#if 0L && !1L +S _ARMABI_INLINE double _sqrt(double __x) { return __sqrt(__x); } +N#else +N _ARMABI_INLINE double _sqrt(double __x) { return sqrt(__x); } +X static __inline double _sqrt(double __x) { return sqrt(__x); } +N#endif +N#if defined(__TARGET_FPU_VFP_SINGLE) && !defined(__TARGET_FPU_SOFTVFP) +X#if 0L && !1L +S _ARMABI_INLINE float _sqrtf(float __x) { return __sqrtf(__x); } +N#else +N _ARMABI_INLINE float _sqrtf(float __x) { return (float)sqrt(__x); } +X static __inline float _sqrtf(float __x) { return (float)sqrt(__x); } +N#endif +N /* With VFP, _sqrt and _sqrtf should expand inline as the native VFP square root +N * instructions. They will not behave like the C sqrt() function, because +N * they will report unusual values as IEEE exceptions (in fpmodes which +N * support IEEE exceptions) rather than in errno. These function names +N * are not specified in any standard. */ +N +Nextern _ARMABI_PURE double ceil(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double ceil(double ); +N /* computes the smallest integer not less than x. */ +N /* Returns: the smallest integer not less than x, expressed as a double. */ +Nextern _ARMABI_PURE double fabs(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double fabs(double ); +N /* computes the absolute value of the floating-point number x. */ +N /* Returns: the absolute value of x. */ +N +Nextern _ARMABI_PURE double floor(double /*d*/); +Xextern __declspec(__nothrow) __attribute__((const)) double floor(double ); +N /* computes the largest integer not greater than x. */ +N /* Returns: the largest integer not greater than x, expressed as a double */ +N +Nextern _ARMABI double fmod(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double fmod(double , double ); +N /* computes the floating-point remainder of x/y. */ +N /* Returns: the value x - i * y, for some integer i such that, if y is */ +N /* nonzero, the result has the same sign as x and magnitude */ +N /* less than the magnitude of y. If y is zero, a domain error */ +N /* occurs and -HUGE_VAL is returned. */ +N +N /* Additional Mathlib functions not defined by the ANSI standard. +N * Not guaranteed, and not necessarily very well tested. +N * C99 requires the user to include to use these functions +N * declaring them "by hand" is not sufficient +N * +N * The above statement is not completely true now. Some of the above +N * C99 functionality has been added as per the Standard, and (where +N * necessary) old Mathlib functionality withdrawn/changed. Before +N * including this header #define __ENABLE_MATHLIB_LEGACY if you want to +N * re-enable the legacy functionality. +N */ +N +N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +X#if !0L || 1L +N +Nextern _ARMABI double acosh(double /*x*/); +Xextern __declspec(__nothrow) double acosh(double ); +N /* +N * Inverse cosh. EDOM if argument < 1.0 +N */ +Nextern _ARMABI double asinh(double /*x*/); +Xextern __declspec(__nothrow) double asinh(double ); +N /* +N * Inverse sinh. +N */ +Nextern _ARMABI double atanh(double /*x*/); +Xextern __declspec(__nothrow) double atanh(double ); +N /* +N * Inverse tanh. EDOM if |argument| > 1.0 +N */ +Nextern _ARMABI double cbrt(double /*x*/); +Xextern __declspec(__nothrow) double cbrt(double ); +N /* +N * Cube root. +N */ +N_ARMABI_INLINE _ARMABI_PURE double copysign(double __x, double __y) +Xstatic __inline __declspec(__nothrow) __attribute__((const)) double copysign(double __x, double __y) +N /* +N * Returns x with sign bit replaced by sign of y. +N */ +N{ +N __HI(__x) = (__HI(__x) & 0x7fffffff) | (__HI(__y) & 0x80000000); +X (*(1 + (unsigned *)&(__x))) = ((*(1 + (unsigned *)&(__x))) & 0x7fffffff) | ((*(1 + (unsigned *)&(__y))) & 0x80000000); +N return __x; +N} +N_ARMABI_INLINE _ARMABI_PURE float copysignf(float __x, float __y) +Xstatic __inline __declspec(__nothrow) __attribute__((const)) float copysignf(float __x, float __y) +N /* +N * Returns x with sign bit replaced by sign of y. +N */ +N{ +N __FLT(__x) = (__FLT(__x) & 0x7fffffff) | (__FLT(__y) & 0x80000000); +X (*(unsigned *)&(__x)) = ((*(unsigned *)&(__x)) & 0x7fffffff) | ((*(unsigned *)&(__y)) & 0x80000000); +N return __x; +N} +Nextern _ARMABI double erf(double /*x*/); +Xextern __declspec(__nothrow) double erf(double ); +N /* +N * Error function. (2/sqrt(pi)) * integral from 0 to x of exp(-t*t) dt. +N */ +Nextern _ARMABI double erfc(double /*x*/); +Xextern __declspec(__nothrow) double erfc(double ); +N /* +N * 1-erf(x). (More accurate than just coding 1-erf(x), for large x.) +N */ +Nextern _ARMABI double expm1(double /*x*/); +Xextern __declspec(__nothrow) double expm1(double ); +N /* +N * exp(x)-1. (More accurate than just coding exp(x)-1, for small x.) +N */ +N#define fpclassify(x) \ +N ((sizeof(x) == sizeof(float)) ? \ +N __ARM_fpclassifyf(x) : __ARM_fpclassify(x)) +X#define fpclassify(x) ((sizeof(x) == sizeof(float)) ? __ARM_fpclassifyf(x) : __ARM_fpclassify(x)) +N /* +N * Classify a floating point number into one of the following values: +N */ +N#define FP_ZERO (0) +N#define FP_SUBNORMAL (4) +N#define FP_NORMAL (5) +N#define FP_INFINITE (3) +N#define FP_NAN (7) +N +N#if defined(_WANT_SNAN) && defined(__SUPPORT_SNAN__) +X#if 0L && 0L +S/* +S * Note that we'll never classify a number as FP_NAN, as all NaNs will +S * be either FP_NANQ or FP_NANS +S */ +S# define FP_NANQ (8) +S# define FP_NANS (9) +N#endif +N +N +Nextern _ARMABI double hypot(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double hypot(double , double ); +N /* +N * sqrt(x*x+y*y), ie the length of the vector (x,y) or the +N * hypotenuse of a right triangle whose other two sides are x +N * and y. Won't overflow unless the _answer_ is too big, even +N * if the intermediate x*x+y*y is too big. +N */ +Nextern _ARMABI int ilogb(double /*x*/); +Xextern __declspec(__nothrow) int ilogb(double ); +N /* +N * Exponent of x (returns 0 for 1.0, 1 for 2.0, -1 for 0.5, etc.) +N */ +Nextern _ARMABI int ilogbf(float /*x*/); +Xextern __declspec(__nothrow) int ilogbf(float ); +N /* +N * Like ilogb but takes a float +N */ +Nextern _ARMABI int ilogbl(long double /*x*/); +Xextern __declspec(__nothrow) int ilogbl(long double ); +N /* +N * Exponent of x (returns 0 for 1.0, 1 for 2.0, -1 for 0.5, etc.) +N */ +N#define FP_ILOGB0 (-0x7fffffff) /* ilogb(0) == -INT_MAX */ +N#define FP_ILOGBNAN ( 0x80000000) /* ilogb(NAN) == INT_MIN */ +N +N#define isfinite(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_isfinitef(x) \ +N : __ARM_isfinite(x)) +X#define isfinite(x) ((sizeof(x) == sizeof(float)) ? __ARM_isfinitef(x) : __ARM_isfinite(x)) +N /* +N * Returns true if x is a finite number, size independent. +N */ +N +N#define isgreater(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000) \ +N : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000)) +X#define isgreater(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000)) +N /* +N * Returns true if x > y, throws no exceptions except on Signaling NaNs +N * +N * We want the C not set but the Z bit clear, V must be clear +N */ +N +N#define isgreaterequal(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000) \ +N : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000)) +X#define isgreaterequal(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000)) +N /* +N * Returns true if x >= y, throws no exceptions except on Signaling NaNs +N * +N * We just need to see if the C bit is set or not and ensure V clear +N */ +N +N#define isinf(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_isinff(x) \ +N : __ARM_isinf(x)) +X#define isinf(x) ((sizeof(x) == sizeof(float)) ? __ARM_isinff(x) : __ARM_isinf(x)) +N /* +N * Returns true if x is an infinity, size independent. +N */ +N +N#define isless(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000) \ +N : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000)) +X#define isless(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000)) +N /* +N * Returns true if x < y, throws no exceptions except on Signaling NaNs +N * +N * We're less than if N is set, V clear +N */ +N +N#define islessequal(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0) \ +N : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0)) +X#define islessequal(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0) : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0)) +N /* +N * Returns true if x <= y, throws no exceptions except on Signaling NaNs +N * +N * We're less than or equal if one of N or Z is set, V clear +N */ +N +N#define islessgreater(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? __ARM_islessgreaterf((x), (y)) \ +N : __ARM_islessgreater((x), (y))) +X#define islessgreater(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? __ARM_islessgreaterf((x), (y)) : __ARM_islessgreater((x), (y))) +N /* +N * Returns true if x <> y, throws no exceptions except on Signaling NaNs +N * Unfortunately this test is too complicated to do in a macro without +N * evaluating x & y twice. Shame really... +N */ +N +N#define isnan(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_isnanf(x) \ +N : __ARM_isnan(x)) +X#define isnan(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnanf(x) : __ARM_isnan(x)) +N /* +N * Returns TRUE if x is a NaN. +N */ +N +N#define isnormal(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_isnormalf(x) \ +N : __ARM_isnormal(x)) +X#define isnormal(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnormalf(x) : __ARM_isnormal(x)) +N /* +N * Returns TRUE if x is a NaN. +N */ +N +N#define isunordered(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000) \ +N : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000)) +X#define isunordered(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000) : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000)) +N /* +N * Returns true if x ? y, throws no exceptions except on Signaling NaNs +N * Unordered occurs if and only if the V bit is set +N */ +N +Nextern _ARMABI double lgamma (double /*x*/); +Xextern __declspec(__nothrow) double lgamma (double ); +N /* +N * The log of the absolute value of the gamma function of x. The sign +N * of the gamma function of x is returned in the global `signgam'. +N */ +Nextern _ARMABI double log1p(double /*x*/); +Xextern __declspec(__nothrow) double log1p(double ); +N /* +N * log(1+x). (More accurate than just coding log(1+x), for small x.) +N */ +Nextern _ARMABI double logb(double /*x*/); +Xextern __declspec(__nothrow) double logb(double ); +N /* +N * Like ilogb but returns a double. +N */ +Nextern _ARMABI float logbf(float /*x*/); +Xextern __declspec(__nothrow) float logbf(float ); +N /* +N * Like logb but takes and returns float +N */ +Nextern _ARMABI long double logbl(long double /*x*/); +Xextern __declspec(__nothrow) long double logbl(long double ); +N /* +N * Like logb but takes and returns long double +N */ +Nextern _ARMABI double nextafter(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double nextafter(double , double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI float nextafterf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float nextafterf(float , float ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI long double nextafterl(long double /*x*/, long double /*y*/); +Xextern __declspec(__nothrow) long double nextafterl(long double , long double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI double nexttoward(double /*x*/, long double /*y*/); +Xextern __declspec(__nothrow) double nexttoward(double , long double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI float nexttowardf(float /*x*/, long double /*y*/); +Xextern __declspec(__nothrow) float nexttowardf(float , long double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI long double nexttowardl(long double /*x*/, long double /*y*/); +Xextern __declspec(__nothrow) long double nexttowardl(long double , long double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI double remainder(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double remainder(double , double ); +N /* +N * Returns the remainder of x by y, in the IEEE 754 sense. +N */ +Nextern _ARMABI_FPEXCEPT double rint(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double rint(double ); +N /* +N * Rounds x to an integer, in the IEEE 754 sense. +N */ +Nextern _ARMABI double scalbln(double /*x*/, long int /*n*/); +Xextern __declspec(__nothrow) double scalbln(double , long int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI float scalblnf(float /*x*/, long int /*n*/); +Xextern __declspec(__nothrow) float scalblnf(float , long int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI long double scalblnl(long double /*x*/, long int /*n*/); +Xextern __declspec(__nothrow) long double scalblnl(long double , long int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI double scalbn(double /*x*/, int /*n*/); +Xextern __declspec(__nothrow) double scalbn(double , int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI float scalbnf(float /*x*/, int /*n*/); +Xextern __declspec(__nothrow) float scalbnf(float , int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI long double scalbnl(long double /*x*/, int /*n*/); +Xextern __declspec(__nothrow) long double scalbnl(long double , int ); +N /* +N * Compute x times 2^n quickly. +N */ +N#define signbit(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_signbitf(x) \ +N : __ARM_signbit(x)) +X#define signbit(x) ((sizeof(x) == sizeof(float)) ? __ARM_signbitf(x) : __ARM_signbit(x)) +N /* +N * Returns the signbit of x, size independent macro +N */ +N#endif +N +N/* C99 float versions of functions. math.h has always reserved these +N identifiers for this purpose (7.13.4). */ +Nextern _ARMABI_PURE float _fabsf(float); /* old ARM name */ +Xextern __declspec(__nothrow) __attribute__((const)) float _fabsf(float); +N_ARMABI_INLINE _ARMABI_PURE float fabsf(float __f) { return _fabsf(__f); } +Xstatic __inline __declspec(__nothrow) __attribute__((const)) float fabsf(float __f) { return _fabsf(__f); } +Nextern _ARMABI float sinf(float /*x*/); +Xextern __declspec(__nothrow) float sinf(float ); +Nextern _ARMABI float cosf(float /*x*/); +Xextern __declspec(__nothrow) float cosf(float ); +Nextern _ARMABI float tanf(float /*x*/); +Xextern __declspec(__nothrow) float tanf(float ); +Nextern _ARMABI float acosf(float /*x*/); +Xextern __declspec(__nothrow) float acosf(float ); +Nextern _ARMABI float asinf(float /*x*/); +Xextern __declspec(__nothrow) float asinf(float ); +Nextern _ARMABI float atanf(float /*x*/); +Xextern __declspec(__nothrow) float atanf(float ); +Nextern _ARMABI float atan2f(float /*y*/, float /*x*/); +Xextern __declspec(__nothrow) float atan2f(float , float ); +Nextern _ARMABI float sinhf(float /*x*/); +Xextern __declspec(__nothrow) float sinhf(float ); +Nextern _ARMABI float coshf(float /*x*/); +Xextern __declspec(__nothrow) float coshf(float ); +Nextern _ARMABI float tanhf(float /*x*/); +Xextern __declspec(__nothrow) float tanhf(float ); +Nextern _ARMABI float expf(float /*x*/); +Xextern __declspec(__nothrow) float expf(float ); +Nextern _ARMABI float logf(float /*x*/); +Xextern __declspec(__nothrow) float logf(float ); +Nextern _ARMABI float log10f(float /*x*/); +Xextern __declspec(__nothrow) float log10f(float ); +Nextern _ARMABI float powf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float powf(float , float ); +Nextern _ARMABI float sqrtf(float /*x*/); +Xextern __declspec(__nothrow) float sqrtf(float ); +Nextern _ARMABI float ldexpf(float /*x*/, int /*exp*/); +Xextern __declspec(__nothrow) float ldexpf(float , int ); +Nextern _ARMABI float frexpf(float /*value*/, int * /*exp*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) float frexpf(float , int * ) __attribute__((__nonnull__(2))); +Nextern _ARMABI_PURE float ceilf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float ceilf(float ); +Nextern _ARMABI_PURE float floorf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float floorf(float ); +Nextern _ARMABI float fmodf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float fmodf(float , float ); +Nextern _ARMABI float modff(float /*value*/, float * /*iptr*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) float modff(float , float * ) __attribute__((__nonnull__(2))); +N +N/* C99 long double versions of functions. */ +N/* (also need to have 'using' declarations below) */ +N#define _ARMDEFLD1(f) \ +N _ARMABI long double f##l(long double /*x*/) +X#define _ARMDEFLD1(f) _ARMABI long double f##l(long double ) +N +N#define _ARMDEFLD1P(f, T) \ +N _ARMABI long double f##l(long double /*x*/, T /*p*/) +X#define _ARMDEFLD1P(f, T) _ARMABI long double f##l(long double , T ) +N +N#define _ARMDEFLD2(f) \ +N _ARMABI long double f##l(long double /*x*/, long double /*y*/) +X#define _ARMDEFLD2(f) _ARMABI long double f##l(long double , long double ) +N +N/* +N * Long double versions of C89 functions can be defined +N * unconditionally, because C89 reserved these names in "future +N * library directions". +N */ +N_ARMDEFLD1(acos); +X__declspec(__nothrow) long double acosl(long double ); +N_ARMDEFLD1(asin); +X__declspec(__nothrow) long double asinl(long double ); +N_ARMDEFLD1(atan); +X__declspec(__nothrow) long double atanl(long double ); +N_ARMDEFLD2(atan2); +X__declspec(__nothrow) long double atan2l(long double , long double ); +N_ARMDEFLD1(ceil); +X__declspec(__nothrow) long double ceill(long double ); +N_ARMDEFLD1(cos); +X__declspec(__nothrow) long double cosl(long double ); +N_ARMDEFLD1(cosh); +X__declspec(__nothrow) long double coshl(long double ); +N_ARMDEFLD1(exp); +X__declspec(__nothrow) long double expl(long double ); +N_ARMDEFLD1(fabs); +X__declspec(__nothrow) long double fabsl(long double ); +N_ARMDEFLD1(floor); +X__declspec(__nothrow) long double floorl(long double ); +N_ARMDEFLD2(fmod); +X__declspec(__nothrow) long double fmodl(long double , long double ); +N_ARMDEFLD1P(frexp, int*) __attribute__((__nonnull__(2))); +X__declspec(__nothrow) long double frexpl(long double , int* ) __attribute__((__nonnull__(2))); +N_ARMDEFLD1P(ldexp, int); +X__declspec(__nothrow) long double ldexpl(long double , int ); +N_ARMDEFLD1(log); +X__declspec(__nothrow) long double logl(long double ); +N_ARMDEFLD1(log10); +X__declspec(__nothrow) long double log10l(long double ); +N_ARMABI long double modfl(long double /*x*/, long double * /*p*/) __attribute__((__nonnull__(2))); +X__declspec(__nothrow) long double modfl(long double , long double * ) __attribute__((__nonnull__(2))); +N_ARMDEFLD2(pow); +X__declspec(__nothrow) long double powl(long double , long double ); +N_ARMDEFLD1(sin); +X__declspec(__nothrow) long double sinl(long double ); +N_ARMDEFLD1(sinh); +X__declspec(__nothrow) long double sinhl(long double ); +N_ARMDEFLD1(sqrt); +X__declspec(__nothrow) long double sqrtl(long double ); +N_ARMDEFLD1(tan); +X__declspec(__nothrow) long double tanl(long double ); +N_ARMDEFLD1(tanh); +X__declspec(__nothrow) long double tanhl(long double ); +N +N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +X#if !0L || 1L +N +N/* +N * C99 float and long double versions of extra-C89 functions. +N */ +Nextern _ARMABI float acoshf(float /*x*/); +Xextern __declspec(__nothrow) float acoshf(float ); +N_ARMDEFLD1(acosh); +X__declspec(__nothrow) long double acoshl(long double ); +Nextern _ARMABI float asinhf(float /*x*/); +Xextern __declspec(__nothrow) float asinhf(float ); +N_ARMDEFLD1(asinh); +X__declspec(__nothrow) long double asinhl(long double ); +Nextern _ARMABI float atanhf(float /*x*/); +Xextern __declspec(__nothrow) float atanhf(float ); +N_ARMDEFLD1(atanh); +X__declspec(__nothrow) long double atanhl(long double ); +N_ARMDEFLD2(copysign); +X__declspec(__nothrow) long double copysignl(long double , long double ); +Nextern _ARMABI float cbrtf(float /*x*/); +Xextern __declspec(__nothrow) float cbrtf(float ); +N_ARMDEFLD1(cbrt); +X__declspec(__nothrow) long double cbrtl(long double ); +Nextern _ARMABI float erff(float /*x*/); +Xextern __declspec(__nothrow) float erff(float ); +N_ARMDEFLD1(erf); +X__declspec(__nothrow) long double erfl(long double ); +Nextern _ARMABI float erfcf(float /*x*/); +Xextern __declspec(__nothrow) float erfcf(float ); +N_ARMDEFLD1(erfc); +X__declspec(__nothrow) long double erfcl(long double ); +Nextern _ARMABI float expm1f(float /*x*/); +Xextern __declspec(__nothrow) float expm1f(float ); +N_ARMDEFLD1(expm1); +X__declspec(__nothrow) long double expm1l(long double ); +Nextern _ARMABI float log1pf(float /*x*/); +Xextern __declspec(__nothrow) float log1pf(float ); +N_ARMDEFLD1(log1p); +X__declspec(__nothrow) long double log1pl(long double ); +Nextern _ARMABI float hypotf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float hypotf(float , float ); +N_ARMDEFLD2(hypot); +X__declspec(__nothrow) long double hypotl(long double , long double ); +Nextern _ARMABI float lgammaf(float /*x*/); +Xextern __declspec(__nothrow) float lgammaf(float ); +N_ARMDEFLD1(lgamma); +X__declspec(__nothrow) long double lgammal(long double ); +Nextern _ARMABI float remainderf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float remainderf(float , float ); +N_ARMDEFLD2(remainder); +X__declspec(__nothrow) long double remainderl(long double , long double ); +Nextern _ARMABI float rintf(float /*x*/); +Xextern __declspec(__nothrow) float rintf(float ); +N_ARMDEFLD1(rint); +X__declspec(__nothrow) long double rintl(long double ); +N +N#endif +N +N#if (defined(__clang__) && !defined(__STRICT_ANSI)) || defined(__USE_C99_MATH) +X#if (0L && !0L) || 1L +N/* +N * Functions new in C99. +N */ +Nextern _ARMABI double exp2(double /*x*/); /* * 2.^x. */ +Xextern __declspec(__nothrow) double exp2(double ); +Nextern _ARMABI float exp2f(float /*x*/); +Xextern __declspec(__nothrow) float exp2f(float ); +N_ARMDEFLD1(exp2); +X__declspec(__nothrow) long double exp2l(long double ); +Nextern _ARMABI double fdim(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double fdim(double , double ); +Nextern _ARMABI float fdimf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float fdimf(float , float ); +N_ARMDEFLD2(fdim); +X__declspec(__nothrow) long double fdiml(long double , long double ); +N#ifdef __FP_FAST_FMA +S#define FP_FAST_FMA +N#endif +N#ifdef __FP_FAST_FMAF +S#define FP_FAST_FMAF +N#endif +N#ifdef __FP_FAST_FMAL +S#define FP_FAST_FMAL +N#endif +Nextern _ARMABI double fma(double /*x*/, double /*y*/, double /*z*/); +Xextern __declspec(__nothrow) double fma(double , double , double ); +Nextern _ARMABI float fmaf(float /*x*/, float /*y*/, float /*z*/); +Xextern __declspec(__nothrow) float fmaf(float , float , float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI long double fmal(long double __x, long double __y, long double __z) \ +N { return (long double)fma((double)__x, (double)__y, (double)__z); } +Xstatic __inline __declspec(__nothrow) long double fmal(long double __x, long double __y, long double __z) { return (long double)fma((double)__x, (double)__y, (double)__z); } +N#endif +Nextern _ARMABI_FPEXCEPT double fmax(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) __attribute__((const)) double fmax(double , double ); +Nextern _ARMABI_FPEXCEPT float fmaxf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) __attribute__((const)) float fmaxf(float , float ); +N_ARMDEFLD2(fmax); +X__declspec(__nothrow) long double fmaxl(long double , long double ); +Nextern _ARMABI_FPEXCEPT double fmin(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) __attribute__((const)) double fmin(double , double ); +Nextern _ARMABI_FPEXCEPT float fminf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) __attribute__((const)) float fminf(float , float ); +N_ARMDEFLD2(fmin); +X__declspec(__nothrow) long double fminl(long double , long double ); +Nextern _ARMABI double log2(double /*x*/); /* * log base 2 of x. */ +Xextern __declspec(__nothrow) double log2(double ); +Nextern _ARMABI float log2f(float /*x*/); +Xextern __declspec(__nothrow) float log2f(float ); +N_ARMDEFLD1(log2); +X__declspec(__nothrow) long double log2l(long double ); +Nextern _ARMABI long lrint(double /*x*/); +Xextern __declspec(__nothrow) long lrint(double ); +Nextern _ARMABI long lrintf(float /*x*/); +Xextern __declspec(__nothrow) long lrintf(float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI long lrintl(long double __x) \ +N { return lrint((double)__x); } +Xstatic __inline __declspec(__nothrow) long lrintl(long double __x) { return lrint((double)__x); } +N#endif +Nextern _ARMABI __LONGLONG llrint(double /*x*/); +Xextern __declspec(__nothrow) long long llrint(double ); +Nextern _ARMABI __LONGLONG llrintf(float /*x*/); +Xextern __declspec(__nothrow) long long llrintf(float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI __LONGLONG llrintl(long double __x) \ +N { return llrint((double)__x); } +Xstatic __inline __declspec(__nothrow) long long llrintl(long double __x) { return llrint((double)__x); } +N#endif +Nextern _ARMABI long lround(double /*x*/); +Xextern __declspec(__nothrow) long lround(double ); +Nextern _ARMABI long lroundf(float /*x*/); +Xextern __declspec(__nothrow) long lroundf(float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI long lroundl(long double __x) \ +N { return lround((double)__x); } +Xstatic __inline __declspec(__nothrow) long lroundl(long double __x) { return lround((double)__x); } +N#endif +Nextern _ARMABI __LONGLONG llround(double /*x*/); +Xextern __declspec(__nothrow) long long llround(double ); +Nextern _ARMABI __LONGLONG llroundf(float /*x*/); +Xextern __declspec(__nothrow) long long llroundf(float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI __LONGLONG llroundl(long double __x) \ +N { return llround((double)__x); } +Xstatic __inline __declspec(__nothrow) long long llroundl(long double __x) { return llround((double)__x); } +N#endif +Nextern _ARMABI_PURE double nan(const char */*tagp*/); +Xextern __declspec(__nothrow) __attribute__((const)) double nan(const char * ); +Nextern _ARMABI_PURE float nanf(const char */*tagp*/); +Xextern __declspec(__nothrow) __attribute__((const)) float nanf(const char * ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI_PURE long double nanl(const char *__t) \ +N { return (long double)nan(__t); } +Xstatic __inline __declspec(__nothrow) __attribute__((const)) long double nanl(const char *__t) { return (long double)nan(__t); } +N#endif +N#if defined(_WANT_SNAN) && defined(__SUPPORT_SNAN__) +X#if 0L && 0L +Sextern _ARMABI_PURE double nans(const char */*tagp*/); +Sextern _ARMABI_PURE float nansf(const char */*tagp*/); +S#ifdef __HAVE_LONGDOUBLE +S_ARMABI_INLINE _ARMABI_FPEXCEPT long double nansl(const char *__t) \ +S { return (long double)nans(__t); } +X_ARMABI_INLINE _ARMABI_FPEXCEPT long double nansl(const char *__t) { return (long double)nans(__t); } +S#endif +N#endif +Nextern _ARMABI_FPEXCEPT double nearbyint(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double nearbyint(double ); +Nextern _ARMABI_FPEXCEPT float nearbyintf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float nearbyintf(float ); +N_ARMDEFLD1(nearbyint); +X__declspec(__nothrow) long double nearbyintl(long double ); +Nextern double remquo(double /*x*/, double /*y*/, int */*quo*/); +Nextern float remquof(float /*x*/, float /*y*/, int */*quo*/); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE long double remquol(long double __x, long double __y, int *__q) \ +N { return (long double)remquo((double)__x, (double)__y, __q); } +Xstatic __inline long double remquol(long double __x, long double __y, int *__q) { return (long double)remquo((double)__x, (double)__y, __q); } +N#endif +Nextern _ARMABI_FPEXCEPT double round(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double round(double ); +Nextern _ARMABI_FPEXCEPT float roundf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float roundf(float ); +N_ARMDEFLD1(round); +X__declspec(__nothrow) long double roundl(long double ); +Nextern _ARMABI double tgamma(double /*x*/); /* * The gamma function of x. */ +Xextern __declspec(__nothrow) double tgamma(double ); +Nextern _ARMABI float tgammaf(float /*x*/); +Xextern __declspec(__nothrow) float tgammaf(float ); +N_ARMDEFLD1(tgamma); +X__declspec(__nothrow) long double tgammal(long double ); +Nextern _ARMABI_FPEXCEPT double trunc(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double trunc(double ); +Nextern _ARMABI_FPEXCEPT float truncf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float truncf(float ); +N_ARMDEFLD1(trunc); +X__declspec(__nothrow) long double truncl(long double ); +N#endif +N +N#undef _ARMDEFLD1 +N#undef _ARMDEFLD1P +N#undef _ARMDEFLD2 +N +N#if defined(__cplusplus) && ((!defined(__STRICT_ANSI__) || defined(__USE_C99_MATH)) || defined(__ARMCOMPILER_LIBCXX)) +X#if 0L && ((!0L || 1L) || 0L) +S extern "C++" { +S inline int (fpclassify)(double __x) { return fpclassify(__x); } +S inline bool (isfinite)(double __x) { return isfinite(__x); } +S inline bool (isgreater)(double __x, double __y) { return isgreater(__x, __y); } +S inline bool (isgreaterequal)(double __x, double __y) { return isgreaterequal(__x, __y); } +S inline bool (isinf)(double __x) { return isinf(__x); } +S inline bool (isless)(double __x, double __y) { return isless(__x, __y); } +S inline bool (islessequal)(double __x, double __y) { return islessequal(__x, __y); } +S inline bool (islessgreater)(double __x, double __y) { return islessgreater(__x, __y); } +S inline bool (isnan)(double __x) { return isnan(__x); } +S inline bool (isnormal)(double __x) { return isnormal(__x); } +S inline bool (isunordered)(double __x, double __y) { return isunordered(__x, __y); } +S +S } +N#endif +N +N#if defined(__cplusplus) && !defined(__ARMCOMPILER_LIBCXX) +X#if 0L && !0L +S extern "C++" { +S inline float abs(float __x) { return fabsf(__x); } +S inline float acos(float __x) { return acosf(__x); } +S inline float asin(float __x) { return asinf(__x); } +S inline float atan(float __x) { return atanf(__x); } +S inline float atan2(float __y, float __x) { return atan2f(__y,__x); } +S inline float ceil(float __x) { return ceilf(__x); } +S inline float cos(float __x) { return cosf(__x); } +S inline float cosh(float __x) { return coshf(__x); } +S inline float exp(float __x) { return expf(__x); } +S inline float fabs(float __x) { return fabsf(__x); } +S inline float floor(float __x) { return floorf(__x); } +S inline float fmod(float __x, float __y) { return fmodf(__x, __y); } +S float frexp(float __x, int* __exp) __attribute__((__nonnull__(2))); +S inline float frexp(float __x, int* __exp) { return frexpf(__x, __exp); } +S inline float ldexp(float __x, int __exp) { return ldexpf(__x, __exp);} +S inline float log(float __x) { return logf(__x); } +S inline float log10(float __x) { return log10f(__x); } +S float modf(float __x, float* __iptr) __attribute__((__nonnull__(2))); +S inline float modf(float __x, float* __iptr) { return modff(__x, __iptr); } +S inline float pow(float __x, float __y) { return powf(__x,__y); } +S inline float pow(float __x, int __y) { return powf(__x, (float)__y); } +S inline float sin(float __x) { return sinf(__x); } +S inline float sinh(float __x) { return sinhf(__x); } +S inline float sqrt(float __x) { return sqrtf(__x); } +S inline float _sqrt(float __x) { return _sqrtf(__x); } +S inline float tan(float __x) { return tanf(__x); } +S inline float tanh(float __x) { return tanhf(__x); } +S +S inline double abs(double __x) { return fabs(__x); } +S inline double pow(double __x, int __y) +S { return pow(__x, (double) __y); } +S +S#ifdef __HAVE_LONGDOUBLE +S inline long double abs(long double __x) +S { return (long double)fabsl(__x); } +S inline long double acos(long double __x) +S { return (long double)acosl(__x); } +S inline long double asin(long double __x) +S { return (long double)asinl(__x); } +S inline long double atan(long double __x) +S { return (long double)atanl(__x); } +S inline long double atan2(long double __y, long double __x) +S { return (long double)atan2l(__y, __x); } +S inline long double ceil(long double __x) +S { return (long double)ceill( __x); } +S inline long double cos(long double __x) +S { return (long double)cosl(__x); } +S inline long double cosh(long double __x) +S { return (long double)coshl(__x); } +S inline long double exp(long double __x) +S { return (long double)expl(__x); } +S inline long double fabs(long double __x) +S { return (long double)fabsl(__x); } +S inline long double floor(long double __x) +S { return (long double)floorl(__x); } +S inline long double fmod(long double __x, long double __y) +S { return (long double)fmodl(__x, __y); } +S long double frexp(long double __x, int* __p) __attribute__((__nonnull__(2))); +S inline long double frexp(long double __x, int* __p) +S { return (long double)frexpl(__x, __p); } +S inline long double ldexp(long double __x, int __exp) +S { return (long double)ldexpl(__x, __exp); } +S inline long double log(long double __x) +S { return (long double)logl(__x); } +S inline long double log10(long double __x) +S { return (long double)log10l(__x); } +S long double modf(long double __x, long double* __p) __attribute__((__nonnull__(2))); +S inline long double modf(long double __x, long double* __p) +S { return (long double)modfl(__x, __p); } +S inline long double pow(long double __x, long double __y) +S { return (long double)powl(__x, __y); } +S inline long double pow(long double __x, int __y) +S { return (long double)powl(__x, __y); } +S inline long double sin(long double __x) +S { return (long double)sinl(__x); } +S inline long double sinh(long double __x) +S { return (long double)sinhl(__x); } +S inline long double sqrt(long double __x) +S { return (long double)sqrtl(__x); } +S inline long double _sqrt(long double __x) +S { return (long double)_sqrt((double) __x); } +S inline long double tan(long double __x) +S { return (long double)tanl(__x); } +S inline long double tanh(long double __x) +S { return (long double)tanhl(__x); } +S#endif +S +S#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +S inline float acosh(float __x) { return acoshf(__x); } +S inline float asinh(float __x) { return asinhf(__x); } +S inline float atanh(float __x) { return atanhf(__x); } +S inline float cbrt(float __x) { return cbrtf(__x); } +S inline float erf(float __x) { return erff(__x); } +S inline float erfc(float __x) { return erfcf(__x); } +S inline float expm1(float __x) { return expm1f(__x); } +S inline float log1p(float __x) { return log1pf(__x); } +S inline float hypot(float __x, float __y) { return hypotf(__x, __y); } +S inline float lgamma(float __x) { return lgammaf(__x); } +S inline float remainder(float __x, float __y) { return remainderf(__x, __y); } +S inline float rint(float __x) { return rintf(__x); } +S#endif +S +S#ifdef __USE_C99_MATH +S inline float exp2(float __x) { return exp2f(__x); } +S inline float fdim(float __x, float __y) { return fdimf(__x, __y); } +S inline float fma(float __x, float __y, float __z) { return fmaf(__x, __y, __z); } +S inline float fmax(float __x, float __y) { return fmaxf(__x, __y); } +S inline float fmin(float __x, float __y) { return fminf(__x, __y); } +S inline float log2(float __x) { return log2f(__x); } +S inline _ARMABI long lrint(float __x) { return lrintf(__x); } +S inline _ARMABI __LONGLONG llrint(float __x) { return llrintf(__x); } +S inline _ARMABI long lround(float __x) { return lroundf(__x); } +S inline _ARMABI __LONGLONG llround(float __x) { return llroundf(__x); } +S inline _ARMABI_FPEXCEPT float nearbyint(float __x) { return nearbyintf(__x); } +S inline float remquo(float __x, float __y, int *__q) { return remquof(__x, __y, __q); } +S inline _ARMABI_FPEXCEPT float round(float __x) { return roundf(__x); } +S inline float tgamma(float __x) { return tgammaf(__x); } +S inline _ARMABI_FPEXCEPT float trunc(float __x) { return truncf(__x); } +S +S inline int (fpclassify)(float __x) { return fpclassify(__x); } +S inline bool (isfinite)(float __x) { return isfinite(__x); } +S inline bool (isgreater)(float __x, float __y) { return isgreater(__x, __y); } +S inline bool (isgreaterequal)(float __x, float __y) { return isgreaterequal(__x, __y); } +S inline bool (isinf)(float __x) { return isinf(__x); } +S inline bool (isless)(float __x, float __y) { return isless(__x, __y); } +S inline bool (islessequal)(float __x, float __y) { return islessequal(__x, __y); } +S inline bool (islessgreater)(float __x, float __y) { return islessgreater(__x, __y); } +S inline bool (isnan)(float __x) { return isnan(__x); } +S inline bool (isnormal)(float __x) { return isnormal(__x); } +S inline bool (isunordered)(float __x, float __y) { return isunordered(__x, __y); } +S +S#ifdef __HAVE_LONGDOUBLE +S inline long double acosh(long double __x) { return acoshl(__x); } +S inline long double asinh(long double __x) { return asinhl(__x); } +S inline long double atanh(long double __x) { return atanhl(__x); } +S inline long double cbrt(long double __x) { return cbrtl(__x); } +S inline long double erf(long double __x) { return erfl(__x); } +S inline long double erfc(long double __x) { return erfcl(__x); } +S inline long double expm1(long double __x) { return expm1l(__x); } +S inline long double log1p(long double __x) { return log1pl(__x); } +S inline long double hypot(long double __x, long double __y) { return hypotl(__x, __y); } +S inline long double lgamma(long double __x) { return lgammal(__x); } +S inline long double remainder(long double __x, long double __y) { return remainderl(__x, __y); } +S inline long double rint(long double __x) { return rintl(__x); } +S inline long double exp2(long double __x) { return exp2l(__x); } +S inline long double fdim(long double __x, long double __y) { return fdiml(__x, __y); } +S inline long double fma(long double __x, long double __y, long double __z) { return fmal(__x, __y, __z); } +S inline long double fmax(long double __x, long double __y) { return fmaxl(__x, __y); } +S inline long double fmin(long double __x, long double __y) { return fminl(__x, __y); } +S inline long double log2(long double __x) { return log2l(__x); } +S inline _ARMABI long lrint(long double __x) { return lrintl(__x); } +S inline _ARMABI __LONGLONG llrint(long double __x) { return llrintl(__x); } +S inline _ARMABI long lround(long double __x) { return lroundl(__x); } +S inline _ARMABI __LONGLONG llround(long double __x) { return llroundl(__x); } +S inline _ARMABI_FPEXCEPT long double nearbyint(long double __x) { return nearbyintl(__x); } +S inline long double remquo(long double __x, long double __y, int *__q) { return remquol(__x, __y, __q); } +S inline _ARMABI_FPEXCEPT long double round(long double __x) { return roundl(__x); } +S inline long double tgamma(long double __x) { return tgammal(__x); } +S inline _ARMABI_FPEXCEPT long double trunc(long double __x) { return truncl(__x); } +S inline int (fpclassify)(long double __x) { return fpclassify(__x); } +S inline bool (isfinite)(long double __x) { return isfinite(__x); } +S inline bool (isgreater)(long double __x, long double __y) { return isgreater(__x, __y); } +S inline bool (isgreaterequal)(long double __x, long double __y) { return isgreaterequal(__x, __y); } +S inline bool (isinf)(long double __x) { return isinf(__x); } +S inline bool (isless)(long double __x, long double __y) { return isless(__x, __y); } +S inline bool (islessequal)(long double __x, long double __y) { return islessequal(__x, __y); } +S inline bool (islessgreater)(long double __x, long double __y) { return islessgreater(__x, __y); } +S inline bool (isnan)(long double __x) { return isnan(__x); } +S inline bool (isnormal)(long double __x) { return isnormal(__x); } +S inline bool (isunordered)(long double __x, long double __y) { return isunordered(__x, __y); } +S#endif +S +S#undef fpclassify +S#undef isfinite +S#undef isgreater +S#undef isgreaterequal +S#undef isinf +S#undef isless +S#undef islessequal +S#undef islessgreater +S#undef isnan +S#undef isnormal +S#undef isunordered +S +S#endif +S +S } +N#endif +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif +N #endif /* __MATH_DECLS */ +N +N #if _AEABI_PORTABILITY_LEVEL != 0 && !defined _AEABI_PORTABLE +X #if _AEABI_PORTABILITY_LEVEL != 0 && !0L +S #define _AEABI_PORTABLE +N #endif +N +N #if defined(__cplusplus) && !defined(__MATH_NO_EXPORTS) +X #if 0L && !0L +S using ::std::__use_accurate_range_reduction; +S #ifndef __ARMCOMPILER_LIBCXX +S using ::std::abs; +S #endif +S using ::std::acos; +S using ::std::asin; +S using ::std::atan2; +S using ::std::atan; +S using ::std::ceil; +S using ::std::cos; +S using ::std::cosh; +S using ::std::exp; +S using ::std::fabs; +S using ::std::floor; +S using ::std::fmod; +S using ::std::frexp; +S using ::std::ldexp; +S using ::std::log10; +S using ::std::log; +S using ::std::modf; +S using ::std::pow; +S using ::std::sin; +S using ::std::sinh; +S using ::std::sqrt; +S using ::std::_sqrt; +S using ::std::_sqrtf; +S using ::std::tan; +S using ::std::tanh; +S using ::std::_fabsf; +S /* C99 float and long double versions in already-C89-reserved namespace */ +S using ::std::acosf; +S using ::std::acosl; +S using ::std::asinf; +S using ::std::asinl; +S using ::std::atan2f; +S using ::std::atan2l; +S using ::std::atanf; +S using ::std::atanl; +S using ::std::ceilf; +S using ::std::ceill; +S using ::std::cosf; +S using ::std::coshf; +S using ::std::coshl; +S using ::std::cosl; +S using ::std::expf; +S using ::std::expl; +S using ::std::fabsf; +S using ::std::fabsl; +S using ::std::floorf; +S using ::std::floorl; +S using ::std::fmodf; +S using ::std::fmodl; +S using ::std::frexpf; +S using ::std::frexpl; +S using ::std::ldexpf; +S using ::std::ldexpl; +S using ::std::log10f; +S using ::std::log10l; +S using ::std::logf; +S using ::std::logl; +S using ::std::modff; +S using ::std::modfl; +S using ::std::powf; +S using ::std::powl; +S using ::std::sinf; +S using ::std::sinhf; +S using ::std::sinhl; +S using ::std::sinl; +S using ::std::sqrtf; +S using ::std::sqrtl; +S using ::std::tanf; +S using ::std::tanhf; +S using ::std::tanhl; +S using ::std::tanl; +S #if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +S /* C99 additions which for historical reasons appear in non-strict mode */ +S using ::std::acosh; +S using ::std::asinh; +S using ::std::atanh; +S using ::std::cbrt; +S using ::std::copysign; +S using ::std::copysignf; +S using ::std::erf; +S using ::std::erfc; +S using ::std::expm1; +S using ::std::hypot; +S using ::std::ilogb; +S using ::std::ilogbf; +S using ::std::ilogbl; +S using ::std::lgamma; +S using ::std::log1p; +S using ::std::logb; +S using ::std::logbf; +S using ::std::logbl; +S using ::std::nextafter; +S using ::std::nextafterf; +S using ::std::nextafterl; +S using ::std::nexttoward; +S using ::std::nexttowardf; +S using ::std::nexttowardl; +S using ::std::remainder; +S using ::std::rint; +S using ::std::scalbln; +S using ::std::scalblnf; +S using ::std::scalblnl; +S using ::std::scalbn; +S using ::std::scalbnf; +S using ::std::scalbnl; +S using ::std::math_errhandling; +S using ::std::acoshf; +S using ::std::acoshl; +S using ::std::asinhf; +S using ::std::asinhl; +S using ::std::atanhf; +S using ::std::atanhl; +S using ::std::copysignl; +S using ::std::cbrtf; +S using ::std::cbrtl; +S using ::std::erff; +S using ::std::erfl; +S using ::std::erfcf; +S using ::std::erfcl; +S using ::std::expm1f; +S using ::std::expm1l; +S using ::std::log1pf; +S using ::std::log1pl; +S using ::std::hypotf; +S using ::std::hypotl; +S using ::std::lgammaf; +S using ::std::lgammal; +S using ::std::remainderf; +S using ::std::remainderl; +S using ::std::rintf; +S using ::std::rintl; +S /* New in C99. */ +S using ::std::float_t; +S using ::std::double_t; +S #endif +S #if (defined(__clang__) && !defined(__STRICT_ANSI)) || defined(__USE_C99_MATH) +S /* Functions new in C99. */ +S using ::std::exp2; +S using ::std::exp2f; +S using ::std::exp2l; +S using ::std::fdim; +S using ::std::fdimf; +S using ::std::fdiml; +S using ::std::fma; +S using ::std::fmaf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::fmal; +S#endif +S using ::std::fmax; +S using ::std::fmaxf; +S using ::std::fmaxl; +S using ::std::fmin; +S using ::std::fminf; +S using ::std::fminl; +S using ::std::log2; +S using ::std::log2f; +S using ::std::log2l; +S using ::std::lrint; +S using ::std::lrintf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::lrintl; +S#endif +S using ::std::llrint; +S using ::std::llrintf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::llrintl; +S#endif +S using ::std::lround; +S using ::std::lroundf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::lroundl; +S#endif +S using ::std::llround; +S using ::std::llroundf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::llroundl; +S#endif +S using ::std::nan; +S using ::std::nanf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::nanl; +S#endif +S using ::std::nearbyint; +S using ::std::nearbyintf; +S using ::std::nearbyintl; +S using ::std::remquo; +S using ::std::remquof; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::remquol; +S#endif +S using ::std::round; +S using ::std::roundf; +S using ::std::roundl; +S using ::std::tgamma; +S using ::std::tgammaf; +S using ::std::tgammal; +S using ::std::trunc; +S using ::std::truncf; +S using ::std::truncl; +S #endif +S +S #if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +S using ::std::fpclassify; +S using ::std::isfinite; +S using ::std::isgreater; +S using ::std::isgreaterequal; +S using ::std::isinf; +S using ::std::isless; +S using ::std::islessequal; +S using ::std::islessgreater; +S using ::std::isnan; +S using ::std::isnormal; +S using ::std::isunordered; +S #endif +N #endif +N +N#undef __LONGLONG +N +N#endif /* __math_h */ +N +N/* end of math.h */ +L 19 "..\..\src\common\tau_common.h" 2 +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N/** +N * \name 通用常量定义 +N * @{ +N */ +N//#define ENABLE 1 +N//#define DISABLE 0 +N +N#define ON 1 +N#define OFF 0 +N +N#define NONE 0 +N#define EOS '\0' +N +N/* +N#ifndef TRUE +N#define TRUE 1 +N#endif +N +N#ifndef FALSE +N#define FALSE 0 +N#endif +N*/ +N +N#ifndef __cplusplus +N#define true 1 +N#define false 0 +N#define bool _Bool +N#endif /* ifndef __cplusplus */ +N +N#ifndef NULL +N#define NULL ((void *)0) +N#endif +N +N#define TAU_LITTLE_ENDIAN 1234 /**< \brief 小端模式 */ +N#define TAU_BIG_ENDIAN 3412 /**< \brief 大端模式 */ +N +N/** @} */ +N +N/******************************************************************************/ +N +N/** +N * \name 常用宏定义 +N * @{ +N */ +N +N#ifdef __cplusplus +S#define __I volatile /*!< Defines 'read only' permissions */ +N#else +N#define __I volatile const /*!< Defines 'read only' permissions */ +N#endif +N#define __O volatile /*!< Defines 'write only' permissions */ +N#define __IO volatile /*!< Defines 'read / write' permissions */ +N +N#define TAU_INLINE inline +N#define TAU_STATIC_INLINE static inline +N#define TAU_STATIC static +N#define TAU_CONST const +N#define TAU_EXTERN extern +N +N#define MIN(x, y) (((x) < (y)) ? (x) : (y)) +N#define MAX(x, y) (((x) > (y)) ? (x) : (y)) +N +N/** +N * \brief 求结构体成员的偏移 +N * \attention 不同平台上，由于成员大小和内存对齐等原因， +N * 同一结构体成员的偏移可能是不一样的 +N * +N * \par 示例 +N * \code +N * struct my_struct { +N * int m1; +N * char m2; +N * }; +N * int offset_m2; +N * +N * offset_m2 = TAU_OFFSET(struct my_struct, m2); +N * \endcode +N */ +N#define TAU_OFFSET(structure, member) ((uint32_t)(&(((structure *)0)->member))) +N +N/** @} */ +N +N/** +N * \brief 通过结构体成员指针获取包含该结构体成员的结构体 +N * +N * \param ptr 指向结构体成员的指针 +N * \param type 结构体类型 +N * \param member 结构体中该成员的名称 +N * +N * \par 示例 +N * \code +N * struct my_struct = { +N * int m1; +N * char m2; +N * }; +N * struct my_struct my_st; +N * char *p_m2 = &my_st.m2; +N * struct my_struct *p_st = TAU_CONTAINER_OF(p_m2, struct my_struct, m2); +N * \endcode +N */ +N#define TAU_CONTAINER_OF(ptr, type, member) \ +N ((type *)((char *)(ptr)-TAU_OFFSET(type, member))) +X#define TAU_CONTAINER_OF(ptr, type, member) ((type *)((char *)(ptr)-TAU_OFFSET(type, member))) +N +N/** +N * \brief 计算结构体成员的大小 +N * +N * \code +N * struct a = { +N * uint32_t m1; +N * uint32_t m2; +N * }; +N * int size_m2; +N * +N * size_m2 = TAU_MEMBER_SIZE(a, m2); //size_m2 = 4 +N * \endcode +N */ +N#define TAU_MEMBER_SIZE(structure, member) (sizeof(((structure *)0)->member)) +N +N/** +N * \brief 计算数组元素个数 +N * +N * \code +N * int a[] = {0, 1, 2, 3}; +N * int element_a = TAU_NELEMENTS(a); // element_a = 4 +N * \endcode +N */ +N#define TAU_NELEMENTS(array) (sizeof(array) / sizeof((array)[0])) +N +N/** +N * \brief 向上舍入 +N * +N * \param x 被运算的数 +N * \param align 对齐因素 +N * +N * \code +N * int size = TAU_ROUND_UP(15, 4); // size = 16 +N * \endcode +N */ +N#define TAU_ROUND_UP(x, align) (((int)(x)/(align))*(align) + (((int)(x)%(align)) ? (align) : 0)) +N +N/** +N * \brief 向下舍入 +N * +N * \param x 被运算的数 +N * \param align 对齐因素 +N * +N * \code +N * int size = TAU_ROUND_DOWN(15, 4); // size = 12 +N * \endcode +N */ +N#define TAU_ROUND_DOWN(x, align) (((int)(x)/(align))*(align)) +N +N/** \brief 倍数向上舍入 */ +N#define TAU_DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d)) +N +N/** +N * \brief 测试是否对齐 +N * +N * \param x 被运算的数 +N * \param align 对齐因素，必须为2的乘方 +N * +N * \code +N * if (TAU_ALIGNED(x, 4) { +N * ; // x对齐 +N * } else { +N * ; // x不对齐 +N * } +N * \endcode +N */ +N#define TAU_ALIGNED(x, align) (((int)(x) & (align - 1)) == 0) +N +N/** \brief 将1字节BCD数据转换为16进制数据 */ +N#define TAU_BCD_TO_HEX(val) (((val)&0x0f) + ((val) >> 4) * 10) +N +N/** \brief 将1字节16进制数据转换为BCD数据 */ +N#define TAU_HEX_TO_BCD(val) ((((val) / 10) << 4) + (val) % 10) +N +N/** +N * \brief 向上取整 +N */ +N#define TAU_CEIL(val) ceil(val) +N +N +N/*! @brief Construct the version number for drivers. */ +N#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +N +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/*!< @brief 用于返回状态和错误 */ +Ntypedef uint32_t status_t; +N +N/* \brief 通用回调函数指针定义 */ +Ntypedef void (*fcb_type)(void *data); +N +Ntypedef void (*uart_trans_cb)(status_t status, void *user_data); +N +Ntypedef void (*flash_trans_cb)(status_t status, void *user_data); +N#endif /* __TAU_COMMON_H */ +L 16 "..\..\src\sdk\include\hal_system.h" 2 +N#include "hal_gpio.h" +L 1 "..\..\src\sdk\include\hal_gpio.h" 1 +N/******************************************************************************* +N* +N* +N* File: hal_gpio.h +N* Description： gpio HAL层头文件 +N* Version： V0.1 +N* Date： 2023-07-27 +N* Author： kevin +N *******************************************************************************/ +N#ifndef __HAL_GPIO_H__ +N#define __HAL_GPIO_H__ +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_device_datatype.h" +L 1 "..\..\src\common\tau_device_datatype.h" 1 +N/******************************************************************************* +N * +N * +N * File: tau_device_datatype.h +N * Description device datatype +N * Version V0.1 +N * Date 2020-12-04 +N * Author kevin +N *******************************************************************************/ +N +N#ifndef _TAU_DEVICE_DATATYPE_H_ +N#define _TAU_DEVICE_DATATYPE_H_ +N +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N +N#include "stdint.h" +N#include "tau_common.h" +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/*! @brief 计算组状态码 */ +N#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/*! @brief 分组状态值 */ +Nenum _status_groups +N{ +N STATUS_GROUP_GENERIC = 0, +N STATUS_GROUP_I2C = 1, +N STATUS_GROUP_UART = 2, +N STATUS_GROUP_SPI = 3, +N STATUS_GROUP_TIMER = 4, +N}; +N +N/*! @brief 常用状态码 */ +Nenum _generic_status +N{ +N STATUS_SUCCESS = MAKE_STATUS(STATUS_GROUP_GENERIC, 0), +X STATUS_SUCCESS = ((((STATUS_GROUP_GENERIC)*100) + (0))), +N STATUS_FAIL = MAKE_STATUS(STATUS_GROUP_GENERIC, 1), +X STATUS_FAIL = ((((STATUS_GROUP_GENERIC)*100) + (1))), +N STATUS_READ_ONLY = MAKE_STATUS(STATUS_GROUP_GENERIC, 2), +X STATUS_READ_ONLY = ((((STATUS_GROUP_GENERIC)*100) + (2))), +N STATUS_OUT_OF_RANGE = MAKE_STATUS(STATUS_GROUP_GENERIC, 3), +X STATUS_OUT_OF_RANGE = ((((STATUS_GROUP_GENERIC)*100) + (3))), +N STATUS_INVALID_ARGUMENT = MAKE_STATUS(STATUS_GROUP_GENERIC, 4), +X STATUS_INVALID_ARGUMENT = ((((STATUS_GROUP_GENERIC)*100) + (4))), +N STATUS_TIME_OUT = MAKE_STATUS(STATUS_GROUP_GENERIC, 5), +X STATUS_TIME_OUT = ((((STATUS_GROUP_GENERIC)*100) + (5))), +N STATUS_NO_TRANSFER_IN_PROGRESS = MAKE_STATUS(STATUS_GROUP_GENERIC, 6), +X STATUS_NO_TRANSFER_IN_PROGRESS = ((((STATUS_GROUP_GENERIC)*100) + (6))), +N}; +N +N/** +N* @brief UART状态枚举定义 +N* +N*/ +Ntypedef enum +N{ +N STATUS_UART_TX_BUSY = MAKE_STATUS(STATUS_GROUP_UART, 0), /*!< Transmitter is busy. */ +X STATUS_UART_TX_BUSY = ((((STATUS_GROUP_UART)*100) + (0))), +N STATUS_UART_RX_BUSY = MAKE_STATUS(STATUS_GROUP_UART, 1), /*!< Receiver is busy. */ +X STATUS_UART_RX_BUSY = ((((STATUS_GROUP_UART)*100) + (1))), +N STATUS_UART_TX_IDLE = MAKE_STATUS(STATUS_GROUP_UART, 2), /*!< USART transmitter is idle. */ +X STATUS_UART_TX_IDLE = ((((STATUS_GROUP_UART)*100) + (2))), +N STATUS_UART_RX_IDLE = MAKE_STATUS(STATUS_GROUP_UART, 3), /*!< USART receiver is idle. */ +X STATUS_UART_RX_IDLE = ((((STATUS_GROUP_UART)*100) + (3))), +N STATUS_UART_TX_ERR = MAKE_STATUS(STATUS_GROUP_UART, 7), /*!< Error happens on txFIFO. */ +X STATUS_UART_TX_ERR = ((((STATUS_GROUP_UART)*100) + (7))), +N STATUS_UART_RX_ERR = MAKE_STATUS(STATUS_GROUP_UART, 9), /*!< Error happens on rxFIFO. */ +X STATUS_UART_RX_ERR = ((((STATUS_GROUP_UART)*100) + (9))), +N STATUS_UART_RX_RING_BUFF_OVERRUN = MAKE_STATUS(STATUS_GROUP_UART, 8), /*!< Error happens on rx ring buffer */ +X STATUS_UART_RX_RING_BUFF_OVERRUN = ((((STATUS_GROUP_UART)*100) + (8))), +N STATUS_UART_NOISE_ERR = MAKE_STATUS(STATUS_GROUP_UART, 10), /*!< USART noise error. */ +X STATUS_UART_NOISE_ERR = ((((STATUS_GROUP_UART)*100) + (10))), +N STATUS_UART_FRAMING_ERR = MAKE_STATUS(STATUS_GROUP_UART, 11), /*!< USART framing error. */ +X STATUS_UART_FRAMING_ERR = ((((STATUS_GROUP_UART)*100) + (11))), +N STATUS_UART_PARITY_ERR = MAKE_STATUS(STATUS_GROUP_UART, 12), /*!< USART parity error. */ +X STATUS_UART_PARITY_ERR = ((((STATUS_GROUP_UART)*100) + (12))), +N STATUS_UART_BAUDRATE_NOT_SPT = MAKE_STATUS(STATUS_GROUP_UART, 13), /*!< Baudrate is not support in current clock source */ +X STATUS_UART_BAUDRATE_NOT_SPT = ((((STATUS_GROUP_UART)*100) + (13))), +N} uart_status_e; +N +N/*! +N * @brief timer状态 +N */ +Ntypedef enum +N{ +N STATUS_TIMER_IDLE = MAKE_STATUS(STATUS_GROUP_TIMER, 0), /*!< 空闲 */ +X STATUS_TIMER_IDLE = ((((STATUS_GROUP_TIMER)*100) + (0))), +N STATUS_TIMER_RUNNING = MAKE_STATUS(STATUS_GROUP_TIMER, 1), /*!< 运行中 */ +X STATUS_TIMER_RUNNING = ((((STATUS_GROUP_TIMER)*100) + (1))), +N STATUS_TIMER_TIMEOUT = MAKE_STATUS(STATUS_GROUP_TIMER, 2), /*!< 超时 */ +X STATUS_TIMER_TIMEOUT = ((((STATUS_GROUP_TIMER)*100) + (2))), +N} timer_status_e; +N +N/*! +N * @brief system触发事件(中断/复位)模式 +N */ +Ntypedef enum +N{ +N DETECT_HIGH_LVL = 0, +N DETECT_LOW_LVL, +N DETECT_RISING_EDGE, +N DETECT_FALLING_EDGE, +N DETECT_DOUBLE_EDGE +N} sys_cfg_trigger_e; +N +N/** +N* @brief GPIO interrupt type +N*/ +Ntypedef enum +N{ +N TIMER_NUM0 = 0, +N TIMER_NUM1, +N TIMER_NUM2, +N TIMER_NUM3, +N TIMER_NUM_MAX +N} timer_num_e; +N +N/** +N* @brief GPIO interrupt type +N*/ +Ntypedef enum +N{ +N GPIO_INT_EXTI_INT0 = 0, +N GPIO_INT_EXTI_INT1, +N GPIO_INT_EXTI_INT2, +N GPIO_INT_EXTI_INT3, +N GPIO_INT_EXTI_INT4, +N GPIO_INT_EXTI_INT5, +N GPIO_INT_EXTI_INT6, +N GPIO_INT_EXTI_INT7, +N GPIO_INT_MAX +N} gpio_int_e; +N +N/*! @brief PWMI中断类型 */ +Ntypedef enum _pwm_int_type +N{ +N PWM_INT_HIGH_OVERFLOW = 0, +N PWM_INT_LOW_OVERFLOW, +N PWM_INT_TOTAL_OVERFLOW, +N PWM_INT_HIGH_DONE, +N PWM_INT_LOW_DONE, +N PWM_INT_TOTAL_DONE, +N PWM_INT_MAX +N} pwm_int_type_e; +N +N/** +N* @brief I2C chose +N*/ +Ntypedef enum +N{ +N I2C_SELECT_0 = 0, //常用slave +N I2C_SELECT_1, //常用master +N} i2c_select_e; +N +N/*! +N * @brief 传输速度 +N * @note +N */ +Ntypedef enum _i2c_rate +N{ +N I2C_RATE_STANDARD = 1, //100kHz +N I2C_RATE_FAST, //400kHz +N I2C_RATE_HIGH, //1MHz +N} i2c_rate_e; +N +N/*! +N * @brief I2C Index +N * @note +N */ +Ntypedef enum +N{ +N I2C_INDEX_0, +N I2C_INDEX_1, +N I2C_INDEX_2, +N I2C_INDEX_MAX +N} i2c_index_e; +N +N/*! +N * @brief DMA channel type +N * @note +N */ +Ntypedef enum +N{ +N AHB_DMA_CH0, +N AHB_DMA_CH1, +N AHB_DMA_CH2, +N AHB_DMA_CH3, +N AHB_DMA_CH4, +N AHB_DMA_CH5, +N AHB_DMA_CH6, +N AHB_DMA_CH7, +N AHB_DMA_CH_NUM +N} dma_channel_type_e; +N +N/*! @brief Type used for all status and error return values. */ +N +Ntypedef enum +N{ +N DISABLE = 0, +N ENABLE = !DISABLE +N} function_state_e; +N +N/** +N* @brief The reversal types of the bit order of the input/output data +N*/ +Ntypedef enum +N{ +N CRC_REV_NO_TRANSPOSE = 0, /*!< No transposition */ +N CRC_REV_ONLY_BITS_TRANSPOSE, /*!< Bits in bytes are transposed; bytes are not transposed */ +N CRC_REV_BOTH_TRANSPOSE, /*!< Both bits in bytes and bytes are transposed */ +N CRC_REV_ONLY_BYTES_TRANSPOSE, /*!< Only bytes are transposed; no bits in a byte are transposed */ +N} crc_reversal_type_e; +N +N/** +N* @brief Complement Read Of CRC Data Register +N*/ +Ntypedef enum +N{ +N CRC_FXOR_DISABLE = 0, /*!< No XOR on reading */ +N CRC_FXOR_ENABLE, /*!< Invert or complement the read value of the CRC Data register */ +N} crc_fxor_function_e; +N +N/** +N* @brief width of CRC protocol (polynomial) +N*/ +Ntypedef enum +N{ +N CRC_16_BIT_PROTOCOL = 0, /*!< 0: 16-bit CRC protocol */ +N CRC_32_BIT_PROTOCOL, /*!< 1: 32-bit CRC protocol */ +N} crc_protocol_type_e; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N#endif +N +L 17 "..\..\src\sdk\include\hal_gpio.h" 2 +N#include "tau_common.h" +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N/** +N* @brief GPIO pin +N*/ +Ntypedef enum +N{ +N /*以GPIO命名PIN*/ +N IO_PAD_GPIO0 = 0, +N IO_PAD_GPIO1, +N IO_PAD_GPIO2, +N IO_PAD_GPIO3, +N IO_PAD_GPIO4, +N IO_PAD_GPIO5, +N IO_PAD_GPIO6, +N IO_PAD_GPIO7, +N IO_PAD_GPIO8, +N IO_PAD_GPIO9, +N IO_PAD_GPIO10, +N IO_PAD_GPIO11, +N IO_PAD_GPIO12, +N IO_PAD_GPIO13, +N IO_PAD_GPIO14, +N IO_PAD_GPIO15, +N IO_PAD_GPIO16, +N IO_PAD_GPIO17, +N IO_PAD_GPIO18, +N IO_PAD_GPIO19, +N IO_PAD_GPIO20, +N IO_PAD_GPIO21, +N IO_PAD_GPIO22, +N IO_PAD_GPIO23, +N IO_PAD_GPIO24, +N IO_PAD_GPIO25, +N +N /*以实际PAD NAME命名PIN*/ +N IO_PAD_AP_SPIS_MISO = IO_PAD_GPIO0, +N IO_PAD_AP_SPIS_MOSI = IO_PAD_GPIO1, +N IO_PAD_AP_INT = IO_PAD_GPIO2, +N IO_PAD_AP_TE = IO_PAD_GPIO3, +N IO_PAD_AP_SWIRE = IO_PAD_GPIO4, +N IO_PAD_TD_SPIM_MISO = IO_PAD_GPIO5, +N IO_PAD_TD_SPIM_MOSI = IO_PAD_GPIO6, +N IO_PAD_TD_RSTN = IO_PAD_GPIO7, +N IO_PAD_AP_PWMEN = IO_PAD_GPIO8, +N IO_PAD_AP_SPIS_CLK = IO_PAD_GPIO9, +N IO_PAD_AP_SPIS_CSN = IO_PAD_GPIO10, +N IO_PAD_TD_FC_CLK = IO_PAD_GPIO11, +N IO_PAD_TD_FC_CSN = IO_PAD_GPIO12, +N IO_PAD_TD_FC_IO0 = IO_PAD_GPIO13, +N IO_PAD_TD_FC_IO1 = IO_PAD_GPIO14, +N IO_PAD_SWD_CLK = IO_PAD_GPIO15, +N IO_PAD_SWD_DIO = IO_PAD_GPIO16, +N IO_PAD_AP_RSTN = IO_PAD_GPIO17, +N IO_PAD_UART0_TX = IO_PAD_GPIO18, +N IO_PAD_TD_SPIM_CLK = IO_PAD_GPIO19, +N IO_PAD_TD_SPIM_CSN = IO_PAD_GPIO20, +N IO_PAD_AP_TPRSTN = IO_PAD_GPIO21, +N IO_PAD_TD_INT = IO_PAD_GPIO22, +N IO_PAD_TD_TP_RESX = IO_PAD_GPIO23, +N IO_PAD_UART1_TX = IO_PAD_GPIO24, +N IO_PAD_UART0_RX = IO_PAD_GPIO25, +N +N IO_PAD_MAX, +N +N +N /*以实际引脚序号命名PIN*/ +N IO_PIN_1 = IO_PAD_SWD_CLK, +N IO_PIN_2 = IO_PAD_UART0_TX, +N IO_PIN_3 = IO_PAD_SWD_DIO, +N IO_PIN_4 = IO_PAD_TD_SPIM_MOSI, +N IO_PIN_5 = IO_PAD_TD_SPIM_CLK, +N IO_PIN_6 = IO_PAD_TD_SPIM_CSN, +N IO_PIN_7 = IO_PAD_TD_SPIM_MISO, +N IO_PIN_8 = IO_PAD_TD_RSTN, +N IO_PIN_9 = IO_PAD_TD_FC_CSN, +N IO_PIN_10 = IO_PAD_TD_FC_CLK, +N IO_PIN_11 = IO_PAD_TD_FC_IO0, +N IO_PIN_12 = IO_PAD_TD_FC_IO1, +N IO_PIN_13 = IO_PAD_TD_TP_RESX, +N IO_PIN_14 = IO_PAD_UART1_TX, +N IO_PIN_15 = IO_PAD_AP_SWIRE, +N IO_PIN_16 = IO_PAD_AP_INT, +N IO_PIN_17 = IO_PAD_AP_PWMEN, +N IO_PIN_18 = IO_PAD_AP_TPRSTN, +N +N IO_PIN_29 = IO_PAD_AP_TE, +N IO_PIN_30 = IO_PAD_AP_SPIS_MISO, +N IO_PIN_31 = IO_PAD_AP_SPIS_CSN, +N IO_PIN_32 = IO_PAD_AP_SPIS_CLK, +N IO_PIN_33 = IO_PAD_AP_SPIS_MOSI, +N IO_PIN_34 = IO_PAD_AP_RSTN, +N IO_PIN_35 = IO_PAD_TD_INT, +N IO_PIN_36 = IO_PAD_UART0_RX, +N +N} io_pad_e; +N +N +N/* +N芯片引脚 | 默认mode | 可选mode +N---------------------------------------------------------------- +NIO_PIN_1 | IO_PAD_SWCLK, | PIN1_MODE_SWDCLK +N | | PIN1_MODE_GPIO15 +N---------------------------------------------------------------- +NIO_PIN_2 | IO_PAD_UART0_TX, | PIN2_MODE_UART0_TX +N | | PIN2_MODE_PWMO +N | | PIN2_MODE_GPIO18 +N | | PIN2_MODE_PWMI +N | | PIN2_MODE_TEAR1 +N---------------------------------------------------------------- +NIO_PIN_3 | IO_PAD_SWDIO, | PIN3_MODE_SWDIO +N | | PIN3_MODE_GPIO16 +N---------------------------------------------------------------- +NIO_PIN_4 | IO_PAD_TD_SPIM_MOSI, | PIN4_MODE_SPIM_MOSI +N | | PIN4_MODE_I2C02_SDA +N | | PIN4_MODE_GPIO6 +N | | PIN4_MODE_UART0_TX +N---------------------------------------------------------------- +NIO_PIN_5 | IO_PAD_TD_SPIM_CLK, | PIN5_MODE_SPIM_SCLK +N | | PIN5_MODE_I2C1_SCL +N | | PIN5_MODE_GPIO19 +N---------------------------------------------------------------- +NIO_PIN_6 | IO_PAD_TD_SPIM_CSN, | PIN6_MODE_SPIM_CSN +N | | PIN6_MODE_I2C1_SDA +N | | PIN6_MODE_GPIO20 +N---------------------------------------------------------------- +NIO_PIN_7 | IO_PAD_TD_SPIM_MISO, | PIN7_MODE_SPIM_MISO +N | | PIN7_MODE_I2C02_SCL +N | | PIN7_MODE_GPIO5 +N---------------------------------------------------------------- +NIO_PIN_8 | IO_PAD_TD_RSTN, | PIN8_MODE_GPIO7 +N | | PIN8_MODE_I2C02_SDA +N---------------------------------------------------------------- +NIO_PIN_9 | IO_PAD_TD_FC_CSN, | PIN9_MODE_TSPIS_CSN +N | | PIN9_MODE_GPIO12 +N---------------------------------------------------------------- +NIO_PIN_10 | IO_PAD_TD_FC_CLK, | PIN10_MODE_TSPIS_CLK +N | | PIN10_MODE_GPIO11 +N---------------------------------------------------------------- +NIO_PIN_11 | IO_PAD_TD_FC_IO0, | PIN11_MODE_TSPIS_IO0 +N | | PIN11_MODE_GPIO13 +N | | PIN11_MODE_I2C02_SDA +N---------------------------------------------------------------- +NIO_PIN_12 | IO_PAD_TD_FC_IO1, | PIN12_MODE_TSPIS_IO1 +N | | PIN12_MODE_GPIO14 +N | | PIN12_MODE_I2C02_SCL +N---------------------------------------------------------------- +NIO_PIN_13 | IO_PAD_TD_TP_RESX, | PIN13_MODE_GPIO23 +N | | PIN13_MODE_PWMO +N | | PIN13_MODE_UART1_RX +N | | PIN13_MODE_UART1_RX +N---------------------------------------------------------------- +NIO_PIN_14 | IO_PAD_UART1_TX, | PIN14_MODE_GPIO24 +N | | PIN14_MODE_UART0_RX +N | | PIN14_MODE_UART1_TX +N | | +N---------------------------------------------------------------- +NIO_PIN_15 | IO_PAD_AP_SWIRE, | PIN15_MODE_SWIRE +N | | PIN15_MODE_PWMO +N | | PIN15_MODE_GPIO4 +N---------------------------------------------------------------- +NIO_PIN_16 | IO_PAD_AP_INT, | PIN16_MODE_GPIO2 +N---------------------------------------------------------------- +NIO_PIN_17 | IO_PAD_AP_PWMEN, | PIN17_MODE_UART0_RX +N | | PIN17_MODE_GPIO8 +N | | PIN17_MODE_PWMO +N---------------------------------------------------------------- +NIO_PIN_18 | IO_PAD_AP_TPRSTN, | PIN18_MODE_UART0_RX +N | | PIN18_MODE_GPIO21 +N | | PIN18_MODE_I2C02_SCL +N---------------------------------------------------------------- +NIO_PIN_29 | IO_PAD_AP_TE, | PIN29_MODE_JTAG_TRSTN +N | | PIN29_MODE_TEAR +N | | PIN29_MODE_GPIO3 +N---------------------------------------------------------------- +NIO_PIN_30 | IO_PAD_AP_SPIS_MISO, | PIN30_MODE_JTAG_TDO +N | | PIN30_MODE_SPIS_MISO +N | | PIN30_MODE_GPIO0 +N | | PIN30_MODE_UART0_RX +N | | PIN30_MODE_I2C1_SCL +N---------------------------------------------------------------- +NIO_PIN_31 | IO_PAD_AP_SPIS_CSN, | PIN31_MODE_JTAG_TMS +N | | PIN31_MODE_SPIS_CSN +N | | PIN31_MODE_GPIO10 +N | | PIN31_MODE_I2C02_SDA +N---------------------------------------------------------------- +NIO_PIN_32 | IO_PAD_AP_SPIS_CLK, | PIN32_MODE_JTAG_TCK +N | | PIN32_MODE_SPIS_SCLK +N | | PIN32_MODE_GPIO9 +N | | PIN32_MODE_I2C02_SCL +N---------------------------------------------------------------- +NIO_PIN_33 | IO_PAD_AP_SPIS_MOSI, | PIN33_MODE_JTAG_TDI +N | | PIN33_MODE_SPIS_MOSI +N | | PIN33_MODE_GPIO1 +N | | PIN33_MODE_UART0_TX +N | | PIN33_MODE_I2C1_SDA_0 +N---------------------------------------------------------------- +NIO_PIN_34 | IO_PAD_AP_RSTN, | PIN34_MODE_GPIO17 +N---------------------------------------------------------------- +NIO_PIN_35 | IO_PAD_TD_INT, | PIN35_MODE_GPIO22 +N---------------------------------------------------------------- +NIO_PIN_36 | IO_PAD_UART0_RX, | PIN36_MODE_UART0_RX +N | | PIN36_MODE_PWMO +N | | PIN36_MODE_GPIO25 +N---------------------------------------------------------------- +N*/ +N +N +N/** +N* @brief PIN1 IO_PAD_SWD_CLK 可选的mode +N*/ +Ntypedef enum +N{ +N PIN1_MODE_SWDCLK = 0, +N PIN1_MODE_GPIO15 = 2, +N} pin1_mode_e; +N +N +N/** +N* @brief PIN2 PAD_UART0_TX可选的mode +N*/ +Ntypedef enum +N{ +N PIN2_MODE_UART0_TX = 0, +N PIN2_MODE_PWMO = 1, +N PIN2_MODE_GPIO18 = 2, +N PIN2_MODE_PWMI = 3, +N PIN2_MODE_TEAR1 = 4, +N} pin2_mode_e; +N +N/** +N* @brief PIN3 IO_PAD_SWD_DIO 可选的mode +N*/ +Ntypedef enum +N{ +N PIN3_MODE_SWDIO = 0, +N PIN3_MODE_GPIO16 = 2, +N} pin3_mode_e; +N +N +N/** +N* @brief PIN4 PAD_TD_SPIM_MOSI可选的mode +N*/ +Ntypedef enum +N{ +N PIN4_MODE_SPIM_MOSI = 0, +N PIN4_MODE_I2C02_SDA = 1, +N PIN4_MODE_GPIO6 = 2, +N PIN4_MODE_UART0_TX = 3, +N} pin4_mode_e; +N +N/** +N* @brief PIN5 PAD_TD_SPIM_CLK可选的mode +N*/ +Ntypedef enum +N{ +N PIN5_MODE_SPIM_SCLK = 0, +N PIN5_MODE_I2C1_SCL = 1, +N PIN5_MODE_GPIO19 = 2, +N} pin5_mode_e; +N +N/** +N* @brief PIN6 PAD_TD_SPIM_CSN可选的mode +N*/ +Ntypedef enum +N{ +N PIN6_MODE_SPIM_CSN = 0, +N PIN6_MODE_I2C1_SDA = 1, +N PIN6_MODE_GPIO20 = 2, +N} pin6_mode_e; +N +N/** +N* @brief PIN7 PAD_TD_SPIM_MISO可选的mode +N*/ +Ntypedef enum +N{ +N PIN7_MODE_SPIM_MISO = 0, +N PIN7_MODE_I2C02_SCL = 1, +N PIN7_MODE_GPIO5 = 2, +N} pin7_mode_e; +N +N/** +N* @brief PIN8 PAD_TD_RSTN可选的mode +N*/ +Ntypedef enum +N{ +N PIN8_MODE_GPIO7 = 2, +N PIN8_MODE_I2C02_SDA = 3, +N} pin8_mode_e; +N +N/** +N* @brief PIN9 PAD_TD_FC_CSN可选的mode +N*/ +Ntypedef enum +N{ +N PIN9_MODE_TSPIS_CSN = 0, +N PIN9_MODE_GPIO12 = 2, +N} pin9_mode_e; +N +N/** +N* @brief PIN10 PAD_TD_FC_CLK可选的mode +N*/ +Ntypedef enum +N{ +N PIN10_MODE_TSPIS_CLK = 0, +N PIN10_MODE_GPIO11 = 2, +N} pin10_mode_e; +N +N +N/** +N* @brief PIN11 PAD_TD_FC_IO0可选的mode +N*/ +Ntypedef enum +N{ +N PIN11_MODE_TSPIS_IO0 = 0, +N PIN11_MODE_GPIO13 = 2, +N PIN11_MODE_I2C02_SDA = 3, +N} pin11_mode_e; +N +N/** +N* @brief PIN12 PAD_TD_FC_IO1可选的mode +N*/ +Ntypedef enum +N{ +N PIN12_MODE_TSPIS_IO1 = 0, +N PIN12_MODE_GPIO14 = 2, +N PIN12_MODE_I2C02_SCL = 3, +N} pin12_mode_e; +N +N/** +N* @brief PIN13 PAD_TD_TP_RESX可选的mode +N*/ +Ntypedef enum +N{ +N PIN13_MODE_GPIO23 = 2, +N PIN13_MODE_PWMO = 3, +N PIN13_MODE_UART1_RX = 4, +N} pin13_mode_e; +N +N/** +N* @brief PIN14 PAD_UART1_TX可选的mode +N*/ +Ntypedef enum +N{ +N PIN14_MODE_GPIO24 = 2, +N PIN14_MODE_UART0_RX = 3, +N PIN14_MODE_UART1_TX = 4, +N} pin14_mode_e; +N +N +N +N/** +N* @brief PIN15 PAD_AP_SWIRE可选的mode +N*/ +Ntypedef enum +N{ +N PIN15_MODE_SWIRE = 0, +N PIN15_MODE_PWMO = 1, +N PIN15_MODE_GPIO4 = 2, +N} pin15_mode_e; +N +N/** +N* @brief PIN16 IO_PAD_AP_INT 可选的mode +N*/ +Ntypedef enum +N{ +N PIN16_MODE_GPIO2 = 2, +N} pin16_mode_e; +N +N/** +N* @brief PIN17 PAD_AP_PWMEN可选的mode +N*/ +Ntypedef enum +N{ +N PIN17_MODE_UART0_RX = 1, +N PIN17_MODE_GPIO8 = 2, +N PIN17_MODE_PWMO = 3, +N} pin17_mode_e; +N +N/** +N* @brief PIN18 IO_PAD_AP_TPRSTN 可选的mode +N*/ +Ntypedef enum +N{ +N PIN18_MODE_UART0_RX = 0, +N PIN18_MODE_GPIO21 = 2, +N PIN18_MODE_I2C02_SCL = 3, +N} pin18_mode_e; +N +N +N//---------- +N +N/** +N* @brief PIN29 IO_PAD_AP_TE 可选的mode +N*/ +Ntypedef enum +N{ +N PIN29_MODE_JTAG_TRSTN = 0, +N PIN29_MODE_TEAR = 1, +N PIN29_MODE_GPIO3 = 2, +N} pin29_mode_e; +N +N +N/** +N* @brief PIN30 IO_PAD_AP_SPIS_MISO 可选的mode +N*/ +Ntypedef enum +N{ +N PIN30_MODE_JTAG_TDO = 0, +N PIN30_MODE_SPIS_MISO = 1, +N PIN30_MODE_GPIO0 = 2, +N PIN30_MODE_UART0_RX = 3, +N PIN30_MODE_I2C1_SCL = 6, +N} pin30_mode_e; +N +N/** +N* @brief PIN31 IO_PAD_AP_SPIS_CSN 可选的mode +N*/ +Ntypedef enum +N{ +N PIN31_MODE_JTAG_TMS = 0, +N PIN31_MODE_SPIS_CSN = 1, +N PIN31_MODE_GPIO10 = 2, +N PIN31_MODE_I2C02_SDA = 3, +N} pin31_mode_e; +N +N/** +N* @brief PIN32 IO_PAD_AP_SPIS_CLK 可选的mode +N*/ +Ntypedef enum +N{ +N PIN32_MODE_JTAG_TCK = 0, +N PIN32_MODE_SPIS_SCLK = 1, +N PIN32_MODE_GPIO9 = 2, +N PIN32_MODE_I2C02_SCL = 3, +N} pin32_mode_e; +N +N/** +N* @brief PIN33 IO_PAD_AP_SPIS_MOSI 可选的mode +N*/ +Ntypedef enum +N{ +N PIN33_MODE_JTAG_TDI = 0, +N PIN33_MODE_SPIS_MOSI = 1, +N PIN33_MODE_GPIO1 = 2, +N PIN33_MODE_UART0_TX = 3, +N PIN33_MODE_I2C1_SDA_0 = 6, +N} pin33_mode_e; +N +N/** +N* @brief PIN34 PAD_AP_RST可选的mode +N*/ +Ntypedef enum +N{ +N PIN34_MODE_GPIO17 = 2, +N} pin34_mode_e; +N +N +N/** +N* @brief PIN35 PAD_TD_INT可选的mode +N*/ +Ntypedef enum +N{ +N PIN35_MODE_GPIO22 = 2, +N} pin35_mode_e; +N +N +N/** +N* @brief PIN36 PAD_UART_RX可选的mode +N*/ +Ntypedef enum +N{ +N PIN36_MODE_UART0_RX = 0, +N PIN36_MODE_PWMO = 1, +N PIN36_MODE_GPIO25 = 2, +N} pin36_mode_e; +N +N +N +N//------------------------------------------------------------------------- +N/** +N* @brief PAD_SFC_CLK可选的mode 内部PAD +N*/ +Ntypedef enum +N{ +N IO_MODE_INTER_FC_CLK = 0, +N IO_MODE_TSPIS_CLK_EN = 2, +N} pad_sfc_clk_mode_e; +N +N/** +N* @brief PAD_SFC_CSN可选的mode 内部PAD +N*/ +Ntypedef enum +N{ +N IO_MODE_INTER_FC_CSN = 0, +N IO_MODE_TSPIS_CSN_EN = 2, +N} pad_sfc_csn_mode_e; +N +N/** +N* @brief PAD_SFC_IO0可选的mode 内部PAD +N*/ +Ntypedef enum +N{ +N IO_MODE_INTER_FC_IO0 = 0, +N IO_MODE_TSPIS_IO0_EN = 2, +N} pad_sfc_io0_mode_e; +N +N/** +N* @brief PAD_SFC_IO1可选的mode 内部PAD +N*/ +Ntypedef enum +N{ +N IO_MODE_INTER_FC_IO1 = 0, +N IO_MODE_TSPIS_IO1_EN = 2, +N} pad_sfc_io1_mode_e; +N +N/** +N* @brief PAD电压转换速率 +N*/ +Ntypedef enum +N{ +N IO_SLEW_RATE_SLOW = 0, +N IO_SLEW_RATE_FAST = 1, +N} pad_slew_rate_e; +N +N/******************************************************************************* +N* IOE +N*******************************************************************************/ +N/** +N* @brief GPIO io方向 +N*/ +Ntypedef enum +N{ +N IO_IOE_INPUT = 0, +N IO_IOE_OUTPUT, +N IO_IOE_NONE +N} gpio_ioe_e; +N +N/** +N* @brief GPIO level +N*/ +Ntypedef enum +N{ +N IO_LVL_LOW = 0, +N IO_LVL_HIGH, +N IO_LVL_NONE +N} gpio_level_e; +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/** +N* @brief PAD与MODE的MAP结构体 +N*/ +Ntypedef struct +N{ +N io_pad_e pad; +N uint8_t mode; +N gpio_ioe_e ioe; +N gpio_level_e lvl; +N} io_pad_attr_t; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N/** +N* @brief 配置指定PAD为GPIO mode，方向为input，指定中断触发方式 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param trig：4种中断触发方式，参考枚举类型sys_cfg_trigger_e +N* @retval 无 +N*/ +Nvoid hal_gpio_init_eint(io_pad_e pad, sys_cfg_trigger_e trig); +N +N/** +N* @brief 注册GPIO中断回调函数 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param cb_func：回调函数地址 +N* @param data：回调函数参数地址 +N* @retval 无 +N*/ +Nvoid hal_gpio_reg_eint_cb(io_pad_e pad, fcb_type cb_func); +N +N/** +N* @brief 开关GPIO中断 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param state：开关控制 +N* @retval 无 +N*/ +Nvoid hal_gpio_ctrl_eint(io_pad_e pad, bool state); +Xvoid hal_gpio_ctrl_eint(io_pad_e pad, _Bool state); +N +N/** +N* @brief 获取GPIO中断类型 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @retval 无 +N*/ +Ngpio_int_e hal_gpio_get_int_type(io_pad_e pad); +N +N/** +N* @brief 配置指定PAD为GPIO mode，方向为output，指定初始电平 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param lvl：初始电平，参考枚举类型gpio_level_e +N* @retval 无 +N*/ +Nvoid hal_gpio_init_output(io_pad_e pad, gpio_level_e lvl); +N +N/** +N* @brief 封装设置输出接口 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param lvl：初始电平，参考枚举类型gpio_level_e +N* @retval 无 +N*/ +Nvoid hal_gpio_set_output_data(io_pad_e pad, gpio_level_e lvl); +N +N/** +N* @brief 配置指定PAD为GPIO mode，方向为input +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @retval 无 +N*/ +Nvoid hal_gpio_init_input(io_pad_e pad); +N +N/** +N* @brief 读取输入电平 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @retval 无 +N*/ +Ngpio_level_e hal_gpio_get_input_data(io_pad_e pad); +N +N/** +N* @brief 设置io mode +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param mode：工作模式，参考各PAD对应的mode枚举类型 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_mode(io_pad_e pad, uint8_t mode); +N +N/** +N* @brief 设置io 为高阻态 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @retval 无 +N*/ +Nvoid hal_gpio_set_high_impedance(io_pad_e pad); +N +N/** +N* @brief 获取指定PAD的默认上拉、下拉状态 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param up_enable：默认上拉状态 +N* @param down_enable：默认下拉状态 +N* @retval 无 +N*/ +Nvoid hal_gpio_get_pull_state(io_pad_e pad, bool *up_enable, bool *down_enable); +Xvoid hal_gpio_get_pull_state(io_pad_e pad, _Bool *up_enable, _Bool *down_enable); +N +N/** +N* @brief 配置指定PAD的默认上拉、下拉状态 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param up_enable：默认上拉状态 +N* @param down_enable：默认下拉状态 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_pull_state(io_pad_e pad, bool up_enable, bool down_enable); +Xvoid hal_gpio_set_pull_state(io_pad_e pad, _Bool up_enable, _Bool down_enable); +N +N/** +N* @brief 配置指定PAD是否为施密特触发 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param st_enable：1为施密特触发，0为正常触发 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_schmitt_trigger(io_pad_e pad, bool st_enable); +Xvoid hal_gpio_set_schmitt_trigger(io_pad_e pad, _Bool st_enable); +N +N/** +N* @brief 配置指定PAD的驱动能力 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param strength：驱动强度，取值为0~3 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_driving_strength(io_pad_e pad, uint8_t strength); +N +N/** +N* @brief 配置指定PAD的电压转换速率 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param rate：驱动强度，取值为0~3 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_slew_rate(io_pad_e pad, pad_slew_rate_e rate); +N +N/** +N* @brief 配置AP_RSTN引脚中断 +N* @param enable: 中断开关 +N* @param cb_func：回调函数 +N* @param trig：触发模式 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_ap_reset_int(bool enable, fcb_type cb_func, sys_cfg_trigger_e trig); +Xvoid hal_gpio_set_ap_reset_int(_Bool enable, fcb_type cb_func, sys_cfg_trigger_e trig); +N +N/** +N* @brief 批量设置IO参数 +N* @param attrs: PAD属性 +N* @param size: 数组成员个数 +N* @retval 无 +N*/ +Nvoid hal_gpio_config_pad(io_pad_attr_t *attrs, uint8_t size); +N +N#endif /* __HAL_GPIO_H__ */ +L 17 "..\..\src\sdk\include\hal_system.h" 2 +N#include "tau_log.h" +L 1 "..\..\src\common\tau_log.h" 1 +N/******************************************************************************* +N* +N* +N* File: tau_log.h +N* Description log file +N* Version V0.1 +N* Date 2020-12-08 +N* Author linyw +N*******************************************************************************/ +N#ifndef _TAU_LOG_H_ +N#define _TAU_LOG_H_ +N +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include +N#include +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h" 1 +N/* string.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.11 */ +N/* Copyright (C) Codemist Ltd., 1988-1993. */ +N/* Copyright 1991-1993 ARM Limited. All rights reserved. */ +N/* version 0.04 */ +N +N/* +N * RCS $Revision$ +N * Checkin $Date$ +N */ +N +N/* +N * string.h declares one type and several functions, and defines one macro +N * useful for manipulating character arrays and other objects treated as +N * character arrays. Various methods are used for determining the lengths of +N * the arrays, but in all cases a char * or void * argument points to the +N * initial (lowest addresses) character of the array. If an array is written +N * beyond the end of an object, the behaviour is undefined. +N */ +N +N#ifndef __string_h +N#define __string_h +N#define __ARMCLIB_VERSION 5060037 +N +N#define _ARMABI __declspec(__nothrow) +N +N #ifndef __STRING_DECLS +N #define __STRING_DECLS +N +N #undef __CLIBNS +N +N #ifdef __cplusplus +S namespace std { +S #define __CLIBNS std:: +S extern "C" { +N #else +N #define __CLIBNS +N #endif /* __cplusplus */ +N +N#if defined(__cplusplus) || !defined(__STRICT_ANSI__) +X#if 0L || !0L +N /* unconditional in C++ and non-strict C for consistency of debug info */ +N #if __sizeof_ptr == 8 +X #if 4 == 8 +S typedef unsigned long size_t; /* see */ +N #else +N typedef unsigned int size_t; /* see */ +N #endif +N#elif !defined(__size_t) +X#elif !0L +S #define __size_t 1 +S #if __sizeof_ptr == 8 +S typedef unsigned long size_t; /* see */ +S #else +S typedef unsigned int size_t; /* see */ +S #endif +N#endif +N +N#undef NULL +N#define NULL 0 /* see */ +N +Nextern _ARMABI void *memcpy(void * __restrict /*s1*/, +Xextern __declspec(__nothrow) void *memcpy(void * __restrict , +N const void * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +N /* +N * copies n characters from the object pointed to by s2 into the object +N * pointed to by s1. If copying takes place between objects that overlap, +N * the behaviour is undefined. +N * Returns: the value of s1. +N */ +Nextern _ARMABI void *memmove(void * /*s1*/, +Xextern __declspec(__nothrow) void *memmove(void * , +N const void * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +N /* +N * copies n characters from the object pointed to by s2 into the object +N * pointed to by s1. Copying takes place as if the n characters from the +N * object pointed to by s2 are first copied into a temporary array of n +N * characters that does not overlap the objects pointed to by s1 and s2, +N * and then the n characters from the temporary array are copied into the +N * object pointed to by s1. +N * Returns: the value of s1. +N */ +Nextern _ARMABI char *strcpy(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strcpy(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); +N /* +N * copies the string pointed to by s2 (including the terminating nul +N * character) into the array pointed to by s1. If copying takes place +N * between objects that overlap, the behaviour is undefined. +N * Returns: the value of s1. +N */ +Nextern _ARMABI char *strncpy(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strncpy(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * copies not more than n characters (characters that follow a null +N * character are not copied) from the array pointed to by s2 into the array +N * pointed to by s1. If copying takes place between objects that overlap, +N * the behaviour is undefined. +N * Returns: the value of s1. +N */ +N +Nextern _ARMABI char *strcat(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strcat(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); +N /* +N * appends a copy of the string pointed to by s2 (including the terminating +N * null character) to the end of the string pointed to by s1. The initial +N * character of s2 overwrites the null character at the end of s1. +N * Returns: the value of s1. +N */ +Nextern _ARMABI char *strncat(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strncat(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * appends not more than n characters (a null character and characters that +N * follow it are not appended) from the array pointed to by s2 to the end of +N * the string pointed to by s1. The initial character of s2 overwrites the +N * null character at the end of s1. A terminating null character is always +N * appended to the result. +N * Returns: the value of s1. +N */ +N +N/* +N * The sign of a nonzero value returned by the comparison functions is +N * determined by the sign of the difference between the values of the first +N * pair of characters (both interpreted as unsigned char) that differ in the +N * objects being compared. +N */ +N +Nextern _ARMABI int memcmp(const void * /*s1*/, const void * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int memcmp(const void * , const void * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * compares the first n characters of the object pointed to by s1 to the +N * first n characters of the object pointed to by s2. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the object pointed to by s1 is greater than, equal to, or +N * less than the object pointed to by s2. +N */ +Nextern _ARMABI int strcmp(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strcmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * compares the string pointed to by s1 to the string pointed to by s2. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2. +N */ +Nextern _ARMABI int strncmp(const char * /*s1*/, const char * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strncmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * compares not more than n characters (characters that follow a null +N * character are not compared) from the array pointed to by s1 to the array +N * pointed to by s2. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2. +N */ +Nextern _ARMABI int strcasecmp(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strcasecmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * compares the string pointed to by s1 to the string pointed to by s2, +N * case-insensitively as defined by the current locale. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2. +N */ +Nextern _ARMABI int strncasecmp(const char * /*s1*/, const char * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strncasecmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * compares not more than n characters (characters that follow a null +N * character are not compared) from the array pointed to by s1 to the array +N * pointed to by s2, case-insensitively as defined by the current locale. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2. +N */ +Nextern _ARMABI int strcoll(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strcoll(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * compares the string pointed to by s1 to the string pointed to by s2, both +N * interpreted as appropriate to the LC_COLLATE category of the current +N * locale. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2 when both are interpreted +N * as appropriate to the current locale. +N */ +N +Nextern _ARMABI size_t strxfrm(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) size_t strxfrm(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(2))); +N /* +N * transforms the string pointed to by s2 and places the resulting string +N * into the array pointed to by s1. The transformation function is such that +N * if the strcmp function is applied to two transformed strings, it returns +N * a value greater than, equal to or less than zero, corresponding to the +N * result of the strcoll function applied to the same two original strings. +N * No more than n characters are placed into the resulting array pointed to +N * by s1, including the terminating null character. If n is zero, s1 is +N * permitted to be a null pointer. If copying takes place between objects +N * that overlap, the behaviour is undefined. +N * Returns: The length of the transformed string is returned (not including +N * the terminating null character). If the value returned is n or +N * more, the contents of the array pointed to by s1 are +N * indeterminate. +N */ +N +N +N#ifdef __cplusplus +Sextern _ARMABI const void *memchr(const void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1))); +Sextern "C++" void *memchr(void * __s, int __c, size_t __n) __attribute__((__nonnull__(1))); +Sextern "C++" inline void *memchr(void * __s, int __c, size_t __n) +S { return const_cast(memchr(const_cast(__s), __c, __n)); } +N#else +Nextern _ARMABI void *memchr(const void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) void *memchr(const void * , int , size_t ) __attribute__((__nonnull__(1))); +N#endif +N /* +N * locates the first occurence of c (converted to an unsigned char) in the +N * initial n characters (each interpreted as unsigned char) of the object +N * pointed to by s. +N * Returns: a pointer to the located character, or a null pointer if the +N * character does not occur in the object. +N */ +N +N#ifdef __cplusplus +Sextern _ARMABI const char *strchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); +Sextern "C++" char *strchr(char * __s, int __c) __attribute__((__nonnull__(1))); +Sextern "C++" inline char *strchr(char * __s, int __c) +S { return const_cast(strchr(const_cast(__s), __c)); } +N#else +Nextern _ARMABI char *strchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) char *strchr(const char * , int ) __attribute__((__nonnull__(1))); +N#endif +N /* +N * locates the first occurence of c (converted to an char) in the string +N * pointed to by s (including the terminating null character). +N * Returns: a pointer to the located character, or a null pointer if the +N * character does not occur in the string. +N */ +N +Nextern _ARMABI size_t strcspn(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) size_t strcspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * computes the length of the initial segment of the string pointed to by s1 +N * which consists entirely of characters not from the string pointed to by +N * s2. The terminating null character is not considered part of s2. +N * Returns: the length of the segment. +N */ +N +N#ifdef __cplusplus +Sextern _ARMABI const char *strpbrk(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Sextern "C++" char *strpbrk(char * __s1, const char * __s2) __attribute__((__nonnull__(1,2))); +Sextern "C++" inline char *strpbrk(char * __s1, const char * __s2) +S { return const_cast(strpbrk(const_cast(__s1), __s2)); } +N#else +Nextern _ARMABI char *strpbrk(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strpbrk(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N#endif +N /* +N * locates the first occurence in the string pointed to by s1 of any +N * character from the string pointed to by s2. +N * Returns: returns a pointer to the character, or a null pointer if no +N * character form s2 occurs in s1. +N */ +N +N#ifdef __cplusplus +Sextern _ARMABI const char *strrchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); +Sextern "C++" char *strrchr(char * __s, int __c) __attribute__((__nonnull__(1))); +Sextern "C++" inline char *strrchr(char * __s, int __c) +S { return const_cast(strrchr(const_cast(__s), __c)); } +N#else +Nextern _ARMABI char *strrchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) char *strrchr(const char * , int ) __attribute__((__nonnull__(1))); +N#endif +N /* +N * locates the last occurence of c (converted to a char) in the string +N * pointed to by s. The terminating null character is considered part of +N * the string. +N * Returns: returns a pointer to the character, or a null pointer if c does +N * not occur in the string. +N */ +N +Nextern _ARMABI size_t strspn(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) size_t strspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * computes the length of the initial segment of the string pointed to by s1 +N * which consists entirely of characters from the string pointed to by S2 +N * Returns: the length of the segment. +N */ +N +N#ifdef __cplusplus +Sextern _ARMABI const char *strstr(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Sextern "C++" char *strstr(char * __s1, const char * __s2) __attribute__((__nonnull__(1,2))); +Sextern "C++" inline char *strstr(char * __s1, const char * __s2) +S { return const_cast(strstr(const_cast(__s1), __s2)); } +N#else +Nextern _ARMABI char *strstr(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strstr(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N#endif +N /* +N * locates the first occurence in the string pointed to by s1 of the +N * sequence of characters (excluding the terminating null character) in the +N * string pointed to by s2. +N * Returns: a pointer to the located string, or a null pointer if the string +N * is not found. +N */ +N +Nextern _ARMABI char *strtok(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) char *strtok(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(2))); +Nextern _ARMABI char *_strtok_r(char * /*s1*/, const char * /*s2*/, char ** /*ptr*/) __attribute__((__nonnull__(2,3))); +Xextern __declspec(__nothrow) char *_strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); +N#ifndef __STRICT_ANSI__ +Nextern _ARMABI char *strtok_r(char * /*s1*/, const char * /*s2*/, char ** /*ptr*/) __attribute__((__nonnull__(2,3))); +Xextern __declspec(__nothrow) char *strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); +N#endif +N /* +N * A sequence of calls to the strtok function breaks the string pointed to +N * by s1 into a sequence of tokens, each of which is delimited by a +N * character from the string pointed to by s2. The first call in the +N * sequence has s1 as its first argument, and is followed by calls with a +N * null pointer as their first argument. The separator string pointed to by +N * s2 may be different from call to call. +N * The first call in the sequence searches for the first character that is +N * not contained in the current separator string s2. If no such character +N * is found, then there are no tokens in s1 and the strtok function returns +N * a null pointer. If such a character is found, it is the start of the +N * first token. +N * The strtok function then searches from there for a character that is +N * contained in the current separator string. If no such character is found, +N * the current token extends to the end of the string pointed to by s1, and +N * subsequent searches for a token will fail. If such a character is found, +N * it is overwritten by a null character, which terminates the current +N * token. The strtok function saves a pointer to the following character, +N * from which the next search for a token will start. +N * Each subsequent call, with a null pointer as the value for the first +N * argument, starts searching from the saved pointer and behaves as +N * described above. +N * Returns: pointer to the first character of a token, or a null pointer if +N * there is no token. +N * +N * strtok_r() is a common extension which works exactly like +N * strtok(), but instead of storing its state in a hidden +N * library variable, requires the user to pass in a pointer to a +N * char * variable which will be used instead. Any sequence of +N * calls to strtok_r() passing the same char ** pointer should +N * behave exactly like the corresponding sequence of calls to +N * strtok(). This means that strtok_r() can safely be used in +N * multi-threaded programs, and also that you can tokenise two +N * strings in parallel. +N */ +N +Nextern _ARMABI void *memset(void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) void *memset(void * , int , size_t ) __attribute__((__nonnull__(1))); +N /* +N * copies the value of c (converted to an unsigned char) into each of the +N * first n charactes of the object pointed to by s. +N * Returns: the value of s. +N */ +Nextern _ARMABI char *strerror(int /*errnum*/); +Xextern __declspec(__nothrow) char *strerror(int ); +N /* +N * maps the error number in errnum to an error message string. +N * Returns: a pointer to the string, the contents of which are +N * implementation-defined. The array pointed to shall not be +N * modified by the program, but may be overwritten by a +N * subsequent call to the strerror function. +N */ +Nextern _ARMABI size_t strlen(const char * /*s*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) size_t strlen(const char * ) __attribute__((__nonnull__(1))); +N /* +N * computes the length of the string pointed to by s. +N * Returns: the number of characters that precede the terminating null +N * character. +N */ +N +Nextern _ARMABI size_t strlcpy(char * /*dst*/, const char * /*src*/, size_t /*len*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) size_t strlcpy(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * copies the string src into the string dst, using no more than +N * len bytes of dst. Always null-terminates dst _within the +N * length len (i.e. will copy at most len-1 bytes of string plus +N * a NUL), unless len is actually zero. +N * +N * Return value is the length of the string that _would_ have +N * been written, i.e. the length of src. Thus, the operation +N * succeeded without truncation if and only if ret < len; +N * otherwise, the value in ret tells you how big to make dst if +N * you decide to reallocate it. (That value does _not_ include +N * the NUL.) +N * +N * This is a BSD-derived library extension, which we are +N * permitted to declare in a standard header because ISO defines +N * function names beginning with 'str' as reserved for future +N * expansion of . +N */ +N +Nextern _ARMABI size_t strlcat(char * /*dst*/, const char * /*src*/, size_t /*len*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) size_t strlcat(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * concatenates the string src to the string dst, using no more +N * than len bytes of dst. Always null-terminates dst _within the +N * length len (i.e. will copy at most len-1 bytes of string plus +N * a NUL), unless len is actually zero. +N * +N * Return value is the length of the string that _would_ have +N * been written, i.e. the length of src plus the original length +N * of dst. Thus, the operation succeeded without truncation if +N * and only if ret < len; otherwise, the value in ret tells you +N * how big to make dst if you decide to reallocate it. (That +N * value does _not_ include the NUL.) +N * +N * If no NUL is encountered within the first len bytes of dst, +N * then the length of dst is considered to have been equal to +N * len for the purposes of the return value (as if there were a +N * NUL at dst[len]). Thus, the return value in this case is len +N * + strlen(src). +N * +N * This is a BSD-derived library extension, which we are +N * permitted to declare in a standard header because ISO defines +N * function names beginning with 'str' as reserved for future +N * expansion of . +N */ +N +Nextern _ARMABI void _membitcpybl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpybl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpybb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpybb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpyhl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpyhl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpyhb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpyhb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpywl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpywl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpywb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpywb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovebl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovebl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovebb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovebb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovehl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovehl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovehb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovehb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovewl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovewl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovewb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovewb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * Copies or moves a piece of memory from one place to another, +N * with one-bit granularity. So you can start or finish a copy +N * part way through a byte, and you can copy between regions +N * with different alignment within a byte. +N * +N * All these functions have the same prototype: two void * +N * pointers for destination and source, then two integers +N * giving the bit offset from those pointers, and finally the +N * number of bits to copy. +N * +N * Just like memcpy and memmove, the "cpy" functions copy as +N * fast as they can in the assumption that the memory regions +N * do not overlap, while the "move" functions cope correctly +N * with overlap. +N * +N * Treating memory as a stream of individual bits requires +N * defining a convention about what order those bits are +N * considered to be arranged in. The above functions support +N * multiple conventions: +N * +N * - the "bl" functions consider the unit of memory to be the +N * byte, and consider the bits within each byte to be +N * arranged in little-endian fashion, so that the LSB comes +N * first. (For example, membitcpybl(a,b,0,7,1) would copy +N * the MSB of the byte at b to the LSB of the byte at a.) +N * +N * - the "bb" functions consider the unit of memory to be the +N * byte, and consider the bits within each byte to be +N * arranged in big-endian fashion, so that the MSB comes +N * first. +N * +N * - the "hl" functions consider the unit of memory to be the +N * 16-bit halfword, and consider the bits within each word +N * to be arranged in little-endian fashion. +N * +N * - the "hb" functions consider the unit of memory to be the +N * 16-bit halfword, and consider the bits within each word +N * to be arranged in big-endian fashion. +N * +N * - the "wl" functions consider the unit of memory to be the +N * 32-bit word, and consider the bits within each word to be +N * arranged in little-endian fashion. +N * +N * - the "wb" functions consider the unit of memory to be the +N * 32-bit word, and consider the bits within each word to be +N * arranged in big-endian fashion. +N */ +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif /* __cplusplus */ +N #endif /* __STRING_DECLS */ +N +N #ifdef __cplusplus +S #ifndef __STRING_NO_EXPORTS +S using ::std::size_t; +S using ::std::memcpy; +S using ::std::memmove; +S using ::std::strcpy; +S using ::std::strncpy; +S using ::std::strcat; +S using ::std::strncat; +S using ::std::memcmp; +S using ::std::strcmp; +S using ::std::strncmp; +S using ::std::strcasecmp; +S using ::std::strncasecmp; +S using ::std::strcoll; +S using ::std::strxfrm; +S using ::std::memchr; +S using ::std::strchr; +S using ::std::strcspn; +S using ::std::strpbrk; +S using ::std::strrchr; +S using ::std::strspn; +S using ::std::strstr; +S using ::std::strtok; +S#ifndef __STRICT_ANSI__ +S using ::std::strtok_r; +S#endif +S using ::std::_strtok_r; +S using ::std::memset; +S using ::std::strerror; +S using ::std::strlen; +S using ::std::strlcpy; +S using ::std::strlcat; +S using ::std::_membitcpybl; +S using ::std::_membitcpybb; +S using ::std::_membitcpyhl; +S using ::std::_membitcpyhb; +S using ::std::_membitcpywl; +S using ::std::_membitcpywb; +S using ::std::_membitmovebl; +S using ::std::_membitmovebb; +S using ::std::_membitmovehl; +S using ::std::_membitmovehb; +S using ::std::_membitmovewl; +S using ::std::_membitmovewb; +S #endif /* __STRING_NO_EXPORTS */ +N #endif /* __cplusplus */ +N +N#endif +N +N/* end of string.h */ +N +L 19 "..\..\src\common\tau_log.h" 2 +N#include +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.h" 1 +N/* stdarg.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.8 */ +N/* Copyright (C) Codemist Ltd., 1988 */ +N/* Copyright (C) ARM Ltd., 1991-1999. All rights reserved */ +N +N/* +N * RCS $Revision$ +N * Checkin $Date$ +N * Revising $Author: agrant $ +N */ +N +N#ifndef __stdarg_h +N#define __stdarg_h +N#define __ARMCLIB_VERSION 5060037 +N +N #ifndef __STDARG_DECLS +N #define __STDARG_DECLS +N +N #undef __CLIBNS +N +N #ifdef __cplusplus +S namespace std { +S #define __CLIBNS ::std:: +S extern "C" { +N #else +N #define __CLIBNS +N #endif /* __cplusplus */ +N +N/* +N * stdarg.h declares a type and defines macros for advancing through a +N * list of arguments whose number and types are not known to the called +N * function when it is translated. A function may be called with a variable +N * number of arguments of differing types. Its parameter list contains one or +N * more parameters. The rightmost parameter plays a special role in the access +N * mechanism, and will be called parmN in this description. +N */ +N +N/* N.B. is required to declare vfprintf() without defining */ +N/* va_list. Clearly the type __va_list there must keep in step. */ +N#ifdef __clang__ +S typedef __builtin_va_list va_list; +S #define va_start(ap, param) __builtin_va_start(ap, param) +S #define va_end(ap) __builtin_va_end(ap) +S #define va_arg(ap, type) __builtin_va_arg(ap, type) +S #if __STDC_VERSION__ >= 199900L || __cplusplus >= 201103L || !defined(__STRICT_ANSI__) +S #define va_copy(dest, src) __builtin_va_copy(dest, src) +S #endif +N#else +N #ifdef __TARGET_ARCH_AARCH64 +S typedef struct __va_list { +S void *__stack; +S void *__gr_top; +S void *__vr_top; +S int __gr_offs; +S int __vr_offs; +S } va_list; +N #else +N typedef struct __va_list { void *__ap; } va_list; +N #endif +N /* +N * an array type suitable for holding information needed by the macro va_arg +N * and the function va_end. The called function shall declare a variable +N * (referred to as ap) having type va_list. The variable ap may be passed as +N * an argument to another function. +N * Note: va_list is an array type so that when an object of that type +N * is passed as an argument it gets passed by reference. +N */ +N #define va_start(ap, parmN) __va_start(ap, parmN) +N +N /* +N * The va_start macro shall be executed before any access to the unnamed +N * arguments. The parameter ap points to an object that has type va_list. +N * The va_start macro initialises ap for subsequent use by va_arg and +N * va_end. The parameter parmN is the identifier of the rightmost parameter +N * in the variable parameter list in the function definition (the one just +N * before the '...'). If the parameter parmN is declared with the register +N * storage class an error is given. +N * If parmN is a narrow type (char, short, float) an error is given in +N * strict ANSI mode, or a warning otherwise. +N * Returns: no value. +N */ +N #define va_arg(ap, type) __va_arg(ap, type) +N +N /* +N * The va_arg macro expands to an expression that has the type and value of +N * the next argument in the call. The parameter ap shall be the same as the +N * va_list ap initialised by va_start. Each invocation of va_arg modifies +N * ap so that successive arguments are returned in turn. The parameter +N * 'type' is a type name such that the type of a pointer to an object that +N * has the specified type can be obtained simply by postfixing a * to +N * 'type'. If type is a narrow type, an error is given in strict ANSI +N * mode, or a warning otherwise. If the type is an array or function type, +N * an error is given. +N * In non-strict ANSI mode, 'type' is allowed to be any expression. +N * Returns: The first invocation of the va_arg macro after that of the +N * va_start macro returns the value of the argument after that +N * specified by parmN. Successive invocations return the values of +N * the remaining arguments in succession. +N * The result is cast to 'type', even if 'type' is narrow. +N */ +N +N#define __va_copy(dest, src) ((void)((dest) = (src))) +N +N#if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) +X#if !0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus) +N /* va_copy is in C99 and non-strict C90 and non-strict C++ +N * __va_copy is always present. +N */ +N #define va_copy(dest, src) ((void)((dest) = (src))) +N +N /* The va_copy macro makes the va_list dest be a copy of +N * the va_list src, as if the va_start macro had been applied +N * to it followed by the same sequence of uses of the va_arg +N * macro as had previously been used to reach the present state +N * of src. +N */ +N#endif +N +N#define va_end(ap) __va_end(ap) +N /* +N * The va_end macro facilitates a normal return from the function whose +N * variable argument list was referenced by the expansion of va_start that +N * initialised the va_list ap. If the va_end macro is not invoked before +N * the return, the behaviour is undefined. +N * Returns: no value. +N */ +N#endif /* __clang__ */ +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif /* __cplusplus */ +N +N #ifdef __GNUC__ +N /* be cooperative with glibc */ +N typedef __CLIBNS va_list __gnuc_va_list; +X typedef va_list __gnuc_va_list; +N #define __GNUC_VA_LIST +N #undef __need___va_list +N #endif +N +N #endif /* __STDARG_DECLS */ +N +N #ifdef __cplusplus +S #ifndef __STDARG_NO_EXPORTS +S using ::std::va_list; +S #endif +N #endif /* __cplusplus */ +N#endif +N +N/* end of stdarg.h */ +N +L 20 "..\..\src\common\tau_log.h" 2 +N#include "ArmCM0.h" +L 1 "..\..\src\sdk\include\M0\ArmCM0.h" 1 +N/**************************************************************************//** +N * @file ARMCM0.h +N * @brief CMSIS Core Peripheral Access Layer Header File for +N * ARMCM0 Device +N * @version V5.3.1 +N * @date 09. July 2018 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#ifndef ARMCM0_H +N#define ARMCM0_H +N +N#ifdef __cplusplus +Sextern "C" { +N#endif +N +N +N/* ------------------------- Interrupt Number Definition ------------------------ */ +N +Ntypedef enum IRQn +N{ +N /* ------------------- Processor Exceptions Numbers ----------------------------- */ +N NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ +N HardFault_IRQn = -13, /* 3 HardFault Interrupt */ +N SVCall_IRQn = -5, /* 11 SV Call Interrupt */ +N PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ +N SysTick_IRQn = -1, /* 15 System Tick Interrupt */ +N +N /* ------------------- Processor Interrupt Numbers ------------------------------ */ +N VIDC_IRQn = 0, +N LCDC_IRQn = 1, +N MIPI_RX_IRQn = 2, +N MIPI_TX_IRQn = 3, +N MEMC_IRQn = 4, +N VPRE_IRQn = 5, +N FLSCTRL_IRQn = 6, +N DMA_IRQn = 7, +N TIMER0_IRQn = 8, +N TIMER1_IRQn = 9, +N TIMER2_IRQn = 10, +N TIMER3_IRQn = 11, +N WDG_IRQn = 12, +N UART_IRQn = 13, +N I2C0_IRQn = 14, +N I2C1_IRQn = 15, +N SPIS_IRQn = 16, +N SPIM_IRQn = 17, +N VPRE1_IRQn = 18, +N I2C2_IRQn = 19, +N OTP_IRQn = 20, +N SWIRE_IRQn = 21, +N PVD_IRQn = 22, +N AP_NRESET_IRQn = 23, +N EXTI_INT0_IRQn = 24, +N EXTI_INT1_IRQn = 25, +N EXTI_INT2_IRQn = 26, +N EXTI_INT3_IRQn = 27, +N EXTI_INT4_IRQn = 28, +N EXTI_INT5_IRQn = 29, +N EXTI_INT6_IRQn = 30, +N EXTI_INT7_IRQn = 31 +N /* Interrupts 10 .. 31 are left out */ +N} IRQn_Type; +N +N +N/* ================================================================================ */ +N/* ================ Processor and Core Peripheral Section ================ */ +N/* ================================================================================ */ +N +N/* ------- Start of section using anonymous unions and disabling warnings ------- */ +N#if defined (__CC_ARM) +X#if 1L +N#pragma push +N#pragma anon_unions +N#elif defined (__ICCARM__) +X#elif 0L +S#pragma language=extended +S#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +S#pragma clang diagnostic push +S#pragma clang diagnostic ignored "-Wc11-extensions" +S#pragma clang diagnostic ignored "-Wreserved-id-macro" +S#elif defined (__GNUC__) +S/* anonymous unions are enabled by default */ +S#elif defined (__TMS470__) +S/* anonymous unions are enabled by default */ +S#elif defined (__TASKING__) +S#pragma warning 586 +S#elif defined (__CSMC__) +S/* anonymous unions are enabled by default */ +S#else +S#warning Not supported compiler type +N#endif +N +N/* -------- Configuration of Core Peripherals ----------------------------------- */ +N#define __CM0_REV 0x0000U /* Core revision r0p0 */ +N#define __MPU_PRESENT 0U /* no MPU present */ +N#define __VTOR_PRESENT 0U /* no VTOR present */ +N#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ //20220228 +N#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +N +N#define __FPU_PRESENT 0U /* Set to 1 if FPU is present */ +N#define __FPU_DP 0U /* single precision FPU */ +N#define __ICACHE_PRESENT 0U /* Set to 1 if I-CACHE is present */ +N#define __DCACHE_PRESENT 0U /* Set to 1 if D-CACHE is present */ +N#define __DSP_PRESENT 0U /* no DSP extension present */ +N +N#include "core_cm0.h" /* Processor and core peripherals */ +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h" 1 +N/**************************************************************************//** +N * @file core_cm0.h +N * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File +N * @version V5.0.6 +N * @date 13. March 2019 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2019 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#if defined ( __ICCARM__ ) +X#if 0L +S #pragma system_include /* treat file as system include file for MISRA check */ +S#elif defined (__clang__) +X#elif 0L +S #pragma clang system_header /* treat file as system include file */ +N#endif +N +N#ifndef __CORE_CM0_H_GENERIC +N#define __CORE_CM0_H_GENERIC +N +N#include +N +N#ifdef __cplusplus +S extern "C" { +N#endif +N +N/** +N \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions +N CMSIS violates the following MISRA-C:2004 rules: +N +N \li Required Rule 8.5, object/function definition in header file.
+N Function definitions in header files are used to allow 'inlining'. +N +N \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+N Unions are used for effective representation of core registers. +N +N \li Advisory Rule 19.7, Function-like macro defined.
+N Function-like macros are used to allow more efficient code. +N */ +N +N +N/******************************************************************************* +N * CMSIS definitions +N ******************************************************************************/ +N/** +N \ingroup Cortex_M0 +N @{ +N */ +N +N#include "cmsis_version.h" +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_version.h" 1 +N/**************************************************************************//** +N * @file cmsis_version.h +N * @brief CMSIS Core(M) Version definitions +N * @version V5.0.2 +N * @date 19. April 2017 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2017 ARM Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#if defined ( __ICCARM__ ) +X#if 0L +S #pragma system_include /* treat file as system include file for MISRA check */ +S#elif defined (__clang__) +X#elif 0L +S #pragma clang system_header /* treat file as system include file */ +N#endif +N +N#ifndef __CMSIS_VERSION_H +N#define __CMSIS_VERSION_H +N +N/* CMSIS Version definitions */ +N#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +N#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +N#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ +N __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +X#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | __CM_CMSIS_VERSION_SUB ) +N#endif +L 64 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h" 2 +N +N/* CMSIS CM0 definitions */ +N#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +N#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +N#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ +N __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ +X#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB ) +N +N#define __CORTEX_M (0U) /*!< Cortex-M Core */ +N +N/** __FPU_USED indicates whether an FPU is used or not. +N This core does not support an FPU at all +N*/ +N#define __FPU_USED 0U +N +N#if defined ( __CC_ARM ) +X#if 1L +N #if defined __TARGET_FPU_VFP +X #if 0L +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +N #endif +N +N#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +X#elif 1L && (5060750 >= 6010050) +S #if defined __ARM_FP +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __GNUC__ ) +S #if defined (__VFP_FP__) && !defined(__SOFTFP__) +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __ICCARM__ ) +S #if defined __ARMVFP__ +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __TI_ARM__ ) +S #if defined __TI_VFP_SUPPORT__ +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __TASKING__ ) +S #if defined __FPU_VFP__ +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __CSMC__ ) +S #if ( __CSMC__ & 0x400U) +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +N#endif +N +N#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h" 1 +N/**************************************************************************//** +N * @file cmsis_compiler.h +N * @brief CMSIS compiler generic header file +N * @version V5.1.0 +N * @date 09. October 2018 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#ifndef __CMSIS_COMPILER_H +N#define __CMSIS_COMPILER_H +N +N#include +N +N/* +N * Arm Compiler 4/5 +N */ +N#if defined ( __CC_ARM ) +X#if 1L +N #include "cmsis_armcc.h" +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_armcc.h" 1 +N/**************************************************************************//** +N * @file cmsis_armcc.h +N * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file +N * @version V5.0.5 +N * @date 14. December 2018 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#ifndef __CMSIS_ARMCC_H +N#define __CMSIS_ARMCC_H +N +N +N#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) +X#if 1L && (5060750 < 400677) +S #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +N#endif +N +N/* CMSIS compiler control architecture macros */ +N#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ +N (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) +X#if ((0L && (__TARGET_ARCH_6_M == 1)) || (1L && (1 == 1)) ) +N #define __ARM_ARCH_6M__ 1 +N#endif +N +N#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) +X#if (0L && (__TARGET_ARCH_7_M == 1)) +S #define __ARM_ARCH_7M__ 1 +N#endif +N +N#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) +X#if (0L && (__TARGET_ARCH_7E_M == 1)) +S #define __ARM_ARCH_7EM__ 1 +N#endif +N +N /* __ARM_ARCH_8M_BASE__ not applicable */ +N /* __ARM_ARCH_8M_MAIN__ not applicable */ +N +N/* CMSIS compiler control DSP macros */ +N#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7EM__ == 1)) ) +S #define __ARM_FEATURE_DSP 1 +N#endif +N +N/* CMSIS compiler specific defines */ +N#ifndef __ASM +N #define __ASM __asm +N#endif +N#ifndef __INLINE +N #define __INLINE __inline +N#endif +N#ifndef __STATIC_INLINE +N #define __STATIC_INLINE static __inline +N#endif +N#ifndef __STATIC_FORCEINLINE +N #define __STATIC_FORCEINLINE static __forceinline +N#endif +N#ifndef __NO_RETURN +N #define __NO_RETURN __declspec(noreturn) +N#endif +N#ifndef __USED +N #define __USED __attribute__((used)) +N#endif +N#ifndef __WEAK +N #define __WEAK __attribute__((weak)) +N#endif +N#ifndef __PACKED +N #define __PACKED __attribute__((packed)) +N#endif +N#ifndef __PACKED_STRUCT +N #define __PACKED_STRUCT __packed struct +N#endif +N#ifndef __PACKED_UNION +N #define __PACKED_UNION __packed union +N#endif +N#ifndef __UNALIGNED_UINT32 /* deprecated */ +N #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +N#endif +N#ifndef __UNALIGNED_UINT16_WRITE +N #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +N#endif +N#ifndef __UNALIGNED_UINT16_READ +N #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +N#endif +N#ifndef __UNALIGNED_UINT32_WRITE +N #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +N#endif +N#ifndef __UNALIGNED_UINT32_READ +N #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +N#endif +N#ifndef __ALIGNED +N #define __ALIGNED(x) __attribute__((aligned(x))) +N#endif +N#ifndef __RESTRICT +N #define __RESTRICT __restrict +N#endif +N +N/* ########################### Core Function Access ########################### */ +N/** \ingroup CMSIS_Core_FunctionInterface +N \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions +N @{ +N */ +N +N/** +N \brief Enable IRQ Interrupts +N \details Enables IRQ interrupts by clearing the I-bit in the CPSR. +N Can only be executed in Privileged modes. +N */ +N/* intrinsic void __enable_irq(); */ +N +N +N/** +N \brief Disable IRQ Interrupts +N \details Disables IRQ interrupts by setting the I-bit in the CPSR. +N Can only be executed in Privileged modes. +N */ +N/* intrinsic void __disable_irq(); */ +N +N/** +N \brief Get Control Register +N \details Returns the content of the Control Register. +N \return Control Register value +N */ +N__STATIC_INLINE uint32_t __get_CONTROL(void) +Xstatic __inline uint32_t __get_CONTROL(void) +N{ +N register uint32_t __regControl __ASM("control"); +X register uint32_t __regControl __asm("control"); +N return(__regControl); +N} +N +N +N/** +N \brief Set Control Register +N \details Writes the given value to the Control Register. +N \param [in] control Control Register value to set +N */ +N__STATIC_INLINE void __set_CONTROL(uint32_t control) +Xstatic __inline void __set_CONTROL(uint32_t control) +N{ +N register uint32_t __regControl __ASM("control"); +X register uint32_t __regControl __asm("control"); +N __regControl = control; +N} +N +N +N/** +N \brief Get IPSR Register +N \details Returns the content of the IPSR Register. +N \return IPSR Register value +N */ +N__STATIC_INLINE uint32_t __get_IPSR(void) +Xstatic __inline uint32_t __get_IPSR(void) +N{ +N register uint32_t __regIPSR __ASM("ipsr"); +X register uint32_t __regIPSR __asm("ipsr"); +N return(__regIPSR); +N} +N +N +N/** +N \brief Get APSR Register +N \details Returns the content of the APSR Register. +N \return APSR Register value +N */ +N__STATIC_INLINE uint32_t __get_APSR(void) +Xstatic __inline uint32_t __get_APSR(void) +N{ +N register uint32_t __regAPSR __ASM("apsr"); +X register uint32_t __regAPSR __asm("apsr"); +N return(__regAPSR); +N} +N +N +N/** +N \brief Get xPSR Register +N \details Returns the content of the xPSR Register. +N \return xPSR Register value +N */ +N__STATIC_INLINE uint32_t __get_xPSR(void) +Xstatic __inline uint32_t __get_xPSR(void) +N{ +N register uint32_t __regXPSR __ASM("xpsr"); +X register uint32_t __regXPSR __asm("xpsr"); +N return(__regXPSR); +N} +N +N +N/** +N \brief Get Process Stack Pointer +N \details Returns the current value of the Process Stack Pointer (PSP). +N \return PSP Register value +N */ +N__STATIC_INLINE uint32_t __get_PSP(void) +Xstatic __inline uint32_t __get_PSP(void) +N{ +N register uint32_t __regProcessStackPointer __ASM("psp"); +X register uint32_t __regProcessStackPointer __asm("psp"); +N return(__regProcessStackPointer); +N} +N +N +N/** +N \brief Set Process Stack Pointer +N \details Assigns the given value to the Process Stack Pointer (PSP). +N \param [in] topOfProcStack Process Stack Pointer value to set +N */ +N__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +Xstatic __inline void __set_PSP(uint32_t topOfProcStack) +N{ +N register uint32_t __regProcessStackPointer __ASM("psp"); +X register uint32_t __regProcessStackPointer __asm("psp"); +N __regProcessStackPointer = topOfProcStack; +N} +N +N +N/** +N \brief Get Main Stack Pointer +N \details Returns the current value of the Main Stack Pointer (MSP). +N \return MSP Register value +N */ +N__STATIC_INLINE uint32_t __get_MSP(void) +Xstatic __inline uint32_t __get_MSP(void) +N{ +N register uint32_t __regMainStackPointer __ASM("msp"); +X register uint32_t __regMainStackPointer __asm("msp"); +N return(__regMainStackPointer); +N} +N +N +N/** +N \brief Set Main Stack Pointer +N \details Assigns the given value to the Main Stack Pointer (MSP). +N \param [in] topOfMainStack Main Stack Pointer value to set +N */ +N__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +Xstatic __inline void __set_MSP(uint32_t topOfMainStack) +N{ +N register uint32_t __regMainStackPointer __ASM("msp"); +X register uint32_t __regMainStackPointer __asm("msp"); +N __regMainStackPointer = topOfMainStack; +N} +N +N +N/** +N \brief Get Priority Mask +N \details Returns the current state of the priority mask bit from the Priority Mask Register. +N \return Priority Mask value +N */ +N__STATIC_INLINE uint32_t __get_PRIMASK(void) +Xstatic __inline uint32_t __get_PRIMASK(void) +N{ +N register uint32_t __regPriMask __ASM("primask"); +X register uint32_t __regPriMask __asm("primask"); +N return(__regPriMask); +N} +N +N +N/** +N \brief Set Priority Mask +N \details Assigns the given value to the Priority Mask Register. +N \param [in] priMask Priority Mask +N */ +N__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +Xstatic __inline void __set_PRIMASK(uint32_t priMask) +N{ +N register uint32_t __regPriMask __ASM("primask"); +X register uint32_t __regPriMask __asm("primask"); +N __regPriMask = (priMask); +N} +N +N +N#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7M__ == 1)) || (0L && (__ARM_ARCH_7EM__ == 1)) ) +S +S/** +S \brief Enable FIQ +S \details Enables FIQ interrupts by clearing the F-bit in the CPSR. +S Can only be executed in Privileged modes. +S */ +S#define __enable_fault_irq __enable_fiq +S +S +S/** +S \brief Disable FIQ +S \details Disables FIQ interrupts by setting the F-bit in the CPSR. +S Can only be executed in Privileged modes. +S */ +S#define __disable_fault_irq __disable_fiq +S +S +S/** +S \brief Get Base Priority +S \details Returns the current value of the Base Priority register. +S \return Base Priority register value +S */ +S__STATIC_INLINE uint32_t __get_BASEPRI(void) +S{ +S register uint32_t __regBasePri __ASM("basepri"); +S return(__regBasePri); +S} +S +S +S/** +S \brief Set Base Priority +S \details Assigns the given value to the Base Priority register. +S \param [in] basePri Base Priority value to set +S */ +S__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +S{ +S register uint32_t __regBasePri __ASM("basepri"); +S __regBasePri = (basePri & 0xFFU); +S} +S +S +S/** +S \brief Set Base Priority with condition +S \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, +S or the new value increases the BASEPRI priority level. +S \param [in] basePri Base Priority value to set +S */ +S__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +S{ +S register uint32_t __regBasePriMax __ASM("basepri_max"); +S __regBasePriMax = (basePri & 0xFFU); +S} +S +S +S/** +S \brief Get Fault Mask +S \details Returns the current value of the Fault Mask register. +S \return Fault Mask register value +S */ +S__STATIC_INLINE uint32_t __get_FAULTMASK(void) +S{ +S register uint32_t __regFaultMask __ASM("faultmask"); +S return(__regFaultMask); +S} +S +S +S/** +S \brief Set Fault Mask +S \details Assigns the given value to the Fault Mask register. +S \param [in] faultMask Fault Mask value to set +S */ +S__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +S{ +S register uint32_t __regFaultMask __ASM("faultmask"); +S __regFaultMask = (faultMask & (uint32_t)1U); +S} +S +N#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +X#endif +N +N +N/** +N \brief Get FPSCR +N \details Returns the current value of the Floating Point Status/Control register. +N \return Floating Point Status/Control register value +N */ +N__STATIC_INLINE uint32_t __get_FPSCR(void) +Xstatic __inline uint32_t __get_FPSCR(void) +N{ +N#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ +N (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +X#if ((1L && (0U == 1U)) && (1L && (0U == 1U)) ) +S register uint32_t __regfpscr __ASM("fpscr"); +S return(__regfpscr); +N#else +N return(0U); +N#endif +N} +N +N +N/** +N \brief Set FPSCR +N \details Assigns the given value to the Floating Point Status/Control register. +N \param [in] fpscr Floating Point Status/Control value to set +N */ +N__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +Xstatic __inline void __set_FPSCR(uint32_t fpscr) +N{ +N#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ +N (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +X#if ((1L && (0U == 1U)) && (1L && (0U == 1U)) ) +S register uint32_t __regfpscr __ASM("fpscr"); +S __regfpscr = (fpscr); +N#else +N (void)fpscr; +N#endif +N} +N +N +N/*@} end of CMSIS_Core_RegAccFunctions */ +N +N +N/* ########################## Core Instruction Access ######################### */ +N/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface +N Access to dedicated instructions +N @{ +N*/ +N +N/** +N \brief No Operation +N \details No Operation does nothing. This instruction can be used for code alignment purposes. +N */ +N#define __NOP __nop +N +N +N/** +N \brief Wait For Interrupt +N \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. +N */ +N#define __WFI __wfi +N +N +N/** +N \brief Wait For Event +N \details Wait For Event is a hint instruction that permits the processor to enter +N a low-power state until one of a number of events occurs. +N */ +N#define __WFE __wfe +N +N +N/** +N \brief Send Event +N \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. +N */ +N#define __SEV __sev +N +N +N/** +N \brief Instruction Synchronization Barrier +N \details Instruction Synchronization Barrier flushes the pipeline in the processor, +N so that all instructions following the ISB are fetched from cache or memory, +N after the instruction has been completed. +N */ +N#define __ISB() do {\ +N __schedule_barrier();\ +N __isb(0xF);\ +N __schedule_barrier();\ +N } while (0U) +X#define __ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U) +N +N/** +N \brief Data Synchronization Barrier +N \details Acts as a special kind of Data Memory Barrier. +N It completes when all explicit memory accesses before this instruction complete. +N */ +N#define __DSB() do {\ +N __schedule_barrier();\ +N __dsb(0xF);\ +N __schedule_barrier();\ +N } while (0U) +X#define __DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U) +N +N/** +N \brief Data Memory Barrier +N \details Ensures the apparent order of the explicit memory operations before +N and after the instruction, without ensuring their completion. +N */ +N#define __DMB() do {\ +N __schedule_barrier();\ +N __dmb(0xF);\ +N __schedule_barrier();\ +N } while (0U) +X#define __DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U) +N +N +N/** +N \brief Reverse byte order (32 bit) +N \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. +N \param [in] value Value to reverse +N \return Reversed value +N */ +N#define __REV __rev +N +N +N/** +N \brief Reverse byte order (16 bit) +N \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. +N \param [in] value Value to reverse +N \return Reversed value +N */ +N#ifndef __NO_EMBEDDED_ASM +N__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +X__attribute__((section(".rev16_text"))) static __inline __asm uint32_t __REV16(uint32_t value) +N{ +N rev16 r0, r0 +N bx lr +N} +N#endif +N +N +N/** +N \brief Reverse byte order (16 bit) +N \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. +N \param [in] value Value to reverse +N \return Reversed value +N */ +N#ifndef __NO_EMBEDDED_ASM +N__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +X__attribute__((section(".revsh_text"))) static __inline __asm int16_t __REVSH(int16_t value) +N{ +N revsh r0, r0 +N bx lr +N} +N#endif +N +N +N/** +N \brief Rotate Right in unsigned value (32 bit) +N \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. +N \param [in] op1 Value to rotate +N \param [in] op2 Number of Bits to rotate +N \return Rotated value +N */ +N#define __ROR __ror +N +N +N/** +N \brief Breakpoint +N \details Causes the processor to enter Debug state. +N Debug tools can use this to investigate system state when the instruction at a particular address is reached. +N \param [in] value is ignored by the processor. +N If required, a debugger can use it to store additional information about the breakpoint. +N */ +N#define __BKPT(value) __breakpoint(value) +N +N +N/** +N \brief Reverse bit order of value +N \details Reverses the bit order of the given value. +N \param [in] value Value to reverse +N \return Reversed value +N */ +N#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7M__ == 1)) || (0L && (__ARM_ARCH_7EM__ == 1)) ) +S #define __RBIT __rbit +N#else +N__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +X__attribute__((always_inline)) static __inline uint32_t __RBIT(uint32_t value) +N{ +N uint32_t result; +N uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ +N +N result = value; /* r will be reversed bits of v; first get LSB of v */ +N for (value >>= 1U; value != 0U; value >>= 1U) +N { +N result <<= 1U; +N result |= value & 1U; +N s--; +N } +N result <<= s; /* shift when v's highest bits are zero */ +N return result; +N} +N#endif +N +N +N/** +N \brief Count leading zeros +N \details Counts the number of leading zeros of a data value. +N \param [in] value Value to count the leading zeros +N \return number of leading zeros in value +N */ +N#define __CLZ __clz +N +N +N#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7M__ == 1)) || (0L && (__ARM_ARCH_7EM__ == 1)) ) +S +S/** +S \brief LDR Exclusive (8 bit) +S \details Executes a exclusive LDR instruction for 8 bit value. +S \param [in] ptr Pointer to data +S \return value of type uint8_t at (*ptr) +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +S#else +S #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +S#endif +S +S +S/** +S \brief LDR Exclusive (16 bit) +S \details Executes a exclusive LDR instruction for 16 bit values. +S \param [in] ptr Pointer to data +S \return value of type uint16_t at (*ptr) +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +S#else +S #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +S#endif +S +S +S/** +S \brief LDR Exclusive (32 bit) +S \details Executes a exclusive LDR instruction for 32 bit values. +S \param [in] ptr Pointer to data +S \return value of type uint32_t at (*ptr) +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +S#else +S #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +S#endif +S +S +S/** +S \brief STR Exclusive (8 bit) +S \details Executes a exclusive STR instruction for 8 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S \return 0 Function succeeded +S \return 1 Function failed +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __STREXB(value, ptr) __strex(value, ptr) +S#else +S #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +S#endif +S +S +S/** +S \brief STR Exclusive (16 bit) +S \details Executes a exclusive STR instruction for 16 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S \return 0 Function succeeded +S \return 1 Function failed +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __STREXH(value, ptr) __strex(value, ptr) +S#else +S #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +S#endif +S +S +S/** +S \brief STR Exclusive (32 bit) +S \details Executes a exclusive STR instruction for 32 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S \return 0 Function succeeded +S \return 1 Function failed +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __STREXW(value, ptr) __strex(value, ptr) +S#else +S #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +S#endif +S +S +S/** +S \brief Remove the exclusive lock +S \details Removes the exclusive lock which is created by LDREX. +S */ +S#define __CLREX __clrex +S +S +S/** +S \brief Signed Saturate +S \details Saturates a signed value. +S \param [in] value Value to be saturated +S \param [in] sat Bit position to saturate to (1..32) +S \return Saturated value +S */ +S#define __SSAT __ssat +S +S +S/** +S \brief Unsigned Saturate +S \details Saturates an unsigned value. +S \param [in] value Value to be saturated +S \param [in] sat Bit position to saturate to (0..31) +S \return Saturated value +S */ +S#define __USAT __usat +S +S +S/** +S \brief Rotate Right with Extend (32 bit) +S \details Moves each bit of a bitstring right by one bit. +S The carry input is shifted in at the left end of the bitstring. +S \param [in] value Value to rotate +S \return Rotated value +S */ +S#ifndef __NO_EMBEDDED_ASM +S__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +S{ +S rrx r0, r0 +S bx lr +S} +S#endif +S +S +S/** +S \brief LDRT Unprivileged (8 bit) +S \details Executes a Unprivileged LDRT instruction for 8 bit value. +S \param [in] ptr Pointer to data +S \return value of type uint8_t at (*ptr) +S */ +S#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) +S +S +S/** +S \brief LDRT Unprivileged (16 bit) +S \details Executes a Unprivileged LDRT instruction for 16 bit values. +S \param [in] ptr Pointer to data +S \return value of type uint16_t at (*ptr) +S */ +S#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) +S +S +S/** +S \brief LDRT Unprivileged (32 bit) +S \details Executes a Unprivileged LDRT instruction for 32 bit values. +S \param [in] ptr Pointer to data +S \return value of type uint32_t at (*ptr) +S */ +S#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) +S +S +S/** +S \brief STRT Unprivileged (8 bit) +S \details Executes a Unprivileged STRT instruction for 8 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S */ +S#define __STRBT(value, ptr) __strt(value, ptr) +S +S +S/** +S \brief STRT Unprivileged (16 bit) +S \details Executes a Unprivileged STRT instruction for 16 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S */ +S#define __STRHT(value, ptr) __strt(value, ptr) +S +S +S/** +S \brief STRT Unprivileged (32 bit) +S \details Executes a Unprivileged STRT instruction for 32 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S */ +S#define __STRT(value, ptr) __strt(value, ptr) +S +N#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +X#else +N +N/** +N \brief Signed Saturate +N \details Saturates a signed value. +N \param [in] value Value to be saturated +N \param [in] sat Bit position to saturate to (1..32) +N \return Saturated value +N */ +N__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +X__attribute__((always_inline)) static __inline int32_t __SSAT(int32_t val, uint32_t sat) +N{ +N if ((sat >= 1U) && (sat <= 32U)) +N { +N const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); +N const int32_t min = -1 - max ; +N if (val > max) +N { +N return max; +N } +N else if (val < min) +N { +N return min; +N } +N } +N return val; +N} +N +N/** +N \brief Unsigned Saturate +N \details Saturates an unsigned value. +N \param [in] value Value to be saturated +N \param [in] sat Bit position to saturate to (0..31) +N \return Saturated value +N */ +N__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +X__attribute__((always_inline)) static __inline uint32_t __USAT(int32_t val, uint32_t sat) +N{ +N if (sat <= 31U) +N { +N const uint32_t max = ((1U << sat) - 1U); +N if (val > (int32_t)max) +N { +N return max; +N } +N else if (val < 0) +N { +N return 0U; +N } +N } +N return (uint32_t)val; +N} +N +N#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +X#endif +N +N/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ +N +N +N/* ################### Compiler specific Intrinsics ########################### */ +N/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics +N Access to dedicated SIMD instructions +N @{ +N*/ +N +N#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7EM__ == 1)) ) +S +S#define __SADD8 __sadd8 +S#define __QADD8 __qadd8 +S#define __SHADD8 __shadd8 +S#define __UADD8 __uadd8 +S#define __UQADD8 __uqadd8 +S#define __UHADD8 __uhadd8 +S#define __SSUB8 __ssub8 +S#define __QSUB8 __qsub8 +S#define __SHSUB8 __shsub8 +S#define __USUB8 __usub8 +S#define __UQSUB8 __uqsub8 +S#define __UHSUB8 __uhsub8 +S#define __SADD16 __sadd16 +S#define __QADD16 __qadd16 +S#define __SHADD16 __shadd16 +S#define __UADD16 __uadd16 +S#define __UQADD16 __uqadd16 +S#define __UHADD16 __uhadd16 +S#define __SSUB16 __ssub16 +S#define __QSUB16 __qsub16 +S#define __SHSUB16 __shsub16 +S#define __USUB16 __usub16 +S#define __UQSUB16 __uqsub16 +S#define __UHSUB16 __uhsub16 +S#define __SASX __sasx +S#define __QASX __qasx +S#define __SHASX __shasx +S#define __UASX __uasx +S#define __UQASX __uqasx +S#define __UHASX __uhasx +S#define __SSAX __ssax +S#define __QSAX __qsax +S#define __SHSAX __shsax +S#define __USAX __usax +S#define __UQSAX __uqsax +S#define __UHSAX __uhsax +S#define __USAD8 __usad8 +S#define __USADA8 __usada8 +S#define __SSAT16 __ssat16 +S#define __USAT16 __usat16 +S#define __UXTB16 __uxtb16 +S#define __UXTAB16 __uxtab16 +S#define __SXTB16 __sxtb16 +S#define __SXTAB16 __sxtab16 +S#define __SMUAD __smuad +S#define __SMUADX __smuadx +S#define __SMLAD __smlad +S#define __SMLADX __smladx +S#define __SMLALD __smlald +S#define __SMLALDX __smlaldx +S#define __SMUSD __smusd +S#define __SMUSDX __smusdx +S#define __SMLSD __smlsd +S#define __SMLSDX __smlsdx +S#define __SMLSLD __smlsld +S#define __SMLSLDX __smlsldx +S#define __SEL __sel +S#define __QADD __qadd +S#define __QSUB __qsub +S +S#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ +S ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) +X#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) +S +S#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ +S ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) +X#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) +S +S#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ +S ((int64_t)(ARG3) << 32U) ) >> 32U)) +X#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U) ) >> 32U)) +S +N#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +N/*@} end of group CMSIS_SIMD_intrinsics */ +N +N +N#endif /* __CMSIS_ARMCC_H */ +L 35 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h" 2 +N +N +N/* +N * Arm Compiler 6.6 LTM (armclang) +N */ +N#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) +X#elif 1L && (5060750 >= 6010050) && (5060750 < 6100100) +S #include "cmsis_armclang_ltm.h" +S +S /* +S * Arm Compiler above 6.10.1 (armclang) +S */ +S#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) +S #include "cmsis_armclang.h" +S +S +S/* +S * GNU Compiler +S */ +S#elif defined ( __GNUC__ ) +S #include "cmsis_gcc.h" +S +S +S/* +S * IAR Compiler +S */ +S#elif defined ( __ICCARM__ ) +S #include +S +S +S/* +S * TI Arm Compiler +S */ +S#elif defined ( __TI_ARM__ ) +S #include +S +S #ifndef __ASM +S #define __ASM __asm +S #endif +S #ifndef __INLINE +S #define __INLINE inline +S #endif +S #ifndef __STATIC_INLINE +S #define __STATIC_INLINE static inline +S #endif +S #ifndef __STATIC_FORCEINLINE +S #define __STATIC_FORCEINLINE __STATIC_INLINE +S #endif +S #ifndef __NO_RETURN +S #define __NO_RETURN __attribute__((noreturn)) +S #endif +S #ifndef __USED +S #define __USED __attribute__((used)) +S #endif +S #ifndef __WEAK +S #define __WEAK __attribute__((weak)) +S #endif +S #ifndef __PACKED +S #define __PACKED __attribute__((packed)) +S #endif +S #ifndef __PACKED_STRUCT +S #define __PACKED_STRUCT struct __attribute__((packed)) +S #endif +S #ifndef __PACKED_UNION +S #define __PACKED_UNION union __attribute__((packed)) +S #endif +S #ifndef __UNALIGNED_UINT32 /* deprecated */ +S struct __attribute__((packed)) T_UINT32 { uint32_t v; }; +S #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +S #endif +S #ifndef __UNALIGNED_UINT16_WRITE +S __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +S #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT16_READ +S __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +S #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __UNALIGNED_UINT32_WRITE +S __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +S #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT32_READ +S __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +S #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __ALIGNED +S #define __ALIGNED(x) __attribute__((aligned(x))) +S #endif +S #ifndef __RESTRICT +S #define __RESTRICT __restrict +S #endif +S +S +S/* +S * TASKING Compiler +S */ +S#elif defined ( __TASKING__ ) +S /* +S * The CMSIS functions have been implemented as intrinsics in the compiler. +S * Please use "carm -?i" to get an up to date list of all intrinsics, +S * Including the CMSIS ones. +S */ +S +S #ifndef __ASM +S #define __ASM __asm +S #endif +S #ifndef __INLINE +S #define __INLINE inline +S #endif +S #ifndef __STATIC_INLINE +S #define __STATIC_INLINE static inline +S #endif +S #ifndef __STATIC_FORCEINLINE +S #define __STATIC_FORCEINLINE __STATIC_INLINE +S #endif +S #ifndef __NO_RETURN +S #define __NO_RETURN __attribute__((noreturn)) +S #endif +S #ifndef __USED +S #define __USED __attribute__((used)) +S #endif +S #ifndef __WEAK +S #define __WEAK __attribute__((weak)) +S #endif +S #ifndef __PACKED +S #define __PACKED __packed__ +S #endif +S #ifndef __PACKED_STRUCT +S #define __PACKED_STRUCT struct __packed__ +S #endif +S #ifndef __PACKED_UNION +S #define __PACKED_UNION union __packed__ +S #endif +S #ifndef __UNALIGNED_UINT32 /* deprecated */ +S struct __packed__ T_UINT32 { uint32_t v; }; +S #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +S #endif +S #ifndef __UNALIGNED_UINT16_WRITE +S __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +S #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT16_READ +S __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +S #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __UNALIGNED_UINT32_WRITE +S __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +S #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT32_READ +S __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +S #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __ALIGNED +S #define __ALIGNED(x) __align(x) +S #endif +S #ifndef __RESTRICT +S #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. +S #define __RESTRICT +S #endif +S +S +S/* +S * COSMIC Compiler +S */ +S#elif defined ( __CSMC__ ) +S #include +S +S #ifndef __ASM +S #define __ASM _asm +S #endif +S #ifndef __INLINE +S #define __INLINE inline +S #endif +S #ifndef __STATIC_INLINE +S #define __STATIC_INLINE static inline +S #endif +S #ifndef __STATIC_FORCEINLINE +S #define __STATIC_FORCEINLINE __STATIC_INLINE +S #endif +S #ifndef __NO_RETURN +S // NO RETURN is automatically detected hence no warning here +S #define __NO_RETURN +S #endif +S #ifndef __USED +S #warning No compiler specific solution for __USED. __USED is ignored. +S #define __USED +S #endif +S #ifndef __WEAK +S #define __WEAK __weak +S #endif +S #ifndef __PACKED +S #define __PACKED @packed +S #endif +S #ifndef __PACKED_STRUCT +S #define __PACKED_STRUCT @packed struct +S #endif +S #ifndef __PACKED_UNION +S #define __PACKED_UNION @packed union +S #endif +S #ifndef __UNALIGNED_UINT32 /* deprecated */ +S @packed struct T_UINT32 { uint32_t v; }; +S #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +S #endif +S #ifndef __UNALIGNED_UINT16_WRITE +S __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +S #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT16_READ +S __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +S #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __UNALIGNED_UINT32_WRITE +S __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +S #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT32_READ +S __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +S #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __ALIGNED +S #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. +S #define __ALIGNED(x) +S #endif +S #ifndef __RESTRICT +S #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. +S #define __RESTRICT +S #endif +S +S +S#else +S #error Unknown compiler. +N#endif +N +N +N#endif /* __CMSIS_COMPILER_H */ +N +L 116 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h" 2 +N +N +N#ifdef __cplusplus +S} +N#endif +N +N#endif /* __CORE_CM0_H_GENERIC */ +N +N#ifndef __CMSIS_GENERIC +N +N#ifndef __CORE_CM0_H_DEPENDANT +N#define __CORE_CM0_H_DEPENDANT +N +N#ifdef __cplusplus +S extern "C" { +N#endif +N +N/* check device defines and use defaults */ +N#if defined __CHECK_DEVICE_DEFINES +X#if 0L +S #ifndef __CM0_REV +S #define __CM0_REV 0x0000U +S #warning "__CM0_REV not defined in device header file; using default!" +S #endif +S +S #ifndef __NVIC_PRIO_BITS +S #define __NVIC_PRIO_BITS 2U +S #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +S #endif +S +S #ifndef __Vendor_SysTickConfig +S #define __Vendor_SysTickConfig 0U +S #warning "__Vendor_SysTickConfig not defined in device header file; using default!" +S #endif +N#endif +N +N/* IO definitions (access restrictions to peripheral registers) */ +N/** +N \defgroup CMSIS_glob_defs CMSIS Global Defines +N +N IO Type Qualifiers are used +N \li to specify the access to peripheral variables. +N \li for automatic generation of peripheral register debug information. +N*/ +N#ifdef __cplusplus +S #define __I volatile /*!< Defines 'read only' permissions */ +N#else +N #define __I volatile const /*!< Defines 'read only' permissions */ +N#endif +N#define __O volatile /*!< Defines 'write only' permissions */ +N#define __IO volatile /*!< Defines 'read / write' permissions */ +N +N/* following defines should be used for structure members */ +N#define __IM volatile const /*! Defines 'read only' structure member permissions */ +N#define __OM volatile /*! Defines 'write only' structure member permissions */ +N#define __IOM volatile /*! Defines 'read / write' structure member permissions */ +N +N/*@} end of group Cortex_M0 */ +N +N +N +N/******************************************************************************* +N * Register Abstraction +N Core Register contain: +N - Core Register +N - Core NVIC Register +N - Core SCB Register +N - Core SysTick Register +N ******************************************************************************/ +N/** +N \defgroup CMSIS_core_register Defines and Type Definitions +N \brief Type definitions and defines for Cortex-M processor based devices. +N*/ +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_CORE Status and Control Registers +N \brief Core Register type definitions. +N @{ +N */ +N +N/** +N \brief Union type to access the Application Program Status Register (APSR). +N */ +Ntypedef union +N{ +N struct +N { +N uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ +N uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ +N uint32_t C:1; /*!< bit: 29 Carry condition code flag */ +N uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ +N uint32_t N:1; /*!< bit: 31 Negative condition code flag */ +N } b; /*!< Structure used for bit access */ +N uint32_t w; /*!< Type used for word access */ +N} APSR_Type; +N +N/* APSR Register Definitions */ +N#define APSR_N_Pos 31U /*!< APSR: N Position */ +N#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ +N +N#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +N#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ +N +N#define APSR_C_Pos 29U /*!< APSR: C Position */ +N#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ +N +N#define APSR_V_Pos 28U /*!< APSR: V Position */ +N#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ +N +N +N/** +N \brief Union type to access the Interrupt Program Status Register (IPSR). +N */ +Ntypedef union +N{ +N struct +N { +N uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +N uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ +N } b; /*!< Structure used for bit access */ +N uint32_t w; /*!< Type used for word access */ +N} IPSR_Type; +N +N/* IPSR Register Definitions */ +N#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +N#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ +N +N +N/** +N \brief Union type to access the Special-Purpose Program Status Registers (xPSR). +N */ +Ntypedef union +N{ +N struct +N { +N uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +N uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +N uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ +N uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ +N uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ +N uint32_t C:1; /*!< bit: 29 Carry condition code flag */ +N uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ +N uint32_t N:1; /*!< bit: 31 Negative condition code flag */ +N } b; /*!< Structure used for bit access */ +N uint32_t w; /*!< Type used for word access */ +N} xPSR_Type; +N +N/* xPSR Register Definitions */ +N#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +N#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ +N +N#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +N#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ +N +N#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +N#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ +N +N#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +N#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ +N +N#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +N#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ +N +N#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +N#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ +N +N +N/** +N \brief Union type to access the Control Registers (CONTROL). +N */ +Ntypedef union +N{ +N struct +N { +N uint32_t _reserved0:1; /*!< bit: 0 Reserved */ +N uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ +N uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ +N } b; /*!< Structure used for bit access */ +N uint32_t w; /*!< Type used for word access */ +N} CONTROL_Type; +N +N/* CONTROL Register Definitions */ +N#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +N#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ +N +N/*@} end of group CMSIS_CORE */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) +N \brief Type definitions for the NVIC Registers +N @{ +N */ +N +N/** +N \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). +N */ +Ntypedef struct +N{ +N __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ +X volatile uint32_t ISER[1U]; +N uint32_t RESERVED0[31U]; +N __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ +X volatile uint32_t ICER[1U]; +N uint32_t RESERVED1[31U]; +N __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ +X volatile uint32_t ISPR[1U]; +N uint32_t RESERVED2[31U]; +N __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ +X volatile uint32_t ICPR[1U]; +N uint32_t RESERVED3[31U]; +N uint32_t RESERVED4[64U]; +N __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +X volatile uint32_t IP[8U]; +N} NVIC_Type; +N +N/*@} end of group CMSIS_NVIC */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_SCB System Control Block (SCB) +N \brief Type definitions for the System Control Block Registers +N @{ +N */ +N +N/** +N \brief Structure type to access the System Control Block (SCB). +N */ +Ntypedef struct +N{ +N __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ +X volatile const uint32_t CPUID; +N __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +X volatile uint32_t ICSR; +N uint32_t RESERVED0; +N __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ +X volatile uint32_t AIRCR; +N __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ +X volatile uint32_t SCR; +N __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ +X volatile uint32_t CCR; +N uint32_t RESERVED1; +N __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ +X volatile uint32_t SHP[2U]; +N __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +X volatile uint32_t SHCSR; +N} SCB_Type; +N +N/* SCB CPUID Register Definitions */ +N#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +N#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +N +N#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +N#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +N +N#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +N#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ +N +N#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +N#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +N +N#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +N#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ +N +N/* SCB Interrupt Control State Register Definitions */ +N#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +N#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ +N +N#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +N#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ +N +N#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +N#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ +N +N#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +N#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ +N +N#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +N#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ +N +N#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +N#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ +N +N#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +N#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ +N +N#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +N#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ +N +N#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +N#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ +N +N/* SCB Application Interrupt and Reset Control Register Definitions */ +N#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +N#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ +N +N#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +N#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ +N +N#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +N#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +N +N#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +N#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ +N +N#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +N#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ +N +N/* SCB System Control Register Definitions */ +N#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +N#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ +N +N#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +N#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ +N +N#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +N#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ +N +N/* SCB Configuration Control Register Definitions */ +N#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +N#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ +N +N#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +N#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ +N +N/* SCB System Handler Control and State Register Definitions */ +N#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +N#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ +N +N/*@} end of group CMSIS_SCB */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_SysTick System Tick Timer (SysTick) +N \brief Type definitions for the System Timer Registers. +N @{ +N */ +N +N/** +N \brief Structure type to access the System Timer (SysTick). +N */ +Ntypedef struct +N{ +N __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ +X volatile uint32_t CTRL; +N __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ +X volatile uint32_t LOAD; +N __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ +X volatile uint32_t VAL; +N __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +X volatile const uint32_t CALIB; +N} SysTick_Type; +N +N/* SysTick Control / Status Register Definitions */ +N#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +N#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ +N +N#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +N#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ +N +N#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +N#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ +N +N#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +N#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ +N +N/* SysTick Reload Register Definitions */ +N#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +N#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ +N +N/* SysTick Current Register Definitions */ +N#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +N#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ +N +N/* SysTick Calibration Register Definitions */ +N#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +N#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ +N +N#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +N#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ +N +N#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +N#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ +N +N/*@} end of group CMSIS_SysTick */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) +N \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. +N Therefore they are not covered by the Cortex-M0 header file. +N @{ +N */ +N/*@} end of group CMSIS_CoreDebug */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_core_bitfield Core register bit field macros +N \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). +N @{ +N */ +N +N/** +N \brief Mask and shift a bit field value for use in a register bit range. +N \param[in] field Name of the register bit field. +N \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. +N \return Masked and shifted value. +N*/ +N#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) +N +N/** +N \brief Mask and shift a register value to extract a bit filed value. +N \param[in] field Name of the register bit field. +N \param[in] value Value of register. This parameter is interpreted as an uint32_t type. +N \return Masked and shifted bit field value. +N*/ +N#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) +N +N/*@} end of group CMSIS_core_bitfield */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_core_base Core Definitions +N \brief Definitions for base addresses, unions, and structures. +N @{ +N */ +N +N/* Memory mapping of Core Hardware */ +N#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +N#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +N#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +N#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +N +N#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +N#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +N#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +N +N +N/*@} */ +N +N +N +N/******************************************************************************* +N * Hardware Abstraction Layer +N Core Function Interface contains: +N - Core NVIC Functions +N - Core SysTick Functions +N - Core Register Access Functions +N ******************************************************************************/ +N/** +N \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +N*/ +N +N +N +N/* ########################## NVIC functions #################################### */ +N/** +N \ingroup CMSIS_Core_FunctionInterface +N \defgroup CMSIS_Core_NVICFunctions NVIC Functions +N \brief Functions that manage interrupts and exceptions via the NVIC. +N @{ +N */ +N +N#ifdef CMSIS_NVIC_VIRTUAL +S #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +S #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +S #endif +S #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +N#else +N #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +N #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +N #define NVIC_EnableIRQ __NVIC_EnableIRQ +N #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +N #define NVIC_DisableIRQ __NVIC_DisableIRQ +N #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +N #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +N #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +N/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ +N #define NVIC_SetPriority __NVIC_SetPriority +N #define NVIC_GetPriority __NVIC_GetPriority +N #define NVIC_SystemReset __NVIC_SystemReset +N#endif /* CMSIS_NVIC_VIRTUAL */ +N +N#ifdef CMSIS_VECTAB_VIRTUAL +S #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +S #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +S #endif +S #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +N#else +N #define NVIC_SetVector __NVIC_SetVector +N #define NVIC_GetVector __NVIC_GetVector +N#endif /* (CMSIS_VECTAB_VIRTUAL) */ +N +N#define NVIC_USER_IRQ_OFFSET 16 +N +N +N/* The following EXC_RETURN values are saved the LR on exception entry */ +N#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +N#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +N#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +N +N +N/* Interrupt Priorities are WORD accessible only under Armv6-M */ +N/* The following MACROS handle generation of the register offset and byte masks */ +N#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +N#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +N#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) +N +N#define __NVIC_SetPriorityGrouping(X) (void)(X) +N#define __NVIC_GetPriorityGrouping() (0U) +N +N/** +N \brief Enable Interrupt +N \details Enables a device specific interrupt in the NVIC interrupt controller. +N \param [in] IRQn Device specific interrupt number. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +Xstatic __inline void __NVIC_EnableIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +N } +N} +N +N +N/** +N \brief Get Interrupt Enable status +N \details Returns a device specific interrupt enable status from the NVIC interrupt controller. +N \param [in] IRQn Device specific interrupt number. +N \return 0 Interrupt is not enabled. +N \return 1 Interrupt is enabled. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +Xstatic __inline uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +X return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +N } +N else +N { +N return(0U); +N } +N} +N +N +N/** +N \brief Disable Interrupt +N \details Disables a device specific interrupt in the NVIC interrupt controller. +N \param [in] IRQn Device specific interrupt number. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +Xstatic __inline void __NVIC_DisableIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +N __DSB(); +X do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); +N __ISB(); +X do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U); +N } +N} +N +N +N/** +N \brief Get Pending Interrupt +N \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. +N \param [in] IRQn Device specific interrupt number. +N \return 0 Interrupt status is not pending. +N \return 1 Interrupt status is pending. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +Xstatic __inline uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +X return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +N } +N else +N { +N return(0U); +N } +N} +N +N +N/** +N \brief Set Pending Interrupt +N \details Sets the pending bit of a device specific interrupt in the NVIC pending register. +N \param [in] IRQn Device specific interrupt number. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +Xstatic __inline void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +N } +N} +N +N +N/** +N \brief Clear Pending Interrupt +N \details Clears the pending bit of a device specific interrupt in the NVIC pending register. +N \param [in] IRQn Device specific interrupt number. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +Xstatic __inline void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +N } +N} +N +N +N/** +N \brief Set Interrupt Priority +N \details Sets the priority of a device specific interrupt or a processor exception. +N The interrupt number can be positive to specify a device specific interrupt, +N or negative to specify a processor exception. +N \param [in] IRQn Interrupt number. +N \param [in] priority Priority to set. +N \note The priority cannot be set for every processor exception. +N */ +N__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +Xstatic __inline void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] = ((uint32_t)(((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | +N (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); +X (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); +N } +N else +N { +N SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | +X ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] = ((uint32_t)(((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | +N (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); +X (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); +N } +N} +N +N +N/** +N \brief Get Interrupt Priority +N \details Reads the priority of a device specific interrupt or a processor exception. +N The interrupt number can be positive to specify a device specific interrupt, +N or negative to specify a processor exception. +N \param [in] IRQn Interrupt number. +N \return Interrupt Priority. +N Value is aligned automatically to the implemented priority bits of the microcontroller. +N */ +N__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +Xstatic __inline uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +N{ +N +N if ((int32_t)(IRQn) >= 0) +N { +N return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); +X return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[ ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); +N } +N else +N { +N return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); +X return((uint32_t)(((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); +N } +N} +N +N +N/** +N \brief Encode Priority +N \details Encodes the priority for an interrupt with the given priority group, +N preemptive priority value, and subpriority value. +N In case of a conflict between priority grouping and available +N priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +N \param [in] PriorityGroup Used priority group. +N \param [in] PreemptPriority Preemptive priority value (starting from 0). +N \param [in] SubPriority Subpriority value (starting from 0). +N \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). +N */ +N__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +Xstatic __inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +N{ +N uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ +N uint32_t PreemptPriorityBits; +N uint32_t SubPriorityBits; +N +N PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); +X PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); +N SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); +X SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); +N +N return ( +N ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | +N ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) +N ); +N} +N +N +N/** +N \brief Decode Priority +N \details Decodes an interrupt priority value with a given priority group to +N preemptive priority value and subpriority value. +N In case of a conflict between priority grouping and available +N priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. +N \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). +N \param [in] PriorityGroup Used priority group. +N \param [out] pPreemptPriority Preemptive priority value (starting from 0). +N \param [out] pSubPriority Subpriority value (starting from 0). +N */ +N__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +Xstatic __inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +N{ +N uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ +N uint32_t PreemptPriorityBits; +N uint32_t SubPriorityBits; +N +N PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); +X PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); +N SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); +X SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); +N +N *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); +N *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +N} +N +N +N +N/** +N \brief Set Interrupt Vector +N \details Sets an interrupt vector in SRAM based interrupt vector table. +N The interrupt number can be positive to specify a device specific interrupt, +N or negative to specify a processor exception. +N Address 0 must be mapped to SRAM. +N \param [in] IRQn Interrupt number +N \param [in] vector Address of interrupt handler function +N */ +N__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +Xstatic __inline void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +N{ +N uint32_t vectors = 0x0U; +N (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; +X (* (int *) (vectors + ((int32_t)IRQn + 16) * 4)) = vector; +N} +N +N +N/** +N \brief Get Interrupt Vector +N \details Reads an interrupt vector from interrupt vector table. +N The interrupt number can be positive to specify a device specific interrupt, +N or negative to specify a processor exception. +N \param [in] IRQn Interrupt number. +N \return Address of interrupt handler function +N */ +N__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +Xstatic __inline uint32_t __NVIC_GetVector(IRQn_Type IRQn) +N{ +N uint32_t vectors = 0x0U; +N return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +X return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + 16) * 4)); +N} +N +N +N/** +N \brief System Reset +N \details Initiates a system reset request to reset the MCU. +N */ +N__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +X__declspec(noreturn) static __inline void __NVIC_SystemReset(void) +N{ +N __DSB(); /* Ensure all outstanding memory accesses included +X do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); +N buffered write are completed before reset */ +N SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | +X ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR = ((0x5FAUL << 16U) | +N SCB_AIRCR_SYSRESETREQ_Msk); +X (1UL << 2U)); +N __DSB(); /* Ensure completion of memory access */ +X do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); +N +N for(;;) /* wait until reset */ +N { +N __NOP(); +X __nop(); +N } +N} +N +N/*@} end of CMSIS_Core_NVICFunctions */ +N +N +N/* ########################## FPU functions #################################### */ +N/** +N \ingroup CMSIS_Core_FunctionInterface +N \defgroup CMSIS_Core_FpuFunctions FPU Functions +N \brief Function that provides FPU type. +N @{ +N */ +N +N/** +N \brief get FPU type +N \details returns the FPU type +N \returns +N - \b 0: No FPU +N - \b 1: Single precision FPU +N - \b 2: Double + Single precision FPU +N */ +N__STATIC_INLINE uint32_t SCB_GetFPUType(void) +Xstatic __inline uint32_t SCB_GetFPUType(void) +N{ +N return 0U; /* No FPU */ +N} +N +N +N/*@} end of CMSIS_Core_FpuFunctions */ +N +N +N +N/* ################################## SysTick function ############################################ */ +N/** +N \ingroup CMSIS_Core_FunctionInterface +N \defgroup CMSIS_Core_SysTickFunctions SysTick Functions +N \brief Functions that configure the System. +N @{ +N */ +N +N#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) +X#if 1L && (0U == 0U) +N +N/** +N \brief System Tick Configuration +N \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. +N Counter is in free running mode to generate periodic interrupts. +N \param [in] ticks Number of ticks between two interrupts. +N \return 0 Function succeeded. +N \return 1 Function failed. +N \note When the variable __Vendor_SysTickConfig is set to 1, then the +N function SysTick_Config is not included. In this case, the file device.h +N must contain a vendor-specific implementation of this function. +N */ +N__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +Xstatic __inline uint32_t SysTick_Config(uint32_t ticks) +N{ +N if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) +X if ((ticks - 1UL) > (0xFFFFFFUL )) +N { +N return (1UL); /* Reload value impossible */ +N } +N +N SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ +X ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->LOAD = (uint32_t)(ticks - 1UL); +N NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ +X __NVIC_SetPriority (SysTick_IRQn, (1UL << 2U) - 1UL); +N SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ +X ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->VAL = 0UL; +N SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | +X ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL = (1UL << 2U) | +N SysTick_CTRL_TICKINT_Msk | +X (1UL << 1U) | +N SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ +X (1UL ); +N return (0UL); /* Function successful */ +N} +N +N#endif +N +N/*@} end of CMSIS_Core_SysTickFunctions */ +N +N +N +N +N#ifdef __cplusplus +S} +N#endif +N +N#endif /* __CORE_CM0_H_DEPENDANT */ +N +N#endif /* __CMSIS_GENERIC */ +L 122 "..\..\src\sdk\include\M0\ArmCM0.h" 2 +N#include "system_ARMCM0.h" /* System Header */ +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include\system_ARMCM0.h" 1 +N/**************************************************************************//** +N * @file system_ARMCM0.h +N * @brief CMSIS Device System Header File for +N * ARMCM0 Device +N * @version V5.3.1 +N * @date 09. July 2018 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#ifndef SYSTEM_ARMCM0_H +N#define SYSTEM_ARMCM0_H +N +N#ifdef __cplusplus +Sextern "C" { +N#endif +N +Nextern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +N +N +N/** +N \brief Setup the microcontroller system. +N +N Initialize the System and update the SystemCoreClock variable. +N */ +Nextern void SystemInit (void); +N +N +N/** +N \brief Update SystemCoreClock variable. +N +N Updates the SystemCoreClock with current core Clock retrieved from cpu registers. +N */ +Nextern void SystemCoreClockUpdate (void); +N +N#ifdef __cplusplus +S} +N#endif +N +N#endif /* SYSTEM_ARMCM0_H */ +L 123 "..\..\src\sdk\include\M0\ArmCM0.h" 2 +N +N/* -------- End of section using anonymous unions and disabling warnings -------- */ +N#if defined (__CC_ARM) +X#if 1L +N#pragma pop +N#elif defined (__ICCARM__) +X#elif 0L +S/* leave anonymous unions enabled */ +S#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +S#pragma clang diagnostic pop +S#elif defined (__GNUC__) +S/* anonymous unions are enabled by default */ +S#elif defined (__TMS470__) +S/* anonymous unions are enabled by default */ +S#elif defined (__TASKING__) +S#pragma warning restore +S#elif defined (__CSMC__) +S/* anonymous unions are enabled by default */ +S#else +S#warning Not supported compiler type +N#endif +N +N/* In HS mode and when the DMA is used, all variables and data structures dealing +N with the DMA during the transaction process should be 4-bytes aligned */ +N#define DMA_WORD_ALIGN_EN +N#ifdef DMA_WORD_ALIGN_EN +N#if defined (__GNUC__) /* GNU Compiler */ +X#if 1L +N#define __ALIGN_END __attribute__ ((aligned (4))) +N#define __ALIGN_BEGIN +N#else +S#define __ALIGN_END +S#if defined (__CC_ARM) /* ARM Compiler */ +S#define __ALIGN_BEGIN __align(4) +S#elif defined (__ICCARM__) /* IAR Compiler */ +S#define __ALIGN_BEGIN +S#elif defined (__TASKING__) /* TASKING Compiler */ +S#define __ALIGN_BEGIN __align(4) +S#endif /* __CC_ARM */ +N#endif /* __GNUC__ */ +N#else +S +S#define __ALIGN_BEGIN +S#define __ALIGN_END +S +S#define __ALIGN_END_1 __attribute__ ((aligned (1))) +N#endif /* DMA_WORD_ALIGN_EN */ +N +N/* __packed keyword used to decrease the data type alignment to 1-byte */ +N#if defined (__CC_ARM) /* ARM Compiler */ +X#if 1L +N#define __packed __packed +N#elif defined (__ICCARM__) /* IAR Compiler */ +X#elif 0L +S#define __packed __packed +S#elif defined ( __GNUC__ ) /* GNU Compiler */ +S#define __packed __attribute__ ((__packed__)) +S#define __weak __attribute__((weak)) +S#elif defined (__TASKING__) /* TASKING Compiler */ +S#define __packed __unaligned +N#endif /* __CC_ARM */ +N +N#ifdef __cplusplus +S} +N#endif +N +N#endif /* ARMCM0_H */ +L 21 "..\..\src\common\tau_log.h" 2 +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N#ifdef LOG_TAG +S#undef LOG_TAG +N#endif +N#define LOG_TAG "tau_log" +N#define LOG_CURREN_LEVEL kLOG_LEVEL_DBG /* 配置打印等级 TODO:每个模块可配置打印等级 */ +N#define LOG_BUF_SIZE (256) /* 配置打印缓存的大小 */ +N +N/* +N * Using the following three macros for conveniently logging. +N */ +N#define TAU_LOGD(format,...) \ +N do { \ +N tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); \ +N } while (0) +X#define TAU_LOGD(format,...) do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); } while (0) +N +N#define TAU_LOGI(format,...) \ +N do { \ +N tau_log_printf(kLOG_LEVEL_INF, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); \ +N } while (0) +X#define TAU_LOGI(format,...) do { tau_log_printf(kLOG_LEVEL_INF, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); } while (0) +N +N#define TAU_LOGE(format,...) \ +N do { \ +N tau_log_printf(kLOG_LEVEL_ERR, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); \ +N } while (0) +X#define TAU_LOGE(format,...) do { tau_log_printf(kLOG_LEVEL_ERR, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); } while (0) +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/** +N* @brief log打印等级枚举 +N* +N*/ +Ntypedef enum +N{ +N kLOG_LEVEL_DBG = 0, +N kLOG_LEVEL_INF, +N kLOG_LEVEL_ERR, +N kLOG_LEVEL_NONE /* 不打印任何参数 */ +N} log_level_e; +N +N/** +N* @brief log打印端口枚举 +N* +N*/ +Ntypedef enum +N{ +N LOG_PORT_UART0, /* 使用串口输出打印 */ +N LOG_PORT_UART1, /* 使用串口输出打印 */ +N LOG_PORT_SWD, /* 使用swd输出打印 */ +N LOG_PORT_UNKNOWN +N} log_port_e; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N/** +N* @brief 初始化log系统 +N* @param baud_rate 波特率 +N* @param log_port 打印端口选择 +N* @retval none +N*/ +Nvoid tau_log_init(uint32_t baud_rate, log_port_e log_port); +N +N/** +N* @brief 初始化log系统 +N* @param baud_rate 波特率 +N* @param log_port 打印端口选择 +N* @retval none +N*/ +Nvoid tau_log_printf(log_level_e log_lv, const char *fmt, ...); +N +N#endif +L 18 "..\..\src\sdk\include\hal_system.h" 2 +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/** +N* @brief 系统时钟配置 +N*/ +Ntypedef enum +N{ +N HAL_SYSCLK_80M = 80000000, +N HAL_SYSCLK_100M = 100000000, +N HAL_SYSCLK_150M = 150000000 +N} hal_system_clk_e; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N +N/** +N* @brief system 初始化 +N* @param sysclk:系统时钟 +N* @retval none +N*/ +Nvoid hal_system_init(hal_system_clk_e sysclk); +N +N/** +N* @brief mcu进入idle模式,等待中断唤醒 +N* @param disable_systick: 进入idle时是否关闭systick(退出idle 恢复systick) +N* @retval none +N*/ +Nvoid hal_system_idle_mode(bool disable_systick); +Xvoid hal_system_idle_mode(_Bool disable_systick); +N +N/** +N* @brief 注册systick回调函数 +N* @param cb_func：回调函数地址 +N* @retval 无 +N*/ +Nvoid hal_system_register_systick_cb(fcb_type cb_func); +N +N/** +N* @brief 启动sys tickt +N* @param ms: sys tickt 间隔, 范围1-10ms +N* @retval true/false +N*/ +Nbool hal_system_enable_systick(uint8_t ms); +X_Bool hal_system_enable_systick(uint8_t ms); +N +N/** +N* @brief 获取systickt +N* @param none +N* @retval 当前systickt值 +N*/ +Nbool hal_system_disable_systick(void); +X_Bool hal_system_disable_systick(void); +N +N/** +N* @brief 获取systickt +N* @param none +N* @retval 当前systickt值 +N*/ +Nuint32_t hal_system_get_tick(void); +N +N/** +N* @brief reset chip +N* @param none +N* @retval none +N*/ +Nvoid hal_system_reset_chip(void); +N +N/** +N* @brief 获取上位机设置的debug state(debug only) +N* @param none +N* @retval debug state +N*/ +Nuint32_t hal_system_get_debug_state(void); +N +N/** +N* @brief clear debug state(debug only) +N* @param none +N* @retval none +N*/ +Nvoid hal_system_clear_debug_state(void); +N +N/** +N* @brief 更新MCU时钟 +N* @param sysclk:系统时钟 +N* @retval true/false +N*/ +Nbool hal_system_updata_sysclk(hal_system_clk_e sysclk); +X_Bool hal_system_updata_sysclk(hal_system_clk_e sysclk); +N +N#endif //__HAL_SYSTEM_H__ +L 12 "..\..\src\board\board.c" 2 +N#include "hal_gpio.h" +N#include "ArmCM0.h" +N#include "tau_log.h" +N +N/** +N* @brief 系统板级初始化,配置系统时钟,调试log输出 +N* @param none +N* @retval none +N*/ +Nvoid board_Init(void) +N{ +N /* system init ,配置MCU时钟 */ +N hal_system_init(HAL_SYSCLK_80M); +N +N /* 使用SWD口作为Debug Log输出,可配置成Uart方式 */ +N tau_log_init(115200, LOG_PORT_UART0); +N +N /* systick init,根据需要配置 */ +N //hal_system_enable_systick(1); +N} diff --git a/project/WL668/Listings/board.txt b/project/WL668/Listings/board.txt new file mode 100644 index 0000000..3d97ded --- /dev/null +++ b/project/WL668/Listings/board.txt @@ -0,0 +1,57 @@ +; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] +; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave --gnu -o.\objects\board.o --asm_dir=.\Listings\ --list_dir=.\Listings\ --depend=.\objects\board.d --cpu=Cortex-M0 --apcs=interwork -O0 --diag_suppress=9931 -I..\..\src -I..\..\src\board -I..\..\src\common -I..\..\src\sdk\include -I..\..\src\sdk\include\M0 -I..\..\src\app -I..\..\src\app\S8 -I..\..\src\app\touch -I..\..\src\app\module_demo -I..\..\src\app\P8P -I.\RTE\_WL668 -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include -D__MICROLIB -D__UVISION_VERSION=528 -D_RTE_ -DARMCM0 --omf_browse=.\objects\board.crf ..\..\src\board\board.c] + THUMB + + AREA ||i.board_Init||, CODE, READONLY, ALIGN=2 + + board_Init PROC +;;;20 */ +;;;21 void board_Init(void) +000000 b510 PUSH {r4,lr} +;;;22 { +;;;23 /* system init ,配置MCU时钟 */ +;;;24 hal_system_init(HAL_SYSCLK_80M); +000002 4804 LDR r0,|L1.20| +000004 f7fffffe BL hal_system_init +;;;25 +;;;26 /* 使用SWD口作为Debug Log输出,可配置成Uart方式 */ +;;;27 tau_log_init(115200, LOG_PORT_UART0); +000008 2100 MOVS r1,#0 +00000a 20e1 MOVS r0,#0xe1 +00000c 0240 LSLS r0,r0,#9 +00000e f7fffffe BL tau_log_init +;;;28 +;;;29 /* systick init,根据需要配置 */ +;;;30 //hal_system_enable_systick(1); +;;;31 } +000012 bd10 POP {r4,pc} + ENDP + + |L1.20| + DCD 0x04c4b400 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\src\\board\\board.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___7_board_c_bcd01269____REV16| +#line 467 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" +|__asm___7_board_c_bcd01269____REV16| PROC +#line 468 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___7_board_c_bcd01269____REVSH| +#line 482 +|__asm___7_board_c_bcd01269____REVSH| PROC +#line 483 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/project/WL668/Listings/main._ip b/project/WL668/Listings/main._ip new file mode 100644 index 0000000..4da327d --- /dev/null +++ b/project/WL668/Listings/main._ip @@ -0,0 +1,6 @@ +..\..\src\app\main.c -E --c99 --gnu -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I ..\..\src -I ..\..\src\board -I ..\..\src\common -I ..\..\src\sdk\include -I ..\..\src\sdk\include\M0 -I ..\..\src\app -I ..\..\src\app\S8 -I ..\..\src\app\touch -I ..\..\src\app\module_demo -I ..\..\src\app\P8P +-I.\RTE\_WL668 +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include +-D__UVISION_VERSION="528" -D_RTE_ -DARMCM0 +-o .\listings\main.i --list_dir ".\\Listings\\" --list \ No newline at end of file diff --git a/project/WL668/Listings/main.i b/project/WL668/Listings/main.i new file mode 100644 index 0000000..3ea14d6 --- /dev/null +++ b/project/WL668/Listings/main.i @@ -0,0 +1,6424 @@ +# 1 "..\\..\\src\\app\\main.c" +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdio.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 47 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdio.h" + + + + + + + typedef unsigned int size_t; + + + + + + + + + + + + + + + + + typedef struct __va_list __va_list; + + + + + + + + + + + + + + + + +typedef struct __fpos_t_struct { + unsigned __int64 __pos; + + + + + + struct { + unsigned int __state1, __state2; + } __mbstate; +} fpos_t; + + + + + + + + + + +typedef struct __FILE FILE; + + + + + + + + + +# 136 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdio.h" + + +extern FILE __stdin, __stdout, __stderr; +extern FILE *__aeabi_stdin, *__aeabi_stdout, *__aeabi_stderr; + +# 166 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdio.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) int remove(const char * ) __attribute__((__nonnull__(1))); + + + + + + + +extern __declspec(__nothrow) int rename(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + +extern __declspec(__nothrow) FILE *tmpfile(void); + + + + + + +extern __declspec(__nothrow) char *tmpnam(char * ); + + + + + + + + + + + + + + +extern __declspec(__nothrow) int fclose(FILE * ) __attribute__((__nonnull__(1))); + + + + + + + + + +extern __declspec(__nothrow) int fflush(FILE * ); + + + + + + + + + +extern __declspec(__nothrow) FILE *fopen(const char * __restrict , + const char * __restrict ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) FILE *freopen(const char * __restrict , + const char * __restrict , + FILE * __restrict ) __attribute__((__nonnull__(2,3))); + + + + + + + + + + +extern __declspec(__nothrow) void setbuf(FILE * __restrict , + char * __restrict ) __attribute__((__nonnull__(1))); + + + + + + +extern __declspec(__nothrow) int setvbuf(FILE * __restrict , + char * __restrict , + int , size_t ) __attribute__((__nonnull__(1))); + + + + + + + + + + + + + + + + + +#pragma __printf_args +extern __declspec(__nothrow) int fprintf(FILE * __restrict , + const char * __restrict , ...) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + + + + + +#pragma __printf_args +extern __declspec(__nothrow) int _fprintf(FILE * __restrict , + const char * __restrict , ...) __attribute__((__nonnull__(1,2))); + + + + + +#pragma __printf_args +extern __declspec(__nothrow) int printf(const char * __restrict , ...) __attribute__((__nonnull__(1))); + + + + + + +#pragma __printf_args +extern __declspec(__nothrow) int _printf(const char * __restrict , ...) __attribute__((__nonnull__(1))); + + + + + +#pragma __printf_args +extern __declspec(__nothrow) int sprintf(char * __restrict , const char * __restrict , ...) __attribute__((__nonnull__(1,2))); + + + + + + + + +#pragma __printf_args +extern __declspec(__nothrow) int _sprintf(char * __restrict , const char * __restrict , ...) __attribute__((__nonnull__(1,2))); + + + + + + +#pragma __printf_args +extern __declspec(__nothrow) int __ARM_snprintf(char * __restrict , size_t , + const char * __restrict , ...) __attribute__((__nonnull__(3))); + + +#pragma __printf_args +extern __declspec(__nothrow) int snprintf(char * __restrict , size_t , + const char * __restrict , ...) __attribute__((__nonnull__(3))); + + + + + + + + + + + + + + + + + + +#pragma __printf_args +extern __declspec(__nothrow) int _snprintf(char * __restrict , size_t , + const char * __restrict , ...) __attribute__((__nonnull__(3))); + + + + + +#pragma __scanf_args +extern __declspec(__nothrow) int fscanf(FILE * __restrict , + const char * __restrict , ...) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#pragma __scanf_args +extern __declspec(__nothrow) int _fscanf(FILE * __restrict , + const char * __restrict , ...) __attribute__((__nonnull__(1,2))); + + + + + +#pragma __scanf_args +extern __declspec(__nothrow) int scanf(const char * __restrict , ...) __attribute__((__nonnull__(1))); + + + + + + + + +#pragma __scanf_args +extern __declspec(__nothrow) int _scanf(const char * __restrict , ...) __attribute__((__nonnull__(1))); + + + + + +#pragma __scanf_args +extern __declspec(__nothrow) int sscanf(const char * __restrict , + const char * __restrict , ...) __attribute__((__nonnull__(1,2))); + + + + + + + + + + +#pragma __scanf_args +extern __declspec(__nothrow) int _sscanf(const char * __restrict , + const char * __restrict , ...) __attribute__((__nonnull__(1,2))); + + + + + + + +extern __declspec(__nothrow) int vfscanf(FILE * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) int vscanf(const char * __restrict , __va_list) __attribute__((__nonnull__(1))); +extern __declspec(__nothrow) int vsscanf(const char * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); + +extern __declspec(__nothrow) int _vfscanf(FILE * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) int _vscanf(const char * __restrict , __va_list) __attribute__((__nonnull__(1))); +extern __declspec(__nothrow) int _vsscanf(const char * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) int __ARM_vsscanf(const char * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); + +extern __declspec(__nothrow) int vprintf(const char * __restrict , __va_list ) __attribute__((__nonnull__(1))); + + + + + + + +extern __declspec(__nothrow) int _vprintf(const char * __restrict , __va_list ) __attribute__((__nonnull__(1))); + + + + + +extern __declspec(__nothrow) int vfprintf(FILE * __restrict , + const char * __restrict , __va_list ) __attribute__((__nonnull__(1,2))); + + + + + + + + +extern __declspec(__nothrow) int vsprintf(char * __restrict , + const char * __restrict , __va_list ) __attribute__((__nonnull__(1,2))); + + + + + + + + +extern __declspec(__nothrow) int __ARM_vsnprintf(char * __restrict , size_t , + const char * __restrict , __va_list ) __attribute__((__nonnull__(3))); + +extern __declspec(__nothrow) int vsnprintf(char * __restrict , size_t , + const char * __restrict , __va_list ) __attribute__((__nonnull__(3))); + + + + + + + + + + +extern __declspec(__nothrow) int _vsprintf(char * __restrict , + const char * __restrict , __va_list ) __attribute__((__nonnull__(1,2))); + + + + + +extern __declspec(__nothrow) int _vfprintf(FILE * __restrict , + const char * __restrict , __va_list ) __attribute__((__nonnull__(1,2))); + + + + + +extern __declspec(__nothrow) int _vsnprintf(char * __restrict , size_t , + const char * __restrict , __va_list ) __attribute__((__nonnull__(3))); + + + + + + +#pragma __printf_args +extern __declspec(__nothrow) int asprintf(char ** , const char * __restrict , ...) __attribute__((__nonnull__(2))); +extern __declspec(__nothrow) int vasprintf(char ** , const char * __restrict , __va_list ) __attribute__((__nonnull__(2))); + +#pragma __printf_args +extern __declspec(__nothrow) int __ARM_asprintf(char ** , const char * __restrict , ...) __attribute__((__nonnull__(2))); +extern __declspec(__nothrow) int __ARM_vasprintf(char ** , const char * __restrict , __va_list ) __attribute__((__nonnull__(2))); + + + + + + + + + + + +extern __declspec(__nothrow) int fgetc(FILE * ) __attribute__((__nonnull__(1))); + + + + + + + + + +extern __declspec(__nothrow) char *fgets(char * __restrict , int , + FILE * __restrict ) __attribute__((__nonnull__(1,3))); + + + + + + + + + + + + +extern __declspec(__nothrow) int fputc(int , FILE * ) __attribute__((__nonnull__(2))); + + + + + + + + + +extern __declspec(__nothrow) int fputs(const char * __restrict , FILE * __restrict ) __attribute__((__nonnull__(1,2))); + + + + + + +extern __declspec(__nothrow) int getc(FILE * ) __attribute__((__nonnull__(1))); + + + + + + + + + + + + + + extern __declspec(__nothrow) int (getchar)(void); + + + + + + + + +extern __declspec(__nothrow) char *gets(char * ) __attribute__((__nonnull__(1))); + + + + + + + + + + + +extern __declspec(__nothrow) int putc(int , FILE * ) __attribute__((__nonnull__(2))); + + + + + + + + + + + + extern __declspec(__nothrow) int (putchar)(int ); + + + + + + +extern __declspec(__nothrow) int puts(const char * ) __attribute__((__nonnull__(1))); + + + + + + + +extern __declspec(__nothrow) int ungetc(int , FILE * ) __attribute__((__nonnull__(2))); + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) size_t fread(void * __restrict , + size_t , size_t , FILE * __restrict ) __attribute__((__nonnull__(1,4))); + + + + + + + + + + + + + + +extern __declspec(__nothrow) size_t __fread_bytes_avail(void * __restrict , + size_t , FILE * __restrict ) __attribute__((__nonnull__(1,3))); + + + + + + + + + + + + + + +extern __declspec(__nothrow) size_t fwrite(const void * __restrict , + size_t , size_t , FILE * __restrict ) __attribute__((__nonnull__(1,4))); + + + + + + + + + + +extern __declspec(__nothrow) int fgetpos(FILE * __restrict , fpos_t * __restrict ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + +extern __declspec(__nothrow) int fseek(FILE * , long int , int ) __attribute__((__nonnull__(1))); + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) int fsetpos(FILE * __restrict , const fpos_t * __restrict ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + +extern __declspec(__nothrow) long int ftell(FILE * ) __attribute__((__nonnull__(1))); + + + + + + + + + + + + + +extern __declspec(__nothrow) void rewind(FILE * ) __attribute__((__nonnull__(1))); + + + + + + + + +extern __declspec(__nothrow) void clearerr(FILE * ) __attribute__((__nonnull__(1))); + + + + + + + +extern __declspec(__nothrow) int feof(FILE * ) __attribute__((__nonnull__(1))); + + + + +extern __declspec(__nothrow) int ferror(FILE * ) __attribute__((__nonnull__(1))); + + + + +extern __declspec(__nothrow) void perror(const char * ); + + + + + + + + + + + + +extern __declspec(__nothrow) int _fisatty(FILE * ) __attribute__((__nonnull__(1))); + + + +extern __declspec(__nothrow) void __use_no_semihosting_swi(void); +extern __declspec(__nothrow) void __use_no_semihosting(void); + + + + + + + + + + + + + + + + + + +# 1021 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdio.h" + + + + + +# 2 "..\\..\\src\\app\\main.c" +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 38 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" + + + + + + + typedef unsigned int size_t; +# 54 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" + + + + +extern __declspec(__nothrow) void *memcpy(void * __restrict , + const void * __restrict , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + +extern __declspec(__nothrow) void *memmove(void * , + const void * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + +extern __declspec(__nothrow) char *strcpy(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); + + + + + + +extern __declspec(__nothrow) char *strncpy(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + +extern __declspec(__nothrow) char *strcat(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); + + + + + + +extern __declspec(__nothrow) char *strncat(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) int memcmp(const void * , const void * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + +extern __declspec(__nothrow) int strcmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + +extern __declspec(__nothrow) int strncmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + +extern __declspec(__nothrow) int strcasecmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + +extern __declspec(__nothrow) int strncasecmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + +extern __declspec(__nothrow) int strcoll(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + +extern __declspec(__nothrow) size_t strxfrm(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(2))); + + + + + + + + + + + + + + + + + +# 193 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) void *memchr(const void * , int , size_t ) __attribute__((__nonnull__(1))); + + + + + + + + + +# 209 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) char *strchr(const char * , int ) __attribute__((__nonnull__(1))); + + + + + + + + +extern __declspec(__nothrow) size_t strcspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + +# 232 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) char *strpbrk(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + + +# 247 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) char *strrchr(const char * , int ) __attribute__((__nonnull__(1))); + + + + + + + + + +extern __declspec(__nothrow) size_t strspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + +# 270 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) char *strstr(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + + + +extern __declspec(__nothrow) char *strtok(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(2))); +extern __declspec(__nothrow) char *_strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); + +extern __declspec(__nothrow) char *strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) void *memset(void * , int , size_t ) __attribute__((__nonnull__(1))); + + + + + +extern __declspec(__nothrow) char *strerror(int ); + + + + + + + +extern __declspec(__nothrow) size_t strlen(const char * ) __attribute__((__nonnull__(1))); + + + + + + +extern __declspec(__nothrow) size_t strlcpy(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) size_t strlcat(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) void _membitcpybl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpybb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpyhl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpyhb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpywl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpywb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovebl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovebb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovehl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovehb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovewl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovewb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 502 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" + + + + + +# 3 "..\\..\\src\\app\\main.c" +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdlib.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 54 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdlib.h" + + + + + + + typedef unsigned int size_t; +# 70 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdlib.h" + + + + + + + + + + + typedef unsigned short wchar_t; +# 91 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdlib.h" + +typedef struct div_t { int quot, rem; } div_t; + +typedef struct ldiv_t { long int quot, rem; } ldiv_t; + + +typedef struct lldiv_t { long long quot, rem; } lldiv_t; + + + +# 112 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdlib.h" + + + + + + + + + + + + +# 131 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdlib.h" + + + + +extern __declspec(__nothrow) int __aeabi_MB_CUR_MAX(void); + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) double atof(const char * ) __attribute__((__nonnull__(1))); + + + + + +extern __declspec(__nothrow) int atoi(const char * ) __attribute__((__nonnull__(1))); + + + + + +extern __declspec(__nothrow) long int atol(const char * ) __attribute__((__nonnull__(1))); + + + + + + +extern __declspec(__nothrow) long long atoll(const char * ) __attribute__((__nonnull__(1))); + + + + + + + +extern __declspec(__nothrow) double strtod(const char * __restrict , char ** __restrict ) __attribute__((__nonnull__(1))); + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) float strtof(const char * __restrict , char ** __restrict ) __attribute__((__nonnull__(1))); +extern __declspec(__nothrow) long double strtold(const char * __restrict , char ** __restrict ) __attribute__((__nonnull__(1))); + + + + +extern __declspec(__nothrow) long int strtol(const char * __restrict , + char ** __restrict , int ) __attribute__((__nonnull__(1))); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) unsigned long int strtoul(const char * __restrict , + char ** __restrict , int ) __attribute__((__nonnull__(1))); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) long long strtoll(const char * __restrict , + char ** __restrict , int ) + __attribute__((__nonnull__(1))); + + + + + + +extern __declspec(__nothrow) unsigned long long strtoull(const char * __restrict , + char ** __restrict , int ) + __attribute__((__nonnull__(1))); + + + + + + +extern __declspec(__nothrow) int rand(void); + + + + + + + + + +extern __declspec(__nothrow) void srand(unsigned int ); + + + + + + + + + +struct _rand_state { int __x[57]; }; +extern __declspec(__nothrow) int _rand_r(struct _rand_state *); +extern __declspec(__nothrow) void _srand_r(struct _rand_state *, unsigned int); +struct _ANSI_rand_state { int __x[1]; }; +extern __declspec(__nothrow) int _ANSI_rand_r(struct _ANSI_rand_state *); +extern __declspec(__nothrow) void _ANSI_srand_r(struct _ANSI_rand_state *, unsigned int); + + + + + +extern __declspec(__nothrow) void *calloc(size_t , size_t ); + + + + + +extern __declspec(__nothrow) void free(void * ); + + + + + + + +extern __declspec(__nothrow) void *malloc(size_t ); + + + + + +extern __declspec(__nothrow) void *realloc(void * , size_t ); + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) int posix_memalign(void ** , size_t , size_t ); + + + + + + + + + + + + +typedef int (*__heapprt)(void *, char const *, ...); +extern __declspec(__nothrow) void __heapstats(int (* )(void * , + char const * , ...), + void * ) __attribute__((__nonnull__(1))); + + + + + + + + + + + + +extern __declspec(__nothrow) int __heapvalid(int (* )(void * , + char const * , ...), + void * , int ) __attribute__((__nonnull__(1))); + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) __declspec(__noreturn) void abort(void); + + + + + + + + + + +extern __declspec(__nothrow) int atexit(void (* )(void)) __attribute__((__nonnull__(1))); + + + + + + +# 436 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdlib.h" + + +extern __declspec(__nothrow) __declspec(__noreturn) void exit(int ); + + + + + + + + + + + + + + + +extern __declspec(__nothrow) __declspec(__noreturn) void _Exit(int ); + + + + + + + + + + +extern __declspec(__nothrow) char *getenv(const char * ) __attribute__((__nonnull__(1))); + + + + + + + + + + + + +extern __declspec(__nothrow) int system(const char * ); + + + + + + + + + + + + +extern void *bsearch(const void * , const void * , + size_t , size_t , + int (* )(const void *, const void *)) __attribute__((__nonnull__(1,2,5))); + + + + + + + + + + + + + + +# 524 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdlib.h" + + +extern void qsort(void * , size_t , size_t , + int (* )(const void *, const void *)) __attribute__((__nonnull__(1,4))); + + + + + + + + + + + + +# 553 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdlib.h" + +extern __declspec(__nothrow) __attribute__((const)) int abs(int ); + + + + + + +extern __declspec(__nothrow) __attribute__((const)) div_t div(int , int ); + + + + + + + + + + + +extern __declspec(__nothrow) __attribute__((const)) long int labs(long int ); + + + + + + + + + +extern __declspec(__nothrow) __attribute__((const)) ldiv_t ldiv(long int , long int ); + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) __attribute__((const)) long long llabs(long long ); + + + + + + + + + +extern __declspec(__nothrow) __attribute__((const)) lldiv_t lldiv(long long , long long ); + + + + + + + + + + + + + +# 634 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdlib.h" + + + + + +typedef struct __sdiv32by16 { int quot, rem; } __sdiv32by16; +typedef struct __udiv32by16 { unsigned int quot, rem; } __udiv32by16; + +typedef struct __sdiv64by32 { int rem, quot; } __sdiv64by32; + +__value_in_regs extern __declspec(__nothrow) __attribute__((const)) __sdiv32by16 __rt_sdiv32by16( + int , + short int ); + + + +__value_in_regs extern __declspec(__nothrow) __attribute__((const)) __udiv32by16 __rt_udiv32by16( + unsigned int , + unsigned short ); + + + +__value_in_regs extern __declspec(__nothrow) __attribute__((const)) __sdiv64by32 __rt_sdiv64by32( + int , unsigned int , + int ); + + + + + + + + +extern __declspec(__nothrow) unsigned int __fp_status(unsigned int , unsigned int ); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) int mblen(const char * , size_t ); + + + + + + + + + + + + + + +extern __declspec(__nothrow) int mbtowc(wchar_t * __restrict , + const char * __restrict , size_t ); + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) int wctomb(char * , wchar_t ); + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) size_t mbstowcs(wchar_t * __restrict , + const char * __restrict , size_t ) __attribute__((__nonnull__(2))); + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) size_t wcstombs(char * __restrict , + const wchar_t * __restrict , size_t ) __attribute__((__nonnull__(2))); + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) void __use_realtime_heap(void); +extern __declspec(__nothrow) void __use_realtime_division(void); +extern __declspec(__nothrow) void __use_two_region_memory(void); +extern __declspec(__nothrow) void __use_no_heap(void); +extern __declspec(__nothrow) void __use_no_heap_region(void); + +extern __declspec(__nothrow) char const *__C_library_version_string(void); +extern __declspec(__nothrow) int __C_library_version_number(void); + + + + + + + + + + + +# 892 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdlib.h" + + + + + + +# 4 "..\\..\\src\\app\\main.c" +# 1 "..\\..\\src\\app\\test_cfg_global.h" + + + + + + + + + + + + + + + + + + + +# 31 "..\\..\\src\\app\\test_cfg_global.h" + + + + +# 1 "..\\..\\src\\app\\P8P\\p8p_demo.h" + + + + + + + + + + + + + + + + + + +void google_p8p_demo(void); + +# 37 "..\\..\\src\\app\\test_cfg_global.h" + + + +# 5 "..\\..\\src\\app\\main.c" +# 1 "..\\..\\src\\common\\tau_log.h" + + + + + + + + + + + + + + + + +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + + + + + + + + + +# 27 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + + + +# 46 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + +typedef signed char int8_t; +typedef signed short int int16_t; +typedef signed int int32_t; +typedef signed __int64 int64_t; + + +typedef unsigned char uint8_t; +typedef unsigned short int uint16_t; +typedef unsigned int uint32_t; +typedef unsigned __int64 uint64_t; + + + + + +typedef signed char int_least8_t; +typedef signed short int int_least16_t; +typedef signed int int_least32_t; +typedef signed __int64 int_least64_t; + + +typedef unsigned char uint_least8_t; +typedef unsigned short int uint_least16_t; +typedef unsigned int uint_least32_t; +typedef unsigned __int64 uint_least64_t; + + + + +typedef signed int int_fast8_t; +typedef signed int int_fast16_t; +typedef signed int int_fast32_t; +typedef signed __int64 int_fast64_t; + + +typedef unsigned int uint_fast8_t; +typedef unsigned int uint_fast16_t; +typedef unsigned int uint_fast32_t; +typedef unsigned __int64 uint_fast64_t; + + + + + + +typedef signed int intptr_t; +typedef unsigned int uintptr_t; + + + +typedef signed long long intmax_t; +typedef unsigned long long uintmax_t; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 216 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + + + + + + + + + +# 241 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 305 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + +# 18 "..\\..\\src\\common\\tau_log.h" +# 19 "..\\..\\src\\common\\tau_log.h" +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdarg.h" + + + + + + + + + + + + + + + + + + + +# 27 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdarg.h" + + + + + + + + + + + + +# 57 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdarg.h" + typedef struct __va_list { void *__ap; } va_list; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + typedef va_list __gnuc_va_list; + + + + + + +# 147 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdarg.h" + + + +# 20 "..\\..\\src\\common\\tau_log.h" +# 1 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef enum IRQn +{ + + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + + VIDC_IRQn = 0, + LCDC_IRQn = 1, + MIPI_RX_IRQn = 2, + MIPI_TX_IRQn = 3, + MEMC_IRQn = 4, + VPRE_IRQn = 5, + FLSCTRL_IRQn = 6, + DMA_IRQn = 7, + TIMER0_IRQn = 8, + TIMER1_IRQn = 9, + TIMER2_IRQn = 10, + TIMER3_IRQn = 11, + WDG_IRQn = 12, + UART_IRQn = 13, + I2C0_IRQn = 14, + I2C1_IRQn = 15, + SPIS_IRQn = 16, + SPIM_IRQn = 17, + VPRE1_IRQn = 18, + I2C2_IRQn = 19, + OTP_IRQn = 20, + SWIRE_IRQn = 21, + PVD_IRQn = 22, + AP_NRESET_IRQn = 23, + EXTI_INT0_IRQn = 24, + EXTI_INT1_IRQn = 25, + EXTI_INT2_IRQn = 26, + EXTI_INT3_IRQn = 27, + EXTI_INT4_IRQn = 28, + EXTI_INT5_IRQn = 29, + EXTI_INT6_IRQn = 30, + EXTI_INT7_IRQn = 31 + +} IRQn_Type; + + + + + + + + +#pragma push +#pragma anon_unions +# 107 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + + + + + + + + + + + + +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 35 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_version.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 64 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + +# 114 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_compiler.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 29 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_compiler.h" + + + + +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 107 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + +static __inline uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __asm("control"); + return(__regControl); +} + + + + + + + +static __inline void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __asm("control"); + __regControl = control; +} + + + + + + + +static __inline uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __asm("ipsr"); + return(__regIPSR); +} + + + + + + + +static __inline uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __asm("apsr"); + return(__regAPSR); +} + + + + + + + +static __inline uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __asm("xpsr"); + return(__regXPSR); +} + + + + + + + +static __inline uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __asm("psp"); + return(__regProcessStackPointer); +} + + + + + + + +static __inline void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __asm("psp"); + __regProcessStackPointer = topOfProcStack; +} + + + + + + + +static __inline uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __asm("msp"); + return(__regMainStackPointer); +} + + + + + + + +static __inline void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __asm("msp"); + __regMainStackPointer = topOfMainStack; +} + + + + + + + +static __inline uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __asm("primask"); + return(__regPriMask); +} + + + + + + + +static __inline void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __asm("primask"); + __regPriMask = (priMask); +} + + +# 342 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + + + + + +static __inline uint32_t __get_FPSCR(void) +{ + + + + + + return(0U); + +} + + + + + + + +static __inline void __set_FPSCR(uint32_t fpscr) +{ + + + + + + (void)fpscr; + +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +__attribute__((section(".rev16_text"))) static __inline __asm uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + + + + + + + + + +__attribute__((section(".revsh_text"))) static __inline __asm int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +__attribute__((always_inline)) static __inline uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U * 8U) - 1U; + + result = value; + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; + return result; +} + + + + + + + + + + + + +# 732 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + + + + + + +__attribute__((always_inline)) static __inline int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + + + + + + + + +__attribute__((always_inline)) static __inline uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + + + + + + + + + + + + + +# 866 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + +# 35 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_compiler.h" + + + + + +# 268 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_compiler.h" + + + + +# 116 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + +# 150 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + +# 166 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef union +{ + struct + { + uint32_t _reserved0:28; + uint32_t V:1; + uint32_t C:1; + uint32_t Z:1; + uint32_t N:1; + } b; + uint32_t w; +} APSR_Type; + + + + + + + + + + + + + + + + + + +typedef union +{ + struct + { + uint32_t ISR:9; + uint32_t _reserved0:23; + } b; + uint32_t w; +} IPSR_Type; + + + + + + + + + +typedef union +{ + struct + { + uint32_t ISR:9; + uint32_t _reserved0:15; + uint32_t T:1; + uint32_t _reserved1:3; + uint32_t V:1; + uint32_t C:1; + uint32_t Z:1; + uint32_t N:1; + } b; + uint32_t w; +} xPSR_Type; + + + + + + + + + + + + + + + + + + + + + + + + +typedef union +{ + struct + { + uint32_t _reserved0:1; + uint32_t SPSEL:1; + uint32_t _reserved1:30; + } b; + uint32_t w; +} CONTROL_Type; + + + + + + + + + + + + + + + + + + +typedef struct +{ + volatile uint32_t ISER[1U]; + uint32_t RESERVED0[31U]; + volatile uint32_t ICER[1U]; + uint32_t RESERVED1[31U]; + volatile uint32_t ISPR[1U]; + uint32_t RESERVED2[31U]; + volatile uint32_t ICPR[1U]; + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + volatile uint32_t IP[8U]; +} NVIC_Type; + + + + + + + + + + + + + + +typedef struct +{ + volatile const uint32_t CPUID; + volatile uint32_t ICSR; + uint32_t RESERVED0; + volatile uint32_t AIRCR; + volatile uint32_t SCR; + volatile uint32_t CCR; + uint32_t RESERVED1; + volatile uint32_t SHP[2U]; + volatile uint32_t SHCSR; +} SCB_Type; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef struct +{ + volatile uint32_t CTRL; + volatile uint32_t LOAD; + volatile uint32_t VAL; + volatile const uint32_t CALIB; +} SysTick_Type; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 583 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + +# 598 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + + + + + + + +static __inline void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + + + + + + + + + +static __inline uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + + + + + + + +static __inline void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); + do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U); + } +} + + + + + + + + + + +static __inline uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + + + + + + + +static __inline void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + + + + + + + +static __inline void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + + + + + + + + + + +static __inline void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] = ((uint32_t)(((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | + (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); + } + else + { + ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] = ((uint32_t)(((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | + (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); + } +} + + + + + + + + + + + +static __inline uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[ ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); + } + else + { + return((uint32_t)(((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); + } +} + + + + + + + + + + + + + +static __inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + + + + + + + + + + + + +static __inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + + + + + + + + + + +static __inline void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + 16) * 4)) = vector; +} + + + + + + + + + + +static __inline uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + 16) * 4)); +} + + + + + + +__declspec(noreturn) static __inline void __NVIC_SystemReset(void) +{ + do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); + + ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR = ((0x5FAUL << 16U) | + (1UL << 2U)); + do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); + + for(;;) + { + __nop(); + } +} + + + + + + + + + + + + + + + + + + + + +static __inline uint32_t SCB_GetFPUType(void) +{ + return 0U; +} + + + + + + + + + + + + + + + + + + + + + + + + + + + +static __inline uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > (0xFFFFFFUL )) + { + return (1UL); + } + + ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->LOAD = (uint32_t)(ticks - 1UL); + __NVIC_SetPriority (SysTick_IRQn, (1UL << 2U) - 1UL); + ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->VAL = 0UL; + ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL = (1UL << 2U) | + (1UL << 1U) | + (1UL ); + return (0UL); +} + + + + + + + + + + + + + + +# 122 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\Device\\ARM\\ARMCM0\\Include\\system_ARMCM0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern uint32_t SystemCoreClock; + + + + + + + +extern void SystemInit (void); + + + + + + + +extern void SystemCoreClockUpdate (void); + + + + + +# 123 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + +#pragma pop +# 142 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + +# 167 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + +# 179 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + + + +# 21 "..\\..\\src\\common\\tau_log.h" + + + + +# 31 "..\\..\\src\\common\\tau_log.h" + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef enum +{ + kLOG_LEVEL_DBG = 0, + kLOG_LEVEL_INF, + kLOG_LEVEL_ERR, + kLOG_LEVEL_NONE +} log_level_e; + + + + + +typedef enum +{ + LOG_PORT_UART0, + LOG_PORT_UART1, + LOG_PORT_SWD, + LOG_PORT_UNKNOWN +} log_port_e; + + + + + + + + + + + + + + +void tau_log_init(uint32_t baud_rate, log_port_e log_port); + + + + + + + +void tau_log_printf(log_level_e log_lv, const char *fmt, ...); + +# 6 "..\\..\\src\\app\\main.c" +# 1 "..\\..\\src\\sdk\\include\\hal_system.h" + + + + + + + + + + + + + + +# 1 "..\\..\\src\\common\\tau_common.h" + + + + + + + + + + + + + + + + +# 18 "..\\..\\src\\common\\tau_common.h" +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 61 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + +# 75 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 112 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + + + + + + + + + +extern __attribute__((__pcs__("aapcs"))) unsigned __ARM_dcmp4(double , double ); +extern __attribute__((__pcs__("aapcs"))) unsigned __ARM_fcmp4(float , float ); + + + + + + + +extern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassifyf(float ); +extern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassify(double ); + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinitef(float __x) +{ + return (((*(unsigned *)&(__x)) >> 23) & 0xff) != 0xff; +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinite(double __x) +{ + return (((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff) != 0x7ff; +} + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinff(float __x) +{ + return ((*(unsigned *)&(__x)) << 1) == 0xff000000; +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinf(double __x) +{ + return (((*(1 + (unsigned *)&(__x))) << 1) == 0xffe00000) && ((*(unsigned *)&(__x)) == 0); +} + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreaterf(float __x, float __y) +{ + unsigned __f = __ARM_fcmp4(__x, __y) >> 28; + return (__f == 8) || (__f == 2); +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreater(double __x, double __y) +{ + unsigned __f = __ARM_dcmp4(__x, __y) >> 28; + return (__f == 8) || (__f == 2); +} + + + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnanf(float __x) +{ + return (0x7f800000 - ((*(unsigned *)&(__x)) & 0x7fffffff)) >> 31; +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnan(double __x) +{ + unsigned __xf = (*(1 + (unsigned *)&(__x))) | (((*(unsigned *)&(__x)) == 0) ? 0 : 1); + return (0x7ff00000 - (__xf & 0x7fffffff)) >> 31; +} + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormalf(float __x) +{ + unsigned __xe = ((*(unsigned *)&(__x)) >> 23) & 0xff; + return (__xe != 0xff) && (__xe != 0); +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormal(double __x) +{ + unsigned __xe = ((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff; + return (__xe != 0x7ff) && (__xe != 0); +} + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbitf(float __x) +{ + return (*(unsigned *)&(__x)) >> 31; +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbit(double __x) +{ + return (*(1 + (unsigned *)&(__x))) >> 31; +} + + + + + + + + + + +# 230 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + typedef float float_t; + typedef double double_t; +# 251 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + +extern const int math_errhandling; +# 261 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + +extern __declspec(__nothrow) double acos(double ); + + + +extern __declspec(__nothrow) double asin(double ); + + + + + +extern __declspec(__nothrow) __attribute__((const)) double atan(double ); + + + +extern __declspec(__nothrow) double atan2(double , double ); + + + + + +extern __declspec(__nothrow) double cos(double ); + + + + +extern __declspec(__nothrow) double sin(double ); + + + + + +extern void __use_accurate_range_reduction(void); + + + +extern __declspec(__nothrow) double tan(double ); + + + + + +extern __declspec(__nothrow) double cosh(double ); + + + + +extern __declspec(__nothrow) double sinh(double ); + + + + + + +extern __declspec(__nothrow) __attribute__((const)) double tanh(double ); + + + +extern __declspec(__nothrow) double exp(double ); + + + + + + +extern __declspec(__nothrow) double frexp(double , int * ) __attribute__((__nonnull__(2))); + + + + + + + +extern __declspec(__nothrow) double ldexp(double , int ); + + + + +extern __declspec(__nothrow) double log(double ); + + + + + +extern __declspec(__nothrow) double log10(double ); + + + +extern __declspec(__nothrow) double modf(double , double * ) __attribute__((__nonnull__(2))); + + + + + +extern __declspec(__nothrow) double pow(double , double ); + + + + + + +extern __declspec(__nothrow) double sqrt(double ); + + + + + + + + static __inline double _sqrt(double __x) { return sqrt(__x); } + + + + + static __inline float _sqrtf(float __x) { return (float)sqrt(__x); } + + + + + + + +extern __declspec(__nothrow) __attribute__((const)) double ceil(double ); + + +extern __declspec(__nothrow) __attribute__((const)) double fabs(double ); + + + +extern __declspec(__nothrow) __attribute__((const)) double floor(double ); + + + +extern __declspec(__nothrow) double fmod(double , double ); + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) double acosh(double ); + + + +extern __declspec(__nothrow) double asinh(double ); + + + +extern __declspec(__nothrow) double atanh(double ); + + + +extern __declspec(__nothrow) double cbrt(double ); + + + +static __inline __declspec(__nothrow) __attribute__((const)) double copysign(double __x, double __y) + + + +{ + (*(1 + (unsigned *)&(__x))) = ((*(1 + (unsigned *)&(__x))) & 0x7fffffff) | ((*(1 + (unsigned *)&(__y))) & 0x80000000); + return __x; +} +static __inline __declspec(__nothrow) __attribute__((const)) float copysignf(float __x, float __y) + + + +{ + (*(unsigned *)&(__x)) = ((*(unsigned *)&(__x)) & 0x7fffffff) | ((*(unsigned *)&(__y)) & 0x80000000); + return __x; +} +extern __declspec(__nothrow) double erf(double ); + + + +extern __declspec(__nothrow) double erfc(double ); + + + +extern __declspec(__nothrow) double expm1(double ); + + + + + + + + + + + + + + + +# 479 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + +extern __declspec(__nothrow) double hypot(double , double ); + + + + + + +extern __declspec(__nothrow) int ilogb(double ); + + + +extern __declspec(__nothrow) int ilogbf(float ); + + + +extern __declspec(__nothrow) int ilogbl(long double ); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) double lgamma (double ); + + + + +extern __declspec(__nothrow) double log1p(double ); + + + +extern __declspec(__nothrow) double logb(double ); + + + +extern __declspec(__nothrow) float logbf(float ); + + + +extern __declspec(__nothrow) long double logbl(long double ); + + + +extern __declspec(__nothrow) double nextafter(double , double ); + + + + +extern __declspec(__nothrow) float nextafterf(float , float ); + + + + +extern __declspec(__nothrow) long double nextafterl(long double , long double ); + + + + +extern __declspec(__nothrow) double nexttoward(double , long double ); + + + + +extern __declspec(__nothrow) float nexttowardf(float , long double ); + + + + +extern __declspec(__nothrow) long double nexttowardl(long double , long double ); + + + + +extern __declspec(__nothrow) double remainder(double , double ); + + + +extern __declspec(__nothrow) __attribute__((const)) double rint(double ); + + + +extern __declspec(__nothrow) double scalbln(double , long int ); + + + +extern __declspec(__nothrow) float scalblnf(float , long int ); + + + +extern __declspec(__nothrow) long double scalblnl(long double , long int ); + + + +extern __declspec(__nothrow) double scalbn(double , int ); + + + +extern __declspec(__nothrow) float scalbnf(float , int ); + + + +extern __declspec(__nothrow) long double scalbnl(long double , int ); + + + + + + + + + + + + + + +extern __declspec(__nothrow) __attribute__((const)) float _fabsf(float); +static __inline __declspec(__nothrow) __attribute__((const)) float fabsf(float __f) { return _fabsf(__f); } +extern __declspec(__nothrow) float sinf(float ); +extern __declspec(__nothrow) float cosf(float ); +extern __declspec(__nothrow) float tanf(float ); +extern __declspec(__nothrow) float acosf(float ); +extern __declspec(__nothrow) float asinf(float ); +extern __declspec(__nothrow) float atanf(float ); +extern __declspec(__nothrow) float atan2f(float , float ); +extern __declspec(__nothrow) float sinhf(float ); +extern __declspec(__nothrow) float coshf(float ); +extern __declspec(__nothrow) float tanhf(float ); +extern __declspec(__nothrow) float expf(float ); +extern __declspec(__nothrow) float logf(float ); +extern __declspec(__nothrow) float log10f(float ); +extern __declspec(__nothrow) float powf(float , float ); +extern __declspec(__nothrow) float sqrtf(float ); +extern __declspec(__nothrow) float ldexpf(float , int ); +extern __declspec(__nothrow) float frexpf(float , int * ) __attribute__((__nonnull__(2))); +extern __declspec(__nothrow) __attribute__((const)) float ceilf(float ); +extern __declspec(__nothrow) __attribute__((const)) float floorf(float ); +extern __declspec(__nothrow) float fmodf(float , float ); +extern __declspec(__nothrow) float modff(float , float * ) __attribute__((__nonnull__(2))); + + + + + + + + + + + + + + + + + +__declspec(__nothrow) long double acosl(long double ); +__declspec(__nothrow) long double asinl(long double ); +__declspec(__nothrow) long double atanl(long double ); +__declspec(__nothrow) long double atan2l(long double , long double ); +__declspec(__nothrow) long double ceill(long double ); +__declspec(__nothrow) long double cosl(long double ); +__declspec(__nothrow) long double coshl(long double ); +__declspec(__nothrow) long double expl(long double ); +__declspec(__nothrow) long double fabsl(long double ); +__declspec(__nothrow) long double floorl(long double ); +__declspec(__nothrow) long double fmodl(long double , long double ); +__declspec(__nothrow) long double frexpl(long double , int* ) __attribute__((__nonnull__(2))); +__declspec(__nothrow) long double ldexpl(long double , int ); +__declspec(__nothrow) long double logl(long double ); +__declspec(__nothrow) long double log10l(long double ); +__declspec(__nothrow) long double modfl(long double , long double * ) __attribute__((__nonnull__(2))); +__declspec(__nothrow) long double powl(long double , long double ); +__declspec(__nothrow) long double sinl(long double ); +__declspec(__nothrow) long double sinhl(long double ); +__declspec(__nothrow) long double sqrtl(long double ); +__declspec(__nothrow) long double tanl(long double ); +__declspec(__nothrow) long double tanhl(long double ); + + + + + + +extern __declspec(__nothrow) float acoshf(float ); +__declspec(__nothrow) long double acoshl(long double ); +extern __declspec(__nothrow) float asinhf(float ); +__declspec(__nothrow) long double asinhl(long double ); +extern __declspec(__nothrow) float atanhf(float ); +__declspec(__nothrow) long double atanhl(long double ); +__declspec(__nothrow) long double copysignl(long double , long double ); +extern __declspec(__nothrow) float cbrtf(float ); +__declspec(__nothrow) long double cbrtl(long double ); +extern __declspec(__nothrow) float erff(float ); +__declspec(__nothrow) long double erfl(long double ); +extern __declspec(__nothrow) float erfcf(float ); +__declspec(__nothrow) long double erfcl(long double ); +extern __declspec(__nothrow) float expm1f(float ); +__declspec(__nothrow) long double expm1l(long double ); +extern __declspec(__nothrow) float log1pf(float ); +__declspec(__nothrow) long double log1pl(long double ); +extern __declspec(__nothrow) float hypotf(float , float ); +__declspec(__nothrow) long double hypotl(long double , long double ); +extern __declspec(__nothrow) float lgammaf(float ); +__declspec(__nothrow) long double lgammal(long double ); +extern __declspec(__nothrow) float remainderf(float , float ); +__declspec(__nothrow) long double remainderl(long double , long double ); +extern __declspec(__nothrow) float rintf(float ); +__declspec(__nothrow) long double rintl(long double ); + + + + + + + +extern __declspec(__nothrow) double exp2(double ); +extern __declspec(__nothrow) float exp2f(float ); +__declspec(__nothrow) long double exp2l(long double ); +extern __declspec(__nothrow) double fdim(double , double ); +extern __declspec(__nothrow) float fdimf(float , float ); +__declspec(__nothrow) long double fdiml(long double , long double ); +# 803 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" +extern __declspec(__nothrow) double fma(double , double , double ); +extern __declspec(__nothrow) float fmaf(float , float , float ); + +static __inline __declspec(__nothrow) long double fmal(long double __x, long double __y, long double __z) { return (long double)fma((double)__x, (double)__y, (double)__z); } + + +extern __declspec(__nothrow) __attribute__((const)) double fmax(double , double ); +extern __declspec(__nothrow) __attribute__((const)) float fmaxf(float , float ); +__declspec(__nothrow) long double fmaxl(long double , long double ); +extern __declspec(__nothrow) __attribute__((const)) double fmin(double , double ); +extern __declspec(__nothrow) __attribute__((const)) float fminf(float , float ); +__declspec(__nothrow) long double fminl(long double , long double ); +extern __declspec(__nothrow) double log2(double ); +extern __declspec(__nothrow) float log2f(float ); +__declspec(__nothrow) long double log2l(long double ); +extern __declspec(__nothrow) long lrint(double ); +extern __declspec(__nothrow) long lrintf(float ); + +static __inline __declspec(__nothrow) long lrintl(long double __x) { return lrint((double)__x); } + + +extern __declspec(__nothrow) long long llrint(double ); +extern __declspec(__nothrow) long long llrintf(float ); + +static __inline __declspec(__nothrow) long long llrintl(long double __x) { return llrint((double)__x); } + + +extern __declspec(__nothrow) long lround(double ); +extern __declspec(__nothrow) long lroundf(float ); + +static __inline __declspec(__nothrow) long lroundl(long double __x) { return lround((double)__x); } + + +extern __declspec(__nothrow) long long llround(double ); +extern __declspec(__nothrow) long long llroundf(float ); + +static __inline __declspec(__nothrow) long long llroundl(long double __x) { return llround((double)__x); } + + +extern __declspec(__nothrow) __attribute__((const)) double nan(const char * ); +extern __declspec(__nothrow) __attribute__((const)) float nanf(const char * ); + +static __inline __declspec(__nothrow) __attribute__((const)) long double nanl(const char *__t) { return (long double)nan(__t); } +# 856 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" +extern __declspec(__nothrow) __attribute__((const)) double nearbyint(double ); +extern __declspec(__nothrow) __attribute__((const)) float nearbyintf(float ); +__declspec(__nothrow) long double nearbyintl(long double ); +extern double remquo(double , double , int * ); +extern float remquof(float , float , int * ); + +static __inline long double remquol(long double __x, long double __y, int *__q) { return (long double)remquo((double)__x, (double)__y, __q); } + + +extern __declspec(__nothrow) __attribute__((const)) double round(double ); +extern __declspec(__nothrow) __attribute__((const)) float roundf(float ); +__declspec(__nothrow) long double roundl(long double ); +extern __declspec(__nothrow) double tgamma(double ); +extern __declspec(__nothrow) float tgammaf(float ); +__declspec(__nothrow) long double tgammal(long double ); +extern __declspec(__nothrow) __attribute__((const)) double trunc(double ); +extern __declspec(__nothrow) __attribute__((const)) float truncf(float ); +__declspec(__nothrow) long double truncl(long double ); + + + + + + +# 896 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + +# 1087 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + + + +# 1317 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + +# 19 "..\\..\\src\\common\\tau_common.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 75 "..\\..\\src\\common\\tau_common.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef uint32_t status_t; + + +typedef void (*fcb_type)(void *data); + +typedef void (*uart_trans_cb)(status_t status, void *user_data); + +typedef void (*flash_trans_cb)(status_t status, void *user_data); +# 16 "..\\..\\src\\sdk\\include\\hal_system.h" +# 1 "..\\..\\src\\sdk\\include\\hal_gpio.h" + + + + + + + + + + + + + + + +# 1 "..\\..\\src\\common\\tau_device_datatype.h" + + + + + + + + + + + + + + + + + + +# 20 "..\\..\\src\\common\\tau_device_datatype.h" +# 21 "..\\..\\src\\common\\tau_device_datatype.h" + + + + + + + + + + + + + + + +enum _status_groups +{ + STATUS_GROUP_GENERIC = 0, + STATUS_GROUP_I2C = 1, + STATUS_GROUP_UART = 2, + STATUS_GROUP_SPI = 3, + STATUS_GROUP_TIMER = 4, +}; + + +enum _generic_status +{ + STATUS_SUCCESS = ((((STATUS_GROUP_GENERIC)*100) + (0))), + STATUS_FAIL = ((((STATUS_GROUP_GENERIC)*100) + (1))), + STATUS_READ_ONLY = ((((STATUS_GROUP_GENERIC)*100) + (2))), + STATUS_OUT_OF_RANGE = ((((STATUS_GROUP_GENERIC)*100) + (3))), + STATUS_INVALID_ARGUMENT = ((((STATUS_GROUP_GENERIC)*100) + (4))), + STATUS_TIME_OUT = ((((STATUS_GROUP_GENERIC)*100) + (5))), + STATUS_NO_TRANSFER_IN_PROGRESS = ((((STATUS_GROUP_GENERIC)*100) + (6))), +}; + + + + + +typedef enum +{ + STATUS_UART_TX_BUSY = ((((STATUS_GROUP_UART)*100) + (0))), + STATUS_UART_RX_BUSY = ((((STATUS_GROUP_UART)*100) + (1))), + STATUS_UART_TX_IDLE = ((((STATUS_GROUP_UART)*100) + (2))), + STATUS_UART_RX_IDLE = ((((STATUS_GROUP_UART)*100) + (3))), + STATUS_UART_TX_ERR = ((((STATUS_GROUP_UART)*100) + (7))), + STATUS_UART_RX_ERR = ((((STATUS_GROUP_UART)*100) + (9))), + STATUS_UART_RX_RING_BUFF_OVERRUN = ((((STATUS_GROUP_UART)*100) + (8))), + STATUS_UART_NOISE_ERR = ((((STATUS_GROUP_UART)*100) + (10))), + STATUS_UART_FRAMING_ERR = ((((STATUS_GROUP_UART)*100) + (11))), + STATUS_UART_PARITY_ERR = ((((STATUS_GROUP_UART)*100) + (12))), + STATUS_UART_BAUDRATE_NOT_SPT = ((((STATUS_GROUP_UART)*100) + (13))), +} uart_status_e; + + + + +typedef enum +{ + STATUS_TIMER_IDLE = ((((STATUS_GROUP_TIMER)*100) + (0))), + STATUS_TIMER_RUNNING = ((((STATUS_GROUP_TIMER)*100) + (1))), + STATUS_TIMER_TIMEOUT = ((((STATUS_GROUP_TIMER)*100) + (2))), +} timer_status_e; + + + + +typedef enum +{ + DETECT_HIGH_LVL = 0, + DETECT_LOW_LVL, + DETECT_RISING_EDGE, + DETECT_FALLING_EDGE, + DETECT_DOUBLE_EDGE +} sys_cfg_trigger_e; + + + + +typedef enum +{ + TIMER_NUM0 = 0, + TIMER_NUM1, + TIMER_NUM2, + TIMER_NUM3, + TIMER_NUM_MAX +} timer_num_e; + + + + +typedef enum +{ + GPIO_INT_EXTI_INT0 = 0, + GPIO_INT_EXTI_INT1, + GPIO_INT_EXTI_INT2, + GPIO_INT_EXTI_INT3, + GPIO_INT_EXTI_INT4, + GPIO_INT_EXTI_INT5, + GPIO_INT_EXTI_INT6, + GPIO_INT_EXTI_INT7, + GPIO_INT_MAX +} gpio_int_e; + + +typedef enum _pwm_int_type +{ + PWM_INT_HIGH_OVERFLOW = 0, + PWM_INT_LOW_OVERFLOW, + PWM_INT_TOTAL_OVERFLOW, + PWM_INT_HIGH_DONE, + PWM_INT_LOW_DONE, + PWM_INT_TOTAL_DONE, + PWM_INT_MAX +} pwm_int_type_e; + + + + +typedef enum +{ + I2C_SELECT_0 = 0, + I2C_SELECT_1, +} i2c_select_e; + + + + + +typedef enum _i2c_rate +{ + I2C_RATE_STANDARD = 1, + I2C_RATE_FAST, + I2C_RATE_HIGH, +} i2c_rate_e; + + + + + +typedef enum +{ + I2C_INDEX_0, + I2C_INDEX_1, + I2C_INDEX_2, + I2C_INDEX_MAX +} i2c_index_e; + + + + + +typedef enum +{ + AHB_DMA_CH0, + AHB_DMA_CH1, + AHB_DMA_CH2, + AHB_DMA_CH3, + AHB_DMA_CH4, + AHB_DMA_CH5, + AHB_DMA_CH6, + AHB_DMA_CH7, + AHB_DMA_CH_NUM +} dma_channel_type_e; + + + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} function_state_e; + + + + +typedef enum +{ + CRC_REV_NO_TRANSPOSE = 0, + CRC_REV_ONLY_BITS_TRANSPOSE, + CRC_REV_BOTH_TRANSPOSE, + CRC_REV_ONLY_BYTES_TRANSPOSE, +} crc_reversal_type_e; + + + + +typedef enum +{ + CRC_FXOR_DISABLE = 0, + CRC_FXOR_ENABLE, +} crc_fxor_function_e; + + + + +typedef enum +{ + CRC_16_BIT_PROTOCOL = 0, + CRC_32_BIT_PROTOCOL, +} crc_protocol_type_e; + + + + + + + +# 17 "..\\..\\src\\sdk\\include\\hal_gpio.h" +# 18 "..\\..\\src\\sdk\\include\\hal_gpio.h" + + + + + + + +typedef enum +{ + + IO_PAD_GPIO0 = 0, + IO_PAD_GPIO1, + IO_PAD_GPIO2, + IO_PAD_GPIO3, + IO_PAD_GPIO4, + IO_PAD_GPIO5, + IO_PAD_GPIO6, + IO_PAD_GPIO7, + IO_PAD_GPIO8, + IO_PAD_GPIO9, + IO_PAD_GPIO10, + IO_PAD_GPIO11, + IO_PAD_GPIO12, + IO_PAD_GPIO13, + IO_PAD_GPIO14, + IO_PAD_GPIO15, + IO_PAD_GPIO16, + IO_PAD_GPIO17, + IO_PAD_GPIO18, + IO_PAD_GPIO19, + IO_PAD_GPIO20, + IO_PAD_GPIO21, + IO_PAD_GPIO22, + IO_PAD_GPIO23, + IO_PAD_GPIO24, + IO_PAD_GPIO25, + + + IO_PAD_AP_SPIS_MISO = IO_PAD_GPIO0, + IO_PAD_AP_SPIS_MOSI = IO_PAD_GPIO1, + IO_PAD_AP_INT = IO_PAD_GPIO2, + IO_PAD_AP_TE = IO_PAD_GPIO3, + IO_PAD_AP_SWIRE = IO_PAD_GPIO4, + IO_PAD_TD_SPIM_MISO = IO_PAD_GPIO5, + IO_PAD_TD_SPIM_MOSI = IO_PAD_GPIO6, + IO_PAD_TD_RSTN = IO_PAD_GPIO7, + IO_PAD_AP_PWMEN = IO_PAD_GPIO8, + IO_PAD_AP_SPIS_CLK = IO_PAD_GPIO9, + IO_PAD_AP_SPIS_CSN = IO_PAD_GPIO10, + IO_PAD_TD_FC_CLK = IO_PAD_GPIO11, + IO_PAD_TD_FC_CSN = IO_PAD_GPIO12, + IO_PAD_TD_FC_IO0 = IO_PAD_GPIO13, + IO_PAD_TD_FC_IO1 = IO_PAD_GPIO14, + IO_PAD_SWD_CLK = IO_PAD_GPIO15, + IO_PAD_SWD_DIO = IO_PAD_GPIO16, + IO_PAD_AP_RSTN = IO_PAD_GPIO17, + IO_PAD_UART0_TX = IO_PAD_GPIO18, + IO_PAD_TD_SPIM_CLK = IO_PAD_GPIO19, + IO_PAD_TD_SPIM_CSN = IO_PAD_GPIO20, + IO_PAD_AP_TPRSTN = IO_PAD_GPIO21, + IO_PAD_TD_INT = IO_PAD_GPIO22, + IO_PAD_TD_TP_RESX = IO_PAD_GPIO23, + IO_PAD_UART1_TX = IO_PAD_GPIO24, + IO_PAD_UART0_RX = IO_PAD_GPIO25, + + IO_PAD_MAX, + + + + IO_PIN_1 = IO_PAD_SWD_CLK, + IO_PIN_2 = IO_PAD_UART0_TX, + IO_PIN_3 = IO_PAD_SWD_DIO, + IO_PIN_4 = IO_PAD_TD_SPIM_MOSI, + IO_PIN_5 = IO_PAD_TD_SPIM_CLK, + IO_PIN_6 = IO_PAD_TD_SPIM_CSN, + IO_PIN_7 = IO_PAD_TD_SPIM_MISO, + IO_PIN_8 = IO_PAD_TD_RSTN, + IO_PIN_9 = IO_PAD_TD_FC_CSN, + IO_PIN_10 = IO_PAD_TD_FC_CLK, + IO_PIN_11 = IO_PAD_TD_FC_IO0, + IO_PIN_12 = IO_PAD_TD_FC_IO1, + IO_PIN_13 = IO_PAD_TD_TP_RESX, + IO_PIN_14 = IO_PAD_UART1_TX, + IO_PIN_15 = IO_PAD_AP_SWIRE, + IO_PIN_16 = IO_PAD_AP_INT, + IO_PIN_17 = IO_PAD_AP_PWMEN, + IO_PIN_18 = IO_PAD_AP_TPRSTN, + + IO_PIN_29 = IO_PAD_AP_TE, + IO_PIN_30 = IO_PAD_AP_SPIS_MISO, + IO_PIN_31 = IO_PAD_AP_SPIS_CSN, + IO_PIN_32 = IO_PAD_AP_SPIS_CLK, + IO_PIN_33 = IO_PAD_AP_SPIS_MOSI, + IO_PIN_34 = IO_PAD_AP_RSTN, + IO_PIN_35 = IO_PAD_TD_INT, + IO_PIN_36 = IO_PAD_UART0_RX, + +} io_pad_e; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef enum +{ + PIN1_MODE_SWDCLK = 0, + PIN1_MODE_GPIO15 = 2, +} pin1_mode_e; + + + + + +typedef enum +{ + PIN2_MODE_UART0_TX = 0, + PIN2_MODE_PWMO = 1, + PIN2_MODE_GPIO18 = 2, + PIN2_MODE_PWMI = 3, + PIN2_MODE_TEAR1 = 4, +} pin2_mode_e; + + + + +typedef enum +{ + PIN3_MODE_SWDIO = 0, + PIN3_MODE_GPIO16 = 2, +} pin3_mode_e; + + + + + +typedef enum +{ + PIN4_MODE_SPIM_MOSI = 0, + PIN4_MODE_I2C02_SDA = 1, + PIN4_MODE_GPIO6 = 2, + PIN4_MODE_UART0_TX = 3, +} pin4_mode_e; + + + + +typedef enum +{ + PIN5_MODE_SPIM_SCLK = 0, + PIN5_MODE_I2C1_SCL = 1, + PIN5_MODE_GPIO19 = 2, +} pin5_mode_e; + + + + +typedef enum +{ + PIN6_MODE_SPIM_CSN = 0, + PIN6_MODE_I2C1_SDA = 1, + PIN6_MODE_GPIO20 = 2, +} pin6_mode_e; + + + + +typedef enum +{ + PIN7_MODE_SPIM_MISO = 0, + PIN7_MODE_I2C02_SCL = 1, + PIN7_MODE_GPIO5 = 2, +} pin7_mode_e; + + + + +typedef enum +{ + PIN8_MODE_GPIO7 = 2, + PIN8_MODE_I2C02_SDA = 3, +} pin8_mode_e; + + + + +typedef enum +{ + PIN9_MODE_TSPIS_CSN = 0, + PIN9_MODE_GPIO12 = 2, +} pin9_mode_e; + + + + +typedef enum +{ + PIN10_MODE_TSPIS_CLK = 0, + PIN10_MODE_GPIO11 = 2, +} pin10_mode_e; + + + + + +typedef enum +{ + PIN11_MODE_TSPIS_IO0 = 0, + PIN11_MODE_GPIO13 = 2, + PIN11_MODE_I2C02_SDA = 3, +} pin11_mode_e; + + + + +typedef enum +{ + PIN12_MODE_TSPIS_IO1 = 0, + PIN12_MODE_GPIO14 = 2, + PIN12_MODE_I2C02_SCL = 3, +} pin12_mode_e; + + + + +typedef enum +{ + PIN13_MODE_GPIO23 = 2, + PIN13_MODE_PWMO = 3, + PIN13_MODE_UART1_RX = 4, +} pin13_mode_e; + + + + +typedef enum +{ + PIN14_MODE_GPIO24 = 2, + PIN14_MODE_UART0_RX = 3, + PIN14_MODE_UART1_TX = 4, +} pin14_mode_e; + + + + + + +typedef enum +{ + PIN15_MODE_SWIRE = 0, + PIN15_MODE_PWMO = 1, + PIN15_MODE_GPIO4 = 2, +} pin15_mode_e; + + + + +typedef enum +{ + PIN16_MODE_GPIO2 = 2, +} pin16_mode_e; + + + + +typedef enum +{ + PIN17_MODE_UART0_RX = 1, + PIN17_MODE_GPIO8 = 2, + PIN17_MODE_PWMO = 3, +} pin17_mode_e; + + + + +typedef enum +{ + PIN18_MODE_UART0_RX = 0, + PIN18_MODE_GPIO21 = 2, + PIN18_MODE_I2C02_SCL = 3, +} pin18_mode_e; + + + + + + + +typedef enum +{ + PIN29_MODE_JTAG_TRSTN = 0, + PIN29_MODE_TEAR = 1, + PIN29_MODE_GPIO3 = 2, +} pin29_mode_e; + + + + + +typedef enum +{ + PIN30_MODE_JTAG_TDO = 0, + PIN30_MODE_SPIS_MISO = 1, + PIN30_MODE_GPIO0 = 2, + PIN30_MODE_UART0_RX = 3, + PIN30_MODE_I2C1_SCL = 6, +} pin30_mode_e; + + + + +typedef enum +{ + PIN31_MODE_JTAG_TMS = 0, + PIN31_MODE_SPIS_CSN = 1, + PIN31_MODE_GPIO10 = 2, + PIN31_MODE_I2C02_SDA = 3, +} pin31_mode_e; + + + + +typedef enum +{ + PIN32_MODE_JTAG_TCK = 0, + PIN32_MODE_SPIS_SCLK = 1, + PIN32_MODE_GPIO9 = 2, + PIN32_MODE_I2C02_SCL = 3, +} pin32_mode_e; + + + + +typedef enum +{ + PIN33_MODE_JTAG_TDI = 0, + PIN33_MODE_SPIS_MOSI = 1, + PIN33_MODE_GPIO1 = 2, + PIN33_MODE_UART0_TX = 3, + PIN33_MODE_I2C1_SDA_0 = 6, +} pin33_mode_e; + + + + +typedef enum +{ + PIN34_MODE_GPIO17 = 2, +} pin34_mode_e; + + + + + +typedef enum +{ + PIN35_MODE_GPIO22 = 2, +} pin35_mode_e; + + + + + +typedef enum +{ + PIN36_MODE_UART0_RX = 0, + PIN36_MODE_PWMO = 1, + PIN36_MODE_GPIO25 = 2, +} pin36_mode_e; + + + + + + + +typedef enum +{ + IO_MODE_INTER_FC_CLK = 0, + IO_MODE_TSPIS_CLK_EN = 2, +} pad_sfc_clk_mode_e; + + + + +typedef enum +{ + IO_MODE_INTER_FC_CSN = 0, + IO_MODE_TSPIS_CSN_EN = 2, +} pad_sfc_csn_mode_e; + + + + +typedef enum +{ + IO_MODE_INTER_FC_IO0 = 0, + IO_MODE_TSPIS_IO0_EN = 2, +} pad_sfc_io0_mode_e; + + + + +typedef enum +{ + IO_MODE_INTER_FC_IO1 = 0, + IO_MODE_TSPIS_IO1_EN = 2, +} pad_sfc_io1_mode_e; + + + + +typedef enum +{ + IO_SLEW_RATE_SLOW = 0, + IO_SLEW_RATE_FAST = 1, +} pad_slew_rate_e; + + + + + + + +typedef enum +{ + IO_IOE_INPUT = 0, + IO_IOE_OUTPUT, + IO_IOE_NONE +} gpio_ioe_e; + + + + +typedef enum +{ + IO_LVL_LOW = 0, + IO_LVL_HIGH, + IO_LVL_NONE +} gpio_level_e; + + + + + + + +typedef struct +{ + io_pad_e pad; + uint8_t mode; + gpio_ioe_e ioe; + gpio_level_e lvl; +} io_pad_attr_t; + + + + + + + + + + + + + + +void hal_gpio_init_eint(io_pad_e pad, sys_cfg_trigger_e trig); + + + + + + + + +void hal_gpio_reg_eint_cb(io_pad_e pad, fcb_type cb_func); + + + + + + + +void hal_gpio_ctrl_eint(io_pad_e pad, _Bool state); + + + + + + +gpio_int_e hal_gpio_get_int_type(io_pad_e pad); + + + + + + + +void hal_gpio_init_output(io_pad_e pad, gpio_level_e lvl); + + + + + + + +void hal_gpio_set_output_data(io_pad_e pad, gpio_level_e lvl); + + + + + + +void hal_gpio_init_input(io_pad_e pad); + + + + + + +gpio_level_e hal_gpio_get_input_data(io_pad_e pad); + + + + + + + +void hal_gpio_set_mode(io_pad_e pad, uint8_t mode); + + + + + + +void hal_gpio_set_high_impedance(io_pad_e pad); + + + + + + + + +void hal_gpio_get_pull_state(io_pad_e pad, _Bool *up_enable, _Bool *down_enable); + + + + + + + + +void hal_gpio_set_pull_state(io_pad_e pad, _Bool up_enable, _Bool down_enable); + + + + + + + +void hal_gpio_set_schmitt_trigger(io_pad_e pad, _Bool st_enable); + + + + + + + +void hal_gpio_set_driving_strength(io_pad_e pad, uint8_t strength); + + + + + + + +void hal_gpio_set_slew_rate(io_pad_e pad, pad_slew_rate_e rate); + + + + + + + + +void hal_gpio_set_ap_reset_int(_Bool enable, fcb_type cb_func, sys_cfg_trigger_e trig); + + + + + + + +void hal_gpio_config_pad(io_pad_attr_t *attrs, uint8_t size); + +# 17 "..\\..\\src\\sdk\\include\\hal_system.h" +# 18 "..\\..\\src\\sdk\\include\\hal_system.h" + + + + + + + + + + + +typedef enum +{ + HAL_SYSCLK_80M = 80000000, + HAL_SYSCLK_100M = 100000000, + HAL_SYSCLK_150M = 150000000 +} hal_system_clk_e; + + + + + + + + + + + + + + +void hal_system_init(hal_system_clk_e sysclk); + + + + + + +void hal_system_idle_mode(_Bool disable_systick); + + + + + + +void hal_system_register_systick_cb(fcb_type cb_func); + + + + + + +_Bool hal_system_enable_systick(uint8_t ms); + + + + + + +_Bool hal_system_disable_systick(void); + + + + + + +uint32_t hal_system_get_tick(void); + + + + + + +void hal_system_reset_chip(void); + + + + + + +uint32_t hal_system_get_debug_state(void); + + + + + + +void hal_system_clear_debug_state(void); + + + + + + +_Bool hal_system_updata_sysclk(hal_system_clk_e sysclk); + +# 7 "..\\..\\src\\app\\main.c" +# 1 "..\\..\\src\\board\\board.h" + + + + + + + + + + + + + + + + + + +void board_Init(void); + +# 8 "..\\..\\src\\app\\main.c" +# 1 "..\\..\\src\\app\\module_demo\\module_demo_main.h" + + + + + + + + + +# 13 "..\\..\\src\\app\\module_demo\\module_demo_main.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +void module_demo_main(void); + +# 9 "..\\..\\src\\app\\main.c" +int main() +{ + board_Init(); + + while (1) + { + + + + + + + google_p8p_demo(); + + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "668 Demo\n", "tau_log", 23); } while (0); + while (1); + } +} diff --git a/project/WL668/Listings/main.lst b/project/WL668/Listings/main.lst new file mode 100644 index 0000000..f7c2d89 --- /dev/null +++ b/project/WL668/Listings/main.lst @@ -0,0 +1,8825 @@ +L 1 "..\..\src\app\main.c" +N#include +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h" 1 +N/* stdio.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.9 */ +N/* Copyright (C) Codemist Ltd., 1988-1993 */ +N/* Copyright 1991-1998 ARM Limited. All rights reserved. */ +N +N/* +N * RCS $Revision$ +N * Checkin $Date$ +N * Revising $Author: sdouglas $ +N */ +N +N/* +N * stdio.h declares two types, several macros, and many functions for +N * performing input and output. For a discussion on Streams and Files +N * refer to sections 4.9.2 and 4.9.3 in the above ANSI draft, or to a +N * modern textbook on C. +N */ +N +N#ifndef __stdio_h +N#define __stdio_h +N#define __ARMCLIB_VERSION 5060037 +N +N/* +N * Depending on compiler version __int64 or __INT64_TYPE__ should be defined. +N */ +N#ifndef __int64 +N #ifdef __INT64_TYPE__ +S #define __int64 __INT64_TYPE__ +N #endif +N /* On some architectures neither of these may be defined - if so, fall +N through and error out if used. */ +N#endif +N +N +N#define _ARMABI __declspec(__nothrow) +N +N #ifndef __STDIO_DECLS +N #define __STDIO_DECLS +N +N #undef __CLIBNS +N #ifdef __cplusplus +S namespace std { +S #define __CLIBNS ::std:: +S extern "C" { +N #else /* ndef __cplusplus */ +N #define __CLIBNS +N #endif /* ndef __cplusplus */ +N +N#if defined(__cplusplus) || !defined(__STRICT_ANSI__) || !defined(__size_t) +X#if 0L || !0L || !0L +N /* always defined in C++ and non-strict C for consistency of debug info */ +N #if __sizeof_ptr == 8 +X #if 4 == 8 +S typedef unsigned long size_t; /* see */ +N #else +N typedef unsigned int size_t; /* see */ +N #endif +N #if !defined(__cplusplus) && defined(__STRICT_ANSI__) +X #if !0L && 0L +S #define __size_t 1 +N #endif +N#endif +N +N#undef NULL +N#define NULL 0 /* see */ +N +N/* ANSI forbids va_list to be defined here */ +N/* keep in step with and */ +N#if !defined(__va_list) && (defined(__cplusplus) || !defined(__STRICT_ANSI__) || !defined(__va_list_defined)) +X#if !0L && (0L || !0L || !0L) +N/* always defined in C++ and non-strict C for consistency of debug info */ +N #ifdef __clang__ +S typedef __builtin_va_list __va_list; +N #else +N typedef struct __va_list __va_list; +N #endif +N #if !defined(__cplusplus) && defined(__STRICT_ANSI__) +X #if !0L && 0L +S #define __va_list_defined 1 +N #endif +N#endif +N +N /* +N * If the compiler supports signalling nans as per N965 then it +N * will define __SUPPORT_SNAN__, in which case a user may define +N * _WANT_SNAN in order to obtain compliant versions of the printf +N * and scanf families of functions +N */ +N#if defined(__SUPPORT_SNAN__) && defined(_WANT_SNAN) +X#if 0L && 0L +S#pragma import(__use_snan) +N#endif +N +Ntypedef struct __fpos_t_struct { +N unsigned __int64 __pos; +N /* +N * this structure is equivalent to an mbstate_t, but we're not +N * allowed to actually define the type name `mbstate_t' within +N * stdio.h +N */ +N struct { +N unsigned int __state1, __state2; +N } __mbstate; +N} fpos_t; +N /* +N * fpos_t is an object capable of recording all information needed to +N * specify uniquely every position within a file. +N */ +N +N#define _SYS_OPEN 16 +N /* _SYS_OPEN defines a limit on the number of open files that is imposed +N * by this C library +N */ +N +Ntypedef struct __FILE FILE; +N /* +N * FILE is an object capable of recording all information needed to control +N * a stream, such as its file position indicator, a pointer to its +N * associated buffer, an error indicator that records whether a read/write +N * error has occurred and an end-of-file indicator that records whether the +N * end-of-file has been reached. +N * Its structure is not made known to library clients. +N */ +N +N#if defined(__STRICT_ANSI__) && !__FILE_INCOMPLETE +X#if 0L && !__FILE_INCOMPLETE +Sstruct __FILE { +S union { +S long __FILE_alignment; +S#ifdef __TARGET_ARCH_AARCH64 +S char __FILE_size[136]; +S#else /* __TARGET_ARCH_AARCH64 */ +S char __FILE_size[84]; +S#endif /* __TARGET_ARCH_AARCH64 */ +S } __FILE_opaque; +S}; +S /* +S * FILE must be an object type (C99 - 7.19.1) and an object type fully +S * describes an object [including its static size] (C99 - 6.2.5). +S * This definition is a placeholder which matches the struct __FILE in +S * size and alignment as used internally by libc. +S */ +N#endif +N +N +Nextern FILE __stdin, __stdout, __stderr; +Nextern FILE *__aeabi_stdin, *__aeabi_stdout, *__aeabi_stderr; +N +N#if _AEABI_PORTABILITY_LEVEL != 0 || (!defined _AEABI_PORTABILITY_LEVEL && __DEFAULT_AEABI_PORTABILITY_LEVEL != 0) +X#if _AEABI_PORTABILITY_LEVEL != 0 || (!0L && __DEFAULT_AEABI_PORTABILITY_LEVEL != 0) +S#define stdin (__CLIBNS __aeabi_stdin) +S /* pointer to a FILE object associated with standard input stream */ +S#define stdout (__CLIBNS __aeabi_stdout) +S /* pointer to a FILE object associated with standard output stream */ +S#define stderr (__CLIBNS __aeabi_stderr) +S /* pointer to a FILE object associated with standard error stream */ +Sextern const int __aeabi_IOFBF; +S#define _IOFBF (__CLIBNS __aeabi_IOFBF) +Sextern const int __aeabi_IONBF; +S#define _IONBF (__CLIBNS __aeabi_IONBF) +Sextern const int __aeabi_IOLBF; +S#define _IOLBF (__CLIBNS __aeabi_IOLBF) +Sextern const int __aeabi_BUFSIZ; +S#define BUFSIZ (__CLIBNS __aeabi_BUFSIZ) +Sextern const int __aeabi_FOPEN_MAX; +S#define FOPEN_MAX (__CLIBNS __aeabi_FOPEN_MAX) +Sextern const int __aeabi_TMP_MAX; +S#define TMP_MAX (__CLIBNS __aeabi_TMP_MAX) +Sextern const int __aeabi_FILENAME_MAX; +S#define FILENAME_MAX (__CLIBNS __aeabi_FILENAME_MAX) +Sextern const int __aeabi_L_tmpnam; +S#define L_tmpnam (__CLIBNS __aeabi_L_tmpnam) +N#else +N#define stdin (&__CLIBNS __stdin) +N /* pointer to a FILE object associated with standard input stream */ +N#define stdout (&__CLIBNS __stdout) +N /* pointer to a FILE object associated with standard output stream */ +N#define stderr (&__CLIBNS __stderr) +N /* pointer to a FILE object associated with standard error stream */ +N +N#define _IOFBF 0x100 /* fully buffered IO */ +N#define _IOLBF 0x200 /* line buffered IO */ +N#define _IONBF 0x400 /* unbuffered IO */ +N +N /* Various default file IO buffer sizes */ +N#define BUFSIZ (512) /* system buffer size (as used by setbuf) */ +N +N#define FOPEN_MAX _SYS_OPEN +N /* +N * an integral constant expression that is the minimum number of files that +N * this implementation guarantees can be open simultaneously. +N */ +N +N#define FILENAME_MAX 256 +N /* +N * an integral constant expression that is the size of an array of char +N * large enough to hold the longest filename string +N */ +N#define L_tmpnam FILENAME_MAX +N /* +N * an integral constant expression that is the size of an array of char +N * large enough to hold a temporary file name string generated by the +N * tmpnam function. +N */ +N#define TMP_MAX 256 +N /* +N * an integral constant expression that is the minimum number of unique +N * file names that shall be generated by the tmpnam function. +N */ +N +N#endif +N +N#define EOF (-1) +N /* +N * negative integral constant, indicates end-of-file, that is, no more input +N * from a stream. +N */ +N +N#define SEEK_SET 0 /* start of stream (see fseek) */ +N#define SEEK_CUR 1 /* current position in stream (see fseek) */ +N#define SEEK_END 2 /* end of stream (see fseek) */ +N +N /* +N * _IOBIN is the flag passed to _sys_write to denote a binary +N * file. +N */ +N#define _IOBIN 0x04 /* binary stream */ +N +N#define __STDIN_BUFSIZ (64) /* default stdin buffer size */ +N#define __STDOUT_BUFSIZ (64) /* default stdout buffer size */ +N#define __STDERR_BUFSIZ (16) /* default stderr buffer size */ +N +Nextern _ARMABI int remove(const char * /*filename*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int remove(const char * ) __attribute__((__nonnull__(1))); +N /* +N * causes the file whose name is the string pointed to by filename to be +N * removed. Subsequent attempts to open the file will fail, unless it is +N * created anew. If the file is open, the behaviour of the remove function +N * is implementation-defined. +N * Returns: zero if the operation succeeds, nonzero if it fails. +N */ +Nextern _ARMABI int rename(const char * /*old*/, const char * /*new*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int rename(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * causes the file whose name is the string pointed to by old to be +N * henceforth known by the name given by the string pointed to by new. The +N * file named old is effectively removed. If a file named by the string +N * pointed to by new exists prior to the call of the rename function, the +N * behaviour is implementation-defined. +N * Returns: zero if the operation succeeds, nonzero if it fails, in which +N * case if the file existed previously it is still known by its +N * original name. +N */ +Nextern _ARMABI FILE *tmpfile(void); +Xextern __declspec(__nothrow) FILE *tmpfile(void); +N /* +N * creates a temporary binary file that will be automatically removed when +N * it is closed or at program termination. The file is opened for update. +N * Returns: a pointer to the stream of the file that it created. If the file +N * cannot be created, a null pointer is returned. +N */ +Nextern _ARMABI char *tmpnam(char * /*s*/); +Xextern __declspec(__nothrow) char *tmpnam(char * ); +N /* +N * generates a string that is not the same as the name of an existing file. +N * The tmpnam function generates a different string each time it is called, +N * up to TMP_MAX times. If it is called more than TMP_MAX times, the +N * behaviour is implementation-defined. +N * Returns: If the argument is a null pointer, the tmpnam function leaves +N * its result in an internal static object and returns a pointer to +N * that object. Subsequent calls to the tmpnam function may modify +N * the same object. if the argument is not a null pointer, it is +N * assumed to point to an array of at least L_tmpnam characters; +N * the tmpnam function writes its result in that array and returns +N * the argument as its value. +N */ +N +Nextern _ARMABI int fclose(FILE * /*stream*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int fclose(FILE * ) __attribute__((__nonnull__(1))); +N /* +N * causes the stream pointed to by stream to be flushed and the associated +N * file to be closed. Any unwritten buffered data for the stream are +N * delivered to the host environment to be written to the file; any unread +N * buffered data are discarded. The stream is disassociated from the file. +N * If the associated buffer was automatically allocated, it is deallocated. +N * Returns: zero if the stream was succesfully closed, or nonzero if any +N * errors were detected or if the stream was already closed. +N */ +Nextern _ARMABI int fflush(FILE * /*stream*/); +Xextern __declspec(__nothrow) int fflush(FILE * ); +N /* +N * If the stream points to an output or update stream in which the most +N * recent operation was output, the fflush function causes any unwritten +N * data for that stream to be delivered to the host environment to be +N * written to the file. If the stream points to an input or update stream, +N * the fflush function undoes the effect of any preceding ungetc operation +N * on the stream. +N * Returns: nonzero if a write error occurs. +N */ +Nextern _ARMABI FILE *fopen(const char * __restrict /*filename*/, +Xextern __declspec(__nothrow) FILE *fopen(const char * __restrict , +N const char * __restrict /*mode*/) __attribute__((__nonnull__(1,2))); +N /* +N * opens the file whose name is the string pointed to by filename, and +N * associates a stream with it. +N * The argument mode points to a string beginning with one of the following +N * sequences: +N * "r" open text file for reading +N * "w" create text file for writing, or truncate to zero length +N * "a" append; open text file or create for writing at eof +N * "rb" open binary file for reading +N * "wb" create binary file for writing, or truncate to zero length +N * "ab" append; open binary file or create for writing at eof +N * "r+" open text file for update (reading and writing) +N * "w+" create text file for update, or truncate to zero length +N * "a+" append; open text file or create for update, writing at eof +N * "r+b"/"rb+" open binary file for update (reading and writing) +N * "w+b"/"wb+" create binary file for update, or truncate to zero length +N * "a+b"/"ab+" append; open binary file or create for update, writing at eof +N * +N * Opening a file with read mode ('r' as the first character in the mode +N * argument) fails if the file does not exist or cannot be read. +N * Opening a file with append mode ('a' as the first character in the mode +N * argument) causes all subsequent writes to be forced to the current end of +N * file, regardless of intervening calls to the fseek function. In some +N * implementations, opening a binary file with append mode ('b' as the +N * second or third character in the mode argument) may initially position +N * the file position indicator beyond the last data written, because of the +N * NUL padding. +N * When a file is opened with update mode ('+' as the second or third +N * character in the mode argument), both input and output may be performed +N * on the associated stream. However, output may not be directly followed +N * by input without an intervening call to the fflush fuction or to a file +N * positioning function (fseek, fsetpos, or rewind), and input be not be +N * directly followed by output without an intervening call to the fflush +N * fuction or to a file positioning function, unless the input operation +N * encounters end-of-file. Opening a file with update mode may open or +N * create a binary stream in some implementations. When opened, a stream +N * is fully buffered if and only if it does not refer to an interactive +N * device. The error and end-of-file indicators for the stream are +N * cleared. +N * Returns: a pointer to the object controlling the stream. If the open +N * operation fails, fopen returns a null pointer. +N */ +Nextern _ARMABI FILE *freopen(const char * __restrict /*filename*/, +Xextern __declspec(__nothrow) FILE *freopen(const char * __restrict , +N const char * __restrict /*mode*/, +N FILE * __restrict /*stream*/) __attribute__((__nonnull__(2,3))); +N /* +N * opens the file whose name is the string pointed to by filename and +N * associates the stream pointed to by stream with it. The mode argument is +N * used just as in the fopen function. +N * The freopen function first attempts to close any file that is associated +N * with the specified stream. Failure to close the file successfully is +N * ignored. The error and end-of-file indicators for the stream are cleared. +N * Returns: a null pointer if the operation fails. Otherwise, freopen +N * returns the value of the stream. +N */ +Nextern _ARMABI void setbuf(FILE * __restrict /*stream*/, +Xextern __declspec(__nothrow) void setbuf(FILE * __restrict , +N char * __restrict /*buf*/) __attribute__((__nonnull__(1))); +N /* +N * Except that it returns no value, the setbuf function is equivalent to the +N * setvbuf function invoked with the values _IOFBF for mode and BUFSIZ for +N * size, or (if buf is a null pointer), with the value _IONBF for mode. +N * Returns: no value. +N */ +Nextern _ARMABI int setvbuf(FILE * __restrict /*stream*/, +Xextern __declspec(__nothrow) int setvbuf(FILE * __restrict , +N char * __restrict /*buf*/, +N int /*mode*/, size_t /*size*/) __attribute__((__nonnull__(1))); +N /* +N * may be used after the stream pointed to by stream has been associated +N * with an open file but before it is read or written. The argument mode +N * determines how stream will be buffered, as follows: _IOFBF causes +N * input/output to be fully buffered; _IOLBF causes output to be line +N * buffered (the buffer will be flushed when a new-line character is +N * written, when the buffer is full, or when input is requested); _IONBF +N * causes input/output to be completely unbuffered. If buf is not the null +N * pointer, the array it points to may be used instead of an automatically +N * allocated buffer (the buffer must have a lifetime at least as great as +N * the open stream, so the stream should be closed before a buffer that has +N * automatic storage duration is deallocated upon block exit). The argument +N * size specifies the size of the array. The contents of the array at any +N * time are indeterminate. +N * Returns: zero on success, or nonzero if an invalid value is given for +N * mode or size, or if the request cannot be honoured. +N */ +N#pragma __printf_args +Nextern _ARMABI int fprintf(FILE * __restrict /*stream*/, +Xextern __declspec(__nothrow) int fprintf(FILE * __restrict , +N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); +N /* +N * writes output to the stream pointed to by stream, under control of the +N * string pointed to by format that specifies how subsequent arguments are +N * converted for output. If there are insufficient arguments for the format, +N * the behaviour is undefined. If the format is exhausted while arguments +N * remain, the excess arguments are evaluated but otherwise ignored. The +N * fprintf function returns when the end of the format string is reached. +N * The format shall be a multibyte character sequence, beginning and ending +N * in its initial shift state. The format is composed of zero or more +N * directives: ordinary multibyte characters (not %), which are copied +N * unchanged to the output stream; and conversion specifiers, each of which +N * results in fetching zero or more subsequent arguments. Each conversion +N * specification is introduced by the character %. For a description of the +N * available conversion specifiers refer to section 4.9.6.1 in the ANSI +N * draft mentioned at the start of this file or to any modern textbook on C. +N * The minimum value for the maximum number of characters producable by any +N * single conversion is at least 509. +N * Returns: the number of characters transmitted, or a negative value if an +N * output error occurred. +N */ +N#pragma __printf_args +Nextern _ARMABI int _fprintf(FILE * __restrict /*stream*/, +Xextern __declspec(__nothrow) int _fprintf(FILE * __restrict , +N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); +N /* +N * is equivalent to fprintf, but does not support floating-point formats. +N * You can use instead of fprintf to improve code size. +N * Returns: as fprintf. +N */ +N#pragma __printf_args +Nextern _ARMABI int printf(const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int printf(const char * __restrict , ...) __attribute__((__nonnull__(1))); +N /* +N * is equivalent to fprintf with the argument stdout interposed before the +N * arguments to printf. +N * Returns: the number of characters transmitted, or a negative value if an +N * output error occurred. +N */ +N#pragma __printf_args +Nextern _ARMABI int _printf(const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int _printf(const char * __restrict , ...) __attribute__((__nonnull__(1))); +N /* +N * is equivalent to printf, but does not support floating-point formats. +N * You can use instead of printf to improve code size. +N * Returns: as printf. +N */ +N#pragma __printf_args +Nextern _ARMABI int sprintf(char * __restrict /*s*/, const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int sprintf(char * __restrict , const char * __restrict , ...) __attribute__((__nonnull__(1,2))); +N /* +N * is equivalent to fprintf, except that the argument s specifies an array +N * into which the generated output is to be written, rather than to a +N * stream. A null character is written at the end of the characters written; +N * it is not counted as part of the returned sum. +N * Returns: the number of characters written to the array, not counting the +N * terminating null character. +N */ +N#pragma __printf_args +Nextern _ARMABI int _sprintf(char * __restrict /*s*/, const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int _sprintf(char * __restrict , const char * __restrict , ...) __attribute__((__nonnull__(1,2))); +N /* +N * is equivalent to sprintf, but does not support floating-point formats. +N * You can use instead of sprintf to improve code size. +N * Returns: as sprintf. +N */ +N +N#pragma __printf_args +Nextern _ARMABI int __ARM_snprintf(char * __restrict /*s*/, size_t /*n*/, +Xextern __declspec(__nothrow) int __ARM_snprintf(char * __restrict , size_t , +N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(3))); +N +N#if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) +X#if !0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus) +N#pragma __printf_args +Nextern _ARMABI int snprintf(char * __restrict /*s*/, size_t /*n*/, +Xextern __declspec(__nothrow) int snprintf(char * __restrict , size_t , +N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(3))); +N /* +N * is equivalent to fprintf, except that the argument s specifies an array +N * into which the generated output is to be written, rather than to a +N * stream. The argument n specifies the size of the output array, so as to +N * avoid overflowing the buffer. +N * A null character is written at the end of the characters written, even +N * if the formatting was not completed; it is not counted as part of the +N * returned sum. At most n characters of the output buffer are used, +N * _including_ the null character. +N * Returns: the number of characters that would have been written to the +N * array, not counting the terminating null character, if the +N * array had been big enough. So if the return is >=0 and =n, the string was truncated (but there is still a null char +N * at the end of what was written); if the return is <0, there was +N * an error. +N */ +N#endif +N#pragma __printf_args +Nextern _ARMABI int _snprintf(char * __restrict /*s*/, size_t /*n*/, +Xextern __declspec(__nothrow) int _snprintf(char * __restrict , size_t , +N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(3))); +N /* +N * is equivalent to snprintf, but does not support floating-point formats. +N * You can use instead of snprintf to improve code size. +N * Returns: as snprintf. +N */ +N#pragma __scanf_args +Nextern _ARMABI int fscanf(FILE * __restrict /*stream*/, +Xextern __declspec(__nothrow) int fscanf(FILE * __restrict , +N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); +N /* +N * reads input from the stream pointed to by stream, under control of the +N * string pointed to by format that specifies the admissible input sequences +N * and how thay are to be converted for assignment, using subsequent +N * arguments as pointers to the objects to receive the converted input. If +N * there are insufficient arguments for the format, the behaviour is +N * undefined. If the format is exhausted while arguments remain, the excess +N * arguments are evaluated but otherwise ignored. +N * The format is composed of zero or more directives: one or more +N * white-space characters; an ordinary character (not %); or a conversion +N * specification. Each conversion specification is introduced by the +N * character %. For a description of the available conversion specifiers +N * refer to section 4.9.6.2 in the ANSI draft mentioned at the start of this +N * file, or to any modern textbook on C. +N * If end-of-file is encountered during input, conversion is terminated. If +N * end-of-file occurs before any characters matching the current directive +N * have been read (other than leading white space, where permitted), +N * execution of the current directive terminates with an input failure; +N * otherwise, unless execution of the current directive is terminated with a +N * matching failure, execution of the following directive (if any) is +N * terminated with an input failure. +N * If conversions terminates on a conflicting input character, the offending +N * input character is left unread in the input strem. Trailing white space +N * (including new-line characters) is left unread unless matched by a +N * directive. The success of literal matches and suppressed asignments is +N * not directly determinable other than via the %n directive. +N * Returns: the value of the macro EOF if an input failure occurs before any +N * conversion. Otherwise, the fscanf function returns the number of +N * input items assigned, which can be fewer than provided for, or +N * even zero, in the event of an early conflict between an input +N * character and the format. +N */ +N#pragma __scanf_args +Nextern _ARMABI int _fscanf(FILE * __restrict /*stream*/, +Xextern __declspec(__nothrow) int _fscanf(FILE * __restrict , +N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); +N /* +N * is equivalent to fscanf, but does not support floating-point formats. +N * You can use instead of fscanf to improve code size. +N * Returns: as fscanf. +N */ +N#pragma __scanf_args +Nextern _ARMABI int scanf(const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int scanf(const char * __restrict , ...) __attribute__((__nonnull__(1))); +N /* +N * is equivalent to fscanf with the argument stdin interposed before the +N * arguments to scanf. +N * Returns: the value of the macro EOF if an input failure occurs before any +N * conversion. Otherwise, the scanf function returns the number of +N * input items assigned, which can be fewer than provided for, or +N * even zero, in the event of an early matching failure. +N */ +N#pragma __scanf_args +Nextern _ARMABI int _scanf(const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int _scanf(const char * __restrict , ...) __attribute__((__nonnull__(1))); +N /* +N * is equivalent to scanf, but does not support floating-point formats. +N * You can use instead of scanf to improve code size. +N * Returns: as scanf. +N */ +N#pragma __scanf_args +Nextern _ARMABI int sscanf(const char * __restrict /*s*/, +Xextern __declspec(__nothrow) int sscanf(const char * __restrict , +N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); +N /* +N * is equivalent to fscanf except that the argument s specifies a string +N * from which the input is to be obtained, rather than from a stream. +N * Reaching the end of the string is equivalent to encountering end-of-file +N * for the fscanf function. +N * Returns: the value of the macro EOF if an input failure occurs before any +N * conversion. Otherwise, the scanf function returns the number of +N * input items assigned, which can be fewer than provided for, or +N * even zero, in the event of an early matching failure. +N */ +N#pragma __scanf_args +Nextern _ARMABI int _sscanf(const char * __restrict /*s*/, +Xextern __declspec(__nothrow) int _sscanf(const char * __restrict , +N const char * __restrict /*format*/, ...) __attribute__((__nonnull__(1,2))); +N /* +N * is equivalent to sscanf, but does not support floating-point formats. +N * You can use instead of sscanf to improve code size. +N * Returns: as sscanf. +N */ +N#if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) +X#if !0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus) +N/* C99 additions */ +Nextern _ARMABI int vfscanf(FILE * __restrict /*stream*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int vfscanf(FILE * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI int vscanf(const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int vscanf(const char * __restrict , __va_list) __attribute__((__nonnull__(1))); +Nextern _ARMABI int vsscanf(const char * __restrict /*s*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int vsscanf(const char * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); +N#endif +Nextern _ARMABI int _vfscanf(FILE * __restrict /*stream*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int _vfscanf(FILE * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI int _vscanf(const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int _vscanf(const char * __restrict , __va_list) __attribute__((__nonnull__(1))); +Nextern _ARMABI int _vsscanf(const char * __restrict /*s*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int _vsscanf(const char * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI int __ARM_vsscanf(const char * __restrict /*s*/, const char * __restrict /*format*/, __va_list) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int __ARM_vsscanf(const char * __restrict , const char * __restrict , __va_list) __attribute__((__nonnull__(1,2))); +N +Nextern _ARMABI int vprintf(const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int vprintf(const char * __restrict , __va_list ) __attribute__((__nonnull__(1))); +N /* +N * is equivalent to printf, with the variable argument list replaced by arg, +N * which has been initialised by the va_start macro (and possibly subsequent +N * va_arg calls). The vprintf function does not invoke the va_end function. +N * Returns: the number of characters transmitted, or a negative value if an +N * output error occurred. +N */ +Nextern _ARMABI int _vprintf(const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int _vprintf(const char * __restrict , __va_list ) __attribute__((__nonnull__(1))); +N /* +N * is equivalent to vprintf, but does not support floating-point formats. +N * You can use instead of vprintf to improve code size. +N * Returns: as vprintf. +N */ +Nextern _ARMABI int vfprintf(FILE * __restrict /*stream*/, +Xextern __declspec(__nothrow) int vfprintf(FILE * __restrict , +N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1,2))); +N /* +N * is equivalent to fprintf, with the variable argument list replaced by +N * arg, which has been initialised by the va_start macro (and possibly +N * subsequent va_arg calls). The vfprintf function does not invoke the +N * va_end function. +N * Returns: the number of characters transmitted, or a negative value if an +N * output error occurred. +N */ +Nextern _ARMABI int vsprintf(char * __restrict /*s*/, +Xextern __declspec(__nothrow) int vsprintf(char * __restrict , +N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1,2))); +N /* +N * is equivalent to sprintf, with the variable argument list replaced by +N * arg, which has been initialised by the va_start macro (and possibly +N * subsequent va_arg calls). The vsprintf function does not invoke the +N * va_end function. +N * Returns: the number of characters written in the array, not counting the +N * terminating null character. +N */ +Nextern _ARMABI int __ARM_vsnprintf(char * __restrict /*s*/, size_t /*n*/, +Xextern __declspec(__nothrow) int __ARM_vsnprintf(char * __restrict , size_t , +N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(3))); +N#if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) +X#if !0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus) +Nextern _ARMABI int vsnprintf(char * __restrict /*s*/, size_t /*n*/, +Xextern __declspec(__nothrow) int vsnprintf(char * __restrict , size_t , +N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(3))); +N /* +N * is equivalent to snprintf, with the variable argument list replaced by +N * arg, which has been initialised by the va_start macro (and possibly +N * subsequent va_arg calls). The vsprintf function does not invoke the +N * va_end function. +N * Returns: the number of characters that would have been written in the +N * array, not counting the terminating null character. As +N * snprintf. +N */ +N#endif +Nextern _ARMABI int _vsprintf(char * __restrict /*s*/, +Xextern __declspec(__nothrow) int _vsprintf(char * __restrict , +N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1,2))); +N /* +N * is equivalent to vsprintf, but does not support floating-point formats. +N * You can use instead of vsprintf to improve code size. +N * Returns: as vsprintf. +N */ +Nextern _ARMABI int _vfprintf(FILE * __restrict /*stream*/, +Xextern __declspec(__nothrow) int _vfprintf(FILE * __restrict , +N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(1,2))); +N /* +N * is equivalent to vfprintf, but does not support floating-point formats. +N * You can use instead of vfprintf to improve code size. +N * Returns: as vfprintf. +N */ +Nextern _ARMABI int _vsnprintf(char * __restrict /*s*/, size_t /*n*/, +Xextern __declspec(__nothrow) int _vsnprintf(char * __restrict , size_t , +N const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(3))); +N /* +N * is equivalent to vsnprintf, but does not support floating-point formats. +N * You can use instead of vsnprintf to improve code size. +N * Returns: as vsnprintf. +N */ +N#if !defined(__STRICT_ANSI__) +X#if !0L +N#pragma __printf_args +Nextern _ARMABI int asprintf(char ** /*strp*/, const char * __restrict /*format*/, ...) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) int asprintf(char ** , const char * __restrict , ...) __attribute__((__nonnull__(2))); +Nextern _ARMABI int vasprintf(char ** /*strp*/, const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) int vasprintf(char ** , const char * __restrict , __va_list ) __attribute__((__nonnull__(2))); +N#endif +N#pragma __printf_args +Nextern _ARMABI int __ARM_asprintf(char ** /*strp*/, const char * __restrict /*format*/, ...) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) int __ARM_asprintf(char ** , const char * __restrict , ...) __attribute__((__nonnull__(2))); +Nextern _ARMABI int __ARM_vasprintf(char ** /*strp*/, const char * __restrict /*format*/, __va_list /*arg*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) int __ARM_vasprintf(char ** , const char * __restrict , __va_list ) __attribute__((__nonnull__(2))); +N /* +N * dynamically allocates a buffer of the right size for the +N * formatted string, and returns it in (*strp). Formal return value +N * is the same as any other printf variant, except that it returns +N * -1 if the buffer could not be allocated. +N * +N * (The functions with __ARM_ prefixed names are identical to the +N * ones without, but are available in all compilation modes without +N * violating user namespace.) +N */ +N +Nextern _ARMABI int fgetc(FILE * /*stream*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int fgetc(FILE * ) __attribute__((__nonnull__(1))); +N /* +N * obtains the next character (if present) as an unsigned char converted to +N * an int, from the input stream pointed to by stream, and advances the +N * associated file position indicator (if defined). +N * Returns: the next character from the input stream pointed to by stream. +N * If the stream is at end-of-file, the end-of-file indicator is +N * set and fgetc returns EOF. If a read error occurs, the error +N * indicator is set and fgetc returns EOF. +N */ +Nextern _ARMABI char *fgets(char * __restrict /*s*/, int /*n*/, +Xextern __declspec(__nothrow) char *fgets(char * __restrict , int , +N FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,3))); +N /* +N * reads at most one less than the number of characters specified by n from +N * the stream pointed to by stream into the array pointed to by s. No +N * additional characters are read after a new-line character (which is +N * retained) or after end-of-file. A null character is written immediately +N * after the last character read into the array. +N * Returns: s if successful. If end-of-file is encountered and no characters +N * have been read into the array, the contents of the array remain +N * unchanged and a null pointer is returned. If a read error occurs +N * during the operation, the array contents are indeterminate and a +N * null pointer is returned. +N */ +Nextern _ARMABI int fputc(int /*c*/, FILE * /*stream*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) int fputc(int , FILE * ) __attribute__((__nonnull__(2))); +N /* +N * writes the character specified by c (converted to an unsigned char) to +N * the output stream pointed to by stream, at the position indicated by the +N * asociated file position indicator (if defined), and advances the +N * indicator appropriately. If the file position indicator is not defined, +N * the character is appended to the output stream. +N * Returns: the character written. If a write error occurs, the error +N * indicator is set and fputc returns EOF. +N */ +Nextern _ARMABI int fputs(const char * __restrict /*s*/, FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int fputs(const char * __restrict , FILE * __restrict ) __attribute__((__nonnull__(1,2))); +N /* +N * writes the string pointed to by s to the stream pointed to by stream. +N * The terminating null character is not written. +N * Returns: EOF if a write error occurs; otherwise it returns a nonnegative +N * value. +N */ +Nextern _ARMABI int getc(FILE * /*stream*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int getc(FILE * ) __attribute__((__nonnull__(1))); +N /* +N * is equivalent to fgetc except that it may be implemented as an unsafe +N * macro (stream may be evaluated more than once, so the argument should +N * never be an expression with side-effects). +N * Returns: the next character from the input stream pointed to by stream. +N * If the stream is at end-of-file, the end-of-file indicator is +N * set and getc returns EOF. If a read error occurs, the error +N * indicator is set and getc returns EOF. +N */ +N#ifdef __cplusplus +S inline int getchar() { return getc(stdin); } +N#else +N #define getchar() getc(stdin) +N extern _ARMABI int (getchar)(void); +X extern __declspec(__nothrow) int (getchar)(void); +N#endif +N /* +N * is equivalent to getc with the argument stdin. +N * Returns: the next character from the input stream pointed to by stdin. +N * If the stream is at end-of-file, the end-of-file indicator is +N * set and getchar returns EOF. If a read error occurs, the error +N * indicator is set and getchar returns EOF. +N */ +Nextern _ARMABI char *gets(char * /*s*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) char *gets(char * ) __attribute__((__nonnull__(1))); +N /* +N * reads characters from the input stream pointed to by stdin into the array +N * pointed to by s, until end-of-file is encountered or a new-line character +N * is read. Any new-line character is discarded, and a null character is +N * written immediately after the last character read into the array. +N * Returns: s if successful. If end-of-file is encountered and no characters +N * have been read into the array, the contents of the array remain +N * unchanged and a null pointer is returned. If a read error occurs +N * during the operation, the array contents are indeterminate and a +N * null pointer is returned. +N */ +Nextern _ARMABI int putc(int /*c*/, FILE * /*stream*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) int putc(int , FILE * ) __attribute__((__nonnull__(2))); +N /* +N * is equivalent to fputc except that it may be implemented as aan unsafe +N * macro (stream may be evaluated more than once, so the argument should +N * never be an expression with side-effects). +N * Returns: the character written. If a write error occurs, the error +N * indicator is set and putc returns EOF. +N */ +N#ifdef __cplusplus +S inline int putchar(int __c) { return putc(__c, stdout); } +N#else +N #define putchar(c) putc(c, stdout) +N extern _ARMABI int (putchar)(int /*c*/); +X extern __declspec(__nothrow) int (putchar)(int ); +N#endif +N /* +N * is equivalent to putc with the second argument stdout. +N * Returns: the character written. If a write error occurs, the error +N * indicator is set and putc returns EOF. +N */ +Nextern _ARMABI int puts(const char * /*s*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int puts(const char * ) __attribute__((__nonnull__(1))); +N /* +N * writes the string pointed to by s to the stream pointed to by stdout, and +N * appends a new-line character to the output. The terminating null +N * character is not written. +N * Returns: EOF if a write error occurs; otherwise it returns a nonnegative +N * value. +N */ +Nextern _ARMABI int ungetc(int /*c*/, FILE * /*stream*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) int ungetc(int , FILE * ) __attribute__((__nonnull__(2))); +N /* +N * pushes the character specified by c (converted to an unsigned char) back +N * onto the input stream pointed to by stream. The character will be +N * returned by the next read on that stream. An intervening call to the +N * fflush function or to a file positioning function (fseek, fsetpos, +N * rewind) discards any pushed-back characters. The extern _ARMABIal storage +N * corresponding to the stream is unchanged. +N * One character pushback is guaranteed. If the unget function is called too +N * many times on the same stream without an intervening read or file +N * positioning operation on that stream, the operation may fail. +N * If the value of c equals that of the macro EOF, the operation fails and +N * the input stream is unchanged. +N * A successful call to the ungetc function clears the end-of-file +N * indicator. The value of the file position indicator after reading or +N * discarding all pushed-back characters shall be the same as it was before +N * the characters were pushed back. For a text stream, the value of the file +N * position indicator after a successful call to the ungetc function is +N * unspecified until all pushed-back characters are read or discarded. For a +N * binary stream, the file position indicator is decremented by each +N * successful call to the ungetc function; if its value was zero before a +N * call, it is indeterminate after the call. +N * Returns: the character pushed back after conversion, or EOF if the +N * operation fails. +N */ +N +Nextern _ARMABI size_t fread(void * __restrict /*ptr*/, +Xextern __declspec(__nothrow) size_t fread(void * __restrict , +N size_t /*size*/, size_t /*nmemb*/, FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,4))); +N /* +N * reads into the array pointed to by ptr, up to nmemb members whose size is +N * specified by size, from the stream pointed to by stream. The file +N * position indicator (if defined) is advanced by the number of characters +N * successfully read. If an error occurs, the resulting value of the file +N * position indicator is indeterminate. If a partial member is read, its +N * value is indeterminate. The ferror or feof function shall be used to +N * distinguish between a read error and end-of-file. +N * Returns: the number of members successfully read, which may be less than +N * nmemb if a read error or end-of-file is encountered. If size or +N * nmemb is zero, fread returns zero and the contents of the array +N * and the state of the stream remain unchanged. +N */ +N +Nextern _ARMABI size_t __fread_bytes_avail(void * __restrict /*ptr*/, +Xextern __declspec(__nothrow) size_t __fread_bytes_avail(void * __restrict , +N size_t /*count*/, FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,3))); +N /* +N * reads into the array pointed to by ptr, up to count characters from the +N * stream pointed to by stream. The file position indicator (if defined) +N * is advanced by the number of characters successfully read. If an error +N * occurs, the resulting value of the file position indicator is +N * indeterminate. The ferror or feof function shall be used to +N * distinguish between a read error and end-of-file. The call will block +N * only if no characters are available. +N * Returns: the number of characters successfully read, which may be less than +N * count. If count is zero, __fread_bytes_avail returns zero and +N * the contents of the array and the state of the stream remain +N * unchanged. +N */ +N +Nextern _ARMABI size_t fwrite(const void * __restrict /*ptr*/, +Xextern __declspec(__nothrow) size_t fwrite(const void * __restrict , +N size_t /*size*/, size_t /*nmemb*/, FILE * __restrict /*stream*/) __attribute__((__nonnull__(1,4))); +N /* +N * writes, from the array pointed to by ptr up to nmemb members whose size +N * is specified by size, to the stream pointed to by stream. The file +N * position indicator (if defined) is advanced by the number of characters +N * successfully written. If an error occurs, the resulting value of the file +N * position indicator is indeterminate. +N * Returns: the number of members successfully written, which will be less +N * than nmemb only if a write error is encountered. +N */ +N +Nextern _ARMABI int fgetpos(FILE * __restrict /*stream*/, fpos_t * __restrict /*pos*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int fgetpos(FILE * __restrict , fpos_t * __restrict ) __attribute__((__nonnull__(1,2))); +N /* +N * stores the current value of the file position indicator for the stream +N * pointed to by stream in the object pointed to by pos. The value stored +N * contains unspecified information usable by the fsetpos function for +N * repositioning the stream to its position at the time of the call to the +N * fgetpos function. +N * Returns: zero, if successful. Otherwise nonzero is returned and the +N * integer expression errno is set to an implementation-defined +N * nonzero value. +N */ +Nextern _ARMABI int fseek(FILE * /*stream*/, long int /*offset*/, int /*whence*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int fseek(FILE * , long int , int ) __attribute__((__nonnull__(1))); +N /* +N * sets the file position indicator for the stream pointed to by stream. +N * For a binary stream, the new position is at the signed number of +N * characters specified by offset away from the point specified by whence. +N * The specified point is the beginning of the file for SEEK_SET, the +N * current position in the file for SEEK_CUR, or end-of-file for SEEK_END. +N * A binary stream need not meaningfully support fseek calls with a whence +N * value of SEEK_END. +N * For a text stream, either offset shall be zero, or offset shall be a +N * value returned by an earlier call to the ftell function on the same +N * stream and whence shall be SEEK_SET. +N * The fseek function clears the end-of-file indicator and undoes any +N * effects of the ungetc function on the same stream. After an fseek call, +N * the next operation on an update stream may be either input or output. +N * Returns: nonzero only for a request that cannot be satisfied. +N */ +Nextern _ARMABI int fsetpos(FILE * __restrict /*stream*/, const fpos_t * __restrict /*pos*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int fsetpos(FILE * __restrict , const fpos_t * __restrict ) __attribute__((__nonnull__(1,2))); +N /* +N * sets the file position indicator for the stream pointed to by stream +N * according to the value of the object pointed to by pos, which shall be a +N * value returned by an earlier call to the fgetpos function on the same +N * stream. +N * The fsetpos function clears the end-of-file indicator and undoes any +N * effects of the ungetc function on the same stream. After an fsetpos call, +N * the next operation on an update stream may be either input or output. +N * Returns: zero, if successful. Otherwise nonzero is returned and the +N * integer expression errno is set to an implementation-defined +N * nonzero value. +N */ +Nextern _ARMABI long int ftell(FILE * /*stream*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) long int ftell(FILE * ) __attribute__((__nonnull__(1))); +N /* +N * obtains the current value of the file position indicator for the stream +N * pointed to by stream. For a binary stream, the value is the number of +N * characters from the beginning of the file. For a text stream, the file +N * position indicator contains unspecified information, usable by the fseek +N * function for returning the file position indicator to its position at the +N * time of the ftell call; the difference between two such return values is +N * not necessarily a meaningful measure of the number of characters written +N * or read. +N * Returns: if successful, the current value of the file position indicator. +N * On failure, the ftell function returns -1L and sets the integer +N * expression errno to an implementation-defined nonzero value. +N */ +Nextern _ARMABI void rewind(FILE * /*stream*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) void rewind(FILE * ) __attribute__((__nonnull__(1))); +N /* +N * sets the file position indicator for the stream pointed to by stream to +N * the beginning of the file. It is equivalent to +N * (void)fseek(stream, 0L, SEEK_SET) +N * except that the error indicator for the stream is also cleared. +N * Returns: no value. +N */ +N +Nextern _ARMABI void clearerr(FILE * /*stream*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) void clearerr(FILE * ) __attribute__((__nonnull__(1))); +N /* +N * clears the end-of-file and error indicators for the stream pointed to by +N * stream. These indicators are cleared only when the file is opened or by +N * an explicit call to the clearerr function or to the rewind function. +N * Returns: no value. +N */ +N +Nextern _ARMABI int feof(FILE * /*stream*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int feof(FILE * ) __attribute__((__nonnull__(1))); +N /* +N * tests the end-of-file indicator for the stream pointed to by stream. +N * Returns: nonzero iff the end-of-file indicator is set for stream. +N */ +Nextern _ARMABI int ferror(FILE * /*stream*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int ferror(FILE * ) __attribute__((__nonnull__(1))); +N /* +N * tests the error indicator for the stream pointed to by stream. +N * Returns: nonzero iff the error indicator is set for stream. +N */ +Nextern _ARMABI void perror(const char * /*s*/); +Xextern __declspec(__nothrow) void perror(const char * ); +N /* +N * maps the error number in the integer expression errno to an error +N * message. It writes a sequence of characters to the standard error stream +N * thus: first (if s is not a null pointer and the character pointed to by +N * s is not the null character), the string pointed to by s followed by a +N * colon and a space; then an appropriate error message string followed by +N * a new-line character. The contents of the error message strings are the +N * same as those returned by the strerror function with argument errno, +N * which are implementation-defined. +N * Returns: no value. +N */ +N +Nextern _ARMABI int _fisatty(FILE * /*stream*/ ) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int _fisatty(FILE * ) __attribute__((__nonnull__(1))); +N /* Returns 1 if the stream is tty (stdin), 0 otherwise. Not ANSI compliant. +N */ +N +Nextern _ARMABI void __use_no_semihosting_swi(void); +Xextern __declspec(__nothrow) void __use_no_semihosting_swi(void); +Nextern _ARMABI void __use_no_semihosting(void); +Xextern __declspec(__nothrow) void __use_no_semihosting(void); +N /* +N * Referencing either of these symbols will cause a link-time +N * error if any library functions that use semihosting SWI +N * calls are also present in the link, i.e. you define it if +N * you want to make sure you haven't accidentally used any such +N * SWIs. +N */ +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif +N #endif /* __STDIO_DECLS */ +N +N #if _AEABI_PORTABILITY_LEVEL != 0 && !defined _AEABI_PORTABLE +X #if _AEABI_PORTABILITY_LEVEL != 0 && !0L +S #define _AEABI_PORTABLE +N #endif +N +N #if defined(__cplusplus) && !defined(__STDIO_NO_EXPORTS) +X #if 0L && !0L +S using ::std::size_t; +S using ::std::fpos_t; +S using ::std::FILE; +S using ::std::remove; +S using ::std::rename; +S using ::std::tmpfile; +S using ::std::tmpnam; +S using ::std::fclose; +S using ::std::fflush; +S using ::std::fopen; +S using ::std::freopen; +S using ::std::setbuf; +S using ::std::setvbuf; +S using ::std::fprintf; +S using ::std::_fprintf; +S using ::std::printf; +S using ::std::_printf; +S using ::std::sprintf; +S using ::std::_sprintf; +S #if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) +S using ::std::snprintf; +S using ::std::vsnprintf; +S using ::std::vfscanf; +S using ::std::vscanf; +S using ::std::vsscanf; +S #endif +S using ::std::_snprintf; +S using ::std::_vsnprintf; +S#if !defined(__STRICT_ANSI__) +S using ::std::asprintf; +S using ::std::vasprintf; +S#endif +S using ::std::__ARM_asprintf; +S using ::std::__ARM_vasprintf; +S using ::std::__ARM_vsnprintf; +S using ::std::__ARM_snprintf; +S using ::std::__ARM_vsscanf; +S using ::std::fscanf; +S using ::std::_fscanf; +S using ::std::scanf; +S using ::std::_scanf; +S using ::std::sscanf; +S using ::std::_sscanf; +S using ::std::_vfscanf; +S using ::std::_vscanf; +S using ::std::_vsscanf; +S using ::std::vprintf; +S using ::std::_vprintf; +S using ::std::vfprintf; +S using ::std::_vfprintf; +S using ::std::vsprintf; +S using ::std::_vsprintf; +S using ::std::fgetc; +S using ::std::fgets; +S using ::std::fputc; +S using ::std::fputs; +S using ::std::getc; +S using ::std::getchar; +S using ::std::gets; +S using ::std::putc; +S using ::std::putchar; +S using ::std::puts; +S using ::std::ungetc; +S using ::std::fread; +S using ::std::__fread_bytes_avail; +S using ::std::fwrite; +S using ::std::fgetpos; +S using ::std::fseek; +S using ::std::fsetpos; +S using ::std::ftell; +S using ::std::rewind; +S using ::std::clearerr; +S using ::std::feof; +S using ::std::ferror; +S using ::std::perror; +S using ::std::_fisatty; +S using ::std::__use_no_semihosting_swi; +S using ::std::__use_no_semihosting; +N #endif +N +N#endif /* ndef __stdio_h */ +N +N/* end of stdio.h */ +N +L 2 "..\..\src\app\main.c" 2 +N#include +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h" 1 +N/* string.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.11 */ +N/* Copyright (C) Codemist Ltd., 1988-1993. */ +N/* Copyright 1991-1993 ARM Limited. All rights reserved. */ +N/* version 0.04 */ +N +N/* +N * RCS $Revision$ +N * Checkin $Date$ +N */ +N +N/* +N * string.h declares one type and several functions, and defines one macro +N * useful for manipulating character arrays and other objects treated as +N * character arrays. Various methods are used for determining the lengths of +N * the arrays, but in all cases a char * or void * argument points to the +N * initial (lowest addresses) character of the array. If an array is written +N * beyond the end of an object, the behaviour is undefined. +N */ +N +N#ifndef __string_h +N#define __string_h +N#define __ARMCLIB_VERSION 5060037 +N +N#define _ARMABI __declspec(__nothrow) +N +N #ifndef __STRING_DECLS +N #define __STRING_DECLS +N +N #undef __CLIBNS +N +N #ifdef __cplusplus +S namespace std { +S #define __CLIBNS std:: +S extern "C" { +N #else +N #define __CLIBNS +N #endif /* __cplusplus */ +N +N#if defined(__cplusplus) || !defined(__STRICT_ANSI__) +X#if 0L || !0L +N /* unconditional in C++ and non-strict C for consistency of debug info */ +N #if __sizeof_ptr == 8 +X #if 4 == 8 +S typedef unsigned long size_t; /* see */ +N #else +N typedef unsigned int size_t; /* see */ +N #endif +N#elif !defined(__size_t) +X#elif !0L +S #define __size_t 1 +S #if __sizeof_ptr == 8 +S typedef unsigned long size_t; /* see */ +S #else +S typedef unsigned int size_t; /* see */ +S #endif +N#endif +N +N#undef NULL +N#define NULL 0 /* see */ +N +Nextern _ARMABI void *memcpy(void * __restrict /*s1*/, +Xextern __declspec(__nothrow) void *memcpy(void * __restrict , +N const void * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +N /* +N * copies n characters from the object pointed to by s2 into the object +N * pointed to by s1. If copying takes place between objects that overlap, +N * the behaviour is undefined. +N * Returns: the value of s1. +N */ +Nextern _ARMABI void *memmove(void * /*s1*/, +Xextern __declspec(__nothrow) void *memmove(void * , +N const void * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +N /* +N * copies n characters from the object pointed to by s2 into the object +N * pointed to by s1. Copying takes place as if the n characters from the +N * object pointed to by s2 are first copied into a temporary array of n +N * characters that does not overlap the objects pointed to by s1 and s2, +N * and then the n characters from the temporary array are copied into the +N * object pointed to by s1. +N * Returns: the value of s1. +N */ +Nextern _ARMABI char *strcpy(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strcpy(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); +N /* +N * copies the string pointed to by s2 (including the terminating nul +N * character) into the array pointed to by s1. If copying takes place +N * between objects that overlap, the behaviour is undefined. +N * Returns: the value of s1. +N */ +Nextern _ARMABI char *strncpy(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strncpy(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * copies not more than n characters (characters that follow a null +N * character are not copied) from the array pointed to by s2 into the array +N * pointed to by s1. If copying takes place between objects that overlap, +N * the behaviour is undefined. +N * Returns: the value of s1. +N */ +N +Nextern _ARMABI char *strcat(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strcat(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); +N /* +N * appends a copy of the string pointed to by s2 (including the terminating +N * null character) to the end of the string pointed to by s1. The initial +N * character of s2 overwrites the null character at the end of s1. +N * Returns: the value of s1. +N */ +Nextern _ARMABI char *strncat(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strncat(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * appends not more than n characters (a null character and characters that +N * follow it are not appended) from the array pointed to by s2 to the end of +N * the string pointed to by s1. The initial character of s2 overwrites the +N * null character at the end of s1. A terminating null character is always +N * appended to the result. +N * Returns: the value of s1. +N */ +N +N/* +N * The sign of a nonzero value returned by the comparison functions is +N * determined by the sign of the difference between the values of the first +N * pair of characters (both interpreted as unsigned char) that differ in the +N * objects being compared. +N */ +N +Nextern _ARMABI int memcmp(const void * /*s1*/, const void * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int memcmp(const void * , const void * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * compares the first n characters of the object pointed to by s1 to the +N * first n characters of the object pointed to by s2. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the object pointed to by s1 is greater than, equal to, or +N * less than the object pointed to by s2. +N */ +Nextern _ARMABI int strcmp(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strcmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * compares the string pointed to by s1 to the string pointed to by s2. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2. +N */ +Nextern _ARMABI int strncmp(const char * /*s1*/, const char * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strncmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * compares not more than n characters (characters that follow a null +N * character are not compared) from the array pointed to by s1 to the array +N * pointed to by s2. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2. +N */ +Nextern _ARMABI int strcasecmp(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strcasecmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * compares the string pointed to by s1 to the string pointed to by s2, +N * case-insensitively as defined by the current locale. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2. +N */ +Nextern _ARMABI int strncasecmp(const char * /*s1*/, const char * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strncasecmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * compares not more than n characters (characters that follow a null +N * character are not compared) from the array pointed to by s1 to the array +N * pointed to by s2, case-insensitively as defined by the current locale. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2. +N */ +Nextern _ARMABI int strcoll(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strcoll(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * compares the string pointed to by s1 to the string pointed to by s2, both +N * interpreted as appropriate to the LC_COLLATE category of the current +N * locale. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2 when both are interpreted +N * as appropriate to the current locale. +N */ +N +Nextern _ARMABI size_t strxfrm(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) size_t strxfrm(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(2))); +N /* +N * transforms the string pointed to by s2 and places the resulting string +N * into the array pointed to by s1. The transformation function is such that +N * if the strcmp function is applied to two transformed strings, it returns +N * a value greater than, equal to or less than zero, corresponding to the +N * result of the strcoll function applied to the same two original strings. +N * No more than n characters are placed into the resulting array pointed to +N * by s1, including the terminating null character. If n is zero, s1 is +N * permitted to be a null pointer. If copying takes place between objects +N * that overlap, the behaviour is undefined. +N * Returns: The length of the transformed string is returned (not including +N * the terminating null character). If the value returned is n or +N * more, the contents of the array pointed to by s1 are +N * indeterminate. +N */ +N +N +N#ifdef __cplusplus +Sextern _ARMABI const void *memchr(const void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1))); +Sextern "C++" void *memchr(void * __s, int __c, size_t __n) __attribute__((__nonnull__(1))); +Sextern "C++" inline void *memchr(void * __s, int __c, size_t __n) +S { return const_cast(memchr(const_cast(__s), __c, __n)); } +N#else +Nextern _ARMABI void *memchr(const void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) void *memchr(const void * , int , size_t ) __attribute__((__nonnull__(1))); +N#endif +N /* +N * locates the first occurence of c (converted to an unsigned char) in the +N * initial n characters (each interpreted as unsigned char) of the object +N * pointed to by s. +N * Returns: a pointer to the located character, or a null pointer if the +N * character does not occur in the object. +N */ +N +N#ifdef __cplusplus +Sextern _ARMABI const char *strchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); +Sextern "C++" char *strchr(char * __s, int __c) __attribute__((__nonnull__(1))); +Sextern "C++" inline char *strchr(char * __s, int __c) +S { return const_cast(strchr(const_cast(__s), __c)); } +N#else +Nextern _ARMABI char *strchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) char *strchr(const char * , int ) __attribute__((__nonnull__(1))); +N#endif +N /* +N * locates the first occurence of c (converted to an char) in the string +N * pointed to by s (including the terminating null character). +N * Returns: a pointer to the located character, or a null pointer if the +N * character does not occur in the string. +N */ +N +Nextern _ARMABI size_t strcspn(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) size_t strcspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * computes the length of the initial segment of the string pointed to by s1 +N * which consists entirely of characters not from the string pointed to by +N * s2. The terminating null character is not considered part of s2. +N * Returns: the length of the segment. +N */ +N +N#ifdef __cplusplus +Sextern _ARMABI const char *strpbrk(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Sextern "C++" char *strpbrk(char * __s1, const char * __s2) __attribute__((__nonnull__(1,2))); +Sextern "C++" inline char *strpbrk(char * __s1, const char * __s2) +S { return const_cast(strpbrk(const_cast(__s1), __s2)); } +N#else +Nextern _ARMABI char *strpbrk(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strpbrk(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N#endif +N /* +N * locates the first occurence in the string pointed to by s1 of any +N * character from the string pointed to by s2. +N * Returns: returns a pointer to the character, or a null pointer if no +N * character form s2 occurs in s1. +N */ +N +N#ifdef __cplusplus +Sextern _ARMABI const char *strrchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); +Sextern "C++" char *strrchr(char * __s, int __c) __attribute__((__nonnull__(1))); +Sextern "C++" inline char *strrchr(char * __s, int __c) +S { return const_cast(strrchr(const_cast(__s), __c)); } +N#else +Nextern _ARMABI char *strrchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) char *strrchr(const char * , int ) __attribute__((__nonnull__(1))); +N#endif +N /* +N * locates the last occurence of c (converted to a char) in the string +N * pointed to by s. The terminating null character is considered part of +N * the string. +N * Returns: returns a pointer to the character, or a null pointer if c does +N * not occur in the string. +N */ +N +Nextern _ARMABI size_t strspn(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) size_t strspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * computes the length of the initial segment of the string pointed to by s1 +N * which consists entirely of characters from the string pointed to by S2 +N * Returns: the length of the segment. +N */ +N +N#ifdef __cplusplus +Sextern _ARMABI const char *strstr(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Sextern "C++" char *strstr(char * __s1, const char * __s2) __attribute__((__nonnull__(1,2))); +Sextern "C++" inline char *strstr(char * __s1, const char * __s2) +S { return const_cast(strstr(const_cast(__s1), __s2)); } +N#else +Nextern _ARMABI char *strstr(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strstr(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N#endif +N /* +N * locates the first occurence in the string pointed to by s1 of the +N * sequence of characters (excluding the terminating null character) in the +N * string pointed to by s2. +N * Returns: a pointer to the located string, or a null pointer if the string +N * is not found. +N */ +N +Nextern _ARMABI char *strtok(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) char *strtok(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(2))); +Nextern _ARMABI char *_strtok_r(char * /*s1*/, const char * /*s2*/, char ** /*ptr*/) __attribute__((__nonnull__(2,3))); +Xextern __declspec(__nothrow) char *_strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); +N#ifndef __STRICT_ANSI__ +Nextern _ARMABI char *strtok_r(char * /*s1*/, const char * /*s2*/, char ** /*ptr*/) __attribute__((__nonnull__(2,3))); +Xextern __declspec(__nothrow) char *strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); +N#endif +N /* +N * A sequence of calls to the strtok function breaks the string pointed to +N * by s1 into a sequence of tokens, each of which is delimited by a +N * character from the string pointed to by s2. The first call in the +N * sequence has s1 as its first argument, and is followed by calls with a +N * null pointer as their first argument. The separator string pointed to by +N * s2 may be different from call to call. +N * The first call in the sequence searches for the first character that is +N * not contained in the current separator string s2. If no such character +N * is found, then there are no tokens in s1 and the strtok function returns +N * a null pointer. If such a character is found, it is the start of the +N * first token. +N * The strtok function then searches from there for a character that is +N * contained in the current separator string. If no such character is found, +N * the current token extends to the end of the string pointed to by s1, and +N * subsequent searches for a token will fail. If such a character is found, +N * it is overwritten by a null character, which terminates the current +N * token. The strtok function saves a pointer to the following character, +N * from which the next search for a token will start. +N * Each subsequent call, with a null pointer as the value for the first +N * argument, starts searching from the saved pointer and behaves as +N * described above. +N * Returns: pointer to the first character of a token, or a null pointer if +N * there is no token. +N * +N * strtok_r() is a common extension which works exactly like +N * strtok(), but instead of storing its state in a hidden +N * library variable, requires the user to pass in a pointer to a +N * char * variable which will be used instead. Any sequence of +N * calls to strtok_r() passing the same char ** pointer should +N * behave exactly like the corresponding sequence of calls to +N * strtok(). This means that strtok_r() can safely be used in +N * multi-threaded programs, and also that you can tokenise two +N * strings in parallel. +N */ +N +Nextern _ARMABI void *memset(void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) void *memset(void * , int , size_t ) __attribute__((__nonnull__(1))); +N /* +N * copies the value of c (converted to an unsigned char) into each of the +N * first n charactes of the object pointed to by s. +N * Returns: the value of s. +N */ +Nextern _ARMABI char *strerror(int /*errnum*/); +Xextern __declspec(__nothrow) char *strerror(int ); +N /* +N * maps the error number in errnum to an error message string. +N * Returns: a pointer to the string, the contents of which are +N * implementation-defined. The array pointed to shall not be +N * modified by the program, but may be overwritten by a +N * subsequent call to the strerror function. +N */ +Nextern _ARMABI size_t strlen(const char * /*s*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) size_t strlen(const char * ) __attribute__((__nonnull__(1))); +N /* +N * computes the length of the string pointed to by s. +N * Returns: the number of characters that precede the terminating null +N * character. +N */ +N +Nextern _ARMABI size_t strlcpy(char * /*dst*/, const char * /*src*/, size_t /*len*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) size_t strlcpy(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * copies the string src into the string dst, using no more than +N * len bytes of dst. Always null-terminates dst _within the +N * length len (i.e. will copy at most len-1 bytes of string plus +N * a NUL), unless len is actually zero. +N * +N * Return value is the length of the string that _would_ have +N * been written, i.e. the length of src. Thus, the operation +N * succeeded without truncation if and only if ret < len; +N * otherwise, the value in ret tells you how big to make dst if +N * you decide to reallocate it. (That value does _not_ include +N * the NUL.) +N * +N * This is a BSD-derived library extension, which we are +N * permitted to declare in a standard header because ISO defines +N * function names beginning with 'str' as reserved for future +N * expansion of . +N */ +N +Nextern _ARMABI size_t strlcat(char * /*dst*/, const char * /*src*/, size_t /*len*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) size_t strlcat(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * concatenates the string src to the string dst, using no more +N * than len bytes of dst. Always null-terminates dst _within the +N * length len (i.e. will copy at most len-1 bytes of string plus +N * a NUL), unless len is actually zero. +N * +N * Return value is the length of the string that _would_ have +N * been written, i.e. the length of src plus the original length +N * of dst. Thus, the operation succeeded without truncation if +N * and only if ret < len; otherwise, the value in ret tells you +N * how big to make dst if you decide to reallocate it. (That +N * value does _not_ include the NUL.) +N * +N * If no NUL is encountered within the first len bytes of dst, +N * then the length of dst is considered to have been equal to +N * len for the purposes of the return value (as if there were a +N * NUL at dst[len]). Thus, the return value in this case is len +N * + strlen(src). +N * +N * This is a BSD-derived library extension, which we are +N * permitted to declare in a standard header because ISO defines +N * function names beginning with 'str' as reserved for future +N * expansion of . +N */ +N +Nextern _ARMABI void _membitcpybl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpybl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpybb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpybb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpyhl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpyhl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpyhb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpyhb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpywl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpywl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpywb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpywb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovebl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovebl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovebb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovebb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovehl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovehl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovehb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovehb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovewl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovewl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovewb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovewb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * Copies or moves a piece of memory from one place to another, +N * with one-bit granularity. So you can start or finish a copy +N * part way through a byte, and you can copy between regions +N * with different alignment within a byte. +N * +N * All these functions have the same prototype: two void * +N * pointers for destination and source, then two integers +N * giving the bit offset from those pointers, and finally the +N * number of bits to copy. +N * +N * Just like memcpy and memmove, the "cpy" functions copy as +N * fast as they can in the assumption that the memory regions +N * do not overlap, while the "move" functions cope correctly +N * with overlap. +N * +N * Treating memory as a stream of individual bits requires +N * defining a convention about what order those bits are +N * considered to be arranged in. The above functions support +N * multiple conventions: +N * +N * - the "bl" functions consider the unit of memory to be the +N * byte, and consider the bits within each byte to be +N * arranged in little-endian fashion, so that the LSB comes +N * first. (For example, membitcpybl(a,b,0,7,1) would copy +N * the MSB of the byte at b to the LSB of the byte at a.) +N * +N * - the "bb" functions consider the unit of memory to be the +N * byte, and consider the bits within each byte to be +N * arranged in big-endian fashion, so that the MSB comes +N * first. +N * +N * - the "hl" functions consider the unit of memory to be the +N * 16-bit halfword, and consider the bits within each word +N * to be arranged in little-endian fashion. +N * +N * - the "hb" functions consider the unit of memory to be the +N * 16-bit halfword, and consider the bits within each word +N * to be arranged in big-endian fashion. +N * +N * - the "wl" functions consider the unit of memory to be the +N * 32-bit word, and consider the bits within each word to be +N * arranged in little-endian fashion. +N * +N * - the "wb" functions consider the unit of memory to be the +N * 32-bit word, and consider the bits within each word to be +N * arranged in big-endian fashion. +N */ +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif /* __cplusplus */ +N #endif /* __STRING_DECLS */ +N +N #ifdef __cplusplus +S #ifndef __STRING_NO_EXPORTS +S using ::std::size_t; +S using ::std::memcpy; +S using ::std::memmove; +S using ::std::strcpy; +S using ::std::strncpy; +S using ::std::strcat; +S using ::std::strncat; +S using ::std::memcmp; +S using ::std::strcmp; +S using ::std::strncmp; +S using ::std::strcasecmp; +S using ::std::strncasecmp; +S using ::std::strcoll; +S using ::std::strxfrm; +S using ::std::memchr; +S using ::std::strchr; +S using ::std::strcspn; +S using ::std::strpbrk; +S using ::std::strrchr; +S using ::std::strspn; +S using ::std::strstr; +S using ::std::strtok; +S#ifndef __STRICT_ANSI__ +S using ::std::strtok_r; +S#endif +S using ::std::_strtok_r; +S using ::std::memset; +S using ::std::strerror; +S using ::std::strlen; +S using ::std::strlcpy; +S using ::std::strlcat; +S using ::std::_membitcpybl; +S using ::std::_membitcpybb; +S using ::std::_membitcpyhl; +S using ::std::_membitcpyhb; +S using ::std::_membitcpywl; +S using ::std::_membitcpywb; +S using ::std::_membitmovebl; +S using ::std::_membitmovebb; +S using ::std::_membitmovehl; +S using ::std::_membitmovehb; +S using ::std::_membitmovewl; +S using ::std::_membitmovewb; +S #endif /* __STRING_NO_EXPORTS */ +N #endif /* __cplusplus */ +N +N#endif +N +N/* end of string.h */ +N +L 3 "..\..\src\app\main.c" 2 +N#include +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h" 1 +N/* stdlib.h: ANSI draft (X3J11 May 88) library header, section 4.10 */ +N/* Copyright (C) Codemist Ltd., 1988-1993. */ +N/* Copyright 1991-1998,2014 ARM Limited. All rights reserved. */ +N/* +N * RCS $Revision$ +N * Checkin $Date$ +N * Revising $Author: agrant $ +N */ +N +N/* +N * stdlib.h declares four types, several general purpose functions, +N * and defines several macros. +N */ +N +N#ifndef __stdlib_h +N#define __stdlib_h +N#define __ARMCLIB_VERSION 5060037 +N +N#if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__)) +X#if 0L || (1L && !0L) +N /* armclang and non-strict armcc allow 'long long' in system headers */ +N #define __LONGLONG long long +N#else +S /* strict armcc has '__int64' */ +S #define __LONGLONG __int64 +N#endif +N +N#define _ARMABI __declspec(__nothrow) +N#define _ARMABI_PURE __declspec(__nothrow) __attribute__((const)) +N#define _ARMABI_NORETURN __declspec(__nothrow) __declspec(__noreturn) +N#define _ARMABI_THROW +N +N #ifndef __STDLIB_DECLS +N #define __STDLIB_DECLS +N +N /* +N * Some of these declarations are new in C99. To access them in C++ +N * you can use -D__USE_C99_STDLIB (or -D__USE_C99ALL). +N */ +N #ifndef __USE_C99_STDLIB +N #if defined(__USE_C99_ALL) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) +X #if 0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus) +N #define __USE_C99_STDLIB 1 +N #endif +N #endif +N +N #undef __CLIBNS +N +N #ifdef __cplusplus +S namespace std { +S #define __CLIBNS ::std:: +S extern "C" { +N #else +N #define __CLIBNS +N #endif /* __cplusplus */ +N +N#if defined(__cplusplus) || !defined(__STRICT_ANSI__) +X#if 0L || !0L +N /* unconditional in C++ and non-strict C for consistency of debug info */ +N #if __sizeof_ptr == 8 +X #if 4 == 8 +S typedef unsigned long size_t; /* see */ +N #else +N typedef unsigned int size_t; /* see */ +N #endif +N#elif !defined(__size_t) +X#elif !0L +S #define __size_t 1 +S #if __sizeof_ptr == 8 +S typedef unsigned long size_t; /* see */ +S #else +S typedef unsigned int size_t; /* see */ +S #endif +N#endif +N +N#undef NULL +N#define NULL 0 /* see */ +N +N#ifndef __cplusplus /* wchar_t is a builtin type for C++ */ +N #if !defined(__STRICT_ANSI__) +X #if !0L +N /* unconditional in non-strict C for consistency of debug info */ +N #if defined(__WCHAR32) || (defined(__ARM_SIZEOF_WCHAR_T) && __ARM_SIZEOF_WCHAR_T == 4) +X #if 0L || (0L && __ARM_SIZEOF_WCHAR_T == 4) +S typedef unsigned int wchar_t; /* see */ +N #else +N typedef unsigned short wchar_t; /* see */ +N #endif +N #elif !defined(__wchar_t) +X #elif !0L +S #define __wchar_t 1 +S #if defined(__WCHAR32) || (defined(__ARM_SIZEOF_WCHAR_T) && __ARM_SIZEOF_WCHAR_T == 4) +S typedef unsigned int wchar_t; /* see */ +S #else +S typedef unsigned short wchar_t; /* see */ +S #endif +N #endif +N#endif +N +Ntypedef struct div_t { int quot, rem; } div_t; +N /* type of the value returned by the div function. */ +Ntypedef struct ldiv_t { long int quot, rem; } ldiv_t; +N /* type of the value returned by the ldiv function. */ +N#if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB +X#if !0L || 1 +Ntypedef struct lldiv_t { __LONGLONG quot, rem; } lldiv_t; +Xtypedef struct lldiv_t { long long quot, rem; } lldiv_t; +N /* type of the value returned by the lldiv function. */ +N#endif +N +N#ifdef __EXIT_FAILURE +S# define EXIT_FAILURE __EXIT_FAILURE +S /* +S * an integral expression which may be used as an argument to the exit +S * function to return unsuccessful termination status to the host +S * environment. +S */ +N#else +N# define EXIT_FAILURE 1 /* unixoid */ +N#endif +N#define EXIT_SUCCESS 0 +N /* +N * an integral expression which may be used as an argument to the exit +N * function to return successful termination status to the host +N * environment. +N */ +N +N /* +N * Defining __USE_ANSI_EXAMPLE_RAND at compile time switches to +N * the example implementation of rand() and srand() provided in +N * the ANSI C standard. This implementation is very poor, but is +N * provided for completeness. +N */ +N#ifdef __USE_ANSI_EXAMPLE_RAND +S#define srand _ANSI_srand +S#define rand _ANSI_rand +S#define RAND_MAX 0x7fff +N#else +N#define RAND_MAX 0x7fffffff +N#endif +N /* +N * RAND_MAX: an integral constant expression, the value of which +N * is the maximum value returned by the rand function. +N */ +Nextern _ARMABI int __aeabi_MB_CUR_MAX(void); +Xextern __declspec(__nothrow) int __aeabi_MB_CUR_MAX(void); +N#define MB_CUR_MAX ( __aeabi_MB_CUR_MAX() ) +N /* +N * a positive integer expression whose value is the maximum number of bytes +N * in a multibyte character for the extended character set specified by the +N * current locale (category LC_CTYPE), and whose value is never greater +N * than MB_LEN_MAX. +N */ +N +N /* +N * If the compiler supports signalling nans as per N965 then it +N * will define __SUPPORT_SNAN__, in which case a user may define +N * _WANT_SNAN in order to obtain a compliant version of the strtod +N * family of functions. +N */ +N#if defined(__SUPPORT_SNAN__) && defined(_WANT_SNAN) +X#if 0L && 0L +S#pragma import(__use_snan) +N#endif +N +Nextern _ARMABI double atof(const char * /*nptr*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) double atof(const char * ) __attribute__((__nonnull__(1))); +N /* +N * converts the initial part of the string pointed to by nptr to double +N * representation. +N * Returns: the converted value. +N */ +Nextern _ARMABI int atoi(const char * /*nptr*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int atoi(const char * ) __attribute__((__nonnull__(1))); +N /* +N * converts the initial part of the string pointed to by nptr to int +N * representation. +N * Returns: the converted value. +N */ +Nextern _ARMABI long int atol(const char * /*nptr*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) long int atol(const char * ) __attribute__((__nonnull__(1))); +N /* +N * converts the initial part of the string pointed to by nptr to long int +N * representation. +N * Returns: the converted value. +N */ +N#if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB +X#if !0L || 1 +Nextern _ARMABI __LONGLONG atoll(const char * /*nptr*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) long long atoll(const char * ) __attribute__((__nonnull__(1))); +N /* +N * converts the initial part of the string pointed to by nptr to +N * long long int representation. +N * Returns: the converted value. +N */ +N#endif +N +Nextern _ARMABI double strtod(const char * __restrict /*nptr*/, char ** __restrict /*endptr*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) double strtod(const char * __restrict , char ** __restrict ) __attribute__((__nonnull__(1))); +N /* +N * converts the initial part of the string pointed to by nptr to double +N * representation. First it decomposes the input string into three parts: +N * an initial, possibly empty, sequence of white-space characters (as +N * specified by the isspace function), a subject sequence resembling a +N * floating point constant; and a final string of one or more unrecognised +N * characters, including the terminating null character of the input string. +N * Then it attempts to convert the subject sequence to a floating point +N * number, and returns the result. A pointer to the final string is stored +N * in the object pointed to by endptr, provided that endptr is not a null +N * pointer. +N * Returns: the converted value if any. If no conversion could be performed, +N * zero is returned. If the correct value is outside the range of +N * representable values, plus or minus HUGE_VAL is returned +N * (according to the sign of the value), and the value of the macro +N * ERANGE is stored in errno. If the correct value would cause +N * underflow, zero is returned and the value of the macro ERANGE is +N * stored in errno. +N */ +N#if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB +X#if !0L || 1 +Nextern _ARMABI float strtof(const char * __restrict /*nptr*/, char ** __restrict /*endptr*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) float strtof(const char * __restrict , char ** __restrict ) __attribute__((__nonnull__(1))); +Nextern _ARMABI long double strtold(const char * __restrict /*nptr*/, char ** __restrict /*endptr*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) long double strtold(const char * __restrict , char ** __restrict ) __attribute__((__nonnull__(1))); +N /* +N * same as strtod, but return float and long double respectively. +N */ +N#endif +Nextern _ARMABI long int strtol(const char * __restrict /*nptr*/, +Xextern __declspec(__nothrow) long int strtol(const char * __restrict , +N char ** __restrict /*endptr*/, int /*base*/) __attribute__((__nonnull__(1))); +N /* +N * converts the initial part of the string pointed to by nptr to long int +N * representation. First it decomposes the input string into three parts: +N * an initial, possibly empty, sequence of white-space characters (as +N * specified by the isspace function), a subject sequence resembling an +N * integer represented in some radix determined by the value of base, and a +N * final string of one or more unrecognised characters, including the +N * terminating null character of the input string. Then it attempts to +N * convert the subject sequence to an integer, and returns the result. +N * If the value of base is 0, the expected form of the subject sequence is +N * that of an integer constant (described in ANSI Draft, section 3.1.3.2), +N * optionally preceded by a '+' or '-' sign, but not including an integer +N * suffix. If the value of base is between 2 and 36, the expected form of +N * the subject sequence is a sequence of letters and digits representing an +N * integer with the radix specified by base, optionally preceded by a plus +N * or minus sign, but not including an integer suffix. The letters from a +N * (or A) through z (or Z) are ascribed the values 10 to 35; only letters +N * whose ascribed values are less than that of the base are permitted. If +N * the value of base is 16, the characters 0x or 0X may optionally precede +N * the sequence of letters and digits following the sign if present. +N * A pointer to the final string is stored in the object +N * pointed to by endptr, provided that endptr is not a null pointer. +N * Returns: the converted value if any. If no conversion could be performed, +N * zero is returned and nptr is stored in *endptr. +N * If the correct value is outside the range of +N * representable values, LONG_MAX or LONG_MIN is returned +N * (according to the sign of the value), and the value of the +N * macro ERANGE is stored in errno. +N */ +Nextern _ARMABI unsigned long int strtoul(const char * __restrict /*nptr*/, +Xextern __declspec(__nothrow) unsigned long int strtoul(const char * __restrict , +N char ** __restrict /*endptr*/, int /*base*/) __attribute__((__nonnull__(1))); +N /* +N * converts the initial part of the string pointed to by nptr to unsigned +N * long int representation. First it decomposes the input string into three +N * parts: an initial, possibly empty, sequence of white-space characters (as +N * determined by the isspace function), a subject sequence resembling an +N * unsigned integer represented in some radix determined by the value of +N * base, and a final string of one or more unrecognised characters, +N * including the terminating null character of the input string. Then it +N * attempts to convert the subject sequence to an unsigned integer, and +N * returns the result. If the value of base is zero, the expected form of +N * the subject sequence is that of an integer constant (described in ANSI +N * Draft, section 3.1.3.2), optionally preceded by a '+' or '-' sign, but +N * not including an integer suffix. If the value of base is between 2 and +N * 36, the expected form of the subject sequence is a sequence of letters +N * and digits representing an integer with the radix specified by base, +N * optionally preceded by a '+' or '-' sign, but not including an integer +N * suffix. The letters from a (or A) through z (or Z) stand for the values +N * 10 to 35; only letters whose ascribed values are less than that of the +N * base are permitted. If the value of base is 16, the characters 0x or 0X +N * may optionally precede the sequence of letters and digits following the +N * sign, if present. A pointer to the final string is stored in the object +N * pointed to by endptr, provided that endptr is not a null pointer. +N * Returns: the converted value if any. If no conversion could be performed, +N * zero is returned and nptr is stored in *endptr. +N * If the correct value is outside the range of +N * representable values, ULONG_MAX is returned, and the value of +N * the macro ERANGE is stored in errno. +N */ +N +N/* C90 reserves all names beginning with 'str' */ +Nextern _ARMABI __LONGLONG strtoll(const char * __restrict /*nptr*/, +Xextern __declspec(__nothrow) long long strtoll(const char * __restrict , +N char ** __restrict /*endptr*/, int /*base*/) +N __attribute__((__nonnull__(1))); +N /* +N * as strtol but returns a long long int value. If the correct value is +N * outside the range of representable values, LLONG_MAX or LLONG_MIN is +N * returned (according to the sign of the value), and the value of the +N * macro ERANGE is stored in errno. +N */ +Nextern _ARMABI unsigned __LONGLONG strtoull(const char * __restrict /*nptr*/, +Xextern __declspec(__nothrow) unsigned long long strtoull(const char * __restrict , +N char ** __restrict /*endptr*/, int /*base*/) +N __attribute__((__nonnull__(1))); +N /* +N * as strtoul but returns an unsigned long long int value. If the correct +N * value is outside the range of representable values, ULLONG_MAX is returned, +N * and the value of the macro ERANGE is stored in errno. +N */ +N +Nextern _ARMABI int rand(void); +Xextern __declspec(__nothrow) int rand(void); +N /* +N * Computes a sequence of pseudo-random integers in the range 0 to RAND_MAX. +N * Uses an additive generator (Mitchell & Moore) of the form: +N * Xn = (X[n-24] + X[n-55]) MOD 2^31 +N * This is described in section 3.2.2 of Knuth, vol 2. It's period is +N * in excess of 2^55 and its randomness properties, though unproven, are +N * conjectured to be good. Empirical testing since 1958 has shown no flaws. +N * Returns: a pseudo-random integer. +N */ +Nextern _ARMABI void srand(unsigned int /*seed*/); +Xextern __declspec(__nothrow) void srand(unsigned int ); +N /* +N * uses its argument as a seed for a new sequence of pseudo-random numbers +N * to be returned by subsequent calls to rand. If srand is then called with +N * the same seed value, the sequence of pseudo-random numbers is repeated. +N * If rand is called before any calls to srand have been made, the same +N * sequence is generated as when srand is first called with a seed value +N * of 1. +N */ +N +Nstruct _rand_state { int __x[57]; }; +Nextern _ARMABI int _rand_r(struct _rand_state *); +Xextern __declspec(__nothrow) int _rand_r(struct _rand_state *); +Nextern _ARMABI void _srand_r(struct _rand_state *, unsigned int); +Xextern __declspec(__nothrow) void _srand_r(struct _rand_state *, unsigned int); +Nstruct _ANSI_rand_state { int __x[1]; }; +Nextern _ARMABI int _ANSI_rand_r(struct _ANSI_rand_state *); +Xextern __declspec(__nothrow) int _ANSI_rand_r(struct _ANSI_rand_state *); +Nextern _ARMABI void _ANSI_srand_r(struct _ANSI_rand_state *, unsigned int); +Xextern __declspec(__nothrow) void _ANSI_srand_r(struct _ANSI_rand_state *, unsigned int); +N /* +N * Re-entrant variants of both flavours of rand, which operate on +N * an explicitly supplied state buffer. +N */ +N +Nextern _ARMABI void *calloc(size_t /*nmemb*/, size_t /*size*/); +Xextern __declspec(__nothrow) void *calloc(size_t , size_t ); +N /* +N * allocates space for an array of nmemb objects, each of whose size is +N * 'size'. The space is initialised to all bits zero. +N * Returns: either a null pointer or a pointer to the allocated space. +N */ +Nextern _ARMABI void free(void * /*ptr*/); +Xextern __declspec(__nothrow) void free(void * ); +N /* +N * causes the space pointed to by ptr to be deallocated (i.e., made +N * available for further allocation). If ptr is a null pointer, no action +N * occurs. Otherwise, if ptr does not match a pointer earlier returned by +N * calloc, malloc or realloc or if the space has been deallocated by a call +N * to free or realloc, the behaviour is undefined. +N */ +Nextern _ARMABI void *malloc(size_t /*size*/); +Xextern __declspec(__nothrow) void *malloc(size_t ); +N /* +N * allocates space for an object whose size is specified by 'size' and whose +N * value is indeterminate. +N * Returns: either a null pointer or a pointer to the allocated space. +N */ +Nextern _ARMABI void *realloc(void * /*ptr*/, size_t /*size*/); +Xextern __declspec(__nothrow) void *realloc(void * , size_t ); +N /* +N * changes the size of the object pointed to by ptr to the size specified by +N * size. The contents of the object shall be unchanged up to the lesser of +N * the new and old sizes. If the new size is larger, the value of the newly +N * allocated portion of the object is indeterminate. If ptr is a null +N * pointer, the realloc function behaves like a call to malloc for the +N * specified size. Otherwise, if ptr does not match a pointer earlier +N * returned by calloc, malloc or realloc, or if the space has been +N * deallocated by a call to free or realloc, the behaviour is undefined. +N * If the space cannot be allocated, the object pointed to by ptr is +N * unchanged. If size is zero and ptr is not a null pointer, the object it +N * points to is freed. +N * Returns: either a null pointer or a pointer to the possibly moved +N * allocated space. +N */ +N#if !defined(__STRICT_ANSI__) +X#if !0L +Nextern _ARMABI int posix_memalign(void ** /*ret*/, size_t /*alignment*/, size_t /*size*/); +Xextern __declspec(__nothrow) int posix_memalign(void ** , size_t , size_t ); +N /* +N * allocates space for an object of size 'size', aligned to a +N * multiple of 'alignment' (which must be a power of two and at +N * least 4). +N * +N * On success, a pointer to the allocated object is stored in +N * *ret, and zero is returned. On failure, the return value is +N * either ENOMEM (allocation failed because no suitable piece of +N * memory was available) or EINVAL (the 'alignment' parameter was +N * invalid). +N */ +N#endif +Ntypedef int (*__heapprt)(void *, char const *, ...); +Nextern _ARMABI void __heapstats(int (* /*dprint*/)(void * /*param*/, +Xextern __declspec(__nothrow) void __heapstats(int (* )(void * , +N char const * /*format*/, ...), +N void * /*param*/) __attribute__((__nonnull__(1))); +N /* +N * reports current heap statistics (eg. number of free blocks in +N * the free-list). Output is as implementation-defined free-form +N * text, provided via the dprint function. `param' gives an +N * extra data word to pass to dprint. You can call +N * __heapstats(fprintf,stdout) by casting fprintf to the above +N * function type; the typedef `__heapprt' is provided for this +N * purpose. +N * +N * `dprint' will not be called while the heap is being examined, +N * so it can allocate memory itself without trouble. +N */ +Nextern _ARMABI int __heapvalid(int (* /*dprint*/)(void * /*param*/, +Xextern __declspec(__nothrow) int __heapvalid(int (* )(void * , +N char const * /*format*/, ...), +N void * /*param*/, int /*verbose*/) __attribute__((__nonnull__(1))); +N /* +N * performs a consistency check on the heap. Errors are reported +N * through dprint, like __heapstats. If `verbose' is nonzero, +N * full diagnostic information on the heap state is printed out. +N * +N * This routine probably won't work if the heap isn't a +N * contiguous chunk (for example, if __user_heap_extend has been +N * overridden). +N * +N * `dprint' may be called while the heap is being examined or +N * even in an invalid state, so it must perform no memory +N * allocation. In particular, if `dprint' calls (or is) a stdio +N * function, the stream it outputs to must already have either +N * been written to or been setvbuf'ed, or else the system will +N * allocate buffer space for it on the first call to dprint. +N */ +Nextern _ARMABI_NORETURN void abort(void); +Xextern __declspec(__nothrow) __declspec(__noreturn) void abort(void); +N /* +N * causes abnormal program termination to occur, unless the signal SIGABRT +N * is being caught and the signal handler does not return. Whether open +N * output streams are flushed or open streams are closed or temporary +N * files removed is implementation-defined. +N * An implementation-defined form of the status 'unsuccessful termination' +N * is returned to the host environment by means of a call to +N * raise(SIGABRT). +N */ +N +Nextern _ARMABI int atexit(void (* /*func*/)(void)) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) int atexit(void (* )(void)) __attribute__((__nonnull__(1))); +N /* +N * registers the function pointed to by func, to be called without its +N * arguments at normal program termination. It is possible to register at +N * least 32 functions. +N * Returns: zero if the registration succeeds, nonzero if it fails. +N */ +N#if defined(__EDG__) && !defined(__GNUC__) +X#if 1L && !1L +S#define __LANGUAGE_LINKAGE_CHANGES_FUNCTION_TYPE +N#endif +N#if defined(__cplusplus) && defined(__LANGUAGE_LINKAGE_CHANGES_FUNCTION_TYPE) +X#if 0L && 0L +S /* atexit that takes a ptr to a function with C++ linkage +S * but not in GNU mode +S */ +S typedef void (* __C_exitfuncptr)(); +S extern "C++" +S inline int atexit(void (* __func)()) { +S return atexit((__C_exitfuncptr)__func); +S } +N#endif +N +N +Nextern _ARMABI_NORETURN void exit(int /*status*/); +Xextern __declspec(__nothrow) __declspec(__noreturn) void exit(int ); +N /* +N * causes normal program termination to occur. If more than one call to the +N * exit function is executed by a program, the behaviour is undefined. +N * First, all functions registered by the atexit function are called, in the +N * reverse order of their registration. +N * Next, all open output streams are flushed, all open streams are closed, +N * and all files created by the tmpfile function are removed. +N * Finally, control is returned to the host environment. If the value of +N * status is zero or EXIT_SUCCESS, an implementation-defined form of the +N * status 'successful termination' is returned. If the value of status is +N * EXIT_FAILURE, an implementation-defined form of the status +N * 'unsuccessful termination' is returned. Otherwise the status returned +N * is implementation-defined. +N */ +N +Nextern _ARMABI_NORETURN void _Exit(int /*status*/); +Xextern __declspec(__nothrow) __declspec(__noreturn) void _Exit(int ); +N /* +N * causes normal program termination to occur. No functions registered +N * by the atexit function are called. +N * In this implementation, all open output streams are flushed, all +N * open streams are closed, and all files created by the tmpfile function +N * are removed. +N * Control is returned to the host environment. The status returned to +N * the host environment is determined in the same way as for 'exit'. +N */ +N +Nextern _ARMABI char *getenv(const char * /*name*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) char *getenv(const char * ) __attribute__((__nonnull__(1))); +N /* +N * searches the environment list, provided by the host environment, for a +N * string that matches the string pointed to by name. The set of environment +N * names and the method for altering the environment list are +N * implementation-defined. +N * Returns: a pointer to a string associated with the matched list member. +N * The array pointed to shall not be modified by the program, but +N * may be overwritten by a subsequent call to the getenv function. +N * If the specified name cannot be found, a null pointer is +N * returned. +N */ +N +Nextern _ARMABI int system(const char * /*string*/); +Xextern __declspec(__nothrow) int system(const char * ); +N /* +N * passes the string pointed to by string to the host environment to be +N * executed by a command processor in an implementation-defined manner. +N * A null pointer may be used for string, to inquire whether a command +N * processor exists. +N * +N * Returns: If the argument is a null pointer, the system function returns +N * non-zero only if a command processor is available. If the +N * argument is not a null pointer, the system function returns an +N * implementation-defined value. +N */ +N +Nextern _ARMABI_THROW void *bsearch(const void * /*key*/, const void * /*base*/, +Xextern void *bsearch(const void * , const void * , +N size_t /*nmemb*/, size_t /*size*/, +N int (* /*compar*/)(const void *, const void *)) __attribute__((__nonnull__(1,2,5))); +N /* +N * searches an array of nmemb objects, the initial member of which is +N * pointed to by base, for a member that matches the object pointed to by +N * key. The size of each member of the array is specified by size. +N * The contents of the array shall be in ascending sorted order according to +N * a comparison function pointed to by compar, which is called with two +N * arguments that point to the key object and to an array member, in that +N * order. The function shall return an integer less than, equal to, or +N * greater than zero if the key object is considered, respectively, to be +N * less than, to match, or to be greater than the array member. +N * Returns: a pointer to a matching member of the array, or a null pointer +N * if no match is found. If two members compare as equal, which +N * member is matched is unspecified. +N */ +N#if defined(__cplusplus) && defined(__LANGUAGE_LINKAGE_CHANGES_FUNCTION_TYPE) +X#if 0L && 0L +S /* bsearch that takes a ptr to a function with C++ linkage +S * but not in GNU mode +S */ +S typedef int (* __C_compareprocptr)(const void *, const void *); +S extern "C++" +S void *bsearch(const void * __key, const void * __base, +S size_t __nmemb, size_t __size, +S int (* __compar)(const void *, const void *)) __attribute__((__nonnull__(1,2,5))); +S extern "C++" +S inline void *bsearch(const void * __key, const void * __base, +S size_t __nmemb, size_t __size, +S int (* __compar)(const void *, const void *)) { +S return bsearch(__key, __base, __nmemb, __size, (__C_compareprocptr)__compar); +S } +N#endif +N +N +Nextern _ARMABI_THROW void qsort(void * /*base*/, size_t /*nmemb*/, size_t /*size*/, +Xextern void qsort(void * , size_t , size_t , +N int (* /*compar*/)(const void *, const void *)) __attribute__((__nonnull__(1,4))); +N /* +N * sorts an array of nmemb objects, the initial member of which is pointed +N * to by base. The size of each object is specified by size. +N * The contents of the array shall be in ascending order according to a +N * comparison function pointed to by compar, which is called with two +N * arguments that point to the objects being compared. The function shall +N * return an integer less than, equal to, or greater than zero if the first +N * argument is considered to be respectively less than, equal to, or greater +N * than the second. If two members compare as equal, their order in the +N * sorted array is unspecified. +N */ +N +N#if defined(__cplusplus) && defined(__LANGUAGE_LINKAGE_CHANGES_FUNCTION_TYPE) +X#if 0L && 0L +S /* qsort that takes a ptr to a function with C++ linkage +S * but not in GNU mode +S */ +S extern "C++" +S void qsort(void * __base, size_t __nmemb, size_t __size, +S int (* __compar)(const void *, const void *)) __attribute__((__nonnull__(1,4))); +S extern "C++" +S inline void qsort(void * __base, size_t __nmemb, size_t __size, +S int (* __compar)(const void *, const void *)) { +S qsort(__base, __nmemb, __size, (__C_compareprocptr)__compar); +S } +N#endif +N +Nextern _ARMABI_PURE int abs(int /*j*/); +Xextern __declspec(__nothrow) __attribute__((const)) int abs(int ); +N /* +N * computes the absolute value of an integer j. If the result cannot be +N * represented, the behaviour is undefined. +N * Returns: the absolute value. +N */ +N +Nextern _ARMABI_PURE div_t div(int /*numer*/, int /*denom*/); +Xextern __declspec(__nothrow) __attribute__((const)) div_t div(int , int ); +N /* +N * computes the quotient and remainder of the division of the numerator +N * numer by the denominator denom. If the division is inexact, the resulting +N * quotient is the integer of lesser magnitude that is the nearest to the +N * algebraic quotient. If the result cannot be represented, the behaviour is +N * undefined; otherwise, quot * denom + rem shall equal numer. +N * Returns: a structure of type div_t, comprising both the quotient and the +N * remainder. the structure shall contain the following members, +N * in either order. +N * int quot; int rem; +N */ +Nextern _ARMABI_PURE long int labs(long int /*j*/); +Xextern __declspec(__nothrow) __attribute__((const)) long int labs(long int ); +N /* +N * computes the absolute value of an long integer j. If the result cannot be +N * represented, the behaviour is undefined. +N * Returns: the absolute value. +N */ +N#ifdef __cplusplus +S extern "C++" inline _ARMABI_PURE long abs(long int x) { return labs(x); } +N#endif +N +Nextern _ARMABI_PURE ldiv_t ldiv(long int /*numer*/, long int /*denom*/); +Xextern __declspec(__nothrow) __attribute__((const)) ldiv_t ldiv(long int , long int ); +N /* +N * computes the quotient and remainder of the division of the numerator +N * numer by the denominator denom. If the division is inexact, the sign of +N * the resulting quotient is that of the algebraic quotient, and the +N * magnitude of the resulting quotient is the largest integer less than the +N * magnitude of the algebraic quotient. If the result cannot be represented, +N * the behaviour is undefined; otherwise, quot * denom + rem shall equal +N * numer. +N * Returns: a structure of type ldiv_t, comprising both the quotient and the +N * remainder. the structure shall contain the following members, +N * in either order. +N * long int quot; long int rem; +N */ +N#ifdef __cplusplus +S extern "C++" inline _ARMABI_PURE ldiv_t div(long int __numer, long int __denom) { +S return ldiv(__numer, __denom); +S } +N#endif +N +N#if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB +X#if !0L || 1 +Nextern _ARMABI_PURE __LONGLONG llabs(__LONGLONG /*j*/); +Xextern __declspec(__nothrow) __attribute__((const)) long long llabs(long long ); +N /* +N * computes the absolute value of a long long integer j. If the +N * result cannot be represented, the behaviour is undefined. +N * Returns: the absolute value. +N */ +N#ifdef __cplusplus +S extern "C++" inline _ARMABI_PURE __LONGLONG abs(__LONGLONG x) { return llabs(x); } +N#endif +N +Nextern _ARMABI_PURE lldiv_t lldiv(__LONGLONG /*numer*/, __LONGLONG /*denom*/); +Xextern __declspec(__nothrow) __attribute__((const)) lldiv_t lldiv(long long , long long ); +N /* +N * computes the quotient and remainder of the division of the numerator +N * numer by the denominator denom. If the division is inexact, the sign of +N * the resulting quotient is that of the algebraic quotient, and the +N * magnitude of the resulting quotient is the largest integer less than the +N * magnitude of the algebraic quotient. If the result cannot be represented, +N * the behaviour is undefined; otherwise, quot * denom + rem shall equal +N * numer. +N * Returns: a structure of type lldiv_t, comprising both the quotient and the +N * remainder. the structure shall contain the following members, +N * in either order. +N * long long quot; long long rem; +N */ +N#ifdef __cplusplus +S extern "C++" inline _ARMABI_PURE lldiv_t div(__LONGLONG __numer, __LONGLONG __denom) { +S return lldiv(__numer, __denom); +S } +N#endif +N#endif +N +N#if !(__ARM_NO_DEPRECATED_FUNCTIONS) +N/* +N * ARM real-time divide functions for guaranteed performance +N */ +Ntypedef struct __sdiv32by16 { int quot, rem; } __sdiv32by16; +Ntypedef struct __udiv32by16 { unsigned int quot, rem; } __udiv32by16; +N /* used int so that values return in separate regs, although 16-bit */ +Ntypedef struct __sdiv64by32 { int rem, quot; } __sdiv64by32; +N +N__value_in_regs extern _ARMABI_PURE __sdiv32by16 __rt_sdiv32by16( +X__value_in_regs extern __declspec(__nothrow) __attribute__((const)) __sdiv32by16 __rt_sdiv32by16( +N int /*numer*/, +N short int /*denom*/); +N /* +N * Signed divide: (16-bit quot), (16-bit rem) = (32-bit) / (16-bit) +N */ +N__value_in_regs extern _ARMABI_PURE __udiv32by16 __rt_udiv32by16( +X__value_in_regs extern __declspec(__nothrow) __attribute__((const)) __udiv32by16 __rt_udiv32by16( +N unsigned int /*numer*/, +N unsigned short /*denom*/); +N /* +N * Unsigned divide: (16-bit quot), (16-bit rem) = (32-bit) / (16-bit) +N */ +N__value_in_regs extern _ARMABI_PURE __sdiv64by32 __rt_sdiv64by32( +X__value_in_regs extern __declspec(__nothrow) __attribute__((const)) __sdiv64by32 __rt_sdiv64by32( +N int /*numer_h*/, unsigned int /*numer_l*/, +N int /*denom*/); +N /* +N * Signed divide: (32-bit quot), (32-bit rem) = (64-bit) / (32-bit) +N */ +N#endif +N +N/* +N * ARM floating-point mask/status function (for both hardfp and softfp) +N */ +Nextern _ARMABI unsigned int __fp_status(unsigned int /*mask*/, unsigned int /*flags*/); +Xextern __declspec(__nothrow) unsigned int __fp_status(unsigned int , unsigned int ); +N /* +N * mask and flags are bit-fields which correspond directly to the +N * floating point status register in the FPE/FPA and fplib. +N * __fp_status returns the current value of the status register, +N * and also sets the writable bits of the word +N * (the exception control and flag bytes) to: +N * +N * new = (old & ~mask) ^ flags; +N */ +N#define __fpsr_IXE 0x100000 +N#define __fpsr_UFE 0x80000 +N#define __fpsr_OFE 0x40000 +N#define __fpsr_DZE 0x20000 +N#define __fpsr_IOE 0x10000 +N +N#define __fpsr_IXC 0x10 +N#define __fpsr_UFC 0x8 +N#define __fpsr_OFC 0x4 +N#define __fpsr_DZC 0x2 +N#define __fpsr_IOC 0x1 +N +N/* +N * Multibyte Character Functions. +N * The behaviour of the multibyte character functions is affected by the +N * LC_CTYPE category of the current locale. For a state-dependent encoding, +N * each function is placed into its initial state by a call for which its +N * character pointer argument, s, is a null pointer. Subsequent calls with s +N * as other than a null pointer cause the internal state of the function to be +N * altered as necessary. A call with s as a null pointer causes these functions +N * to return a nonzero value if encodings have state dependency, and a zero +N * otherwise. After the LC_CTYPE category is changed, the shift state of these +N * functions is indeterminate. +N */ +Nextern _ARMABI int mblen(const char * /*s*/, size_t /*n*/); +Xextern __declspec(__nothrow) int mblen(const char * , size_t ); +N /* +N * If s is not a null pointer, the mblen function determines the number of +N * bytes compromising the multibyte character pointed to by s. Except that +N * the shift state of the mbtowc function is not affected, it is equivalent +N * to mbtowc((wchar_t *)0, s, n); +N * Returns: If s is a null pointer, the mblen function returns a nonzero or +N * zero value, if multibyte character encodings, respectively, do +N * or do not have state-dependent encodings. If s is not a null +N * pointer, the mblen function either returns a 0 (if s points to a +N * null character), or returns the number of bytes that compromise +N * the multibyte character (if the next n of fewer bytes form a +N * valid multibyte character), or returns -1 (they do not form a +N * valid multibyte character). +N */ +Nextern _ARMABI int mbtowc(wchar_t * __restrict /*pwc*/, +Xextern __declspec(__nothrow) int mbtowc(wchar_t * __restrict , +N const char * __restrict /*s*/, size_t /*n*/); +N /* +N * If s is not a null pointer, the mbtowc function determines the number of +N * bytes that compromise the multibyte character pointed to by s. It then +N * determines the code for value of type wchar_t that corresponds to that +N * multibyte character. (The value of the code corresponding to the null +N * character is zero). If the multibyte character is valid and pwc is not a +N * null pointer, the mbtowc function stores the code in the object pointed +N * to by pwc. At most n bytes of the array pointed to by s will be examined. +N * Returns: If s is a null pointer, the mbtowc function returns a nonzero or +N * zero value, if multibyte character encodings, respectively, do +N * or do not have state-dependent encodings. If s is not a null +N * pointer, the mbtowc function either returns a 0 (if s points to +N * a null character), or returns the number of bytes that +N * compromise the converted multibyte character (if the next n of +N * fewer bytes form a valid multibyte character), or returns -1 +N * (they do not form a valid multibyte character). +N */ +Nextern _ARMABI int wctomb(char * /*s*/, wchar_t /*wchar*/); +Xextern __declspec(__nothrow) int wctomb(char * , wchar_t ); +N /* +N * determines the number of bytes need to represent the multibyte character +N * corresponding to the code whose value is wchar (including any change in +N * shift state). It stores the multibyte character representation in the +N * array object pointed to by s (if s is not a null pointer). At most +N * MB_CUR_MAX characters are stored. If the value of wchar is zero, the +N * wctomb function is left in the initial shift state). +N * Returns: If s is a null pointer, the wctomb function returns a nonzero or +N * zero value, if multibyte character encodings, respectively, do +N * or do not have state-dependent encodings. If s is not a null +N * pointer, the wctomb function returns a -1 if the value of wchar +N * does not correspond to a valid multibyte character, or returns +N * the number of bytes that compromise the multibyte character +N * corresponding to the value of wchar. +N */ +N +N/* +N * Multibyte String Functions. +N * The behaviour of the multibyte string functions is affected by the LC_CTYPE +N * category of the current locale. +N */ +Nextern _ARMABI size_t mbstowcs(wchar_t * __restrict /*pwcs*/, +Xextern __declspec(__nothrow) size_t mbstowcs(wchar_t * __restrict , +N const char * __restrict /*s*/, size_t /*n*/) __attribute__((__nonnull__(2))); +N /* +N * converts a sequence of multibyte character that begins in the initial +N * shift state from the array pointed to by s into a sequence of +N * corresponding codes and stores not more than n codes into the array +N * pointed to by pwcs. No multibyte character that follow a null character +N * (which is converted into a code with value zero) will be examined or +N * converted. Each multibyte character is converted as if by a call to +N * mbtowc function, except that the shift state of the mbtowc function is +N * not affected. No more than n elements will be modified in the array +N * pointed to by pwcs. If copying takes place between objects that overlap, +N * the behaviour is undefined. +N * Returns: If an invalid multibyte character is encountered, the mbstowcs +N * function returns (size_t)-1. Otherwise, the mbstowcs function +N * returns the number of array elements modified, not including +N * a terminating zero code, if any. +N */ +Nextern _ARMABI size_t wcstombs(char * __restrict /*s*/, +Xextern __declspec(__nothrow) size_t wcstombs(char * __restrict , +N const wchar_t * __restrict /*pwcs*/, size_t /*n*/) __attribute__((__nonnull__(2))); +N /* +N * converts a sequence of codes that correspond to multibyte characters +N * from the array pointed to by pwcs into a sequence of multibyte +N * characters that begins in the initial shift state and stores these +N * multibyte characters into the array pointed to by s, stopping if a +N * multibyte character would exceed the limit of n total bytes or if a +N * null character is stored. Each code is converted as if by a call to the +N * wctomb function, except that the shift state of the wctomb function is +N * not affected. No more than n elements will be modified in the array +N * pointed to by s. If copying takes place between objects that overlap, +N * the behaviour is undefined. +N * Returns: If a code is encountered that does not correspond to a valid +N * multibyte character, the wcstombs function returns (size_t)-1. +N * Otherwise, the wcstombs function returns the number of bytes +N * modified, not including a terminating null character, if any. +N */ +N +Nextern _ARMABI void __use_realtime_heap(void); +Xextern __declspec(__nothrow) void __use_realtime_heap(void); +Nextern _ARMABI void __use_realtime_division(void); +Xextern __declspec(__nothrow) void __use_realtime_division(void); +Nextern _ARMABI void __use_two_region_memory(void); +Xextern __declspec(__nothrow) void __use_two_region_memory(void); +Nextern _ARMABI void __use_no_heap(void); +Xextern __declspec(__nothrow) void __use_no_heap(void); +Nextern _ARMABI void __use_no_heap_region(void); +Xextern __declspec(__nothrow) void __use_no_heap_region(void); +N +Nextern _ARMABI char const *__C_library_version_string(void); +Xextern __declspec(__nothrow) char const *__C_library_version_string(void); +Nextern _ARMABI int __C_library_version_number(void); +Xextern __declspec(__nothrow) int __C_library_version_number(void); +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif /* __cplusplus */ +N #endif /* __STDLIB_DECLS */ +N +N #if _AEABI_PORTABILITY_LEVEL != 0 && !defined _AEABI_PORTABLE +X #if _AEABI_PORTABILITY_LEVEL != 0 && !0L +S #define _AEABI_PORTABLE +N #endif +N +N #ifdef __cplusplus +S #ifndef __STDLIB_NO_EXPORTS +S #if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB +S using ::std::atoll; +S using ::std::lldiv_t; +S #endif /* !defined(__STRICT_ANSI__) || __USE_C99_STDLIB */ +S using ::std::div_t; +S using ::std::ldiv_t; +S using ::std::atof; +S using ::std::atoi; +S using ::std::atol; +S using ::std::strtod; +S#if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB +S using ::std::strtof; +S using ::std::strtold; +S#endif +S using ::std::strtol; +S using ::std::strtoul; +S using ::std::strtoll; +S using ::std::strtoull; +S using ::std::rand; +S using ::std::srand; +S using ::std::_rand_state; +S using ::std::_rand_r; +S using ::std::_srand_r; +S using ::std::_ANSI_rand_state; +S using ::std::_ANSI_rand_r; +S using ::std::_ANSI_srand_r; +S using ::std::calloc; +S using ::std::free; +S using ::std::malloc; +S using ::std::realloc; +S#if !defined(__STRICT_ANSI__) +S using ::std::posix_memalign; +S#endif +S using ::std::__heapprt; +S using ::std::__heapstats; +S using ::std::__heapvalid; +S using ::std::abort; +S using ::std::atexit; +S using ::std::exit; +S using ::std::_Exit; +S using ::std::getenv; +S using ::std::system; +S using ::std::bsearch; +S using ::std::qsort; +S using ::std::abs; +S using ::std::div; +S using ::std::labs; +S using ::std::ldiv; +S #if !defined(__STRICT_ANSI__) || __USE_C99_STDLIB +S using ::std::llabs; +S using ::std::lldiv; +S #endif /* !defined(__STRICT_ANSI__) || __USE_C99_STDLIB */ +S#if !(__ARM_NO_DEPRECATED_FUNCTIONS) +S using ::std::__sdiv32by16; +S using ::std::__udiv32by16; +S using ::std::__sdiv64by32; +S using ::std::__rt_sdiv32by16; +S using ::std::__rt_udiv32by16; +S using ::std::__rt_sdiv64by32; +S#endif +S using ::std::__fp_status; +S using ::std::mblen; +S using ::std::mbtowc; +S using ::std::wctomb; +S using ::std::mbstowcs; +S using ::std::wcstombs; +S using ::std::__use_realtime_heap; +S using ::std::__use_realtime_division; +S using ::std::__use_two_region_memory; +S using ::std::__use_no_heap; +S using ::std::__use_no_heap_region; +S using ::std::__C_library_version_string; +S using ::std::__C_library_version_number; +S using ::std::size_t; +S using ::std::__aeabi_MB_CUR_MAX; +S #endif /* __STDLIB_NO_EXPORTS */ +N #endif /* __cplusplus */ +N +N#undef __LONGLONG +N +N#endif /* __stdlib_h */ +N +N/* end of stdlib.h */ +L 4 "..\..\src\app\main.c" 2 +N#include "test_cfg_global.h" +L 1 "..\..\src\app\test_cfg_global.h" 1 +N/******************************************************************************* +N* +N* File: test_cfg_global.h +N* Description： 测试用例全局配置头文件 +N* Version： V0.1 +N* Date： 2021-05-01 +N* Author： kevin +N *******************************************************************************/ +N +N#ifndef __TEST_GLOBAL_CONFIG_H__ +N#define __TEST_GLOBAL_CONFIG_H__ +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N/* 模块demo 宏定义 */ +N#define _MODULE_DEMO_ENABLE 0 +N#define _MODULE_DEMO_TIMER_EN 0 +N#define _MODULE_DEMO_DSI_TX_EN 0 +N#define _MODULE_DEMO_DSI_RX_EN 0 +N#define _MODULE_DEMO_PWM_EN 0 +N#define _MODULE_DEMO_SWIRE_EN 0 +N#define _MODULE_DEMO_WDG_EN 0 +N#define _MODULE_DEMO_GPIO_EN 0 +N#define _MODULE_DEMO_I2C_EN 0 +N#define _MODULE_DEMO_SPI_EN 0 +N#define _MODULE_DEMO_PWR_EN 0 +N/* ap demo 宏定义 */ +N#define _DEMO_GOOGLE_P8P_EN 1 +N +N +N#if _DEMO_GOOGLE_P8P_EN +X#if 1 +N #include "p8p_demo.h" +L 1 "..\..\src\app\P8P\p8p_demo.h" 1 +N/******************************************************************************* +N* Copyright (C) 2019-2022, TAU Systems (R),All Rights Reserved. +N* +N* File: P8P.h +N* Description GOOGLE P8P DEMO file +N* Version V0.1 +N* Date 2023-12-25 +N* Author Markin +N*******************************************************************************/ +N#ifndef __GOOGLE_P8P_DEMO_H__ +N#define __GOOGLE_P8P_DEMO_H__ +N +N +N#define PANEL_INIT_CODE_ARRAY 1 +N#define DDIC_FPS_SETTING 1 +N +N +N +Nvoid google_p8p_demo(void); +N +N#endif +L 37 "..\..\src\app\test_cfg_global.h" 2 +N#endif +N#endif +N +L 5 "..\..\src\app\main.c" 2 +N#include "tau_log.h" +L 1 "..\..\src\common\tau_log.h" 1 +N/******************************************************************************* +N* +N* +N* File: tau_log.h +N* Description log file +N* Version V0.1 +N* Date 2020-12-08 +N* Author linyw +N*******************************************************************************/ +N#ifndef _TAU_LOG_H_ +N#define _TAU_LOG_H_ +N +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h" 1 +N/* Copyright (C) ARM Ltd., 1999,2014 */ +N/* All rights reserved */ +N +N/* +N * RCS $Revision$ +N * Checkin $Date$ +N * Revising $Author: agrant $ +N */ +N +N#ifndef __stdint_h +N#define __stdint_h +N#define __ARMCLIB_VERSION 5060037 +N +N #ifdef __INT64_TYPE__ +S /* armclang predefines '__INT64_TYPE__' and '__INT64_C_SUFFIX__' */ +S #define __INT64 __INT64_TYPE__ +N #else +N /* armcc has builtin '__int64' which can be used in --strict mode */ +N #define __INT64 __int64 +N #define __INT64_C_SUFFIX__ ll +N #endif +N #define __PASTE2(x, y) x ## y +N #define __PASTE(x, y) __PASTE2(x, y) +N #define __INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__)) +N #define __UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__)) +N #if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__)) +X #if 0L || (1L && !0L) +N /* armclang and non-strict armcc allow 'long long' in system headers */ +N #define __LONGLONG long long +N #else +S /* strict armcc has '__int64' */ +S #define __LONGLONG __int64 +N #endif +N +N #ifndef __STDINT_DECLS +N #define __STDINT_DECLS +N +N #undef __CLIBNS +N +N #ifdef __cplusplus +S namespace std { +S #define __CLIBNS std:: +S extern "C" { +N #else +N #define __CLIBNS +N #endif /* __cplusplus */ +N +N +N/* +N * 'signed' is redundant below, except for 'signed char' and if +N * the typedef is used to declare a bitfield. +N */ +N +N /* 7.18.1.1 */ +N +N /* exact-width signed integer types */ +Ntypedef signed char int8_t; +Ntypedef signed short int int16_t; +Ntypedef signed int int32_t; +Ntypedef signed __INT64 int64_t; +Xtypedef signed __int64 int64_t; +N +N /* exact-width unsigned integer types */ +Ntypedef unsigned char uint8_t; +Ntypedef unsigned short int uint16_t; +Ntypedef unsigned int uint32_t; +Ntypedef unsigned __INT64 uint64_t; +Xtypedef unsigned __int64 uint64_t; +N +N /* 7.18.1.2 */ +N +N /* smallest type of at least n bits */ +N /* minimum-width signed integer types */ +Ntypedef signed char int_least8_t; +Ntypedef signed short int int_least16_t; +Ntypedef signed int int_least32_t; +Ntypedef signed __INT64 int_least64_t; +Xtypedef signed __int64 int_least64_t; +N +N /* minimum-width unsigned integer types */ +Ntypedef unsigned char uint_least8_t; +Ntypedef unsigned short int uint_least16_t; +Ntypedef unsigned int uint_least32_t; +Ntypedef unsigned __INT64 uint_least64_t; +Xtypedef unsigned __int64 uint_least64_t; +N +N /* 7.18.1.3 */ +N +N /* fastest minimum-width signed integer types */ +Ntypedef signed int int_fast8_t; +Ntypedef signed int int_fast16_t; +Ntypedef signed int int_fast32_t; +Ntypedef signed __INT64 int_fast64_t; +Xtypedef signed __int64 int_fast64_t; +N +N /* fastest minimum-width unsigned integer types */ +Ntypedef unsigned int uint_fast8_t; +Ntypedef unsigned int uint_fast16_t; +Ntypedef unsigned int uint_fast32_t; +Ntypedef unsigned __INT64 uint_fast64_t; +Xtypedef unsigned __int64 uint_fast64_t; +N +N /* 7.18.1.4 integer types capable of holding object pointers */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +Stypedef signed __INT64 intptr_t; +Stypedef unsigned __INT64 uintptr_t; +N#else +Ntypedef signed int intptr_t; +Ntypedef unsigned int uintptr_t; +N#endif +N +N /* 7.18.1.5 greatest-width integer types */ +Ntypedef signed __LONGLONG intmax_t; +Xtypedef signed long long intmax_t; +Ntypedef unsigned __LONGLONG uintmax_t; +Xtypedef unsigned long long uintmax_t; +N +N +N#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) +X#if !0L || 0L +N +N /* 7.18.2.1 */ +N +N /* minimum values of exact-width signed integer types */ +N#define INT8_MIN -128 +N#define INT16_MIN -32768 +N#define INT32_MIN (~0x7fffffff) /* -2147483648 is unsigned */ +N#define INT64_MIN __INT64_C(~0x7fffffffffffffff) /* -9223372036854775808 is unsigned */ +N +N /* maximum values of exact-width signed integer types */ +N#define INT8_MAX 127 +N#define INT16_MAX 32767 +N#define INT32_MAX 2147483647 +N#define INT64_MAX __INT64_C(9223372036854775807) +N +N /* maximum values of exact-width unsigned integer types */ +N#define UINT8_MAX 255 +N#define UINT16_MAX 65535 +N#define UINT32_MAX 4294967295u +N#define UINT64_MAX __UINT64_C(18446744073709551615) +N +N /* 7.18.2.2 */ +N +N /* minimum values of minimum-width signed integer types */ +N#define INT_LEAST8_MIN -128 +N#define INT_LEAST16_MIN -32768 +N#define INT_LEAST32_MIN (~0x7fffffff) +N#define INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff) +N +N /* maximum values of minimum-width signed integer types */ +N#define INT_LEAST8_MAX 127 +N#define INT_LEAST16_MAX 32767 +N#define INT_LEAST32_MAX 2147483647 +N#define INT_LEAST64_MAX __INT64_C(9223372036854775807) +N +N /* maximum values of minimum-width unsigned integer types */ +N#define UINT_LEAST8_MAX 255 +N#define UINT_LEAST16_MAX 65535 +N#define UINT_LEAST32_MAX 4294967295u +N#define UINT_LEAST64_MAX __UINT64_C(18446744073709551615) +N +N /* 7.18.2.3 */ +N +N /* minimum values of fastest minimum-width signed integer types */ +N#define INT_FAST8_MIN (~0x7fffffff) +N#define INT_FAST16_MIN (~0x7fffffff) +N#define INT_FAST32_MIN (~0x7fffffff) +N#define INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff) +N +N /* maximum values of fastest minimum-width signed integer types */ +N#define INT_FAST8_MAX 2147483647 +N#define INT_FAST16_MAX 2147483647 +N#define INT_FAST32_MAX 2147483647 +N#define INT_FAST64_MAX __INT64_C(9223372036854775807) +N +N /* maximum values of fastest minimum-width unsigned integer types */ +N#define UINT_FAST8_MAX 4294967295u +N#define UINT_FAST16_MAX 4294967295u +N#define UINT_FAST32_MAX 4294967295u +N#define UINT_FAST64_MAX __UINT64_C(18446744073709551615) +N +N /* 7.18.2.4 */ +N +N /* minimum value of pointer-holding signed integer type */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define INTPTR_MIN INT64_MIN +N#else +N#define INTPTR_MIN INT32_MIN +N#endif +N +N /* maximum value of pointer-holding signed integer type */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define INTPTR_MAX INT64_MAX +N#else +N#define INTPTR_MAX INT32_MAX +N#endif +N +N /* maximum value of pointer-holding unsigned integer type */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define UINTPTR_MAX UINT64_MAX +N#else +N#define UINTPTR_MAX UINT32_MAX +N#endif +N +N /* 7.18.2.5 */ +N +N /* minimum value of greatest-width signed integer type */ +N#define INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) +N +N /* maximum value of greatest-width signed integer type */ +N#define INTMAX_MAX __ESCAPE__(9223372036854775807ll) +N +N /* maximum value of greatest-width unsigned integer type */ +N#define UINTMAX_MAX __ESCAPE__(18446744073709551615ull) +N +N /* 7.18.3 */ +N +N /* limits of ptrdiff_t */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define PTRDIFF_MIN INT64_MIN +S#define PTRDIFF_MAX INT64_MAX +N#else +N#define PTRDIFF_MIN INT32_MIN +N#define PTRDIFF_MAX INT32_MAX +N#endif +N +N /* limits of sig_atomic_t */ +N#define SIG_ATOMIC_MIN (~0x7fffffff) +N#define SIG_ATOMIC_MAX 2147483647 +N +N /* limit of size_t */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define SIZE_MAX UINT64_MAX +N#else +N#define SIZE_MAX UINT32_MAX +N#endif +N +N /* limits of wchar_t */ +N /* NB we have to undef and redef because they're defined in both +N * stdint.h and wchar.h */ +N#undef WCHAR_MIN +N#undef WCHAR_MAX +N +N#if defined(__WCHAR32) || (defined(__ARM_SIZEOF_WCHAR_T) && __ARM_SIZEOF_WCHAR_T == 4) +X#if 0L || (0L && __ARM_SIZEOF_WCHAR_T == 4) +S #define WCHAR_MIN 0 +S #define WCHAR_MAX 0xffffffffU +N#else +N #define WCHAR_MIN 0 +N #define WCHAR_MAX 65535 +N#endif +N +N /* limits of wint_t */ +N#define WINT_MIN (~0x7fffffff) +N#define WINT_MAX 2147483647 +N +N#endif /* __STDC_LIMIT_MACROS */ +N +N#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) +X#if !0L || 0L +N +N /* 7.18.4.1 macros for minimum-width integer constants */ +N#define INT8_C(x) (x) +N#define INT16_C(x) (x) +N#define INT32_C(x) (x) +N#define INT64_C(x) __INT64_C(x) +N +N#define UINT8_C(x) (x ## u) +N#define UINT16_C(x) (x ## u) +N#define UINT32_C(x) (x ## u) +N#define UINT64_C(x) __UINT64_C(x) +N +N /* 7.18.4.2 macros for greatest-width integer constants */ +N#define INTMAX_C(x) __ESCAPE__(x ## ll) +N#define UINTMAX_C(x) __ESCAPE__(x ## ull) +N +N#endif /* __STDC_CONSTANT_MACROS */ +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif /* __cplusplus */ +N #endif /* __STDINT_DECLS */ +N +N #ifdef __cplusplus +S #ifndef __STDINT_NO_EXPORTS +S using ::std::int8_t; +S using ::std::int16_t; +S using ::std::int32_t; +S using ::std::int64_t; +S using ::std::uint8_t; +S using ::std::uint16_t; +S using ::std::uint32_t; +S using ::std::uint64_t; +S using ::std::int_least8_t; +S using ::std::int_least16_t; +S using ::std::int_least32_t; +S using ::std::int_least64_t; +S using ::std::uint_least8_t; +S using ::std::uint_least16_t; +S using ::std::uint_least32_t; +S using ::std::uint_least64_t; +S using ::std::int_fast8_t; +S using ::std::int_fast16_t; +S using ::std::int_fast32_t; +S using ::std::int_fast64_t; +S using ::std::uint_fast8_t; +S using ::std::uint_fast16_t; +S using ::std::uint_fast32_t; +S using ::std::uint_fast64_t; +S using ::std::intptr_t; +S using ::std::uintptr_t; +S using ::std::intmax_t; +S using ::std::uintmax_t; +S #endif +N #endif /* __cplusplus */ +N +N#undef __INT64 +N#undef __LONGLONG +N +N#endif /* __stdint_h */ +N +N/* end of stdint.h */ +L 18 "..\..\src\common\tau_log.h" 2 +N#include +N#include +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.h" 1 +N/* stdarg.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.8 */ +N/* Copyright (C) Codemist Ltd., 1988 */ +N/* Copyright (C) ARM Ltd., 1991-1999. All rights reserved */ +N +N/* +N * RCS $Revision$ +N * Checkin $Date$ +N * Revising $Author: agrant $ +N */ +N +N#ifndef __stdarg_h +N#define __stdarg_h +N#define __ARMCLIB_VERSION 5060037 +N +N #ifndef __STDARG_DECLS +N #define __STDARG_DECLS +N +N #undef __CLIBNS +N +N #ifdef __cplusplus +S namespace std { +S #define __CLIBNS ::std:: +S extern "C" { +N #else +N #define __CLIBNS +N #endif /* __cplusplus */ +N +N/* +N * stdarg.h declares a type and defines macros for advancing through a +N * list of arguments whose number and types are not known to the called +N * function when it is translated. A function may be called with a variable +N * number of arguments of differing types. Its parameter list contains one or +N * more parameters. The rightmost parameter plays a special role in the access +N * mechanism, and will be called parmN in this description. +N */ +N +N/* N.B. is required to declare vfprintf() without defining */ +N/* va_list. Clearly the type __va_list there must keep in step. */ +N#ifdef __clang__ +S typedef __builtin_va_list va_list; +S #define va_start(ap, param) __builtin_va_start(ap, param) +S #define va_end(ap) __builtin_va_end(ap) +S #define va_arg(ap, type) __builtin_va_arg(ap, type) +S #if __STDC_VERSION__ >= 199900L || __cplusplus >= 201103L || !defined(__STRICT_ANSI__) +S #define va_copy(dest, src) __builtin_va_copy(dest, src) +S #endif +N#else +N #ifdef __TARGET_ARCH_AARCH64 +S typedef struct __va_list { +S void *__stack; +S void *__gr_top; +S void *__vr_top; +S int __gr_offs; +S int __vr_offs; +S } va_list; +N #else +N typedef struct __va_list { void *__ap; } va_list; +N #endif +N /* +N * an array type suitable for holding information needed by the macro va_arg +N * and the function va_end. The called function shall declare a variable +N * (referred to as ap) having type va_list. The variable ap may be passed as +N * an argument to another function. +N * Note: va_list is an array type so that when an object of that type +N * is passed as an argument it gets passed by reference. +N */ +N #define va_start(ap, parmN) __va_start(ap, parmN) +N +N /* +N * The va_start macro shall be executed before any access to the unnamed +N * arguments. The parameter ap points to an object that has type va_list. +N * The va_start macro initialises ap for subsequent use by va_arg and +N * va_end. The parameter parmN is the identifier of the rightmost parameter +N * in the variable parameter list in the function definition (the one just +N * before the '...'). If the parameter parmN is declared with the register +N * storage class an error is given. +N * If parmN is a narrow type (char, short, float) an error is given in +N * strict ANSI mode, or a warning otherwise. +N * Returns: no value. +N */ +N #define va_arg(ap, type) __va_arg(ap, type) +N +N /* +N * The va_arg macro expands to an expression that has the type and value of +N * the next argument in the call. The parameter ap shall be the same as the +N * va_list ap initialised by va_start. Each invocation of va_arg modifies +N * ap so that successive arguments are returned in turn. The parameter +N * 'type' is a type name such that the type of a pointer to an object that +N * has the specified type can be obtained simply by postfixing a * to +N * 'type'. If type is a narrow type, an error is given in strict ANSI +N * mode, or a warning otherwise. If the type is an array or function type, +N * an error is given. +N * In non-strict ANSI mode, 'type' is allowed to be any expression. +N * Returns: The first invocation of the va_arg macro after that of the +N * va_start macro returns the value of the argument after that +N * specified by parmN. Successive invocations return the values of +N * the remaining arguments in succession. +N * The result is cast to 'type', even if 'type' is narrow. +N */ +N +N#define __va_copy(dest, src) ((void)((dest) = (src))) +N +N#if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) +X#if !0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus) +N /* va_copy is in C99 and non-strict C90 and non-strict C++ +N * __va_copy is always present. +N */ +N #define va_copy(dest, src) ((void)((dest) = (src))) +N +N /* The va_copy macro makes the va_list dest be a copy of +N * the va_list src, as if the va_start macro had been applied +N * to it followed by the same sequence of uses of the va_arg +N * macro as had previously been used to reach the present state +N * of src. +N */ +N#endif +N +N#define va_end(ap) __va_end(ap) +N /* +N * The va_end macro facilitates a normal return from the function whose +N * variable argument list was referenced by the expansion of va_start that +N * initialised the va_list ap. If the va_end macro is not invoked before +N * the return, the behaviour is undefined. +N * Returns: no value. +N */ +N#endif /* __clang__ */ +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif /* __cplusplus */ +N +N #ifdef __GNUC__ +N /* be cooperative with glibc */ +N typedef __CLIBNS va_list __gnuc_va_list; +X typedef va_list __gnuc_va_list; +N #define __GNUC_VA_LIST +N #undef __need___va_list +N #endif +N +N #endif /* __STDARG_DECLS */ +N +N #ifdef __cplusplus +S #ifndef __STDARG_NO_EXPORTS +S using ::std::va_list; +S #endif +N #endif /* __cplusplus */ +N#endif +N +N/* end of stdarg.h */ +N +L 20 "..\..\src\common\tau_log.h" 2 +N#include "ArmCM0.h" +L 1 "..\..\src\sdk\include\M0\ArmCM0.h" 1 +N/**************************************************************************//** +N * @file ARMCM0.h +N * @brief CMSIS Core Peripheral Access Layer Header File for +N * ARMCM0 Device +N * @version V5.3.1 +N * @date 09. July 2018 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#ifndef ARMCM0_H +N#define ARMCM0_H +N +N#ifdef __cplusplus +Sextern "C" { +N#endif +N +N +N/* ------------------------- Interrupt Number Definition ------------------------ */ +N +Ntypedef enum IRQn +N{ +N /* ------------------- Processor Exceptions Numbers ----------------------------- */ +N NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ +N HardFault_IRQn = -13, /* 3 HardFault Interrupt */ +N SVCall_IRQn = -5, /* 11 SV Call Interrupt */ +N PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ +N SysTick_IRQn = -1, /* 15 System Tick Interrupt */ +N +N /* ------------------- Processor Interrupt Numbers ------------------------------ */ +N VIDC_IRQn = 0, +N LCDC_IRQn = 1, +N MIPI_RX_IRQn = 2, +N MIPI_TX_IRQn = 3, +N MEMC_IRQn = 4, +N VPRE_IRQn = 5, +N FLSCTRL_IRQn = 6, +N DMA_IRQn = 7, +N TIMER0_IRQn = 8, +N TIMER1_IRQn = 9, +N TIMER2_IRQn = 10, +N TIMER3_IRQn = 11, +N WDG_IRQn = 12, +N UART_IRQn = 13, +N I2C0_IRQn = 14, +N I2C1_IRQn = 15, +N SPIS_IRQn = 16, +N SPIM_IRQn = 17, +N VPRE1_IRQn = 18, +N I2C2_IRQn = 19, +N OTP_IRQn = 20, +N SWIRE_IRQn = 21, +N PVD_IRQn = 22, +N AP_NRESET_IRQn = 23, +N EXTI_INT0_IRQn = 24, +N EXTI_INT1_IRQn = 25, +N EXTI_INT2_IRQn = 26, +N EXTI_INT3_IRQn = 27, +N EXTI_INT4_IRQn = 28, +N EXTI_INT5_IRQn = 29, +N EXTI_INT6_IRQn = 30, +N EXTI_INT7_IRQn = 31 +N /* Interrupts 10 .. 31 are left out */ +N} IRQn_Type; +N +N +N/* ================================================================================ */ +N/* ================ Processor and Core Peripheral Section ================ */ +N/* ================================================================================ */ +N +N/* ------- Start of section using anonymous unions and disabling warnings ------- */ +N#if defined (__CC_ARM) +X#if 1L +N#pragma push +N#pragma anon_unions +N#elif defined (__ICCARM__) +X#elif 0L +S#pragma language=extended +S#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +S#pragma clang diagnostic push +S#pragma clang diagnostic ignored "-Wc11-extensions" +S#pragma clang diagnostic ignored "-Wreserved-id-macro" +S#elif defined (__GNUC__) +S/* anonymous unions are enabled by default */ +S#elif defined (__TMS470__) +S/* anonymous unions are enabled by default */ +S#elif defined (__TASKING__) +S#pragma warning 586 +S#elif defined (__CSMC__) +S/* anonymous unions are enabled by default */ +S#else +S#warning Not supported compiler type +N#endif +N +N/* -------- Configuration of Core Peripherals ----------------------------------- */ +N#define __CM0_REV 0x0000U /* Core revision r0p0 */ +N#define __MPU_PRESENT 0U /* no MPU present */ +N#define __VTOR_PRESENT 0U /* no VTOR present */ +N#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ //20220228 +N#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +N +N#define __FPU_PRESENT 0U /* Set to 1 if FPU is present */ +N#define __FPU_DP 0U /* single precision FPU */ +N#define __ICACHE_PRESENT 0U /* Set to 1 if I-CACHE is present */ +N#define __DCACHE_PRESENT 0U /* Set to 1 if D-CACHE is present */ +N#define __DSP_PRESENT 0U /* no DSP extension present */ +N +N#include "core_cm0.h" /* Processor and core peripherals */ +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h" 1 +N/**************************************************************************//** +N * @file core_cm0.h +N * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File +N * @version V5.0.6 +N * @date 13. March 2019 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2019 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#if defined ( __ICCARM__ ) +X#if 0L +S #pragma system_include /* treat file as system include file for MISRA check */ +S#elif defined (__clang__) +X#elif 0L +S #pragma clang system_header /* treat file as system include file */ +N#endif +N +N#ifndef __CORE_CM0_H_GENERIC +N#define __CORE_CM0_H_GENERIC +N +N#include +N +N#ifdef __cplusplus +S extern "C" { +N#endif +N +N/** +N \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions +N CMSIS violates the following MISRA-C:2004 rules: +N +N \li Required Rule 8.5, object/function definition in header file.
+N Function definitions in header files are used to allow 'inlining'. +N +N \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+N Unions are used for effective representation of core registers. +N +N \li Advisory Rule 19.7, Function-like macro defined.
+N Function-like macros are used to allow more efficient code. +N */ +N +N +N/******************************************************************************* +N * CMSIS definitions +N ******************************************************************************/ +N/** +N \ingroup Cortex_M0 +N @{ +N */ +N +N#include "cmsis_version.h" +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_version.h" 1 +N/**************************************************************************//** +N * @file cmsis_version.h +N * @brief CMSIS Core(M) Version definitions +N * @version V5.0.2 +N * @date 19. April 2017 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2017 ARM Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#if defined ( __ICCARM__ ) +X#if 0L +S #pragma system_include /* treat file as system include file for MISRA check */ +S#elif defined (__clang__) +X#elif 0L +S #pragma clang system_header /* treat file as system include file */ +N#endif +N +N#ifndef __CMSIS_VERSION_H +N#define __CMSIS_VERSION_H +N +N/* CMSIS Version definitions */ +N#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +N#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +N#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ +N __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +X#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | __CM_CMSIS_VERSION_SUB ) +N#endif +L 64 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h" 2 +N +N/* CMSIS CM0 definitions */ +N#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +N#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +N#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ +N __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ +X#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB ) +N +N#define __CORTEX_M (0U) /*!< Cortex-M Core */ +N +N/** __FPU_USED indicates whether an FPU is used or not. +N This core does not support an FPU at all +N*/ +N#define __FPU_USED 0U +N +N#if defined ( __CC_ARM ) +X#if 1L +N #if defined __TARGET_FPU_VFP +X #if 0L +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +N #endif +N +N#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +X#elif 1L && (5060750 >= 6010050) +S #if defined __ARM_FP +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __GNUC__ ) +S #if defined (__VFP_FP__) && !defined(__SOFTFP__) +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __ICCARM__ ) +S #if defined __ARMVFP__ +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __TI_ARM__ ) +S #if defined __TI_VFP_SUPPORT__ +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __TASKING__ ) +S #if defined __FPU_VFP__ +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __CSMC__ ) +S #if ( __CSMC__ & 0x400U) +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +N#endif +N +N#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h" 1 +N/**************************************************************************//** +N * @file cmsis_compiler.h +N * @brief CMSIS compiler generic header file +N * @version V5.1.0 +N * @date 09. October 2018 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#ifndef __CMSIS_COMPILER_H +N#define __CMSIS_COMPILER_H +N +N#include +N +N/* +N * Arm Compiler 4/5 +N */ +N#if defined ( __CC_ARM ) +X#if 1L +N #include "cmsis_armcc.h" +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_armcc.h" 1 +N/**************************************************************************//** +N * @file cmsis_armcc.h +N * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file +N * @version V5.0.5 +N * @date 14. December 2018 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#ifndef __CMSIS_ARMCC_H +N#define __CMSIS_ARMCC_H +N +N +N#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) +X#if 1L && (5060750 < 400677) +S #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +N#endif +N +N/* CMSIS compiler control architecture macros */ +N#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ +N (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) +X#if ((0L && (__TARGET_ARCH_6_M == 1)) || (1L && (1 == 1)) ) +N #define __ARM_ARCH_6M__ 1 +N#endif +N +N#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) +X#if (0L && (__TARGET_ARCH_7_M == 1)) +S #define __ARM_ARCH_7M__ 1 +N#endif +N +N#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) +X#if (0L && (__TARGET_ARCH_7E_M == 1)) +S #define __ARM_ARCH_7EM__ 1 +N#endif +N +N /* __ARM_ARCH_8M_BASE__ not applicable */ +N /* __ARM_ARCH_8M_MAIN__ not applicable */ +N +N/* CMSIS compiler control DSP macros */ +N#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7EM__ == 1)) ) +S #define __ARM_FEATURE_DSP 1 +N#endif +N +N/* CMSIS compiler specific defines */ +N#ifndef __ASM +N #define __ASM __asm +N#endif +N#ifndef __INLINE +N #define __INLINE __inline +N#endif +N#ifndef __STATIC_INLINE +N #define __STATIC_INLINE static __inline +N#endif +N#ifndef __STATIC_FORCEINLINE +N #define __STATIC_FORCEINLINE static __forceinline +N#endif +N#ifndef __NO_RETURN +N #define __NO_RETURN __declspec(noreturn) +N#endif +N#ifndef __USED +N #define __USED __attribute__((used)) +N#endif +N#ifndef __WEAK +N #define __WEAK __attribute__((weak)) +N#endif +N#ifndef __PACKED +N #define __PACKED __attribute__((packed)) +N#endif +N#ifndef __PACKED_STRUCT +N #define __PACKED_STRUCT __packed struct +N#endif +N#ifndef __PACKED_UNION +N #define __PACKED_UNION __packed union +N#endif +N#ifndef __UNALIGNED_UINT32 /* deprecated */ +N #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +N#endif +N#ifndef __UNALIGNED_UINT16_WRITE +N #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +N#endif +N#ifndef __UNALIGNED_UINT16_READ +N #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +N#endif +N#ifndef __UNALIGNED_UINT32_WRITE +N #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +N#endif +N#ifndef __UNALIGNED_UINT32_READ +N #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +N#endif +N#ifndef __ALIGNED +N #define __ALIGNED(x) __attribute__((aligned(x))) +N#endif +N#ifndef __RESTRICT +N #define __RESTRICT __restrict +N#endif +N +N/* ########################### Core Function Access ########################### */ +N/** \ingroup CMSIS_Core_FunctionInterface +N \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions +N @{ +N */ +N +N/** +N \brief Enable IRQ Interrupts +N \details Enables IRQ interrupts by clearing the I-bit in the CPSR. +N Can only be executed in Privileged modes. +N */ +N/* intrinsic void __enable_irq(); */ +N +N +N/** +N \brief Disable IRQ Interrupts +N \details Disables IRQ interrupts by setting the I-bit in the CPSR. +N Can only be executed in Privileged modes. +N */ +N/* intrinsic void __disable_irq(); */ +N +N/** +N \brief Get Control Register +N \details Returns the content of the Control Register. +N \return Control Register value +N */ +N__STATIC_INLINE uint32_t __get_CONTROL(void) +Xstatic __inline uint32_t __get_CONTROL(void) +N{ +N register uint32_t __regControl __ASM("control"); +X register uint32_t __regControl __asm("control"); +N return(__regControl); +N} +N +N +N/** +N \brief Set Control Register +N \details Writes the given value to the Control Register. +N \param [in] control Control Register value to set +N */ +N__STATIC_INLINE void __set_CONTROL(uint32_t control) +Xstatic __inline void __set_CONTROL(uint32_t control) +N{ +N register uint32_t __regControl __ASM("control"); +X register uint32_t __regControl __asm("control"); +N __regControl = control; +N} +N +N +N/** +N \brief Get IPSR Register +N \details Returns the content of the IPSR Register. +N \return IPSR Register value +N */ +N__STATIC_INLINE uint32_t __get_IPSR(void) +Xstatic __inline uint32_t __get_IPSR(void) +N{ +N register uint32_t __regIPSR __ASM("ipsr"); +X register uint32_t __regIPSR __asm("ipsr"); +N return(__regIPSR); +N} +N +N +N/** +N \brief Get APSR Register +N \details Returns the content of the APSR Register. +N \return APSR Register value +N */ +N__STATIC_INLINE uint32_t __get_APSR(void) +Xstatic __inline uint32_t __get_APSR(void) +N{ +N register uint32_t __regAPSR __ASM("apsr"); +X register uint32_t __regAPSR __asm("apsr"); +N return(__regAPSR); +N} +N +N +N/** +N \brief Get xPSR Register +N \details Returns the content of the xPSR Register. +N \return xPSR Register value +N */ +N__STATIC_INLINE uint32_t __get_xPSR(void) +Xstatic __inline uint32_t __get_xPSR(void) +N{ +N register uint32_t __regXPSR __ASM("xpsr"); +X register uint32_t __regXPSR __asm("xpsr"); +N return(__regXPSR); +N} +N +N +N/** +N \brief Get Process Stack Pointer +N \details Returns the current value of the Process Stack Pointer (PSP). +N \return PSP Register value +N */ +N__STATIC_INLINE uint32_t __get_PSP(void) +Xstatic __inline uint32_t __get_PSP(void) +N{ +N register uint32_t __regProcessStackPointer __ASM("psp"); +X register uint32_t __regProcessStackPointer __asm("psp"); +N return(__regProcessStackPointer); +N} +N +N +N/** +N \brief Set Process Stack Pointer +N \details Assigns the given value to the Process Stack Pointer (PSP). +N \param [in] topOfProcStack Process Stack Pointer value to set +N */ +N__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +Xstatic __inline void __set_PSP(uint32_t topOfProcStack) +N{ +N register uint32_t __regProcessStackPointer __ASM("psp"); +X register uint32_t __regProcessStackPointer __asm("psp"); +N __regProcessStackPointer = topOfProcStack; +N} +N +N +N/** +N \brief Get Main Stack Pointer +N \details Returns the current value of the Main Stack Pointer (MSP). +N \return MSP Register value +N */ +N__STATIC_INLINE uint32_t __get_MSP(void) +Xstatic __inline uint32_t __get_MSP(void) +N{ +N register uint32_t __regMainStackPointer __ASM("msp"); +X register uint32_t __regMainStackPointer __asm("msp"); +N return(__regMainStackPointer); +N} +N +N +N/** +N \brief Set Main Stack Pointer +N \details Assigns the given value to the Main Stack Pointer (MSP). +N \param [in] topOfMainStack Main Stack Pointer value to set +N */ +N__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +Xstatic __inline void __set_MSP(uint32_t topOfMainStack) +N{ +N register uint32_t __regMainStackPointer __ASM("msp"); +X register uint32_t __regMainStackPointer __asm("msp"); +N __regMainStackPointer = topOfMainStack; +N} +N +N +N/** +N \brief Get Priority Mask +N \details Returns the current state of the priority mask bit from the Priority Mask Register. +N \return Priority Mask value +N */ +N__STATIC_INLINE uint32_t __get_PRIMASK(void) +Xstatic __inline uint32_t __get_PRIMASK(void) +N{ +N register uint32_t __regPriMask __ASM("primask"); +X register uint32_t __regPriMask __asm("primask"); +N return(__regPriMask); +N} +N +N +N/** +N \brief Set Priority Mask +N \details Assigns the given value to the Priority Mask Register. +N \param [in] priMask Priority Mask +N */ +N__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +Xstatic __inline void __set_PRIMASK(uint32_t priMask) +N{ +N register uint32_t __regPriMask __ASM("primask"); +X register uint32_t __regPriMask __asm("primask"); +N __regPriMask = (priMask); +N} +N +N +N#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7M__ == 1)) || (0L && (__ARM_ARCH_7EM__ == 1)) ) +S +S/** +S \brief Enable FIQ +S \details Enables FIQ interrupts by clearing the F-bit in the CPSR. +S Can only be executed in Privileged modes. +S */ +S#define __enable_fault_irq __enable_fiq +S +S +S/** +S \brief Disable FIQ +S \details Disables FIQ interrupts by setting the F-bit in the CPSR. +S Can only be executed in Privileged modes. +S */ +S#define __disable_fault_irq __disable_fiq +S +S +S/** +S \brief Get Base Priority +S \details Returns the current value of the Base Priority register. +S \return Base Priority register value +S */ +S__STATIC_INLINE uint32_t __get_BASEPRI(void) +S{ +S register uint32_t __regBasePri __ASM("basepri"); +S return(__regBasePri); +S} +S +S +S/** +S \brief Set Base Priority +S \details Assigns the given value to the Base Priority register. +S \param [in] basePri Base Priority value to set +S */ +S__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +S{ +S register uint32_t __regBasePri __ASM("basepri"); +S __regBasePri = (basePri & 0xFFU); +S} +S +S +S/** +S \brief Set Base Priority with condition +S \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, +S or the new value increases the BASEPRI priority level. +S \param [in] basePri Base Priority value to set +S */ +S__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +S{ +S register uint32_t __regBasePriMax __ASM("basepri_max"); +S __regBasePriMax = (basePri & 0xFFU); +S} +S +S +S/** +S \brief Get Fault Mask +S \details Returns the current value of the Fault Mask register. +S \return Fault Mask register value +S */ +S__STATIC_INLINE uint32_t __get_FAULTMASK(void) +S{ +S register uint32_t __regFaultMask __ASM("faultmask"); +S return(__regFaultMask); +S} +S +S +S/** +S \brief Set Fault Mask +S \details Assigns the given value to the Fault Mask register. +S \param [in] faultMask Fault Mask value to set +S */ +S__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +S{ +S register uint32_t __regFaultMask __ASM("faultmask"); +S __regFaultMask = (faultMask & (uint32_t)1U); +S} +S +N#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +X#endif +N +N +N/** +N \brief Get FPSCR +N \details Returns the current value of the Floating Point Status/Control register. +N \return Floating Point Status/Control register value +N */ +N__STATIC_INLINE uint32_t __get_FPSCR(void) +Xstatic __inline uint32_t __get_FPSCR(void) +N{ +N#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ +N (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +X#if ((1L && (0U == 1U)) && (1L && (0U == 1U)) ) +S register uint32_t __regfpscr __ASM("fpscr"); +S return(__regfpscr); +N#else +N return(0U); +N#endif +N} +N +N +N/** +N \brief Set FPSCR +N \details Assigns the given value to the Floating Point Status/Control register. +N \param [in] fpscr Floating Point Status/Control value to set +N */ +N__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +Xstatic __inline void __set_FPSCR(uint32_t fpscr) +N{ +N#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ +N (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +X#if ((1L && (0U == 1U)) && (1L && (0U == 1U)) ) +S register uint32_t __regfpscr __ASM("fpscr"); +S __regfpscr = (fpscr); +N#else +N (void)fpscr; +N#endif +N} +N +N +N/*@} end of CMSIS_Core_RegAccFunctions */ +N +N +N/* ########################## Core Instruction Access ######################### */ +N/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface +N Access to dedicated instructions +N @{ +N*/ +N +N/** +N \brief No Operation +N \details No Operation does nothing. This instruction can be used for code alignment purposes. +N */ +N#define __NOP __nop +N +N +N/** +N \brief Wait For Interrupt +N \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. +N */ +N#define __WFI __wfi +N +N +N/** +N \brief Wait For Event +N \details Wait For Event is a hint instruction that permits the processor to enter +N a low-power state until one of a number of events occurs. +N */ +N#define __WFE __wfe +N +N +N/** +N \brief Send Event +N \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. +N */ +N#define __SEV __sev +N +N +N/** +N \brief Instruction Synchronization Barrier +N \details Instruction Synchronization Barrier flushes the pipeline in the processor, +N so that all instructions following the ISB are fetched from cache or memory, +N after the instruction has been completed. +N */ +N#define __ISB() do {\ +N __schedule_barrier();\ +N __isb(0xF);\ +N __schedule_barrier();\ +N } while (0U) +X#define __ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U) +N +N/** +N \brief Data Synchronization Barrier +N \details Acts as a special kind of Data Memory Barrier. +N It completes when all explicit memory accesses before this instruction complete. +N */ +N#define __DSB() do {\ +N __schedule_barrier();\ +N __dsb(0xF);\ +N __schedule_barrier();\ +N } while (0U) +X#define __DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U) +N +N/** +N \brief Data Memory Barrier +N \details Ensures the apparent order of the explicit memory operations before +N and after the instruction, without ensuring their completion. +N */ +N#define __DMB() do {\ +N __schedule_barrier();\ +N __dmb(0xF);\ +N __schedule_barrier();\ +N } while (0U) +X#define __DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U) +N +N +N/** +N \brief Reverse byte order (32 bit) +N \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. +N \param [in] value Value to reverse +N \return Reversed value +N */ +N#define __REV __rev +N +N +N/** +N \brief Reverse byte order (16 bit) +N \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. +N \param [in] value Value to reverse +N \return Reversed value +N */ +N#ifndef __NO_EMBEDDED_ASM +N__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +X__attribute__((section(".rev16_text"))) static __inline __asm uint32_t __REV16(uint32_t value) +N{ +N rev16 r0, r0 +N bx lr +N} +N#endif +N +N +N/** +N \brief Reverse byte order (16 bit) +N \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. +N \param [in] value Value to reverse +N \return Reversed value +N */ +N#ifndef __NO_EMBEDDED_ASM +N__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +X__attribute__((section(".revsh_text"))) static __inline __asm int16_t __REVSH(int16_t value) +N{ +N revsh r0, r0 +N bx lr +N} +N#endif +N +N +N/** +N \brief Rotate Right in unsigned value (32 bit) +N \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. +N \param [in] op1 Value to rotate +N \param [in] op2 Number of Bits to rotate +N \return Rotated value +N */ +N#define __ROR __ror +N +N +N/** +N \brief Breakpoint +N \details Causes the processor to enter Debug state. +N Debug tools can use this to investigate system state when the instruction at a particular address is reached. +N \param [in] value is ignored by the processor. +N If required, a debugger can use it to store additional information about the breakpoint. +N */ +N#define __BKPT(value) __breakpoint(value) +N +N +N/** +N \brief Reverse bit order of value +N \details Reverses the bit order of the given value. +N \param [in] value Value to reverse +N \return Reversed value +N */ +N#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7M__ == 1)) || (0L && (__ARM_ARCH_7EM__ == 1)) ) +S #define __RBIT __rbit +N#else +N__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +X__attribute__((always_inline)) static __inline uint32_t __RBIT(uint32_t value) +N{ +N uint32_t result; +N uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ +N +N result = value; /* r will be reversed bits of v; first get LSB of v */ +N for (value >>= 1U; value != 0U; value >>= 1U) +N { +N result <<= 1U; +N result |= value & 1U; +N s--; +N } +N result <<= s; /* shift when v's highest bits are zero */ +N return result; +N} +N#endif +N +N +N/** +N \brief Count leading zeros +N \details Counts the number of leading zeros of a data value. +N \param [in] value Value to count the leading zeros +N \return number of leading zeros in value +N */ +N#define __CLZ __clz +N +N +N#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7M__ == 1)) || (0L && (__ARM_ARCH_7EM__ == 1)) ) +S +S/** +S \brief LDR Exclusive (8 bit) +S \details Executes a exclusive LDR instruction for 8 bit value. +S \param [in] ptr Pointer to data +S \return value of type uint8_t at (*ptr) +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +S#else +S #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +S#endif +S +S +S/** +S \brief LDR Exclusive (16 bit) +S \details Executes a exclusive LDR instruction for 16 bit values. +S \param [in] ptr Pointer to data +S \return value of type uint16_t at (*ptr) +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +S#else +S #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +S#endif +S +S +S/** +S \brief LDR Exclusive (32 bit) +S \details Executes a exclusive LDR instruction for 32 bit values. +S \param [in] ptr Pointer to data +S \return value of type uint32_t at (*ptr) +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +S#else +S #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +S#endif +S +S +S/** +S \brief STR Exclusive (8 bit) +S \details Executes a exclusive STR instruction for 8 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S \return 0 Function succeeded +S \return 1 Function failed +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __STREXB(value, ptr) __strex(value, ptr) +S#else +S #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +S#endif +S +S +S/** +S \brief STR Exclusive (16 bit) +S \details Executes a exclusive STR instruction for 16 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S \return 0 Function succeeded +S \return 1 Function failed +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __STREXH(value, ptr) __strex(value, ptr) +S#else +S #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +S#endif +S +S +S/** +S \brief STR Exclusive (32 bit) +S \details Executes a exclusive STR instruction for 32 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S \return 0 Function succeeded +S \return 1 Function failed +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __STREXW(value, ptr) __strex(value, ptr) +S#else +S #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +S#endif +S +S +S/** +S \brief Remove the exclusive lock +S \details Removes the exclusive lock which is created by LDREX. +S */ +S#define __CLREX __clrex +S +S +S/** +S \brief Signed Saturate +S \details Saturates a signed value. +S \param [in] value Value to be saturated +S \param [in] sat Bit position to saturate to (1..32) +S \return Saturated value +S */ +S#define __SSAT __ssat +S +S +S/** +S \brief Unsigned Saturate +S \details Saturates an unsigned value. +S \param [in] value Value to be saturated +S \param [in] sat Bit position to saturate to (0..31) +S \return Saturated value +S */ +S#define __USAT __usat +S +S +S/** +S \brief Rotate Right with Extend (32 bit) +S \details Moves each bit of a bitstring right by one bit. +S The carry input is shifted in at the left end of the bitstring. +S \param [in] value Value to rotate +S \return Rotated value +S */ +S#ifndef __NO_EMBEDDED_ASM +S__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +S{ +S rrx r0, r0 +S bx lr +S} +S#endif +S +S +S/** +S \brief LDRT Unprivileged (8 bit) +S \details Executes a Unprivileged LDRT instruction for 8 bit value. +S \param [in] ptr Pointer to data +S \return value of type uint8_t at (*ptr) +S */ +S#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) +S +S +S/** +S \brief LDRT Unprivileged (16 bit) +S \details Executes a Unprivileged LDRT instruction for 16 bit values. +S \param [in] ptr Pointer to data +S \return value of type uint16_t at (*ptr) +S */ +S#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) +S +S +S/** +S \brief LDRT Unprivileged (32 bit) +S \details Executes a Unprivileged LDRT instruction for 32 bit values. +S \param [in] ptr Pointer to data +S \return value of type uint32_t at (*ptr) +S */ +S#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) +S +S +S/** +S \brief STRT Unprivileged (8 bit) +S \details Executes a Unprivileged STRT instruction for 8 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S */ +S#define __STRBT(value, ptr) __strt(value, ptr) +S +S +S/** +S \brief STRT Unprivileged (16 bit) +S \details Executes a Unprivileged STRT instruction for 16 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S */ +S#define __STRHT(value, ptr) __strt(value, ptr) +S +S +S/** +S \brief STRT Unprivileged (32 bit) +S \details Executes a Unprivileged STRT instruction for 32 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S */ +S#define __STRT(value, ptr) __strt(value, ptr) +S +N#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +X#else +N +N/** +N \brief Signed Saturate +N \details Saturates a signed value. +N \param [in] value Value to be saturated +N \param [in] sat Bit position to saturate to (1..32) +N \return Saturated value +N */ +N__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +X__attribute__((always_inline)) static __inline int32_t __SSAT(int32_t val, uint32_t sat) +N{ +N if ((sat >= 1U) && (sat <= 32U)) +N { +N const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); +N const int32_t min = -1 - max ; +N if (val > max) +N { +N return max; +N } +N else if (val < min) +N { +N return min; +N } +N } +N return val; +N} +N +N/** +N \brief Unsigned Saturate +N \details Saturates an unsigned value. +N \param [in] value Value to be saturated +N \param [in] sat Bit position to saturate to (0..31) +N \return Saturated value +N */ +N__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +X__attribute__((always_inline)) static __inline uint32_t __USAT(int32_t val, uint32_t sat) +N{ +N if (sat <= 31U) +N { +N const uint32_t max = ((1U << sat) - 1U); +N if (val > (int32_t)max) +N { +N return max; +N } +N else if (val < 0) +N { +N return 0U; +N } +N } +N return (uint32_t)val; +N} +N +N#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +X#endif +N +N/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ +N +N +N/* ################### Compiler specific Intrinsics ########################### */ +N/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics +N Access to dedicated SIMD instructions +N @{ +N*/ +N +N#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7EM__ == 1)) ) +S +S#define __SADD8 __sadd8 +S#define __QADD8 __qadd8 +S#define __SHADD8 __shadd8 +S#define __UADD8 __uadd8 +S#define __UQADD8 __uqadd8 +S#define __UHADD8 __uhadd8 +S#define __SSUB8 __ssub8 +S#define __QSUB8 __qsub8 +S#define __SHSUB8 __shsub8 +S#define __USUB8 __usub8 +S#define __UQSUB8 __uqsub8 +S#define __UHSUB8 __uhsub8 +S#define __SADD16 __sadd16 +S#define __QADD16 __qadd16 +S#define __SHADD16 __shadd16 +S#define __UADD16 __uadd16 +S#define __UQADD16 __uqadd16 +S#define __UHADD16 __uhadd16 +S#define __SSUB16 __ssub16 +S#define __QSUB16 __qsub16 +S#define __SHSUB16 __shsub16 +S#define __USUB16 __usub16 +S#define __UQSUB16 __uqsub16 +S#define __UHSUB16 __uhsub16 +S#define __SASX __sasx +S#define __QASX __qasx +S#define __SHASX __shasx +S#define __UASX __uasx +S#define __UQASX __uqasx +S#define __UHASX __uhasx +S#define __SSAX __ssax +S#define __QSAX __qsax +S#define __SHSAX __shsax +S#define __USAX __usax +S#define __UQSAX __uqsax +S#define __UHSAX __uhsax +S#define __USAD8 __usad8 +S#define __USADA8 __usada8 +S#define __SSAT16 __ssat16 +S#define __USAT16 __usat16 +S#define __UXTB16 __uxtb16 +S#define __UXTAB16 __uxtab16 +S#define __SXTB16 __sxtb16 +S#define __SXTAB16 __sxtab16 +S#define __SMUAD __smuad +S#define __SMUADX __smuadx +S#define __SMLAD __smlad +S#define __SMLADX __smladx +S#define __SMLALD __smlald +S#define __SMLALDX __smlaldx +S#define __SMUSD __smusd +S#define __SMUSDX __smusdx +S#define __SMLSD __smlsd +S#define __SMLSDX __smlsdx +S#define __SMLSLD __smlsld +S#define __SMLSLDX __smlsldx +S#define __SEL __sel +S#define __QADD __qadd +S#define __QSUB __qsub +S +S#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ +S ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) +X#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) +S +S#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ +S ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) +X#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) +S +S#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ +S ((int64_t)(ARG3) << 32U) ) >> 32U)) +X#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U) ) >> 32U)) +S +N#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +N/*@} end of group CMSIS_SIMD_intrinsics */ +N +N +N#endif /* __CMSIS_ARMCC_H */ +L 35 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h" 2 +N +N +N/* +N * Arm Compiler 6.6 LTM (armclang) +N */ +N#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) +X#elif 1L && (5060750 >= 6010050) && (5060750 < 6100100) +S #include "cmsis_armclang_ltm.h" +S +S /* +S * Arm Compiler above 6.10.1 (armclang) +S */ +S#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) +S #include "cmsis_armclang.h" +S +S +S/* +S * GNU Compiler +S */ +S#elif defined ( __GNUC__ ) +S #include "cmsis_gcc.h" +S +S +S/* +S * IAR Compiler +S */ +S#elif defined ( __ICCARM__ ) +S #include +S +S +S/* +S * TI Arm Compiler +S */ +S#elif defined ( __TI_ARM__ ) +S #include +S +S #ifndef __ASM +S #define __ASM __asm +S #endif +S #ifndef __INLINE +S #define __INLINE inline +S #endif +S #ifndef __STATIC_INLINE +S #define __STATIC_INLINE static inline +S #endif +S #ifndef __STATIC_FORCEINLINE +S #define __STATIC_FORCEINLINE __STATIC_INLINE +S #endif +S #ifndef __NO_RETURN +S #define __NO_RETURN __attribute__((noreturn)) +S #endif +S #ifndef __USED +S #define __USED __attribute__((used)) +S #endif +S #ifndef __WEAK +S #define __WEAK __attribute__((weak)) +S #endif +S #ifndef __PACKED +S #define __PACKED __attribute__((packed)) +S #endif +S #ifndef __PACKED_STRUCT +S #define __PACKED_STRUCT struct __attribute__((packed)) +S #endif +S #ifndef __PACKED_UNION +S #define __PACKED_UNION union __attribute__((packed)) +S #endif +S #ifndef __UNALIGNED_UINT32 /* deprecated */ +S struct __attribute__((packed)) T_UINT32 { uint32_t v; }; +S #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +S #endif +S #ifndef __UNALIGNED_UINT16_WRITE +S __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +S #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT16_READ +S __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +S #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __UNALIGNED_UINT32_WRITE +S __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +S #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT32_READ +S __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +S #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __ALIGNED +S #define __ALIGNED(x) __attribute__((aligned(x))) +S #endif +S #ifndef __RESTRICT +S #define __RESTRICT __restrict +S #endif +S +S +S/* +S * TASKING Compiler +S */ +S#elif defined ( __TASKING__ ) +S /* +S * The CMSIS functions have been implemented as intrinsics in the compiler. +S * Please use "carm -?i" to get an up to date list of all intrinsics, +S * Including the CMSIS ones. +S */ +S +S #ifndef __ASM +S #define __ASM __asm +S #endif +S #ifndef __INLINE +S #define __INLINE inline +S #endif +S #ifndef __STATIC_INLINE +S #define __STATIC_INLINE static inline +S #endif +S #ifndef __STATIC_FORCEINLINE +S #define __STATIC_FORCEINLINE __STATIC_INLINE +S #endif +S #ifndef __NO_RETURN +S #define __NO_RETURN __attribute__((noreturn)) +S #endif +S #ifndef __USED +S #define __USED __attribute__((used)) +S #endif +S #ifndef __WEAK +S #define __WEAK __attribute__((weak)) +S #endif +S #ifndef __PACKED +S #define __PACKED __packed__ +S #endif +S #ifndef __PACKED_STRUCT +S #define __PACKED_STRUCT struct __packed__ +S #endif +S #ifndef __PACKED_UNION +S #define __PACKED_UNION union __packed__ +S #endif +S #ifndef __UNALIGNED_UINT32 /* deprecated */ +S struct __packed__ T_UINT32 { uint32_t v; }; +S #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +S #endif +S #ifndef __UNALIGNED_UINT16_WRITE +S __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +S #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT16_READ +S __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +S #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __UNALIGNED_UINT32_WRITE +S __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +S #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT32_READ +S __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +S #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __ALIGNED +S #define __ALIGNED(x) __align(x) +S #endif +S #ifndef __RESTRICT +S #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. +S #define __RESTRICT +S #endif +S +S +S/* +S * COSMIC Compiler +S */ +S#elif defined ( __CSMC__ ) +S #include +S +S #ifndef __ASM +S #define __ASM _asm +S #endif +S #ifndef __INLINE +S #define __INLINE inline +S #endif +S #ifndef __STATIC_INLINE +S #define __STATIC_INLINE static inline +S #endif +S #ifndef __STATIC_FORCEINLINE +S #define __STATIC_FORCEINLINE __STATIC_INLINE +S #endif +S #ifndef __NO_RETURN +S // NO RETURN is automatically detected hence no warning here +S #define __NO_RETURN +S #endif +S #ifndef __USED +S #warning No compiler specific solution for __USED. __USED is ignored. +S #define __USED +S #endif +S #ifndef __WEAK +S #define __WEAK __weak +S #endif +S #ifndef __PACKED +S #define __PACKED @packed +S #endif +S #ifndef __PACKED_STRUCT +S #define __PACKED_STRUCT @packed struct +S #endif +S #ifndef __PACKED_UNION +S #define __PACKED_UNION @packed union +S #endif +S #ifndef __UNALIGNED_UINT32 /* deprecated */ +S @packed struct T_UINT32 { uint32_t v; }; +S #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +S #endif +S #ifndef __UNALIGNED_UINT16_WRITE +S __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +S #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT16_READ +S __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +S #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __UNALIGNED_UINT32_WRITE +S __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +S #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT32_READ +S __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +S #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __ALIGNED +S #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. +S #define __ALIGNED(x) +S #endif +S #ifndef __RESTRICT +S #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. +S #define __RESTRICT +S #endif +S +S +S#else +S #error Unknown compiler. +N#endif +N +N +N#endif /* __CMSIS_COMPILER_H */ +N +L 116 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h" 2 +N +N +N#ifdef __cplusplus +S} +N#endif +N +N#endif /* __CORE_CM0_H_GENERIC */ +N +N#ifndef __CMSIS_GENERIC +N +N#ifndef __CORE_CM0_H_DEPENDANT +N#define __CORE_CM0_H_DEPENDANT +N +N#ifdef __cplusplus +S extern "C" { +N#endif +N +N/* check device defines and use defaults */ +N#if defined __CHECK_DEVICE_DEFINES +X#if 0L +S #ifndef __CM0_REV +S #define __CM0_REV 0x0000U +S #warning "__CM0_REV not defined in device header file; using default!" +S #endif +S +S #ifndef __NVIC_PRIO_BITS +S #define __NVIC_PRIO_BITS 2U +S #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +S #endif +S +S #ifndef __Vendor_SysTickConfig +S #define __Vendor_SysTickConfig 0U +S #warning "__Vendor_SysTickConfig not defined in device header file; using default!" +S #endif +N#endif +N +N/* IO definitions (access restrictions to peripheral registers) */ +N/** +N \defgroup CMSIS_glob_defs CMSIS Global Defines +N +N IO Type Qualifiers are used +N \li to specify the access to peripheral variables. +N \li for automatic generation of peripheral register debug information. +N*/ +N#ifdef __cplusplus +S #define __I volatile /*!< Defines 'read only' permissions */ +N#else +N #define __I volatile const /*!< Defines 'read only' permissions */ +N#endif +N#define __O volatile /*!< Defines 'write only' permissions */ +N#define __IO volatile /*!< Defines 'read / write' permissions */ +N +N/* following defines should be used for structure members */ +N#define __IM volatile const /*! Defines 'read only' structure member permissions */ +N#define __OM volatile /*! Defines 'write only' structure member permissions */ +N#define __IOM volatile /*! Defines 'read / write' structure member permissions */ +N +N/*@} end of group Cortex_M0 */ +N +N +N +N/******************************************************************************* +N * Register Abstraction +N Core Register contain: +N - Core Register +N - Core NVIC Register +N - Core SCB Register +N - Core SysTick Register +N ******************************************************************************/ +N/** +N \defgroup CMSIS_core_register Defines and Type Definitions +N \brief Type definitions and defines for Cortex-M processor based devices. +N*/ +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_CORE Status and Control Registers +N \brief Core Register type definitions. +N @{ +N */ +N +N/** +N \brief Union type to access the Application Program Status Register (APSR). +N */ +Ntypedef union +N{ +N struct +N { +N uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ +N uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ +N uint32_t C:1; /*!< bit: 29 Carry condition code flag */ +N uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ +N uint32_t N:1; /*!< bit: 31 Negative condition code flag */ +N } b; /*!< Structure used for bit access */ +N uint32_t w; /*!< Type used for word access */ +N} APSR_Type; +N +N/* APSR Register Definitions */ +N#define APSR_N_Pos 31U /*!< APSR: N Position */ +N#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ +N +N#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +N#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ +N +N#define APSR_C_Pos 29U /*!< APSR: C Position */ +N#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ +N +N#define APSR_V_Pos 28U /*!< APSR: V Position */ +N#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ +N +N +N/** +N \brief Union type to access the Interrupt Program Status Register (IPSR). +N */ +Ntypedef union +N{ +N struct +N { +N uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +N uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ +N } b; /*!< Structure used for bit access */ +N uint32_t w; /*!< Type used for word access */ +N} IPSR_Type; +N +N/* IPSR Register Definitions */ +N#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +N#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ +N +N +N/** +N \brief Union type to access the Special-Purpose Program Status Registers (xPSR). +N */ +Ntypedef union +N{ +N struct +N { +N uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +N uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +N uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ +N uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ +N uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ +N uint32_t C:1; /*!< bit: 29 Carry condition code flag */ +N uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ +N uint32_t N:1; /*!< bit: 31 Negative condition code flag */ +N } b; /*!< Structure used for bit access */ +N uint32_t w; /*!< Type used for word access */ +N} xPSR_Type; +N +N/* xPSR Register Definitions */ +N#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +N#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ +N +N#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +N#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ +N +N#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +N#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ +N +N#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +N#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ +N +N#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +N#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ +N +N#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +N#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ +N +N +N/** +N \brief Union type to access the Control Registers (CONTROL). +N */ +Ntypedef union +N{ +N struct +N { +N uint32_t _reserved0:1; /*!< bit: 0 Reserved */ +N uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ +N uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ +N } b; /*!< Structure used for bit access */ +N uint32_t w; /*!< Type used for word access */ +N} CONTROL_Type; +N +N/* CONTROL Register Definitions */ +N#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +N#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ +N +N/*@} end of group CMSIS_CORE */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) +N \brief Type definitions for the NVIC Registers +N @{ +N */ +N +N/** +N \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). +N */ +Ntypedef struct +N{ +N __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ +X volatile uint32_t ISER[1U]; +N uint32_t RESERVED0[31U]; +N __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ +X volatile uint32_t ICER[1U]; +N uint32_t RESERVED1[31U]; +N __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ +X volatile uint32_t ISPR[1U]; +N uint32_t RESERVED2[31U]; +N __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ +X volatile uint32_t ICPR[1U]; +N uint32_t RESERVED3[31U]; +N uint32_t RESERVED4[64U]; +N __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +X volatile uint32_t IP[8U]; +N} NVIC_Type; +N +N/*@} end of group CMSIS_NVIC */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_SCB System Control Block (SCB) +N \brief Type definitions for the System Control Block Registers +N @{ +N */ +N +N/** +N \brief Structure type to access the System Control Block (SCB). +N */ +Ntypedef struct +N{ +N __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ +X volatile const uint32_t CPUID; +N __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +X volatile uint32_t ICSR; +N uint32_t RESERVED0; +N __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ +X volatile uint32_t AIRCR; +N __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ +X volatile uint32_t SCR; +N __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ +X volatile uint32_t CCR; +N uint32_t RESERVED1; +N __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ +X volatile uint32_t SHP[2U]; +N __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +X volatile uint32_t SHCSR; +N} SCB_Type; +N +N/* SCB CPUID Register Definitions */ +N#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +N#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +N +N#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +N#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +N +N#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +N#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ +N +N#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +N#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +N +N#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +N#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ +N +N/* SCB Interrupt Control State Register Definitions */ +N#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +N#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ +N +N#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +N#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ +N +N#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +N#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ +N +N#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +N#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ +N +N#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +N#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ +N +N#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +N#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ +N +N#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +N#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ +N +N#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +N#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ +N +N#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +N#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ +N +N/* SCB Application Interrupt and Reset Control Register Definitions */ +N#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +N#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ +N +N#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +N#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ +N +N#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +N#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +N +N#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +N#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ +N +N#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +N#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ +N +N/* SCB System Control Register Definitions */ +N#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +N#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ +N +N#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +N#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ +N +N#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +N#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ +N +N/* SCB Configuration Control Register Definitions */ +N#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +N#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ +N +N#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +N#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ +N +N/* SCB System Handler Control and State Register Definitions */ +N#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +N#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ +N +N/*@} end of group CMSIS_SCB */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_SysTick System Tick Timer (SysTick) +N \brief Type definitions for the System Timer Registers. +N @{ +N */ +N +N/** +N \brief Structure type to access the System Timer (SysTick). +N */ +Ntypedef struct +N{ +N __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ +X volatile uint32_t CTRL; +N __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ +X volatile uint32_t LOAD; +N __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ +X volatile uint32_t VAL; +N __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +X volatile const uint32_t CALIB; +N} SysTick_Type; +N +N/* SysTick Control / Status Register Definitions */ +N#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +N#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ +N +N#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +N#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ +N +N#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +N#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ +N +N#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +N#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ +N +N/* SysTick Reload Register Definitions */ +N#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +N#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ +N +N/* SysTick Current Register Definitions */ +N#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +N#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ +N +N/* SysTick Calibration Register Definitions */ +N#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +N#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ +N +N#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +N#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ +N +N#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +N#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ +N +N/*@} end of group CMSIS_SysTick */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) +N \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. +N Therefore they are not covered by the Cortex-M0 header file. +N @{ +N */ +N/*@} end of group CMSIS_CoreDebug */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_core_bitfield Core register bit field macros +N \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). +N @{ +N */ +N +N/** +N \brief Mask and shift a bit field value for use in a register bit range. +N \param[in] field Name of the register bit field. +N \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. +N \return Masked and shifted value. +N*/ +N#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) +N +N/** +N \brief Mask and shift a register value to extract a bit filed value. +N \param[in] field Name of the register bit field. +N \param[in] value Value of register. This parameter is interpreted as an uint32_t type. +N \return Masked and shifted bit field value. +N*/ +N#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) +N +N/*@} end of group CMSIS_core_bitfield */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_core_base Core Definitions +N \brief Definitions for base addresses, unions, and structures. +N @{ +N */ +N +N/* Memory mapping of Core Hardware */ +N#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +N#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +N#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +N#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +N +N#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +N#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +N#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +N +N +N/*@} */ +N +N +N +N/******************************************************************************* +N * Hardware Abstraction Layer +N Core Function Interface contains: +N - Core NVIC Functions +N - Core SysTick Functions +N - Core Register Access Functions +N ******************************************************************************/ +N/** +N \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +N*/ +N +N +N +N/* ########################## NVIC functions #################################### */ +N/** +N \ingroup CMSIS_Core_FunctionInterface +N \defgroup CMSIS_Core_NVICFunctions NVIC Functions +N \brief Functions that manage interrupts and exceptions via the NVIC. +N @{ +N */ +N +N#ifdef CMSIS_NVIC_VIRTUAL +S #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +S #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +S #endif +S #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +N#else +N #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +N #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +N #define NVIC_EnableIRQ __NVIC_EnableIRQ +N #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +N #define NVIC_DisableIRQ __NVIC_DisableIRQ +N #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +N #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +N #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +N/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ +N #define NVIC_SetPriority __NVIC_SetPriority +N #define NVIC_GetPriority __NVIC_GetPriority +N #define NVIC_SystemReset __NVIC_SystemReset +N#endif /* CMSIS_NVIC_VIRTUAL */ +N +N#ifdef CMSIS_VECTAB_VIRTUAL +S #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +S #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +S #endif +S #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +N#else +N #define NVIC_SetVector __NVIC_SetVector +N #define NVIC_GetVector __NVIC_GetVector +N#endif /* (CMSIS_VECTAB_VIRTUAL) */ +N +N#define NVIC_USER_IRQ_OFFSET 16 +N +N +N/* The following EXC_RETURN values are saved the LR on exception entry */ +N#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +N#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +N#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +N +N +N/* Interrupt Priorities are WORD accessible only under Armv6-M */ +N/* The following MACROS handle generation of the register offset and byte masks */ +N#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +N#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +N#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) +N +N#define __NVIC_SetPriorityGrouping(X) (void)(X) +N#define __NVIC_GetPriorityGrouping() (0U) +N +N/** +N \brief Enable Interrupt +N \details Enables a device specific interrupt in the NVIC interrupt controller. +N \param [in] IRQn Device specific interrupt number. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +Xstatic __inline void __NVIC_EnableIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +N } +N} +N +N +N/** +N \brief Get Interrupt Enable status +N \details Returns a device specific interrupt enable status from the NVIC interrupt controller. +N \param [in] IRQn Device specific interrupt number. +N \return 0 Interrupt is not enabled. +N \return 1 Interrupt is enabled. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +Xstatic __inline uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +X return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +N } +N else +N { +N return(0U); +N } +N} +N +N +N/** +N \brief Disable Interrupt +N \details Disables a device specific interrupt in the NVIC interrupt controller. +N \param [in] IRQn Device specific interrupt number. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +Xstatic __inline void __NVIC_DisableIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +N __DSB(); +X do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); +N __ISB(); +X do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U); +N } +N} +N +N +N/** +N \brief Get Pending Interrupt +N \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. +N \param [in] IRQn Device specific interrupt number. +N \return 0 Interrupt status is not pending. +N \return 1 Interrupt status is pending. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +Xstatic __inline uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +X return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +N } +N else +N { +N return(0U); +N } +N} +N +N +N/** +N \brief Set Pending Interrupt +N \details Sets the pending bit of a device specific interrupt in the NVIC pending register. +N \param [in] IRQn Device specific interrupt number. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +Xstatic __inline void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +N } +N} +N +N +N/** +N \brief Clear Pending Interrupt +N \details Clears the pending bit of a device specific interrupt in the NVIC pending register. +N \param [in] IRQn Device specific interrupt number. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +Xstatic __inline void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +N } +N} +N +N +N/** +N \brief Set Interrupt Priority +N \details Sets the priority of a device specific interrupt or a processor exception. +N The interrupt number can be positive to specify a device specific interrupt, +N or negative to specify a processor exception. +N \param [in] IRQn Interrupt number. +N \param [in] priority Priority to set. +N \note The priority cannot be set for every processor exception. +N */ +N__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +Xstatic __inline void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] = ((uint32_t)(((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | +N (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); +X (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); +N } +N else +N { +N SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | +X ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] = ((uint32_t)(((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | +N (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); +X (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); +N } +N} +N +N +N/** +N \brief Get Interrupt Priority +N \details Reads the priority of a device specific interrupt or a processor exception. +N The interrupt number can be positive to specify a device specific interrupt, +N or negative to specify a processor exception. +N \param [in] IRQn Interrupt number. +N \return Interrupt Priority. +N Value is aligned automatically to the implemented priority bits of the microcontroller. +N */ +N__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +Xstatic __inline uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +N{ +N +N if ((int32_t)(IRQn) >= 0) +N { +N return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); +X return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[ ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); +N } +N else +N { +N return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); +X return((uint32_t)(((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); +N } +N} +N +N +N/** +N \brief Encode Priority +N \details Encodes the priority for an interrupt with the given priority group, +N preemptive priority value, and subpriority value. +N In case of a conflict between priority grouping and available +N priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +N \param [in] PriorityGroup Used priority group. +N \param [in] PreemptPriority Preemptive priority value (starting from 0). +N \param [in] SubPriority Subpriority value (starting from 0). +N \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). +N */ +N__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +Xstatic __inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +N{ +N uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ +N uint32_t PreemptPriorityBits; +N uint32_t SubPriorityBits; +N +N PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); +X PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); +N SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); +X SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); +N +N return ( +N ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | +N ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) +N ); +N} +N +N +N/** +N \brief Decode Priority +N \details Decodes an interrupt priority value with a given priority group to +N preemptive priority value and subpriority value. +N In case of a conflict between priority grouping and available +N priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. +N \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). +N \param [in] PriorityGroup Used priority group. +N \param [out] pPreemptPriority Preemptive priority value (starting from 0). +N \param [out] pSubPriority Subpriority value (starting from 0). +N */ +N__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +Xstatic __inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +N{ +N uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ +N uint32_t PreemptPriorityBits; +N uint32_t SubPriorityBits; +N +N PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); +X PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); +N SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); +X SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); +N +N *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); +N *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +N} +N +N +N +N/** +N \brief Set Interrupt Vector +N \details Sets an interrupt vector in SRAM based interrupt vector table. +N The interrupt number can be positive to specify a device specific interrupt, +N or negative to specify a processor exception. +N Address 0 must be mapped to SRAM. +N \param [in] IRQn Interrupt number +N \param [in] vector Address of interrupt handler function +N */ +N__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +Xstatic __inline void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +N{ +N uint32_t vectors = 0x0U; +N (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; +X (* (int *) (vectors + ((int32_t)IRQn + 16) * 4)) = vector; +N} +N +N +N/** +N \brief Get Interrupt Vector +N \details Reads an interrupt vector from interrupt vector table. +N The interrupt number can be positive to specify a device specific interrupt, +N or negative to specify a processor exception. +N \param [in] IRQn Interrupt number. +N \return Address of interrupt handler function +N */ +N__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +Xstatic __inline uint32_t __NVIC_GetVector(IRQn_Type IRQn) +N{ +N uint32_t vectors = 0x0U; +N return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +X return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + 16) * 4)); +N} +N +N +N/** +N \brief System Reset +N \details Initiates a system reset request to reset the MCU. +N */ +N__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +X__declspec(noreturn) static __inline void __NVIC_SystemReset(void) +N{ +N __DSB(); /* Ensure all outstanding memory accesses included +X do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); +N buffered write are completed before reset */ +N SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | +X ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR = ((0x5FAUL << 16U) | +N SCB_AIRCR_SYSRESETREQ_Msk); +X (1UL << 2U)); +N __DSB(); /* Ensure completion of memory access */ +X do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); +N +N for(;;) /* wait until reset */ +N { +N __NOP(); +X __nop(); +N } +N} +N +N/*@} end of CMSIS_Core_NVICFunctions */ +N +N +N/* ########################## FPU functions #################################### */ +N/** +N \ingroup CMSIS_Core_FunctionInterface +N \defgroup CMSIS_Core_FpuFunctions FPU Functions +N \brief Function that provides FPU type. +N @{ +N */ +N +N/** +N \brief get FPU type +N \details returns the FPU type +N \returns +N - \b 0: No FPU +N - \b 1: Single precision FPU +N - \b 2: Double + Single precision FPU +N */ +N__STATIC_INLINE uint32_t SCB_GetFPUType(void) +Xstatic __inline uint32_t SCB_GetFPUType(void) +N{ +N return 0U; /* No FPU */ +N} +N +N +N/*@} end of CMSIS_Core_FpuFunctions */ +N +N +N +N/* ################################## SysTick function ############################################ */ +N/** +N \ingroup CMSIS_Core_FunctionInterface +N \defgroup CMSIS_Core_SysTickFunctions SysTick Functions +N \brief Functions that configure the System. +N @{ +N */ +N +N#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) +X#if 1L && (0U == 0U) +N +N/** +N \brief System Tick Configuration +N \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. +N Counter is in free running mode to generate periodic interrupts. +N \param [in] ticks Number of ticks between two interrupts. +N \return 0 Function succeeded. +N \return 1 Function failed. +N \note When the variable __Vendor_SysTickConfig is set to 1, then the +N function SysTick_Config is not included. In this case, the file device.h +N must contain a vendor-specific implementation of this function. +N */ +N__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +Xstatic __inline uint32_t SysTick_Config(uint32_t ticks) +N{ +N if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) +X if ((ticks - 1UL) > (0xFFFFFFUL )) +N { +N return (1UL); /* Reload value impossible */ +N } +N +N SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ +X ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->LOAD = (uint32_t)(ticks - 1UL); +N NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ +X __NVIC_SetPriority (SysTick_IRQn, (1UL << 2U) - 1UL); +N SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ +X ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->VAL = 0UL; +N SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | +X ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL = (1UL << 2U) | +N SysTick_CTRL_TICKINT_Msk | +X (1UL << 1U) | +N SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ +X (1UL ); +N return (0UL); /* Function successful */ +N} +N +N#endif +N +N/*@} end of CMSIS_Core_SysTickFunctions */ +N +N +N +N +N#ifdef __cplusplus +S} +N#endif +N +N#endif /* __CORE_CM0_H_DEPENDANT */ +N +N#endif /* __CMSIS_GENERIC */ +L 122 "..\..\src\sdk\include\M0\ArmCM0.h" 2 +N#include "system_ARMCM0.h" /* System Header */ +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include\system_ARMCM0.h" 1 +N/**************************************************************************//** +N * @file system_ARMCM0.h +N * @brief CMSIS Device System Header File for +N * ARMCM0 Device +N * @version V5.3.1 +N * @date 09. July 2018 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#ifndef SYSTEM_ARMCM0_H +N#define SYSTEM_ARMCM0_H +N +N#ifdef __cplusplus +Sextern "C" { +N#endif +N +Nextern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +N +N +N/** +N \brief Setup the microcontroller system. +N +N Initialize the System and update the SystemCoreClock variable. +N */ +Nextern void SystemInit (void); +N +N +N/** +N \brief Update SystemCoreClock variable. +N +N Updates the SystemCoreClock with current core Clock retrieved from cpu registers. +N */ +Nextern void SystemCoreClockUpdate (void); +N +N#ifdef __cplusplus +S} +N#endif +N +N#endif /* SYSTEM_ARMCM0_H */ +L 123 "..\..\src\sdk\include\M0\ArmCM0.h" 2 +N +N/* -------- End of section using anonymous unions and disabling warnings -------- */ +N#if defined (__CC_ARM) +X#if 1L +N#pragma pop +N#elif defined (__ICCARM__) +X#elif 0L +S/* leave anonymous unions enabled */ +S#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +S#pragma clang diagnostic pop +S#elif defined (__GNUC__) +S/* anonymous unions are enabled by default */ +S#elif defined (__TMS470__) +S/* anonymous unions are enabled by default */ +S#elif defined (__TASKING__) +S#pragma warning restore +S#elif defined (__CSMC__) +S/* anonymous unions are enabled by default */ +S#else +S#warning Not supported compiler type +N#endif +N +N/* In HS mode and when the DMA is used, all variables and data structures dealing +N with the DMA during the transaction process should be 4-bytes aligned */ +N#define DMA_WORD_ALIGN_EN +N#ifdef DMA_WORD_ALIGN_EN +N#if defined (__GNUC__) /* GNU Compiler */ +X#if 1L +N#define __ALIGN_END __attribute__ ((aligned (4))) +N#define __ALIGN_BEGIN +N#else +S#define __ALIGN_END +S#if defined (__CC_ARM) /* ARM Compiler */ +S#define __ALIGN_BEGIN __align(4) +S#elif defined (__ICCARM__) /* IAR Compiler */ +S#define __ALIGN_BEGIN +S#elif defined (__TASKING__) /* TASKING Compiler */ +S#define __ALIGN_BEGIN __align(4) +S#endif /* __CC_ARM */ +N#endif /* __GNUC__ */ +N#else +S +S#define __ALIGN_BEGIN +S#define __ALIGN_END +S +S#define __ALIGN_END_1 __attribute__ ((aligned (1))) +N#endif /* DMA_WORD_ALIGN_EN */ +N +N/* __packed keyword used to decrease the data type alignment to 1-byte */ +N#if defined (__CC_ARM) /* ARM Compiler */ +X#if 1L +N#define __packed __packed +N#elif defined (__ICCARM__) /* IAR Compiler */ +X#elif 0L +S#define __packed __packed +S#elif defined ( __GNUC__ ) /* GNU Compiler */ +S#define __packed __attribute__ ((__packed__)) +S#define __weak __attribute__((weak)) +S#elif defined (__TASKING__) /* TASKING Compiler */ +S#define __packed __unaligned +N#endif /* __CC_ARM */ +N +N#ifdef __cplusplus +S} +N#endif +N +N#endif /* ARMCM0_H */ +L 21 "..\..\src\common\tau_log.h" 2 +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N#ifdef LOG_TAG +S#undef LOG_TAG +N#endif +N#define LOG_TAG "tau_log" +N#define LOG_CURREN_LEVEL kLOG_LEVEL_DBG /* 配置打印等级 TODO:每个模块可配置打印等级 */ +N#define LOG_BUF_SIZE (256) /* 配置打印缓存的大小 */ +N +N/* +N * Using the following three macros for conveniently logging. +N */ +N#define TAU_LOGD(format,...) \ +N do { \ +N tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); \ +N } while (0) +X#define TAU_LOGD(format,...) do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); } while (0) +N +N#define TAU_LOGI(format,...) \ +N do { \ +N tau_log_printf(kLOG_LEVEL_INF, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); \ +N } while (0) +X#define TAU_LOGI(format,...) do { tau_log_printf(kLOG_LEVEL_INF, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); } while (0) +N +N#define TAU_LOGE(format,...) \ +N do { \ +N tau_log_printf(kLOG_LEVEL_ERR, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); \ +N } while (0) +X#define TAU_LOGE(format,...) do { tau_log_printf(kLOG_LEVEL_ERR, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); } while (0) +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/** +N* @brief log打印等级枚举 +N* +N*/ +Ntypedef enum +N{ +N kLOG_LEVEL_DBG = 0, +N kLOG_LEVEL_INF, +N kLOG_LEVEL_ERR, +N kLOG_LEVEL_NONE /* 不打印任何参数 */ +N} log_level_e; +N +N/** +N* @brief log打印端口枚举 +N* +N*/ +Ntypedef enum +N{ +N LOG_PORT_UART0, /* 使用串口输出打印 */ +N LOG_PORT_UART1, /* 使用串口输出打印 */ +N LOG_PORT_SWD, /* 使用swd输出打印 */ +N LOG_PORT_UNKNOWN +N} log_port_e; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N/** +N* @brief 初始化log系统 +N* @param baud_rate 波特率 +N* @param log_port 打印端口选择 +N* @retval none +N*/ +Nvoid tau_log_init(uint32_t baud_rate, log_port_e log_port); +N +N/** +N* @brief 初始化log系统 +N* @param baud_rate 波特率 +N* @param log_port 打印端口选择 +N* @retval none +N*/ +Nvoid tau_log_printf(log_level_e log_lv, const char *fmt, ...); +N +N#endif +L 6 "..\..\src\app\main.c" 2 +N#include "hal_system.h" +L 1 "..\..\src\sdk\include\hal_system.h" 1 +N/******************************************************************************* +N* +N* +N* File: hal_system.h +N* Description hal 通用系统接口头文件 +N* Version V0.1 +N* Date 2021-05-21 +N* Author lzy +N *******************************************************************************/ +N#ifndef __HAL_SYSTEM_H__ +N#define __HAL_SYSTEM_H__ +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_common.h" +L 1 "..\..\src\common\tau_common.h" 1 +N/******************************************************************************* +N* +N* +N* File: tau_common.h +N* Description 通用数据类型相关定义头文件 +N* Version V0.1 +N* Date 2020-09-07 +N* Author lzy +N *******************************************************************************/ +N +N#ifndef __TAU_COMMON_H +N#define __TAU_COMMON_H +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "stdint.h" +N#include "math.h" +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h" 1 +N/* +N * math.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.5 +N * Copyright (C) Codemist Ltd., 1988 +N * Copyright 1991-1998,2004-2006,2014 ARM Limited. All rights reserved +N */ +N +N/* +N * RCS $Revision$ Codemist 0.03 +N * Checkin $Date$ +N * Revising $Author: statham $ +N */ +N +N/* +N * Parts of this file are based upon fdlibm: +N * +N * ==================================================== +N * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. +N * +N * Developed at SunSoft, a Sun Microsystems, Inc. business. +N * Permission to use, copy, modify, and distribute this +N * software is freely granted, provided that this notice +N * is preserved. +N * ==================================================== +N */ +N +N#ifndef __math_h +N#define __math_h +N#define __ARMCLIB_VERSION 5060037 +N +N#if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__)) +X#if 0L || (1L && !0L) +N /* armclang and non-strict armcc allow 'long long' in system headers */ +N #define __LONGLONG long long +N#else +S /* strict armcc has '__int64' */ +S #define __LONGLONG __int64 +N#endif +N +N/* +N * Some of these declarations are new in C99. To access them in C++ +N * you can use -D__USE_C99_MATH (or -D__USE_C99_ALL). +N */ +N#ifndef __USE_C99_MATH +N #if defined(__USE_C99_ALL) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) +X #if 0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus) +N #define __USE_C99_MATH 1 +N #endif +N#endif +N +N#define _ARMABI __declspec(__nothrow) +N#ifdef __TARGET_ARCH_AARCH64 +S# define _ARMABI_SOFTFP __declspec(__nothrow) +N#else +N# define _ARMABI_SOFTFP __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) +N# define __HAVE_LONGDOUBLE 1 +N#endif +N#define _ARMABI_PURE __declspec(__nothrow) __attribute__((const)) +N#ifdef __FP_FENV_EXCEPTIONS +S# define _ARMABI_FPEXCEPT _ARMABI +N#else +N# define _ARMABI_FPEXCEPT _ARMABI __attribute__((const)) +N#endif +N +N#ifdef __cplusplus +S#define _ARMABI_INLINE inline +S#define _ARMABI_INLINE_DEF inline +N#elif defined __GNUC__ || defined _USE_STATIC_INLINE +X#elif 1L || 0L +N#define _ARMABI_INLINE static __inline +N#define _ARMABI_INLINE_DEF static __inline +N#elif (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) +X#elif (1L && 199901L <= 199901L) +S#define _ARMABI_INLINE inline +S#define _ARMABI_INLINE_DEF static inline +S#else +S#define _ARMABI_INLINE __inline +S#define _ARMABI_INLINE_DEF __inline +N#endif +N +N#ifdef __TARGET_ARCH_AARCH64 +S# define _SOFTFP +N#else +N# define _SOFTFP __attribute__((__pcs__("aapcs"))) +N#endif +N +N /* +N * If the compiler supports signalling nans as per N965 then it +N * will define __SUPPORT_SNAN__, in which case a user may define +N * _WANT_SNAN in order to obtain the nans function, as well as the +N * FP_NANS and FP_NANQ classification macros. +N */ +N#if defined(__SUPPORT_SNAN__) && defined(_WANT_SNAN) +X#if 0L && 0L +S#pragma import(__use_snan) +N#endif +N +N/* +N * Macros for our inline functions down below. +N * unsigned& __FLT(float x) - returns the bit pattern of x +N * unsigned& __HI(double x) - returns the bit pattern of the high part of x +N * (high part has exponent & sign bit in it) +N * unsigned& __LO(double x) - returns the bit pattern of the low part of x +N * +N * We can assign to __FLT, __HI, and __LO and the appropriate bits get set in +N * the floating point variable used. +N * +N * __HI & __LO are affected by the endianness and the target FPU. +N */ +N#define __FLT(x) (*(unsigned *)&(x)) +N#if defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN) +X#if 0L || 0L +S# define __LO(x) (*(1 + (unsigned *)&(x))) +S# define __HI(x) (*(unsigned *)&(x)) +N#else /* !defined(__ARM_BIG_ENDIAN) && !defined(__BIG_ENDIAN) */ +N# define __HI(x) (*(1 + (unsigned *)&(x))) +N# define __LO(x) (*(unsigned *)&(x)) +N#endif /* !defined(__ARM_BIG_ENDIAN) && !defined(__BIG_ENDIAN) */ +N +N# ifndef __MATH_DECLS +N# define __MATH_DECLS +N +N +N/* +N * A set of functions that we don't actually want to put in the standard +N * namespace ever. These are all called by the C99 macros. As they're +N * not specified by any standard they can't belong in ::std::. The +N * macro #defines are below amongst the standard function declarations. +N * We only include these if we actually need them later on +N */ +N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +X#if !0L || 1L +N# ifdef __cplusplus +S extern "C" { +N# endif /* __cplusplus */ +N +Nextern _SOFTFP unsigned __ARM_dcmp4(double /*x*/, double /*y*/); +Xextern __attribute__((__pcs__("aapcs"))) unsigned __ARM_dcmp4(double , double ); +Nextern _SOFTFP unsigned __ARM_fcmp4(float /*x*/, float /*y*/); +Xextern __attribute__((__pcs__("aapcs"))) unsigned __ARM_fcmp4(float , float ); +N /* +N * Compare x and y and return the CPSR in r0. These means we can test for +N * result types with bit pattern matching. +N * +N * These are a copy of the declarations in rt_fp.h keep in sync. +N */ +N +Nextern _ARMABI_SOFTFP int __ARM_fpclassifyf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassifyf(float ); +Nextern _ARMABI_SOFTFP int __ARM_fpclassify(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassify(double ); +N /* Classify x into NaN, infinite, normal, subnormal, zero */ +N /* Used by fpclassify macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isfinitef(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinitef(float __x) +N{ +N return ((__FLT(__x) >> 23) & 0xff) != 0xff; +X return (((*(unsigned *)&(__x)) >> 23) & 0xff) != 0xff; +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isfinite(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinite(double __x) +N{ +N return ((__HI(__x) >> 20) & 0x7ff) != 0x7ff; +X return (((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff) != 0x7ff; +N} +N /* Return 1 if __x is finite, 0 otherwise */ +N /* Used by isfinite macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isinff(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinff(float __x) +N{ +N return (__FLT(__x) << 1) == 0xff000000; +X return ((*(unsigned *)&(__x)) << 1) == 0xff000000; +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isinf(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinf(double __x) +N{ +N return ((__HI(__x) << 1) == 0xffe00000) && (__LO(__x) == 0); +X return (((*(1 + (unsigned *)&(__x))) << 1) == 0xffe00000) && ((*(unsigned *)&(__x)) == 0); +N} +N /* Return 1 if __x is infinite, 0 otherwise */ +N /* Used by isinf macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_islessgreaterf(float __x, float __y) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreaterf(float __x, float __y) +N{ +N unsigned __f = __ARM_fcmp4(__x, __y) >> 28; +N return (__f == 8) || (__f == 2); /* Just N set or Just Z set */ +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_islessgreater(double __x, double __y) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreater(double __x, double __y) +N{ +N unsigned __f = __ARM_dcmp4(__x, __y) >> 28; +N return (__f == 8) || (__f == 2); /* Just N set or Just Z set */ +N} +N /* +N * Compare __x and __y and return 1 if __x < __y or __x > __y, 0 otherwise +N * Used by islessgreater macro +N */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnanf(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnanf(float __x) +N{ +N return (0x7f800000 - (__FLT(__x) & 0x7fffffff)) >> 31; +X return (0x7f800000 - ((*(unsigned *)&(__x)) & 0x7fffffff)) >> 31; +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnan(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnan(double __x) +N{ +N unsigned __xf = __HI(__x) | ((__LO(__x) == 0) ? 0 : 1); +X unsigned __xf = (*(1 + (unsigned *)&(__x))) | (((*(unsigned *)&(__x)) == 0) ? 0 : 1); +N return (0x7ff00000 - (__xf & 0x7fffffff)) >> 31; +N} +N /* Return 1 if __x is a NaN, 0 otherwise */ +N /* Used by isnan macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnormalf(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormalf(float __x) +N{ +N unsigned __xe = (__FLT(__x) >> 23) & 0xff; +X unsigned __xe = ((*(unsigned *)&(__x)) >> 23) & 0xff; +N return (__xe != 0xff) && (__xe != 0); +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnormal(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormal(double __x) +N{ +N unsigned __xe = (__HI(__x) >> 20) & 0x7ff; +X unsigned __xe = ((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff; +N return (__xe != 0x7ff) && (__xe != 0); +N} +N /* Return 1 if __x is a normalised number, 0 otherwise */ +N /* used by isnormal macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_signbitf(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbitf(float __x) +N{ +N return __FLT(__x) >> 31; +X return (*(unsigned *)&(__x)) >> 31; +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_signbit(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbit(double __x) +N{ +N return __HI(__x) >> 31; +X return (*(1 + (unsigned *)&(__x))) >> 31; +N} +N /* Return signbit of __x */ +N /* Used by signbit macro */ +N +N# ifdef __cplusplus +S } /* extern "C" */ +N# endif /* __cplusplus */ +N#endif /* Strict ANSI */ +N +N# undef __CLIBNS +N +N# ifdef __cplusplus +S namespace std { +S# define __CLIBNS ::std:: +S extern "C" { +N# else +N# define __CLIBNS +N# endif /* __cplusplus */ +N +N +N#ifndef __has_builtin +N #define __has_builtin(x) 0 +N#endif +N +N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +X#if !0L || 1L +N /* C99 additions */ +N typedef float float_t; +N typedef double double_t; +N#if __has_builtin(__builtin_inf) +X#if 0 +S# define HUGE_VALF __builtin_inff() +S# define HUGE_VALL __builtin_infl() +S# define INFINITY __builtin_inff() +S# define NAN __builtin_nanf("") +N# else +N# define HUGE_VALF ((float)__INFINITY__) +N# define HUGE_VALL ((long double)__INFINITY__) +N# define INFINITY ((float)__INFINITY__) +N# define NAN (__ESCAPE__(0f_7FC00000)) +N#endif +N +N# define MATH_ERRNO 1 +N# define MATH_ERREXCEPT 2 +Nextern const int math_errhandling; +N#endif +N#if __has_builtin(__builtin_inf) +X#if 0 +S# define HUGE_VAL __builtin_inf() +N#else +N# define HUGE_VAL ((double)__INFINITY__) +N#endif +N +Nextern _ARMABI double acos(double /*x*/); +Xextern __declspec(__nothrow) double acos(double ); +N /* computes the principal value of the arc cosine of x */ +N /* a domain error occurs for arguments not in the range -1 to 1 */ +N /* Returns: the arc cosine in the range 0 to Pi. */ +Nextern _ARMABI double asin(double /*x*/); +Xextern __declspec(__nothrow) double asin(double ); +N /* computes the principal value of the arc sine of x */ +N /* a domain error occurs for arguments not in the range -1 to 1 */ +N /* and -HUGE_VAL is returned. */ +N /* Returns: the arc sine in the range -Pi/2 to Pi/2. */ +N +Nextern _ARMABI_PURE double atan(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double atan(double ); +N /* computes the principal value of the arc tangent of x */ +N /* Returns: the arc tangent in the range -Pi/2 to Pi/2. */ +N +Nextern _ARMABI double atan2(double /*y*/, double /*x*/); +Xextern __declspec(__nothrow) double atan2(double , double ); +N /* computes the principal value of the arc tangent of y/x, using the */ +N /* signs of both arguments to determine the quadrant of the return value */ +N /* a domain error occurs if both args are zero, and -HUGE_VAL returned. */ +N /* Returns: the arc tangent of y/x, in the range -Pi to Pi. */ +N +Nextern _ARMABI double cos(double /*x*/); +Xextern __declspec(__nothrow) double cos(double ); +N /* computes the cosine of x (measured in radians). A large magnitude */ +N /* argument may yield a result with little or no significance. */ +N /* a domain error occurs for infinite input (C 7.12.1 footnote 196). */ +N /* Returns: the cosine value. */ +Nextern _ARMABI double sin(double /*x*/); +Xextern __declspec(__nothrow) double sin(double ); +N /* computes the sine of x (measured in radians). A large magnitude */ +N /* argument may yield a result with little or no significance. */ +N /* a domain error occurs for infinite input (C 7.12.1 footnote 196). */ +N /* Returns: the sine value. */ +N +Nextern void __use_accurate_range_reduction(void); +N /* reference this to select the larger, slower, but more accurate */ +N /* range reduction in sin, cos and tan */ +N +Nextern _ARMABI double tan(double /*x*/); +Xextern __declspec(__nothrow) double tan(double ); +N /* computes the tangent of x (measured in radians). A large magnitude */ +N /* argument may yield a result with little or no significance */ +N /* Returns: the tangent value. */ +N /* if range error; returns HUGE_VAL. */ +N +Nextern _ARMABI double cosh(double /*x*/); +Xextern __declspec(__nothrow) double cosh(double ); +N /* computes the hyperbolic cosine of x. A range error occurs if the */ +N /* magnitude of x is too large. */ +N /* Returns: the hyperbolic cosine value. */ +N /* if range error; returns HUGE_VAL. */ +Nextern _ARMABI double sinh(double /*x*/); +Xextern __declspec(__nothrow) double sinh(double ); +N /* computes the hyperbolic sine of x. A range error occurs if the */ +N /* magnitude of x is too large. */ +N /* Returns: the hyperbolic sine value. */ +N /* if range error; returns -HUGE_VAL or HUGE_VAL depending */ +N /* on the sign of the argument */ +N +Nextern _ARMABI_PURE double tanh(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double tanh(double ); +N /* computes the hyperbolic tangent of x. */ +N /* Returns: the hyperbolic tangent value. */ +N +Nextern _ARMABI double exp(double /*x*/); +Xextern __declspec(__nothrow) double exp(double ); +N /* computes the exponential function of x. A range error occurs if the */ +N /* magnitude of x is too large. */ +N /* Returns: the exponential value. */ +N /* if underflow range error; 0 is returned. */ +N /* if overflow range error; HUGE_VAL is returned. */ +N +Nextern _ARMABI double frexp(double /*value*/, int * /*exp*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) double frexp(double , int * ) __attribute__((__nonnull__(2))); +N /* breaks a floating-point number into a normalised fraction and an */ +N /* integral power of 2. It stores the integer in the int object pointed */ +N /* to by exp. */ +N /* Returns: the value x, such that x is a double with magnitude in the */ +N /* interval 0.5 to 1.0 or zero, and value equals x times 2 raised to the */ +N /* power *exp. If value is zero, both parts of the result are zero. */ +N +Nextern _ARMABI double ldexp(double /*x*/, int /*exp*/); +Xextern __declspec(__nothrow) double ldexp(double , int ); +N /* multiplies a floating-point number by an integral power of 2. */ +N /* A range error may occur. */ +N /* Returns: the value of x times 2 raised to the power of exp. */ +N /* if range error; HUGE_VAL is returned. */ +Nextern _ARMABI double log(double /*x*/); +Xextern __declspec(__nothrow) double log(double ); +N /* computes the natural logarithm of x. A domain error occurs if the */ +N /* argument is negative, and -HUGE_VAL is returned. A range error occurs */ +N /* if the argument is zero. */ +N /* Returns: the natural logarithm. */ +N /* if range error; -HUGE_VAL is returned. */ +Nextern _ARMABI double log10(double /*x*/); +Xextern __declspec(__nothrow) double log10(double ); +N /* computes the base-ten logarithm of x. A domain error occurs if the */ +N /* argument is negative. A range error occurs if the argument is zero. */ +N /* Returns: the base-ten logarithm. */ +Nextern _ARMABI double modf(double /*value*/, double * /*iptr*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) double modf(double , double * ) __attribute__((__nonnull__(2))); +N /* breaks the argument value into integral and fraction parts, each of */ +N /* which has the same sign as the argument. It stores the integral part */ +N /* as a double in the object pointed to by iptr. */ +N /* Returns: the signed fractional part of value. */ +N +Nextern _ARMABI double pow(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double pow(double , double ); +N /* computes x raised to the power of y. A domain error occurs if x is */ +N /* zero and y is less than or equal to zero, or if x is negative and y */ +N /* is not an integer, and -HUGE_VAL returned. A range error may occur. */ +N /* Returns: the value of x raised to the power of y. */ +N /* if underflow range error; 0 is returned. */ +N /* if overflow range error; HUGE_VAL is returned. */ +Nextern _ARMABI double sqrt(double /*x*/); +Xextern __declspec(__nothrow) double sqrt(double ); +N /* computes the non-negative square root of x. A domain error occurs */ +N /* if the argument is negative, and -HUGE_VAL returned. */ +N /* Returns: the value of the square root. */ +N +N#if defined(__TARGET_FPU_VFP_DOUBLE) && !defined(__TARGET_FPU_SOFTVFP) +X#if 0L && !1L +S _ARMABI_INLINE double _sqrt(double __x) { return __sqrt(__x); } +N#else +N _ARMABI_INLINE double _sqrt(double __x) { return sqrt(__x); } +X static __inline double _sqrt(double __x) { return sqrt(__x); } +N#endif +N#if defined(__TARGET_FPU_VFP_SINGLE) && !defined(__TARGET_FPU_SOFTVFP) +X#if 0L && !1L +S _ARMABI_INLINE float _sqrtf(float __x) { return __sqrtf(__x); } +N#else +N _ARMABI_INLINE float _sqrtf(float __x) { return (float)sqrt(__x); } +X static __inline float _sqrtf(float __x) { return (float)sqrt(__x); } +N#endif +N /* With VFP, _sqrt and _sqrtf should expand inline as the native VFP square root +N * instructions. They will not behave like the C sqrt() function, because +N * they will report unusual values as IEEE exceptions (in fpmodes which +N * support IEEE exceptions) rather than in errno. These function names +N * are not specified in any standard. */ +N +Nextern _ARMABI_PURE double ceil(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double ceil(double ); +N /* computes the smallest integer not less than x. */ +N /* Returns: the smallest integer not less than x, expressed as a double. */ +Nextern _ARMABI_PURE double fabs(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double fabs(double ); +N /* computes the absolute value of the floating-point number x. */ +N /* Returns: the absolute value of x. */ +N +Nextern _ARMABI_PURE double floor(double /*d*/); +Xextern __declspec(__nothrow) __attribute__((const)) double floor(double ); +N /* computes the largest integer not greater than x. */ +N /* Returns: the largest integer not greater than x, expressed as a double */ +N +Nextern _ARMABI double fmod(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double fmod(double , double ); +N /* computes the floating-point remainder of x/y. */ +N /* Returns: the value x - i * y, for some integer i such that, if y is */ +N /* nonzero, the result has the same sign as x and magnitude */ +N /* less than the magnitude of y. If y is zero, a domain error */ +N /* occurs and -HUGE_VAL is returned. */ +N +N /* Additional Mathlib functions not defined by the ANSI standard. +N * Not guaranteed, and not necessarily very well tested. +N * C99 requires the user to include to use these functions +N * declaring them "by hand" is not sufficient +N * +N * The above statement is not completely true now. Some of the above +N * C99 functionality has been added as per the Standard, and (where +N * necessary) old Mathlib functionality withdrawn/changed. Before +N * including this header #define __ENABLE_MATHLIB_LEGACY if you want to +N * re-enable the legacy functionality. +N */ +N +N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +X#if !0L || 1L +N +Nextern _ARMABI double acosh(double /*x*/); +Xextern __declspec(__nothrow) double acosh(double ); +N /* +N * Inverse cosh. EDOM if argument < 1.0 +N */ +Nextern _ARMABI double asinh(double /*x*/); +Xextern __declspec(__nothrow) double asinh(double ); +N /* +N * Inverse sinh. +N */ +Nextern _ARMABI double atanh(double /*x*/); +Xextern __declspec(__nothrow) double atanh(double ); +N /* +N * Inverse tanh. EDOM if |argument| > 1.0 +N */ +Nextern _ARMABI double cbrt(double /*x*/); +Xextern __declspec(__nothrow) double cbrt(double ); +N /* +N * Cube root. +N */ +N_ARMABI_INLINE _ARMABI_PURE double copysign(double __x, double __y) +Xstatic __inline __declspec(__nothrow) __attribute__((const)) double copysign(double __x, double __y) +N /* +N * Returns x with sign bit replaced by sign of y. +N */ +N{ +N __HI(__x) = (__HI(__x) & 0x7fffffff) | (__HI(__y) & 0x80000000); +X (*(1 + (unsigned *)&(__x))) = ((*(1 + (unsigned *)&(__x))) & 0x7fffffff) | ((*(1 + (unsigned *)&(__y))) & 0x80000000); +N return __x; +N} +N_ARMABI_INLINE _ARMABI_PURE float copysignf(float __x, float __y) +Xstatic __inline __declspec(__nothrow) __attribute__((const)) float copysignf(float __x, float __y) +N /* +N * Returns x with sign bit replaced by sign of y. +N */ +N{ +N __FLT(__x) = (__FLT(__x) & 0x7fffffff) | (__FLT(__y) & 0x80000000); +X (*(unsigned *)&(__x)) = ((*(unsigned *)&(__x)) & 0x7fffffff) | ((*(unsigned *)&(__y)) & 0x80000000); +N return __x; +N} +Nextern _ARMABI double erf(double /*x*/); +Xextern __declspec(__nothrow) double erf(double ); +N /* +N * Error function. (2/sqrt(pi)) * integral from 0 to x of exp(-t*t) dt. +N */ +Nextern _ARMABI double erfc(double /*x*/); +Xextern __declspec(__nothrow) double erfc(double ); +N /* +N * 1-erf(x). (More accurate than just coding 1-erf(x), for large x.) +N */ +Nextern _ARMABI double expm1(double /*x*/); +Xextern __declspec(__nothrow) double expm1(double ); +N /* +N * exp(x)-1. (More accurate than just coding exp(x)-1, for small x.) +N */ +N#define fpclassify(x) \ +N ((sizeof(x) == sizeof(float)) ? \ +N __ARM_fpclassifyf(x) : __ARM_fpclassify(x)) +X#define fpclassify(x) ((sizeof(x) == sizeof(float)) ? __ARM_fpclassifyf(x) : __ARM_fpclassify(x)) +N /* +N * Classify a floating point number into one of the following values: +N */ +N#define FP_ZERO (0) +N#define FP_SUBNORMAL (4) +N#define FP_NORMAL (5) +N#define FP_INFINITE (3) +N#define FP_NAN (7) +N +N#if defined(_WANT_SNAN) && defined(__SUPPORT_SNAN__) +X#if 0L && 0L +S/* +S * Note that we'll never classify a number as FP_NAN, as all NaNs will +S * be either FP_NANQ or FP_NANS +S */ +S# define FP_NANQ (8) +S# define FP_NANS (9) +N#endif +N +N +Nextern _ARMABI double hypot(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double hypot(double , double ); +N /* +N * sqrt(x*x+y*y), ie the length of the vector (x,y) or the +N * hypotenuse of a right triangle whose other two sides are x +N * and y. Won't overflow unless the _answer_ is too big, even +N * if the intermediate x*x+y*y is too big. +N */ +Nextern _ARMABI int ilogb(double /*x*/); +Xextern __declspec(__nothrow) int ilogb(double ); +N /* +N * Exponent of x (returns 0 for 1.0, 1 for 2.0, -1 for 0.5, etc.) +N */ +Nextern _ARMABI int ilogbf(float /*x*/); +Xextern __declspec(__nothrow) int ilogbf(float ); +N /* +N * Like ilogb but takes a float +N */ +Nextern _ARMABI int ilogbl(long double /*x*/); +Xextern __declspec(__nothrow) int ilogbl(long double ); +N /* +N * Exponent of x (returns 0 for 1.0, 1 for 2.0, -1 for 0.5, etc.) +N */ +N#define FP_ILOGB0 (-0x7fffffff) /* ilogb(0) == -INT_MAX */ +N#define FP_ILOGBNAN ( 0x80000000) /* ilogb(NAN) == INT_MIN */ +N +N#define isfinite(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_isfinitef(x) \ +N : __ARM_isfinite(x)) +X#define isfinite(x) ((sizeof(x) == sizeof(float)) ? __ARM_isfinitef(x) : __ARM_isfinite(x)) +N /* +N * Returns true if x is a finite number, size independent. +N */ +N +N#define isgreater(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000) \ +N : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000)) +X#define isgreater(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000)) +N /* +N * Returns true if x > y, throws no exceptions except on Signaling NaNs +N * +N * We want the C not set but the Z bit clear, V must be clear +N */ +N +N#define isgreaterequal(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000) \ +N : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000)) +X#define isgreaterequal(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000)) +N /* +N * Returns true if x >= y, throws no exceptions except on Signaling NaNs +N * +N * We just need to see if the C bit is set or not and ensure V clear +N */ +N +N#define isinf(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_isinff(x) \ +N : __ARM_isinf(x)) +X#define isinf(x) ((sizeof(x) == sizeof(float)) ? __ARM_isinff(x) : __ARM_isinf(x)) +N /* +N * Returns true if x is an infinity, size independent. +N */ +N +N#define isless(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000) \ +N : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000)) +X#define isless(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000)) +N /* +N * Returns true if x < y, throws no exceptions except on Signaling NaNs +N * +N * We're less than if N is set, V clear +N */ +N +N#define islessequal(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0) \ +N : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0)) +X#define islessequal(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0) : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0)) +N /* +N * Returns true if x <= y, throws no exceptions except on Signaling NaNs +N * +N * We're less than or equal if one of N or Z is set, V clear +N */ +N +N#define islessgreater(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? __ARM_islessgreaterf((x), (y)) \ +N : __ARM_islessgreater((x), (y))) +X#define islessgreater(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? __ARM_islessgreaterf((x), (y)) : __ARM_islessgreater((x), (y))) +N /* +N * Returns true if x <> y, throws no exceptions except on Signaling NaNs +N * Unfortunately this test is too complicated to do in a macro without +N * evaluating x & y twice. Shame really... +N */ +N +N#define isnan(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_isnanf(x) \ +N : __ARM_isnan(x)) +X#define isnan(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnanf(x) : __ARM_isnan(x)) +N /* +N * Returns TRUE if x is a NaN. +N */ +N +N#define isnormal(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_isnormalf(x) \ +N : __ARM_isnormal(x)) +X#define isnormal(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnormalf(x) : __ARM_isnormal(x)) +N /* +N * Returns TRUE if x is a NaN. +N */ +N +N#define isunordered(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000) \ +N : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000)) +X#define isunordered(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000) : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000)) +N /* +N * Returns true if x ? y, throws no exceptions except on Signaling NaNs +N * Unordered occurs if and only if the V bit is set +N */ +N +Nextern _ARMABI double lgamma (double /*x*/); +Xextern __declspec(__nothrow) double lgamma (double ); +N /* +N * The log of the absolute value of the gamma function of x. The sign +N * of the gamma function of x is returned in the global `signgam'. +N */ +Nextern _ARMABI double log1p(double /*x*/); +Xextern __declspec(__nothrow) double log1p(double ); +N /* +N * log(1+x). (More accurate than just coding log(1+x), for small x.) +N */ +Nextern _ARMABI double logb(double /*x*/); +Xextern __declspec(__nothrow) double logb(double ); +N /* +N * Like ilogb but returns a double. +N */ +Nextern _ARMABI float logbf(float /*x*/); +Xextern __declspec(__nothrow) float logbf(float ); +N /* +N * Like logb but takes and returns float +N */ +Nextern _ARMABI long double logbl(long double /*x*/); +Xextern __declspec(__nothrow) long double logbl(long double ); +N /* +N * Like logb but takes and returns long double +N */ +Nextern _ARMABI double nextafter(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double nextafter(double , double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI float nextafterf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float nextafterf(float , float ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI long double nextafterl(long double /*x*/, long double /*y*/); +Xextern __declspec(__nothrow) long double nextafterl(long double , long double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI double nexttoward(double /*x*/, long double /*y*/); +Xextern __declspec(__nothrow) double nexttoward(double , long double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI float nexttowardf(float /*x*/, long double /*y*/); +Xextern __declspec(__nothrow) float nexttowardf(float , long double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI long double nexttowardl(long double /*x*/, long double /*y*/); +Xextern __declspec(__nothrow) long double nexttowardl(long double , long double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI double remainder(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double remainder(double , double ); +N /* +N * Returns the remainder of x by y, in the IEEE 754 sense. +N */ +Nextern _ARMABI_FPEXCEPT double rint(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double rint(double ); +N /* +N * Rounds x to an integer, in the IEEE 754 sense. +N */ +Nextern _ARMABI double scalbln(double /*x*/, long int /*n*/); +Xextern __declspec(__nothrow) double scalbln(double , long int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI float scalblnf(float /*x*/, long int /*n*/); +Xextern __declspec(__nothrow) float scalblnf(float , long int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI long double scalblnl(long double /*x*/, long int /*n*/); +Xextern __declspec(__nothrow) long double scalblnl(long double , long int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI double scalbn(double /*x*/, int /*n*/); +Xextern __declspec(__nothrow) double scalbn(double , int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI float scalbnf(float /*x*/, int /*n*/); +Xextern __declspec(__nothrow) float scalbnf(float , int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI long double scalbnl(long double /*x*/, int /*n*/); +Xextern __declspec(__nothrow) long double scalbnl(long double , int ); +N /* +N * Compute x times 2^n quickly. +N */ +N#define signbit(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_signbitf(x) \ +N : __ARM_signbit(x)) +X#define signbit(x) ((sizeof(x) == sizeof(float)) ? __ARM_signbitf(x) : __ARM_signbit(x)) +N /* +N * Returns the signbit of x, size independent macro +N */ +N#endif +N +N/* C99 float versions of functions. math.h has always reserved these +N identifiers for this purpose (7.13.4). */ +Nextern _ARMABI_PURE float _fabsf(float); /* old ARM name */ +Xextern __declspec(__nothrow) __attribute__((const)) float _fabsf(float); +N_ARMABI_INLINE _ARMABI_PURE float fabsf(float __f) { return _fabsf(__f); } +Xstatic __inline __declspec(__nothrow) __attribute__((const)) float fabsf(float __f) { return _fabsf(__f); } +Nextern _ARMABI float sinf(float /*x*/); +Xextern __declspec(__nothrow) float sinf(float ); +Nextern _ARMABI float cosf(float /*x*/); +Xextern __declspec(__nothrow) float cosf(float ); +Nextern _ARMABI float tanf(float /*x*/); +Xextern __declspec(__nothrow) float tanf(float ); +Nextern _ARMABI float acosf(float /*x*/); +Xextern __declspec(__nothrow) float acosf(float ); +Nextern _ARMABI float asinf(float /*x*/); +Xextern __declspec(__nothrow) float asinf(float ); +Nextern _ARMABI float atanf(float /*x*/); +Xextern __declspec(__nothrow) float atanf(float ); +Nextern _ARMABI float atan2f(float /*y*/, float /*x*/); +Xextern __declspec(__nothrow) float atan2f(float , float ); +Nextern _ARMABI float sinhf(float /*x*/); +Xextern __declspec(__nothrow) float sinhf(float ); +Nextern _ARMABI float coshf(float /*x*/); +Xextern __declspec(__nothrow) float coshf(float ); +Nextern _ARMABI float tanhf(float /*x*/); +Xextern __declspec(__nothrow) float tanhf(float ); +Nextern _ARMABI float expf(float /*x*/); +Xextern __declspec(__nothrow) float expf(float ); +Nextern _ARMABI float logf(float /*x*/); +Xextern __declspec(__nothrow) float logf(float ); +Nextern _ARMABI float log10f(float /*x*/); +Xextern __declspec(__nothrow) float log10f(float ); +Nextern _ARMABI float powf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float powf(float , float ); +Nextern _ARMABI float sqrtf(float /*x*/); +Xextern __declspec(__nothrow) float sqrtf(float ); +Nextern _ARMABI float ldexpf(float /*x*/, int /*exp*/); +Xextern __declspec(__nothrow) float ldexpf(float , int ); +Nextern _ARMABI float frexpf(float /*value*/, int * /*exp*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) float frexpf(float , int * ) __attribute__((__nonnull__(2))); +Nextern _ARMABI_PURE float ceilf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float ceilf(float ); +Nextern _ARMABI_PURE float floorf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float floorf(float ); +Nextern _ARMABI float fmodf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float fmodf(float , float ); +Nextern _ARMABI float modff(float /*value*/, float * /*iptr*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) float modff(float , float * ) __attribute__((__nonnull__(2))); +N +N/* C99 long double versions of functions. */ +N/* (also need to have 'using' declarations below) */ +N#define _ARMDEFLD1(f) \ +N _ARMABI long double f##l(long double /*x*/) +X#define _ARMDEFLD1(f) _ARMABI long double f##l(long double ) +N +N#define _ARMDEFLD1P(f, T) \ +N _ARMABI long double f##l(long double /*x*/, T /*p*/) +X#define _ARMDEFLD1P(f, T) _ARMABI long double f##l(long double , T ) +N +N#define _ARMDEFLD2(f) \ +N _ARMABI long double f##l(long double /*x*/, long double /*y*/) +X#define _ARMDEFLD2(f) _ARMABI long double f##l(long double , long double ) +N +N/* +N * Long double versions of C89 functions can be defined +N * unconditionally, because C89 reserved these names in "future +N * library directions". +N */ +N_ARMDEFLD1(acos); +X__declspec(__nothrow) long double acosl(long double ); +N_ARMDEFLD1(asin); +X__declspec(__nothrow) long double asinl(long double ); +N_ARMDEFLD1(atan); +X__declspec(__nothrow) long double atanl(long double ); +N_ARMDEFLD2(atan2); +X__declspec(__nothrow) long double atan2l(long double , long double ); +N_ARMDEFLD1(ceil); +X__declspec(__nothrow) long double ceill(long double ); +N_ARMDEFLD1(cos); +X__declspec(__nothrow) long double cosl(long double ); +N_ARMDEFLD1(cosh); +X__declspec(__nothrow) long double coshl(long double ); +N_ARMDEFLD1(exp); +X__declspec(__nothrow) long double expl(long double ); +N_ARMDEFLD1(fabs); +X__declspec(__nothrow) long double fabsl(long double ); +N_ARMDEFLD1(floor); +X__declspec(__nothrow) long double floorl(long double ); +N_ARMDEFLD2(fmod); +X__declspec(__nothrow) long double fmodl(long double , long double ); +N_ARMDEFLD1P(frexp, int*) __attribute__((__nonnull__(2))); +X__declspec(__nothrow) long double frexpl(long double , int* ) __attribute__((__nonnull__(2))); +N_ARMDEFLD1P(ldexp, int); +X__declspec(__nothrow) long double ldexpl(long double , int ); +N_ARMDEFLD1(log); +X__declspec(__nothrow) long double logl(long double ); +N_ARMDEFLD1(log10); +X__declspec(__nothrow) long double log10l(long double ); +N_ARMABI long double modfl(long double /*x*/, long double * /*p*/) __attribute__((__nonnull__(2))); +X__declspec(__nothrow) long double modfl(long double , long double * ) __attribute__((__nonnull__(2))); +N_ARMDEFLD2(pow); +X__declspec(__nothrow) long double powl(long double , long double ); +N_ARMDEFLD1(sin); +X__declspec(__nothrow) long double sinl(long double ); +N_ARMDEFLD1(sinh); +X__declspec(__nothrow) long double sinhl(long double ); +N_ARMDEFLD1(sqrt); +X__declspec(__nothrow) long double sqrtl(long double ); +N_ARMDEFLD1(tan); +X__declspec(__nothrow) long double tanl(long double ); +N_ARMDEFLD1(tanh); +X__declspec(__nothrow) long double tanhl(long double ); +N +N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +X#if !0L || 1L +N +N/* +N * C99 float and long double versions of extra-C89 functions. +N */ +Nextern _ARMABI float acoshf(float /*x*/); +Xextern __declspec(__nothrow) float acoshf(float ); +N_ARMDEFLD1(acosh); +X__declspec(__nothrow) long double acoshl(long double ); +Nextern _ARMABI float asinhf(float /*x*/); +Xextern __declspec(__nothrow) float asinhf(float ); +N_ARMDEFLD1(asinh); +X__declspec(__nothrow) long double asinhl(long double ); +Nextern _ARMABI float atanhf(float /*x*/); +Xextern __declspec(__nothrow) float atanhf(float ); +N_ARMDEFLD1(atanh); +X__declspec(__nothrow) long double atanhl(long double ); +N_ARMDEFLD2(copysign); +X__declspec(__nothrow) long double copysignl(long double , long double ); +Nextern _ARMABI float cbrtf(float /*x*/); +Xextern __declspec(__nothrow) float cbrtf(float ); +N_ARMDEFLD1(cbrt); +X__declspec(__nothrow) long double cbrtl(long double ); +Nextern _ARMABI float erff(float /*x*/); +Xextern __declspec(__nothrow) float erff(float ); +N_ARMDEFLD1(erf); +X__declspec(__nothrow) long double erfl(long double ); +Nextern _ARMABI float erfcf(float /*x*/); +Xextern __declspec(__nothrow) float erfcf(float ); +N_ARMDEFLD1(erfc); +X__declspec(__nothrow) long double erfcl(long double ); +Nextern _ARMABI float expm1f(float /*x*/); +Xextern __declspec(__nothrow) float expm1f(float ); +N_ARMDEFLD1(expm1); +X__declspec(__nothrow) long double expm1l(long double ); +Nextern _ARMABI float log1pf(float /*x*/); +Xextern __declspec(__nothrow) float log1pf(float ); +N_ARMDEFLD1(log1p); +X__declspec(__nothrow) long double log1pl(long double ); +Nextern _ARMABI float hypotf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float hypotf(float , float ); +N_ARMDEFLD2(hypot); +X__declspec(__nothrow) long double hypotl(long double , long double ); +Nextern _ARMABI float lgammaf(float /*x*/); +Xextern __declspec(__nothrow) float lgammaf(float ); +N_ARMDEFLD1(lgamma); +X__declspec(__nothrow) long double lgammal(long double ); +Nextern _ARMABI float remainderf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float remainderf(float , float ); +N_ARMDEFLD2(remainder); +X__declspec(__nothrow) long double remainderl(long double , long double ); +Nextern _ARMABI float rintf(float /*x*/); +Xextern __declspec(__nothrow) float rintf(float ); +N_ARMDEFLD1(rint); +X__declspec(__nothrow) long double rintl(long double ); +N +N#endif +N +N#if (defined(__clang__) && !defined(__STRICT_ANSI)) || defined(__USE_C99_MATH) +X#if (0L && !0L) || 1L +N/* +N * Functions new in C99. +N */ +Nextern _ARMABI double exp2(double /*x*/); /* * 2.^x. */ +Xextern __declspec(__nothrow) double exp2(double ); +Nextern _ARMABI float exp2f(float /*x*/); +Xextern __declspec(__nothrow) float exp2f(float ); +N_ARMDEFLD1(exp2); +X__declspec(__nothrow) long double exp2l(long double ); +Nextern _ARMABI double fdim(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double fdim(double , double ); +Nextern _ARMABI float fdimf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float fdimf(float , float ); +N_ARMDEFLD2(fdim); +X__declspec(__nothrow) long double fdiml(long double , long double ); +N#ifdef __FP_FAST_FMA +S#define FP_FAST_FMA +N#endif +N#ifdef __FP_FAST_FMAF +S#define FP_FAST_FMAF +N#endif +N#ifdef __FP_FAST_FMAL +S#define FP_FAST_FMAL +N#endif +Nextern _ARMABI double fma(double /*x*/, double /*y*/, double /*z*/); +Xextern __declspec(__nothrow) double fma(double , double , double ); +Nextern _ARMABI float fmaf(float /*x*/, float /*y*/, float /*z*/); +Xextern __declspec(__nothrow) float fmaf(float , float , float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI long double fmal(long double __x, long double __y, long double __z) \ +N { return (long double)fma((double)__x, (double)__y, (double)__z); } +Xstatic __inline __declspec(__nothrow) long double fmal(long double __x, long double __y, long double __z) { return (long double)fma((double)__x, (double)__y, (double)__z); } +N#endif +Nextern _ARMABI_FPEXCEPT double fmax(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) __attribute__((const)) double fmax(double , double ); +Nextern _ARMABI_FPEXCEPT float fmaxf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) __attribute__((const)) float fmaxf(float , float ); +N_ARMDEFLD2(fmax); +X__declspec(__nothrow) long double fmaxl(long double , long double ); +Nextern _ARMABI_FPEXCEPT double fmin(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) __attribute__((const)) double fmin(double , double ); +Nextern _ARMABI_FPEXCEPT float fminf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) __attribute__((const)) float fminf(float , float ); +N_ARMDEFLD2(fmin); +X__declspec(__nothrow) long double fminl(long double , long double ); +Nextern _ARMABI double log2(double /*x*/); /* * log base 2 of x. */ +Xextern __declspec(__nothrow) double log2(double ); +Nextern _ARMABI float log2f(float /*x*/); +Xextern __declspec(__nothrow) float log2f(float ); +N_ARMDEFLD1(log2); +X__declspec(__nothrow) long double log2l(long double ); +Nextern _ARMABI long lrint(double /*x*/); +Xextern __declspec(__nothrow) long lrint(double ); +Nextern _ARMABI long lrintf(float /*x*/); +Xextern __declspec(__nothrow) long lrintf(float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI long lrintl(long double __x) \ +N { return lrint((double)__x); } +Xstatic __inline __declspec(__nothrow) long lrintl(long double __x) { return lrint((double)__x); } +N#endif +Nextern _ARMABI __LONGLONG llrint(double /*x*/); +Xextern __declspec(__nothrow) long long llrint(double ); +Nextern _ARMABI __LONGLONG llrintf(float /*x*/); +Xextern __declspec(__nothrow) long long llrintf(float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI __LONGLONG llrintl(long double __x) \ +N { return llrint((double)__x); } +Xstatic __inline __declspec(__nothrow) long long llrintl(long double __x) { return llrint((double)__x); } +N#endif +Nextern _ARMABI long lround(double /*x*/); +Xextern __declspec(__nothrow) long lround(double ); +Nextern _ARMABI long lroundf(float /*x*/); +Xextern __declspec(__nothrow) long lroundf(float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI long lroundl(long double __x) \ +N { return lround((double)__x); } +Xstatic __inline __declspec(__nothrow) long lroundl(long double __x) { return lround((double)__x); } +N#endif +Nextern _ARMABI __LONGLONG llround(double /*x*/); +Xextern __declspec(__nothrow) long long llround(double ); +Nextern _ARMABI __LONGLONG llroundf(float /*x*/); +Xextern __declspec(__nothrow) long long llroundf(float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI __LONGLONG llroundl(long double __x) \ +N { return llround((double)__x); } +Xstatic __inline __declspec(__nothrow) long long llroundl(long double __x) { return llround((double)__x); } +N#endif +Nextern _ARMABI_PURE double nan(const char */*tagp*/); +Xextern __declspec(__nothrow) __attribute__((const)) double nan(const char * ); +Nextern _ARMABI_PURE float nanf(const char */*tagp*/); +Xextern __declspec(__nothrow) __attribute__((const)) float nanf(const char * ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI_PURE long double nanl(const char *__t) \ +N { return (long double)nan(__t); } +Xstatic __inline __declspec(__nothrow) __attribute__((const)) long double nanl(const char *__t) { return (long double)nan(__t); } +N#endif +N#if defined(_WANT_SNAN) && defined(__SUPPORT_SNAN__) +X#if 0L && 0L +Sextern _ARMABI_PURE double nans(const char */*tagp*/); +Sextern _ARMABI_PURE float nansf(const char */*tagp*/); +S#ifdef __HAVE_LONGDOUBLE +S_ARMABI_INLINE _ARMABI_FPEXCEPT long double nansl(const char *__t) \ +S { return (long double)nans(__t); } +X_ARMABI_INLINE _ARMABI_FPEXCEPT long double nansl(const char *__t) { return (long double)nans(__t); } +S#endif +N#endif +Nextern _ARMABI_FPEXCEPT double nearbyint(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double nearbyint(double ); +Nextern _ARMABI_FPEXCEPT float nearbyintf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float nearbyintf(float ); +N_ARMDEFLD1(nearbyint); +X__declspec(__nothrow) long double nearbyintl(long double ); +Nextern double remquo(double /*x*/, double /*y*/, int */*quo*/); +Nextern float remquof(float /*x*/, float /*y*/, int */*quo*/); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE long double remquol(long double __x, long double __y, int *__q) \ +N { return (long double)remquo((double)__x, (double)__y, __q); } +Xstatic __inline long double remquol(long double __x, long double __y, int *__q) { return (long double)remquo((double)__x, (double)__y, __q); } +N#endif +Nextern _ARMABI_FPEXCEPT double round(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double round(double ); +Nextern _ARMABI_FPEXCEPT float roundf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float roundf(float ); +N_ARMDEFLD1(round); +X__declspec(__nothrow) long double roundl(long double ); +Nextern _ARMABI double tgamma(double /*x*/); /* * The gamma function of x. */ +Xextern __declspec(__nothrow) double tgamma(double ); +Nextern _ARMABI float tgammaf(float /*x*/); +Xextern __declspec(__nothrow) float tgammaf(float ); +N_ARMDEFLD1(tgamma); +X__declspec(__nothrow) long double tgammal(long double ); +Nextern _ARMABI_FPEXCEPT double trunc(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double trunc(double ); +Nextern _ARMABI_FPEXCEPT float truncf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float truncf(float ); +N_ARMDEFLD1(trunc); +X__declspec(__nothrow) long double truncl(long double ); +N#endif +N +N#undef _ARMDEFLD1 +N#undef _ARMDEFLD1P +N#undef _ARMDEFLD2 +N +N#if defined(__cplusplus) && ((!defined(__STRICT_ANSI__) || defined(__USE_C99_MATH)) || defined(__ARMCOMPILER_LIBCXX)) +X#if 0L && ((!0L || 1L) || 0L) +S extern "C++" { +S inline int (fpclassify)(double __x) { return fpclassify(__x); } +S inline bool (isfinite)(double __x) { return isfinite(__x); } +S inline bool (isgreater)(double __x, double __y) { return isgreater(__x, __y); } +S inline bool (isgreaterequal)(double __x, double __y) { return isgreaterequal(__x, __y); } +S inline bool (isinf)(double __x) { return isinf(__x); } +S inline bool (isless)(double __x, double __y) { return isless(__x, __y); } +S inline bool (islessequal)(double __x, double __y) { return islessequal(__x, __y); } +S inline bool (islessgreater)(double __x, double __y) { return islessgreater(__x, __y); } +S inline bool (isnan)(double __x) { return isnan(__x); } +S inline bool (isnormal)(double __x) { return isnormal(__x); } +S inline bool (isunordered)(double __x, double __y) { return isunordered(__x, __y); } +S +S } +N#endif +N +N#if defined(__cplusplus) && !defined(__ARMCOMPILER_LIBCXX) +X#if 0L && !0L +S extern "C++" { +S inline float abs(float __x) { return fabsf(__x); } +S inline float acos(float __x) { return acosf(__x); } +S inline float asin(float __x) { return asinf(__x); } +S inline float atan(float __x) { return atanf(__x); } +S inline float atan2(float __y, float __x) { return atan2f(__y,__x); } +S inline float ceil(float __x) { return ceilf(__x); } +S inline float cos(float __x) { return cosf(__x); } +S inline float cosh(float __x) { return coshf(__x); } +S inline float exp(float __x) { return expf(__x); } +S inline float fabs(float __x) { return fabsf(__x); } +S inline float floor(float __x) { return floorf(__x); } +S inline float fmod(float __x, float __y) { return fmodf(__x, __y); } +S float frexp(float __x, int* __exp) __attribute__((__nonnull__(2))); +S inline float frexp(float __x, int* __exp) { return frexpf(__x, __exp); } +S inline float ldexp(float __x, int __exp) { return ldexpf(__x, __exp);} +S inline float log(float __x) { return logf(__x); } +S inline float log10(float __x) { return log10f(__x); } +S float modf(float __x, float* __iptr) __attribute__((__nonnull__(2))); +S inline float modf(float __x, float* __iptr) { return modff(__x, __iptr); } +S inline float pow(float __x, float __y) { return powf(__x,__y); } +S inline float pow(float __x, int __y) { return powf(__x, (float)__y); } +S inline float sin(float __x) { return sinf(__x); } +S inline float sinh(float __x) { return sinhf(__x); } +S inline float sqrt(float __x) { return sqrtf(__x); } +S inline float _sqrt(float __x) { return _sqrtf(__x); } +S inline float tan(float __x) { return tanf(__x); } +S inline float tanh(float __x) { return tanhf(__x); } +S +S inline double abs(double __x) { return fabs(__x); } +S inline double pow(double __x, int __y) +S { return pow(__x, (double) __y); } +S +S#ifdef __HAVE_LONGDOUBLE +S inline long double abs(long double __x) +S { return (long double)fabsl(__x); } +S inline long double acos(long double __x) +S { return (long double)acosl(__x); } +S inline long double asin(long double __x) +S { return (long double)asinl(__x); } +S inline long double atan(long double __x) +S { return (long double)atanl(__x); } +S inline long double atan2(long double __y, long double __x) +S { return (long double)atan2l(__y, __x); } +S inline long double ceil(long double __x) +S { return (long double)ceill( __x); } +S inline long double cos(long double __x) +S { return (long double)cosl(__x); } +S inline long double cosh(long double __x) +S { return (long double)coshl(__x); } +S inline long double exp(long double __x) +S { return (long double)expl(__x); } +S inline long double fabs(long double __x) +S { return (long double)fabsl(__x); } +S inline long double floor(long double __x) +S { return (long double)floorl(__x); } +S inline long double fmod(long double __x, long double __y) +S { return (long double)fmodl(__x, __y); } +S long double frexp(long double __x, int* __p) __attribute__((__nonnull__(2))); +S inline long double frexp(long double __x, int* __p) +S { return (long double)frexpl(__x, __p); } +S inline long double ldexp(long double __x, int __exp) +S { return (long double)ldexpl(__x, __exp); } +S inline long double log(long double __x) +S { return (long double)logl(__x); } +S inline long double log10(long double __x) +S { return (long double)log10l(__x); } +S long double modf(long double __x, long double* __p) __attribute__((__nonnull__(2))); +S inline long double modf(long double __x, long double* __p) +S { return (long double)modfl(__x, __p); } +S inline long double pow(long double __x, long double __y) +S { return (long double)powl(__x, __y); } +S inline long double pow(long double __x, int __y) +S { return (long double)powl(__x, __y); } +S inline long double sin(long double __x) +S { return (long double)sinl(__x); } +S inline long double sinh(long double __x) +S { return (long double)sinhl(__x); } +S inline long double sqrt(long double __x) +S { return (long double)sqrtl(__x); } +S inline long double _sqrt(long double __x) +S { return (long double)_sqrt((double) __x); } +S inline long double tan(long double __x) +S { return (long double)tanl(__x); } +S inline long double tanh(long double __x) +S { return (long double)tanhl(__x); } +S#endif +S +S#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +S inline float acosh(float __x) { return acoshf(__x); } +S inline float asinh(float __x) { return asinhf(__x); } +S inline float atanh(float __x) { return atanhf(__x); } +S inline float cbrt(float __x) { return cbrtf(__x); } +S inline float erf(float __x) { return erff(__x); } +S inline float erfc(float __x) { return erfcf(__x); } +S inline float expm1(float __x) { return expm1f(__x); } +S inline float log1p(float __x) { return log1pf(__x); } +S inline float hypot(float __x, float __y) { return hypotf(__x, __y); } +S inline float lgamma(float __x) { return lgammaf(__x); } +S inline float remainder(float __x, float __y) { return remainderf(__x, __y); } +S inline float rint(float __x) { return rintf(__x); } +S#endif +S +S#ifdef __USE_C99_MATH +S inline float exp2(float __x) { return exp2f(__x); } +S inline float fdim(float __x, float __y) { return fdimf(__x, __y); } +S inline float fma(float __x, float __y, float __z) { return fmaf(__x, __y, __z); } +S inline float fmax(float __x, float __y) { return fmaxf(__x, __y); } +S inline float fmin(float __x, float __y) { return fminf(__x, __y); } +S inline float log2(float __x) { return log2f(__x); } +S inline _ARMABI long lrint(float __x) { return lrintf(__x); } +S inline _ARMABI __LONGLONG llrint(float __x) { return llrintf(__x); } +S inline _ARMABI long lround(float __x) { return lroundf(__x); } +S inline _ARMABI __LONGLONG llround(float __x) { return llroundf(__x); } +S inline _ARMABI_FPEXCEPT float nearbyint(float __x) { return nearbyintf(__x); } +S inline float remquo(float __x, float __y, int *__q) { return remquof(__x, __y, __q); } +S inline _ARMABI_FPEXCEPT float round(float __x) { return roundf(__x); } +S inline float tgamma(float __x) { return tgammaf(__x); } +S inline _ARMABI_FPEXCEPT float trunc(float __x) { return truncf(__x); } +S +S inline int (fpclassify)(float __x) { return fpclassify(__x); } +S inline bool (isfinite)(float __x) { return isfinite(__x); } +S inline bool (isgreater)(float __x, float __y) { return isgreater(__x, __y); } +S inline bool (isgreaterequal)(float __x, float __y) { return isgreaterequal(__x, __y); } +S inline bool (isinf)(float __x) { return isinf(__x); } +S inline bool (isless)(float __x, float __y) { return isless(__x, __y); } +S inline bool (islessequal)(float __x, float __y) { return islessequal(__x, __y); } +S inline bool (islessgreater)(float __x, float __y) { return islessgreater(__x, __y); } +S inline bool (isnan)(float __x) { return isnan(__x); } +S inline bool (isnormal)(float __x) { return isnormal(__x); } +S inline bool (isunordered)(float __x, float __y) { return isunordered(__x, __y); } +S +S#ifdef __HAVE_LONGDOUBLE +S inline long double acosh(long double __x) { return acoshl(__x); } +S inline long double asinh(long double __x) { return asinhl(__x); } +S inline long double atanh(long double __x) { return atanhl(__x); } +S inline long double cbrt(long double __x) { return cbrtl(__x); } +S inline long double erf(long double __x) { return erfl(__x); } +S inline long double erfc(long double __x) { return erfcl(__x); } +S inline long double expm1(long double __x) { return expm1l(__x); } +S inline long double log1p(long double __x) { return log1pl(__x); } +S inline long double hypot(long double __x, long double __y) { return hypotl(__x, __y); } +S inline long double lgamma(long double __x) { return lgammal(__x); } +S inline long double remainder(long double __x, long double __y) { return remainderl(__x, __y); } +S inline long double rint(long double __x) { return rintl(__x); } +S inline long double exp2(long double __x) { return exp2l(__x); } +S inline long double fdim(long double __x, long double __y) { return fdiml(__x, __y); } +S inline long double fma(long double __x, long double __y, long double __z) { return fmal(__x, __y, __z); } +S inline long double fmax(long double __x, long double __y) { return fmaxl(__x, __y); } +S inline long double fmin(long double __x, long double __y) { return fminl(__x, __y); } +S inline long double log2(long double __x) { return log2l(__x); } +S inline _ARMABI long lrint(long double __x) { return lrintl(__x); } +S inline _ARMABI __LONGLONG llrint(long double __x) { return llrintl(__x); } +S inline _ARMABI long lround(long double __x) { return lroundl(__x); } +S inline _ARMABI __LONGLONG llround(long double __x) { return llroundl(__x); } +S inline _ARMABI_FPEXCEPT long double nearbyint(long double __x) { return nearbyintl(__x); } +S inline long double remquo(long double __x, long double __y, int *__q) { return remquol(__x, __y, __q); } +S inline _ARMABI_FPEXCEPT long double round(long double __x) { return roundl(__x); } +S inline long double tgamma(long double __x) { return tgammal(__x); } +S inline _ARMABI_FPEXCEPT long double trunc(long double __x) { return truncl(__x); } +S inline int (fpclassify)(long double __x) { return fpclassify(__x); } +S inline bool (isfinite)(long double __x) { return isfinite(__x); } +S inline bool (isgreater)(long double __x, long double __y) { return isgreater(__x, __y); } +S inline bool (isgreaterequal)(long double __x, long double __y) { return isgreaterequal(__x, __y); } +S inline bool (isinf)(long double __x) { return isinf(__x); } +S inline bool (isless)(long double __x, long double __y) { return isless(__x, __y); } +S inline bool (islessequal)(long double __x, long double __y) { return islessequal(__x, __y); } +S inline bool (islessgreater)(long double __x, long double __y) { return islessgreater(__x, __y); } +S inline bool (isnan)(long double __x) { return isnan(__x); } +S inline bool (isnormal)(long double __x) { return isnormal(__x); } +S inline bool (isunordered)(long double __x, long double __y) { return isunordered(__x, __y); } +S#endif +S +S#undef fpclassify +S#undef isfinite +S#undef isgreater +S#undef isgreaterequal +S#undef isinf +S#undef isless +S#undef islessequal +S#undef islessgreater +S#undef isnan +S#undef isnormal +S#undef isunordered +S +S#endif +S +S } +N#endif +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif +N #endif /* __MATH_DECLS */ +N +N #if _AEABI_PORTABILITY_LEVEL != 0 && !defined _AEABI_PORTABLE +X #if _AEABI_PORTABILITY_LEVEL != 0 && !0L +S #define _AEABI_PORTABLE +N #endif +N +N #if defined(__cplusplus) && !defined(__MATH_NO_EXPORTS) +X #if 0L && !0L +S using ::std::__use_accurate_range_reduction; +S #ifndef __ARMCOMPILER_LIBCXX +S using ::std::abs; +S #endif +S using ::std::acos; +S using ::std::asin; +S using ::std::atan2; +S using ::std::atan; +S using ::std::ceil; +S using ::std::cos; +S using ::std::cosh; +S using ::std::exp; +S using ::std::fabs; +S using ::std::floor; +S using ::std::fmod; +S using ::std::frexp; +S using ::std::ldexp; +S using ::std::log10; +S using ::std::log; +S using ::std::modf; +S using ::std::pow; +S using ::std::sin; +S using ::std::sinh; +S using ::std::sqrt; +S using ::std::_sqrt; +S using ::std::_sqrtf; +S using ::std::tan; +S using ::std::tanh; +S using ::std::_fabsf; +S /* C99 float and long double versions in already-C89-reserved namespace */ +S using ::std::acosf; +S using ::std::acosl; +S using ::std::asinf; +S using ::std::asinl; +S using ::std::atan2f; +S using ::std::atan2l; +S using ::std::atanf; +S using ::std::atanl; +S using ::std::ceilf; +S using ::std::ceill; +S using ::std::cosf; +S using ::std::coshf; +S using ::std::coshl; +S using ::std::cosl; +S using ::std::expf; +S using ::std::expl; +S using ::std::fabsf; +S using ::std::fabsl; +S using ::std::floorf; +S using ::std::floorl; +S using ::std::fmodf; +S using ::std::fmodl; +S using ::std::frexpf; +S using ::std::frexpl; +S using ::std::ldexpf; +S using ::std::ldexpl; +S using ::std::log10f; +S using ::std::log10l; +S using ::std::logf; +S using ::std::logl; +S using ::std::modff; +S using ::std::modfl; +S using ::std::powf; +S using ::std::powl; +S using ::std::sinf; +S using ::std::sinhf; +S using ::std::sinhl; +S using ::std::sinl; +S using ::std::sqrtf; +S using ::std::sqrtl; +S using ::std::tanf; +S using ::std::tanhf; +S using ::std::tanhl; +S using ::std::tanl; +S #if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +S /* C99 additions which for historical reasons appear in non-strict mode */ +S using ::std::acosh; +S using ::std::asinh; +S using ::std::atanh; +S using ::std::cbrt; +S using ::std::copysign; +S using ::std::copysignf; +S using ::std::erf; +S using ::std::erfc; +S using ::std::expm1; +S using ::std::hypot; +S using ::std::ilogb; +S using ::std::ilogbf; +S using ::std::ilogbl; +S using ::std::lgamma; +S using ::std::log1p; +S using ::std::logb; +S using ::std::logbf; +S using ::std::logbl; +S using ::std::nextafter; +S using ::std::nextafterf; +S using ::std::nextafterl; +S using ::std::nexttoward; +S using ::std::nexttowardf; +S using ::std::nexttowardl; +S using ::std::remainder; +S using ::std::rint; +S using ::std::scalbln; +S using ::std::scalblnf; +S using ::std::scalblnl; +S using ::std::scalbn; +S using ::std::scalbnf; +S using ::std::scalbnl; +S using ::std::math_errhandling; +S using ::std::acoshf; +S using ::std::acoshl; +S using ::std::asinhf; +S using ::std::asinhl; +S using ::std::atanhf; +S using ::std::atanhl; +S using ::std::copysignl; +S using ::std::cbrtf; +S using ::std::cbrtl; +S using ::std::erff; +S using ::std::erfl; +S using ::std::erfcf; +S using ::std::erfcl; +S using ::std::expm1f; +S using ::std::expm1l; +S using ::std::log1pf; +S using ::std::log1pl; +S using ::std::hypotf; +S using ::std::hypotl; +S using ::std::lgammaf; +S using ::std::lgammal; +S using ::std::remainderf; +S using ::std::remainderl; +S using ::std::rintf; +S using ::std::rintl; +S /* New in C99. */ +S using ::std::float_t; +S using ::std::double_t; +S #endif +S #if (defined(__clang__) && !defined(__STRICT_ANSI)) || defined(__USE_C99_MATH) +S /* Functions new in C99. */ +S using ::std::exp2; +S using ::std::exp2f; +S using ::std::exp2l; +S using ::std::fdim; +S using ::std::fdimf; +S using ::std::fdiml; +S using ::std::fma; +S using ::std::fmaf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::fmal; +S#endif +S using ::std::fmax; +S using ::std::fmaxf; +S using ::std::fmaxl; +S using ::std::fmin; +S using ::std::fminf; +S using ::std::fminl; +S using ::std::log2; +S using ::std::log2f; +S using ::std::log2l; +S using ::std::lrint; +S using ::std::lrintf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::lrintl; +S#endif +S using ::std::llrint; +S using ::std::llrintf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::llrintl; +S#endif +S using ::std::lround; +S using ::std::lroundf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::lroundl; +S#endif +S using ::std::llround; +S using ::std::llroundf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::llroundl; +S#endif +S using ::std::nan; +S using ::std::nanf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::nanl; +S#endif +S using ::std::nearbyint; +S using ::std::nearbyintf; +S using ::std::nearbyintl; +S using ::std::remquo; +S using ::std::remquof; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::remquol; +S#endif +S using ::std::round; +S using ::std::roundf; +S using ::std::roundl; +S using ::std::tgamma; +S using ::std::tgammaf; +S using ::std::tgammal; +S using ::std::trunc; +S using ::std::truncf; +S using ::std::truncl; +S #endif +S +S #if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +S using ::std::fpclassify; +S using ::std::isfinite; +S using ::std::isgreater; +S using ::std::isgreaterequal; +S using ::std::isinf; +S using ::std::isless; +S using ::std::islessequal; +S using ::std::islessgreater; +S using ::std::isnan; +S using ::std::isnormal; +S using ::std::isunordered; +S #endif +N #endif +N +N#undef __LONGLONG +N +N#endif /* __math_h */ +N +N/* end of math.h */ +L 19 "..\..\src\common\tau_common.h" 2 +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N/** +N * \name 通用常量定义 +N * @{ +N */ +N//#define ENABLE 1 +N//#define DISABLE 0 +N +N#define ON 1 +N#define OFF 0 +N +N#define NONE 0 +N#define EOS '\0' +N +N/* +N#ifndef TRUE +N#define TRUE 1 +N#endif +N +N#ifndef FALSE +N#define FALSE 0 +N#endif +N*/ +N +N#ifndef __cplusplus +N#define true 1 +N#define false 0 +N#define bool _Bool +N#endif /* ifndef __cplusplus */ +N +N#ifndef NULL +S#define NULL ((void *)0) +N#endif +N +N#define TAU_LITTLE_ENDIAN 1234 /**< \brief 小端模式 */ +N#define TAU_BIG_ENDIAN 3412 /**< \brief 大端模式 */ +N +N/** @} */ +N +N/******************************************************************************/ +N +N/** +N * \name 常用宏定义 +N * @{ +N */ +N +N#ifdef __cplusplus +S#define __I volatile /*!< Defines 'read only' permissions */ +N#else +N#define __I volatile const /*!< Defines 'read only' permissions */ +N#endif +N#define __O volatile /*!< Defines 'write only' permissions */ +N#define __IO volatile /*!< Defines 'read / write' permissions */ +N +N#define TAU_INLINE inline +N#define TAU_STATIC_INLINE static inline +N#define TAU_STATIC static +N#define TAU_CONST const +N#define TAU_EXTERN extern +N +N#define MIN(x, y) (((x) < (y)) ? (x) : (y)) +N#define MAX(x, y) (((x) > (y)) ? (x) : (y)) +N +N/** +N * \brief 求结构体成员的偏移 +N * \attention 不同平台上，由于成员大小和内存对齐等原因， +N * 同一结构体成员的偏移可能是不一样的 +N * +N * \par 示例 +N * \code +N * struct my_struct { +N * int m1; +N * char m2; +N * }; +N * int offset_m2; +N * +N * offset_m2 = TAU_OFFSET(struct my_struct, m2); +N * \endcode +N */ +N#define TAU_OFFSET(structure, member) ((uint32_t)(&(((structure *)0)->member))) +N +N/** @} */ +N +N/** +N * \brief 通过结构体成员指针获取包含该结构体成员的结构体 +N * +N * \param ptr 指向结构体成员的指针 +N * \param type 结构体类型 +N * \param member 结构体中该成员的名称 +N * +N * \par 示例 +N * \code +N * struct my_struct = { +N * int m1; +N * char m2; +N * }; +N * struct my_struct my_st; +N * char *p_m2 = &my_st.m2; +N * struct my_struct *p_st = TAU_CONTAINER_OF(p_m2, struct my_struct, m2); +N * \endcode +N */ +N#define TAU_CONTAINER_OF(ptr, type, member) \ +N ((type *)((char *)(ptr)-TAU_OFFSET(type, member))) +X#define TAU_CONTAINER_OF(ptr, type, member) ((type *)((char *)(ptr)-TAU_OFFSET(type, member))) +N +N/** +N * \brief 计算结构体成员的大小 +N * +N * \code +N * struct a = { +N * uint32_t m1; +N * uint32_t m2; +N * }; +N * int size_m2; +N * +N * size_m2 = TAU_MEMBER_SIZE(a, m2); //size_m2 = 4 +N * \endcode +N */ +N#define TAU_MEMBER_SIZE(structure, member) (sizeof(((structure *)0)->member)) +N +N/** +N * \brief 计算数组元素个数 +N * +N * \code +N * int a[] = {0, 1, 2, 3}; +N * int element_a = TAU_NELEMENTS(a); // element_a = 4 +N * \endcode +N */ +N#define TAU_NELEMENTS(array) (sizeof(array) / sizeof((array)[0])) +N +N/** +N * \brief 向上舍入 +N * +N * \param x 被运算的数 +N * \param align 对齐因素 +N * +N * \code +N * int size = TAU_ROUND_UP(15, 4); // size = 16 +N * \endcode +N */ +N#define TAU_ROUND_UP(x, align) (((int)(x)/(align))*(align) + (((int)(x)%(align)) ? (align) : 0)) +N +N/** +N * \brief 向下舍入 +N * +N * \param x 被运算的数 +N * \param align 对齐因素 +N * +N * \code +N * int size = TAU_ROUND_DOWN(15, 4); // size = 12 +N * \endcode +N */ +N#define TAU_ROUND_DOWN(x, align) (((int)(x)/(align))*(align)) +N +N/** \brief 倍数向上舍入 */ +N#define TAU_DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d)) +N +N/** +N * \brief 测试是否对齐 +N * +N * \param x 被运算的数 +N * \param align 对齐因素，必须为2的乘方 +N * +N * \code +N * if (TAU_ALIGNED(x, 4) { +N * ; // x对齐 +N * } else { +N * ; // x不对齐 +N * } +N * \endcode +N */ +N#define TAU_ALIGNED(x, align) (((int)(x) & (align - 1)) == 0) +N +N/** \brief 将1字节BCD数据转换为16进制数据 */ +N#define TAU_BCD_TO_HEX(val) (((val)&0x0f) + ((val) >> 4) * 10) +N +N/** \brief 将1字节16进制数据转换为BCD数据 */ +N#define TAU_HEX_TO_BCD(val) ((((val) / 10) << 4) + (val) % 10) +N +N/** +N * \brief 向上取整 +N */ +N#define TAU_CEIL(val) ceil(val) +N +N +N/*! @brief Construct the version number for drivers. */ +N#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +N +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/*!< @brief 用于返回状态和错误 */ +Ntypedef uint32_t status_t; +N +N/* \brief 通用回调函数指针定义 */ +Ntypedef void (*fcb_type)(void *data); +N +Ntypedef void (*uart_trans_cb)(status_t status, void *user_data); +N +Ntypedef void (*flash_trans_cb)(status_t status, void *user_data); +N#endif /* __TAU_COMMON_H */ +L 16 "..\..\src\sdk\include\hal_system.h" 2 +N#include "hal_gpio.h" +L 1 "..\..\src\sdk\include\hal_gpio.h" 1 +N/******************************************************************************* +N* +N* +N* File: hal_gpio.h +N* Description： gpio HAL层头文件 +N* Version： V0.1 +N* Date： 2023-07-27 +N* Author： kevin +N *******************************************************************************/ +N#ifndef __HAL_GPIO_H__ +N#define __HAL_GPIO_H__ +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_device_datatype.h" +L 1 "..\..\src\common\tau_device_datatype.h" 1 +N/******************************************************************************* +N * +N * +N * File: tau_device_datatype.h +N * Description device datatype +N * Version V0.1 +N * Date 2020-12-04 +N * Author kevin +N *******************************************************************************/ +N +N#ifndef _TAU_DEVICE_DATATYPE_H_ +N#define _TAU_DEVICE_DATATYPE_H_ +N +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N +N#include "stdint.h" +N#include "tau_common.h" +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/*! @brief 计算组状态码 */ +N#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/*! @brief 分组状态值 */ +Nenum _status_groups +N{ +N STATUS_GROUP_GENERIC = 0, +N STATUS_GROUP_I2C = 1, +N STATUS_GROUP_UART = 2, +N STATUS_GROUP_SPI = 3, +N STATUS_GROUP_TIMER = 4, +N}; +N +N/*! @brief 常用状态码 */ +Nenum _generic_status +N{ +N STATUS_SUCCESS = MAKE_STATUS(STATUS_GROUP_GENERIC, 0), +X STATUS_SUCCESS = ((((STATUS_GROUP_GENERIC)*100) + (0))), +N STATUS_FAIL = MAKE_STATUS(STATUS_GROUP_GENERIC, 1), +X STATUS_FAIL = ((((STATUS_GROUP_GENERIC)*100) + (1))), +N STATUS_READ_ONLY = MAKE_STATUS(STATUS_GROUP_GENERIC, 2), +X STATUS_READ_ONLY = ((((STATUS_GROUP_GENERIC)*100) + (2))), +N STATUS_OUT_OF_RANGE = MAKE_STATUS(STATUS_GROUP_GENERIC, 3), +X STATUS_OUT_OF_RANGE = ((((STATUS_GROUP_GENERIC)*100) + (3))), +N STATUS_INVALID_ARGUMENT = MAKE_STATUS(STATUS_GROUP_GENERIC, 4), +X STATUS_INVALID_ARGUMENT = ((((STATUS_GROUP_GENERIC)*100) + (4))), +N STATUS_TIME_OUT = MAKE_STATUS(STATUS_GROUP_GENERIC, 5), +X STATUS_TIME_OUT = ((((STATUS_GROUP_GENERIC)*100) + (5))), +N STATUS_NO_TRANSFER_IN_PROGRESS = MAKE_STATUS(STATUS_GROUP_GENERIC, 6), +X STATUS_NO_TRANSFER_IN_PROGRESS = ((((STATUS_GROUP_GENERIC)*100) + (6))), +N}; +N +N/** +N* @brief UART状态枚举定义 +N* +N*/ +Ntypedef enum +N{ +N STATUS_UART_TX_BUSY = MAKE_STATUS(STATUS_GROUP_UART, 0), /*!< Transmitter is busy. */ +X STATUS_UART_TX_BUSY = ((((STATUS_GROUP_UART)*100) + (0))), +N STATUS_UART_RX_BUSY = MAKE_STATUS(STATUS_GROUP_UART, 1), /*!< Receiver is busy. */ +X STATUS_UART_RX_BUSY = ((((STATUS_GROUP_UART)*100) + (1))), +N STATUS_UART_TX_IDLE = MAKE_STATUS(STATUS_GROUP_UART, 2), /*!< USART transmitter is idle. */ +X STATUS_UART_TX_IDLE = ((((STATUS_GROUP_UART)*100) + (2))), +N STATUS_UART_RX_IDLE = MAKE_STATUS(STATUS_GROUP_UART, 3), /*!< USART receiver is idle. */ +X STATUS_UART_RX_IDLE = ((((STATUS_GROUP_UART)*100) + (3))), +N STATUS_UART_TX_ERR = MAKE_STATUS(STATUS_GROUP_UART, 7), /*!< Error happens on txFIFO. */ +X STATUS_UART_TX_ERR = ((((STATUS_GROUP_UART)*100) + (7))), +N STATUS_UART_RX_ERR = MAKE_STATUS(STATUS_GROUP_UART, 9), /*!< Error happens on rxFIFO. */ +X STATUS_UART_RX_ERR = ((((STATUS_GROUP_UART)*100) + (9))), +N STATUS_UART_RX_RING_BUFF_OVERRUN = MAKE_STATUS(STATUS_GROUP_UART, 8), /*!< Error happens on rx ring buffer */ +X STATUS_UART_RX_RING_BUFF_OVERRUN = ((((STATUS_GROUP_UART)*100) + (8))), +N STATUS_UART_NOISE_ERR = MAKE_STATUS(STATUS_GROUP_UART, 10), /*!< USART noise error. */ +X STATUS_UART_NOISE_ERR = ((((STATUS_GROUP_UART)*100) + (10))), +N STATUS_UART_FRAMING_ERR = MAKE_STATUS(STATUS_GROUP_UART, 11), /*!< USART framing error. */ +X STATUS_UART_FRAMING_ERR = ((((STATUS_GROUP_UART)*100) + (11))), +N STATUS_UART_PARITY_ERR = MAKE_STATUS(STATUS_GROUP_UART, 12), /*!< USART parity error. */ +X STATUS_UART_PARITY_ERR = ((((STATUS_GROUP_UART)*100) + (12))), +N STATUS_UART_BAUDRATE_NOT_SPT = MAKE_STATUS(STATUS_GROUP_UART, 13), /*!< Baudrate is not support in current clock source */ +X STATUS_UART_BAUDRATE_NOT_SPT = ((((STATUS_GROUP_UART)*100) + (13))), +N} uart_status_e; +N +N/*! +N * @brief timer状态 +N */ +Ntypedef enum +N{ +N STATUS_TIMER_IDLE = MAKE_STATUS(STATUS_GROUP_TIMER, 0), /*!< 空闲 */ +X STATUS_TIMER_IDLE = ((((STATUS_GROUP_TIMER)*100) + (0))), +N STATUS_TIMER_RUNNING = MAKE_STATUS(STATUS_GROUP_TIMER, 1), /*!< 运行中 */ +X STATUS_TIMER_RUNNING = ((((STATUS_GROUP_TIMER)*100) + (1))), +N STATUS_TIMER_TIMEOUT = MAKE_STATUS(STATUS_GROUP_TIMER, 2), /*!< 超时 */ +X STATUS_TIMER_TIMEOUT = ((((STATUS_GROUP_TIMER)*100) + (2))), +N} timer_status_e; +N +N/*! +N * @brief system触发事件(中断/复位)模式 +N */ +Ntypedef enum +N{ +N DETECT_HIGH_LVL = 0, +N DETECT_LOW_LVL, +N DETECT_RISING_EDGE, +N DETECT_FALLING_EDGE, +N DETECT_DOUBLE_EDGE +N} sys_cfg_trigger_e; +N +N/** +N* @brief GPIO interrupt type +N*/ +Ntypedef enum +N{ +N TIMER_NUM0 = 0, +N TIMER_NUM1, +N TIMER_NUM2, +N TIMER_NUM3, +N TIMER_NUM_MAX +N} timer_num_e; +N +N/** +N* @brief GPIO interrupt type +N*/ +Ntypedef enum +N{ +N GPIO_INT_EXTI_INT0 = 0, +N GPIO_INT_EXTI_INT1, +N GPIO_INT_EXTI_INT2, +N GPIO_INT_EXTI_INT3, +N GPIO_INT_EXTI_INT4, +N GPIO_INT_EXTI_INT5, +N GPIO_INT_EXTI_INT6, +N GPIO_INT_EXTI_INT7, +N GPIO_INT_MAX +N} gpio_int_e; +N +N/*! @brief PWMI中断类型 */ +Ntypedef enum _pwm_int_type +N{ +N PWM_INT_HIGH_OVERFLOW = 0, +N PWM_INT_LOW_OVERFLOW, +N PWM_INT_TOTAL_OVERFLOW, +N PWM_INT_HIGH_DONE, +N PWM_INT_LOW_DONE, +N PWM_INT_TOTAL_DONE, +N PWM_INT_MAX +N} pwm_int_type_e; +N +N/** +N* @brief I2C chose +N*/ +Ntypedef enum +N{ +N I2C_SELECT_0 = 0, //常用slave +N I2C_SELECT_1, //常用master +N} i2c_select_e; +N +N/*! +N * @brief 传输速度 +N * @note +N */ +Ntypedef enum _i2c_rate +N{ +N I2C_RATE_STANDARD = 1, //100kHz +N I2C_RATE_FAST, //400kHz +N I2C_RATE_HIGH, //1MHz +N} i2c_rate_e; +N +N/*! +N * @brief I2C Index +N * @note +N */ +Ntypedef enum +N{ +N I2C_INDEX_0, +N I2C_INDEX_1, +N I2C_INDEX_2, +N I2C_INDEX_MAX +N} i2c_index_e; +N +N/*! +N * @brief DMA channel type +N * @note +N */ +Ntypedef enum +N{ +N AHB_DMA_CH0, +N AHB_DMA_CH1, +N AHB_DMA_CH2, +N AHB_DMA_CH3, +N AHB_DMA_CH4, +N AHB_DMA_CH5, +N AHB_DMA_CH6, +N AHB_DMA_CH7, +N AHB_DMA_CH_NUM +N} dma_channel_type_e; +N +N/*! @brief Type used for all status and error return values. */ +N +Ntypedef enum +N{ +N DISABLE = 0, +N ENABLE = !DISABLE +N} function_state_e; +N +N/** +N* @brief The reversal types of the bit order of the input/output data +N*/ +Ntypedef enum +N{ +N CRC_REV_NO_TRANSPOSE = 0, /*!< No transposition */ +N CRC_REV_ONLY_BITS_TRANSPOSE, /*!< Bits in bytes are transposed; bytes are not transposed */ +N CRC_REV_BOTH_TRANSPOSE, /*!< Both bits in bytes and bytes are transposed */ +N CRC_REV_ONLY_BYTES_TRANSPOSE, /*!< Only bytes are transposed; no bits in a byte are transposed */ +N} crc_reversal_type_e; +N +N/** +N* @brief Complement Read Of CRC Data Register +N*/ +Ntypedef enum +N{ +N CRC_FXOR_DISABLE = 0, /*!< No XOR on reading */ +N CRC_FXOR_ENABLE, /*!< Invert or complement the read value of the CRC Data register */ +N} crc_fxor_function_e; +N +N/** +N* @brief width of CRC protocol (polynomial) +N*/ +Ntypedef enum +N{ +N CRC_16_BIT_PROTOCOL = 0, /*!< 0: 16-bit CRC protocol */ +N CRC_32_BIT_PROTOCOL, /*!< 1: 32-bit CRC protocol */ +N} crc_protocol_type_e; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N#endif +N +L 17 "..\..\src\sdk\include\hal_gpio.h" 2 +N#include "tau_common.h" +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N/** +N* @brief GPIO pin +N*/ +Ntypedef enum +N{ +N /*以GPIO命名PIN*/ +N IO_PAD_GPIO0 = 0, +N IO_PAD_GPIO1, +N IO_PAD_GPIO2, +N IO_PAD_GPIO3, +N IO_PAD_GPIO4, +N IO_PAD_GPIO5, +N IO_PAD_GPIO6, +N IO_PAD_GPIO7, +N IO_PAD_GPIO8, +N IO_PAD_GPIO9, +N IO_PAD_GPIO10, +N IO_PAD_GPIO11, +N IO_PAD_GPIO12, +N IO_PAD_GPIO13, +N IO_PAD_GPIO14, +N IO_PAD_GPIO15, +N IO_PAD_GPIO16, +N IO_PAD_GPIO17, +N IO_PAD_GPIO18, +N IO_PAD_GPIO19, +N IO_PAD_GPIO20, +N IO_PAD_GPIO21, +N IO_PAD_GPIO22, +N IO_PAD_GPIO23, +N IO_PAD_GPIO24, +N IO_PAD_GPIO25, +N +N /*以实际PAD NAME命名PIN*/ +N IO_PAD_AP_SPIS_MISO = IO_PAD_GPIO0, +N IO_PAD_AP_SPIS_MOSI = IO_PAD_GPIO1, +N IO_PAD_AP_INT = IO_PAD_GPIO2, +N IO_PAD_AP_TE = IO_PAD_GPIO3, +N IO_PAD_AP_SWIRE = IO_PAD_GPIO4, +N IO_PAD_TD_SPIM_MISO = IO_PAD_GPIO5, +N IO_PAD_TD_SPIM_MOSI = IO_PAD_GPIO6, +N IO_PAD_TD_RSTN = IO_PAD_GPIO7, +N IO_PAD_AP_PWMEN = IO_PAD_GPIO8, +N IO_PAD_AP_SPIS_CLK = IO_PAD_GPIO9, +N IO_PAD_AP_SPIS_CSN = IO_PAD_GPIO10, +N IO_PAD_TD_FC_CLK = IO_PAD_GPIO11, +N IO_PAD_TD_FC_CSN = IO_PAD_GPIO12, +N IO_PAD_TD_FC_IO0 = IO_PAD_GPIO13, +N IO_PAD_TD_FC_IO1 = IO_PAD_GPIO14, +N IO_PAD_SWD_CLK = IO_PAD_GPIO15, +N IO_PAD_SWD_DIO = IO_PAD_GPIO16, +N IO_PAD_AP_RSTN = IO_PAD_GPIO17, +N IO_PAD_UART0_TX = IO_PAD_GPIO18, +N IO_PAD_TD_SPIM_CLK = IO_PAD_GPIO19, +N IO_PAD_TD_SPIM_CSN = IO_PAD_GPIO20, +N IO_PAD_AP_TPRSTN = IO_PAD_GPIO21, +N IO_PAD_TD_INT = IO_PAD_GPIO22, +N IO_PAD_TD_TP_RESX = IO_PAD_GPIO23, +N IO_PAD_UART1_TX = IO_PAD_GPIO24, +N IO_PAD_UART0_RX = IO_PAD_GPIO25, +N +N IO_PAD_MAX, +N +N +N /*以实际引脚序号命名PIN*/ +N IO_PIN_1 = IO_PAD_SWD_CLK, +N IO_PIN_2 = IO_PAD_UART0_TX, +N IO_PIN_3 = IO_PAD_SWD_DIO, +N IO_PIN_4 = IO_PAD_TD_SPIM_MOSI, +N IO_PIN_5 = IO_PAD_TD_SPIM_CLK, +N IO_PIN_6 = IO_PAD_TD_SPIM_CSN, +N IO_PIN_7 = IO_PAD_TD_SPIM_MISO, +N IO_PIN_8 = IO_PAD_TD_RSTN, +N IO_PIN_9 = IO_PAD_TD_FC_CSN, +N IO_PIN_10 = IO_PAD_TD_FC_CLK, +N IO_PIN_11 = IO_PAD_TD_FC_IO0, +N IO_PIN_12 = IO_PAD_TD_FC_IO1, +N IO_PIN_13 = IO_PAD_TD_TP_RESX, +N IO_PIN_14 = IO_PAD_UART1_TX, +N IO_PIN_15 = IO_PAD_AP_SWIRE, +N IO_PIN_16 = IO_PAD_AP_INT, +N IO_PIN_17 = IO_PAD_AP_PWMEN, +N IO_PIN_18 = IO_PAD_AP_TPRSTN, +N +N IO_PIN_29 = IO_PAD_AP_TE, +N IO_PIN_30 = IO_PAD_AP_SPIS_MISO, +N IO_PIN_31 = IO_PAD_AP_SPIS_CSN, +N IO_PIN_32 = IO_PAD_AP_SPIS_CLK, +N IO_PIN_33 = IO_PAD_AP_SPIS_MOSI, +N IO_PIN_34 = IO_PAD_AP_RSTN, +N IO_PIN_35 = IO_PAD_TD_INT, +N IO_PIN_36 = IO_PAD_UART0_RX, +N +N} io_pad_e; +N +N +N/* +N芯片引脚 | 默认mode | 可选mode +N---------------------------------------------------------------- +NIO_PIN_1 | IO_PAD_SWCLK, | PIN1_MODE_SWDCLK +N | | PIN1_MODE_GPIO15 +N---------------------------------------------------------------- +NIO_PIN_2 | IO_PAD_UART0_TX, | PIN2_MODE_UART0_TX +N | | PIN2_MODE_PWMO +N | | PIN2_MODE_GPIO18 +N | | PIN2_MODE_PWMI +N | | PIN2_MODE_TEAR1 +N---------------------------------------------------------------- +NIO_PIN_3 | IO_PAD_SWDIO, | PIN3_MODE_SWDIO +N | | PIN3_MODE_GPIO16 +N---------------------------------------------------------------- +NIO_PIN_4 | IO_PAD_TD_SPIM_MOSI, | PIN4_MODE_SPIM_MOSI +N | | PIN4_MODE_I2C02_SDA +N | | PIN4_MODE_GPIO6 +N | | PIN4_MODE_UART0_TX +N---------------------------------------------------------------- +NIO_PIN_5 | IO_PAD_TD_SPIM_CLK, | PIN5_MODE_SPIM_SCLK +N | | PIN5_MODE_I2C1_SCL +N | | PIN5_MODE_GPIO19 +N---------------------------------------------------------------- +NIO_PIN_6 | IO_PAD_TD_SPIM_CSN, | PIN6_MODE_SPIM_CSN +N | | PIN6_MODE_I2C1_SDA +N | | PIN6_MODE_GPIO20 +N---------------------------------------------------------------- +NIO_PIN_7 | IO_PAD_TD_SPIM_MISO, | PIN7_MODE_SPIM_MISO +N | | PIN7_MODE_I2C02_SCL +N | | PIN7_MODE_GPIO5 +N---------------------------------------------------------------- +NIO_PIN_8 | IO_PAD_TD_RSTN, | PIN8_MODE_GPIO7 +N | | PIN8_MODE_I2C02_SDA +N---------------------------------------------------------------- +NIO_PIN_9 | IO_PAD_TD_FC_CSN, | PIN9_MODE_TSPIS_CSN +N | | PIN9_MODE_GPIO12 +N---------------------------------------------------------------- +NIO_PIN_10 | IO_PAD_TD_FC_CLK, | PIN10_MODE_TSPIS_CLK +N | | PIN10_MODE_GPIO11 +N---------------------------------------------------------------- +NIO_PIN_11 | IO_PAD_TD_FC_IO0, | PIN11_MODE_TSPIS_IO0 +N | | PIN11_MODE_GPIO13 +N | | PIN11_MODE_I2C02_SDA +N---------------------------------------------------------------- +NIO_PIN_12 | IO_PAD_TD_FC_IO1, | PIN12_MODE_TSPIS_IO1 +N | | PIN12_MODE_GPIO14 +N | | PIN12_MODE_I2C02_SCL +N---------------------------------------------------------------- +NIO_PIN_13 | IO_PAD_TD_TP_RESX, | PIN13_MODE_GPIO23 +N | | PIN13_MODE_PWMO +N | | PIN13_MODE_UART1_RX +N | | PIN13_MODE_UART1_RX +N---------------------------------------------------------------- +NIO_PIN_14 | IO_PAD_UART1_TX, | PIN14_MODE_GPIO24 +N | | PIN14_MODE_UART0_RX +N | | PIN14_MODE_UART1_TX +N | | +N---------------------------------------------------------------- +NIO_PIN_15 | IO_PAD_AP_SWIRE, | PIN15_MODE_SWIRE +N | | PIN15_MODE_PWMO +N | | PIN15_MODE_GPIO4 +N---------------------------------------------------------------- +NIO_PIN_16 | IO_PAD_AP_INT, | PIN16_MODE_GPIO2 +N---------------------------------------------------------------- +NIO_PIN_17 | IO_PAD_AP_PWMEN, | PIN17_MODE_UART0_RX +N | | PIN17_MODE_GPIO8 +N | | PIN17_MODE_PWMO +N---------------------------------------------------------------- +NIO_PIN_18 | IO_PAD_AP_TPRSTN, | PIN18_MODE_UART0_RX +N | | PIN18_MODE_GPIO21 +N | | PIN18_MODE_I2C02_SCL +N---------------------------------------------------------------- +NIO_PIN_29 | IO_PAD_AP_TE, | PIN29_MODE_JTAG_TRSTN +N | | PIN29_MODE_TEAR +N | | PIN29_MODE_GPIO3 +N---------------------------------------------------------------- +NIO_PIN_30 | IO_PAD_AP_SPIS_MISO, | PIN30_MODE_JTAG_TDO +N | | PIN30_MODE_SPIS_MISO +N | | PIN30_MODE_GPIO0 +N | | PIN30_MODE_UART0_RX +N | | PIN30_MODE_I2C1_SCL +N---------------------------------------------------------------- +NIO_PIN_31 | IO_PAD_AP_SPIS_CSN, | PIN31_MODE_JTAG_TMS +N | | PIN31_MODE_SPIS_CSN +N | | PIN31_MODE_GPIO10 +N | | PIN31_MODE_I2C02_SDA +N---------------------------------------------------------------- +NIO_PIN_32 | IO_PAD_AP_SPIS_CLK, | PIN32_MODE_JTAG_TCK +N | | PIN32_MODE_SPIS_SCLK +N | | PIN32_MODE_GPIO9 +N | | PIN32_MODE_I2C02_SCL +N---------------------------------------------------------------- +NIO_PIN_33 | IO_PAD_AP_SPIS_MOSI, | PIN33_MODE_JTAG_TDI +N | | PIN33_MODE_SPIS_MOSI +N | | PIN33_MODE_GPIO1 +N | | PIN33_MODE_UART0_TX +N | | PIN33_MODE_I2C1_SDA_0 +N---------------------------------------------------------------- +NIO_PIN_34 | IO_PAD_AP_RSTN, | PIN34_MODE_GPIO17 +N---------------------------------------------------------------- +NIO_PIN_35 | IO_PAD_TD_INT, | PIN35_MODE_GPIO22 +N---------------------------------------------------------------- +NIO_PIN_36 | IO_PAD_UART0_RX, | PIN36_MODE_UART0_RX +N | | PIN36_MODE_PWMO +N | | PIN36_MODE_GPIO25 +N---------------------------------------------------------------- +N*/ +N +N +N/** +N* @brief PIN1 IO_PAD_SWD_CLK 可选的mode +N*/ +Ntypedef enum +N{ +N PIN1_MODE_SWDCLK = 0, +N PIN1_MODE_GPIO15 = 2, +N} pin1_mode_e; +N +N +N/** +N* @brief PIN2 PAD_UART0_TX可选的mode +N*/ +Ntypedef enum +N{ +N PIN2_MODE_UART0_TX = 0, +N PIN2_MODE_PWMO = 1, +N PIN2_MODE_GPIO18 = 2, +N PIN2_MODE_PWMI = 3, +N PIN2_MODE_TEAR1 = 4, +N} pin2_mode_e; +N +N/** +N* @brief PIN3 IO_PAD_SWD_DIO 可选的mode +N*/ +Ntypedef enum +N{ +N PIN3_MODE_SWDIO = 0, +N PIN3_MODE_GPIO16 = 2, +N} pin3_mode_e; +N +N +N/** +N* @brief PIN4 PAD_TD_SPIM_MOSI可选的mode +N*/ +Ntypedef enum +N{ +N PIN4_MODE_SPIM_MOSI = 0, +N PIN4_MODE_I2C02_SDA = 1, +N PIN4_MODE_GPIO6 = 2, +N PIN4_MODE_UART0_TX = 3, +N} pin4_mode_e; +N +N/** +N* @brief PIN5 PAD_TD_SPIM_CLK可选的mode +N*/ +Ntypedef enum +N{ +N PIN5_MODE_SPIM_SCLK = 0, +N PIN5_MODE_I2C1_SCL = 1, +N PIN5_MODE_GPIO19 = 2, +N} pin5_mode_e; +N +N/** +N* @brief PIN6 PAD_TD_SPIM_CSN可选的mode +N*/ +Ntypedef enum +N{ +N PIN6_MODE_SPIM_CSN = 0, +N PIN6_MODE_I2C1_SDA = 1, +N PIN6_MODE_GPIO20 = 2, +N} pin6_mode_e; +N +N/** +N* @brief PIN7 PAD_TD_SPIM_MISO可选的mode +N*/ +Ntypedef enum +N{ +N PIN7_MODE_SPIM_MISO = 0, +N PIN7_MODE_I2C02_SCL = 1, +N PIN7_MODE_GPIO5 = 2, +N} pin7_mode_e; +N +N/** +N* @brief PIN8 PAD_TD_RSTN可选的mode +N*/ +Ntypedef enum +N{ +N PIN8_MODE_GPIO7 = 2, +N PIN8_MODE_I2C02_SDA = 3, +N} pin8_mode_e; +N +N/** +N* @brief PIN9 PAD_TD_FC_CSN可选的mode +N*/ +Ntypedef enum +N{ +N PIN9_MODE_TSPIS_CSN = 0, +N PIN9_MODE_GPIO12 = 2, +N} pin9_mode_e; +N +N/** +N* @brief PIN10 PAD_TD_FC_CLK可选的mode +N*/ +Ntypedef enum +N{ +N PIN10_MODE_TSPIS_CLK = 0, +N PIN10_MODE_GPIO11 = 2, +N} pin10_mode_e; +N +N +N/** +N* @brief PIN11 PAD_TD_FC_IO0可选的mode +N*/ +Ntypedef enum +N{ +N PIN11_MODE_TSPIS_IO0 = 0, +N PIN11_MODE_GPIO13 = 2, +N PIN11_MODE_I2C02_SDA = 3, +N} pin11_mode_e; +N +N/** +N* @brief PIN12 PAD_TD_FC_IO1可选的mode +N*/ +Ntypedef enum +N{ +N PIN12_MODE_TSPIS_IO1 = 0, +N PIN12_MODE_GPIO14 = 2, +N PIN12_MODE_I2C02_SCL = 3, +N} pin12_mode_e; +N +N/** +N* @brief PIN13 PAD_TD_TP_RESX可选的mode +N*/ +Ntypedef enum +N{ +N PIN13_MODE_GPIO23 = 2, +N PIN13_MODE_PWMO = 3, +N PIN13_MODE_UART1_RX = 4, +N} pin13_mode_e; +N +N/** +N* @brief PIN14 PAD_UART1_TX可选的mode +N*/ +Ntypedef enum +N{ +N PIN14_MODE_GPIO24 = 2, +N PIN14_MODE_UART0_RX = 3, +N PIN14_MODE_UART1_TX = 4, +N} pin14_mode_e; +N +N +N +N/** +N* @brief PIN15 PAD_AP_SWIRE可选的mode +N*/ +Ntypedef enum +N{ +N PIN15_MODE_SWIRE = 0, +N PIN15_MODE_PWMO = 1, +N PIN15_MODE_GPIO4 = 2, +N} pin15_mode_e; +N +N/** +N* @brief PIN16 IO_PAD_AP_INT 可选的mode +N*/ +Ntypedef enum +N{ +N PIN16_MODE_GPIO2 = 2, +N} pin16_mode_e; +N +N/** +N* @brief PIN17 PAD_AP_PWMEN可选的mode +N*/ +Ntypedef enum +N{ +N PIN17_MODE_UART0_RX = 1, +N PIN17_MODE_GPIO8 = 2, +N PIN17_MODE_PWMO = 3, +N} pin17_mode_e; +N +N/** +N* @brief PIN18 IO_PAD_AP_TPRSTN 可选的mode +N*/ +Ntypedef enum +N{ +N PIN18_MODE_UART0_RX = 0, +N PIN18_MODE_GPIO21 = 2, +N PIN18_MODE_I2C02_SCL = 3, +N} pin18_mode_e; +N +N +N//---------- +N +N/** +N* @brief PIN29 IO_PAD_AP_TE 可选的mode +N*/ +Ntypedef enum +N{ +N PIN29_MODE_JTAG_TRSTN = 0, +N PIN29_MODE_TEAR = 1, +N PIN29_MODE_GPIO3 = 2, +N} pin29_mode_e; +N +N +N/** +N* @brief PIN30 IO_PAD_AP_SPIS_MISO 可选的mode +N*/ +Ntypedef enum +N{ +N PIN30_MODE_JTAG_TDO = 0, +N PIN30_MODE_SPIS_MISO = 1, +N PIN30_MODE_GPIO0 = 2, +N PIN30_MODE_UART0_RX = 3, +N PIN30_MODE_I2C1_SCL = 6, +N} pin30_mode_e; +N +N/** +N* @brief PIN31 IO_PAD_AP_SPIS_CSN 可选的mode +N*/ +Ntypedef enum +N{ +N PIN31_MODE_JTAG_TMS = 0, +N PIN31_MODE_SPIS_CSN = 1, +N PIN31_MODE_GPIO10 = 2, +N PIN31_MODE_I2C02_SDA = 3, +N} pin31_mode_e; +N +N/** +N* @brief PIN32 IO_PAD_AP_SPIS_CLK 可选的mode +N*/ +Ntypedef enum +N{ +N PIN32_MODE_JTAG_TCK = 0, +N PIN32_MODE_SPIS_SCLK = 1, +N PIN32_MODE_GPIO9 = 2, +N PIN32_MODE_I2C02_SCL = 3, +N} pin32_mode_e; +N +N/** +N* @brief PIN33 IO_PAD_AP_SPIS_MOSI 可选的mode +N*/ +Ntypedef enum +N{ +N PIN33_MODE_JTAG_TDI = 0, +N PIN33_MODE_SPIS_MOSI = 1, +N PIN33_MODE_GPIO1 = 2, +N PIN33_MODE_UART0_TX = 3, +N PIN33_MODE_I2C1_SDA_0 = 6, +N} pin33_mode_e; +N +N/** +N* @brief PIN34 PAD_AP_RST可选的mode +N*/ +Ntypedef enum +N{ +N PIN34_MODE_GPIO17 = 2, +N} pin34_mode_e; +N +N +N/** +N* @brief PIN35 PAD_TD_INT可选的mode +N*/ +Ntypedef enum +N{ +N PIN35_MODE_GPIO22 = 2, +N} pin35_mode_e; +N +N +N/** +N* @brief PIN36 PAD_UART_RX可选的mode +N*/ +Ntypedef enum +N{ +N PIN36_MODE_UART0_RX = 0, +N PIN36_MODE_PWMO = 1, +N PIN36_MODE_GPIO25 = 2, +N} pin36_mode_e; +N +N +N +N//------------------------------------------------------------------------- +N/** +N* @brief PAD_SFC_CLK可选的mode 内部PAD +N*/ +Ntypedef enum +N{ +N IO_MODE_INTER_FC_CLK = 0, +N IO_MODE_TSPIS_CLK_EN = 2, +N} pad_sfc_clk_mode_e; +N +N/** +N* @brief PAD_SFC_CSN可选的mode 内部PAD +N*/ +Ntypedef enum +N{ +N IO_MODE_INTER_FC_CSN = 0, +N IO_MODE_TSPIS_CSN_EN = 2, +N} pad_sfc_csn_mode_e; +N +N/** +N* @brief PAD_SFC_IO0可选的mode 内部PAD +N*/ +Ntypedef enum +N{ +N IO_MODE_INTER_FC_IO0 = 0, +N IO_MODE_TSPIS_IO0_EN = 2, +N} pad_sfc_io0_mode_e; +N +N/** +N* @brief PAD_SFC_IO1可选的mode 内部PAD +N*/ +Ntypedef enum +N{ +N IO_MODE_INTER_FC_IO1 = 0, +N IO_MODE_TSPIS_IO1_EN = 2, +N} pad_sfc_io1_mode_e; +N +N/** +N* @brief PAD电压转换速率 +N*/ +Ntypedef enum +N{ +N IO_SLEW_RATE_SLOW = 0, +N IO_SLEW_RATE_FAST = 1, +N} pad_slew_rate_e; +N +N/******************************************************************************* +N* IOE +N*******************************************************************************/ +N/** +N* @brief GPIO io方向 +N*/ +Ntypedef enum +N{ +N IO_IOE_INPUT = 0, +N IO_IOE_OUTPUT, +N IO_IOE_NONE +N} gpio_ioe_e; +N +N/** +N* @brief GPIO level +N*/ +Ntypedef enum +N{ +N IO_LVL_LOW = 0, +N IO_LVL_HIGH, +N IO_LVL_NONE +N} gpio_level_e; +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/** +N* @brief PAD与MODE的MAP结构体 +N*/ +Ntypedef struct +N{ +N io_pad_e pad; +N uint8_t mode; +N gpio_ioe_e ioe; +N gpio_level_e lvl; +N} io_pad_attr_t; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N/** +N* @brief 配置指定PAD为GPIO mode，方向为input，指定中断触发方式 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param trig：4种中断触发方式，参考枚举类型sys_cfg_trigger_e +N* @retval 无 +N*/ +Nvoid hal_gpio_init_eint(io_pad_e pad, sys_cfg_trigger_e trig); +N +N/** +N* @brief 注册GPIO中断回调函数 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param cb_func：回调函数地址 +N* @param data：回调函数参数地址 +N* @retval 无 +N*/ +Nvoid hal_gpio_reg_eint_cb(io_pad_e pad, fcb_type cb_func); +N +N/** +N* @brief 开关GPIO中断 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param state：开关控制 +N* @retval 无 +N*/ +Nvoid hal_gpio_ctrl_eint(io_pad_e pad, bool state); +Xvoid hal_gpio_ctrl_eint(io_pad_e pad, _Bool state); +N +N/** +N* @brief 获取GPIO中断类型 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @retval 无 +N*/ +Ngpio_int_e hal_gpio_get_int_type(io_pad_e pad); +N +N/** +N* @brief 配置指定PAD为GPIO mode，方向为output，指定初始电平 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param lvl：初始电平，参考枚举类型gpio_level_e +N* @retval 无 +N*/ +Nvoid hal_gpio_init_output(io_pad_e pad, gpio_level_e lvl); +N +N/** +N* @brief 封装设置输出接口 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param lvl：初始电平，参考枚举类型gpio_level_e +N* @retval 无 +N*/ +Nvoid hal_gpio_set_output_data(io_pad_e pad, gpio_level_e lvl); +N +N/** +N* @brief 配置指定PAD为GPIO mode，方向为input +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @retval 无 +N*/ +Nvoid hal_gpio_init_input(io_pad_e pad); +N +N/** +N* @brief 读取输入电平 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @retval 无 +N*/ +Ngpio_level_e hal_gpio_get_input_data(io_pad_e pad); +N +N/** +N* @brief 设置io mode +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param mode：工作模式，参考各PAD对应的mode枚举类型 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_mode(io_pad_e pad, uint8_t mode); +N +N/** +N* @brief 设置io 为高阻态 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @retval 无 +N*/ +Nvoid hal_gpio_set_high_impedance(io_pad_e pad); +N +N/** +N* @brief 获取指定PAD的默认上拉、下拉状态 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param up_enable：默认上拉状态 +N* @param down_enable：默认下拉状态 +N* @retval 无 +N*/ +Nvoid hal_gpio_get_pull_state(io_pad_e pad, bool *up_enable, bool *down_enable); +Xvoid hal_gpio_get_pull_state(io_pad_e pad, _Bool *up_enable, _Bool *down_enable); +N +N/** +N* @brief 配置指定PAD的默认上拉、下拉状态 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param up_enable：默认上拉状态 +N* @param down_enable：默认下拉状态 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_pull_state(io_pad_e pad, bool up_enable, bool down_enable); +Xvoid hal_gpio_set_pull_state(io_pad_e pad, _Bool up_enable, _Bool down_enable); +N +N/** +N* @brief 配置指定PAD是否为施密特触发 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param st_enable：1为施密特触发，0为正常触发 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_schmitt_trigger(io_pad_e pad, bool st_enable); +Xvoid hal_gpio_set_schmitt_trigger(io_pad_e pad, _Bool st_enable); +N +N/** +N* @brief 配置指定PAD的驱动能力 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param strength：驱动强度，取值为0~3 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_driving_strength(io_pad_e pad, uint8_t strength); +N +N/** +N* @brief 配置指定PAD的电压转换速率 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param rate：驱动强度，取值为0~3 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_slew_rate(io_pad_e pad, pad_slew_rate_e rate); +N +N/** +N* @brief 配置AP_RSTN引脚中断 +N* @param enable: 中断开关 +N* @param cb_func：回调函数 +N* @param trig：触发模式 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_ap_reset_int(bool enable, fcb_type cb_func, sys_cfg_trigger_e trig); +Xvoid hal_gpio_set_ap_reset_int(_Bool enable, fcb_type cb_func, sys_cfg_trigger_e trig); +N +N/** +N* @brief 批量设置IO参数 +N* @param attrs: PAD属性 +N* @param size: 数组成员个数 +N* @retval 无 +N*/ +Nvoid hal_gpio_config_pad(io_pad_attr_t *attrs, uint8_t size); +N +N#endif /* __HAL_GPIO_H__ */ +L 17 "..\..\src\sdk\include\hal_system.h" 2 +N#include "tau_log.h" +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/** +N* @brief 系统时钟配置 +N*/ +Ntypedef enum +N{ +N HAL_SYSCLK_80M = 80000000, +N HAL_SYSCLK_100M = 100000000, +N HAL_SYSCLK_150M = 150000000 +N} hal_system_clk_e; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N +N/** +N* @brief system 初始化 +N* @param sysclk:系统时钟 +N* @retval none +N*/ +Nvoid hal_system_init(hal_system_clk_e sysclk); +N +N/** +N* @brief mcu进入idle模式,等待中断唤醒 +N* @param disable_systick: 进入idle时是否关闭systick(退出idle 恢复systick) +N* @retval none +N*/ +Nvoid hal_system_idle_mode(bool disable_systick); +Xvoid hal_system_idle_mode(_Bool disable_systick); +N +N/** +N* @brief 注册systick回调函数 +N* @param cb_func：回调函数地址 +N* @retval 无 +N*/ +Nvoid hal_system_register_systick_cb(fcb_type cb_func); +N +N/** +N* @brief 启动sys tickt +N* @param ms: sys tickt 间隔, 范围1-10ms +N* @retval true/false +N*/ +Nbool hal_system_enable_systick(uint8_t ms); +X_Bool hal_system_enable_systick(uint8_t ms); +N +N/** +N* @brief 获取systickt +N* @param none +N* @retval 当前systickt值 +N*/ +Nbool hal_system_disable_systick(void); +X_Bool hal_system_disable_systick(void); +N +N/** +N* @brief 获取systickt +N* @param none +N* @retval 当前systickt值 +N*/ +Nuint32_t hal_system_get_tick(void); +N +N/** +N* @brief reset chip +N* @param none +N* @retval none +N*/ +Nvoid hal_system_reset_chip(void); +N +N/** +N* @brief 获取上位机设置的debug state(debug only) +N* @param none +N* @retval debug state +N*/ +Nuint32_t hal_system_get_debug_state(void); +N +N/** +N* @brief clear debug state(debug only) +N* @param none +N* @retval none +N*/ +Nvoid hal_system_clear_debug_state(void); +N +N/** +N* @brief 更新MCU时钟 +N* @param sysclk:系统时钟 +N* @retval true/false +N*/ +Nbool hal_system_updata_sysclk(hal_system_clk_e sysclk); +X_Bool hal_system_updata_sysclk(hal_system_clk_e sysclk); +N +N#endif //__HAL_SYSTEM_H__ +L 7 "..\..\src\app\main.c" 2 +N#include "board.h" +L 1 "..\..\src\board\board.h" 1 +N/******************************************************************************* +N* +N* +N* File: board.h +N* Description: baord 初始化头文件 +N* Version: V0.1 +N* Date: 2020-01-08 +N* Author: lzy +N *******************************************************************************/ +N +N#ifndef __BOARD_H__ +N#define __BOARD_H__ +N +N/** +N* @brief 系统板级初始化,配置系统时钟,调试log输出 +N* @param none +N* @retval none +N*/ +Nvoid board_Init(void); +N +N#endif +L 8 "..\..\src\app\main.c" 2 +N#include "module_demo_main.h" +L 1 "..\..\src\app\module_demo\module_demo_main.h" 1 +N/******************************************************************************* +N* +N* File: module_demo_main.h +N* Description: module demo main file +N* Version: V0.1 +N* Date: 2023-07-27 +N* Author: Jaya +N *******************************************************************************/ +N +N#ifndef __MODULE_DEMO_MAIN_H__ +N#define __MODULE_DEMO_MAIN_H__ +N#include "test_cfg_global.h" +N +N#if _MODULE_DEMO_DSI_TX_EN +X#if 0 +S#include "demo_hal_dsi_tx.h" +N#endif +N +N#if _MODULE_DEMO_DSI_RX_EN +X#if 0 +S#include "demo_hal_dsi_rx.h" +N#endif +N +N#if _MODULE_DEMO_TIMER_EN +X#if 0 +S#include "demo_hal_timer.h" +N#endif +N +N#if _MODULE_DEMO_WDG_EN +X#if 0 +S#include "demo_hal_wdg.h" +N#endif +N +N#if _MODULE_DEMO_GPIO_EN +X#if 0 +S#include "demo_hal_gpio.h" +N#endif +N +N#if _MODULE_DEMO_SWIRE_EN +X#if 0 +S#include "demo_hal_swire.h" +N#endif +N +N#if _MODULE_DEMO_SPI_EN +X#if 0 +S#include "demo_hal_spi.h" +N#endif +N +N#if _MODULE_DEMO_I2C_EN +X#if 0 +S#include "demo_hal_i2c.h" +N#endif +N +N#if _MODULE_DEMO_FLASH_EN +S#include "demo_hal_flash.h" +N#endif +N +N#if _MODULE_DEMO_PWM_EN +X#if 0 +S#include "demo_hal_pwm.h" +N#endif +N +N#if _MODULE_DEMO_PWR_EN +X#if 0 +S#include "demo_hal_pwr.h" +N#endif +N +N#if _MODULE_DEMO_UART_EN +S#include "demo_hal_uart.h" +N#endif +N +N#if _MODULE_DEMO_CRC_EN +S#include "demo_hal_crc.h" +N#endif +N +Nvoid module_demo_main(void); +N +N#endif /* __MODULE_DEMO_MAIN_H__ */ +L 9 "..\..\src\app\main.c" 2 +Nint main() +N{ +N board_Init(); +N +N while (1) +N { +N#if _MODULE_DEMO_ENABLE +X#if 0 +S module_demo_main(); +N#endif +N +N +N#if _DEMO_GOOGLE_P8P_EN +X#if 1 +N google_p8p_demo(); +N#endif +N TAU_LOGD("668 Demo\n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "668 Demo\n", "tau_log", 23); } while (0); +N while (1); +N } +N} diff --git a/project/WL668/Listings/main.txt b/project/WL668/Listings/main.txt new file mode 100644 index 0000000..0a9b2cb --- /dev/null +++ b/project/WL668/Listings/main.txt @@ -0,0 +1,84 @@ +; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] +; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave --gnu -o.\objects\main.o --asm_dir=.\Listings\ --list_dir=.\Listings\ --depend=.\objects\main.d --cpu=Cortex-M0 --apcs=interwork -O0 --diag_suppress=9931 -I..\..\src -I..\..\src\board -I..\..\src\common -I..\..\src\sdk\include -I..\..\src\sdk\include\M0 -I..\..\src\app -I..\..\src\app\S8 -I..\..\src\app\touch -I..\..\src\app\module_demo -I..\..\src\app\P8P -I.\RTE\_WL668 -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include -D__MICROLIB -D__UVISION_VERSION=528 -D_RTE_ -DARMCM0 --omf_browse=.\objects\main.crf ..\..\src\app\main.c] + THUMB + + AREA ||i.main||, CODE, READONLY, ALIGN=2 + + main PROC +;;;68 #endif /* __MODULE_DEMO_MAIN_H__ */ +;;;9 int main() +000000 f7fffffe BL board_Init +;;;10 { +;;;11 board_Init(); +;;;12 +;;;13 while (1) +000004 e00b B |L1.30| + |L1.6| +;;;14 { +;;;15 #if _MODULE_DEMO_ENABLE +;;;16 module_demo_main(); +;;;17 #endif +;;;18 +;;;19 +;;;20 #if _DEMO_GOOGLE_P8P_EN +;;;21 google_p8p_demo(); +000006 f7fffffe BL google_p8p_demo +;;;22 #endif +;;;23 TAU_LOGD("668 Demo\n"); +00000a bf00 NOP +00000c 2317 MOVS r3,#0x17 +00000e a204 ADR r2,|L1.32| +000010 a105 ADR r1,|L1.40| +000012 2000 MOVS r0,#0 +000014 f7fffffe BL tau_log_printf +000018 bf00 NOP +;;;24 while (1); +00001a bf00 NOP + |L1.28| +00001c e7fe B |L1.28| + |L1.30| +00001e e7f2 B |L1.6| +;;;25 } +;;;26 } + ENDP + + |L1.32| +000020 7461755f DCB "tau_log",0 +000024 6c6f6700 + |L1.40| +000028 5b25735d DCB "[%s] (%04d) 668 Demo\n",0 +00002c 20282530 +000030 34642920 +000034 36363820 +000038 44656d6f +00003c 0a00 +00003e 00 DCB 0 +00003f 00 DCB 0 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\src\\app\\main.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___6_main_c_main____REV16| +#line 467 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" +|__asm___6_main_c_main____REV16| PROC +#line 468 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___6_main_c_main____REVSH| +#line 482 +|__asm___6_main_c_main____REVSH| PROC +#line 483 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** + + __ARM_use_no_argv EQU 0 diff --git a/project/WL668/Listings/p8p_demo._ip b/project/WL668/Listings/p8p_demo._ip new file mode 100644 index 0000000..392393e --- /dev/null +++ b/project/WL668/Listings/p8p_demo._ip @@ -0,0 +1,6 @@ +..\..\src\app\P8P\p8p_demo.c -E --c99 --gnu -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections -I ..\..\src -I ..\..\src\board -I ..\..\src\common -I ..\..\src\sdk\include -I ..\..\src\sdk\include\M0 -I ..\..\src\app -I ..\..\src\app\S8 -I ..\..\src\app\touch -I ..\..\src\app\module_demo -I ..\..\src\app\P8P +-I.\RTE\_WL668 +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include +-D__UVISION_VERSION="528" -D_RTE_ -DARMCM0 +-o .\listings\p8p_demo.i --list_dir ".\\Listings\\" --list \ No newline at end of file diff --git a/project/WL668/Listings/p8p_demo.i b/project/WL668/Listings/p8p_demo.i new file mode 100644 index 0000000..0720511 --- /dev/null +++ b/project/WL668/Listings/p8p_demo.i @@ -0,0 +1,8325 @@ +# 1 "..\\..\\src\\app\\P8P\\p8p_demo.c" + + + + + + + + +# 1 "..\\..\\src\\app\\P8P\\p8p_demo.h" + + + + + + + + + + + + + + + + + + +void google_p8p_demo(void); + +# 10 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef enum IRQn +{ + + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVCall_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + + VIDC_IRQn = 0, + LCDC_IRQn = 1, + MIPI_RX_IRQn = 2, + MIPI_TX_IRQn = 3, + MEMC_IRQn = 4, + VPRE_IRQn = 5, + FLSCTRL_IRQn = 6, + DMA_IRQn = 7, + TIMER0_IRQn = 8, + TIMER1_IRQn = 9, + TIMER2_IRQn = 10, + TIMER3_IRQn = 11, + WDG_IRQn = 12, + UART_IRQn = 13, + I2C0_IRQn = 14, + I2C1_IRQn = 15, + SPIS_IRQn = 16, + SPIM_IRQn = 17, + VPRE1_IRQn = 18, + I2C2_IRQn = 19, + OTP_IRQn = 20, + SWIRE_IRQn = 21, + PVD_IRQn = 22, + AP_NRESET_IRQn = 23, + EXTI_INT0_IRQn = 24, + EXTI_INT1_IRQn = 25, + EXTI_INT2_IRQn = 26, + EXTI_INT3_IRQn = 27, + EXTI_INT4_IRQn = 28, + EXTI_INT5_IRQn = 29, + EXTI_INT6_IRQn = 30, + EXTI_INT7_IRQn = 31 + +} IRQn_Type; + + + + + + + + +#pragma push +#pragma anon_unions +# 107 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + + + + + + + + + + + + +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + + + + + + + + + +# 27 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + + + +# 46 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + +typedef signed char int8_t; +typedef signed short int int16_t; +typedef signed int int32_t; +typedef signed __int64 int64_t; + + +typedef unsigned char uint8_t; +typedef unsigned short int uint16_t; +typedef unsigned int uint32_t; +typedef unsigned __int64 uint64_t; + + + + + +typedef signed char int_least8_t; +typedef signed short int int_least16_t; +typedef signed int int_least32_t; +typedef signed __int64 int_least64_t; + + +typedef unsigned char uint_least8_t; +typedef unsigned short int uint_least16_t; +typedef unsigned int uint_least32_t; +typedef unsigned __int64 uint_least64_t; + + + + +typedef signed int int_fast8_t; +typedef signed int int_fast16_t; +typedef signed int int_fast32_t; +typedef signed __int64 int_fast64_t; + + +typedef unsigned int uint_fast8_t; +typedef unsigned int uint_fast16_t; +typedef unsigned int uint_fast32_t; +typedef unsigned __int64 uint_fast64_t; + + + + + + +typedef signed int intptr_t; +typedef unsigned int uintptr_t; + + + +typedef signed long long intmax_t; +typedef unsigned long long uintmax_t; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 216 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + + + + + + + + + +# 241 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 305 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h" + + + + + + + +# 35 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_version.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 64 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + +# 114 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_compiler.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 29 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_compiler.h" + + + + +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 107 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + +static __inline uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __asm("control"); + return(__regControl); +} + + + + + + + +static __inline void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __asm("control"); + __regControl = control; +} + + + + + + + +static __inline uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __asm("ipsr"); + return(__regIPSR); +} + + + + + + + +static __inline uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __asm("apsr"); + return(__regAPSR); +} + + + + + + + +static __inline uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __asm("xpsr"); + return(__regXPSR); +} + + + + + + + +static __inline uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __asm("psp"); + return(__regProcessStackPointer); +} + + + + + + + +static __inline void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __asm("psp"); + __regProcessStackPointer = topOfProcStack; +} + + + + + + + +static __inline uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __asm("msp"); + return(__regMainStackPointer); +} + + + + + + + +static __inline void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __asm("msp"); + __regMainStackPointer = topOfMainStack; +} + + + + + + + +static __inline uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __asm("primask"); + return(__regPriMask); +} + + + + + + + +static __inline void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __asm("primask"); + __regPriMask = (priMask); +} + + +# 342 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + + + + + +static __inline uint32_t __get_FPSCR(void) +{ + + + + + + return(0U); + +} + + + + + + + +static __inline void __set_FPSCR(uint32_t fpscr) +{ + + + + + + (void)fpscr; + +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +__attribute__((section(".rev16_text"))) static __inline __asm uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + + + + + + + + + +__attribute__((section(".revsh_text"))) static __inline __asm int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +__attribute__((always_inline)) static __inline uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U * 8U) - 1U; + + result = value; + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; + return result; +} + + + + + + + + + + + + +# 732 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + + + + + + +__attribute__((always_inline)) static __inline int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + + + + + + + + +__attribute__((always_inline)) static __inline uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + + + + + + + + + + + + + +# 866 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" + + + +# 35 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_compiler.h" + + + + + +# 268 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_compiler.h" + + + + +# 116 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + +# 150 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + +# 166 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef union +{ + struct + { + uint32_t _reserved0:28; + uint32_t V:1; + uint32_t C:1; + uint32_t Z:1; + uint32_t N:1; + } b; + uint32_t w; +} APSR_Type; + + + + + + + + + + + + + + + + + + +typedef union +{ + struct + { + uint32_t ISR:9; + uint32_t _reserved0:23; + } b; + uint32_t w; +} IPSR_Type; + + + + + + + + + +typedef union +{ + struct + { + uint32_t ISR:9; + uint32_t _reserved0:15; + uint32_t T:1; + uint32_t _reserved1:3; + uint32_t V:1; + uint32_t C:1; + uint32_t Z:1; + uint32_t N:1; + } b; + uint32_t w; +} xPSR_Type; + + + + + + + + + + + + + + + + + + + + + + + + +typedef union +{ + struct + { + uint32_t _reserved0:1; + uint32_t SPSEL:1; + uint32_t _reserved1:30; + } b; + uint32_t w; +} CONTROL_Type; + + + + + + + + + + + + + + + + + + +typedef struct +{ + volatile uint32_t ISER[1U]; + uint32_t RESERVED0[31U]; + volatile uint32_t ICER[1U]; + uint32_t RESERVED1[31U]; + volatile uint32_t ISPR[1U]; + uint32_t RESERVED2[31U]; + volatile uint32_t ICPR[1U]; + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + volatile uint32_t IP[8U]; +} NVIC_Type; + + + + + + + + + + + + + + +typedef struct +{ + volatile const uint32_t CPUID; + volatile uint32_t ICSR; + uint32_t RESERVED0; + volatile uint32_t AIRCR; + volatile uint32_t SCR; + volatile uint32_t CCR; + uint32_t RESERVED1; + volatile uint32_t SHP[2U]; + volatile uint32_t SHCSR; +} SCB_Type; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef struct +{ + volatile uint32_t CTRL; + volatile uint32_t LOAD; + volatile uint32_t VAL; + volatile const uint32_t CALIB; +} SysTick_Type; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 583 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + +# 598 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\core_cm0.h" + + + + + + + + + + + + + + + + + + + + + + + + + +static __inline void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + + + + + + + + + +static __inline uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + + + + + + + +static __inline void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); + do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U); + } +} + + + + + + + + + + +static __inline uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + + + + + + + +static __inline void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + + + + + + + +static __inline void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + + + + + + + + + + +static __inline void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] = ((uint32_t)(((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | + (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); + } + else + { + ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] = ((uint32_t)(((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | + (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); + } +} + + + + + + + + + + + +static __inline uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[ ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); + } + else + { + return((uint32_t)(((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); + } +} + + + + + + + + + + + + + +static __inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + + + + + + + + + + + + +static __inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + + + + + + + + + + +static __inline void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + 16) * 4)) = vector; +} + + + + + + + + + + +static __inline uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + 16) * 4)); +} + + + + + + +__declspec(noreturn) static __inline void __NVIC_SystemReset(void) +{ + do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); + + ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR = ((0x5FAUL << 16U) | + (1UL << 2U)); + do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); + + for(;;) + { + __nop(); + } +} + + + + + + + + + + + + + + + + + + + + +static __inline uint32_t SCB_GetFPUType(void) +{ + return 0U; +} + + + + + + + + + + + + + + + + + + + + + + + + + + + +static __inline uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > (0xFFFFFFUL )) + { + return (1UL); + } + + ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->LOAD = (uint32_t)(ticks - 1UL); + __NVIC_SetPriority (SysTick_IRQn, (1UL << 2U) - 1UL); + ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->VAL = 0UL; + ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL = (1UL << 2U) | + (1UL << 1U) | + (1UL ); + return (0UL); +} + + + + + + + + + + + + + + +# 122 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" +# 1 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\Device\\ARM\\ARMCM0\\Include\\system_ARMCM0.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern uint32_t SystemCoreClock; + + + + + + + +extern void SystemInit (void); + + + + + + + +extern void SystemCoreClockUpdate (void); + + + + + +# 123 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + +#pragma pop +# 142 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + +# 167 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + +# 179 "..\\..\\src\\sdk\\include\\M0\\ArmCM0.h" + + + + + +# 11 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\common\\tau_device_datatype.h" + + + + + + + + + + + + + + + + + + +# 20 "..\\..\\src\\common\\tau_device_datatype.h" +# 1 "..\\..\\src\\common\\tau_common.h" + + + + + + + + + + + + + + + + +# 18 "..\\..\\src\\common\\tau_common.h" +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 61 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + +# 75 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 112 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + + + + + + + + + +extern __attribute__((__pcs__("aapcs"))) unsigned __ARM_dcmp4(double , double ); +extern __attribute__((__pcs__("aapcs"))) unsigned __ARM_fcmp4(float , float ); + + + + + + + +extern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassifyf(float ); +extern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassify(double ); + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinitef(float __x) +{ + return (((*(unsigned *)&(__x)) >> 23) & 0xff) != 0xff; +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinite(double __x) +{ + return (((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff) != 0x7ff; +} + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinff(float __x) +{ + return ((*(unsigned *)&(__x)) << 1) == 0xff000000; +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinf(double __x) +{ + return (((*(1 + (unsigned *)&(__x))) << 1) == 0xffe00000) && ((*(unsigned *)&(__x)) == 0); +} + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreaterf(float __x, float __y) +{ + unsigned __f = __ARM_fcmp4(__x, __y) >> 28; + return (__f == 8) || (__f == 2); +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreater(double __x, double __y) +{ + unsigned __f = __ARM_dcmp4(__x, __y) >> 28; + return (__f == 8) || (__f == 2); +} + + + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnanf(float __x) +{ + return (0x7f800000 - ((*(unsigned *)&(__x)) & 0x7fffffff)) >> 31; +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnan(double __x) +{ + unsigned __xf = (*(1 + (unsigned *)&(__x))) | (((*(unsigned *)&(__x)) == 0) ? 0 : 1); + return (0x7ff00000 - (__xf & 0x7fffffff)) >> 31; +} + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormalf(float __x) +{ + unsigned __xe = ((*(unsigned *)&(__x)) >> 23) & 0xff; + return (__xe != 0xff) && (__xe != 0); +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormal(double __x) +{ + unsigned __xe = ((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff; + return (__xe != 0x7ff) && (__xe != 0); +} + + + +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbitf(float __x) +{ + return (*(unsigned *)&(__x)) >> 31; +} +static __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbit(double __x) +{ + return (*(1 + (unsigned *)&(__x))) >> 31; +} + + + + + + + + + + +# 230 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + typedef float float_t; + typedef double double_t; +# 251 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + +extern const int math_errhandling; +# 261 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + +extern __declspec(__nothrow) double acos(double ); + + + +extern __declspec(__nothrow) double asin(double ); + + + + + +extern __declspec(__nothrow) __attribute__((const)) double atan(double ); + + + +extern __declspec(__nothrow) double atan2(double , double ); + + + + + +extern __declspec(__nothrow) double cos(double ); + + + + +extern __declspec(__nothrow) double sin(double ); + + + + + +extern void __use_accurate_range_reduction(void); + + + +extern __declspec(__nothrow) double tan(double ); + + + + + +extern __declspec(__nothrow) double cosh(double ); + + + + +extern __declspec(__nothrow) double sinh(double ); + + + + + + +extern __declspec(__nothrow) __attribute__((const)) double tanh(double ); + + + +extern __declspec(__nothrow) double exp(double ); + + + + + + +extern __declspec(__nothrow) double frexp(double , int * ) __attribute__((__nonnull__(2))); + + + + + + + +extern __declspec(__nothrow) double ldexp(double , int ); + + + + +extern __declspec(__nothrow) double log(double ); + + + + + +extern __declspec(__nothrow) double log10(double ); + + + +extern __declspec(__nothrow) double modf(double , double * ) __attribute__((__nonnull__(2))); + + + + + +extern __declspec(__nothrow) double pow(double , double ); + + + + + + +extern __declspec(__nothrow) double sqrt(double ); + + + + + + + + static __inline double _sqrt(double __x) { return sqrt(__x); } + + + + + static __inline float _sqrtf(float __x) { return (float)sqrt(__x); } + + + + + + + +extern __declspec(__nothrow) __attribute__((const)) double ceil(double ); + + +extern __declspec(__nothrow) __attribute__((const)) double fabs(double ); + + + +extern __declspec(__nothrow) __attribute__((const)) double floor(double ); + + + +extern __declspec(__nothrow) double fmod(double , double ); + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) double acosh(double ); + + + +extern __declspec(__nothrow) double asinh(double ); + + + +extern __declspec(__nothrow) double atanh(double ); + + + +extern __declspec(__nothrow) double cbrt(double ); + + + +static __inline __declspec(__nothrow) __attribute__((const)) double copysign(double __x, double __y) + + + +{ + (*(1 + (unsigned *)&(__x))) = ((*(1 + (unsigned *)&(__x))) & 0x7fffffff) | ((*(1 + (unsigned *)&(__y))) & 0x80000000); + return __x; +} +static __inline __declspec(__nothrow) __attribute__((const)) float copysignf(float __x, float __y) + + + +{ + (*(unsigned *)&(__x)) = ((*(unsigned *)&(__x)) & 0x7fffffff) | ((*(unsigned *)&(__y)) & 0x80000000); + return __x; +} +extern __declspec(__nothrow) double erf(double ); + + + +extern __declspec(__nothrow) double erfc(double ); + + + +extern __declspec(__nothrow) double expm1(double ); + + + + + + + + + + + + + + + +# 479 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + +extern __declspec(__nothrow) double hypot(double , double ); + + + + + + +extern __declspec(__nothrow) int ilogb(double ); + + + +extern __declspec(__nothrow) int ilogbf(float ); + + + +extern __declspec(__nothrow) int ilogbl(long double ); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) double lgamma (double ); + + + + +extern __declspec(__nothrow) double log1p(double ); + + + +extern __declspec(__nothrow) double logb(double ); + + + +extern __declspec(__nothrow) float logbf(float ); + + + +extern __declspec(__nothrow) long double logbl(long double ); + + + +extern __declspec(__nothrow) double nextafter(double , double ); + + + + +extern __declspec(__nothrow) float nextafterf(float , float ); + + + + +extern __declspec(__nothrow) long double nextafterl(long double , long double ); + + + + +extern __declspec(__nothrow) double nexttoward(double , long double ); + + + + +extern __declspec(__nothrow) float nexttowardf(float , long double ); + + + + +extern __declspec(__nothrow) long double nexttowardl(long double , long double ); + + + + +extern __declspec(__nothrow) double remainder(double , double ); + + + +extern __declspec(__nothrow) __attribute__((const)) double rint(double ); + + + +extern __declspec(__nothrow) double scalbln(double , long int ); + + + +extern __declspec(__nothrow) float scalblnf(float , long int ); + + + +extern __declspec(__nothrow) long double scalblnl(long double , long int ); + + + +extern __declspec(__nothrow) double scalbn(double , int ); + + + +extern __declspec(__nothrow) float scalbnf(float , int ); + + + +extern __declspec(__nothrow) long double scalbnl(long double , int ); + + + + + + + + + + + + + + +extern __declspec(__nothrow) __attribute__((const)) float _fabsf(float); +static __inline __declspec(__nothrow) __attribute__((const)) float fabsf(float __f) { return _fabsf(__f); } +extern __declspec(__nothrow) float sinf(float ); +extern __declspec(__nothrow) float cosf(float ); +extern __declspec(__nothrow) float tanf(float ); +extern __declspec(__nothrow) float acosf(float ); +extern __declspec(__nothrow) float asinf(float ); +extern __declspec(__nothrow) float atanf(float ); +extern __declspec(__nothrow) float atan2f(float , float ); +extern __declspec(__nothrow) float sinhf(float ); +extern __declspec(__nothrow) float coshf(float ); +extern __declspec(__nothrow) float tanhf(float ); +extern __declspec(__nothrow) float expf(float ); +extern __declspec(__nothrow) float logf(float ); +extern __declspec(__nothrow) float log10f(float ); +extern __declspec(__nothrow) float powf(float , float ); +extern __declspec(__nothrow) float sqrtf(float ); +extern __declspec(__nothrow) float ldexpf(float , int ); +extern __declspec(__nothrow) float frexpf(float , int * ) __attribute__((__nonnull__(2))); +extern __declspec(__nothrow) __attribute__((const)) float ceilf(float ); +extern __declspec(__nothrow) __attribute__((const)) float floorf(float ); +extern __declspec(__nothrow) float fmodf(float , float ); +extern __declspec(__nothrow) float modff(float , float * ) __attribute__((__nonnull__(2))); + + + + + + + + + + + + + + + + + +__declspec(__nothrow) long double acosl(long double ); +__declspec(__nothrow) long double asinl(long double ); +__declspec(__nothrow) long double atanl(long double ); +__declspec(__nothrow) long double atan2l(long double , long double ); +__declspec(__nothrow) long double ceill(long double ); +__declspec(__nothrow) long double cosl(long double ); +__declspec(__nothrow) long double coshl(long double ); +__declspec(__nothrow) long double expl(long double ); +__declspec(__nothrow) long double fabsl(long double ); +__declspec(__nothrow) long double floorl(long double ); +__declspec(__nothrow) long double fmodl(long double , long double ); +__declspec(__nothrow) long double frexpl(long double , int* ) __attribute__((__nonnull__(2))); +__declspec(__nothrow) long double ldexpl(long double , int ); +__declspec(__nothrow) long double logl(long double ); +__declspec(__nothrow) long double log10l(long double ); +__declspec(__nothrow) long double modfl(long double , long double * ) __attribute__((__nonnull__(2))); +__declspec(__nothrow) long double powl(long double , long double ); +__declspec(__nothrow) long double sinl(long double ); +__declspec(__nothrow) long double sinhl(long double ); +__declspec(__nothrow) long double sqrtl(long double ); +__declspec(__nothrow) long double tanl(long double ); +__declspec(__nothrow) long double tanhl(long double ); + + + + + + +extern __declspec(__nothrow) float acoshf(float ); +__declspec(__nothrow) long double acoshl(long double ); +extern __declspec(__nothrow) float asinhf(float ); +__declspec(__nothrow) long double asinhl(long double ); +extern __declspec(__nothrow) float atanhf(float ); +__declspec(__nothrow) long double atanhl(long double ); +__declspec(__nothrow) long double copysignl(long double , long double ); +extern __declspec(__nothrow) float cbrtf(float ); +__declspec(__nothrow) long double cbrtl(long double ); +extern __declspec(__nothrow) float erff(float ); +__declspec(__nothrow) long double erfl(long double ); +extern __declspec(__nothrow) float erfcf(float ); +__declspec(__nothrow) long double erfcl(long double ); +extern __declspec(__nothrow) float expm1f(float ); +__declspec(__nothrow) long double expm1l(long double ); +extern __declspec(__nothrow) float log1pf(float ); +__declspec(__nothrow) long double log1pl(long double ); +extern __declspec(__nothrow) float hypotf(float , float ); +__declspec(__nothrow) long double hypotl(long double , long double ); +extern __declspec(__nothrow) float lgammaf(float ); +__declspec(__nothrow) long double lgammal(long double ); +extern __declspec(__nothrow) float remainderf(float , float ); +__declspec(__nothrow) long double remainderl(long double , long double ); +extern __declspec(__nothrow) float rintf(float ); +__declspec(__nothrow) long double rintl(long double ); + + + + + + + +extern __declspec(__nothrow) double exp2(double ); +extern __declspec(__nothrow) float exp2f(float ); +__declspec(__nothrow) long double exp2l(long double ); +extern __declspec(__nothrow) double fdim(double , double ); +extern __declspec(__nothrow) float fdimf(float , float ); +__declspec(__nothrow) long double fdiml(long double , long double ); +# 803 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" +extern __declspec(__nothrow) double fma(double , double , double ); +extern __declspec(__nothrow) float fmaf(float , float , float ); + +static __inline __declspec(__nothrow) long double fmal(long double __x, long double __y, long double __z) { return (long double)fma((double)__x, (double)__y, (double)__z); } + + +extern __declspec(__nothrow) __attribute__((const)) double fmax(double , double ); +extern __declspec(__nothrow) __attribute__((const)) float fmaxf(float , float ); +__declspec(__nothrow) long double fmaxl(long double , long double ); +extern __declspec(__nothrow) __attribute__((const)) double fmin(double , double ); +extern __declspec(__nothrow) __attribute__((const)) float fminf(float , float ); +__declspec(__nothrow) long double fminl(long double , long double ); +extern __declspec(__nothrow) double log2(double ); +extern __declspec(__nothrow) float log2f(float ); +__declspec(__nothrow) long double log2l(long double ); +extern __declspec(__nothrow) long lrint(double ); +extern __declspec(__nothrow) long lrintf(float ); + +static __inline __declspec(__nothrow) long lrintl(long double __x) { return lrint((double)__x); } + + +extern __declspec(__nothrow) long long llrint(double ); +extern __declspec(__nothrow) long long llrintf(float ); + +static __inline __declspec(__nothrow) long long llrintl(long double __x) { return llrint((double)__x); } + + +extern __declspec(__nothrow) long lround(double ); +extern __declspec(__nothrow) long lroundf(float ); + +static __inline __declspec(__nothrow) long lroundl(long double __x) { return lround((double)__x); } + + +extern __declspec(__nothrow) long long llround(double ); +extern __declspec(__nothrow) long long llroundf(float ); + +static __inline __declspec(__nothrow) long long llroundl(long double __x) { return llround((double)__x); } + + +extern __declspec(__nothrow) __attribute__((const)) double nan(const char * ); +extern __declspec(__nothrow) __attribute__((const)) float nanf(const char * ); + +static __inline __declspec(__nothrow) __attribute__((const)) long double nanl(const char *__t) { return (long double)nan(__t); } +# 856 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" +extern __declspec(__nothrow) __attribute__((const)) double nearbyint(double ); +extern __declspec(__nothrow) __attribute__((const)) float nearbyintf(float ); +__declspec(__nothrow) long double nearbyintl(long double ); +extern double remquo(double , double , int * ); +extern float remquof(float , float , int * ); + +static __inline long double remquol(long double __x, long double __y, int *__q) { return (long double)remquo((double)__x, (double)__y, __q); } + + +extern __declspec(__nothrow) __attribute__((const)) double round(double ); +extern __declspec(__nothrow) __attribute__((const)) float roundf(float ); +__declspec(__nothrow) long double roundl(long double ); +extern __declspec(__nothrow) double tgamma(double ); +extern __declspec(__nothrow) float tgammaf(float ); +__declspec(__nothrow) long double tgammal(long double ); +extern __declspec(__nothrow) __attribute__((const)) double trunc(double ); +extern __declspec(__nothrow) __attribute__((const)) float truncf(float ); +__declspec(__nothrow) long double truncl(long double ); + + + + + + +# 896 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + +# 1087 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + + + + + + +# 1317 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\math.h" + + + + + + +# 19 "..\\..\\src\\common\\tau_common.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 75 "..\\..\\src\\common\\tau_common.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef uint32_t status_t; + + +typedef void (*fcb_type)(void *data); + +typedef void (*uart_trans_cb)(status_t status, void *user_data); + +typedef void (*flash_trans_cb)(status_t status, void *user_data); +# 21 "..\\..\\src\\common\\tau_device_datatype.h" + + + + + + + + + + + + + + + +enum _status_groups +{ + STATUS_GROUP_GENERIC = 0, + STATUS_GROUP_I2C = 1, + STATUS_GROUP_UART = 2, + STATUS_GROUP_SPI = 3, + STATUS_GROUP_TIMER = 4, +}; + + +enum _generic_status +{ + STATUS_SUCCESS = ((((STATUS_GROUP_GENERIC)*100) + (0))), + STATUS_FAIL = ((((STATUS_GROUP_GENERIC)*100) + (1))), + STATUS_READ_ONLY = ((((STATUS_GROUP_GENERIC)*100) + (2))), + STATUS_OUT_OF_RANGE = ((((STATUS_GROUP_GENERIC)*100) + (3))), + STATUS_INVALID_ARGUMENT = ((((STATUS_GROUP_GENERIC)*100) + (4))), + STATUS_TIME_OUT = ((((STATUS_GROUP_GENERIC)*100) + (5))), + STATUS_NO_TRANSFER_IN_PROGRESS = ((((STATUS_GROUP_GENERIC)*100) + (6))), +}; + + + + + +typedef enum +{ + STATUS_UART_TX_BUSY = ((((STATUS_GROUP_UART)*100) + (0))), + STATUS_UART_RX_BUSY = ((((STATUS_GROUP_UART)*100) + (1))), + STATUS_UART_TX_IDLE = ((((STATUS_GROUP_UART)*100) + (2))), + STATUS_UART_RX_IDLE = ((((STATUS_GROUP_UART)*100) + (3))), + STATUS_UART_TX_ERR = ((((STATUS_GROUP_UART)*100) + (7))), + STATUS_UART_RX_ERR = ((((STATUS_GROUP_UART)*100) + (9))), + STATUS_UART_RX_RING_BUFF_OVERRUN = ((((STATUS_GROUP_UART)*100) + (8))), + STATUS_UART_NOISE_ERR = ((((STATUS_GROUP_UART)*100) + (10))), + STATUS_UART_FRAMING_ERR = ((((STATUS_GROUP_UART)*100) + (11))), + STATUS_UART_PARITY_ERR = ((((STATUS_GROUP_UART)*100) + (12))), + STATUS_UART_BAUDRATE_NOT_SPT = ((((STATUS_GROUP_UART)*100) + (13))), +} uart_status_e; + + + + +typedef enum +{ + STATUS_TIMER_IDLE = ((((STATUS_GROUP_TIMER)*100) + (0))), + STATUS_TIMER_RUNNING = ((((STATUS_GROUP_TIMER)*100) + (1))), + STATUS_TIMER_TIMEOUT = ((((STATUS_GROUP_TIMER)*100) + (2))), +} timer_status_e; + + + + +typedef enum +{ + DETECT_HIGH_LVL = 0, + DETECT_LOW_LVL, + DETECT_RISING_EDGE, + DETECT_FALLING_EDGE, + DETECT_DOUBLE_EDGE +} sys_cfg_trigger_e; + + + + +typedef enum +{ + TIMER_NUM0 = 0, + TIMER_NUM1, + TIMER_NUM2, + TIMER_NUM3, + TIMER_NUM_MAX +} timer_num_e; + + + + +typedef enum +{ + GPIO_INT_EXTI_INT0 = 0, + GPIO_INT_EXTI_INT1, + GPIO_INT_EXTI_INT2, + GPIO_INT_EXTI_INT3, + GPIO_INT_EXTI_INT4, + GPIO_INT_EXTI_INT5, + GPIO_INT_EXTI_INT6, + GPIO_INT_EXTI_INT7, + GPIO_INT_MAX +} gpio_int_e; + + +typedef enum _pwm_int_type +{ + PWM_INT_HIGH_OVERFLOW = 0, + PWM_INT_LOW_OVERFLOW, + PWM_INT_TOTAL_OVERFLOW, + PWM_INT_HIGH_DONE, + PWM_INT_LOW_DONE, + PWM_INT_TOTAL_DONE, + PWM_INT_MAX +} pwm_int_type_e; + + + + +typedef enum +{ + I2C_SELECT_0 = 0, + I2C_SELECT_1, +} i2c_select_e; + + + + + +typedef enum _i2c_rate +{ + I2C_RATE_STANDARD = 1, + I2C_RATE_FAST, + I2C_RATE_HIGH, +} i2c_rate_e; + + + + + +typedef enum +{ + I2C_INDEX_0, + I2C_INDEX_1, + I2C_INDEX_2, + I2C_INDEX_MAX +} i2c_index_e; + + + + + +typedef enum +{ + AHB_DMA_CH0, + AHB_DMA_CH1, + AHB_DMA_CH2, + AHB_DMA_CH3, + AHB_DMA_CH4, + AHB_DMA_CH5, + AHB_DMA_CH6, + AHB_DMA_CH7, + AHB_DMA_CH_NUM +} dma_channel_type_e; + + + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} function_state_e; + + + + +typedef enum +{ + CRC_REV_NO_TRANSPOSE = 0, + CRC_REV_ONLY_BITS_TRANSPOSE, + CRC_REV_BOTH_TRANSPOSE, + CRC_REV_ONLY_BYTES_TRANSPOSE, +} crc_reversal_type_e; + + + + +typedef enum +{ + CRC_FXOR_DISABLE = 0, + CRC_FXOR_ENABLE, +} crc_fxor_function_e; + + + + +typedef enum +{ + CRC_16_BIT_PROTOCOL = 0, + CRC_32_BIT_PROTOCOL, +} crc_protocol_type_e; + + + + + + + +# 12 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\common\\tau_log.h" + + + + + + + + + + + + + + + + +# 18 "..\\..\\src\\common\\tau_log.h" +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 38 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" + + + + + + + typedef unsigned int size_t; +# 54 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" + + + + +extern __declspec(__nothrow) void *memcpy(void * __restrict , + const void * __restrict , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + +extern __declspec(__nothrow) void *memmove(void * , + const void * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + +extern __declspec(__nothrow) char *strcpy(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); + + + + + + +extern __declspec(__nothrow) char *strncpy(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + +extern __declspec(__nothrow) char *strcat(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); + + + + + + +extern __declspec(__nothrow) char *strncat(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) int memcmp(const void * , const void * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + +extern __declspec(__nothrow) int strcmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + +extern __declspec(__nothrow) int strncmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + +extern __declspec(__nothrow) int strcasecmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + +extern __declspec(__nothrow) int strncasecmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + +extern __declspec(__nothrow) int strcoll(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + +extern __declspec(__nothrow) size_t strxfrm(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(2))); + + + + + + + + + + + + + + + + + +# 193 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) void *memchr(const void * , int , size_t ) __attribute__((__nonnull__(1))); + + + + + + + + + +# 209 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) char *strchr(const char * , int ) __attribute__((__nonnull__(1))); + + + + + + + + +extern __declspec(__nothrow) size_t strcspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + +# 232 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) char *strpbrk(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + + +# 247 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) char *strrchr(const char * , int ) __attribute__((__nonnull__(1))); + + + + + + + + + +extern __declspec(__nothrow) size_t strspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + +# 270 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" +extern __declspec(__nothrow) char *strstr(const char * , const char * ) __attribute__((__nonnull__(1,2))); + + + + + + + + + +extern __declspec(__nothrow) char *strtok(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(2))); +extern __declspec(__nothrow) char *_strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); + +extern __declspec(__nothrow) char *strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) void *memset(void * , int , size_t ) __attribute__((__nonnull__(1))); + + + + + +extern __declspec(__nothrow) char *strerror(int ); + + + + + + + +extern __declspec(__nothrow) size_t strlen(const char * ) __attribute__((__nonnull__(1))); + + + + + + +extern __declspec(__nothrow) size_t strlcpy(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) size_t strlcat(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + + + + + + + + + + +extern __declspec(__nothrow) void _membitcpybl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpybb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpyhl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpyhb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpywl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitcpywb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovebl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovebb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovehl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovehb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovewl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +extern __declspec(__nothrow) void _membitmovewb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 502 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\string.h" + + + + + +# 19 "..\\..\\src\\common\\tau_log.h" +# 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdarg.h" + + + + + + + + + + + + + + + + + + + +# 27 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdarg.h" + + + + + + + + + + + + +# 57 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdarg.h" + typedef struct __va_list { void *__ap; } va_list; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + typedef va_list __gnuc_va_list; + + + + + + +# 147 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdarg.h" + + + +# 20 "..\\..\\src\\common\\tau_log.h" +# 21 "..\\..\\src\\common\\tau_log.h" + + + + +# 31 "..\\..\\src\\common\\tau_log.h" + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef enum +{ + kLOG_LEVEL_DBG = 0, + kLOG_LEVEL_INF, + kLOG_LEVEL_ERR, + kLOG_LEVEL_NONE +} log_level_e; + + + + + +typedef enum +{ + LOG_PORT_UART0, + LOG_PORT_UART1, + LOG_PORT_SWD, + LOG_PORT_UNKNOWN +} log_port_e; + + + + + + + + + + + + + + +void tau_log_init(uint32_t baud_rate, log_port_e log_port); + + + + + + + +void tau_log_printf(log_level_e log_lv, const char *fmt, ...); + +# 13 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\common\\tau_operations.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# 14 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 15 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\common\\tau_delay.h" + + + + + + + + + + + + + + + +# 19 "..\\..\\src\\common\\tau_delay.h" + + + + + + +void delayMs(uint32_t ms); + + + + + + +void delayUs(uint32_t us); + +# 16 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\sdk\\include\\hal_dsi_rx_ctrl.h" + + + + + + + + + + + + + + + +# 1 "..\\..\\src\\common\\tau_dsi_datatype.h" + + + + + + + + + + + + + + + + +# 18 "..\\..\\src\\common\\tau_dsi_datatype.h" + + + + + + + + + + + + +typedef enum +{ + DSI_ACK_DT_ERROR = 0x02, + DSI_ACK_DT_EOTP = 0x08, + DSI_ACK_DT_GEN_SHORT_RESPONSE_1B = 0x11, + DSI_ACK_DT_GEN_SHORT_RESPONSE_2B = 0x12, + DSI_ACK_DT_GEN_LONG_RESPONSE = 0x1A, + DSI_ACK_DT_DCS_LONG_RESPONSE = 0x1C, + DSI_ACK_DT_DCS_SHORT_RESPONSE_1B = 0x21, + DSI_ACK_DT_DCS_SHORT_RESPONSE_2B = 0x22, + DSI_ACK_DT_MAX +} dsi_ack_data_type_e; + + + + +typedef enum +{ + DSI_RECV_DT_PPS = 0x0A, + DSI_RECV_DT_GEN_WRITE_1B = 0x13, + DSI_RECV_DT_GEN_WRITE_2B = 0x23, + DSI_RECV_DT_GEN_READ_0B = 0x04, + DSI_RECV_DT_GEN_READ_1B = 0x14, + DSI_RECV_DT_GEN_READ_2B = 0x24, + DSI_RECV_DT_DCS_WRITE_0B = 0x05, + DSI_RECV_DT_DCS_WRITE_1B = 0x15, + DSI_RECV_DT_DCS_READ_0B = 0x06, + DSI_RECV_DT_GEN_WRITE_LONG = 0x29, + DSI_RECV_DT_DCS_WRITE_LONG = 0x39, + DSI_RECV_DT_MAX +} dsi_data_type_e; + +typedef enum +{ + DCS_ENTER_IDLE_MODE = 0x39, + DCS_ENTER_INVERT_MODE = 0x21, + DCS_ENTER_NORMAL_MODE = 0x13, + DCS_ENTER_PARTIAL_MODE = 0x12, + DCS_ENTER_SLEEP_MODE = 0x10, + DCS_EXIT_IDLE_MODE = 0x38, + DCS_EXIT_INVERT_MODE = 0x20, + DCS_EXIT_SLEEP_MODE = 0x11, + DCS_GET_3D_CONTROL = 0x3F, + DCS_GET_ADDRESS_MODE = 0x0B, + DCS_GET_BLUE_CHANNEL = 0x08, + DCS_GET_COMPRESSION_MODE = 0x03, + DCS_GET_DIAGNOSTIC_RESULT = 0x0F, + DCS_GET_DISPLAY_MODE = 0x0D, + DCS_GET_GREEN_CHANNEL = 0x07, + DCS_GET_PIXEL_FORMAT = 0x0C, + DCS_GET_POWER_MODE = 0x0A, + DCS_GET_RED_CHANNEL = 0x06, + DCS_GET_SCANLINE = 0x45, + DCS_GET_SIGNAL_MODE = 0x0E, + DCS_NOP = 0x00, + DCS_READ_DDB_CONTINUE = 0xA8, + DCS_READ_DDB_START = 0xA1, + DCS_READ_MEMORY_CONTINUE = 0x3E, + DCS_READ_MEMORY_START = 0x2E, + DCS_SET_3D_CONTROL = 0x3D, + DCS_SET_ADDRESS_MODE = 0x36, + DCS_SET_COLUMN_ADDRESS = 0x2A, + DCS_SET_DISPLAY_OFF = 0x28, + DCS_SET_DISPLAY_ON = 0x29, + DCS_SET_GAMMA_CURVE = 0x26, + DCS_SET_PAGE_ADDRESS = 0x2B, + DCS_SET_PARTIAL_COLUMNS = 0x31, + DCS_SET_PARTIAL_ROWS = 0x30, + DCS_SET_PIXEL_FORMAT = 0x3A, + DCS_SET_SCROLL_AREA = 0x33, + DCS_SET_SCROLL_START = 0x37, + DCS_SET_TEAR_OFF = 0x34, + DCS_SET_TEAR_ON = 0x35, + DCS_SET_TEAR_SCANLINE = 0x44, + DCS_SET_VSYNC_TIMING = 0x40, + DCS_SOFT_RESET = 0x01, + DCS_WRITE_LUT = 0x2D, + DCS_WRITE_MEMORY_CONTINUE = 0x3C, + DCS_WRITE_MEMORY_START = 0x2C +} dsi_dcs_cmd_type_e; + + + + +typedef enum +{ + DSI_DATA_VIDEO_MODE = 0, + DSI_DATA_CMD_MODE = 1, + DSI_DATA_MODE_MAX +} dsi_video_data_mode_e; + + + + +typedef enum +{ + DSI_VC_0 = 0, + DSI_VC_1 = 1, + DSI_VC_2 = 2, + DSI_VC_3 = 3, + DSI_VC_MAX +} dsi_virtual_channel_e; + + + + +typedef enum +{ + DSI_FRAME_RATE_60HZ = 0, + DSI_FRAME_RATE_90HZ = 1, + DSI_FRAME_RATE_120HZ = 2, + DSI_FRAME_RATE_144HZ = 3, + DSI_FRAME_RATE_160HZ = 4, + DSI_FRAME_RATE_MAX +} dsi_video_frame_rate_e; + + + + +typedef enum +{ + DSI_RGB565 = 1, + DSI_RGB666 = 2, + DSI_RGB666_LOOSELY = 3, + DSI_RGB888 = 4, + DSI_RGB10_10_10 = 5, + DSI_RGB12_12_12 = 6, + DSI_YCbCr422_16 = 7, + DSI_PENTILE_16 = DSI_YCbCr422_16, + DSI_YCbCr422_20_LOOSELY = 8, + DSI_YCbCr422_24 = 9, + DSI_YCbCr420_12 = 10, + DSI_DSC_STREAM = 11, + DSI_COLOR_CODE_MAX +} dsi_color_code_e; + + + + +typedef enum +{ + DPI_ENDIAN_RGB = 0, + DPI_ENDIAN_BGR +} dsi_endianness_e; + + + + +typedef enum +{ + DSI_LANE_1 = 1, + DSI_LANE_2 = 2, + DSI_LANE_3 = 3, + DSI_LANE_4 = 4, + DSI_LANE_NUME_MAX +} dsi_lane_nume_e; + + + + +typedef enum +{ + DSI_NONBURST_PULSE = 0, + DSI_NONBURST_EVENT = 1, + DSI_BURST_MODE = 2, + DSI_VIDEO_MODE_MAX +} dsi_video_mode_type_e; + + + + +typedef enum +{ + DSI_CMD_TX_HS = 0, + DSI_CMD_TX_LP = 1 +} dsi_tx_cmd_tx_type_e; + + + + +typedef enum +{ + VIDOE_ROT_ANGLE_0 = 0, + VIDOE_ROT_ANGLE_90 = 1, + VIDOE_ROT_ANGLE_180 = 2, + VIDOE_ROT_ANGLE_270 = 3, + VIDOE_ROT_ANGLE_MAX +} video_rotate_angle_e; + + + + + + + + + +typedef enum +{ + RX_LANE_SWAP_0123 = 0x0, + RX_LANE_SWAP_3210 = 0x1, + RX_LANE_SWAP_2103 = 0x2, + RX_LANE_SWAP_DEFAULT_ORDER = 0x2, + RX_LANE_SWAP_3012 = 0x3, + RX_LANE_SWAP_MAX +} dsi_rx_lane_swap_e; + + + + + + + +typedef enum +{ + RX_LANE_0_PN_SWAP = 0x1, + RX_LANE_1_PN_SWAP = 0x2, + RX_LANE_2_PN_SWAP = 0x4, + RX_LANE_3_PN_SWAP = 0x8, + RX_LANE_CLK_PN_SWAP = 0x10 +} dsi_rx_lane_pn_swap_e; + + + + +typedef enum +{ + ERR_HANDLE_NONE = 0, + ERR_HANDLE_L1 = 1, + ERR_HANDLE_L2 = 2, + ERR_HANDLE_L3 = 3, + ERR_HANDLE_MAX +} hal_err_handle_level_e; + + + + +typedef enum +{ + FC_AUTO_MODE = 0, + FC_V2V_NORMAL_MODE = 1, + FC_V2C_NORMAL_MODE = 2, + FC_C2V_NORMAL_MODE = 3, + FC_C2C_NORMAL_MODE = 4, + FC_PRO_MOTION_MODE = 6, + FC_PRO_MOTION_MODE_2 = 5, + FC_PRO_MOTION_WITH_PU_MODE = 7, + FC_V2V_AUTO_SYCN_MODE = 8, + FC_V2V_DIRECT_MODE = 9, + FC_MODE_MAX +} flow_control_mode_e; + + + + +typedef struct +{ + uint16_t top; + uint16_t bottom; + uint16_t left; + uint16_t right; + _Bool enable; +} pic_edge_info_t; + + + + +typedef struct +{ + uint32_t src_w; + uint32_t src_h; + uint32_t dst_w; + uint32_t dst_h; + dsi_video_frame_rate_e src_frate; + dsi_video_data_mode_e src_mode; + dsi_video_data_mode_e dst_mode; + uint16_t pn_swap; +} dsi_base_trans_info_t; + + + + +typedef struct +{ + _Bool mirror_en; + _Bool pu_optimize; + video_rotate_angle_e rot_angle; + flow_control_mode_e flow_control_mode; + pic_edge_info_t crop_info; + pic_edge_info_t blank_info; + _Bool bw_optimize; + uint8_t pq_type; +} dsi_base_extra_info_t; + + + + +typedef struct +{ + uint32_t coef_c00; + uint32_t coef_c01; + uint32_t coef_c02; + uint32_t coef_c10; + uint32_t coef_c11; + uint32_t coef_c12; + uint32_t coef_c20; + uint32_t coef_c21; + uint32_t coef_c22; +} ccm_coef_t; + + + + +typedef enum +{ + HIGHT_PERFORMAN_NONE = 0, + HIGHT_PERFORMAN_L1 = 1, + HIGHT_PERFORMAN_L2 = 2, + HIGHT_PERFORMAN_MAX +} hight_performan_mode_e; + + + + +typedef struct +{ + uint16_t edgemedslope; + uint16_t desatslope; +} dsi_tx_fc_t; + + + + +typedef struct +{ + _Bool y_enh_method; + uint8_t enhance_str; + uint16_t enhance_slope; + uint16_t boundscale_low; + uint16_t boundscale_high; +} dsi_tx_edge_enh_t; + + + + +typedef struct +{ + uint8_t edge_thr; + _Bool use_large_kernel; +} dsi_tx_edge_dect_t; + + + + +typedef struct +{ + int8_t brightness; + uint16_t contrast; + uint16_t saturation; +} dsi_tx_bcs_t; + + + + +typedef struct +{ + uint32_t st_line; + uint32_t st_col; + uint32_t end_line; + uint32_t end_col; + uint8_t value_r; + uint8_t value_g; + uint8_t value_b; +} dsi_tx_par_dis_t; + +# 17 "..\\..\\src\\sdk\\include\\hal_dsi_rx_ctrl.h" +# 18 "..\\..\\src\\sdk\\include\\hal_dsi_rx_ctrl.h" +# 19 "..\\..\\src\\sdk\\include\\hal_dsi_rx_ctrl.h" + + + + + + + + + +typedef struct hal_dcs_execute_entry_t hal_dcs_execute_entry_t; + +typedef struct hal_dcs_packet_t hal_dcs_packet_t; + +typedef struct hal_dsi_rx_ctrl_handle_t hal_dsi_rx_ctrl_handle_t; + + +typedef _Bool (*hal_dsi_rx_ctrl_dcs_execute)(hal_dsi_rx_ctrl_handle_t *rx_handle, hal_dcs_packet_t *dcs_packet); + + +typedef _Bool (*hal_dsi_rx_ctrl_read_entry)(uint8_t data_type, uint8_t dcs_cmd, uint8_t param); + + +typedef _Bool (*hal_dsi_rx_ctrl_pps_entry)(uint8_t *pps, uint8_t size, uint32_t pic_width, uint32_t pic_height); + + + + +typedef enum hal_rx_event_e +{ + HAL_RX_FS_EVENT = 0x1, + HAL_RX_LINE_EVENT = 0x2, + HAL_RX_END_EVENT = 0x4, +} hal_rx_event_e; + + + + + + +typedef enum +{ + RX_FLT_OPT_0 = 0, + RX_FLT_OPT_1 = 1, + RX_FLT_OPT_2 = 2, + RX_FLT_OPT_3 = 3, + RX_FLT_OPT_4 = 4, + RX_FLT_OPT_5 = 5, + RX_FLT_OPT_6 = 6, + RX_FLT_OPT_7 = 7, + RX_FLT_OPT_8 = 8, + RX_FLT_OPT_9 = 9, + RX_FLT_OPT_10 = 10, + RX_FLT_LINEAR = 11, + RX_FLT_MAX +} hal_dsi_rx_pq_filter_e; + + +typedef void (*hal_dsi_rx_ctrl_event_entry)(hal_rx_event_e event, void *data); + + + + +typedef struct hal_dsi_rx_ctrl_handle_t +{ + dsi_base_trans_info_t base_info; + dsi_base_extra_info_t extra_info; + dsi_color_code_e rx_color_mode; + dsi_lane_nume_e rx_lanes; + dsi_video_mode_type_e rx_nonburst_models; + _Bool compress_en; + uint32_t rx_hsclk_rate; + uint8_t rx_dsc_pps[128]; + const hal_dcs_execute_entry_t *cus_dcs_entry_table; + hal_dsi_rx_ctrl_read_entry rx_dcs_read_entry; + hal_dsi_rx_ctrl_pps_entry pps_update_entry; + _Bool used; + hal_err_handle_level_e err_handler_level; + uint8_t rx_strength; + hight_performan_mode_e hight_performan_mode; + dsi_rx_lane_swap_e rx_lane_swap; + hal_dsi_rx_pq_filter_e rx_pq_index; +} hal_dsi_rx_ctrl_handle_t; + + + + +typedef struct hal_dcs_execute_entry_t +{ + uint32_t dcs_command; + hal_dsi_rx_ctrl_dcs_execute execute_func; + _Bool immediately_func; +} hal_dcs_execute_entry_t; + + + + +typedef struct hal_dcs_packet_t +{ + uint32_t data_type; + uint32_t dcs_command; + uint32_t param_length; + uint8_t *packet_param; + uint16_t crc_data; + const hal_dcs_execute_entry_t *dcs_execute_entry; +} hal_dcs_packet_t; + + + + +typedef struct +{ + uint32_t ipi_pg_hsa; + uint32_t ipi_pg_hbp; + uint32_t ipi_pg_hfp; + uint32_t ipi_pg_vsa; + uint32_t ipi_pg_vbp; + uint32_t ipi_pg_vfp; + uint32_t frame_rate; +} hal_dsi_rx_ipi_pg_t; + + + + + +typedef enum +{ + HAL_RX_DCS_FILTER_0 = 0x0, + HAL_RX_DCS_FILTER_1 = 0x1, + HAL_RX_DCS_FILTER_2 = 0x2, + HAL_RX_DCS_FILTER_3 = 0x3, + HAL_RX_DCS_FILTER_4 = 0x4, + HAL_RX_DCS_FILTER_5 = 0x5, + HAL_RX_DCS_FILTER_6 = 0x6, + HAL_RX_DCS_FILTER_7 = 0x7, + HAL_RX_DCS_FILTER_8 = 0x8, + HAL_RX_DCS_FILTER_9 = 0x9, + HAL_RX_DCS_FILTER_A = 0xA, + HAL_RX_DCS_FILTER_B = 0xB, + HAL_RX_DCS_FILTER_MAX +} hal_rx_dcs_filter_sel_e; + + + + + +typedef enum +{ + HAL_RX_QRESP_CODE0 = 0, + HAL_RX_QRESP_CODE1 = 1, + HAL_RX_QRESP_CODE2 = 2, + HAL_RX_QRESP_CODE3 = 3, + HAL_RX_QRESP_CODE4 = 4, + HAL_RX_QRESP_CODE5 = 5, + HAL_RX_QRESP_CODE6 = 6, + HAL_RX_QRESP_CODE7 = 7, + HAL_RX_QRESP_MAX +} hal_rx_dcs_qresp_e; + + + + +typedef enum +{ + PENTILE_SRC_FORMAT_RGB = 0x0, + PENTILE_SRC_FORMAT_BGR = 0x1, + PENTILE_SRC_FORMAT_RGBG_BGRG = 0x8, + PENTILE_SRC_FORMAT_GBGR_GRGB = 0x9, + PENTILE_SRC_FORMAT_BGRG_RGBG = 0xA, + PENTILE_SRC_FORMAT_GRGB_GBGR = 0xB, + PENTILE_SRC_FORMAT_RGBG_RGBG = 0xC, + PENTILE_SRC_FORMAT_GBGR_GBGR = 0xD, + PENTILE_SRC_FORMAT_BGRG_BGRG = 0xE, + PENTILE_SRC_FORMAT_GRGB_GRGB = 0xF, + PENTILE_SRC_FORMAT_MAX +} pentile_src_format_e; + + + + +typedef enum +{ + RX_CLK_100M = 0, + RX_CLK_150M = 1, + RX_CLK_200M = 2, + RX_CLK_300M = 3, + RX_CLK_40M = 4, + RX_CLK_80M = 5, + RX_CLK_MAX +} hal_rx_clk_e; + + + + +typedef enum +{ + PQ_TYPE_DEFAULT = 0x0, + PQ_TYPE_LIMIT = 0x1, + PQ_TYPE_MAX +} pq_type_e; + + + + +typedef enum +{ + LINE_WEIGHT_FINE = 0, + LINE_WEIGHT_MEDIUM = 1, + LINE_WEIGHT_BOLD = 2, + LINE_WEIGHT_MAX +} line_weight_e; + + + + + + + + + + + + + + +hal_dsi_rx_ctrl_handle_t *hal_dsi_rx_ctrl_create_handle(void); + + + + + + +_Bool hal_dsi_rx_ctrl_release_handle(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + + + + + + + + +_Bool hal_dsi_rx_ctrl_pre_init_pps(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint8_t pps[], uint32_t pps_size); + + + + + + +_Bool hal_dsi_rx_ctrl_init(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + + + + + + +_Bool hal_dsi_rx_ctrl_deinit(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + + + + + + +_Bool hal_dsi_rx_ctrl_start(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + + + + + + +_Bool hal_dsi_rx_ctrl_restart(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + + + + + + +_Bool hal_dsi_rx_ctrl_stop(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + + + + + + +_Bool hal_dsi_rx_ctrl_set_rx_clk(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_rx_clk_e rxbr_clk); + + + + + + + + + + +_Bool hal_dsi_rx_ctrl_send_ack_cmd(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, dsi_ack_data_type_e data_type, dsi_virtual_channel_e vc, uint8_t cmd_count, ...); + + + + + + + + + + + + +_Bool hal_dsi_rx_ctrl_ack_short_cmd(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint8_t data_size, uint8_t data[]); + + + + + + + + + + + + + +_Bool hal_dsi_rx_ctrl_ack_long_cmd(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint32_t data_size, uint8_t data[]); + + + + + + +_Bool hal_dsi_rx_ctrl_dcs_async_handler(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + + + + + + + + + +_Bool hal_dsi_rx_ctrl_set_hw_cmd_filter(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, + hal_rx_dcs_filter_sel_e filter_number, + uint32_t cmd_start, uint32_t cmd_end); + + + + + + + + + +_Bool hal_dsi_rx_ctrl_enable_test_pattern(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint8_t pg_orient, _Bool enable, int frame_rate); + + + + + + + +uint32_t hal_dsi_rx_ctrl_get_max_ret_size(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + + + + + + +_Bool hal_dsi_rx_ctrl_get_compressen_en(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + + + + + + +_Bool hal_dsi_rx_ctrl_toggle_resolution(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + + + + + + + +_Bool hal_dsi_rx_ctrl_set_cus_esc_clk(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint32_t esc_clk); + + + + + + + +_Bool hal_dsi_rx_ctrl_set_auto_hw_filter(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, _Bool enable); + + + + + + +_Bool hal_dsi_rx_ctrl_toggle_input_frame_rate(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, dsi_video_frame_rate_e frame_rate); + + + + + + + + +void hal_dsi_rx_ctrl_register_write_cmd_entry(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_dsi_rx_ctrl_dcs_execute execute_func); + + + + + + + + + + + + + +_Bool hal_dsi_rx_ctrl_set_auto_ack(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_rx_dcs_qresp_e qresp_number, dsi_ack_data_type_e data_type, uint32_t cmd_code, uint8_t cmd_count, ...); + + + + + + + + + + +void hal_dsi_rx_ctrl_draw_mode_init(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, _Bool draw_en, _Bool pxl_init_en, dsi_color_code_e color_mode, uint32_t init_value); + + + + + + + + + + + +void hal_dsi_rx_ctrl_set_pixel_data(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, int x, int y, uint8_t red_data, uint8_t green_data, uint8_t blue_data); + + + + + + + + + +void hal_dsi_rx_ctrl_force_video_crtl(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, _Bool enable, dsi_color_code_e frc_vid_code); + + + + + + + + + + +void hal_dsi_rx_ctrl_register_callback(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_dsi_rx_ctrl_event_entry event_cb, uint32_t event_mask, _Bool enable, void *user_data); + + + + + + + +void hal_dsi_rx_ctrl_set_check_crc(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, _Bool enable); + + + + + + +void hal_dsi_rx_ctrl_set_log_level(log_level_e rx_drv_level); + + + + + + + + + + + +void hal_dsi_rx_ctrl_draw_line(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint8_t red_data, uint8_t green_data, uint8_t blue_data, line_weight_e line_weight); + + + + + + + +void hal_dsi_rx_ctrl_set_cap_pixel_pos(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x0, uint16_t y0); + + + + + +uint32_t hal_dsi_rx_ctrl_get_cap_pixel_color(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + +# 17 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\sdk\\include\\hal_dsi_tx_ctrl.h" + + + + + + + + + + + + + + + +# 17 "..\\..\\src\\sdk\\include\\hal_dsi_tx_ctrl.h" +# 18 "..\\..\\src\\sdk\\include\\hal_dsi_tx_ctrl.h" +# 1 "..\\..\\src\\sdk\\include\\hal_gpio.h" + + + + + + + + + + + + + + + +# 17 "..\\..\\src\\sdk\\include\\hal_gpio.h" +# 18 "..\\..\\src\\sdk\\include\\hal_gpio.h" + + + + + + + +typedef enum +{ + + IO_PAD_GPIO0 = 0, + IO_PAD_GPIO1, + IO_PAD_GPIO2, + IO_PAD_GPIO3, + IO_PAD_GPIO4, + IO_PAD_GPIO5, + IO_PAD_GPIO6, + IO_PAD_GPIO7, + IO_PAD_GPIO8, + IO_PAD_GPIO9, + IO_PAD_GPIO10, + IO_PAD_GPIO11, + IO_PAD_GPIO12, + IO_PAD_GPIO13, + IO_PAD_GPIO14, + IO_PAD_GPIO15, + IO_PAD_GPIO16, + IO_PAD_GPIO17, + IO_PAD_GPIO18, + IO_PAD_GPIO19, + IO_PAD_GPIO20, + IO_PAD_GPIO21, + IO_PAD_GPIO22, + IO_PAD_GPIO23, + IO_PAD_GPIO24, + IO_PAD_GPIO25, + + + IO_PAD_AP_SPIS_MISO = IO_PAD_GPIO0, + IO_PAD_AP_SPIS_MOSI = IO_PAD_GPIO1, + IO_PAD_AP_INT = IO_PAD_GPIO2, + IO_PAD_AP_TE = IO_PAD_GPIO3, + IO_PAD_AP_SWIRE = IO_PAD_GPIO4, + IO_PAD_TD_SPIM_MISO = IO_PAD_GPIO5, + IO_PAD_TD_SPIM_MOSI = IO_PAD_GPIO6, + IO_PAD_TD_RSTN = IO_PAD_GPIO7, + IO_PAD_AP_PWMEN = IO_PAD_GPIO8, + IO_PAD_AP_SPIS_CLK = IO_PAD_GPIO9, + IO_PAD_AP_SPIS_CSN = IO_PAD_GPIO10, + IO_PAD_TD_FC_CLK = IO_PAD_GPIO11, + IO_PAD_TD_FC_CSN = IO_PAD_GPIO12, + IO_PAD_TD_FC_IO0 = IO_PAD_GPIO13, + IO_PAD_TD_FC_IO1 = IO_PAD_GPIO14, + IO_PAD_SWD_CLK = IO_PAD_GPIO15, + IO_PAD_SWD_DIO = IO_PAD_GPIO16, + IO_PAD_AP_RSTN = IO_PAD_GPIO17, + IO_PAD_UART0_TX = IO_PAD_GPIO18, + IO_PAD_TD_SPIM_CLK = IO_PAD_GPIO19, + IO_PAD_TD_SPIM_CSN = IO_PAD_GPIO20, + IO_PAD_AP_TPRSTN = IO_PAD_GPIO21, + IO_PAD_TD_INT = IO_PAD_GPIO22, + IO_PAD_TD_TP_RESX = IO_PAD_GPIO23, + IO_PAD_UART1_TX = IO_PAD_GPIO24, + IO_PAD_UART0_RX = IO_PAD_GPIO25, + + IO_PAD_MAX, + + + + IO_PIN_1 = IO_PAD_SWD_CLK, + IO_PIN_2 = IO_PAD_UART0_TX, + IO_PIN_3 = IO_PAD_SWD_DIO, + IO_PIN_4 = IO_PAD_TD_SPIM_MOSI, + IO_PIN_5 = IO_PAD_TD_SPIM_CLK, + IO_PIN_6 = IO_PAD_TD_SPIM_CSN, + IO_PIN_7 = IO_PAD_TD_SPIM_MISO, + IO_PIN_8 = IO_PAD_TD_RSTN, + IO_PIN_9 = IO_PAD_TD_FC_CSN, + IO_PIN_10 = IO_PAD_TD_FC_CLK, + IO_PIN_11 = IO_PAD_TD_FC_IO0, + IO_PIN_12 = IO_PAD_TD_FC_IO1, + IO_PIN_13 = IO_PAD_TD_TP_RESX, + IO_PIN_14 = IO_PAD_UART1_TX, + IO_PIN_15 = IO_PAD_AP_SWIRE, + IO_PIN_16 = IO_PAD_AP_INT, + IO_PIN_17 = IO_PAD_AP_PWMEN, + IO_PIN_18 = IO_PAD_AP_TPRSTN, + + IO_PIN_29 = IO_PAD_AP_TE, + IO_PIN_30 = IO_PAD_AP_SPIS_MISO, + IO_PIN_31 = IO_PAD_AP_SPIS_CSN, + IO_PIN_32 = IO_PAD_AP_SPIS_CLK, + IO_PIN_33 = IO_PAD_AP_SPIS_MOSI, + IO_PIN_34 = IO_PAD_AP_RSTN, + IO_PIN_35 = IO_PAD_TD_INT, + IO_PIN_36 = IO_PAD_UART0_RX, + +} io_pad_e; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef enum +{ + PIN1_MODE_SWDCLK = 0, + PIN1_MODE_GPIO15 = 2, +} pin1_mode_e; + + + + + +typedef enum +{ + PIN2_MODE_UART0_TX = 0, + PIN2_MODE_PWMO = 1, + PIN2_MODE_GPIO18 = 2, + PIN2_MODE_PWMI = 3, + PIN2_MODE_TEAR1 = 4, +} pin2_mode_e; + + + + +typedef enum +{ + PIN3_MODE_SWDIO = 0, + PIN3_MODE_GPIO16 = 2, +} pin3_mode_e; + + + + + +typedef enum +{ + PIN4_MODE_SPIM_MOSI = 0, + PIN4_MODE_I2C02_SDA = 1, + PIN4_MODE_GPIO6 = 2, + PIN4_MODE_UART0_TX = 3, +} pin4_mode_e; + + + + +typedef enum +{ + PIN5_MODE_SPIM_SCLK = 0, + PIN5_MODE_I2C1_SCL = 1, + PIN5_MODE_GPIO19 = 2, +} pin5_mode_e; + + + + +typedef enum +{ + PIN6_MODE_SPIM_CSN = 0, + PIN6_MODE_I2C1_SDA = 1, + PIN6_MODE_GPIO20 = 2, +} pin6_mode_e; + + + + +typedef enum +{ + PIN7_MODE_SPIM_MISO = 0, + PIN7_MODE_I2C02_SCL = 1, + PIN7_MODE_GPIO5 = 2, +} pin7_mode_e; + + + + +typedef enum +{ + PIN8_MODE_GPIO7 = 2, + PIN8_MODE_I2C02_SDA = 3, +} pin8_mode_e; + + + + +typedef enum +{ + PIN9_MODE_TSPIS_CSN = 0, + PIN9_MODE_GPIO12 = 2, +} pin9_mode_e; + + + + +typedef enum +{ + PIN10_MODE_TSPIS_CLK = 0, + PIN10_MODE_GPIO11 = 2, +} pin10_mode_e; + + + + + +typedef enum +{ + PIN11_MODE_TSPIS_IO0 = 0, + PIN11_MODE_GPIO13 = 2, + PIN11_MODE_I2C02_SDA = 3, +} pin11_mode_e; + + + + +typedef enum +{ + PIN12_MODE_TSPIS_IO1 = 0, + PIN12_MODE_GPIO14 = 2, + PIN12_MODE_I2C02_SCL = 3, +} pin12_mode_e; + + + + +typedef enum +{ + PIN13_MODE_GPIO23 = 2, + PIN13_MODE_PWMO = 3, + PIN13_MODE_UART1_RX = 4, +} pin13_mode_e; + + + + +typedef enum +{ + PIN14_MODE_GPIO24 = 2, + PIN14_MODE_UART0_RX = 3, + PIN14_MODE_UART1_TX = 4, +} pin14_mode_e; + + + + + + +typedef enum +{ + PIN15_MODE_SWIRE = 0, + PIN15_MODE_PWMO = 1, + PIN15_MODE_GPIO4 = 2, +} pin15_mode_e; + + + + +typedef enum +{ + PIN16_MODE_GPIO2 = 2, +} pin16_mode_e; + + + + +typedef enum +{ + PIN17_MODE_UART0_RX = 1, + PIN17_MODE_GPIO8 = 2, + PIN17_MODE_PWMO = 3, +} pin17_mode_e; + + + + +typedef enum +{ + PIN18_MODE_UART0_RX = 0, + PIN18_MODE_GPIO21 = 2, + PIN18_MODE_I2C02_SCL = 3, +} pin18_mode_e; + + + + + + + +typedef enum +{ + PIN29_MODE_JTAG_TRSTN = 0, + PIN29_MODE_TEAR = 1, + PIN29_MODE_GPIO3 = 2, +} pin29_mode_e; + + + + + +typedef enum +{ + PIN30_MODE_JTAG_TDO = 0, + PIN30_MODE_SPIS_MISO = 1, + PIN30_MODE_GPIO0 = 2, + PIN30_MODE_UART0_RX = 3, + PIN30_MODE_I2C1_SCL = 6, +} pin30_mode_e; + + + + +typedef enum +{ + PIN31_MODE_JTAG_TMS = 0, + PIN31_MODE_SPIS_CSN = 1, + PIN31_MODE_GPIO10 = 2, + PIN31_MODE_I2C02_SDA = 3, +} pin31_mode_e; + + + + +typedef enum +{ + PIN32_MODE_JTAG_TCK = 0, + PIN32_MODE_SPIS_SCLK = 1, + PIN32_MODE_GPIO9 = 2, + PIN32_MODE_I2C02_SCL = 3, +} pin32_mode_e; + + + + +typedef enum +{ + PIN33_MODE_JTAG_TDI = 0, + PIN33_MODE_SPIS_MOSI = 1, + PIN33_MODE_GPIO1 = 2, + PIN33_MODE_UART0_TX = 3, + PIN33_MODE_I2C1_SDA_0 = 6, +} pin33_mode_e; + + + + +typedef enum +{ + PIN34_MODE_GPIO17 = 2, +} pin34_mode_e; + + + + + +typedef enum +{ + PIN35_MODE_GPIO22 = 2, +} pin35_mode_e; + + + + + +typedef enum +{ + PIN36_MODE_UART0_RX = 0, + PIN36_MODE_PWMO = 1, + PIN36_MODE_GPIO25 = 2, +} pin36_mode_e; + + + + + + + +typedef enum +{ + IO_MODE_INTER_FC_CLK = 0, + IO_MODE_TSPIS_CLK_EN = 2, +} pad_sfc_clk_mode_e; + + + + +typedef enum +{ + IO_MODE_INTER_FC_CSN = 0, + IO_MODE_TSPIS_CSN_EN = 2, +} pad_sfc_csn_mode_e; + + + + +typedef enum +{ + IO_MODE_INTER_FC_IO0 = 0, + IO_MODE_TSPIS_IO0_EN = 2, +} pad_sfc_io0_mode_e; + + + + +typedef enum +{ + IO_MODE_INTER_FC_IO1 = 0, + IO_MODE_TSPIS_IO1_EN = 2, +} pad_sfc_io1_mode_e; + + + + +typedef enum +{ + IO_SLEW_RATE_SLOW = 0, + IO_SLEW_RATE_FAST = 1, +} pad_slew_rate_e; + + + + + + + +typedef enum +{ + IO_IOE_INPUT = 0, + IO_IOE_OUTPUT, + IO_IOE_NONE +} gpio_ioe_e; + + + + +typedef enum +{ + IO_LVL_LOW = 0, + IO_LVL_HIGH, + IO_LVL_NONE +} gpio_level_e; + + + + + + + +typedef struct +{ + io_pad_e pad; + uint8_t mode; + gpio_ioe_e ioe; + gpio_level_e lvl; +} io_pad_attr_t; + + + + + + + + + + + + + + +void hal_gpio_init_eint(io_pad_e pad, sys_cfg_trigger_e trig); + + + + + + + + +void hal_gpio_reg_eint_cb(io_pad_e pad, fcb_type cb_func); + + + + + + + +void hal_gpio_ctrl_eint(io_pad_e pad, _Bool state); + + + + + + +gpio_int_e hal_gpio_get_int_type(io_pad_e pad); + + + + + + + +void hal_gpio_init_output(io_pad_e pad, gpio_level_e lvl); + + + + + + + +void hal_gpio_set_output_data(io_pad_e pad, gpio_level_e lvl); + + + + + + +void hal_gpio_init_input(io_pad_e pad); + + + + + + +gpio_level_e hal_gpio_get_input_data(io_pad_e pad); + + + + + + + +void hal_gpio_set_mode(io_pad_e pad, uint8_t mode); + + + + + + +void hal_gpio_set_high_impedance(io_pad_e pad); + + + + + + + + +void hal_gpio_get_pull_state(io_pad_e pad, _Bool *up_enable, _Bool *down_enable); + + + + + + + + +void hal_gpio_set_pull_state(io_pad_e pad, _Bool up_enable, _Bool down_enable); + + + + + + + +void hal_gpio_set_schmitt_trigger(io_pad_e pad, _Bool st_enable); + + + + + + + +void hal_gpio_set_driving_strength(io_pad_e pad, uint8_t strength); + + + + + + + +void hal_gpio_set_slew_rate(io_pad_e pad, pad_slew_rate_e rate); + + + + + + + + +void hal_gpio_set_ap_reset_int(_Bool enable, fcb_type cb_func, sys_cfg_trigger_e trig); + + + + + + + +void hal_gpio_config_pad(io_pad_attr_t *attrs, uint8_t size); + +# 19 "..\\..\\src\\sdk\\include\\hal_dsi_tx_ctrl.h" + + + + + + + + + + + +typedef struct +{ + uint16_t st_col; + uint16_t width; + uint8_t remap_en; + uint8_t blank_en; +} blank_disp_t; + + + + +typedef uint8_t (remap_rule_t)[24]; + + + + +typedef struct +{ + _Bool pentile_enable; + _Bool pentile_reverse_en; + _Bool pentile_24b; + uint32_t rgb_hact; + remap_rule_t *remapl_rule; + remap_rule_t *remapr_rule; + blank_disp_t blank_info0; + blank_disp_t blank_info1; +} dsi_tx_pent_info_t; + + + + + + +typedef enum +{ + ALWAYS_HS = 0, + ONLY_DATA_LANE_AUTO_LP = 1, + CLK_DATA_LANE_AUTO_LP = 2, +} dsi_tx_lane_lp_e; + + + + + +typedef enum +{ + TX_FLT_OPT = 0, + TX_FLT_LINEAR = 1, + TX_FLT_MAX +} hal_dsi_tx_pq_filter_e; + + + + +typedef struct +{ + dsi_base_trans_info_t base_info; + uint32_t dpi_vsa; + uint32_t dpi_vbp; + uint32_t dpi_vfp; + uint32_t dpi_hsa; + uint32_t dpi_hbp; + uint32_t dpi_hfp; + float tx_frame_rate; + uint8_t lane_num; + _Bool used; + _Bool lp_exit_lpdt; + dsi_tx_lane_lp_e tx_lane_lp; + dsi_virtual_channel_e channel_id; + dsi_video_mode_type_e vid_mode; + dsi_tx_cmd_tx_type_e cmd_tx_type; + dsi_tx_pent_info_t pentile_info; + hal_dsi_tx_pq_filter_e tx_pq_index; +} hal_dsi_tx_ctrl_handle_t; + + + + +typedef enum +{ + TE_60HZ_MODE = 0, + TE_USER_MODE = 1, + TE_STOP_MODE = 1, + TE_90HZ_MODE = 2, + TE_120HZ_MODE = 3, + TE_144HZ_MODE = 4, + TE_160HZ_MODE = 5, + TE_MODE_MAX +} te_mode_e; + + + + +typedef enum +{ + TX_VPG_V_COLOR = 0, + TX_VPG_H_COLOR = 1, + TX_VPG_V_BER = 2, + TX_VPG_FLICKER = 3, + TX_VPG_MAX +} dsi_tx_vpg_style_e; + + + + + + +_Bool hal_dsi_tx_ctrl_init(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); + + + + + + +_Bool hal_dsi_tx_ctrl_deinit(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); + + + + + + +hal_dsi_tx_ctrl_handle_t *hal_dsi_tx_ctrl_create_handle(void); + + + + + + +_Bool hal_dsi_tx_ctrl_release_handle(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); + + + + + + +_Bool hal_dsi_tx_ctrl_start(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); + + + + + + +_Bool hal_dsi_tx_ctrl_stop(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); + + + + + + + + + + +void hal_dsi_tx_ctrl_read_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd, uint8_t size, uint8_t *data); + + + + + + + + + + +_Bool hal_dsi_tx_ctrl_vporch_bta_opera(uint8_t data_type, uint8_t cmd, uint8_t size, uint8_t *data); + + + + + + + + + +_Bool hal_dsi_tx_ctrl_write_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd_count, ...); + + + + + + + + + +_Bool hal_dsi_tx_ctrl_write_array_cmd(uint8_t data_type, uint8_t vc, uint8_t size, const uint8_t *data); + + + + + + + +void hal_dsi_tx_ctrl_cmd_mode(_Bool enable); + + + + + + +void hal_dsi_tx_ctrl_set_escape_clock_div(uint32_t esc_clk); + + + + + + + +void hal_dsi_tx_ctrl_set_endianness(dsi_endianness_e endianness); + + + + + + +void hal_dsi_tx_ctrl_set_ccm(ccm_coef_t *ccm); + + + + + + + +void hal_dsi_tx_ctrl_set_edge_dect(dsi_tx_edge_dect_t *edge_dect_para, _Bool edge_dect_en); + + + + + + + +void hal_dsi_tx_ctrl_set_edge_enhance(dsi_tx_edge_enh_t *edge_enh_para, _Bool edge_enh_en); + + + + + + + +void hal_dsi_tx_ctrl_set_fc(dsi_tx_fc_t *fc_para, _Bool fc_en); + + + + + + + +void hal_dsi_tx_ctrl_set_bcs(dsi_tx_bcs_t *bcs_para, _Bool bcs_en); + + + + + + + + +void hal_dsi_tx_ctrl_set_overwrite_rgb(uint8_t R, uint8_t G, uint8_t B); + + + + + + +void hal_dsi_tx_ctrl_overwrite_enable(_Bool enable); + + + + + + + +void hal_dsi_tx_ctrl_partial_disp_enable(_Bool enable, dsi_tx_par_dis_t *par_disp_cfg); + + + + + + + + + +void hal_dsi_tx_ctrl_set_vpg(_Bool vpg_en, dsi_tx_vpg_style_e style, _Bool vpg_hline_adj); + + + + + + + +void hal_dsi_tx_ctrl_set_tear_mode(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle, te_mode_e te); + + + + + + +void hal_dsi_tx_ctrl_gen_a_tear_signal(void); + + + + + + +_Bool hal_dsi_tx_ctrl_gen_a_frame(void); + + + + + + + +_Bool hal_dsi_tx_ctrl_set_cus_sync_line(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle, uint32_t line_num); + + + + + + +uint32_t hal_dsi_tx_ctrl_get_disp_line(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); + +# 18 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\sdk\\include\\hal_swire.h" + + + + + + + + + + + + + + + +# 17 "..\\..\\src\\sdk\\include\\hal_swire.h" +# 18 "..\\..\\src\\sdk\\include\\hal_swire.h" + + + + + + + + + + + + + + + + + + + + + +void hal_swire_init(void); + + + + + + +void hal_swire_deinit(void); + + + + + + + + + +void hal_swire_set_waveform(uint32_t start_time, uint32_t stop_time, + uint32_t high_time, uint32_t low_time); + + + + + + + +void hal_swire_set_pulse(uint32_t pulse); + + + + + + +void hal_swire_enable(_Bool state); + + + + + + + + +void hal_swire_set_timer(timer_num_e index, uint32_t ms, _Bool repeat); + + + + + + +void hal_swire_register_callback(fcb_type cb_func); + +# 19 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\sdk\\include\\hal_timer.h" + + + + + + + + + + + + + + + +# 17 "..\\..\\src\\sdk\\include\\hal_timer.h" +# 18 "..\\..\\src\\sdk\\include\\hal_timer.h" + + + + + + + + + + + + + + + + + + + + + +void hal_timer_init(timer_num_e index); + + + + + + +void hal_timer_deinit(timer_num_e index); + + + + + + + + + + +void hal_timer_start(timer_num_e index, uint32_t ms, fcb_type cb_func, void *data); + + + + + + + + + + +void hal_timer_start_ex(timer_num_e index, uint32_t us, fcb_type cb_func, void *data); + + + + + + +void hal_timer_stop(timer_num_e index); + + + + + + + +void hal_timer_set_repeat(timer_num_e index, _Bool repeat); + + + + + + +timer_status_e hal_timer_get_status(timer_num_e index); + +# 20 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\sdk\\include\\hal_system.h" + + + + + + + + + + + + + + +# 16 "..\\..\\src\\sdk\\include\\hal_system.h" +# 17 "..\\..\\src\\sdk\\include\\hal_system.h" +# 18 "..\\..\\src\\sdk\\include\\hal_system.h" + + + + + + + + + + + +typedef enum +{ + HAL_SYSCLK_80M = 80000000, + HAL_SYSCLK_100M = 100000000, + HAL_SYSCLK_150M = 150000000 +} hal_system_clk_e; + + + + + + + + + + + + + + +void hal_system_init(hal_system_clk_e sysclk); + + + + + + +void hal_system_idle_mode(_Bool disable_systick); + + + + + + +void hal_system_register_systick_cb(fcb_type cb_func); + + + + + + +_Bool hal_system_enable_systick(uint8_t ms); + + + + + + +_Bool hal_system_disable_systick(void); + + + + + + +uint32_t hal_system_get_tick(void); + + + + + + +void hal_system_reset_chip(void); + + + + + + +uint32_t hal_system_get_debug_state(void); + + + + + + +void hal_system_clear_debug_state(void); + + + + + + +_Bool hal_system_updata_sysclk(hal_system_clk_e sysclk); + +# 21 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 22 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\app\\test_cfg_global.h" + + + + + + + + + + + + + + + + + + + +# 31 "..\\..\\src\\app\\test_cfg_global.h" + + + + +# 37 "..\\..\\src\\app\\test_cfg_global.h" + + + +# 23 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\sdk\\include\\hal_pwr.h" + + + + + + + + + + + + + + + +# 17 "..\\..\\src\\sdk\\include\\hal_pwr.h" +# 18 "..\\..\\src\\sdk\\include\\hal_pwr.h" +# 19 "..\\..\\src\\sdk\\include\\hal_pwr.h" + + + + + + + + + + + +typedef enum +{ + PWR_SEL_IOV18 = 0, + PWR_SEL_TP18 = 1, + PWR_SEL_VCC = 2, + PWR_SEL_VDD13CP = 3, +} pwr_main_power_sel_e; + + + + +typedef enum +{ + PWR_SLEEP_IN_NON = 0, + PWR_SLEEP_IN_TP18 = 1, + PWR_SLEEP_IN_VCC = 2, + PWR_SLEEP_IN_VCC_TP18 = 3, + PWR_SLEEP_IN_IOV18 = 4, + PWR_SLEEP_IN_IOV18_TP18 = 5, + PWR_SLEEP_IN_IOV18_VCC = 6, + PWR_SLEEP_IN_IOV18_VCC_TP18 = 7, +} pwr_sleep_power_sel_e; + + + + +typedef enum +{ + WUP_RISING_EDGE = 2, + WUP_FALLING_EDGE = 3 +} pwr_wakeup_trigger_e; + + + + +typedef enum +{ + RF_POWER_ON = 0, + RF_CORE_RST = 1, + RF_WDT_RST = 2, + RF_CHIP_RST = 3, + RF_APRSTN_WAKEUP = 4, + RF_TDINT_WAKEUP = 5 +} pwr_reset_flag_e; + + + + + +typedef enum +{ + PWR_NORMAL_SLEEP_MODE = 0, + PWR_STOP_SLEEP_MODE = 1, + PWR_DEEP_SLEEP_MODE = 2 +} pwr_sleep_mode_e; + + +typedef enum _pwr_hv_ldo_e +{ + HV_LDO_0 = 0, + HV_LDO_1 = 1, + HV_LDO_2 = 2, + HV_LDO_3 = 3, + HV_LDO_4 = 4, + HV_LDO_5 = 5, + HV_LDO_6 = 6, + HV_LDO_7 = 7, + HV_LDO_8 = 8, + HV_LDO_9 = 9, + HV_LDO_10 = 10, + HV_LDO_11 = 11, + HV_LDO_12 = 12, + HV_LDO_13 = 13, + HV_LDO_14 = 14, + HV_LDO_15 = 15, +} pwr_hv_ldo_e; + + +typedef enum _pwr_ldo_13s_e +{ + LDO_13S_0 = 0, + LDO_13S_1 = 1, + LDO_13S_2 = 2, + LDO_13S_3 = 3, + LDO_13S_4 = 4, + LDO_13S_5 = 5, + LDO_13S_6 = 6, + LDO_13S_7 = 7, +} pwr_ldo_13s_e; + + +typedef enum _pwr_ldo_18s_e +{ + LDO_18S_0 = 0, + LDO_18S_1 = 1, + LDO_18S_2 = 2, + LDO_18S_3 = 3, + LDO_18S_4 = 4, + LDO_18S_5 = 5, + LDO_18S_6 = 6, + LDO_18S_7 = 7, +} pwr_ldo_18s_e; + + +typedef enum +{ + PVD_IOVCC = 3, + PVD_VCI = 15, +} pwr_pvd_index_e; + + + + + + + + + + + + + + +void hal_pwr_set_main_power(pwr_main_power_sel_e power_sel); + + + + + + + +_Bool hal_pwr_get_vcc_power_ready(void); + + + + + + +void hal_pwr_set_vcc_enable(_Bool enable); + + + + + + + + +void hal_pwr_set_sleep_mode_power(pwr_sleep_power_sel_e power_sel); + + + + + + + + +_Bool hal_pwr_enter_normal_sleep_mode(void); + + + + + + + + +io_pad_e hal_pwr_enter_stop_sleep_mode(void); + + + + + + + +_Bool hal_pwr_set_stop_sleep_wakeup_pin(io_pad_e pad, pwr_wakeup_trigger_e trig); + + + + + + + + +void hal_pwr_enter_deep_sleep_mode(pwr_wakeup_trigger_e ap_rstn_trig, pwr_wakeup_trigger_e td_int_trig); + + + + + + +_Bool hal_pwr_exit_sleep_mode(void); + + + + + + +pwr_reset_flag_e hal_pwr_get_reset_flag(void); + + + + + + +void hal_pwr_elvcc_ldo_en(_Bool enable); + + + + + + + + + + + + + + + + + + + + + + + +void hal_pwr_elvcc_vol_set(pwr_hv_ldo_e voltage); + + + + + + +void hal_pwr_ldo18s_en(_Bool enable); + + + + + + + + + + + + + + + +void hal_pwr_ldo18s_set(pwr_ldo_18s_e voltage); + + + + + + +void hal_pwr_ldo13s_en(_Bool enable); + + + + + + + + + + + + + + + +void hal_pwr_ldo13s_set(pwr_ldo_13s_e voltage); + + + + + + + + +void hal_pwr_set_pvd(pwr_pvd_index_e index, _Bool enable); + + + + + + + + +void hal_pwr_sw_tp18_en(_Bool enable); + + + +# 24 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\sdk\\include\\hal_pwm.h" + + + + + + + + + + + + + + + +# 17 "..\\..\\src\\sdk\\include\\hal_pwm.h" +# 18 "..\\..\\src\\sdk\\include\\hal_pwm.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + +_Bool hal_pwm_init(uint32_t frequency, uint32_t duty_step); + + + + + + +void hal_pwm_enable(_Bool enable); + + + + + + +void hal_pwm_set_duty(uint32_t duty_ratio); + + + + + + +_Bool hal_pwm_set_elvcc_output(_Bool enable); + + + + + + +void hal_pwm_set_elvcc_capacity(uint8_t capacity); + + + + + + +_Bool hal_pwm_deinit(void); + +# 25 "..\\..\\src\\app\\P8P\\p8p_demo.c" +# 1 "..\\..\\src\\sdk\\include\\hal_crc.h" + + + + + + + + + + + + + + + + + + + +# 21 "..\\..\\src\\sdk\\include\\hal_crc.h" +# 22 "..\\..\\src\\sdk\\include\\hal_crc.h" + + + + + + + + + + + +typedef struct +{ + uint32_t polynomial_value; + uint32_t initial_seed_value; + crc_protocol_type_e crc_protocol; + crc_fxor_function_e crc_foxr; + crc_reversal_type_e crc_reversal_in; + crc_reversal_type_e crc_reversal_out; +} crc_ctrl_handle_t; + + + + +typedef void (*crc_dma_callback)(uint32_t crc_result); + + + + + + + + + + + + + +_Bool hal_crc_init(const crc_ctrl_handle_t *crc_ctrl_handle); + + + + + + +_Bool hal_crc_deinit(void); + + + + + + +_Bool hal_crc_reset(void); + + + + + + + +uint32_t hal_crc_cal(const void *buffer_address, uint32_t buffer_length); + + + + + + + + + +_Bool hal_crc_dma_init(const crc_ctrl_handle_t *crc_ctrl_handle, crc_dma_callback cb_func, const void *buffer_address, uint16_t buffer_length); + + + + + + +_Bool hal_crc_dma_deinit(void); + + + + + + +_Bool hal_crc_dma_start(void); + + + + + + + + +# 26 "..\\..\\src\\app\\P8P\\p8p_demo.c" + + + + + + + + + +# 46 "..\\..\\src\\app\\P8P\\p8p_demo.c" + + + + + + + +# 59 "..\\..\\src\\app\\P8P\\p8p_demo.c" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +static hal_dsi_rx_ctrl_handle_t *g_rx_ctrl_handle = 0; +static hal_dsi_tx_ctrl_handle_t *g_tx_ctrl_handle = 0; + + +static _Bool panel_display_done = 0; +static _Bool sg_system_resume = 0; +static _Bool sg_system_suspend = 0; +static _Bool sg_exit_idle_mode_flag = 0; + +static volatile _Bool g_resolution_change = 0; +static uint32_t pps_renew_flag = 0; +static uint32_t pwr_rst_flag = 0; + +# 143 "..\\..\\src\\app\\P8P\\p8p_demo.c" + +uint16_t rd_51_val,rd_51_val2; + + +static void ap_rstn_pull_high_cb(void *data); +static void ap_rstn_pull_down_cb(void *data); +static void app_mipi_rx_start_cb(void *data); + + + +# 164 "..\\..\\src\\app\\P8P\\p8p_demo.c" + + + + + + +static _Bool ap_dcs_read(uint8_t data_type, uint8_t dcs_cmd, uint8_t param) +{ + if (dcs_cmd == 0x04) + { + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_LONG_RESPONSE, + DSI_VC_0, + 3, 0x0A,0x60,0x20); + } + else if (dcs_cmd == 0xa1) + { + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_LONG_RESPONSE, + DSI_VC_0, + 13, 0x0C,0x21,0x0C,0xC6,0x01,0xF3,0xAA,0x11,0x06,0x2B,0x25,0x21,0xF6); + } + else if (dcs_cmd == 0xDA) + { + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, + DSI_VC_0, + 1, 0x0A); + } + else if (dcs_cmd == 0xDB) + { + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, + DSI_VC_0, + 1, 0x68); + } + else if (dcs_cmd == 0xDC) + { + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, + DSI_VC_0, + 1, 0x07); + } + else if (dcs_cmd == 0xD6) + { + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_LONG_RESPONSE, + DSI_VC_0, + 5, 0xF0, 0xEA, 0x85, 0x61, 0x86); + } + else + { + uint32_t return_size = hal_dsi_rx_ctrl_get_max_ret_size(g_rx_ctrl_handle); + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, + DSI_VC_0, + 1, 0); + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "r[%x] [%d] err!!!!!!\n", "p8p", 221,dcs_cmd, return_size); } while (0); + } + + + return 1; +} + +uint8_t pps[128] = {0x11,0x00,0x00,0x89,0x30,0x80,0x0B,0xB0, + 0x05,0x40,0x00,0xBB,0x02,0xA0,0x02,0xA0, + 0x02,0x00,0x02,0x50,0x00,0x20,0x14,0x39, + 0x00,0x09,0x00,0x0C,0x00,0x85,0x00,0x70, + 0x18,0x00,0x10,0xF0,0x03,0x0C,0x20,0x00, + 0x06,0x0B,0x0B,0x33,0x0E,0x1C,0x2A,0x38, + 0x46,0x54,0x62,0x69,0x70,0x77,0x79,0x7B, + 0x7D,0x7E,0x01,0x02,0x01,0x00,0x09,0x40, + 0x09,0xBE,0x19,0xFC,0x19,0xFA,0x19,0xF8, + 0x1A,0x38,0x1A,0x78,0x1A,0xB6,0x2A,0xF6, + 0x2B,0x34,0x2B,0x74,0x3B,0x74,0x6B,0xF4, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; +uint8_t pps_fhd[128] = {0x11,0x00,0x00,0x89,0x30,0x80,0x08,0xC4, + 0x03,0xF0,0x00,0xBB,0x01,0xF8,0x01,0xF8, + 0x02,0x00,0x01,0xF8,0x00,0x20,0x11,0x82, + 0x00,0x07,0x00,0x0C,0x00,0x85,0x00,0x96, + 0x18,0x00,0x10,0xF0,0x03,0x0C,0x20,0x00, + 0x06,0x0B,0x0B,0x33,0x0E,0x1C,0x2A,0x38, + 0x46,0x54,0x62,0x69,0x70,0x77,0x79,0x7B, + 0x7D,0x7E,0x01,0x02,0x01,0x00,0x09,0x40, + 0x09,0xBE,0x19,0xFC,0x19,0xFA,0x19,0xF8, + 0x1A,0x38,0x1A,0x78,0x1A,0xB6,0x2A,0xF6, + 0x2B,0x34,0x2B,0x74,0x3B,0x74,0x6B,0xF4, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; + + + + +static _Bool pps_update_handle(uint8_t *pps, uint8_t size, uint32_t pic_width, uint32_t pic_height) +{ + + + + + + + + if (pic_width != g_rx_ctrl_handle->base_info.src_w || pic_height != g_rx_ctrl_handle->base_info.src_h) + { + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_USER_MODE); + + g_rx_ctrl_handle->base_info.src_w = pic_width; + g_rx_ctrl_handle->base_info.src_h = pic_height; + + g_rx_ctrl_handle->compress_en = 1; + g_resolution_change = 1; + if(pic_width > 720) + { + g_tx_ctrl_handle->base_info.src_w = pic_width; + g_tx_ctrl_handle->base_info.src_h = pic_height; + } + + + + + hal_dsi_rx_ctrl_toggle_resolution(g_rx_ctrl_handle); + + } + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); + + return 1; +} + + + + + + + + + + +static _Bool ap_dcs_set_display_on(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + + if(g_resolution_change) + { + hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps_fhd, 128); + hal_dsi_rx_ctrl_toggle_resolution(g_rx_ctrl_handle); + g_resolution_change = 0; + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "pps_update_1\r\n", "p8p", 316); } while (0); + } + + + hal_dsi_tx_ctrl_write_cmd(0x05, 0, 2, 0x29); + + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "disp on \n", "p8p", 322); } while (0); + return 1; +} + + +void REG_51_OFF_output(uint16_t REG_51_VALUE) +{ + uint8_t i; + uint16_t REG_51; + + + + for (i =0; i< 50; i++) + { + REG_51=REG_51_VALUE*(50-i)/50; + hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, REG_51>>8, REG_51&0x00FF);; + delayMs(17); + + } + +} + + + + + + + +static _Bool ap_dcs_set_display_off(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + + + + + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "disp off %d\n", "p8p", 356,panel_display_done); } while (0); + return 1; +} + + + + + + + + +void Gpio_swire_output(uint8_t flag, uint8_t num) +{ + uint8_t ii; + + if (flag) + { + if (flag ==2) + { + hal_gpio_init_output(IO_PAD_AP_SWIRE, IO_LVL_HIGH); + delayMs(2); + } + for (ii =0; ii< num; ii++) + { + hal_gpio_set_output_data(IO_PAD_AP_SWIRE, IO_LVL_LOW); + delayUs(10); + hal_gpio_set_output_data(IO_PAD_AP_SWIRE, IO_LVL_HIGH); + delayUs(9); + } + } + else + { + hal_gpio_init_output(IO_PAD_AP_SWIRE, IO_LVL_LOW); + } +} + + + + + + + + + +static _Bool ap_dcs_set_enter_sleep_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x28); + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_STOP_MODE); + delayMs(10); + + + + + hal_swire_enable(0); + delayMs(10); + hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x10); + delayMs(20); + + hal_gpio_set_output_data(IO_PAD_AP_PWMEN, IO_LVL_LOW); + + + hal_gpio_set_ap_reset_int(ENABLE, ap_rstn_pull_down_cb, DETECT_LOW_LVL); + + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "enter sleep mode\n", "p8p", 419); } while (0); + + return 1; +} + + + + + + + +static _Bool ap_dcs_set_exit_sleep_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + + + + + +# 443 "..\\..\\src\\app\\P8P\\p8p_demo.c" + + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "exit sleep mode \n", "p8p", 444); } while (0); + + return 1; +} + + + + + + + + + + +uint8_t value_51H,value_51L; +static _Bool reg53_E8_fg=0; +static _Bool ap_dcs_set_backlight(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + + + + + + + rd_51_val = dcs_packet->packet_param[0]; + rd_51_val <<=8; + rd_51_val |= dcs_packet->packet_param[1]; + + + if((rd_51_val >=0x00)&&(rd_51_val <= 0xFFF) ){ + + rd_51_val2 = (rd_51_val-0xC4)*2555/3889+0x04; + + } + else if(rd_51_val >0xFFF) { + + rd_51_val2 = 0x9FF; + + } + hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, rd_51_val2>>8, rd_51_val2&0x00FF); + + + return 1; +} + +# 526 "..\\..\\src\\app\\P8P\\p8p_demo.c" + + + + + + + +static _Bool ap_dcs_set_exit_idle_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + sg_exit_idle_mode_flag = 1; + hal_dsi_rx_ctrl_set_hw_cmd_filter(g_rx_ctrl_handle, HAL_RX_DCS_FILTER_B, 0x2C, 0x2C); + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "exit idle mode,skip 0x2C\n", "p8p", 537); } while (0); + return 1; +} + + +static void soft_te_timer_cb(void *data) +{ + + + + + + hal_dsi_tx_ctrl_gen_a_tear_signal(); + hal_timer_start(TIMER_NUM2, 8, soft_te_timer_cb, 0); + + + + + +} + +static void soft_te_timer_init() +{ + + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle,TE_USER_MODE); + hal_timer_init(TIMER_NUM2); + hal_timer_start(TIMER_NUM2, 1, soft_te_timer_cb, 0); +} + + + + + + + +static _Bool ap_dcs_set_frame_change(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + if (dcs_packet->param_length == 1) + { + if (dcs_packet->packet_param[0] == 0x18) + { + + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); + } + else + { + + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_120HZ_MODE); + } + } + + return 1; +} + +static _Bool ap_set_FPS_53(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + uint8_t value_53 =0; + + value_53 = dcs_packet->packet_param[0]; + + if(value_53 == 0x30) + { + + hal_dsi_tx_ctrl_write_cmd( 0x39, 0, 4, 0x97, 0x11, 0xCF, 0xFF); + + } + else if(value_53 == 0x20) + { + + hal_dsi_tx_ctrl_write_cmd( 0x39, 0, 4, 0x97, 0x00, 0xCF, 0xFF); + + + } + + + return 1; +} + + + + +static const hal_dcs_execute_entry_t g_cus_rx_dcs_execute_table[] = +{ + {DCS_SET_DISPLAY_ON, ap_dcs_set_display_on, 0}, + {DCS_SET_DISPLAY_OFF, ap_dcs_set_display_off, 1}, + {0x51, ap_dcs_set_backlight, 0}, + {0x53, ap_set_FPS_53, 1}, + {DCS_ENTER_SLEEP_MODE, ap_dcs_set_enter_sleep_mode, 1}, + {DCS_EXIT_SLEEP_MODE, ap_dcs_set_exit_sleep_mode, 1}, + {0x60, ap_dcs_set_frame_change, 1}, + + + + + {0, 0, 0} +}; + + + + + + +static void app_tx_panel_reset(void) +{ + + + + hal_gpio_set_output_data(IO_PAD_TD_RSTN, IO_LVL_HIGH); + delayMs(10); + hal_gpio_set_output_data(IO_PAD_TD_RSTN, IO_LVL_LOW); + delayMs(10); + hal_gpio_set_output_data(IO_PAD_TD_RSTN, IO_LVL_HIGH); + delayMs(40); +} + + +static void send_panel_init_code(uint32_t size, uint8_t * data) +{ + uint32_t data_offeset = 0; + uint8_t data_type; + uint8_t vc; + uint8_t data_size; + uint8_t * p_data; + + while(data_offeset < size) + { + data_type = data[data_offeset]; + vc = data[data_offeset + 1]; + data_size = data[data_offeset + 2]; + p_data = &data[data_offeset + 3]; + hal_dsi_tx_ctrl_write_array_cmd(data_type, vc, data_size, p_data); + data_offeset = data_offeset + data_size + 3; + delayUs(50); + } +} + +const uint8_t panel_init_code[] = { + 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+0x39,0,29,0xD4,0xFF,0xF5,0xF3,0xED,0xDE,0xD8,0xCD,0xC8,0xCF,0x0F,0xCD,0xC5,0xC3,0xC3,0x00,0x0F,0x12,0x0F,0x12,0x15,0x17,0x18,0x1D,0x00,0x1F,0x20,0x25,0x2D, +0x39,0,17,0xD5,0x17,0xF9,0xFE,0xFD,0x05,0x00,0x00,0x00,0x17,0xF9,0xF8,0xFE,0x00,0x00,0x00,0x00, +0x39,0,17,0xD6,0x18,0xF5,0xF8,0x03,0x00,0x00,0x00,0x00,0x17,0xEB,0xED,0xEF,0x00,0x00,0x00,0x00, +0x39,0,13,0xD7,0x05,0x00,0x80,0x00,0x80,0xAF,0x00,0x80,0x00,0x80,0x03,0xFF, +0x39,0,17,0xD8,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20, +0x39,0,6,0xEE,0x30,0x10,0x00,0x10,0xFF, +0x39,0,2,0x9F,0x0A, +0x39,0,12,0xB2,0x1F,0x00,0x10,0x01,0x00,0x07,0x00,0x00,0x00,0x11,0x00, +0x39,0,43,0xB3,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00, +0x39,0,43,0xB4,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00, +0x39,0,43,0xB5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00, +0x39,0,12,0xBE,0x00,0x1F,0xFF,0x13,0x91,0x0F,0x04,0x00,0x24,0x80,0xFF, +0x39,0,2,0x9F,0x0B, +0x39,0,10,0xB2,0x01,0x3F,0x3F,0x0F,0x3F,0x0F,0x5F,0x0F,0x0F, +0x39,0,49,0xB9,0x32,0x00,0x00,0x00,0x00,0x00,0x6B,0x54,0x24,0x1C,0xB0,0x14,0xC8,0x5C,0x24,0x1C,0xB0,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,49,0xBA,0x32,0x00,0x00,0x00,0x00,0x00,0x54,0x69,0x24,0x1C,0xB0,0x14,0xC8,0x5C,0x24,0x1C,0xB0,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,49,0xBC,0x32,0x00,0x00,0x00,0x00,0x00,0x4b,0x4b,0x24,0x1C,0xB0,0x14,0xD1,0x65,0x24,0x1C,0xB0,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,49,0xBE,0x32,0x00,0x00,0x00,0x00,0x00,0x25,0x25,0x20,0x1C,0x33,0x00,0x00,0x00,0x00,0x25,0x25,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,20,0xC6,0x8F,0x04,0x04,0x04,0x04,0xFF,0xFF,0xFF,0xFF,0x00,0x22,0x22,0x22,0x22,0x00,0x1E,0x1E,0x1E,0x1E, +0x39,0,20,0xC7,0x0F,0x04,0x04,0x04,0x04,0xFF,0xFF,0xFF,0xFF,0x00,0x22,0x22,0x22,0x22,0x00,0x1E,0x1E,0x1E,0x1E, +0x39,0,16,0xC8,0xF9,0x05,0x05,0xB0,0xE0,0xB0,0x50,0xBA,0xF0,0xB0,0xE0,0xB0,0x20,0xD0,0x50, +0x39,0,2,0x9F,0x0D, +0x39,0,16,0xB2,0x25,0x10,0x21,0x01,0x02,0x10,0x00,0x00,0x16,0x10,0x00,0x00,0x01,0xAA,0x90, +0x39,0,2,0xB3,0xB0, +0x39,0,13,0xB5,0x00,0x24,0x07,0x01,0x00,0x00,0x00,0x00,0x20,0x04,0xEE,0x21, +0x39,0,4,0xB6,0x02,0x12,0x22, +0x39,0,5,0xB7,0x20,0xF0,0xC0,0xE0, +0x39,0,13,0xB8,0x20,0xF0,0xC0,0xE0,0x20,0xF0,0xC0,0xE0,0x20,0xF0,0xC0,0xE0, +0x39,0,5,0xB9,0x01,0x01,0x01,0x01, +0x39,0,3,0xBA,0x00,0x00, +0x39,0,2,0xBB,0x01, +0x39,0,21,0xBC,0x0F,0xFF,0x07,0xFF,0x03,0x33,0x01,0x47,0x01,0x46,0x00,0xCD,0x00,0x66,0x00,0x3A,0x00,0x14,0x00,0x08, +0x39,0,6,0xBD,0x02,0x00,0x02,0x06,0x5B, +0x39,0,12,0xC7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2A,0x00, +0x39,0,2,0x48,0x03, +0x39,0,1,0x11, +0x39,0,3,0x51,0x00,0x0F, +0x39,0,2,0x53,0xE0, +0x39,0,1,0x35, + +# 1435 "..\\..\\src\\app\\P8P\\p8p_demo.c" +0x39,0,2,0x9F,0x04, +0x39,0,14,0xB5,0x00,0x17,0x27,0x1B,0x17,0x00,0x75,0x75,0x10,0x3B,0x08,0xA8,0x48, + + + + + + +0x39,0,18,0xBE,0x00,0xCF,0xFF,0xFF,0xFF,0x3F,0xFF,0xFF,0xFF,0x3F,0xFF,0xFF,0xFF,0x3F,0xFF,0xFF,0xFF, +0x39,0,46,0xE9,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0xFF,0x3F,0x3F,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +0x39,0,28,0xEA,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +0x39,0,46,0xEB,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0xFF,0x3F,0x3F,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +0x39,0,28,0xEC,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +0x39,0,46,0xED,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0xFF,0x3F,0x3F,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +0x39,0,28,0xEE,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +0x39,0,10,0xF8,0x1E,0xE0,0xE0,0xE0,0x00,0x18,0x15,0x00,0xE0, +0x39,0,10,0xF9,0xE1,0x18,0x15,0x00,0xF0,0xF8,0xF0,0xEE,0x00, +0x39,0,10,0xFA,0x1E,0xE0,0xE0,0xE0,0x00,0x18,0x15,0x00,0xE0, +0x39,0,2,0x9F,0x05, +0x39,0,13,0xB4,0x02,0x0F,0x3E,0x00,0x00,0x10,0x06,0x00,0x00,0x02,0x40,0x8D, +0x39,0,41,0xE6,0x0F,0xFF,0x07,0xFF,0x03,0x33,0x01,0x47,0x01,0x46,0x00,0xCD,0x00,0x66,0x00,0x3A,0x00,0x14,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,31,0xE7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,41,0xE8,0x0F,0xFF,0x0F,0xFF,0x0F,0xFF,0x0F,0xFF,0x0F,0xFF,0x0C,0xF0,0x09,0x71,0x07,0x54,0x04,0x8C,0x03,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + +0x39,0,31,0xE9,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + + + +}; + + + + + + + + + +static void app_init_panel(void) +{ + + app_tx_panel_reset(); + + send_panel_init_code(sizeof(panel_init_code), (uint8_t *) panel_init_code); + + hal_gpio_init_output(IO_PAD_AP_PWMEN, IO_LVL_HIGH); + delayMs(90); + + hal_swire_enable(1); + hal_swire_set_pulse(31); + + + + + +} + +# 1507 "..\\..\\src\\app\\P8P\\p8p_demo.c" + +# 1544 "..\\..\\src\\app\\P8P\\p8p_demo.c" + + + + + + +static void app_mipi_rx_init(void) +{ + if (g_rx_ctrl_handle == 0) + { + + g_rx_ctrl_handle = hal_dsi_rx_ctrl_create_handle(); + } + + g_rx_ctrl_handle->base_info.src_w = 1344; + g_rx_ctrl_handle->base_info.src_h = 2992; + g_rx_ctrl_handle->base_info.dst_w = 1080; + g_rx_ctrl_handle->base_info.dst_h = 2400; + g_rx_ctrl_handle->base_info.src_frate = DSI_FRAME_RATE_120HZ; + g_rx_ctrl_handle->base_info.src_mode = DSI_DATA_CMD_MODE; + g_rx_ctrl_handle->base_info.dst_mode = DSI_DATA_VIDEO_MODE; + g_rx_ctrl_handle->rx_color_mode = DSI_RGB888; + g_rx_ctrl_handle->rx_lanes = DSI_LANE_4; + g_rx_ctrl_handle->rx_nonburst_models = DSI_NONBURST_EVENT; + g_rx_ctrl_handle->compress_en = 1; + g_rx_ctrl_handle->rx_hsclk_rate = 1600000000; + g_rx_ctrl_handle->cus_dcs_entry_table = g_cus_rx_dcs_execute_table; + g_rx_ctrl_handle->rx_dcs_read_entry = ap_dcs_read; + + g_rx_ctrl_handle->extra_info.crop_info.top =12; + g_rx_ctrl_handle->extra_info.crop_info.enable=1; + + g_rx_ctrl_handle->pps_update_entry = pps_update_handle; + + + if (g_rx_ctrl_handle->compress_en == 1) + { + hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps, 128); + } + + + hal_dsi_rx_ctrl_init(g_rx_ctrl_handle); + + + + + + +# 1599 "..\\..\\src\\app\\P8P\\p8p_demo.c" + + + + hal_dsi_rx_ctrl_start(g_rx_ctrl_handle); + + + + + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "rx init!\n\r", "p8p", 1607); } while (0); +} + + + + + + +static void app_mipi_tx_init(void) +{ + if (g_tx_ctrl_handle == 0) + { + g_tx_ctrl_handle = hal_dsi_tx_ctrl_create_handle(); + } + g_tx_ctrl_handle->channel_id = DSI_VC_0; + g_tx_ctrl_handle->lane_num = DSI_LANE_4; + g_tx_ctrl_handle->vid_mode = DSI_BURST_MODE; + g_tx_ctrl_handle->cmd_tx_type = DSI_CMD_TX_LP; + g_tx_ctrl_handle->dpi_vsa = 1; + g_tx_ctrl_handle->dpi_vbp = 19; + g_tx_ctrl_handle->dpi_vfp = 12; + g_tx_ctrl_handle->dpi_hsa = 1; + g_tx_ctrl_handle->dpi_hbp = 27; + g_tx_ctrl_handle->dpi_hfp = 77; + g_tx_ctrl_handle->base_info.src_w = 1344; + g_tx_ctrl_handle->base_info.src_h = 2992; + g_tx_ctrl_handle->base_info.dst_w = 1080; + g_tx_ctrl_handle->base_info.dst_h = 2400; + g_tx_ctrl_handle->base_info.src_frate = DSI_FRAME_RATE_120HZ; + g_tx_ctrl_handle->base_info.src_mode = DSI_DATA_CMD_MODE; + g_tx_ctrl_handle->base_info.dst_mode = DSI_DATA_VIDEO_MODE; + g_tx_ctrl_handle->tx_frame_rate=58; + + + + + + + hal_dsi_tx_ctrl_init(g_tx_ctrl_handle); + + + + + + + hal_dsi_tx_ctrl_set_overwrite_rgb(0x00, 0x00, 0x00); + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "tx init!\n\r", "p8p", 1653); } while (0); +} + +# 1671 "..\\..\\src\\app\\P8P\\p8p_demo.c" + +void Panel_CCM(void) +{ + ccm_coef_t ccm; + ccm.coef_c00 = 255; + ccm.coef_c01 = 0; + ccm.coef_c02 = 0; + ccm.coef_c10 = 0; + ccm.coef_c11 = 246; + ccm.coef_c12 = 0; + ccm.coef_c20 = 0; + ccm.coef_c21 = 0; + ccm.coef_c22 = 247; + + hal_dsi_tx_ctrl_set_ccm(&ccm); +} + + + + + + + +static void app_mipi_tx_start(void) +{ + + + app_init_panel(); + + hal_dsi_tx_ctrl_start(g_tx_ctrl_handle); + + + + + + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); + + + panel_display_done = 1; + if(g_tx_ctrl_handle->base_info.src_w==1008) + { + hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps_fhd, 128); + hal_dsi_rx_ctrl_toggle_resolution(g_rx_ctrl_handle); + g_resolution_change = 0; + + } + + delayMs(80); + + + + hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x29); + + + hal_swire_set_pulse(31); + + + + + + + + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "tx_start \n", "p8p", 1733); } while (0); +} + + + + + + +static void ap_rstn_pull_high_cb(void *data) +{ + + sg_system_resume = 1; + + hal_gpio_set_ap_reset_int(DISABLE, 0, DETECT_RISING_EDGE); +} + + + + + + +static void ap_rstn_pull_down_cb(void *data) +{ + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "ap_rstn_pull_down_cb\n", "p8p", 1756); } while (0); + sg_system_suspend = 1; + + hal_gpio_set_ap_reset_int(DISABLE, 0, DETECT_RISING_EDGE); + +} + + + + + + + +void app_gpio_init(void) +{ + io_pad_attr_t attrs[] = + { + {IO_PIN_8, PIN8_MODE_GPIO7, IO_IOE_OUTPUT, IO_LVL_LOW}, + {IO_PIN_17, PIN17_MODE_GPIO8, IO_IOE_OUTPUT, IO_LVL_LOW}, + {IO_PIN_16, PIN16_MODE_GPIO2, IO_IOE_OUTPUT, IO_LVL_LOW}, + + + + {IO_PIN_29, PIN29_MODE_TEAR, IO_IOE_NONE, IO_LVL_NONE}, + + }; + uint8_t size = sizeof(attrs) / sizeof(io_pad_attr_t); + hal_gpio_config_pad(attrs, size); +} + + + + + + + +void app_display_init(void) +{ + + app_mipi_rx_init(); + + if (PWR_SEL_VCC == PWR_SEL_VCC) + { + + while (hal_pwr_get_vcc_power_ready() == 0); + } + + + app_gpio_init(); + + + + hal_swire_init(); + hal_swire_set_timer(TIMER_NUM0, 8, 1); +# 1818 "..\\..\\src\\app\\P8P\\p8p_demo.c" + + + app_mipi_tx_init(); + + + + + app_mipi_tx_start(); + +} + + + + + + +static void app_system_resume(pwr_sleep_mode_e sleep_mode) +{ + + hal_pwr_exit_sleep_mode(); + + + app_display_init(); + + + + + + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "system resume\n", "p8p", 1846); } while (0); +} + + + + + + +static void app_system_suspend(pwr_sleep_mode_e sleep_mode) +{ + + + hal_dsi_tx_ctrl_stop(g_tx_ctrl_handle); + hal_dsi_tx_ctrl_deinit(g_tx_ctrl_handle); + hal_dsi_rx_ctrl_stop(g_rx_ctrl_handle); + hal_dsi_rx_ctrl_deinit(g_rx_ctrl_handle); + + + hal_gpio_init_output(IO_PAD_AP_TE, IO_LVL_LOW); + panel_display_done = 0; + + + + + + + hal_swire_deinit(); + + + + + + + + + + + hal_pwr_set_sleep_mode_power(PWR_SLEEP_IN_IOV18); + + if (sleep_mode == PWR_NORMAL_SLEEP_MODE) + { + + hal_gpio_set_ap_reset_int(ENABLE, ap_rstn_pull_high_cb, DETECT_HIGH_LVL); + hal_pwr_enter_normal_sleep_mode(); + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "PWR_NORMAL_SLEEP_MODE\n", "p8p", 1890); } while (0); + } + else if (sleep_mode == PWR_STOP_SLEEP_MODE) + { + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "PWR_STOP_SLEEP_MODE\n", "p8p", 1894); } while (0); + + + hal_pwr_set_stop_sleep_wakeup_pin(IO_PAD_AP_RSTN, WUP_RISING_EDGE); + + + io_pad_e wakeup_io = hal_pwr_enter_stop_sleep_mode(); + if (wakeup_io == IO_PAD_AP_RSTN) + { + sg_system_resume = 1; + } + else + { + + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "wakeup_io %d FIXME touch wakeup convert to AP\n", "p8p", 1908,wakeup_io); } while (0); + hal_gpio_set_ap_reset_int(ENABLE, ap_rstn_pull_high_cb, DETECT_HIGH_LVL); + } + } + else + { + + hal_pwr_enter_deep_sleep_mode(WUP_RISING_EDGE, WUP_FALLING_EDGE); + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "PWR_DEEP_SLEEP_MODE\n", "p8p", 1916); } while (0); + } + +} + + + + + + +static void app_system_process(void) +{ + + if (sg_system_suspend) + { + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "app_system_process\n", "p8p", 1931); } while (0); + + app_system_suspend(PWR_DEEP_SLEEP_MODE); + sg_system_suspend = 0; + } + + if (sg_system_resume) + { + + app_system_resume(PWR_DEEP_SLEEP_MODE); + sg_system_resume = 0; + } + +# 1951 "..\\..\\src\\app\\P8P\\p8p_demo.c" +} + + + + + + + + +void google_p8p_demo(void) +{ + + + + + hal_pwr_set_main_power(PWR_SEL_VCC); + + + + + + app_display_init(); + + +# 1982 "..\\..\\src\\app\\P8P\\p8p_demo.c" + + do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "p8p demo init done \n", "p8p", 1983); } while (0); + + while (1) + { + + + + + + + + while (hal_dsi_rx_ctrl_dcs_async_handler(g_rx_ctrl_handle)); + + + app_system_process(); + } +} diff --git a/project/WL668/Listings/p8p_demo.lst b/project/WL668/Listings/p8p_demo.lst new file mode 100644 index 0000000..0efb975 --- /dev/null +++ b/project/WL668/Listings/p8p_demo.lst @@ -0,0 +1,11121 @@ +L 1 "..\..\src\app\P8P\p8p_demo.c" +N/******************************************************************************* +N* +N* File: p8p_demo.c +N* Description: 系统测试文件 +N* Version: V0.1 +N* Date: 2020-02-22 +N* Author: Tempest +N *******************************************************************************/ +N#include "p8p_demo.h" +L 1 "..\..\src\app\P8P\p8p_demo.h" 1 +N/******************************************************************************* +N* Copyright (C) 2019-2022, TAU Systems (R),All Rights Reserved. +N* +N* File: P8P.h +N* Description GOOGLE P8P DEMO file +N* Version V0.1 +N* Date 2023-12-25 +N* Author Markin +N*******************************************************************************/ +N#ifndef __GOOGLE_P8P_DEMO_H__ +N#define __GOOGLE_P8P_DEMO_H__ +N +N +N#define PANEL_INIT_CODE_ARRAY 1 +N#define DDIC_FPS_SETTING 1 +N +N +N +Nvoid google_p8p_demo(void); +N +N#endif +L 10 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "ArmCM0.h" +L 1 "..\..\src\sdk\include\M0\ArmCM0.h" 1 +N/**************************************************************************//** +N * @file ARMCM0.h +N * @brief CMSIS Core Peripheral Access Layer Header File for +N * ARMCM0 Device +N * @version V5.3.1 +N * @date 09. July 2018 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#ifndef ARMCM0_H +N#define ARMCM0_H +N +N#ifdef __cplusplus +Sextern "C" { +N#endif +N +N +N/* ------------------------- Interrupt Number Definition ------------------------ */ +N +Ntypedef enum IRQn +N{ +N /* ------------------- Processor Exceptions Numbers ----------------------------- */ +N NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ +N HardFault_IRQn = -13, /* 3 HardFault Interrupt */ +N SVCall_IRQn = -5, /* 11 SV Call Interrupt */ +N PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ +N SysTick_IRQn = -1, /* 15 System Tick Interrupt */ +N +N /* ------------------- Processor Interrupt Numbers ------------------------------ */ +N VIDC_IRQn = 0, +N LCDC_IRQn = 1, +N MIPI_RX_IRQn = 2, +N MIPI_TX_IRQn = 3, +N MEMC_IRQn = 4, +N VPRE_IRQn = 5, +N FLSCTRL_IRQn = 6, +N DMA_IRQn = 7, +N TIMER0_IRQn = 8, +N TIMER1_IRQn = 9, +N TIMER2_IRQn = 10, +N TIMER3_IRQn = 11, +N WDG_IRQn = 12, +N UART_IRQn = 13, +N I2C0_IRQn = 14, +N I2C1_IRQn = 15, +N SPIS_IRQn = 16, +N SPIM_IRQn = 17, +N VPRE1_IRQn = 18, +N I2C2_IRQn = 19, +N OTP_IRQn = 20, +N SWIRE_IRQn = 21, +N PVD_IRQn = 22, +N AP_NRESET_IRQn = 23, +N EXTI_INT0_IRQn = 24, +N EXTI_INT1_IRQn = 25, +N EXTI_INT2_IRQn = 26, +N EXTI_INT3_IRQn = 27, +N EXTI_INT4_IRQn = 28, +N EXTI_INT5_IRQn = 29, +N EXTI_INT6_IRQn = 30, +N EXTI_INT7_IRQn = 31 +N /* Interrupts 10 .. 31 are left out */ +N} IRQn_Type; +N +N +N/* ================================================================================ */ +N/* ================ Processor and Core Peripheral Section ================ */ +N/* ================================================================================ */ +N +N/* ------- Start of section using anonymous unions and disabling warnings ------- */ +N#if defined (__CC_ARM) +X#if 1L +N#pragma push +N#pragma anon_unions +N#elif defined (__ICCARM__) +X#elif 0L +S#pragma language=extended +S#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +S#pragma clang diagnostic push +S#pragma clang diagnostic ignored "-Wc11-extensions" +S#pragma clang diagnostic ignored "-Wreserved-id-macro" +S#elif defined (__GNUC__) +S/* anonymous unions are enabled by default */ +S#elif defined (__TMS470__) +S/* anonymous unions are enabled by default */ +S#elif defined (__TASKING__) +S#pragma warning 586 +S#elif defined (__CSMC__) +S/* anonymous unions are enabled by default */ +S#else +S#warning Not supported compiler type +N#endif +N +N/* -------- Configuration of Core Peripherals ----------------------------------- */ +N#define __CM0_REV 0x0000U /* Core revision r0p0 */ +N#define __MPU_PRESENT 0U /* no MPU present */ +N#define __VTOR_PRESENT 0U /* no VTOR present */ +N#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ //20220228 +N#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +N +N#define __FPU_PRESENT 0U /* Set to 1 if FPU is present */ +N#define __FPU_DP 0U /* single precision FPU */ +N#define __ICACHE_PRESENT 0U /* Set to 1 if I-CACHE is present */ +N#define __DCACHE_PRESENT 0U /* Set to 1 if D-CACHE is present */ +N#define __DSP_PRESENT 0U /* no DSP extension present */ +N +N#include "core_cm0.h" /* Processor and core peripherals */ +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h" 1 +N/**************************************************************************//** +N * @file core_cm0.h +N * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File +N * @version V5.0.6 +N * @date 13. March 2019 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2019 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#if defined ( __ICCARM__ ) +X#if 0L +S #pragma system_include /* treat file as system include file for MISRA check */ +S#elif defined (__clang__) +X#elif 0L +S #pragma clang system_header /* treat file as system include file */ +N#endif +N +N#ifndef __CORE_CM0_H_GENERIC +N#define __CORE_CM0_H_GENERIC +N +N#include +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h" 1 +N/* Copyright (C) ARM Ltd., 1999,2014 */ +N/* All rights reserved */ +N +N/* +N * RCS $Revision$ +N * Checkin $Date$ +N * Revising $Author: agrant $ +N */ +N +N#ifndef __stdint_h +N#define __stdint_h +N#define __ARMCLIB_VERSION 5060037 +N +N #ifdef __INT64_TYPE__ +S /* armclang predefines '__INT64_TYPE__' and '__INT64_C_SUFFIX__' */ +S #define __INT64 __INT64_TYPE__ +N #else +N /* armcc has builtin '__int64' which can be used in --strict mode */ +N #define __INT64 __int64 +N #define __INT64_C_SUFFIX__ ll +N #endif +N #define __PASTE2(x, y) x ## y +N #define __PASTE(x, y) __PASTE2(x, y) +N #define __INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__)) +N #define __UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__)) +N #if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__)) +X #if 0L || (1L && !0L) +N /* armclang and non-strict armcc allow 'long long' in system headers */ +N #define __LONGLONG long long +N #else +S /* strict armcc has '__int64' */ +S #define __LONGLONG __int64 +N #endif +N +N #ifndef __STDINT_DECLS +N #define __STDINT_DECLS +N +N #undef __CLIBNS +N +N #ifdef __cplusplus +S namespace std { +S #define __CLIBNS std:: +S extern "C" { +N #else +N #define __CLIBNS +N #endif /* __cplusplus */ +N +N +N/* +N * 'signed' is redundant below, except for 'signed char' and if +N * the typedef is used to declare a bitfield. +N */ +N +N /* 7.18.1.1 */ +N +N /* exact-width signed integer types */ +Ntypedef signed char int8_t; +Ntypedef signed short int int16_t; +Ntypedef signed int int32_t; +Ntypedef signed __INT64 int64_t; +Xtypedef signed __int64 int64_t; +N +N /* exact-width unsigned integer types */ +Ntypedef unsigned char uint8_t; +Ntypedef unsigned short int uint16_t; +Ntypedef unsigned int uint32_t; +Ntypedef unsigned __INT64 uint64_t; +Xtypedef unsigned __int64 uint64_t; +N +N /* 7.18.1.2 */ +N +N /* smallest type of at least n bits */ +N /* minimum-width signed integer types */ +Ntypedef signed char int_least8_t; +Ntypedef signed short int int_least16_t; +Ntypedef signed int int_least32_t; +Ntypedef signed __INT64 int_least64_t; +Xtypedef signed __int64 int_least64_t; +N +N /* minimum-width unsigned integer types */ +Ntypedef unsigned char uint_least8_t; +Ntypedef unsigned short int uint_least16_t; +Ntypedef unsigned int uint_least32_t; +Ntypedef unsigned __INT64 uint_least64_t; +Xtypedef unsigned __int64 uint_least64_t; +N +N /* 7.18.1.3 */ +N +N /* fastest minimum-width signed integer types */ +Ntypedef signed int int_fast8_t; +Ntypedef signed int int_fast16_t; +Ntypedef signed int int_fast32_t; +Ntypedef signed __INT64 int_fast64_t; +Xtypedef signed __int64 int_fast64_t; +N +N /* fastest minimum-width unsigned integer types */ +Ntypedef unsigned int uint_fast8_t; +Ntypedef unsigned int uint_fast16_t; +Ntypedef unsigned int uint_fast32_t; +Ntypedef unsigned __INT64 uint_fast64_t; +Xtypedef unsigned __int64 uint_fast64_t; +N +N /* 7.18.1.4 integer types capable of holding object pointers */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +Stypedef signed __INT64 intptr_t; +Stypedef unsigned __INT64 uintptr_t; +N#else +Ntypedef signed int intptr_t; +Ntypedef unsigned int uintptr_t; +N#endif +N +N /* 7.18.1.5 greatest-width integer types */ +Ntypedef signed __LONGLONG intmax_t; +Xtypedef signed long long intmax_t; +Ntypedef unsigned __LONGLONG uintmax_t; +Xtypedef unsigned long long uintmax_t; +N +N +N#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) +X#if !0L || 0L +N +N /* 7.18.2.1 */ +N +N /* minimum values of exact-width signed integer types */ +N#define INT8_MIN -128 +N#define INT16_MIN -32768 +N#define INT32_MIN (~0x7fffffff) /* -2147483648 is unsigned */ +N#define INT64_MIN __INT64_C(~0x7fffffffffffffff) /* -9223372036854775808 is unsigned */ +N +N /* maximum values of exact-width signed integer types */ +N#define INT8_MAX 127 +N#define INT16_MAX 32767 +N#define INT32_MAX 2147483647 +N#define INT64_MAX __INT64_C(9223372036854775807) +N +N /* maximum values of exact-width unsigned integer types */ +N#define UINT8_MAX 255 +N#define UINT16_MAX 65535 +N#define UINT32_MAX 4294967295u +N#define UINT64_MAX __UINT64_C(18446744073709551615) +N +N /* 7.18.2.2 */ +N +N /* minimum values of minimum-width signed integer types */ +N#define INT_LEAST8_MIN -128 +N#define INT_LEAST16_MIN -32768 +N#define INT_LEAST32_MIN (~0x7fffffff) +N#define INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff) +N +N /* maximum values of minimum-width signed integer types */ +N#define INT_LEAST8_MAX 127 +N#define INT_LEAST16_MAX 32767 +N#define INT_LEAST32_MAX 2147483647 +N#define INT_LEAST64_MAX __INT64_C(9223372036854775807) +N +N /* maximum values of minimum-width unsigned integer types */ +N#define UINT_LEAST8_MAX 255 +N#define UINT_LEAST16_MAX 65535 +N#define UINT_LEAST32_MAX 4294967295u +N#define UINT_LEAST64_MAX __UINT64_C(18446744073709551615) +N +N /* 7.18.2.3 */ +N +N /* minimum values of fastest minimum-width signed integer types */ +N#define INT_FAST8_MIN (~0x7fffffff) +N#define INT_FAST16_MIN (~0x7fffffff) +N#define INT_FAST32_MIN (~0x7fffffff) +N#define INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff) +N +N /* maximum values of fastest minimum-width signed integer types */ +N#define INT_FAST8_MAX 2147483647 +N#define INT_FAST16_MAX 2147483647 +N#define INT_FAST32_MAX 2147483647 +N#define INT_FAST64_MAX __INT64_C(9223372036854775807) +N +N /* maximum values of fastest minimum-width unsigned integer types */ +N#define UINT_FAST8_MAX 4294967295u +N#define UINT_FAST16_MAX 4294967295u +N#define UINT_FAST32_MAX 4294967295u +N#define UINT_FAST64_MAX __UINT64_C(18446744073709551615) +N +N /* 7.18.2.4 */ +N +N /* minimum value of pointer-holding signed integer type */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define INTPTR_MIN INT64_MIN +N#else +N#define INTPTR_MIN INT32_MIN +N#endif +N +N /* maximum value of pointer-holding signed integer type */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define INTPTR_MAX INT64_MAX +N#else +N#define INTPTR_MAX INT32_MAX +N#endif +N +N /* maximum value of pointer-holding unsigned integer type */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define UINTPTR_MAX UINT64_MAX +N#else +N#define UINTPTR_MAX UINT32_MAX +N#endif +N +N /* 7.18.2.5 */ +N +N /* minimum value of greatest-width signed integer type */ +N#define INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) +N +N /* maximum value of greatest-width signed integer type */ +N#define INTMAX_MAX __ESCAPE__(9223372036854775807ll) +N +N /* maximum value of greatest-width unsigned integer type */ +N#define UINTMAX_MAX __ESCAPE__(18446744073709551615ull) +N +N /* 7.18.3 */ +N +N /* limits of ptrdiff_t */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define PTRDIFF_MIN INT64_MIN +S#define PTRDIFF_MAX INT64_MAX +N#else +N#define PTRDIFF_MIN INT32_MIN +N#define PTRDIFF_MAX INT32_MAX +N#endif +N +N /* limits of sig_atomic_t */ +N#define SIG_ATOMIC_MIN (~0x7fffffff) +N#define SIG_ATOMIC_MAX 2147483647 +N +N /* limit of size_t */ +N#if __sizeof_ptr == 8 +X#if 4 == 8 +S#define SIZE_MAX UINT64_MAX +N#else +N#define SIZE_MAX UINT32_MAX +N#endif +N +N /* limits of wchar_t */ +N /* NB we have to undef and redef because they're defined in both +N * stdint.h and wchar.h */ +N#undef WCHAR_MIN +N#undef WCHAR_MAX +N +N#if defined(__WCHAR32) || (defined(__ARM_SIZEOF_WCHAR_T) && __ARM_SIZEOF_WCHAR_T == 4) +X#if 0L || (0L && __ARM_SIZEOF_WCHAR_T == 4) +S #define WCHAR_MIN 0 +S #define WCHAR_MAX 0xffffffffU +N#else +N #define WCHAR_MIN 0 +N #define WCHAR_MAX 65535 +N#endif +N +N /* limits of wint_t */ +N#define WINT_MIN (~0x7fffffff) +N#define WINT_MAX 2147483647 +N +N#endif /* __STDC_LIMIT_MACROS */ +N +N#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) +X#if !0L || 0L +N +N /* 7.18.4.1 macros for minimum-width integer constants */ +N#define INT8_C(x) (x) +N#define INT16_C(x) (x) +N#define INT32_C(x) (x) +N#define INT64_C(x) __INT64_C(x) +N +N#define UINT8_C(x) (x ## u) +N#define UINT16_C(x) (x ## u) +N#define UINT32_C(x) (x ## u) +N#define UINT64_C(x) __UINT64_C(x) +N +N /* 7.18.4.2 macros for greatest-width integer constants */ +N#define INTMAX_C(x) __ESCAPE__(x ## ll) +N#define UINTMAX_C(x) __ESCAPE__(x ## ull) +N +N#endif /* __STDC_CONSTANT_MACROS */ +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif /* __cplusplus */ +N #endif /* __STDINT_DECLS */ +N +N #ifdef __cplusplus +S #ifndef __STDINT_NO_EXPORTS +S using ::std::int8_t; +S using ::std::int16_t; +S using ::std::int32_t; +S using ::std::int64_t; +S using ::std::uint8_t; +S using ::std::uint16_t; +S using ::std::uint32_t; +S using ::std::uint64_t; +S using ::std::int_least8_t; +S using ::std::int_least16_t; +S using ::std::int_least32_t; +S using ::std::int_least64_t; +S using ::std::uint_least8_t; +S using ::std::uint_least16_t; +S using ::std::uint_least32_t; +S using ::std::uint_least64_t; +S using ::std::int_fast8_t; +S using ::std::int_fast16_t; +S using ::std::int_fast32_t; +S using ::std::int_fast64_t; +S using ::std::uint_fast8_t; +S using ::std::uint_fast16_t; +S using ::std::uint_fast32_t; +S using ::std::uint_fast64_t; +S using ::std::intptr_t; +S using ::std::uintptr_t; +S using ::std::intmax_t; +S using ::std::uintmax_t; +S #endif +N #endif /* __cplusplus */ +N +N#undef __INT64 +N#undef __LONGLONG +N +N#endif /* __stdint_h */ +N +N/* end of stdint.h */ +L 35 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h" 2 +N +N#ifdef __cplusplus +S extern "C" { +N#endif +N +N/** +N \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions +N CMSIS violates the following MISRA-C:2004 rules: +N +N \li Required Rule 8.5, object/function definition in header file.
+N Function definitions in header files are used to allow 'inlining'. +N +N \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+N Unions are used for effective representation of core registers. +N +N \li Advisory Rule 19.7, Function-like macro defined.
+N Function-like macros are used to allow more efficient code. +N */ +N +N +N/******************************************************************************* +N * CMSIS definitions +N ******************************************************************************/ +N/** +N \ingroup Cortex_M0 +N @{ +N */ +N +N#include "cmsis_version.h" +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_version.h" 1 +N/**************************************************************************//** +N * @file cmsis_version.h +N * @brief CMSIS Core(M) Version definitions +N * @version V5.0.2 +N * @date 19. April 2017 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2017 ARM Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#if defined ( __ICCARM__ ) +X#if 0L +S #pragma system_include /* treat file as system include file for MISRA check */ +S#elif defined (__clang__) +X#elif 0L +S #pragma clang system_header /* treat file as system include file */ +N#endif +N +N#ifndef __CMSIS_VERSION_H +N#define __CMSIS_VERSION_H +N +N/* CMSIS Version definitions */ +N#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +N#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +N#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ +N __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +X#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | __CM_CMSIS_VERSION_SUB ) +N#endif +L 64 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h" 2 +N +N/* CMSIS CM0 definitions */ +N#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +N#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +N#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ +N __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ +X#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB ) +N +N#define __CORTEX_M (0U) /*!< Cortex-M Core */ +N +N/** __FPU_USED indicates whether an FPU is used or not. +N This core does not support an FPU at all +N*/ +N#define __FPU_USED 0U +N +N#if defined ( __CC_ARM ) +X#if 1L +N #if defined __TARGET_FPU_VFP +X #if 0L +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +N #endif +N +N#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +X#elif 1L && (5060750 >= 6010050) +S #if defined __ARM_FP +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __GNUC__ ) +S #if defined (__VFP_FP__) && !defined(__SOFTFP__) +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __ICCARM__ ) +S #if defined __ARMVFP__ +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __TI_ARM__ ) +S #if defined __TI_VFP_SUPPORT__ +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __TASKING__ ) +S #if defined __FPU_VFP__ +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +S#elif defined ( __CSMC__ ) +S #if ( __CSMC__ & 0x400U) +S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +S #endif +S +N#endif +N +N#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h" 1 +N/**************************************************************************//** +N * @file cmsis_compiler.h +N * @brief CMSIS compiler generic header file +N * @version V5.1.0 +N * @date 09. October 2018 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#ifndef __CMSIS_COMPILER_H +N#define __CMSIS_COMPILER_H +N +N#include +N +N/* +N * Arm Compiler 4/5 +N */ +N#if defined ( __CC_ARM ) +X#if 1L +N #include "cmsis_armcc.h" +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_armcc.h" 1 +N/**************************************************************************//** +N * @file cmsis_armcc.h +N * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file +N * @version V5.0.5 +N * @date 14. December 2018 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#ifndef __CMSIS_ARMCC_H +N#define __CMSIS_ARMCC_H +N +N +N#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) +X#if 1L && (5060750 < 400677) +S #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +N#endif +N +N/* CMSIS compiler control architecture macros */ +N#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ +N (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) +X#if ((0L && (__TARGET_ARCH_6_M == 1)) || (1L && (1 == 1)) ) +N #define __ARM_ARCH_6M__ 1 +N#endif +N +N#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) +X#if (0L && (__TARGET_ARCH_7_M == 1)) +S #define __ARM_ARCH_7M__ 1 +N#endif +N +N#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) +X#if (0L && (__TARGET_ARCH_7E_M == 1)) +S #define __ARM_ARCH_7EM__ 1 +N#endif +N +N /* __ARM_ARCH_8M_BASE__ not applicable */ +N /* __ARM_ARCH_8M_MAIN__ not applicable */ +N +N/* CMSIS compiler control DSP macros */ +N#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7EM__ == 1)) ) +S #define __ARM_FEATURE_DSP 1 +N#endif +N +N/* CMSIS compiler specific defines */ +N#ifndef __ASM +N #define __ASM __asm +N#endif +N#ifndef __INLINE +N #define __INLINE __inline +N#endif +N#ifndef __STATIC_INLINE +N #define __STATIC_INLINE static __inline +N#endif +N#ifndef __STATIC_FORCEINLINE +N #define __STATIC_FORCEINLINE static __forceinline +N#endif +N#ifndef __NO_RETURN +N #define __NO_RETURN __declspec(noreturn) +N#endif +N#ifndef __USED +N #define __USED __attribute__((used)) +N#endif +N#ifndef __WEAK +N #define __WEAK __attribute__((weak)) +N#endif +N#ifndef __PACKED +N #define __PACKED __attribute__((packed)) +N#endif +N#ifndef __PACKED_STRUCT +N #define __PACKED_STRUCT __packed struct +N#endif +N#ifndef __PACKED_UNION +N #define __PACKED_UNION __packed union +N#endif +N#ifndef __UNALIGNED_UINT32 /* deprecated */ +N #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +N#endif +N#ifndef __UNALIGNED_UINT16_WRITE +N #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +N#endif +N#ifndef __UNALIGNED_UINT16_READ +N #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +N#endif +N#ifndef __UNALIGNED_UINT32_WRITE +N #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +N#endif +N#ifndef __UNALIGNED_UINT32_READ +N #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +N#endif +N#ifndef __ALIGNED +N #define __ALIGNED(x) __attribute__((aligned(x))) +N#endif +N#ifndef __RESTRICT +N #define __RESTRICT __restrict +N#endif +N +N/* ########################### Core Function Access ########################### */ +N/** \ingroup CMSIS_Core_FunctionInterface +N \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions +N @{ +N */ +N +N/** +N \brief Enable IRQ Interrupts +N \details Enables IRQ interrupts by clearing the I-bit in the CPSR. +N Can only be executed in Privileged modes. +N */ +N/* intrinsic void __enable_irq(); */ +N +N +N/** +N \brief Disable IRQ Interrupts +N \details Disables IRQ interrupts by setting the I-bit in the CPSR. +N Can only be executed in Privileged modes. +N */ +N/* intrinsic void __disable_irq(); */ +N +N/** +N \brief Get Control Register +N \details Returns the content of the Control Register. +N \return Control Register value +N */ +N__STATIC_INLINE uint32_t __get_CONTROL(void) +Xstatic __inline uint32_t __get_CONTROL(void) +N{ +N register uint32_t __regControl __ASM("control"); +X register uint32_t __regControl __asm("control"); +N return(__regControl); +N} +N +N +N/** +N \brief Set Control Register +N \details Writes the given value to the Control Register. +N \param [in] control Control Register value to set +N */ +N__STATIC_INLINE void __set_CONTROL(uint32_t control) +Xstatic __inline void __set_CONTROL(uint32_t control) +N{ +N register uint32_t __regControl __ASM("control"); +X register uint32_t __regControl __asm("control"); +N __regControl = control; +N} +N +N +N/** +N \brief Get IPSR Register +N \details Returns the content of the IPSR Register. +N \return IPSR Register value +N */ +N__STATIC_INLINE uint32_t __get_IPSR(void) +Xstatic __inline uint32_t __get_IPSR(void) +N{ +N register uint32_t __regIPSR __ASM("ipsr"); +X register uint32_t __regIPSR __asm("ipsr"); +N return(__regIPSR); +N} +N +N +N/** +N \brief Get APSR Register +N \details Returns the content of the APSR Register. +N \return APSR Register value +N */ +N__STATIC_INLINE uint32_t __get_APSR(void) +Xstatic __inline uint32_t __get_APSR(void) +N{ +N register uint32_t __regAPSR __ASM("apsr"); +X register uint32_t __regAPSR __asm("apsr"); +N return(__regAPSR); +N} +N +N +N/** +N \brief Get xPSR Register +N \details Returns the content of the xPSR Register. +N \return xPSR Register value +N */ +N__STATIC_INLINE uint32_t __get_xPSR(void) +Xstatic __inline uint32_t __get_xPSR(void) +N{ +N register uint32_t __regXPSR __ASM("xpsr"); +X register uint32_t __regXPSR __asm("xpsr"); +N return(__regXPSR); +N} +N +N +N/** +N \brief Get Process Stack Pointer +N \details Returns the current value of the Process Stack Pointer (PSP). +N \return PSP Register value +N */ +N__STATIC_INLINE uint32_t __get_PSP(void) +Xstatic __inline uint32_t __get_PSP(void) +N{ +N register uint32_t __regProcessStackPointer __ASM("psp"); +X register uint32_t __regProcessStackPointer __asm("psp"); +N return(__regProcessStackPointer); +N} +N +N +N/** +N \brief Set Process Stack Pointer +N \details Assigns the given value to the Process Stack Pointer (PSP). +N \param [in] topOfProcStack Process Stack Pointer value to set +N */ +N__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +Xstatic __inline void __set_PSP(uint32_t topOfProcStack) +N{ +N register uint32_t __regProcessStackPointer __ASM("psp"); +X register uint32_t __regProcessStackPointer __asm("psp"); +N __regProcessStackPointer = topOfProcStack; +N} +N +N +N/** +N \brief Get Main Stack Pointer +N \details Returns the current value of the Main Stack Pointer (MSP). +N \return MSP Register value +N */ +N__STATIC_INLINE uint32_t __get_MSP(void) +Xstatic __inline uint32_t __get_MSP(void) +N{ +N register uint32_t __regMainStackPointer __ASM("msp"); +X register uint32_t __regMainStackPointer __asm("msp"); +N return(__regMainStackPointer); +N} +N +N +N/** +N \brief Set Main Stack Pointer +N \details Assigns the given value to the Main Stack Pointer (MSP). +N \param [in] topOfMainStack Main Stack Pointer value to set +N */ +N__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +Xstatic __inline void __set_MSP(uint32_t topOfMainStack) +N{ +N register uint32_t __regMainStackPointer __ASM("msp"); +X register uint32_t __regMainStackPointer __asm("msp"); +N __regMainStackPointer = topOfMainStack; +N} +N +N +N/** +N \brief Get Priority Mask +N \details Returns the current state of the priority mask bit from the Priority Mask Register. +N \return Priority Mask value +N */ +N__STATIC_INLINE uint32_t __get_PRIMASK(void) +Xstatic __inline uint32_t __get_PRIMASK(void) +N{ +N register uint32_t __regPriMask __ASM("primask"); +X register uint32_t __regPriMask __asm("primask"); +N return(__regPriMask); +N} +N +N +N/** +N \brief Set Priority Mask +N \details Assigns the given value to the Priority Mask Register. +N \param [in] priMask Priority Mask +N */ +N__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +Xstatic __inline void __set_PRIMASK(uint32_t priMask) +N{ +N register uint32_t __regPriMask __ASM("primask"); +X register uint32_t __regPriMask __asm("primask"); +N __regPriMask = (priMask); +N} +N +N +N#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7M__ == 1)) || (0L && (__ARM_ARCH_7EM__ == 1)) ) +S +S/** +S \brief Enable FIQ +S \details Enables FIQ interrupts by clearing the F-bit in the CPSR. +S Can only be executed in Privileged modes. +S */ +S#define __enable_fault_irq __enable_fiq +S +S +S/** +S \brief Disable FIQ +S \details Disables FIQ interrupts by setting the F-bit in the CPSR. +S Can only be executed in Privileged modes. +S */ +S#define __disable_fault_irq __disable_fiq +S +S +S/** +S \brief Get Base Priority +S \details Returns the current value of the Base Priority register. +S \return Base Priority register value +S */ +S__STATIC_INLINE uint32_t __get_BASEPRI(void) +S{ +S register uint32_t __regBasePri __ASM("basepri"); +S return(__regBasePri); +S} +S +S +S/** +S \brief Set Base Priority +S \details Assigns the given value to the Base Priority register. +S \param [in] basePri Base Priority value to set +S */ +S__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +S{ +S register uint32_t __regBasePri __ASM("basepri"); +S __regBasePri = (basePri & 0xFFU); +S} +S +S +S/** +S \brief Set Base Priority with condition +S \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, +S or the new value increases the BASEPRI priority level. +S \param [in] basePri Base Priority value to set +S */ +S__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +S{ +S register uint32_t __regBasePriMax __ASM("basepri_max"); +S __regBasePriMax = (basePri & 0xFFU); +S} +S +S +S/** +S \brief Get Fault Mask +S \details Returns the current value of the Fault Mask register. +S \return Fault Mask register value +S */ +S__STATIC_INLINE uint32_t __get_FAULTMASK(void) +S{ +S register uint32_t __regFaultMask __ASM("faultmask"); +S return(__regFaultMask); +S} +S +S +S/** +S \brief Set Fault Mask +S \details Assigns the given value to the Fault Mask register. +S \param [in] faultMask Fault Mask value to set +S */ +S__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +S{ +S register uint32_t __regFaultMask __ASM("faultmask"); +S __regFaultMask = (faultMask & (uint32_t)1U); +S} +S +N#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +X#endif +N +N +N/** +N \brief Get FPSCR +N \details Returns the current value of the Floating Point Status/Control register. +N \return Floating Point Status/Control register value +N */ +N__STATIC_INLINE uint32_t __get_FPSCR(void) +Xstatic __inline uint32_t __get_FPSCR(void) +N{ +N#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ +N (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +X#if ((1L && (0U == 1U)) && (1L && (0U == 1U)) ) +S register uint32_t __regfpscr __ASM("fpscr"); +S return(__regfpscr); +N#else +N return(0U); +N#endif +N} +N +N +N/** +N \brief Set FPSCR +N \details Assigns the given value to the Floating Point Status/Control register. +N \param [in] fpscr Floating Point Status/Control value to set +N */ +N__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +Xstatic __inline void __set_FPSCR(uint32_t fpscr) +N{ +N#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ +N (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +X#if ((1L && (0U == 1U)) && (1L && (0U == 1U)) ) +S register uint32_t __regfpscr __ASM("fpscr"); +S __regfpscr = (fpscr); +N#else +N (void)fpscr; +N#endif +N} +N +N +N/*@} end of CMSIS_Core_RegAccFunctions */ +N +N +N/* ########################## Core Instruction Access ######################### */ +N/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface +N Access to dedicated instructions +N @{ +N*/ +N +N/** +N \brief No Operation +N \details No Operation does nothing. This instruction can be used for code alignment purposes. +N */ +N#define __NOP __nop +N +N +N/** +N \brief Wait For Interrupt +N \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. +N */ +N#define __WFI __wfi +N +N +N/** +N \brief Wait For Event +N \details Wait For Event is a hint instruction that permits the processor to enter +N a low-power state until one of a number of events occurs. +N */ +N#define __WFE __wfe +N +N +N/** +N \brief Send Event +N \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. +N */ +N#define __SEV __sev +N +N +N/** +N \brief Instruction Synchronization Barrier +N \details Instruction Synchronization Barrier flushes the pipeline in the processor, +N so that all instructions following the ISB are fetched from cache or memory, +N after the instruction has been completed. +N */ +N#define __ISB() do {\ +N __schedule_barrier();\ +N __isb(0xF);\ +N __schedule_barrier();\ +N } while (0U) +X#define __ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U) +N +N/** +N \brief Data Synchronization Barrier +N \details Acts as a special kind of Data Memory Barrier. +N It completes when all explicit memory accesses before this instruction complete. +N */ +N#define __DSB() do {\ +N __schedule_barrier();\ +N __dsb(0xF);\ +N __schedule_barrier();\ +N } while (0U) +X#define __DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U) +N +N/** +N \brief Data Memory Barrier +N \details Ensures the apparent order of the explicit memory operations before +N and after the instruction, without ensuring their completion. +N */ +N#define __DMB() do {\ +N __schedule_barrier();\ +N __dmb(0xF);\ +N __schedule_barrier();\ +N } while (0U) +X#define __DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U) +N +N +N/** +N \brief Reverse byte order (32 bit) +N \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. +N \param [in] value Value to reverse +N \return Reversed value +N */ +N#define __REV __rev +N +N +N/** +N \brief Reverse byte order (16 bit) +N \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. +N \param [in] value Value to reverse +N \return Reversed value +N */ +N#ifndef __NO_EMBEDDED_ASM +N__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +X__attribute__((section(".rev16_text"))) static __inline __asm uint32_t __REV16(uint32_t value) +N{ +N rev16 r0, r0 +N bx lr +N} +N#endif +N +N +N/** +N \brief Reverse byte order (16 bit) +N \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. +N \param [in] value Value to reverse +N \return Reversed value +N */ +N#ifndef __NO_EMBEDDED_ASM +N__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +X__attribute__((section(".revsh_text"))) static __inline __asm int16_t __REVSH(int16_t value) +N{ +N revsh r0, r0 +N bx lr +N} +N#endif +N +N +N/** +N \brief Rotate Right in unsigned value (32 bit) +N \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. +N \param [in] op1 Value to rotate +N \param [in] op2 Number of Bits to rotate +N \return Rotated value +N */ +N#define __ROR __ror +N +N +N/** +N \brief Breakpoint +N \details Causes the processor to enter Debug state. +N Debug tools can use this to investigate system state when the instruction at a particular address is reached. +N \param [in] value is ignored by the processor. +N If required, a debugger can use it to store additional information about the breakpoint. +N */ +N#define __BKPT(value) __breakpoint(value) +N +N +N/** +N \brief Reverse bit order of value +N \details Reverses the bit order of the given value. +N \param [in] value Value to reverse +N \return Reversed value +N */ +N#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7M__ == 1)) || (0L && (__ARM_ARCH_7EM__ == 1)) ) +S #define __RBIT __rbit +N#else +N__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +X__attribute__((always_inline)) static __inline uint32_t __RBIT(uint32_t value) +N{ +N uint32_t result; +N uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ +N +N result = value; /* r will be reversed bits of v; first get LSB of v */ +N for (value >>= 1U; value != 0U; value >>= 1U) +N { +N result <<= 1U; +N result |= value & 1U; +N s--; +N } +N result <<= s; /* shift when v's highest bits are zero */ +N return result; +N} +N#endif +N +N +N/** +N \brief Count leading zeros +N \details Counts the number of leading zeros of a data value. +N \param [in] value Value to count the leading zeros +N \return number of leading zeros in value +N */ +N#define __CLZ __clz +N +N +N#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7M__ == 1)) || (0L && (__ARM_ARCH_7EM__ == 1)) ) +S +S/** +S \brief LDR Exclusive (8 bit) +S \details Executes a exclusive LDR instruction for 8 bit value. +S \param [in] ptr Pointer to data +S \return value of type uint8_t at (*ptr) +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +S#else +S #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +S#endif +S +S +S/** +S \brief LDR Exclusive (16 bit) +S \details Executes a exclusive LDR instruction for 16 bit values. +S \param [in] ptr Pointer to data +S \return value of type uint16_t at (*ptr) +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +S#else +S #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +S#endif +S +S +S/** +S \brief LDR Exclusive (32 bit) +S \details Executes a exclusive LDR instruction for 32 bit values. +S \param [in] ptr Pointer to data +S \return value of type uint32_t at (*ptr) +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +S#else +S #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +S#endif +S +S +S/** +S \brief STR Exclusive (8 bit) +S \details Executes a exclusive STR instruction for 8 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S \return 0 Function succeeded +S \return 1 Function failed +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __STREXB(value, ptr) __strex(value, ptr) +S#else +S #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +S#endif +S +S +S/** +S \brief STR Exclusive (16 bit) +S \details Executes a exclusive STR instruction for 16 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S \return 0 Function succeeded +S \return 1 Function failed +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __STREXH(value, ptr) __strex(value, ptr) +S#else +S #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +S#endif +S +S +S/** +S \brief STR Exclusive (32 bit) +S \details Executes a exclusive STR instruction for 32 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S \return 0 Function succeeded +S \return 1 Function failed +S */ +S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) +S #define __STREXW(value, ptr) __strex(value, ptr) +S#else +S #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +S#endif +S +S +S/** +S \brief Remove the exclusive lock +S \details Removes the exclusive lock which is created by LDREX. +S */ +S#define __CLREX __clrex +S +S +S/** +S \brief Signed Saturate +S \details Saturates a signed value. +S \param [in] value Value to be saturated +S \param [in] sat Bit position to saturate to (1..32) +S \return Saturated value +S */ +S#define __SSAT __ssat +S +S +S/** +S \brief Unsigned Saturate +S \details Saturates an unsigned value. +S \param [in] value Value to be saturated +S \param [in] sat Bit position to saturate to (0..31) +S \return Saturated value +S */ +S#define __USAT __usat +S +S +S/** +S \brief Rotate Right with Extend (32 bit) +S \details Moves each bit of a bitstring right by one bit. +S The carry input is shifted in at the left end of the bitstring. +S \param [in] value Value to rotate +S \return Rotated value +S */ +S#ifndef __NO_EMBEDDED_ASM +S__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +S{ +S rrx r0, r0 +S bx lr +S} +S#endif +S +S +S/** +S \brief LDRT Unprivileged (8 bit) +S \details Executes a Unprivileged LDRT instruction for 8 bit value. +S \param [in] ptr Pointer to data +S \return value of type uint8_t at (*ptr) +S */ +S#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) +S +S +S/** +S \brief LDRT Unprivileged (16 bit) +S \details Executes a Unprivileged LDRT instruction for 16 bit values. +S \param [in] ptr Pointer to data +S \return value of type uint16_t at (*ptr) +S */ +S#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) +S +S +S/** +S \brief LDRT Unprivileged (32 bit) +S \details Executes a Unprivileged LDRT instruction for 32 bit values. +S \param [in] ptr Pointer to data +S \return value of type uint32_t at (*ptr) +S */ +S#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) +S +S +S/** +S \brief STRT Unprivileged (8 bit) +S \details Executes a Unprivileged STRT instruction for 8 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S */ +S#define __STRBT(value, ptr) __strt(value, ptr) +S +S +S/** +S \brief STRT Unprivileged (16 bit) +S \details Executes a Unprivileged STRT instruction for 16 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S */ +S#define __STRHT(value, ptr) __strt(value, ptr) +S +S +S/** +S \brief STRT Unprivileged (32 bit) +S \details Executes a Unprivileged STRT instruction for 32 bit values. +S \param [in] value Value to store +S \param [in] ptr Pointer to location +S */ +S#define __STRT(value, ptr) __strt(value, ptr) +S +N#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +X#else +N +N/** +N \brief Signed Saturate +N \details Saturates a signed value. +N \param [in] value Value to be saturated +N \param [in] sat Bit position to saturate to (1..32) +N \return Saturated value +N */ +N__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +X__attribute__((always_inline)) static __inline int32_t __SSAT(int32_t val, uint32_t sat) +N{ +N if ((sat >= 1U) && (sat <= 32U)) +N { +N const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); +N const int32_t min = -1 - max ; +N if (val > max) +N { +N return max; +N } +N else if (val < min) +N { +N return min; +N } +N } +N return val; +N} +N +N/** +N \brief Unsigned Saturate +N \details Saturates an unsigned value. +N \param [in] value Value to be saturated +N \param [in] sat Bit position to saturate to (0..31) +N \return Saturated value +N */ +N__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +X__attribute__((always_inline)) static __inline uint32_t __USAT(int32_t val, uint32_t sat) +N{ +N if (sat <= 31U) +N { +N const uint32_t max = ((1U << sat) - 1U); +N if (val > (int32_t)max) +N { +N return max; +N } +N else if (val < 0) +N { +N return 0U; +N } +N } +N return (uint32_t)val; +N} +N +N#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +X#endif +N +N/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ +N +N +N/* ################### Compiler specific Intrinsics ########################### */ +N/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics +N Access to dedicated SIMD instructions +N @{ +N*/ +N +N#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +X#if ((0L && (__ARM_ARCH_7EM__ == 1)) ) +S +S#define __SADD8 __sadd8 +S#define __QADD8 __qadd8 +S#define __SHADD8 __shadd8 +S#define __UADD8 __uadd8 +S#define __UQADD8 __uqadd8 +S#define __UHADD8 __uhadd8 +S#define __SSUB8 __ssub8 +S#define __QSUB8 __qsub8 +S#define __SHSUB8 __shsub8 +S#define __USUB8 __usub8 +S#define __UQSUB8 __uqsub8 +S#define __UHSUB8 __uhsub8 +S#define __SADD16 __sadd16 +S#define __QADD16 __qadd16 +S#define __SHADD16 __shadd16 +S#define __UADD16 __uadd16 +S#define __UQADD16 __uqadd16 +S#define __UHADD16 __uhadd16 +S#define __SSUB16 __ssub16 +S#define __QSUB16 __qsub16 +S#define __SHSUB16 __shsub16 +S#define __USUB16 __usub16 +S#define __UQSUB16 __uqsub16 +S#define __UHSUB16 __uhsub16 +S#define __SASX __sasx +S#define __QASX __qasx +S#define __SHASX __shasx +S#define __UASX __uasx +S#define __UQASX __uqasx +S#define __UHASX __uhasx +S#define __SSAX __ssax +S#define __QSAX __qsax +S#define __SHSAX __shsax +S#define __USAX __usax +S#define __UQSAX __uqsax +S#define __UHSAX __uhsax +S#define __USAD8 __usad8 +S#define __USADA8 __usada8 +S#define __SSAT16 __ssat16 +S#define __USAT16 __usat16 +S#define __UXTB16 __uxtb16 +S#define __UXTAB16 __uxtab16 +S#define __SXTB16 __sxtb16 +S#define __SXTAB16 __sxtab16 +S#define __SMUAD __smuad +S#define __SMUADX __smuadx +S#define __SMLAD __smlad +S#define __SMLADX __smladx +S#define __SMLALD __smlald +S#define __SMLALDX __smlaldx +S#define __SMUSD __smusd +S#define __SMUSDX __smusdx +S#define __SMLSD __smlsd +S#define __SMLSDX __smlsdx +S#define __SMLSLD __smlsld +S#define __SMLSLDX __smlsldx +S#define __SEL __sel +S#define __QADD __qadd +S#define __QSUB __qsub +S +S#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ +S ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) +X#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) +S +S#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ +S ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) +X#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) +S +S#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ +S ((int64_t)(ARG3) << 32U) ) >> 32U)) +X#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U) ) >> 32U)) +S +N#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +N/*@} end of group CMSIS_SIMD_intrinsics */ +N +N +N#endif /* __CMSIS_ARMCC_H */ +L 35 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h" 2 +N +N +N/* +N * Arm Compiler 6.6 LTM (armclang) +N */ +N#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) +X#elif 1L && (5060750 >= 6010050) && (5060750 < 6100100) +S #include "cmsis_armclang_ltm.h" +S +S /* +S * Arm Compiler above 6.10.1 (armclang) +S */ +S#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) +S #include "cmsis_armclang.h" +S +S +S/* +S * GNU Compiler +S */ +S#elif defined ( __GNUC__ ) +S #include "cmsis_gcc.h" +S +S +S/* +S * IAR Compiler +S */ +S#elif defined ( __ICCARM__ ) +S #include +S +S +S/* +S * TI Arm Compiler +S */ +S#elif defined ( __TI_ARM__ ) +S #include +S +S #ifndef __ASM +S #define __ASM __asm +S #endif +S #ifndef __INLINE +S #define __INLINE inline +S #endif +S #ifndef __STATIC_INLINE +S #define __STATIC_INLINE static inline +S #endif +S #ifndef __STATIC_FORCEINLINE +S #define __STATIC_FORCEINLINE __STATIC_INLINE +S #endif +S #ifndef __NO_RETURN +S #define __NO_RETURN __attribute__((noreturn)) +S #endif +S #ifndef __USED +S #define __USED __attribute__((used)) +S #endif +S #ifndef __WEAK +S #define __WEAK __attribute__((weak)) +S #endif +S #ifndef __PACKED +S #define __PACKED __attribute__((packed)) +S #endif +S #ifndef __PACKED_STRUCT +S #define __PACKED_STRUCT struct __attribute__((packed)) +S #endif +S #ifndef __PACKED_UNION +S #define __PACKED_UNION union __attribute__((packed)) +S #endif +S #ifndef __UNALIGNED_UINT32 /* deprecated */ +S struct __attribute__((packed)) T_UINT32 { uint32_t v; }; +S #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +S #endif +S #ifndef __UNALIGNED_UINT16_WRITE +S __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +S #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT16_READ +S __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +S #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __UNALIGNED_UINT32_WRITE +S __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +S #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT32_READ +S __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +S #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __ALIGNED +S #define __ALIGNED(x) __attribute__((aligned(x))) +S #endif +S #ifndef __RESTRICT +S #define __RESTRICT __restrict +S #endif +S +S +S/* +S * TASKING Compiler +S */ +S#elif defined ( __TASKING__ ) +S /* +S * The CMSIS functions have been implemented as intrinsics in the compiler. +S * Please use "carm -?i" to get an up to date list of all intrinsics, +S * Including the CMSIS ones. +S */ +S +S #ifndef __ASM +S #define __ASM __asm +S #endif +S #ifndef __INLINE +S #define __INLINE inline +S #endif +S #ifndef __STATIC_INLINE +S #define __STATIC_INLINE static inline +S #endif +S #ifndef __STATIC_FORCEINLINE +S #define __STATIC_FORCEINLINE __STATIC_INLINE +S #endif +S #ifndef __NO_RETURN +S #define __NO_RETURN __attribute__((noreturn)) +S #endif +S #ifndef __USED +S #define __USED __attribute__((used)) +S #endif +S #ifndef __WEAK +S #define __WEAK __attribute__((weak)) +S #endif +S #ifndef __PACKED +S #define __PACKED __packed__ +S #endif +S #ifndef __PACKED_STRUCT +S #define __PACKED_STRUCT struct __packed__ +S #endif +S #ifndef __PACKED_UNION +S #define __PACKED_UNION union __packed__ +S #endif +S #ifndef __UNALIGNED_UINT32 /* deprecated */ +S struct __packed__ T_UINT32 { uint32_t v; }; +S #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +S #endif +S #ifndef __UNALIGNED_UINT16_WRITE +S __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +S #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT16_READ +S __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +S #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __UNALIGNED_UINT32_WRITE +S __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +S #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT32_READ +S __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +S #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __ALIGNED +S #define __ALIGNED(x) __align(x) +S #endif +S #ifndef __RESTRICT +S #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. +S #define __RESTRICT +S #endif +S +S +S/* +S * COSMIC Compiler +S */ +S#elif defined ( __CSMC__ ) +S #include +S +S #ifndef __ASM +S #define __ASM _asm +S #endif +S #ifndef __INLINE +S #define __INLINE inline +S #endif +S #ifndef __STATIC_INLINE +S #define __STATIC_INLINE static inline +S #endif +S #ifndef __STATIC_FORCEINLINE +S #define __STATIC_FORCEINLINE __STATIC_INLINE +S #endif +S #ifndef __NO_RETURN +S // NO RETURN is automatically detected hence no warning here +S #define __NO_RETURN +S #endif +S #ifndef __USED +S #warning No compiler specific solution for __USED. __USED is ignored. +S #define __USED +S #endif +S #ifndef __WEAK +S #define __WEAK __weak +S #endif +S #ifndef __PACKED +S #define __PACKED @packed +S #endif +S #ifndef __PACKED_STRUCT +S #define __PACKED_STRUCT @packed struct +S #endif +S #ifndef __PACKED_UNION +S #define __PACKED_UNION @packed union +S #endif +S #ifndef __UNALIGNED_UINT32 /* deprecated */ +S @packed struct T_UINT32 { uint32_t v; }; +S #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +S #endif +S #ifndef __UNALIGNED_UINT16_WRITE +S __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +S #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT16_READ +S __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +S #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __UNALIGNED_UINT32_WRITE +S __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +S #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +S #endif +S #ifndef __UNALIGNED_UINT32_READ +S __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +S #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +S #endif +S #ifndef __ALIGNED +S #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. +S #define __ALIGNED(x) +S #endif +S #ifndef __RESTRICT +S #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. +S #define __RESTRICT +S #endif +S +S +S#else +S #error Unknown compiler. +N#endif +N +N +N#endif /* __CMSIS_COMPILER_H */ +N +L 116 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h" 2 +N +N +N#ifdef __cplusplus +S} +N#endif +N +N#endif /* __CORE_CM0_H_GENERIC */ +N +N#ifndef __CMSIS_GENERIC +N +N#ifndef __CORE_CM0_H_DEPENDANT +N#define __CORE_CM0_H_DEPENDANT +N +N#ifdef __cplusplus +S extern "C" { +N#endif +N +N/* check device defines and use defaults */ +N#if defined __CHECK_DEVICE_DEFINES +X#if 0L +S #ifndef __CM0_REV +S #define __CM0_REV 0x0000U +S #warning "__CM0_REV not defined in device header file; using default!" +S #endif +S +S #ifndef __NVIC_PRIO_BITS +S #define __NVIC_PRIO_BITS 2U +S #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +S #endif +S +S #ifndef __Vendor_SysTickConfig +S #define __Vendor_SysTickConfig 0U +S #warning "__Vendor_SysTickConfig not defined in device header file; using default!" +S #endif +N#endif +N +N/* IO definitions (access restrictions to peripheral registers) */ +N/** +N \defgroup CMSIS_glob_defs CMSIS Global Defines +N +N IO Type Qualifiers are used +N \li to specify the access to peripheral variables. +N \li for automatic generation of peripheral register debug information. +N*/ +N#ifdef __cplusplus +S #define __I volatile /*!< Defines 'read only' permissions */ +N#else +N #define __I volatile const /*!< Defines 'read only' permissions */ +N#endif +N#define __O volatile /*!< Defines 'write only' permissions */ +N#define __IO volatile /*!< Defines 'read / write' permissions */ +N +N/* following defines should be used for structure members */ +N#define __IM volatile const /*! Defines 'read only' structure member permissions */ +N#define __OM volatile /*! Defines 'write only' structure member permissions */ +N#define __IOM volatile /*! Defines 'read / write' structure member permissions */ +N +N/*@} end of group Cortex_M0 */ +N +N +N +N/******************************************************************************* +N * Register Abstraction +N Core Register contain: +N - Core Register +N - Core NVIC Register +N - Core SCB Register +N - Core SysTick Register +N ******************************************************************************/ +N/** +N \defgroup CMSIS_core_register Defines and Type Definitions +N \brief Type definitions and defines for Cortex-M processor based devices. +N*/ +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_CORE Status and Control Registers +N \brief Core Register type definitions. +N @{ +N */ +N +N/** +N \brief Union type to access the Application Program Status Register (APSR). +N */ +Ntypedef union +N{ +N struct +N { +N uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ +N uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ +N uint32_t C:1; /*!< bit: 29 Carry condition code flag */ +N uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ +N uint32_t N:1; /*!< bit: 31 Negative condition code flag */ +N } b; /*!< Structure used for bit access */ +N uint32_t w; /*!< Type used for word access */ +N} APSR_Type; +N +N/* APSR Register Definitions */ +N#define APSR_N_Pos 31U /*!< APSR: N Position */ +N#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ +N +N#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +N#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ +N +N#define APSR_C_Pos 29U /*!< APSR: C Position */ +N#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ +N +N#define APSR_V_Pos 28U /*!< APSR: V Position */ +N#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ +N +N +N/** +N \brief Union type to access the Interrupt Program Status Register (IPSR). +N */ +Ntypedef union +N{ +N struct +N { +N uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +N uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ +N } b; /*!< Structure used for bit access */ +N uint32_t w; /*!< Type used for word access */ +N} IPSR_Type; +N +N/* IPSR Register Definitions */ +N#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +N#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ +N +N +N/** +N \brief Union type to access the Special-Purpose Program Status Registers (xPSR). +N */ +Ntypedef union +N{ +N struct +N { +N uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +N uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +N uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ +N uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ +N uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ +N uint32_t C:1; /*!< bit: 29 Carry condition code flag */ +N uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ +N uint32_t N:1; /*!< bit: 31 Negative condition code flag */ +N } b; /*!< Structure used for bit access */ +N uint32_t w; /*!< Type used for word access */ +N} xPSR_Type; +N +N/* xPSR Register Definitions */ +N#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +N#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ +N +N#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +N#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ +N +N#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +N#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ +N +N#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +N#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ +N +N#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +N#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ +N +N#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +N#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ +N +N +N/** +N \brief Union type to access the Control Registers (CONTROL). +N */ +Ntypedef union +N{ +N struct +N { +N uint32_t _reserved0:1; /*!< bit: 0 Reserved */ +N uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ +N uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ +N } b; /*!< Structure used for bit access */ +N uint32_t w; /*!< Type used for word access */ +N} CONTROL_Type; +N +N/* CONTROL Register Definitions */ +N#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +N#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ +N +N/*@} end of group CMSIS_CORE */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) +N \brief Type definitions for the NVIC Registers +N @{ +N */ +N +N/** +N \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). +N */ +Ntypedef struct +N{ +N __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ +X volatile uint32_t ISER[1U]; +N uint32_t RESERVED0[31U]; +N __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ +X volatile uint32_t ICER[1U]; +N uint32_t RESERVED1[31U]; +N __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ +X volatile uint32_t ISPR[1U]; +N uint32_t RESERVED2[31U]; +N __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ +X volatile uint32_t ICPR[1U]; +N uint32_t RESERVED3[31U]; +N uint32_t RESERVED4[64U]; +N __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +X volatile uint32_t IP[8U]; +N} NVIC_Type; +N +N/*@} end of group CMSIS_NVIC */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_SCB System Control Block (SCB) +N \brief Type definitions for the System Control Block Registers +N @{ +N */ +N +N/** +N \brief Structure type to access the System Control Block (SCB). +N */ +Ntypedef struct +N{ +N __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ +X volatile const uint32_t CPUID; +N __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +X volatile uint32_t ICSR; +N uint32_t RESERVED0; +N __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ +X volatile uint32_t AIRCR; +N __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ +X volatile uint32_t SCR; +N __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ +X volatile uint32_t CCR; +N uint32_t RESERVED1; +N __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ +X volatile uint32_t SHP[2U]; +N __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +X volatile uint32_t SHCSR; +N} SCB_Type; +N +N/* SCB CPUID Register Definitions */ +N#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +N#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ +N +N#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +N#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ +N +N#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +N#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ +N +N#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +N#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ +N +N#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +N#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ +N +N/* SCB Interrupt Control State Register Definitions */ +N#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +N#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ +N +N#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +N#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ +N +N#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +N#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ +N +N#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +N#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ +N +N#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +N#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ +N +N#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +N#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ +N +N#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +N#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ +N +N#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +N#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ +N +N#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +N#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ +N +N/* SCB Application Interrupt and Reset Control Register Definitions */ +N#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +N#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ +N +N#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +N#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ +N +N#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +N#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ +N +N#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +N#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ +N +N#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +N#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ +N +N/* SCB System Control Register Definitions */ +N#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +N#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ +N +N#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +N#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ +N +N#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +N#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ +N +N/* SCB Configuration Control Register Definitions */ +N#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +N#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ +N +N#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +N#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ +N +N/* SCB System Handler Control and State Register Definitions */ +N#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +N#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ +N +N/*@} end of group CMSIS_SCB */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_SysTick System Tick Timer (SysTick) +N \brief Type definitions for the System Timer Registers. +N @{ +N */ +N +N/** +N \brief Structure type to access the System Timer (SysTick). +N */ +Ntypedef struct +N{ +N __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ +X volatile uint32_t CTRL; +N __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ +X volatile uint32_t LOAD; +N __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ +X volatile uint32_t VAL; +N __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +X volatile const uint32_t CALIB; +N} SysTick_Type; +N +N/* SysTick Control / Status Register Definitions */ +N#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +N#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ +N +N#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +N#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ +N +N#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +N#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ +N +N#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +N#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ +N +N/* SysTick Reload Register Definitions */ +N#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +N#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ +N +N/* SysTick Current Register Definitions */ +N#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +N#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ +N +N/* SysTick Calibration Register Definitions */ +N#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +N#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ +N +N#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +N#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ +N +N#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +N#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ +N +N/*@} end of group CMSIS_SysTick */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) +N \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. +N Therefore they are not covered by the Cortex-M0 header file. +N @{ +N */ +N/*@} end of group CMSIS_CoreDebug */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_core_bitfield Core register bit field macros +N \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). +N @{ +N */ +N +N/** +N \brief Mask and shift a bit field value for use in a register bit range. +N \param[in] field Name of the register bit field. +N \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. +N \return Masked and shifted value. +N*/ +N#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) +N +N/** +N \brief Mask and shift a register value to extract a bit filed value. +N \param[in] field Name of the register bit field. +N \param[in] value Value of register. This parameter is interpreted as an uint32_t type. +N \return Masked and shifted bit field value. +N*/ +N#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) +N +N/*@} end of group CMSIS_core_bitfield */ +N +N +N/** +N \ingroup CMSIS_core_register +N \defgroup CMSIS_core_base Core Definitions +N \brief Definitions for base addresses, unions, and structures. +N @{ +N */ +N +N/* Memory mapping of Core Hardware */ +N#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +N#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +N#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +N#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +N +N#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +N#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +N#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +N +N +N/*@} */ +N +N +N +N/******************************************************************************* +N * Hardware Abstraction Layer +N Core Function Interface contains: +N - Core NVIC Functions +N - Core SysTick Functions +N - Core Register Access Functions +N ******************************************************************************/ +N/** +N \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +N*/ +N +N +N +N/* ########################## NVIC functions #################################### */ +N/** +N \ingroup CMSIS_Core_FunctionInterface +N \defgroup CMSIS_Core_NVICFunctions NVIC Functions +N \brief Functions that manage interrupts and exceptions via the NVIC. +N @{ +N */ +N +N#ifdef CMSIS_NVIC_VIRTUAL +S #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +S #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +S #endif +S #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +N#else +N #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +N #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +N #define NVIC_EnableIRQ __NVIC_EnableIRQ +N #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +N #define NVIC_DisableIRQ __NVIC_DisableIRQ +N #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +N #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +N #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +N/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ +N #define NVIC_SetPriority __NVIC_SetPriority +N #define NVIC_GetPriority __NVIC_GetPriority +N #define NVIC_SystemReset __NVIC_SystemReset +N#endif /* CMSIS_NVIC_VIRTUAL */ +N +N#ifdef CMSIS_VECTAB_VIRTUAL +S #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +S #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +S #endif +S #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +N#else +N #define NVIC_SetVector __NVIC_SetVector +N #define NVIC_GetVector __NVIC_GetVector +N#endif /* (CMSIS_VECTAB_VIRTUAL) */ +N +N#define NVIC_USER_IRQ_OFFSET 16 +N +N +N/* The following EXC_RETURN values are saved the LR on exception entry */ +N#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +N#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +N#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +N +N +N/* Interrupt Priorities are WORD accessible only under Armv6-M */ +N/* The following MACROS handle generation of the register offset and byte masks */ +N#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +N#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +N#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) +N +N#define __NVIC_SetPriorityGrouping(X) (void)(X) +N#define __NVIC_GetPriorityGrouping() (0U) +N +N/** +N \brief Enable Interrupt +N \details Enables a device specific interrupt in the NVIC interrupt controller. +N \param [in] IRQn Device specific interrupt number. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +Xstatic __inline void __NVIC_EnableIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +N } +N} +N +N +N/** +N \brief Get Interrupt Enable status +N \details Returns a device specific interrupt enable status from the NVIC interrupt controller. +N \param [in] IRQn Device specific interrupt number. +N \return 0 Interrupt is not enabled. +N \return 1 Interrupt is enabled. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +Xstatic __inline uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +X return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +N } +N else +N { +N return(0U); +N } +N} +N +N +N/** +N \brief Disable Interrupt +N \details Disables a device specific interrupt in the NVIC interrupt controller. +N \param [in] IRQn Device specific interrupt number. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +Xstatic __inline void __NVIC_DisableIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +N __DSB(); +X do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); +N __ISB(); +X do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U); +N } +N} +N +N +N/** +N \brief Get Pending Interrupt +N \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. +N \param [in] IRQn Device specific interrupt number. +N \return 0 Interrupt status is not pending. +N \return 1 Interrupt status is pending. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +Xstatic __inline uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +X return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +N } +N else +N { +N return(0U); +N } +N} +N +N +N/** +N \brief Set Pending Interrupt +N \details Sets the pending bit of a device specific interrupt in the NVIC pending register. +N \param [in] IRQn Device specific interrupt number. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +Xstatic __inline void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +N } +N} +N +N +N/** +N \brief Clear Pending Interrupt +N \details Clears the pending bit of a device specific interrupt in the NVIC pending register. +N \param [in] IRQn Device specific interrupt number. +N \note IRQn must not be negative. +N */ +N__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +Xstatic __inline void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +N } +N} +N +N +N/** +N \brief Set Interrupt Priority +N \details Sets the priority of a device specific interrupt or a processor exception. +N The interrupt number can be positive to specify a device specific interrupt, +N or negative to specify a processor exception. +N \param [in] IRQn Interrupt number. +N \param [in] priority Priority to set. +N \note The priority cannot be set for every processor exception. +N */ +N__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +Xstatic __inline void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +N{ +N if ((int32_t)(IRQn) >= 0) +N { +N NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | +X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] = ((uint32_t)(((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | +N (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); +X (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); +N } +N else +N { +N SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | +X ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] = ((uint32_t)(((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | +N (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); +X (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); +N } +N} +N +N +N/** +N \brief Get Interrupt Priority +N \details Reads the priority of a device specific interrupt or a processor exception. +N The interrupt number can be positive to specify a device specific interrupt, +N or negative to specify a processor exception. +N \param [in] IRQn Interrupt number. +N \return Interrupt Priority. +N Value is aligned automatically to the implemented priority bits of the microcontroller. +N */ +N__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +Xstatic __inline uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +N{ +N +N if ((int32_t)(IRQn) >= 0) +N { +N return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); +X return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[ ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); +N } +N else +N { +N return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); +X return((uint32_t)(((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); +N } +N} +N +N +N/** +N \brief Encode Priority +N \details Encodes the priority for an interrupt with the given priority group, +N preemptive priority value, and subpriority value. +N In case of a conflict between priority grouping and available +N priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +N \param [in] PriorityGroup Used priority group. +N \param [in] PreemptPriority Preemptive priority value (starting from 0). +N \param [in] SubPriority Subpriority value (starting from 0). +N \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). +N */ +N__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +Xstatic __inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +N{ +N uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ +N uint32_t PreemptPriorityBits; +N uint32_t SubPriorityBits; +N +N PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); +X PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); +N SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); +X SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); +N +N return ( +N ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | +N ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) +N ); +N} +N +N +N/** +N \brief Decode Priority +N \details Decodes an interrupt priority value with a given priority group to +N preemptive priority value and subpriority value. +N In case of a conflict between priority grouping and available +N priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. +N \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). +N \param [in] PriorityGroup Used priority group. +N \param [out] pPreemptPriority Preemptive priority value (starting from 0). +N \param [out] pSubPriority Subpriority value (starting from 0). +N */ +N__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +Xstatic __inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +N{ +N uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ +N uint32_t PreemptPriorityBits; +N uint32_t SubPriorityBits; +N +N PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); +X PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); +N SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); +X SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); +N +N *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); +N *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +N} +N +N +N +N/** +N \brief Set Interrupt Vector +N \details Sets an interrupt vector in SRAM based interrupt vector table. +N The interrupt number can be positive to specify a device specific interrupt, +N or negative to specify a processor exception. +N Address 0 must be mapped to SRAM. +N \param [in] IRQn Interrupt number +N \param [in] vector Address of interrupt handler function +N */ +N__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +Xstatic __inline void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +N{ +N uint32_t vectors = 0x0U; +N (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; +X (* (int *) (vectors + ((int32_t)IRQn + 16) * 4)) = vector; +N} +N +N +N/** +N \brief Get Interrupt Vector +N \details Reads an interrupt vector from interrupt vector table. +N The interrupt number can be positive to specify a device specific interrupt, +N or negative to specify a processor exception. +N \param [in] IRQn Interrupt number. +N \return Address of interrupt handler function +N */ +N__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +Xstatic __inline uint32_t __NVIC_GetVector(IRQn_Type IRQn) +N{ +N uint32_t vectors = 0x0U; +N return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +X return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + 16) * 4)); +N} +N +N +N/** +N \brief System Reset +N \details Initiates a system reset request to reset the MCU. +N */ +N__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +X__declspec(noreturn) static __inline void __NVIC_SystemReset(void) +N{ +N __DSB(); /* Ensure all outstanding memory accesses included +X do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); +N buffered write are completed before reset */ +N SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | +X ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR = ((0x5FAUL << 16U) | +N SCB_AIRCR_SYSRESETREQ_Msk); +X (1UL << 2U)); +N __DSB(); /* Ensure completion of memory access */ +X do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); +N +N for(;;) /* wait until reset */ +N { +N __NOP(); +X __nop(); +N } +N} +N +N/*@} end of CMSIS_Core_NVICFunctions */ +N +N +N/* ########################## FPU functions #################################### */ +N/** +N \ingroup CMSIS_Core_FunctionInterface +N \defgroup CMSIS_Core_FpuFunctions FPU Functions +N \brief Function that provides FPU type. +N @{ +N */ +N +N/** +N \brief get FPU type +N \details returns the FPU type +N \returns +N - \b 0: No FPU +N - \b 1: Single precision FPU +N - \b 2: Double + Single precision FPU +N */ +N__STATIC_INLINE uint32_t SCB_GetFPUType(void) +Xstatic __inline uint32_t SCB_GetFPUType(void) +N{ +N return 0U; /* No FPU */ +N} +N +N +N/*@} end of CMSIS_Core_FpuFunctions */ +N +N +N +N/* ################################## SysTick function ############################################ */ +N/** +N \ingroup CMSIS_Core_FunctionInterface +N \defgroup CMSIS_Core_SysTickFunctions SysTick Functions +N \brief Functions that configure the System. +N @{ +N */ +N +N#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) +X#if 1L && (0U == 0U) +N +N/** +N \brief System Tick Configuration +N \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. +N Counter is in free running mode to generate periodic interrupts. +N \param [in] ticks Number of ticks between two interrupts. +N \return 0 Function succeeded. +N \return 1 Function failed. +N \note When the variable __Vendor_SysTickConfig is set to 1, then the +N function SysTick_Config is not included. In this case, the file device.h +N must contain a vendor-specific implementation of this function. +N */ +N__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +Xstatic __inline uint32_t SysTick_Config(uint32_t ticks) +N{ +N if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) +X if ((ticks - 1UL) > (0xFFFFFFUL )) +N { +N return (1UL); /* Reload value impossible */ +N } +N +N SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ +X ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->LOAD = (uint32_t)(ticks - 1UL); +N NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ +X __NVIC_SetPriority (SysTick_IRQn, (1UL << 2U) - 1UL); +N SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ +X ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->VAL = 0UL; +N SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | +X ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL = (1UL << 2U) | +N SysTick_CTRL_TICKINT_Msk | +X (1UL << 1U) | +N SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ +X (1UL ); +N return (0UL); /* Function successful */ +N} +N +N#endif +N +N/*@} end of CMSIS_Core_SysTickFunctions */ +N +N +N +N +N#ifdef __cplusplus +S} +N#endif +N +N#endif /* __CORE_CM0_H_DEPENDANT */ +N +N#endif /* __CMSIS_GENERIC */ +L 122 "..\..\src\sdk\include\M0\ArmCM0.h" 2 +N#include "system_ARMCM0.h" /* System Header */ +L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include\system_ARMCM0.h" 1 +N/**************************************************************************//** +N * @file system_ARMCM0.h +N * @brief CMSIS Device System Header File for +N * ARMCM0 Device +N * @version V5.3.1 +N * @date 09. July 2018 +N ******************************************************************************/ +N/* +N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +N * +N * SPDX-License-Identifier: Apache-2.0 +N * +N * Licensed under the Apache License, Version 2.0 (the License); you may +N * not use this file except in compliance with the License. +N * You may obtain a copy of the License at +N * +N * www.apache.org/licenses/LICENSE-2.0 +N * +N * Unless required by applicable law or agreed to in writing, software +N * distributed under the License is distributed on an AS IS BASIS, WITHOUT +N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +N * See the License for the specific language governing permissions and +N * limitations under the License. +N */ +N +N#ifndef SYSTEM_ARMCM0_H +N#define SYSTEM_ARMCM0_H +N +N#ifdef __cplusplus +Sextern "C" { +N#endif +N +Nextern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +N +N +N/** +N \brief Setup the microcontroller system. +N +N Initialize the System and update the SystemCoreClock variable. +N */ +Nextern void SystemInit (void); +N +N +N/** +N \brief Update SystemCoreClock variable. +N +N Updates the SystemCoreClock with current core Clock retrieved from cpu registers. +N */ +Nextern void SystemCoreClockUpdate (void); +N +N#ifdef __cplusplus +S} +N#endif +N +N#endif /* SYSTEM_ARMCM0_H */ +L 123 "..\..\src\sdk\include\M0\ArmCM0.h" 2 +N +N/* -------- End of section using anonymous unions and disabling warnings -------- */ +N#if defined (__CC_ARM) +X#if 1L +N#pragma pop +N#elif defined (__ICCARM__) +X#elif 0L +S/* leave anonymous unions enabled */ +S#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +S#pragma clang diagnostic pop +S#elif defined (__GNUC__) +S/* anonymous unions are enabled by default */ +S#elif defined (__TMS470__) +S/* anonymous unions are enabled by default */ +S#elif defined (__TASKING__) +S#pragma warning restore +S#elif defined (__CSMC__) +S/* anonymous unions are enabled by default */ +S#else +S#warning Not supported compiler type +N#endif +N +N/* In HS mode and when the DMA is used, all variables and data structures dealing +N with the DMA during the transaction process should be 4-bytes aligned */ +N#define DMA_WORD_ALIGN_EN +N#ifdef DMA_WORD_ALIGN_EN +N#if defined (__GNUC__) /* GNU Compiler */ +X#if 1L +N#define __ALIGN_END __attribute__ ((aligned (4))) +N#define __ALIGN_BEGIN +N#else +S#define __ALIGN_END +S#if defined (__CC_ARM) /* ARM Compiler */ +S#define __ALIGN_BEGIN __align(4) +S#elif defined (__ICCARM__) /* IAR Compiler */ +S#define __ALIGN_BEGIN +S#elif defined (__TASKING__) /* TASKING Compiler */ +S#define __ALIGN_BEGIN __align(4) +S#endif /* __CC_ARM */ +N#endif /* __GNUC__ */ +N#else +S +S#define __ALIGN_BEGIN +S#define __ALIGN_END +S +S#define __ALIGN_END_1 __attribute__ ((aligned (1))) +N#endif /* DMA_WORD_ALIGN_EN */ +N +N/* __packed keyword used to decrease the data type alignment to 1-byte */ +N#if defined (__CC_ARM) /* ARM Compiler */ +X#if 1L +N#define __packed __packed +N#elif defined (__ICCARM__) /* IAR Compiler */ +X#elif 0L +S#define __packed __packed +S#elif defined ( __GNUC__ ) /* GNU Compiler */ +S#define __packed __attribute__ ((__packed__)) +S#define __weak __attribute__((weak)) +S#elif defined (__TASKING__) /* TASKING Compiler */ +S#define __packed __unaligned +N#endif /* __CC_ARM */ +N +N#ifdef __cplusplus +S} +N#endif +N +N#endif /* ARMCM0_H */ +L 11 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "tau_device_datatype.h" +L 1 "..\..\src\common\tau_device_datatype.h" 1 +N/******************************************************************************* +N * +N * +N * File: tau_device_datatype.h +N * Description device datatype +N * Version V0.1 +N * Date 2020-12-04 +N * Author kevin +N *******************************************************************************/ +N +N#ifndef _TAU_DEVICE_DATATYPE_H_ +N#define _TAU_DEVICE_DATATYPE_H_ +N +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N +N#include "stdint.h" +N#include "tau_common.h" +L 1 "..\..\src\common\tau_common.h" 1 +N/******************************************************************************* +N* +N* +N* File: tau_common.h +N* Description 通用数据类型相关定义头文件 +N* Version V0.1 +N* Date 2020-09-07 +N* Author lzy +N *******************************************************************************/ +N +N#ifndef __TAU_COMMON_H +N#define __TAU_COMMON_H +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "stdint.h" +N#include "math.h" +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h" 1 +N/* +N * math.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.5 +N * Copyright (C) Codemist Ltd., 1988 +N * Copyright 1991-1998,2004-2006,2014 ARM Limited. All rights reserved +N */ +N +N/* +N * RCS $Revision$ Codemist 0.03 +N * Checkin $Date$ +N * Revising $Author: statham $ +N */ +N +N/* +N * Parts of this file are based upon fdlibm: +N * +N * ==================================================== +N * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. +N * +N * Developed at SunSoft, a Sun Microsystems, Inc. business. +N * Permission to use, copy, modify, and distribute this +N * software is freely granted, provided that this notice +N * is preserved. +N * ==================================================== +N */ +N +N#ifndef __math_h +N#define __math_h +N#define __ARMCLIB_VERSION 5060037 +N +N#if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__)) +X#if 0L || (1L && !0L) +N /* armclang and non-strict armcc allow 'long long' in system headers */ +N #define __LONGLONG long long +N#else +S /* strict armcc has '__int64' */ +S #define __LONGLONG __int64 +N#endif +N +N/* +N * Some of these declarations are new in C99. To access them in C++ +N * you can use -D__USE_C99_MATH (or -D__USE_C99_ALL). +N */ +N#ifndef __USE_C99_MATH +N #if defined(__USE_C99_ALL) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) +X #if 0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus) +N #define __USE_C99_MATH 1 +N #endif +N#endif +N +N#define _ARMABI __declspec(__nothrow) +N#ifdef __TARGET_ARCH_AARCH64 +S# define _ARMABI_SOFTFP __declspec(__nothrow) +N#else +N# define _ARMABI_SOFTFP __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) +N# define __HAVE_LONGDOUBLE 1 +N#endif +N#define _ARMABI_PURE __declspec(__nothrow) __attribute__((const)) +N#ifdef __FP_FENV_EXCEPTIONS +S# define _ARMABI_FPEXCEPT _ARMABI +N#else +N# define _ARMABI_FPEXCEPT _ARMABI __attribute__((const)) +N#endif +N +N#ifdef __cplusplus +S#define _ARMABI_INLINE inline +S#define _ARMABI_INLINE_DEF inline +N#elif defined __GNUC__ || defined _USE_STATIC_INLINE +X#elif 1L || 0L +N#define _ARMABI_INLINE static __inline +N#define _ARMABI_INLINE_DEF static __inline +N#elif (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) +X#elif (1L && 199901L <= 199901L) +S#define _ARMABI_INLINE inline +S#define _ARMABI_INLINE_DEF static inline +S#else +S#define _ARMABI_INLINE __inline +S#define _ARMABI_INLINE_DEF __inline +N#endif +N +N#ifdef __TARGET_ARCH_AARCH64 +S# define _SOFTFP +N#else +N# define _SOFTFP __attribute__((__pcs__("aapcs"))) +N#endif +N +N /* +N * If the compiler supports signalling nans as per N965 then it +N * will define __SUPPORT_SNAN__, in which case a user may define +N * _WANT_SNAN in order to obtain the nans function, as well as the +N * FP_NANS and FP_NANQ classification macros. +N */ +N#if defined(__SUPPORT_SNAN__) && defined(_WANT_SNAN) +X#if 0L && 0L +S#pragma import(__use_snan) +N#endif +N +N/* +N * Macros for our inline functions down below. +N * unsigned& __FLT(float x) - returns the bit pattern of x +N * unsigned& __HI(double x) - returns the bit pattern of the high part of x +N * (high part has exponent & sign bit in it) +N * unsigned& __LO(double x) - returns the bit pattern of the low part of x +N * +N * We can assign to __FLT, __HI, and __LO and the appropriate bits get set in +N * the floating point variable used. +N * +N * __HI & __LO are affected by the endianness and the target FPU. +N */ +N#define __FLT(x) (*(unsigned *)&(x)) +N#if defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN) +X#if 0L || 0L +S# define __LO(x) (*(1 + (unsigned *)&(x))) +S# define __HI(x) (*(unsigned *)&(x)) +N#else /* !defined(__ARM_BIG_ENDIAN) && !defined(__BIG_ENDIAN) */ +N# define __HI(x) (*(1 + (unsigned *)&(x))) +N# define __LO(x) (*(unsigned *)&(x)) +N#endif /* !defined(__ARM_BIG_ENDIAN) && !defined(__BIG_ENDIAN) */ +N +N# ifndef __MATH_DECLS +N# define __MATH_DECLS +N +N +N/* +N * A set of functions that we don't actually want to put in the standard +N * namespace ever. These are all called by the C99 macros. As they're +N * not specified by any standard they can't belong in ::std::. The +N * macro #defines are below amongst the standard function declarations. +N * We only include these if we actually need them later on +N */ +N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +X#if !0L || 1L +N# ifdef __cplusplus +S extern "C" { +N# endif /* __cplusplus */ +N +Nextern _SOFTFP unsigned __ARM_dcmp4(double /*x*/, double /*y*/); +Xextern __attribute__((__pcs__("aapcs"))) unsigned __ARM_dcmp4(double , double ); +Nextern _SOFTFP unsigned __ARM_fcmp4(float /*x*/, float /*y*/); +Xextern __attribute__((__pcs__("aapcs"))) unsigned __ARM_fcmp4(float , float ); +N /* +N * Compare x and y and return the CPSR in r0. These means we can test for +N * result types with bit pattern matching. +N * +N * These are a copy of the declarations in rt_fp.h keep in sync. +N */ +N +Nextern _ARMABI_SOFTFP int __ARM_fpclassifyf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassifyf(float ); +Nextern _ARMABI_SOFTFP int __ARM_fpclassify(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassify(double ); +N /* Classify x into NaN, infinite, normal, subnormal, zero */ +N /* Used by fpclassify macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isfinitef(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinitef(float __x) +N{ +N return ((__FLT(__x) >> 23) & 0xff) != 0xff; +X return (((*(unsigned *)&(__x)) >> 23) & 0xff) != 0xff; +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isfinite(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinite(double __x) +N{ +N return ((__HI(__x) >> 20) & 0x7ff) != 0x7ff; +X return (((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff) != 0x7ff; +N} +N /* Return 1 if __x is finite, 0 otherwise */ +N /* Used by isfinite macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isinff(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinff(float __x) +N{ +N return (__FLT(__x) << 1) == 0xff000000; +X return ((*(unsigned *)&(__x)) << 1) == 0xff000000; +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isinf(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinf(double __x) +N{ +N return ((__HI(__x) << 1) == 0xffe00000) && (__LO(__x) == 0); +X return (((*(1 + (unsigned *)&(__x))) << 1) == 0xffe00000) && ((*(unsigned *)&(__x)) == 0); +N} +N /* Return 1 if __x is infinite, 0 otherwise */ +N /* Used by isinf macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_islessgreaterf(float __x, float __y) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreaterf(float __x, float __y) +N{ +N unsigned __f = __ARM_fcmp4(__x, __y) >> 28; +N return (__f == 8) || (__f == 2); /* Just N set or Just Z set */ +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_islessgreater(double __x, double __y) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreater(double __x, double __y) +N{ +N unsigned __f = __ARM_dcmp4(__x, __y) >> 28; +N return (__f == 8) || (__f == 2); /* Just N set or Just Z set */ +N} +N /* +N * Compare __x and __y and return 1 if __x < __y or __x > __y, 0 otherwise +N * Used by islessgreater macro +N */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnanf(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnanf(float __x) +N{ +N return (0x7f800000 - (__FLT(__x) & 0x7fffffff)) >> 31; +X return (0x7f800000 - ((*(unsigned *)&(__x)) & 0x7fffffff)) >> 31; +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnan(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnan(double __x) +N{ +N unsigned __xf = __HI(__x) | ((__LO(__x) == 0) ? 0 : 1); +X unsigned __xf = (*(1 + (unsigned *)&(__x))) | (((*(unsigned *)&(__x)) == 0) ? 0 : 1); +N return (0x7ff00000 - (__xf & 0x7fffffff)) >> 31; +N} +N /* Return 1 if __x is a NaN, 0 otherwise */ +N /* Used by isnan macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnormalf(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormalf(float __x) +N{ +N unsigned __xe = (__FLT(__x) >> 23) & 0xff; +X unsigned __xe = ((*(unsigned *)&(__x)) >> 23) & 0xff; +N return (__xe != 0xff) && (__xe != 0); +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnormal(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormal(double __x) +N{ +N unsigned __xe = (__HI(__x) >> 20) & 0x7ff; +X unsigned __xe = ((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff; +N return (__xe != 0x7ff) && (__xe != 0); +N} +N /* Return 1 if __x is a normalised number, 0 otherwise */ +N /* used by isnormal macro */ +N +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_signbitf(float __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbitf(float __x) +N{ +N return __FLT(__x) >> 31; +X return (*(unsigned *)&(__x)) >> 31; +N} +N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_signbit(double __x) +Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbit(double __x) +N{ +N return __HI(__x) >> 31; +X return (*(1 + (unsigned *)&(__x))) >> 31; +N} +N /* Return signbit of __x */ +N /* Used by signbit macro */ +N +N# ifdef __cplusplus +S } /* extern "C" */ +N# endif /* __cplusplus */ +N#endif /* Strict ANSI */ +N +N# undef __CLIBNS +N +N# ifdef __cplusplus +S namespace std { +S# define __CLIBNS ::std:: +S extern "C" { +N# else +N# define __CLIBNS +N# endif /* __cplusplus */ +N +N +N#ifndef __has_builtin +N #define __has_builtin(x) 0 +N#endif +N +N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +X#if !0L || 1L +N /* C99 additions */ +N typedef float float_t; +N typedef double double_t; +N#if __has_builtin(__builtin_inf) +X#if 0 +S# define HUGE_VALF __builtin_inff() +S# define HUGE_VALL __builtin_infl() +S# define INFINITY __builtin_inff() +S# define NAN __builtin_nanf("") +N# else +N# define HUGE_VALF ((float)__INFINITY__) +N# define HUGE_VALL ((long double)__INFINITY__) +N# define INFINITY ((float)__INFINITY__) +N# define NAN (__ESCAPE__(0f_7FC00000)) +N#endif +N +N# define MATH_ERRNO 1 +N# define MATH_ERREXCEPT 2 +Nextern const int math_errhandling; +N#endif +N#if __has_builtin(__builtin_inf) +X#if 0 +S# define HUGE_VAL __builtin_inf() +N#else +N# define HUGE_VAL ((double)__INFINITY__) +N#endif +N +Nextern _ARMABI double acos(double /*x*/); +Xextern __declspec(__nothrow) double acos(double ); +N /* computes the principal value of the arc cosine of x */ +N /* a domain error occurs for arguments not in the range -1 to 1 */ +N /* Returns: the arc cosine in the range 0 to Pi. */ +Nextern _ARMABI double asin(double /*x*/); +Xextern __declspec(__nothrow) double asin(double ); +N /* computes the principal value of the arc sine of x */ +N /* a domain error occurs for arguments not in the range -1 to 1 */ +N /* and -HUGE_VAL is returned. */ +N /* Returns: the arc sine in the range -Pi/2 to Pi/2. */ +N +Nextern _ARMABI_PURE double atan(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double atan(double ); +N /* computes the principal value of the arc tangent of x */ +N /* Returns: the arc tangent in the range -Pi/2 to Pi/2. */ +N +Nextern _ARMABI double atan2(double /*y*/, double /*x*/); +Xextern __declspec(__nothrow) double atan2(double , double ); +N /* computes the principal value of the arc tangent of y/x, using the */ +N /* signs of both arguments to determine the quadrant of the return value */ +N /* a domain error occurs if both args are zero, and -HUGE_VAL returned. */ +N /* Returns: the arc tangent of y/x, in the range -Pi to Pi. */ +N +Nextern _ARMABI double cos(double /*x*/); +Xextern __declspec(__nothrow) double cos(double ); +N /* computes the cosine of x (measured in radians). A large magnitude */ +N /* argument may yield a result with little or no significance. */ +N /* a domain error occurs for infinite input (C 7.12.1 footnote 196). */ +N /* Returns: the cosine value. */ +Nextern _ARMABI double sin(double /*x*/); +Xextern __declspec(__nothrow) double sin(double ); +N /* computes the sine of x (measured in radians). A large magnitude */ +N /* argument may yield a result with little or no significance. */ +N /* a domain error occurs for infinite input (C 7.12.1 footnote 196). */ +N /* Returns: the sine value. */ +N +Nextern void __use_accurate_range_reduction(void); +N /* reference this to select the larger, slower, but more accurate */ +N /* range reduction in sin, cos and tan */ +N +Nextern _ARMABI double tan(double /*x*/); +Xextern __declspec(__nothrow) double tan(double ); +N /* computes the tangent of x (measured in radians). A large magnitude */ +N /* argument may yield a result with little or no significance */ +N /* Returns: the tangent value. */ +N /* if range error; returns HUGE_VAL. */ +N +Nextern _ARMABI double cosh(double /*x*/); +Xextern __declspec(__nothrow) double cosh(double ); +N /* computes the hyperbolic cosine of x. A range error occurs if the */ +N /* magnitude of x is too large. */ +N /* Returns: the hyperbolic cosine value. */ +N /* if range error; returns HUGE_VAL. */ +Nextern _ARMABI double sinh(double /*x*/); +Xextern __declspec(__nothrow) double sinh(double ); +N /* computes the hyperbolic sine of x. A range error occurs if the */ +N /* magnitude of x is too large. */ +N /* Returns: the hyperbolic sine value. */ +N /* if range error; returns -HUGE_VAL or HUGE_VAL depending */ +N /* on the sign of the argument */ +N +Nextern _ARMABI_PURE double tanh(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double tanh(double ); +N /* computes the hyperbolic tangent of x. */ +N /* Returns: the hyperbolic tangent value. */ +N +Nextern _ARMABI double exp(double /*x*/); +Xextern __declspec(__nothrow) double exp(double ); +N /* computes the exponential function of x. A range error occurs if the */ +N /* magnitude of x is too large. */ +N /* Returns: the exponential value. */ +N /* if underflow range error; 0 is returned. */ +N /* if overflow range error; HUGE_VAL is returned. */ +N +Nextern _ARMABI double frexp(double /*value*/, int * /*exp*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) double frexp(double , int * ) __attribute__((__nonnull__(2))); +N /* breaks a floating-point number into a normalised fraction and an */ +N /* integral power of 2. It stores the integer in the int object pointed */ +N /* to by exp. */ +N /* Returns: the value x, such that x is a double with magnitude in the */ +N /* interval 0.5 to 1.0 or zero, and value equals x times 2 raised to the */ +N /* power *exp. If value is zero, both parts of the result are zero. */ +N +Nextern _ARMABI double ldexp(double /*x*/, int /*exp*/); +Xextern __declspec(__nothrow) double ldexp(double , int ); +N /* multiplies a floating-point number by an integral power of 2. */ +N /* A range error may occur. */ +N /* Returns: the value of x times 2 raised to the power of exp. */ +N /* if range error; HUGE_VAL is returned. */ +Nextern _ARMABI double log(double /*x*/); +Xextern __declspec(__nothrow) double log(double ); +N /* computes the natural logarithm of x. A domain error occurs if the */ +N /* argument is negative, and -HUGE_VAL is returned. A range error occurs */ +N /* if the argument is zero. */ +N /* Returns: the natural logarithm. */ +N /* if range error; -HUGE_VAL is returned. */ +Nextern _ARMABI double log10(double /*x*/); +Xextern __declspec(__nothrow) double log10(double ); +N /* computes the base-ten logarithm of x. A domain error occurs if the */ +N /* argument is negative. A range error occurs if the argument is zero. */ +N /* Returns: the base-ten logarithm. */ +Nextern _ARMABI double modf(double /*value*/, double * /*iptr*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) double modf(double , double * ) __attribute__((__nonnull__(2))); +N /* breaks the argument value into integral and fraction parts, each of */ +N /* which has the same sign as the argument. It stores the integral part */ +N /* as a double in the object pointed to by iptr. */ +N /* Returns: the signed fractional part of value. */ +N +Nextern _ARMABI double pow(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double pow(double , double ); +N /* computes x raised to the power of y. A domain error occurs if x is */ +N /* zero and y is less than or equal to zero, or if x is negative and y */ +N /* is not an integer, and -HUGE_VAL returned. A range error may occur. */ +N /* Returns: the value of x raised to the power of y. */ +N /* if underflow range error; 0 is returned. */ +N /* if overflow range error; HUGE_VAL is returned. */ +Nextern _ARMABI double sqrt(double /*x*/); +Xextern __declspec(__nothrow) double sqrt(double ); +N /* computes the non-negative square root of x. A domain error occurs */ +N /* if the argument is negative, and -HUGE_VAL returned. */ +N /* Returns: the value of the square root. */ +N +N#if defined(__TARGET_FPU_VFP_DOUBLE) && !defined(__TARGET_FPU_SOFTVFP) +X#if 0L && !1L +S _ARMABI_INLINE double _sqrt(double __x) { return __sqrt(__x); } +N#else +N _ARMABI_INLINE double _sqrt(double __x) { return sqrt(__x); } +X static __inline double _sqrt(double __x) { return sqrt(__x); } +N#endif +N#if defined(__TARGET_FPU_VFP_SINGLE) && !defined(__TARGET_FPU_SOFTVFP) +X#if 0L && !1L +S _ARMABI_INLINE float _sqrtf(float __x) { return __sqrtf(__x); } +N#else +N _ARMABI_INLINE float _sqrtf(float __x) { return (float)sqrt(__x); } +X static __inline float _sqrtf(float __x) { return (float)sqrt(__x); } +N#endif +N /* With VFP, _sqrt and _sqrtf should expand inline as the native VFP square root +N * instructions. They will not behave like the C sqrt() function, because +N * they will report unusual values as IEEE exceptions (in fpmodes which +N * support IEEE exceptions) rather than in errno. These function names +N * are not specified in any standard. */ +N +Nextern _ARMABI_PURE double ceil(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double ceil(double ); +N /* computes the smallest integer not less than x. */ +N /* Returns: the smallest integer not less than x, expressed as a double. */ +Nextern _ARMABI_PURE double fabs(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double fabs(double ); +N /* computes the absolute value of the floating-point number x. */ +N /* Returns: the absolute value of x. */ +N +Nextern _ARMABI_PURE double floor(double /*d*/); +Xextern __declspec(__nothrow) __attribute__((const)) double floor(double ); +N /* computes the largest integer not greater than x. */ +N /* Returns: the largest integer not greater than x, expressed as a double */ +N +Nextern _ARMABI double fmod(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double fmod(double , double ); +N /* computes the floating-point remainder of x/y. */ +N /* Returns: the value x - i * y, for some integer i such that, if y is */ +N /* nonzero, the result has the same sign as x and magnitude */ +N /* less than the magnitude of y. If y is zero, a domain error */ +N /* occurs and -HUGE_VAL is returned. */ +N +N /* Additional Mathlib functions not defined by the ANSI standard. +N * Not guaranteed, and not necessarily very well tested. +N * C99 requires the user to include to use these functions +N * declaring them "by hand" is not sufficient +N * +N * The above statement is not completely true now. Some of the above +N * C99 functionality has been added as per the Standard, and (where +N * necessary) old Mathlib functionality withdrawn/changed. Before +N * including this header #define __ENABLE_MATHLIB_LEGACY if you want to +N * re-enable the legacy functionality. +N */ +N +N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +X#if !0L || 1L +N +Nextern _ARMABI double acosh(double /*x*/); +Xextern __declspec(__nothrow) double acosh(double ); +N /* +N * Inverse cosh. EDOM if argument < 1.0 +N */ +Nextern _ARMABI double asinh(double /*x*/); +Xextern __declspec(__nothrow) double asinh(double ); +N /* +N * Inverse sinh. +N */ +Nextern _ARMABI double atanh(double /*x*/); +Xextern __declspec(__nothrow) double atanh(double ); +N /* +N * Inverse tanh. EDOM if |argument| > 1.0 +N */ +Nextern _ARMABI double cbrt(double /*x*/); +Xextern __declspec(__nothrow) double cbrt(double ); +N /* +N * Cube root. +N */ +N_ARMABI_INLINE _ARMABI_PURE double copysign(double __x, double __y) +Xstatic __inline __declspec(__nothrow) __attribute__((const)) double copysign(double __x, double __y) +N /* +N * Returns x with sign bit replaced by sign of y. +N */ +N{ +N __HI(__x) = (__HI(__x) & 0x7fffffff) | (__HI(__y) & 0x80000000); +X (*(1 + (unsigned *)&(__x))) = ((*(1 + (unsigned *)&(__x))) & 0x7fffffff) | ((*(1 + (unsigned *)&(__y))) & 0x80000000); +N return __x; +N} +N_ARMABI_INLINE _ARMABI_PURE float copysignf(float __x, float __y) +Xstatic __inline __declspec(__nothrow) __attribute__((const)) float copysignf(float __x, float __y) +N /* +N * Returns x with sign bit replaced by sign of y. +N */ +N{ +N __FLT(__x) = (__FLT(__x) & 0x7fffffff) | (__FLT(__y) & 0x80000000); +X (*(unsigned *)&(__x)) = ((*(unsigned *)&(__x)) & 0x7fffffff) | ((*(unsigned *)&(__y)) & 0x80000000); +N return __x; +N} +Nextern _ARMABI double erf(double /*x*/); +Xextern __declspec(__nothrow) double erf(double ); +N /* +N * Error function. (2/sqrt(pi)) * integral from 0 to x of exp(-t*t) dt. +N */ +Nextern _ARMABI double erfc(double /*x*/); +Xextern __declspec(__nothrow) double erfc(double ); +N /* +N * 1-erf(x). (More accurate than just coding 1-erf(x), for large x.) +N */ +Nextern _ARMABI double expm1(double /*x*/); +Xextern __declspec(__nothrow) double expm1(double ); +N /* +N * exp(x)-1. (More accurate than just coding exp(x)-1, for small x.) +N */ +N#define fpclassify(x) \ +N ((sizeof(x) == sizeof(float)) ? \ +N __ARM_fpclassifyf(x) : __ARM_fpclassify(x)) +X#define fpclassify(x) ((sizeof(x) == sizeof(float)) ? __ARM_fpclassifyf(x) : __ARM_fpclassify(x)) +N /* +N * Classify a floating point number into one of the following values: +N */ +N#define FP_ZERO (0) +N#define FP_SUBNORMAL (4) +N#define FP_NORMAL (5) +N#define FP_INFINITE (3) +N#define FP_NAN (7) +N +N#if defined(_WANT_SNAN) && defined(__SUPPORT_SNAN__) +X#if 0L && 0L +S/* +S * Note that we'll never classify a number as FP_NAN, as all NaNs will +S * be either FP_NANQ or FP_NANS +S */ +S# define FP_NANQ (8) +S# define FP_NANS (9) +N#endif +N +N +Nextern _ARMABI double hypot(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double hypot(double , double ); +N /* +N * sqrt(x*x+y*y), ie the length of the vector (x,y) or the +N * hypotenuse of a right triangle whose other two sides are x +N * and y. Won't overflow unless the _answer_ is too big, even +N * if the intermediate x*x+y*y is too big. +N */ +Nextern _ARMABI int ilogb(double /*x*/); +Xextern __declspec(__nothrow) int ilogb(double ); +N /* +N * Exponent of x (returns 0 for 1.0, 1 for 2.0, -1 for 0.5, etc.) +N */ +Nextern _ARMABI int ilogbf(float /*x*/); +Xextern __declspec(__nothrow) int ilogbf(float ); +N /* +N * Like ilogb but takes a float +N */ +Nextern _ARMABI int ilogbl(long double /*x*/); +Xextern __declspec(__nothrow) int ilogbl(long double ); +N /* +N * Exponent of x (returns 0 for 1.0, 1 for 2.0, -1 for 0.5, etc.) +N */ +N#define FP_ILOGB0 (-0x7fffffff) /* ilogb(0) == -INT_MAX */ +N#define FP_ILOGBNAN ( 0x80000000) /* ilogb(NAN) == INT_MIN */ +N +N#define isfinite(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_isfinitef(x) \ +N : __ARM_isfinite(x)) +X#define isfinite(x) ((sizeof(x) == sizeof(float)) ? __ARM_isfinitef(x) : __ARM_isfinite(x)) +N /* +N * Returns true if x is a finite number, size independent. +N */ +N +N#define isgreater(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000) \ +N : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000)) +X#define isgreater(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000)) +N /* +N * Returns true if x > y, throws no exceptions except on Signaling NaNs +N * +N * We want the C not set but the Z bit clear, V must be clear +N */ +N +N#define isgreaterequal(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000) \ +N : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000)) +X#define isgreaterequal(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000)) +N /* +N * Returns true if x >= y, throws no exceptions except on Signaling NaNs +N * +N * We just need to see if the C bit is set or not and ensure V clear +N */ +N +N#define isinf(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_isinff(x) \ +N : __ARM_isinf(x)) +X#define isinf(x) ((sizeof(x) == sizeof(float)) ? __ARM_isinff(x) : __ARM_isinf(x)) +N /* +N * Returns true if x is an infinity, size independent. +N */ +N +N#define isless(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000) \ +N : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000)) +X#define isless(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000)) +N /* +N * Returns true if x < y, throws no exceptions except on Signaling NaNs +N * +N * We're less than if N is set, V clear +N */ +N +N#define islessequal(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0) \ +N : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0)) +X#define islessequal(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0) : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0)) +N /* +N * Returns true if x <= y, throws no exceptions except on Signaling NaNs +N * +N * We're less than or equal if one of N or Z is set, V clear +N */ +N +N#define islessgreater(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? __ARM_islessgreaterf((x), (y)) \ +N : __ARM_islessgreater((x), (y))) +X#define islessgreater(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? __ARM_islessgreaterf((x), (y)) : __ARM_islessgreater((x), (y))) +N /* +N * Returns true if x <> y, throws no exceptions except on Signaling NaNs +N * Unfortunately this test is too complicated to do in a macro without +N * evaluating x & y twice. Shame really... +N */ +N +N#define isnan(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_isnanf(x) \ +N : __ARM_isnan(x)) +X#define isnan(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnanf(x) : __ARM_isnan(x)) +N /* +N * Returns TRUE if x is a NaN. +N */ +N +N#define isnormal(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_isnormalf(x) \ +N : __ARM_isnormal(x)) +X#define isnormal(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnormalf(x) : __ARM_isnormal(x)) +N /* +N * Returns TRUE if x is a NaN. +N */ +N +N#define isunordered(x, y) \ +N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ +N ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000) \ +N : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000)) +X#define isunordered(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000) : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000)) +N /* +N * Returns true if x ? y, throws no exceptions except on Signaling NaNs +N * Unordered occurs if and only if the V bit is set +N */ +N +Nextern _ARMABI double lgamma (double /*x*/); +Xextern __declspec(__nothrow) double lgamma (double ); +N /* +N * The log of the absolute value of the gamma function of x. The sign +N * of the gamma function of x is returned in the global `signgam'. +N */ +Nextern _ARMABI double log1p(double /*x*/); +Xextern __declspec(__nothrow) double log1p(double ); +N /* +N * log(1+x). (More accurate than just coding log(1+x), for small x.) +N */ +Nextern _ARMABI double logb(double /*x*/); +Xextern __declspec(__nothrow) double logb(double ); +N /* +N * Like ilogb but returns a double. +N */ +Nextern _ARMABI float logbf(float /*x*/); +Xextern __declspec(__nothrow) float logbf(float ); +N /* +N * Like logb but takes and returns float +N */ +Nextern _ARMABI long double logbl(long double /*x*/); +Xextern __declspec(__nothrow) long double logbl(long double ); +N /* +N * Like logb but takes and returns long double +N */ +Nextern _ARMABI double nextafter(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double nextafter(double , double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI float nextafterf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float nextafterf(float , float ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI long double nextafterl(long double /*x*/, long double /*y*/); +Xextern __declspec(__nothrow) long double nextafterl(long double , long double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI double nexttoward(double /*x*/, long double /*y*/); +Xextern __declspec(__nothrow) double nexttoward(double , long double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI float nexttowardf(float /*x*/, long double /*y*/); +Xextern __declspec(__nothrow) float nexttowardf(float , long double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI long double nexttowardl(long double /*x*/, long double /*y*/); +Xextern __declspec(__nothrow) long double nexttowardl(long double , long double ); +N /* +N * Returns the next representable number after x, in the +N * direction toward y. +N */ +Nextern _ARMABI double remainder(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double remainder(double , double ); +N /* +N * Returns the remainder of x by y, in the IEEE 754 sense. +N */ +Nextern _ARMABI_FPEXCEPT double rint(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double rint(double ); +N /* +N * Rounds x to an integer, in the IEEE 754 sense. +N */ +Nextern _ARMABI double scalbln(double /*x*/, long int /*n*/); +Xextern __declspec(__nothrow) double scalbln(double , long int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI float scalblnf(float /*x*/, long int /*n*/); +Xextern __declspec(__nothrow) float scalblnf(float , long int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI long double scalblnl(long double /*x*/, long int /*n*/); +Xextern __declspec(__nothrow) long double scalblnl(long double , long int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI double scalbn(double /*x*/, int /*n*/); +Xextern __declspec(__nothrow) double scalbn(double , int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI float scalbnf(float /*x*/, int /*n*/); +Xextern __declspec(__nothrow) float scalbnf(float , int ); +N /* +N * Compute x times 2^n quickly. +N */ +Nextern _ARMABI long double scalbnl(long double /*x*/, int /*n*/); +Xextern __declspec(__nothrow) long double scalbnl(long double , int ); +N /* +N * Compute x times 2^n quickly. +N */ +N#define signbit(x) \ +N ((sizeof(x) == sizeof(float)) \ +N ? __ARM_signbitf(x) \ +N : __ARM_signbit(x)) +X#define signbit(x) ((sizeof(x) == sizeof(float)) ? __ARM_signbitf(x) : __ARM_signbit(x)) +N /* +N * Returns the signbit of x, size independent macro +N */ +N#endif +N +N/* C99 float versions of functions. math.h has always reserved these +N identifiers for this purpose (7.13.4). */ +Nextern _ARMABI_PURE float _fabsf(float); /* old ARM name */ +Xextern __declspec(__nothrow) __attribute__((const)) float _fabsf(float); +N_ARMABI_INLINE _ARMABI_PURE float fabsf(float __f) { return _fabsf(__f); } +Xstatic __inline __declspec(__nothrow) __attribute__((const)) float fabsf(float __f) { return _fabsf(__f); } +Nextern _ARMABI float sinf(float /*x*/); +Xextern __declspec(__nothrow) float sinf(float ); +Nextern _ARMABI float cosf(float /*x*/); +Xextern __declspec(__nothrow) float cosf(float ); +Nextern _ARMABI float tanf(float /*x*/); +Xextern __declspec(__nothrow) float tanf(float ); +Nextern _ARMABI float acosf(float /*x*/); +Xextern __declspec(__nothrow) float acosf(float ); +Nextern _ARMABI float asinf(float /*x*/); +Xextern __declspec(__nothrow) float asinf(float ); +Nextern _ARMABI float atanf(float /*x*/); +Xextern __declspec(__nothrow) float atanf(float ); +Nextern _ARMABI float atan2f(float /*y*/, float /*x*/); +Xextern __declspec(__nothrow) float atan2f(float , float ); +Nextern _ARMABI float sinhf(float /*x*/); +Xextern __declspec(__nothrow) float sinhf(float ); +Nextern _ARMABI float coshf(float /*x*/); +Xextern __declspec(__nothrow) float coshf(float ); +Nextern _ARMABI float tanhf(float /*x*/); +Xextern __declspec(__nothrow) float tanhf(float ); +Nextern _ARMABI float expf(float /*x*/); +Xextern __declspec(__nothrow) float expf(float ); +Nextern _ARMABI float logf(float /*x*/); +Xextern __declspec(__nothrow) float logf(float ); +Nextern _ARMABI float log10f(float /*x*/); +Xextern __declspec(__nothrow) float log10f(float ); +Nextern _ARMABI float powf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float powf(float , float ); +Nextern _ARMABI float sqrtf(float /*x*/); +Xextern __declspec(__nothrow) float sqrtf(float ); +Nextern _ARMABI float ldexpf(float /*x*/, int /*exp*/); +Xextern __declspec(__nothrow) float ldexpf(float , int ); +Nextern _ARMABI float frexpf(float /*value*/, int * /*exp*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) float frexpf(float , int * ) __attribute__((__nonnull__(2))); +Nextern _ARMABI_PURE float ceilf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float ceilf(float ); +Nextern _ARMABI_PURE float floorf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float floorf(float ); +Nextern _ARMABI float fmodf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float fmodf(float , float ); +Nextern _ARMABI float modff(float /*value*/, float * /*iptr*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) float modff(float , float * ) __attribute__((__nonnull__(2))); +N +N/* C99 long double versions of functions. */ +N/* (also need to have 'using' declarations below) */ +N#define _ARMDEFLD1(f) \ +N _ARMABI long double f##l(long double /*x*/) +X#define _ARMDEFLD1(f) _ARMABI long double f##l(long double ) +N +N#define _ARMDEFLD1P(f, T) \ +N _ARMABI long double f##l(long double /*x*/, T /*p*/) +X#define _ARMDEFLD1P(f, T) _ARMABI long double f##l(long double , T ) +N +N#define _ARMDEFLD2(f) \ +N _ARMABI long double f##l(long double /*x*/, long double /*y*/) +X#define _ARMDEFLD2(f) _ARMABI long double f##l(long double , long double ) +N +N/* +N * Long double versions of C89 functions can be defined +N * unconditionally, because C89 reserved these names in "future +N * library directions". +N */ +N_ARMDEFLD1(acos); +X__declspec(__nothrow) long double acosl(long double ); +N_ARMDEFLD1(asin); +X__declspec(__nothrow) long double asinl(long double ); +N_ARMDEFLD1(atan); +X__declspec(__nothrow) long double atanl(long double ); +N_ARMDEFLD2(atan2); +X__declspec(__nothrow) long double atan2l(long double , long double ); +N_ARMDEFLD1(ceil); +X__declspec(__nothrow) long double ceill(long double ); +N_ARMDEFLD1(cos); +X__declspec(__nothrow) long double cosl(long double ); +N_ARMDEFLD1(cosh); +X__declspec(__nothrow) long double coshl(long double ); +N_ARMDEFLD1(exp); +X__declspec(__nothrow) long double expl(long double ); +N_ARMDEFLD1(fabs); +X__declspec(__nothrow) long double fabsl(long double ); +N_ARMDEFLD1(floor); +X__declspec(__nothrow) long double floorl(long double ); +N_ARMDEFLD2(fmod); +X__declspec(__nothrow) long double fmodl(long double , long double ); +N_ARMDEFLD1P(frexp, int*) __attribute__((__nonnull__(2))); +X__declspec(__nothrow) long double frexpl(long double , int* ) __attribute__((__nonnull__(2))); +N_ARMDEFLD1P(ldexp, int); +X__declspec(__nothrow) long double ldexpl(long double , int ); +N_ARMDEFLD1(log); +X__declspec(__nothrow) long double logl(long double ); +N_ARMDEFLD1(log10); +X__declspec(__nothrow) long double log10l(long double ); +N_ARMABI long double modfl(long double /*x*/, long double * /*p*/) __attribute__((__nonnull__(2))); +X__declspec(__nothrow) long double modfl(long double , long double * ) __attribute__((__nonnull__(2))); +N_ARMDEFLD2(pow); +X__declspec(__nothrow) long double powl(long double , long double ); +N_ARMDEFLD1(sin); +X__declspec(__nothrow) long double sinl(long double ); +N_ARMDEFLD1(sinh); +X__declspec(__nothrow) long double sinhl(long double ); +N_ARMDEFLD1(sqrt); +X__declspec(__nothrow) long double sqrtl(long double ); +N_ARMDEFLD1(tan); +X__declspec(__nothrow) long double tanl(long double ); +N_ARMDEFLD1(tanh); +X__declspec(__nothrow) long double tanhl(long double ); +N +N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +X#if !0L || 1L +N +N/* +N * C99 float and long double versions of extra-C89 functions. +N */ +Nextern _ARMABI float acoshf(float /*x*/); +Xextern __declspec(__nothrow) float acoshf(float ); +N_ARMDEFLD1(acosh); +X__declspec(__nothrow) long double acoshl(long double ); +Nextern _ARMABI float asinhf(float /*x*/); +Xextern __declspec(__nothrow) float asinhf(float ); +N_ARMDEFLD1(asinh); +X__declspec(__nothrow) long double asinhl(long double ); +Nextern _ARMABI float atanhf(float /*x*/); +Xextern __declspec(__nothrow) float atanhf(float ); +N_ARMDEFLD1(atanh); +X__declspec(__nothrow) long double atanhl(long double ); +N_ARMDEFLD2(copysign); +X__declspec(__nothrow) long double copysignl(long double , long double ); +Nextern _ARMABI float cbrtf(float /*x*/); +Xextern __declspec(__nothrow) float cbrtf(float ); +N_ARMDEFLD1(cbrt); +X__declspec(__nothrow) long double cbrtl(long double ); +Nextern _ARMABI float erff(float /*x*/); +Xextern __declspec(__nothrow) float erff(float ); +N_ARMDEFLD1(erf); +X__declspec(__nothrow) long double erfl(long double ); +Nextern _ARMABI float erfcf(float /*x*/); +Xextern __declspec(__nothrow) float erfcf(float ); +N_ARMDEFLD1(erfc); +X__declspec(__nothrow) long double erfcl(long double ); +Nextern _ARMABI float expm1f(float /*x*/); +Xextern __declspec(__nothrow) float expm1f(float ); +N_ARMDEFLD1(expm1); +X__declspec(__nothrow) long double expm1l(long double ); +Nextern _ARMABI float log1pf(float /*x*/); +Xextern __declspec(__nothrow) float log1pf(float ); +N_ARMDEFLD1(log1p); +X__declspec(__nothrow) long double log1pl(long double ); +Nextern _ARMABI float hypotf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float hypotf(float , float ); +N_ARMDEFLD2(hypot); +X__declspec(__nothrow) long double hypotl(long double , long double ); +Nextern _ARMABI float lgammaf(float /*x*/); +Xextern __declspec(__nothrow) float lgammaf(float ); +N_ARMDEFLD1(lgamma); +X__declspec(__nothrow) long double lgammal(long double ); +Nextern _ARMABI float remainderf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float remainderf(float , float ); +N_ARMDEFLD2(remainder); +X__declspec(__nothrow) long double remainderl(long double , long double ); +Nextern _ARMABI float rintf(float /*x*/); +Xextern __declspec(__nothrow) float rintf(float ); +N_ARMDEFLD1(rint); +X__declspec(__nothrow) long double rintl(long double ); +N +N#endif +N +N#if (defined(__clang__) && !defined(__STRICT_ANSI)) || defined(__USE_C99_MATH) +X#if (0L && !0L) || 1L +N/* +N * Functions new in C99. +N */ +Nextern _ARMABI double exp2(double /*x*/); /* * 2.^x. */ +Xextern __declspec(__nothrow) double exp2(double ); +Nextern _ARMABI float exp2f(float /*x*/); +Xextern __declspec(__nothrow) float exp2f(float ); +N_ARMDEFLD1(exp2); +X__declspec(__nothrow) long double exp2l(long double ); +Nextern _ARMABI double fdim(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) double fdim(double , double ); +Nextern _ARMABI float fdimf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) float fdimf(float , float ); +N_ARMDEFLD2(fdim); +X__declspec(__nothrow) long double fdiml(long double , long double ); +N#ifdef __FP_FAST_FMA +S#define FP_FAST_FMA +N#endif +N#ifdef __FP_FAST_FMAF +S#define FP_FAST_FMAF +N#endif +N#ifdef __FP_FAST_FMAL +S#define FP_FAST_FMAL +N#endif +Nextern _ARMABI double fma(double /*x*/, double /*y*/, double /*z*/); +Xextern __declspec(__nothrow) double fma(double , double , double ); +Nextern _ARMABI float fmaf(float /*x*/, float /*y*/, float /*z*/); +Xextern __declspec(__nothrow) float fmaf(float , float , float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI long double fmal(long double __x, long double __y, long double __z) \ +N { return (long double)fma((double)__x, (double)__y, (double)__z); } +Xstatic __inline __declspec(__nothrow) long double fmal(long double __x, long double __y, long double __z) { return (long double)fma((double)__x, (double)__y, (double)__z); } +N#endif +Nextern _ARMABI_FPEXCEPT double fmax(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) __attribute__((const)) double fmax(double , double ); +Nextern _ARMABI_FPEXCEPT float fmaxf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) __attribute__((const)) float fmaxf(float , float ); +N_ARMDEFLD2(fmax); +X__declspec(__nothrow) long double fmaxl(long double , long double ); +Nextern _ARMABI_FPEXCEPT double fmin(double /*x*/, double /*y*/); +Xextern __declspec(__nothrow) __attribute__((const)) double fmin(double , double ); +Nextern _ARMABI_FPEXCEPT float fminf(float /*x*/, float /*y*/); +Xextern __declspec(__nothrow) __attribute__((const)) float fminf(float , float ); +N_ARMDEFLD2(fmin); +X__declspec(__nothrow) long double fminl(long double , long double ); +Nextern _ARMABI double log2(double /*x*/); /* * log base 2 of x. */ +Xextern __declspec(__nothrow) double log2(double ); +Nextern _ARMABI float log2f(float /*x*/); +Xextern __declspec(__nothrow) float log2f(float ); +N_ARMDEFLD1(log2); +X__declspec(__nothrow) long double log2l(long double ); +Nextern _ARMABI long lrint(double /*x*/); +Xextern __declspec(__nothrow) long lrint(double ); +Nextern _ARMABI long lrintf(float /*x*/); +Xextern __declspec(__nothrow) long lrintf(float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI long lrintl(long double __x) \ +N { return lrint((double)__x); } +Xstatic __inline __declspec(__nothrow) long lrintl(long double __x) { return lrint((double)__x); } +N#endif +Nextern _ARMABI __LONGLONG llrint(double /*x*/); +Xextern __declspec(__nothrow) long long llrint(double ); +Nextern _ARMABI __LONGLONG llrintf(float /*x*/); +Xextern __declspec(__nothrow) long long llrintf(float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI __LONGLONG llrintl(long double __x) \ +N { return llrint((double)__x); } +Xstatic __inline __declspec(__nothrow) long long llrintl(long double __x) { return llrint((double)__x); } +N#endif +Nextern _ARMABI long lround(double /*x*/); +Xextern __declspec(__nothrow) long lround(double ); +Nextern _ARMABI long lroundf(float /*x*/); +Xextern __declspec(__nothrow) long lroundf(float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI long lroundl(long double __x) \ +N { return lround((double)__x); } +Xstatic __inline __declspec(__nothrow) long lroundl(long double __x) { return lround((double)__x); } +N#endif +Nextern _ARMABI __LONGLONG llround(double /*x*/); +Xextern __declspec(__nothrow) long long llround(double ); +Nextern _ARMABI __LONGLONG llroundf(float /*x*/); +Xextern __declspec(__nothrow) long long llroundf(float ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI __LONGLONG llroundl(long double __x) \ +N { return llround((double)__x); } +Xstatic __inline __declspec(__nothrow) long long llroundl(long double __x) { return llround((double)__x); } +N#endif +Nextern _ARMABI_PURE double nan(const char */*tagp*/); +Xextern __declspec(__nothrow) __attribute__((const)) double nan(const char * ); +Nextern _ARMABI_PURE float nanf(const char */*tagp*/); +Xextern __declspec(__nothrow) __attribute__((const)) float nanf(const char * ); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE _ARMABI_PURE long double nanl(const char *__t) \ +N { return (long double)nan(__t); } +Xstatic __inline __declspec(__nothrow) __attribute__((const)) long double nanl(const char *__t) { return (long double)nan(__t); } +N#endif +N#if defined(_WANT_SNAN) && defined(__SUPPORT_SNAN__) +X#if 0L && 0L +Sextern _ARMABI_PURE double nans(const char */*tagp*/); +Sextern _ARMABI_PURE float nansf(const char */*tagp*/); +S#ifdef __HAVE_LONGDOUBLE +S_ARMABI_INLINE _ARMABI_FPEXCEPT long double nansl(const char *__t) \ +S { return (long double)nans(__t); } +X_ARMABI_INLINE _ARMABI_FPEXCEPT long double nansl(const char *__t) { return (long double)nans(__t); } +S#endif +N#endif +Nextern _ARMABI_FPEXCEPT double nearbyint(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double nearbyint(double ); +Nextern _ARMABI_FPEXCEPT float nearbyintf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float nearbyintf(float ); +N_ARMDEFLD1(nearbyint); +X__declspec(__nothrow) long double nearbyintl(long double ); +Nextern double remquo(double /*x*/, double /*y*/, int */*quo*/); +Nextern float remquof(float /*x*/, float /*y*/, int */*quo*/); +N#ifdef __HAVE_LONGDOUBLE +N_ARMABI_INLINE long double remquol(long double __x, long double __y, int *__q) \ +N { return (long double)remquo((double)__x, (double)__y, __q); } +Xstatic __inline long double remquol(long double __x, long double __y, int *__q) { return (long double)remquo((double)__x, (double)__y, __q); } +N#endif +Nextern _ARMABI_FPEXCEPT double round(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double round(double ); +Nextern _ARMABI_FPEXCEPT float roundf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float roundf(float ); +N_ARMDEFLD1(round); +X__declspec(__nothrow) long double roundl(long double ); +Nextern _ARMABI double tgamma(double /*x*/); /* * The gamma function of x. */ +Xextern __declspec(__nothrow) double tgamma(double ); +Nextern _ARMABI float tgammaf(float /*x*/); +Xextern __declspec(__nothrow) float tgammaf(float ); +N_ARMDEFLD1(tgamma); +X__declspec(__nothrow) long double tgammal(long double ); +Nextern _ARMABI_FPEXCEPT double trunc(double /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) double trunc(double ); +Nextern _ARMABI_FPEXCEPT float truncf(float /*x*/); +Xextern __declspec(__nothrow) __attribute__((const)) float truncf(float ); +N_ARMDEFLD1(trunc); +X__declspec(__nothrow) long double truncl(long double ); +N#endif +N +N#undef _ARMDEFLD1 +N#undef _ARMDEFLD1P +N#undef _ARMDEFLD2 +N +N#if defined(__cplusplus) && ((!defined(__STRICT_ANSI__) || defined(__USE_C99_MATH)) || defined(__ARMCOMPILER_LIBCXX)) +X#if 0L && ((!0L || 1L) || 0L) +S extern "C++" { +S inline int (fpclassify)(double __x) { return fpclassify(__x); } +S inline bool (isfinite)(double __x) { return isfinite(__x); } +S inline bool (isgreater)(double __x, double __y) { return isgreater(__x, __y); } +S inline bool (isgreaterequal)(double __x, double __y) { return isgreaterequal(__x, __y); } +S inline bool (isinf)(double __x) { return isinf(__x); } +S inline bool (isless)(double __x, double __y) { return isless(__x, __y); } +S inline bool (islessequal)(double __x, double __y) { return islessequal(__x, __y); } +S inline bool (islessgreater)(double __x, double __y) { return islessgreater(__x, __y); } +S inline bool (isnan)(double __x) { return isnan(__x); } +S inline bool (isnormal)(double __x) { return isnormal(__x); } +S inline bool (isunordered)(double __x, double __y) { return isunordered(__x, __y); } +S +S } +N#endif +N +N#if defined(__cplusplus) && !defined(__ARMCOMPILER_LIBCXX) +X#if 0L && !0L +S extern "C++" { +S inline float abs(float __x) { return fabsf(__x); } +S inline float acos(float __x) { return acosf(__x); } +S inline float asin(float __x) { return asinf(__x); } +S inline float atan(float __x) { return atanf(__x); } +S inline float atan2(float __y, float __x) { return atan2f(__y,__x); } +S inline float ceil(float __x) { return ceilf(__x); } +S inline float cos(float __x) { return cosf(__x); } +S inline float cosh(float __x) { return coshf(__x); } +S inline float exp(float __x) { return expf(__x); } +S inline float fabs(float __x) { return fabsf(__x); } +S inline float floor(float __x) { return floorf(__x); } +S inline float fmod(float __x, float __y) { return fmodf(__x, __y); } +S float frexp(float __x, int* __exp) __attribute__((__nonnull__(2))); +S inline float frexp(float __x, int* __exp) { return frexpf(__x, __exp); } +S inline float ldexp(float __x, int __exp) { return ldexpf(__x, __exp);} +S inline float log(float __x) { return logf(__x); } +S inline float log10(float __x) { return log10f(__x); } +S float modf(float __x, float* __iptr) __attribute__((__nonnull__(2))); +S inline float modf(float __x, float* __iptr) { return modff(__x, __iptr); } +S inline float pow(float __x, float __y) { return powf(__x,__y); } +S inline float pow(float __x, int __y) { return powf(__x, (float)__y); } +S inline float sin(float __x) { return sinf(__x); } +S inline float sinh(float __x) { return sinhf(__x); } +S inline float sqrt(float __x) { return sqrtf(__x); } +S inline float _sqrt(float __x) { return _sqrtf(__x); } +S inline float tan(float __x) { return tanf(__x); } +S inline float tanh(float __x) { return tanhf(__x); } +S +S inline double abs(double __x) { return fabs(__x); } +S inline double pow(double __x, int __y) +S { return pow(__x, (double) __y); } +S +S#ifdef __HAVE_LONGDOUBLE +S inline long double abs(long double __x) +S { return (long double)fabsl(__x); } +S inline long double acos(long double __x) +S { return (long double)acosl(__x); } +S inline long double asin(long double __x) +S { return (long double)asinl(__x); } +S inline long double atan(long double __x) +S { return (long double)atanl(__x); } +S inline long double atan2(long double __y, long double __x) +S { return (long double)atan2l(__y, __x); } +S inline long double ceil(long double __x) +S { return (long double)ceill( __x); } +S inline long double cos(long double __x) +S { return (long double)cosl(__x); } +S inline long double cosh(long double __x) +S { return (long double)coshl(__x); } +S inline long double exp(long double __x) +S { return (long double)expl(__x); } +S inline long double fabs(long double __x) +S { return (long double)fabsl(__x); } +S inline long double floor(long double __x) +S { return (long double)floorl(__x); } +S inline long double fmod(long double __x, long double __y) +S { return (long double)fmodl(__x, __y); } +S long double frexp(long double __x, int* __p) __attribute__((__nonnull__(2))); +S inline long double frexp(long double __x, int* __p) +S { return (long double)frexpl(__x, __p); } +S inline long double ldexp(long double __x, int __exp) +S { return (long double)ldexpl(__x, __exp); } +S inline long double log(long double __x) +S { return (long double)logl(__x); } +S inline long double log10(long double __x) +S { return (long double)log10l(__x); } +S long double modf(long double __x, long double* __p) __attribute__((__nonnull__(2))); +S inline long double modf(long double __x, long double* __p) +S { return (long double)modfl(__x, __p); } +S inline long double pow(long double __x, long double __y) +S { return (long double)powl(__x, __y); } +S inline long double pow(long double __x, int __y) +S { return (long double)powl(__x, __y); } +S inline long double sin(long double __x) +S { return (long double)sinl(__x); } +S inline long double sinh(long double __x) +S { return (long double)sinhl(__x); } +S inline long double sqrt(long double __x) +S { return (long double)sqrtl(__x); } +S inline long double _sqrt(long double __x) +S { return (long double)_sqrt((double) __x); } +S inline long double tan(long double __x) +S { return (long double)tanl(__x); } +S inline long double tanh(long double __x) +S { return (long double)tanhl(__x); } +S#endif +S +S#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +S inline float acosh(float __x) { return acoshf(__x); } +S inline float asinh(float __x) { return asinhf(__x); } +S inline float atanh(float __x) { return atanhf(__x); } +S inline float cbrt(float __x) { return cbrtf(__x); } +S inline float erf(float __x) { return erff(__x); } +S inline float erfc(float __x) { return erfcf(__x); } +S inline float expm1(float __x) { return expm1f(__x); } +S inline float log1p(float __x) { return log1pf(__x); } +S inline float hypot(float __x, float __y) { return hypotf(__x, __y); } +S inline float lgamma(float __x) { return lgammaf(__x); } +S inline float remainder(float __x, float __y) { return remainderf(__x, __y); } +S inline float rint(float __x) { return rintf(__x); } +S#endif +S +S#ifdef __USE_C99_MATH +S inline float exp2(float __x) { return exp2f(__x); } +S inline float fdim(float __x, float __y) { return fdimf(__x, __y); } +S inline float fma(float __x, float __y, float __z) { return fmaf(__x, __y, __z); } +S inline float fmax(float __x, float __y) { return fmaxf(__x, __y); } +S inline float fmin(float __x, float __y) { return fminf(__x, __y); } +S inline float log2(float __x) { return log2f(__x); } +S inline _ARMABI long lrint(float __x) { return lrintf(__x); } +S inline _ARMABI __LONGLONG llrint(float __x) { return llrintf(__x); } +S inline _ARMABI long lround(float __x) { return lroundf(__x); } +S inline _ARMABI __LONGLONG llround(float __x) { return llroundf(__x); } +S inline _ARMABI_FPEXCEPT float nearbyint(float __x) { return nearbyintf(__x); } +S inline float remquo(float __x, float __y, int *__q) { return remquof(__x, __y, __q); } +S inline _ARMABI_FPEXCEPT float round(float __x) { return roundf(__x); } +S inline float tgamma(float __x) { return tgammaf(__x); } +S inline _ARMABI_FPEXCEPT float trunc(float __x) { return truncf(__x); } +S +S inline int (fpclassify)(float __x) { return fpclassify(__x); } +S inline bool (isfinite)(float __x) { return isfinite(__x); } +S inline bool (isgreater)(float __x, float __y) { return isgreater(__x, __y); } +S inline bool (isgreaterequal)(float __x, float __y) { return isgreaterequal(__x, __y); } +S inline bool (isinf)(float __x) { return isinf(__x); } +S inline bool (isless)(float __x, float __y) { return isless(__x, __y); } +S inline bool (islessequal)(float __x, float __y) { return islessequal(__x, __y); } +S inline bool (islessgreater)(float __x, float __y) { return islessgreater(__x, __y); } +S inline bool (isnan)(float __x) { return isnan(__x); } +S inline bool (isnormal)(float __x) { return isnormal(__x); } +S inline bool (isunordered)(float __x, float __y) { return isunordered(__x, __y); } +S +S#ifdef __HAVE_LONGDOUBLE +S inline long double acosh(long double __x) { return acoshl(__x); } +S inline long double asinh(long double __x) { return asinhl(__x); } +S inline long double atanh(long double __x) { return atanhl(__x); } +S inline long double cbrt(long double __x) { return cbrtl(__x); } +S inline long double erf(long double __x) { return erfl(__x); } +S inline long double erfc(long double __x) { return erfcl(__x); } +S inline long double expm1(long double __x) { return expm1l(__x); } +S inline long double log1p(long double __x) { return log1pl(__x); } +S inline long double hypot(long double __x, long double __y) { return hypotl(__x, __y); } +S inline long double lgamma(long double __x) { return lgammal(__x); } +S inline long double remainder(long double __x, long double __y) { return remainderl(__x, __y); } +S inline long double rint(long double __x) { return rintl(__x); } +S inline long double exp2(long double __x) { return exp2l(__x); } +S inline long double fdim(long double __x, long double __y) { return fdiml(__x, __y); } +S inline long double fma(long double __x, long double __y, long double __z) { return fmal(__x, __y, __z); } +S inline long double fmax(long double __x, long double __y) { return fmaxl(__x, __y); } +S inline long double fmin(long double __x, long double __y) { return fminl(__x, __y); } +S inline long double log2(long double __x) { return log2l(__x); } +S inline _ARMABI long lrint(long double __x) { return lrintl(__x); } +S inline _ARMABI __LONGLONG llrint(long double __x) { return llrintl(__x); } +S inline _ARMABI long lround(long double __x) { return lroundl(__x); } +S inline _ARMABI __LONGLONG llround(long double __x) { return llroundl(__x); } +S inline _ARMABI_FPEXCEPT long double nearbyint(long double __x) { return nearbyintl(__x); } +S inline long double remquo(long double __x, long double __y, int *__q) { return remquol(__x, __y, __q); } +S inline _ARMABI_FPEXCEPT long double round(long double __x) { return roundl(__x); } +S inline long double tgamma(long double __x) { return tgammal(__x); } +S inline _ARMABI_FPEXCEPT long double trunc(long double __x) { return truncl(__x); } +S inline int (fpclassify)(long double __x) { return fpclassify(__x); } +S inline bool (isfinite)(long double __x) { return isfinite(__x); } +S inline bool (isgreater)(long double __x, long double __y) { return isgreater(__x, __y); } +S inline bool (isgreaterequal)(long double __x, long double __y) { return isgreaterequal(__x, __y); } +S inline bool (isinf)(long double __x) { return isinf(__x); } +S inline bool (isless)(long double __x, long double __y) { return isless(__x, __y); } +S inline bool (islessequal)(long double __x, long double __y) { return islessequal(__x, __y); } +S inline bool (islessgreater)(long double __x, long double __y) { return islessgreater(__x, __y); } +S inline bool (isnan)(long double __x) { return isnan(__x); } +S inline bool (isnormal)(long double __x) { return isnormal(__x); } +S inline bool (isunordered)(long double __x, long double __y) { return isunordered(__x, __y); } +S#endif +S +S#undef fpclassify +S#undef isfinite +S#undef isgreater +S#undef isgreaterequal +S#undef isinf +S#undef isless +S#undef islessequal +S#undef islessgreater +S#undef isnan +S#undef isnormal +S#undef isunordered +S +S#endif +S +S } +N#endif +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif +N #endif /* __MATH_DECLS */ +N +N #if _AEABI_PORTABILITY_LEVEL != 0 && !defined _AEABI_PORTABLE +X #if _AEABI_PORTABILITY_LEVEL != 0 && !0L +S #define _AEABI_PORTABLE +N #endif +N +N #if defined(__cplusplus) && !defined(__MATH_NO_EXPORTS) +X #if 0L && !0L +S using ::std::__use_accurate_range_reduction; +S #ifndef __ARMCOMPILER_LIBCXX +S using ::std::abs; +S #endif +S using ::std::acos; +S using ::std::asin; +S using ::std::atan2; +S using ::std::atan; +S using ::std::ceil; +S using ::std::cos; +S using ::std::cosh; +S using ::std::exp; +S using ::std::fabs; +S using ::std::floor; +S using ::std::fmod; +S using ::std::frexp; +S using ::std::ldexp; +S using ::std::log10; +S using ::std::log; +S using ::std::modf; +S using ::std::pow; +S using ::std::sin; +S using ::std::sinh; +S using ::std::sqrt; +S using ::std::_sqrt; +S using ::std::_sqrtf; +S using ::std::tan; +S using ::std::tanh; +S using ::std::_fabsf; +S /* C99 float and long double versions in already-C89-reserved namespace */ +S using ::std::acosf; +S using ::std::acosl; +S using ::std::asinf; +S using ::std::asinl; +S using ::std::atan2f; +S using ::std::atan2l; +S using ::std::atanf; +S using ::std::atanl; +S using ::std::ceilf; +S using ::std::ceill; +S using ::std::cosf; +S using ::std::coshf; +S using ::std::coshl; +S using ::std::cosl; +S using ::std::expf; +S using ::std::expl; +S using ::std::fabsf; +S using ::std::fabsl; +S using ::std::floorf; +S using ::std::floorl; +S using ::std::fmodf; +S using ::std::fmodl; +S using ::std::frexpf; +S using ::std::frexpl; +S using ::std::ldexpf; +S using ::std::ldexpl; +S using ::std::log10f; +S using ::std::log10l; +S using ::std::logf; +S using ::std::logl; +S using ::std::modff; +S using ::std::modfl; +S using ::std::powf; +S using ::std::powl; +S using ::std::sinf; +S using ::std::sinhf; +S using ::std::sinhl; +S using ::std::sinl; +S using ::std::sqrtf; +S using ::std::sqrtl; +S using ::std::tanf; +S using ::std::tanhf; +S using ::std::tanhl; +S using ::std::tanl; +S #if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +S /* C99 additions which for historical reasons appear in non-strict mode */ +S using ::std::acosh; +S using ::std::asinh; +S using ::std::atanh; +S using ::std::cbrt; +S using ::std::copysign; +S using ::std::copysignf; +S using ::std::erf; +S using ::std::erfc; +S using ::std::expm1; +S using ::std::hypot; +S using ::std::ilogb; +S using ::std::ilogbf; +S using ::std::ilogbl; +S using ::std::lgamma; +S using ::std::log1p; +S using ::std::logb; +S using ::std::logbf; +S using ::std::logbl; +S using ::std::nextafter; +S using ::std::nextafterf; +S using ::std::nextafterl; +S using ::std::nexttoward; +S using ::std::nexttowardf; +S using ::std::nexttowardl; +S using ::std::remainder; +S using ::std::rint; +S using ::std::scalbln; +S using ::std::scalblnf; +S using ::std::scalblnl; +S using ::std::scalbn; +S using ::std::scalbnf; +S using ::std::scalbnl; +S using ::std::math_errhandling; +S using ::std::acoshf; +S using ::std::acoshl; +S using ::std::asinhf; +S using ::std::asinhl; +S using ::std::atanhf; +S using ::std::atanhl; +S using ::std::copysignl; +S using ::std::cbrtf; +S using ::std::cbrtl; +S using ::std::erff; +S using ::std::erfl; +S using ::std::erfcf; +S using ::std::erfcl; +S using ::std::expm1f; +S using ::std::expm1l; +S using ::std::log1pf; +S using ::std::log1pl; +S using ::std::hypotf; +S using ::std::hypotl; +S using ::std::lgammaf; +S using ::std::lgammal; +S using ::std::remainderf; +S using ::std::remainderl; +S using ::std::rintf; +S using ::std::rintl; +S /* New in C99. */ +S using ::std::float_t; +S using ::std::double_t; +S #endif +S #if (defined(__clang__) && !defined(__STRICT_ANSI)) || defined(__USE_C99_MATH) +S /* Functions new in C99. */ +S using ::std::exp2; +S using ::std::exp2f; +S using ::std::exp2l; +S using ::std::fdim; +S using ::std::fdimf; +S using ::std::fdiml; +S using ::std::fma; +S using ::std::fmaf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::fmal; +S#endif +S using ::std::fmax; +S using ::std::fmaxf; +S using ::std::fmaxl; +S using ::std::fmin; +S using ::std::fminf; +S using ::std::fminl; +S using ::std::log2; +S using ::std::log2f; +S using ::std::log2l; +S using ::std::lrint; +S using ::std::lrintf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::lrintl; +S#endif +S using ::std::llrint; +S using ::std::llrintf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::llrintl; +S#endif +S using ::std::lround; +S using ::std::lroundf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::lroundl; +S#endif +S using ::std::llround; +S using ::std::llroundf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::llroundl; +S#endif +S using ::std::nan; +S using ::std::nanf; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::nanl; +S#endif +S using ::std::nearbyint; +S using ::std::nearbyintf; +S using ::std::nearbyintl; +S using ::std::remquo; +S using ::std::remquof; +S#ifdef __HAVE_LONGDOUBLE +S using ::std::remquol; +S#endif +S using ::std::round; +S using ::std::roundf; +S using ::std::roundl; +S using ::std::tgamma; +S using ::std::tgammaf; +S using ::std::tgammal; +S using ::std::trunc; +S using ::std::truncf; +S using ::std::truncl; +S #endif +S +S #if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) +S using ::std::fpclassify; +S using ::std::isfinite; +S using ::std::isgreater; +S using ::std::isgreaterequal; +S using ::std::isinf; +S using ::std::isless; +S using ::std::islessequal; +S using ::std::islessgreater; +S using ::std::isnan; +S using ::std::isnormal; +S using ::std::isunordered; +S #endif +N #endif +N +N#undef __LONGLONG +N +N#endif /* __math_h */ +N +N/* end of math.h */ +L 19 "..\..\src\common\tau_common.h" 2 +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N/** +N * \name 通用常量定义 +N * @{ +N */ +N//#define ENABLE 1 +N//#define DISABLE 0 +N +N#define ON 1 +N#define OFF 0 +N +N#define NONE 0 +N#define EOS '\0' +N +N/* +N#ifndef TRUE +N#define TRUE 1 +N#endif +N +N#ifndef FALSE +N#define FALSE 0 +N#endif +N*/ +N +N#ifndef __cplusplus +N#define true 1 +N#define false 0 +N#define bool _Bool +N#endif /* ifndef __cplusplus */ +N +N#ifndef NULL +N#define NULL ((void *)0) +N#endif +N +N#define TAU_LITTLE_ENDIAN 1234 /**< \brief 小端模式 */ +N#define TAU_BIG_ENDIAN 3412 /**< \brief 大端模式 */ +N +N/** @} */ +N +N/******************************************************************************/ +N +N/** +N * \name 常用宏定义 +N * @{ +N */ +N +N#ifdef __cplusplus +S#define __I volatile /*!< Defines 'read only' permissions */ +N#else +N#define __I volatile const /*!< Defines 'read only' permissions */ +N#endif +N#define __O volatile /*!< Defines 'write only' permissions */ +N#define __IO volatile /*!< Defines 'read / write' permissions */ +N +N#define TAU_INLINE inline +N#define TAU_STATIC_INLINE static inline +N#define TAU_STATIC static +N#define TAU_CONST const +N#define TAU_EXTERN extern +N +N#define MIN(x, y) (((x) < (y)) ? (x) : (y)) +N#define MAX(x, y) (((x) > (y)) ? (x) : (y)) +N +N/** +N * \brief 求结构体成员的偏移 +N * \attention 不同平台上，由于成员大小和内存对齐等原因， +N * 同一结构体成员的偏移可能是不一样的 +N * +N * \par 示例 +N * \code +N * struct my_struct { +N * int m1; +N * char m2; +N * }; +N * int offset_m2; +N * +N * offset_m2 = TAU_OFFSET(struct my_struct, m2); +N * \endcode +N */ +N#define TAU_OFFSET(structure, member) ((uint32_t)(&(((structure *)0)->member))) +N +N/** @} */ +N +N/** +N * \brief 通过结构体成员指针获取包含该结构体成员的结构体 +N * +N * \param ptr 指向结构体成员的指针 +N * \param type 结构体类型 +N * \param member 结构体中该成员的名称 +N * +N * \par 示例 +N * \code +N * struct my_struct = { +N * int m1; +N * char m2; +N * }; +N * struct my_struct my_st; +N * char *p_m2 = &my_st.m2; +N * struct my_struct *p_st = TAU_CONTAINER_OF(p_m2, struct my_struct, m2); +N * \endcode +N */ +N#define TAU_CONTAINER_OF(ptr, type, member) \ +N ((type *)((char *)(ptr)-TAU_OFFSET(type, member))) +X#define TAU_CONTAINER_OF(ptr, type, member) ((type *)((char *)(ptr)-TAU_OFFSET(type, member))) +N +N/** +N * \brief 计算结构体成员的大小 +N * +N * \code +N * struct a = { +N * uint32_t m1; +N * uint32_t m2; +N * }; +N * int size_m2; +N * +N * size_m2 = TAU_MEMBER_SIZE(a, m2); //size_m2 = 4 +N * \endcode +N */ +N#define TAU_MEMBER_SIZE(structure, member) (sizeof(((structure *)0)->member)) +N +N/** +N * \brief 计算数组元素个数 +N * +N * \code +N * int a[] = {0, 1, 2, 3}; +N * int element_a = TAU_NELEMENTS(a); // element_a = 4 +N * \endcode +N */ +N#define TAU_NELEMENTS(array) (sizeof(array) / sizeof((array)[0])) +N +N/** +N * \brief 向上舍入 +N * +N * \param x 被运算的数 +N * \param align 对齐因素 +N * +N * \code +N * int size = TAU_ROUND_UP(15, 4); // size = 16 +N * \endcode +N */ +N#define TAU_ROUND_UP(x, align) (((int)(x)/(align))*(align) + (((int)(x)%(align)) ? (align) : 0)) +N +N/** +N * \brief 向下舍入 +N * +N * \param x 被运算的数 +N * \param align 对齐因素 +N * +N * \code +N * int size = TAU_ROUND_DOWN(15, 4); // size = 12 +N * \endcode +N */ +N#define TAU_ROUND_DOWN(x, align) (((int)(x)/(align))*(align)) +N +N/** \brief 倍数向上舍入 */ +N#define TAU_DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d)) +N +N/** +N * \brief 测试是否对齐 +N * +N * \param x 被运算的数 +N * \param align 对齐因素，必须为2的乘方 +N * +N * \code +N * if (TAU_ALIGNED(x, 4) { +N * ; // x对齐 +N * } else { +N * ; // x不对齐 +N * } +N * \endcode +N */ +N#define TAU_ALIGNED(x, align) (((int)(x) & (align - 1)) == 0) +N +N/** \brief 将1字节BCD数据转换为16进制数据 */ +N#define TAU_BCD_TO_HEX(val) (((val)&0x0f) + ((val) >> 4) * 10) +N +N/** \brief 将1字节16进制数据转换为BCD数据 */ +N#define TAU_HEX_TO_BCD(val) ((((val) / 10) << 4) + (val) % 10) +N +N/** +N * \brief 向上取整 +N */ +N#define TAU_CEIL(val) ceil(val) +N +N +N/*! @brief Construct the version number for drivers. */ +N#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +N +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/*!< @brief 用于返回状态和错误 */ +Ntypedef uint32_t status_t; +N +N/* \brief 通用回调函数指针定义 */ +Ntypedef void (*fcb_type)(void *data); +N +Ntypedef void (*uart_trans_cb)(status_t status, void *user_data); +N +Ntypedef void (*flash_trans_cb)(status_t status, void *user_data); +N#endif /* __TAU_COMMON_H */ +L 21 "..\..\src\common\tau_device_datatype.h" 2 +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/*! @brief 计算组状态码 */ +N#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/*! @brief 分组状态值 */ +Nenum _status_groups +N{ +N STATUS_GROUP_GENERIC = 0, +N STATUS_GROUP_I2C = 1, +N STATUS_GROUP_UART = 2, +N STATUS_GROUP_SPI = 3, +N STATUS_GROUP_TIMER = 4, +N}; +N +N/*! @brief 常用状态码 */ +Nenum _generic_status +N{ +N STATUS_SUCCESS = MAKE_STATUS(STATUS_GROUP_GENERIC, 0), +X STATUS_SUCCESS = ((((STATUS_GROUP_GENERIC)*100) + (0))), +N STATUS_FAIL = MAKE_STATUS(STATUS_GROUP_GENERIC, 1), +X STATUS_FAIL = ((((STATUS_GROUP_GENERIC)*100) + (1))), +N STATUS_READ_ONLY = MAKE_STATUS(STATUS_GROUP_GENERIC, 2), +X STATUS_READ_ONLY = ((((STATUS_GROUP_GENERIC)*100) + (2))), +N STATUS_OUT_OF_RANGE = MAKE_STATUS(STATUS_GROUP_GENERIC, 3), +X STATUS_OUT_OF_RANGE = ((((STATUS_GROUP_GENERIC)*100) + (3))), +N STATUS_INVALID_ARGUMENT = MAKE_STATUS(STATUS_GROUP_GENERIC, 4), +X STATUS_INVALID_ARGUMENT = ((((STATUS_GROUP_GENERIC)*100) + (4))), +N STATUS_TIME_OUT = MAKE_STATUS(STATUS_GROUP_GENERIC, 5), +X STATUS_TIME_OUT = ((((STATUS_GROUP_GENERIC)*100) + (5))), +N STATUS_NO_TRANSFER_IN_PROGRESS = MAKE_STATUS(STATUS_GROUP_GENERIC, 6), +X STATUS_NO_TRANSFER_IN_PROGRESS = ((((STATUS_GROUP_GENERIC)*100) + (6))), +N}; +N +N/** +N* @brief UART状态枚举定义 +N* +N*/ +Ntypedef enum +N{ +N STATUS_UART_TX_BUSY = MAKE_STATUS(STATUS_GROUP_UART, 0), /*!< Transmitter is busy. */ +X STATUS_UART_TX_BUSY = ((((STATUS_GROUP_UART)*100) + (0))), +N STATUS_UART_RX_BUSY = MAKE_STATUS(STATUS_GROUP_UART, 1), /*!< Receiver is busy. */ +X STATUS_UART_RX_BUSY = ((((STATUS_GROUP_UART)*100) + (1))), +N STATUS_UART_TX_IDLE = MAKE_STATUS(STATUS_GROUP_UART, 2), /*!< USART transmitter is idle. */ +X STATUS_UART_TX_IDLE = ((((STATUS_GROUP_UART)*100) + (2))), +N STATUS_UART_RX_IDLE = MAKE_STATUS(STATUS_GROUP_UART, 3), /*!< USART receiver is idle. */ +X STATUS_UART_RX_IDLE = ((((STATUS_GROUP_UART)*100) + (3))), +N STATUS_UART_TX_ERR = MAKE_STATUS(STATUS_GROUP_UART, 7), /*!< Error happens on txFIFO. */ +X STATUS_UART_TX_ERR = ((((STATUS_GROUP_UART)*100) + (7))), +N STATUS_UART_RX_ERR = MAKE_STATUS(STATUS_GROUP_UART, 9), /*!< Error happens on rxFIFO. */ +X STATUS_UART_RX_ERR = ((((STATUS_GROUP_UART)*100) + (9))), +N STATUS_UART_RX_RING_BUFF_OVERRUN = MAKE_STATUS(STATUS_GROUP_UART, 8), /*!< Error happens on rx ring buffer */ +X STATUS_UART_RX_RING_BUFF_OVERRUN = ((((STATUS_GROUP_UART)*100) + (8))), +N STATUS_UART_NOISE_ERR = MAKE_STATUS(STATUS_GROUP_UART, 10), /*!< USART noise error. */ +X STATUS_UART_NOISE_ERR = ((((STATUS_GROUP_UART)*100) + (10))), +N STATUS_UART_FRAMING_ERR = MAKE_STATUS(STATUS_GROUP_UART, 11), /*!< USART framing error. */ +X STATUS_UART_FRAMING_ERR = ((((STATUS_GROUP_UART)*100) + (11))), +N STATUS_UART_PARITY_ERR = MAKE_STATUS(STATUS_GROUP_UART, 12), /*!< USART parity error. */ +X STATUS_UART_PARITY_ERR = ((((STATUS_GROUP_UART)*100) + (12))), +N STATUS_UART_BAUDRATE_NOT_SPT = MAKE_STATUS(STATUS_GROUP_UART, 13), /*!< Baudrate is not support in current clock source */ +X STATUS_UART_BAUDRATE_NOT_SPT = ((((STATUS_GROUP_UART)*100) + (13))), +N} uart_status_e; +N +N/*! +N * @brief timer状态 +N */ +Ntypedef enum +N{ +N STATUS_TIMER_IDLE = MAKE_STATUS(STATUS_GROUP_TIMER, 0), /*!< 空闲 */ +X STATUS_TIMER_IDLE = ((((STATUS_GROUP_TIMER)*100) + (0))), +N STATUS_TIMER_RUNNING = MAKE_STATUS(STATUS_GROUP_TIMER, 1), /*!< 运行中 */ +X STATUS_TIMER_RUNNING = ((((STATUS_GROUP_TIMER)*100) + (1))), +N STATUS_TIMER_TIMEOUT = MAKE_STATUS(STATUS_GROUP_TIMER, 2), /*!< 超时 */ +X STATUS_TIMER_TIMEOUT = ((((STATUS_GROUP_TIMER)*100) + (2))), +N} timer_status_e; +N +N/*! +N * @brief system触发事件(中断/复位)模式 +N */ +Ntypedef enum +N{ +N DETECT_HIGH_LVL = 0, +N DETECT_LOW_LVL, +N DETECT_RISING_EDGE, +N DETECT_FALLING_EDGE, +N DETECT_DOUBLE_EDGE +N} sys_cfg_trigger_e; +N +N/** +N* @brief GPIO interrupt type +N*/ +Ntypedef enum +N{ +N TIMER_NUM0 = 0, +N TIMER_NUM1, +N TIMER_NUM2, +N TIMER_NUM3, +N TIMER_NUM_MAX +N} timer_num_e; +N +N/** +N* @brief GPIO interrupt type +N*/ +Ntypedef enum +N{ +N GPIO_INT_EXTI_INT0 = 0, +N GPIO_INT_EXTI_INT1, +N GPIO_INT_EXTI_INT2, +N GPIO_INT_EXTI_INT3, +N GPIO_INT_EXTI_INT4, +N GPIO_INT_EXTI_INT5, +N GPIO_INT_EXTI_INT6, +N GPIO_INT_EXTI_INT7, +N GPIO_INT_MAX +N} gpio_int_e; +N +N/*! @brief PWMI中断类型 */ +Ntypedef enum _pwm_int_type +N{ +N PWM_INT_HIGH_OVERFLOW = 0, +N PWM_INT_LOW_OVERFLOW, +N PWM_INT_TOTAL_OVERFLOW, +N PWM_INT_HIGH_DONE, +N PWM_INT_LOW_DONE, +N PWM_INT_TOTAL_DONE, +N PWM_INT_MAX +N} pwm_int_type_e; +N +N/** +N* @brief I2C chose +N*/ +Ntypedef enum +N{ +N I2C_SELECT_0 = 0, //常用slave +N I2C_SELECT_1, //常用master +N} i2c_select_e; +N +N/*! +N * @brief 传输速度 +N * @note +N */ +Ntypedef enum _i2c_rate +N{ +N I2C_RATE_STANDARD = 1, //100kHz +N I2C_RATE_FAST, //400kHz +N I2C_RATE_HIGH, //1MHz +N} i2c_rate_e; +N +N/*! +N * @brief I2C Index +N * @note +N */ +Ntypedef enum +N{ +N I2C_INDEX_0, +N I2C_INDEX_1, +N I2C_INDEX_2, +N I2C_INDEX_MAX +N} i2c_index_e; +N +N/*! +N * @brief DMA channel type +N * @note +N */ +Ntypedef enum +N{ +N AHB_DMA_CH0, +N AHB_DMA_CH1, +N AHB_DMA_CH2, +N AHB_DMA_CH3, +N AHB_DMA_CH4, +N AHB_DMA_CH5, +N AHB_DMA_CH6, +N AHB_DMA_CH7, +N AHB_DMA_CH_NUM +N} dma_channel_type_e; +N +N/*! @brief Type used for all status and error return values. */ +N +Ntypedef enum +N{ +N DISABLE = 0, +N ENABLE = !DISABLE +N} function_state_e; +N +N/** +N* @brief The reversal types of the bit order of the input/output data +N*/ +Ntypedef enum +N{ +N CRC_REV_NO_TRANSPOSE = 0, /*!< No transposition */ +N CRC_REV_ONLY_BITS_TRANSPOSE, /*!< Bits in bytes are transposed; bytes are not transposed */ +N CRC_REV_BOTH_TRANSPOSE, /*!< Both bits in bytes and bytes are transposed */ +N CRC_REV_ONLY_BYTES_TRANSPOSE, /*!< Only bytes are transposed; no bits in a byte are transposed */ +N} crc_reversal_type_e; +N +N/** +N* @brief Complement Read Of CRC Data Register +N*/ +Ntypedef enum +N{ +N CRC_FXOR_DISABLE = 0, /*!< No XOR on reading */ +N CRC_FXOR_ENABLE, /*!< Invert or complement the read value of the CRC Data register */ +N} crc_fxor_function_e; +N +N/** +N* @brief width of CRC protocol (polynomial) +N*/ +Ntypedef enum +N{ +N CRC_16_BIT_PROTOCOL = 0, /*!< 0: 16-bit CRC protocol */ +N CRC_32_BIT_PROTOCOL, /*!< 1: 32-bit CRC protocol */ +N} crc_protocol_type_e; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N#endif +N +L 12 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "tau_log.h" +L 1 "..\..\src\common\tau_log.h" 1 +N/******************************************************************************* +N* +N* +N* File: tau_log.h +N* Description log file +N* Version V0.1 +N* Date 2020-12-08 +N* Author linyw +N*******************************************************************************/ +N#ifndef _TAU_LOG_H_ +N#define _TAU_LOG_H_ +N +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include +N#include +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h" 1 +N/* string.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.11 */ +N/* Copyright (C) Codemist Ltd., 1988-1993. */ +N/* Copyright 1991-1993 ARM Limited. All rights reserved. */ +N/* version 0.04 */ +N +N/* +N * RCS $Revision$ +N * Checkin $Date$ +N */ +N +N/* +N * string.h declares one type and several functions, and defines one macro +N * useful for manipulating character arrays and other objects treated as +N * character arrays. Various methods are used for determining the lengths of +N * the arrays, but in all cases a char * or void * argument points to the +N * initial (lowest addresses) character of the array. If an array is written +N * beyond the end of an object, the behaviour is undefined. +N */ +N +N#ifndef __string_h +N#define __string_h +N#define __ARMCLIB_VERSION 5060037 +N +N#define _ARMABI __declspec(__nothrow) +N +N #ifndef __STRING_DECLS +N #define __STRING_DECLS +N +N #undef __CLIBNS +N +N #ifdef __cplusplus +S namespace std { +S #define __CLIBNS std:: +S extern "C" { +N #else +N #define __CLIBNS +N #endif /* __cplusplus */ +N +N#if defined(__cplusplus) || !defined(__STRICT_ANSI__) +X#if 0L || !0L +N /* unconditional in C++ and non-strict C for consistency of debug info */ +N #if __sizeof_ptr == 8 +X #if 4 == 8 +S typedef unsigned long size_t; /* see */ +N #else +N typedef unsigned int size_t; /* see */ +N #endif +N#elif !defined(__size_t) +X#elif !0L +S #define __size_t 1 +S #if __sizeof_ptr == 8 +S typedef unsigned long size_t; /* see */ +S #else +S typedef unsigned int size_t; /* see */ +S #endif +N#endif +N +N#undef NULL +N#define NULL 0 /* see */ +N +Nextern _ARMABI void *memcpy(void * __restrict /*s1*/, +Xextern __declspec(__nothrow) void *memcpy(void * __restrict , +N const void * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +N /* +N * copies n characters from the object pointed to by s2 into the object +N * pointed to by s1. If copying takes place between objects that overlap, +N * the behaviour is undefined. +N * Returns: the value of s1. +N */ +Nextern _ARMABI void *memmove(void * /*s1*/, +Xextern __declspec(__nothrow) void *memmove(void * , +N const void * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +N /* +N * copies n characters from the object pointed to by s2 into the object +N * pointed to by s1. Copying takes place as if the n characters from the +N * object pointed to by s2 are first copied into a temporary array of n +N * characters that does not overlap the objects pointed to by s1 and s2, +N * and then the n characters from the temporary array are copied into the +N * object pointed to by s1. +N * Returns: the value of s1. +N */ +Nextern _ARMABI char *strcpy(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strcpy(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); +N /* +N * copies the string pointed to by s2 (including the terminating nul +N * character) into the array pointed to by s1. If copying takes place +N * between objects that overlap, the behaviour is undefined. +N * Returns: the value of s1. +N */ +Nextern _ARMABI char *strncpy(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strncpy(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * copies not more than n characters (characters that follow a null +N * character are not copied) from the array pointed to by s2 into the array +N * pointed to by s1. If copying takes place between objects that overlap, +N * the behaviour is undefined. +N * Returns: the value of s1. +N */ +N +Nextern _ARMABI char *strcat(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strcat(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(1,2))); +N /* +N * appends a copy of the string pointed to by s2 (including the terminating +N * null character) to the end of the string pointed to by s1. The initial +N * character of s2 overwrites the null character at the end of s1. +N * Returns: the value of s1. +N */ +Nextern _ARMABI char *strncat(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strncat(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * appends not more than n characters (a null character and characters that +N * follow it are not appended) from the array pointed to by s2 to the end of +N * the string pointed to by s1. The initial character of s2 overwrites the +N * null character at the end of s1. A terminating null character is always +N * appended to the result. +N * Returns: the value of s1. +N */ +N +N/* +N * The sign of a nonzero value returned by the comparison functions is +N * determined by the sign of the difference between the values of the first +N * pair of characters (both interpreted as unsigned char) that differ in the +N * objects being compared. +N */ +N +Nextern _ARMABI int memcmp(const void * /*s1*/, const void * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int memcmp(const void * , const void * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * compares the first n characters of the object pointed to by s1 to the +N * first n characters of the object pointed to by s2. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the object pointed to by s1 is greater than, equal to, or +N * less than the object pointed to by s2. +N */ +Nextern _ARMABI int strcmp(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strcmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * compares the string pointed to by s1 to the string pointed to by s2. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2. +N */ +Nextern _ARMABI int strncmp(const char * /*s1*/, const char * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strncmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * compares not more than n characters (characters that follow a null +N * character are not compared) from the array pointed to by s1 to the array +N * pointed to by s2. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2. +N */ +Nextern _ARMABI int strcasecmp(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strcasecmp(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * compares the string pointed to by s1 to the string pointed to by s2, +N * case-insensitively as defined by the current locale. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2. +N */ +Nextern _ARMABI int strncasecmp(const char * /*s1*/, const char * /*s2*/, size_t /*n*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strncasecmp(const char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * compares not more than n characters (characters that follow a null +N * character are not compared) from the array pointed to by s1 to the array +N * pointed to by s2, case-insensitively as defined by the current locale. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2. +N */ +Nextern _ARMABI int strcoll(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) int strcoll(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * compares the string pointed to by s1 to the string pointed to by s2, both +N * interpreted as appropriate to the LC_COLLATE category of the current +N * locale. +N * Returns: an integer greater than, equal to, or less than zero, according +N * as the string pointed to by s1 is greater than, equal to, or +N * less than the string pointed to by s2 when both are interpreted +N * as appropriate to the current locale. +N */ +N +Nextern _ARMABI size_t strxfrm(char * __restrict /*s1*/, const char * __restrict /*s2*/, size_t /*n*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) size_t strxfrm(char * __restrict , const char * __restrict , size_t ) __attribute__((__nonnull__(2))); +N /* +N * transforms the string pointed to by s2 and places the resulting string +N * into the array pointed to by s1. The transformation function is such that +N * if the strcmp function is applied to two transformed strings, it returns +N * a value greater than, equal to or less than zero, corresponding to the +N * result of the strcoll function applied to the same two original strings. +N * No more than n characters are placed into the resulting array pointed to +N * by s1, including the terminating null character. If n is zero, s1 is +N * permitted to be a null pointer. If copying takes place between objects +N * that overlap, the behaviour is undefined. +N * Returns: The length of the transformed string is returned (not including +N * the terminating null character). If the value returned is n or +N * more, the contents of the array pointed to by s1 are +N * indeterminate. +N */ +N +N +N#ifdef __cplusplus +Sextern _ARMABI const void *memchr(const void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1))); +Sextern "C++" void *memchr(void * __s, int __c, size_t __n) __attribute__((__nonnull__(1))); +Sextern "C++" inline void *memchr(void * __s, int __c, size_t __n) +S { return const_cast(memchr(const_cast(__s), __c, __n)); } +N#else +Nextern _ARMABI void *memchr(const void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) void *memchr(const void * , int , size_t ) __attribute__((__nonnull__(1))); +N#endif +N /* +N * locates the first occurence of c (converted to an unsigned char) in the +N * initial n characters (each interpreted as unsigned char) of the object +N * pointed to by s. +N * Returns: a pointer to the located character, or a null pointer if the +N * character does not occur in the object. +N */ +N +N#ifdef __cplusplus +Sextern _ARMABI const char *strchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); +Sextern "C++" char *strchr(char * __s, int __c) __attribute__((__nonnull__(1))); +Sextern "C++" inline char *strchr(char * __s, int __c) +S { return const_cast(strchr(const_cast(__s), __c)); } +N#else +Nextern _ARMABI char *strchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) char *strchr(const char * , int ) __attribute__((__nonnull__(1))); +N#endif +N /* +N * locates the first occurence of c (converted to an char) in the string +N * pointed to by s (including the terminating null character). +N * Returns: a pointer to the located character, or a null pointer if the +N * character does not occur in the string. +N */ +N +Nextern _ARMABI size_t strcspn(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) size_t strcspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * computes the length of the initial segment of the string pointed to by s1 +N * which consists entirely of characters not from the string pointed to by +N * s2. The terminating null character is not considered part of s2. +N * Returns: the length of the segment. +N */ +N +N#ifdef __cplusplus +Sextern _ARMABI const char *strpbrk(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Sextern "C++" char *strpbrk(char * __s1, const char * __s2) __attribute__((__nonnull__(1,2))); +Sextern "C++" inline char *strpbrk(char * __s1, const char * __s2) +S { return const_cast(strpbrk(const_cast(__s1), __s2)); } +N#else +Nextern _ARMABI char *strpbrk(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strpbrk(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N#endif +N /* +N * locates the first occurence in the string pointed to by s1 of any +N * character from the string pointed to by s2. +N * Returns: returns a pointer to the character, or a null pointer if no +N * character form s2 occurs in s1. +N */ +N +N#ifdef __cplusplus +Sextern _ARMABI const char *strrchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); +Sextern "C++" char *strrchr(char * __s, int __c) __attribute__((__nonnull__(1))); +Sextern "C++" inline char *strrchr(char * __s, int __c) +S { return const_cast(strrchr(const_cast(__s), __c)); } +N#else +Nextern _ARMABI char *strrchr(const char * /*s*/, int /*c*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) char *strrchr(const char * , int ) __attribute__((__nonnull__(1))); +N#endif +N /* +N * locates the last occurence of c (converted to a char) in the string +N * pointed to by s. The terminating null character is considered part of +N * the string. +N * Returns: returns a pointer to the character, or a null pointer if c does +N * not occur in the string. +N */ +N +Nextern _ARMABI size_t strspn(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) size_t strspn(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N /* +N * computes the length of the initial segment of the string pointed to by s1 +N * which consists entirely of characters from the string pointed to by S2 +N * Returns: the length of the segment. +N */ +N +N#ifdef __cplusplus +Sextern _ARMABI const char *strstr(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Sextern "C++" char *strstr(char * __s1, const char * __s2) __attribute__((__nonnull__(1,2))); +Sextern "C++" inline char *strstr(char * __s1, const char * __s2) +S { return const_cast(strstr(const_cast(__s1), __s2)); } +N#else +Nextern _ARMABI char *strstr(const char * /*s1*/, const char * /*s2*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) char *strstr(const char * , const char * ) __attribute__((__nonnull__(1,2))); +N#endif +N /* +N * locates the first occurence in the string pointed to by s1 of the +N * sequence of characters (excluding the terminating null character) in the +N * string pointed to by s2. +N * Returns: a pointer to the located string, or a null pointer if the string +N * is not found. +N */ +N +Nextern _ARMABI char *strtok(char * __restrict /*s1*/, const char * __restrict /*s2*/) __attribute__((__nonnull__(2))); +Xextern __declspec(__nothrow) char *strtok(char * __restrict , const char * __restrict ) __attribute__((__nonnull__(2))); +Nextern _ARMABI char *_strtok_r(char * /*s1*/, const char * /*s2*/, char ** /*ptr*/) __attribute__((__nonnull__(2,3))); +Xextern __declspec(__nothrow) char *_strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); +N#ifndef __STRICT_ANSI__ +Nextern _ARMABI char *strtok_r(char * /*s1*/, const char * /*s2*/, char ** /*ptr*/) __attribute__((__nonnull__(2,3))); +Xextern __declspec(__nothrow) char *strtok_r(char * , const char * , char ** ) __attribute__((__nonnull__(2,3))); +N#endif +N /* +N * A sequence of calls to the strtok function breaks the string pointed to +N * by s1 into a sequence of tokens, each of which is delimited by a +N * character from the string pointed to by s2. The first call in the +N * sequence has s1 as its first argument, and is followed by calls with a +N * null pointer as their first argument. The separator string pointed to by +N * s2 may be different from call to call. +N * The first call in the sequence searches for the first character that is +N * not contained in the current separator string s2. If no such character +N * is found, then there are no tokens in s1 and the strtok function returns +N * a null pointer. If such a character is found, it is the start of the +N * first token. +N * The strtok function then searches from there for a character that is +N * contained in the current separator string. If no such character is found, +N * the current token extends to the end of the string pointed to by s1, and +N * subsequent searches for a token will fail. If such a character is found, +N * it is overwritten by a null character, which terminates the current +N * token. The strtok function saves a pointer to the following character, +N * from which the next search for a token will start. +N * Each subsequent call, with a null pointer as the value for the first +N * argument, starts searching from the saved pointer and behaves as +N * described above. +N * Returns: pointer to the first character of a token, or a null pointer if +N * there is no token. +N * +N * strtok_r() is a common extension which works exactly like +N * strtok(), but instead of storing its state in a hidden +N * library variable, requires the user to pass in a pointer to a +N * char * variable which will be used instead. Any sequence of +N * calls to strtok_r() passing the same char ** pointer should +N * behave exactly like the corresponding sequence of calls to +N * strtok(). This means that strtok_r() can safely be used in +N * multi-threaded programs, and also that you can tokenise two +N * strings in parallel. +N */ +N +Nextern _ARMABI void *memset(void * /*s*/, int /*c*/, size_t /*n*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) void *memset(void * , int , size_t ) __attribute__((__nonnull__(1))); +N /* +N * copies the value of c (converted to an unsigned char) into each of the +N * first n charactes of the object pointed to by s. +N * Returns: the value of s. +N */ +Nextern _ARMABI char *strerror(int /*errnum*/); +Xextern __declspec(__nothrow) char *strerror(int ); +N /* +N * maps the error number in errnum to an error message string. +N * Returns: a pointer to the string, the contents of which are +N * implementation-defined. The array pointed to shall not be +N * modified by the program, but may be overwritten by a +N * subsequent call to the strerror function. +N */ +Nextern _ARMABI size_t strlen(const char * /*s*/) __attribute__((__nonnull__(1))); +Xextern __declspec(__nothrow) size_t strlen(const char * ) __attribute__((__nonnull__(1))); +N /* +N * computes the length of the string pointed to by s. +N * Returns: the number of characters that precede the terminating null +N * character. +N */ +N +Nextern _ARMABI size_t strlcpy(char * /*dst*/, const char * /*src*/, size_t /*len*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) size_t strlcpy(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * copies the string src into the string dst, using no more than +N * len bytes of dst. Always null-terminates dst _within the +N * length len (i.e. will copy at most len-1 bytes of string plus +N * a NUL), unless len is actually zero. +N * +N * Return value is the length of the string that _would_ have +N * been written, i.e. the length of src. Thus, the operation +N * succeeded without truncation if and only if ret < len; +N * otherwise, the value in ret tells you how big to make dst if +N * you decide to reallocate it. (That value does _not_ include +N * the NUL.) +N * +N * This is a BSD-derived library extension, which we are +N * permitted to declare in a standard header because ISO defines +N * function names beginning with 'str' as reserved for future +N * expansion of . +N */ +N +Nextern _ARMABI size_t strlcat(char * /*dst*/, const char * /*src*/, size_t /*len*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) size_t strlcat(char * , const char * , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * concatenates the string src to the string dst, using no more +N * than len bytes of dst. Always null-terminates dst _within the +N * length len (i.e. will copy at most len-1 bytes of string plus +N * a NUL), unless len is actually zero. +N * +N * Return value is the length of the string that _would_ have +N * been written, i.e. the length of src plus the original length +N * of dst. Thus, the operation succeeded without truncation if +N * and only if ret < len; otherwise, the value in ret tells you +N * how big to make dst if you decide to reallocate it. (That +N * value does _not_ include the NUL.) +N * +N * If no NUL is encountered within the first len bytes of dst, +N * then the length of dst is considered to have been equal to +N * len for the purposes of the return value (as if there were a +N * NUL at dst[len]). Thus, the return value in this case is len +N * + strlen(src). +N * +N * This is a BSD-derived library extension, which we are +N * permitted to declare in a standard header because ISO defines +N * function names beginning with 'str' as reserved for future +N * expansion of . +N */ +N +Nextern _ARMABI void _membitcpybl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpybl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpybb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpybb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpyhl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpyhl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpyhb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpyhb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpywl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpywl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitcpywb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitcpywb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovebl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovebl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovebb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovebb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovehl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovehl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovehb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovehb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovewl(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovewl(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +Nextern _ARMABI void _membitmovewb(void * /*dest*/, const void * /*src*/, int /*destoffset*/, int /*srcoffset*/, size_t /*nbits*/) __attribute__((__nonnull__(1,2))); +Xextern __declspec(__nothrow) void _membitmovewb(void * , const void * , int , int , size_t ) __attribute__((__nonnull__(1,2))); +N /* +N * Copies or moves a piece of memory from one place to another, +N * with one-bit granularity. So you can start or finish a copy +N * part way through a byte, and you can copy between regions +N * with different alignment within a byte. +N * +N * All these functions have the same prototype: two void * +N * pointers for destination and source, then two integers +N * giving the bit offset from those pointers, and finally the +N * number of bits to copy. +N * +N * Just like memcpy and memmove, the "cpy" functions copy as +N * fast as they can in the assumption that the memory regions +N * do not overlap, while the "move" functions cope correctly +N * with overlap. +N * +N * Treating memory as a stream of individual bits requires +N * defining a convention about what order those bits are +N * considered to be arranged in. The above functions support +N * multiple conventions: +N * +N * - the "bl" functions consider the unit of memory to be the +N * byte, and consider the bits within each byte to be +N * arranged in little-endian fashion, so that the LSB comes +N * first. (For example, membitcpybl(a,b,0,7,1) would copy +N * the MSB of the byte at b to the LSB of the byte at a.) +N * +N * - the "bb" functions consider the unit of memory to be the +N * byte, and consider the bits within each byte to be +N * arranged in big-endian fashion, so that the MSB comes +N * first. +N * +N * - the "hl" functions consider the unit of memory to be the +N * 16-bit halfword, and consider the bits within each word +N * to be arranged in little-endian fashion. +N * +N * - the "hb" functions consider the unit of memory to be the +N * 16-bit halfword, and consider the bits within each word +N * to be arranged in big-endian fashion. +N * +N * - the "wl" functions consider the unit of memory to be the +N * 32-bit word, and consider the bits within each word to be +N * arranged in little-endian fashion. +N * +N * - the "wb" functions consider the unit of memory to be the +N * 32-bit word, and consider the bits within each word to be +N * arranged in big-endian fashion. +N */ +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif /* __cplusplus */ +N #endif /* __STRING_DECLS */ +N +N #ifdef __cplusplus +S #ifndef __STRING_NO_EXPORTS +S using ::std::size_t; +S using ::std::memcpy; +S using ::std::memmove; +S using ::std::strcpy; +S using ::std::strncpy; +S using ::std::strcat; +S using ::std::strncat; +S using ::std::memcmp; +S using ::std::strcmp; +S using ::std::strncmp; +S using ::std::strcasecmp; +S using ::std::strncasecmp; +S using ::std::strcoll; +S using ::std::strxfrm; +S using ::std::memchr; +S using ::std::strchr; +S using ::std::strcspn; +S using ::std::strpbrk; +S using ::std::strrchr; +S using ::std::strspn; +S using ::std::strstr; +S using ::std::strtok; +S#ifndef __STRICT_ANSI__ +S using ::std::strtok_r; +S#endif +S using ::std::_strtok_r; +S using ::std::memset; +S using ::std::strerror; +S using ::std::strlen; +S using ::std::strlcpy; +S using ::std::strlcat; +S using ::std::_membitcpybl; +S using ::std::_membitcpybb; +S using ::std::_membitcpyhl; +S using ::std::_membitcpyhb; +S using ::std::_membitcpywl; +S using ::std::_membitcpywb; +S using ::std::_membitmovebl; +S using ::std::_membitmovebb; +S using ::std::_membitmovehl; +S using ::std::_membitmovehb; +S using ::std::_membitmovewl; +S using ::std::_membitmovewb; +S #endif /* __STRING_NO_EXPORTS */ +N #endif /* __cplusplus */ +N +N#endif +N +N/* end of string.h */ +N +L 19 "..\..\src\common\tau_log.h" 2 +N#include +L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.h" 1 +N/* stdarg.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.8 */ +N/* Copyright (C) Codemist Ltd., 1988 */ +N/* Copyright (C) ARM Ltd., 1991-1999. All rights reserved */ +N +N/* +N * RCS $Revision$ +N * Checkin $Date$ +N * Revising $Author: agrant $ +N */ +N +N#ifndef __stdarg_h +N#define __stdarg_h +N#define __ARMCLIB_VERSION 5060037 +N +N #ifndef __STDARG_DECLS +N #define __STDARG_DECLS +N +N #undef __CLIBNS +N +N #ifdef __cplusplus +S namespace std { +S #define __CLIBNS ::std:: +S extern "C" { +N #else +N #define __CLIBNS +N #endif /* __cplusplus */ +N +N/* +N * stdarg.h declares a type and defines macros for advancing through a +N * list of arguments whose number and types are not known to the called +N * function when it is translated. A function may be called with a variable +N * number of arguments of differing types. Its parameter list contains one or +N * more parameters. The rightmost parameter plays a special role in the access +N * mechanism, and will be called parmN in this description. +N */ +N +N/* N.B. is required to declare vfprintf() without defining */ +N/* va_list. Clearly the type __va_list there must keep in step. */ +N#ifdef __clang__ +S typedef __builtin_va_list va_list; +S #define va_start(ap, param) __builtin_va_start(ap, param) +S #define va_end(ap) __builtin_va_end(ap) +S #define va_arg(ap, type) __builtin_va_arg(ap, type) +S #if __STDC_VERSION__ >= 199900L || __cplusplus >= 201103L || !defined(__STRICT_ANSI__) +S #define va_copy(dest, src) __builtin_va_copy(dest, src) +S #endif +N#else +N #ifdef __TARGET_ARCH_AARCH64 +S typedef struct __va_list { +S void *__stack; +S void *__gr_top; +S void *__vr_top; +S int __gr_offs; +S int __vr_offs; +S } va_list; +N #else +N typedef struct __va_list { void *__ap; } va_list; +N #endif +N /* +N * an array type suitable for holding information needed by the macro va_arg +N * and the function va_end. The called function shall declare a variable +N * (referred to as ap) having type va_list. The variable ap may be passed as +N * an argument to another function. +N * Note: va_list is an array type so that when an object of that type +N * is passed as an argument it gets passed by reference. +N */ +N #define va_start(ap, parmN) __va_start(ap, parmN) +N +N /* +N * The va_start macro shall be executed before any access to the unnamed +N * arguments. The parameter ap points to an object that has type va_list. +N * The va_start macro initialises ap for subsequent use by va_arg and +N * va_end. The parameter parmN is the identifier of the rightmost parameter +N * in the variable parameter list in the function definition (the one just +N * before the '...'). If the parameter parmN is declared with the register +N * storage class an error is given. +N * If parmN is a narrow type (char, short, float) an error is given in +N * strict ANSI mode, or a warning otherwise. +N * Returns: no value. +N */ +N #define va_arg(ap, type) __va_arg(ap, type) +N +N /* +N * The va_arg macro expands to an expression that has the type and value of +N * the next argument in the call. The parameter ap shall be the same as the +N * va_list ap initialised by va_start. Each invocation of va_arg modifies +N * ap so that successive arguments are returned in turn. The parameter +N * 'type' is a type name such that the type of a pointer to an object that +N * has the specified type can be obtained simply by postfixing a * to +N * 'type'. If type is a narrow type, an error is given in strict ANSI +N * mode, or a warning otherwise. If the type is an array or function type, +N * an error is given. +N * In non-strict ANSI mode, 'type' is allowed to be any expression. +N * Returns: The first invocation of the va_arg macro after that of the +N * va_start macro returns the value of the argument after that +N * specified by parmN. Successive invocations return the values of +N * the remaining arguments in succession. +N * The result is cast to 'type', even if 'type' is narrow. +N */ +N +N#define __va_copy(dest, src) ((void)((dest) = (src))) +N +N#if !defined(__STRICT_ANSI__) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) +X#if !0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus) +N /* va_copy is in C99 and non-strict C90 and non-strict C++ +N * __va_copy is always present. +N */ +N #define va_copy(dest, src) ((void)((dest) = (src))) +N +N /* The va_copy macro makes the va_list dest be a copy of +N * the va_list src, as if the va_start macro had been applied +N * to it followed by the same sequence of uses of the va_arg +N * macro as had previously been used to reach the present state +N * of src. +N */ +N#endif +N +N#define va_end(ap) __va_end(ap) +N /* +N * The va_end macro facilitates a normal return from the function whose +N * variable argument list was referenced by the expansion of va_start that +N * initialised the va_list ap. If the va_end macro is not invoked before +N * the return, the behaviour is undefined. +N * Returns: no value. +N */ +N#endif /* __clang__ */ +N +N #ifdef __cplusplus +S } /* extern "C" */ +S } /* namespace std */ +N #endif /* __cplusplus */ +N +N #ifdef __GNUC__ +N /* be cooperative with glibc */ +N typedef __CLIBNS va_list __gnuc_va_list; +X typedef va_list __gnuc_va_list; +N #define __GNUC_VA_LIST +N #undef __need___va_list +N #endif +N +N #endif /* __STDARG_DECLS */ +N +N #ifdef __cplusplus +S #ifndef __STDARG_NO_EXPORTS +S using ::std::va_list; +S #endif +N #endif /* __cplusplus */ +N#endif +N +N/* end of stdarg.h */ +N +L 20 "..\..\src\common\tau_log.h" 2 +N#include "ArmCM0.h" +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N#ifdef LOG_TAG +S#undef LOG_TAG +N#endif +N#define LOG_TAG "tau_log" +N#define LOG_CURREN_LEVEL kLOG_LEVEL_DBG /* 配置打印等级 TODO:每个模块可配置打印等级 */ +N#define LOG_BUF_SIZE (256) /* 配置打印缓存的大小 */ +N +N/* +N * Using the following three macros for conveniently logging. +N */ +N#define TAU_LOGD(format,...) \ +N do { \ +N tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); \ +N } while (0) +X#define TAU_LOGD(format,...) do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); } while (0) +N +N#define TAU_LOGI(format,...) \ +N do { \ +N tau_log_printf(kLOG_LEVEL_INF, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); \ +N } while (0) +X#define TAU_LOGI(format,...) do { tau_log_printf(kLOG_LEVEL_INF, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); } while (0) +N +N#define TAU_LOGE(format,...) \ +N do { \ +N tau_log_printf(kLOG_LEVEL_ERR, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); \ +N } while (0) +X#define TAU_LOGE(format,...) do { tau_log_printf(kLOG_LEVEL_ERR, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); } while (0) +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/** +N* @brief log打印等级枚举 +N* +N*/ +Ntypedef enum +N{ +N kLOG_LEVEL_DBG = 0, +N kLOG_LEVEL_INF, +N kLOG_LEVEL_ERR, +N kLOG_LEVEL_NONE /* 不打印任何参数 */ +N} log_level_e; +N +N/** +N* @brief log打印端口枚举 +N* +N*/ +Ntypedef enum +N{ +N LOG_PORT_UART0, /* 使用串口输出打印 */ +N LOG_PORT_UART1, /* 使用串口输出打印 */ +N LOG_PORT_SWD, /* 使用swd输出打印 */ +N LOG_PORT_UNKNOWN +N} log_port_e; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N/** +N* @brief 初始化log系统 +N* @param baud_rate 波特率 +N* @param log_port 打印端口选择 +N* @retval none +N*/ +Nvoid tau_log_init(uint32_t baud_rate, log_port_e log_port); +N +N/** +N* @brief 初始化log系统 +N* @param baud_rate 波特率 +N* @param log_port 打印端口选择 +N* @retval none +N*/ +Nvoid tau_log_printf(log_level_e log_lv, const char *fmt, ...); +N +N#endif +L 13 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "tau_operations.h" +L 1 "..\..\src\common\tau_operations.h" 1 +N/******************************************************************************* +N* +N* +N* File: tau_operations.h +N* Description 位操作与字节操作相关定义头文件 +N* Version V0.1 +N* Date 2020-09-07 +N* Author lzy +N *******************************************************************************/ +N#ifndef __TAU_BYTEOPS_H +N#define __TAU_BYTEOPS_H +N +N/** +N * \name 通用位常数定义 +N * @{ +N */ +N +N/** \brief 长整数位数 */ +N#ifndef TAU_BITS_PER_LONG +N#define TAU_BITS_PER_LONG 32 +N#endif +N +N/** \brief 字节位数 */ +N#define TAU_BITS_PER_BYTE 8 +N +N/** @} */ +N +N +N/******************************************************************************/ +N +N/** +N * \name 通用位操作 +N * @{ +N */ +N +N/** \brief bit移位 +N * TAU_BIT(2) is 0x4 +N */ +N#define TAU_BIT(bit) (1u << (bit)) +N +N/** \brief 值移位 +N * TAU_SBF(0xFF, 8) is 0xff00 +N */ +N#define TAU_SBF(value, field) ((value) << (field)) +N +N/** \brief bit置位 +N * TAU_BIT_SET(0, 8) is 0x100 +N */ +N#define TAU_BIT_SET(data, bit) ((data) |= TAU_BIT(bit)) +N +N/** \brief bit清零 +N * TAU_BIT_CLR(0xFF, 2) is 0xfb +N */ +N#define TAU_BIT_CLR(data, bit) ((data) &= ~TAU_BIT(bit)) +N +N/** \brief bit置位, 根据 mask 指定的位 +N * TAU_BIT_SET_MASK(0xF0F0, 0xF00) is 0xfff0 +N */ +N#define TAU_BIT_SET_MASK(data, mask) ((data) |= (mask)) +N +N/** \brief bit清零, 根据 mask 指定的位 +N * TAU_BIT_CLR_MASK(0xFFFF, 0xFF00) is 0xff +N */ +N#define TAU_BIT_CLR_MASK(data, mask) ((data) &= ~(mask)) +N +N/** \brief bit翻转 +N * TAU_BIT_TOGGLE(0xFFFF, 0) is 0xfffe +N * TAU_BIT_TOGGLE(0x0000, 1) is 0x2 +N */ +N#define TAU_BIT_TOGGLE(data, bit) ((data) ^= TAU_BIT(bit)) +N +N/** \brief bit修改 +N * TAU_BIT_MODIFY(0, 8, 1) is 0x100 +N * TAU_BIT_MODIFY(0xFFFF, 1, 0) is 0xfffd +N */ +N#define TAU_BIT_MODIFY(data, bit, value) \ +N ((value) ? TAU_BIT_SET(data, bit) : TAU_BIT_CLR(data, bit)) +X#define TAU_BIT_MODIFY(data, bit, value) ((value) ? TAU_BIT_SET(data, bit) : TAU_BIT_CLR(data, bit)) +N +N/** \brief 测试bit是否置位 +N * TAU_BIT_ISSET(0xF0F1, 1) is 0 +N * TAU_BIT_ISSET(0xF0F2, 1) is 2 +N */ +N#define TAU_BIT_ISSET(data, bit) ((data) & TAU_BIT(bit)) +N +N/** \brief 获取bit值 +N * TAU_BIT_GET(0xF0F1, 1) is 0 +N * TAU_BIT_GET(0xF0F2, 1) is 1 +N */ +N#define TAU_BIT_GET(data, bit) (TAU_BIT_ISSET(data, bit) ? 1 : 0) +N +N/** \brief 检测bit值 +N * TAU_BIT_CHECK(0xF5FF, 4) is 1 +N */ +N#define TAU_BIT_CHECK(data, bit) \ +N (((data) & TAU_BIT(bit)) ? 1 : 0) +X#define TAU_BIT_CHECK(data, bit) (((data) & TAU_BIT(bit)) ? 1 : 0) +N +N/** \brief 获取 n bits 掩码值 +N * TAU_BITS_MASK(2) is 0x3 +N */ +N#define TAU_BITS_MASK(n) (~((~0u) << (n))) +N +N/** \brief 获取位段值 +N * TAU_BITS_GET(0xF5FF, 0x0F00, 8) is 0x5 +N */ +N#define TAU_BITS_GET(data, mask, pos) \ +N (((data) & (mask)) >> (pos)) +X#define TAU_BITS_GET(data, mask, pos) (((data) & (mask)) >> (pos)) +N +N/** \brief 获取位段值 +N * TAU_BITS_CHECK(0xF5FF, 0x0F00) is 1 +N */ +N#define TAU_BITS_CHECK(data, mask) \ +N (((data) & (mask)) ? 1 : 0) +X#define TAU_BITS_CHECK(data, mask) (((data) & (mask)) ? 1 : 0) +N +N/** \brief 修改位段值 +N * TAU_BITS_MODIFY(0xF5FF, 0x0FF0, 0x8A0) is 0xF8AF +N*/ +N#define TAU_BITS_MODIFY(data, clear_mask, set_mask) \ +N (data) = (((data) & (~(clear_mask))) | (set_mask)) +X#define TAU_BITS_MODIFY(data, clear_mask, set_mask) (data) = (((data) & (~(clear_mask))) | (set_mask)) +N +N/** \brief 设置位段值 +N * TAU_WRITE_REG32(0x05FF, 0xFFFA) is 0xFFFA +N*/ +N#define TAU_WRITE_REG32(data, value) ((data) = (value)) +N +N/** \brief 设置位段值 +N * TAU_RAED_REG32(0x05FF) is 0x05FF +N*/ +N#define TAU_RAED_REG32(data) (data) +N +N +N/** @} */ +N +N/******************************************************************************/ +N +N/** +N * \brief 取2-byte整数的高位byte +N * +N * \par 示例 +N * \code +N * uint16_t a = 0x1234; +N * uint16_t b; +N * +N * b = TAU_MSB(a); //b=0x12 +N * \endcode +N */ +N#define TAU_MSB(x) (((x) >> 8) & 0xff) +N +N/** +N * \brief 取2-byte整数的低位byte +N * +N * \par 示例 +N * \code +N * uint16_t a = 0x1234; +N * uint16_t b; +N * +N * b = TAU_LSB(a); //b=0x34 +N * \endcode +N */ +N#define TAU_LSB(x) ((x) & 0xff) +N +N/** +N * \brief 取2-word整数的高位word +N * +N * \par 示例 +N * \code +N * uint32_t a = 0x12345678; +N * uint32_t b; +N * +N * b = TAU_MSW(a); //b=0x1234 +N * \endcode +N */ +N#define TAU_MSW(x) (((x) >> 16) & 0xffff) +N +N/** +N * \brief 取2-word整数的低位word +N * +N * \par 示例 +N * \code +N * uint32_t a = 0x12345678; +N * uint32_t b; +N * +N * b = TAU_LSW(a); //b=0x5678 +N * \endcode +N */ +N#define TAU_LSW(x) ((x) & 0xffff) +N +N/** +N * \brief 交换32-bit整数的高位word和低位word +N * +N * \par 示例 +N * \code +N * uint32_t a = 0x12345678; +N * uint32_t b; +N * +N * b = TAU_WORDSWAP(a); //b=0x56781234 +N * \endcode +N */ +N#define TAU_WORDSWAP(x) (TAU_MSW(x) | (TAU_LSW(x) << 16)) +N +N/** +N * \brief 交换32-bit整数的字节顺序 +N * +N * \par 示例 +N * \code +N * uint32_t a = 0x12345678; +N * uint32_t b; +N * +N * b = TAU_LONGSWAP(a); //b=0x78563412 +N * \endcode +N */ +N#define TAU_LONGSWAP(x) ((TAU_LLSB(x) << 24) | \ +N (TAU_LNLSB(x) << 16) | \ +N (TAU_LNMSB(x) << 8) | \ +N (TAU_LMSB(x))) +X#define TAU_LONGSWAP(x) ((TAU_LLSB(x) << 24) | (TAU_LNLSB(x) << 16) | (TAU_LNMSB(x) << 8) | (TAU_LMSB(x))) +N +N#define TAU_LLSB(x) ((x) & 0xff) /**< \brief 取32bit整数第1个字节 */ +N#define TAU_LNLSB(x) (((x) >> 8) & 0xff) /**< \brief 取32bit整数第2个字节 */ +N#define TAU_LNMSB(x) (((x) >> 16) & 0xff) /**< \brief 取32bit整数第3个字节 */ +N#define TAU_LMSB(x) (((x) >> 24) & 0xff) /**< \brief 取32bit整数第4个字节 */ +N#define TAU_LNSB(x,n) (((x) >> ((n) * 8) ) & 0xff) /**< \brief 取32bit整数第n个字节 ,参数 0 - 3*/ +N +N/** +N * @} +N */ +N +N#endif /* __TAU_BYTEOPS_H */ +N +N/* end of file */ +N +L 14 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "tau_common.h" +N#include "tau_delay.h" +L 1 "..\..\src\common\tau_delay.h" 1 +N/** +N * File Name: tau_delay.h +N * +N * +N * +N * Author: Fortsense 3D Firmware Team +N * +N * Date: 2020/12/04 +N * +N * Project: Taurus +N * +N * Description: +N * +N * HISTORY: +N**/ +N#ifndef _DELAY_H_ +N#define _DELAY_H_ +N#include "stdint.h" +N +N/** +N* @brief delay ms 函数,误差2%以内 +N* @param ms:delay时长 +N* @retval none +N*/ +Nvoid delayMs(uint32_t ms); +N +N/** +N* @brief delay us 函数,误差2%以内 +N* @param us:delay时长 +N* @retval none +N*/ +Nvoid delayUs(uint32_t us); +N +N#endif +L 16 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "hal_dsi_rx_ctrl.h" +L 1 "..\..\src\sdk\include\hal_dsi_rx_ctrl.h" 1 +N/******************************************************************************* +N* +N* +N* File: hal_dsi_rx_ctrl.h +N* Description: hal mipi dsi rx path control 头文件 +N* Version: V0.1 +N* Date: 2021-04-06 +N* Author: lzy +N *******************************************************************************/ +N#ifndef __HAL_DSI_RX_CTRL_H__ +N#define __HAL_DSI_RX_CTRL_H__ +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_dsi_datatype.h" +L 1 "..\..\src\common\tau_dsi_datatype.h" 1 +N/******************************************************************************* +N* +N* +N* File: tau_dsi_datatype.h +N* Description: mipi dsi 通用头文件 +N* Version: V0.1 +N* Date: 2021-01-13 +N* Author: lzy +N *******************************************************************************/ +N +N#ifndef __MIPI_DSI_COMMON_H__ +N#define __MIPI_DSI_COMMON_H__ +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_common.h" +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N#define DSC_PPS_SIZE 128 +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/** +N* @brief Data Types for Peripheral-sourced Packets,From Mipi DSI Spec +N*/ +Ntypedef enum +N{ +N DSI_ACK_DT_ERROR = 0x02, +N DSI_ACK_DT_EOTP = 0x08, +N DSI_ACK_DT_GEN_SHORT_RESPONSE_1B = 0x11, +N DSI_ACK_DT_GEN_SHORT_RESPONSE_2B = 0x12, +N DSI_ACK_DT_GEN_LONG_RESPONSE = 0x1A, +N DSI_ACK_DT_DCS_LONG_RESPONSE = 0x1C, +N DSI_ACK_DT_DCS_SHORT_RESPONSE_1B = 0x21, +N DSI_ACK_DT_DCS_SHORT_RESPONSE_2B = 0x22, +N DSI_ACK_DT_MAX +N} dsi_ack_data_type_e; +N +N/** +N* @brief Software handle data types +N*/ +Ntypedef enum +N{ +N DSI_RECV_DT_PPS = 0x0A, //Picture Parameter Set +N DSI_RECV_DT_GEN_WRITE_1B = 0x13, //Generic Short WRITE, 1 parameter +N DSI_RECV_DT_GEN_WRITE_2B = 0x23, //Generic Short WRITE, 2 parameters +N DSI_RECV_DT_GEN_READ_0B = 0x04, //Generic READ, no parameters +N DSI_RECV_DT_GEN_READ_1B = 0x14, //Generic READ, 1 parameter +N DSI_RECV_DT_GEN_READ_2B = 0x24, //Generic READ, 2 parameters +N DSI_RECV_DT_DCS_WRITE_0B = 0x05, //DCS Short WRITE, no parameters +N DSI_RECV_DT_DCS_WRITE_1B = 0x15, //DCS Short WRITE, 1 parameter +N DSI_RECV_DT_DCS_READ_0B = 0x06, //DCS READ, no parameters +N DSI_RECV_DT_GEN_WRITE_LONG = 0x29, //Generic Long Write +N DSI_RECV_DT_DCS_WRITE_LONG = 0x39, //DCS Long Write/write_LUT Command Packet +N DSI_RECV_DT_MAX +N} dsi_data_type_e; +N +Ntypedef enum +N{ +N DCS_ENTER_IDLE_MODE = 0x39, +N DCS_ENTER_INVERT_MODE = 0x21, +N DCS_ENTER_NORMAL_MODE = 0x13, +N DCS_ENTER_PARTIAL_MODE = 0x12, +N DCS_ENTER_SLEEP_MODE = 0x10, +N DCS_EXIT_IDLE_MODE = 0x38, +N DCS_EXIT_INVERT_MODE = 0x20, +N DCS_EXIT_SLEEP_MODE = 0x11, +N DCS_GET_3D_CONTROL = 0x3F, +N DCS_GET_ADDRESS_MODE = 0x0B, +N DCS_GET_BLUE_CHANNEL = 0x08, +N DCS_GET_COMPRESSION_MODE = 0x03, +N DCS_GET_DIAGNOSTIC_RESULT = 0x0F, +N DCS_GET_DISPLAY_MODE = 0x0D, +N DCS_GET_GREEN_CHANNEL = 0x07, +N DCS_GET_PIXEL_FORMAT = 0x0C, +N DCS_GET_POWER_MODE = 0x0A, +N DCS_GET_RED_CHANNEL = 0x06, +N DCS_GET_SCANLINE = 0x45, +N DCS_GET_SIGNAL_MODE = 0x0E, +N DCS_NOP = 0x00, +N DCS_READ_DDB_CONTINUE = 0xA8, +N DCS_READ_DDB_START = 0xA1, +N DCS_READ_MEMORY_CONTINUE = 0x3E, +N DCS_READ_MEMORY_START = 0x2E, +N DCS_SET_3D_CONTROL = 0x3D, +N DCS_SET_ADDRESS_MODE = 0x36, +N DCS_SET_COLUMN_ADDRESS = 0x2A, +N DCS_SET_DISPLAY_OFF = 0x28, +N DCS_SET_DISPLAY_ON = 0x29, +N DCS_SET_GAMMA_CURVE = 0x26, +N DCS_SET_PAGE_ADDRESS = 0x2B, +N DCS_SET_PARTIAL_COLUMNS = 0x31, +N DCS_SET_PARTIAL_ROWS = 0x30, +N DCS_SET_PIXEL_FORMAT = 0x3A, +N DCS_SET_SCROLL_AREA = 0x33, +N DCS_SET_SCROLL_START = 0x37, +N DCS_SET_TEAR_OFF = 0x34, +N DCS_SET_TEAR_ON = 0x35, +N DCS_SET_TEAR_SCANLINE = 0x44, +N DCS_SET_VSYNC_TIMING = 0x40, +N DCS_SOFT_RESET = 0x01, +N DCS_WRITE_LUT = 0x2D, +N DCS_WRITE_MEMORY_CONTINUE = 0x3C, +N DCS_WRITE_MEMORY_START = 0x2C +N} dsi_dcs_cmd_type_e; +N +N/** +N* @brief video data transfer mode +N*/ +Ntypedef enum +N{ +N DSI_DATA_VIDEO_MODE = 0, +N DSI_DATA_CMD_MODE = 1, +N DSI_DATA_MODE_MAX +N} dsi_video_data_mode_e; +N +N/** +N* @brief dsi virtual channel +N*/ +Ntypedef enum +N{ +N DSI_VC_0 = 0, +N DSI_VC_1 = 1, +N DSI_VC_2 = 2, +N DSI_VC_3 = 3, +N DSI_VC_MAX +N} dsi_virtual_channel_e; +N +N/** +N* @brief video data mode +N*/ +Ntypedef enum +N{ +N DSI_FRAME_RATE_60HZ = 0, +N DSI_FRAME_RATE_90HZ = 1, +N DSI_FRAME_RATE_120HZ = 2, +N DSI_FRAME_RATE_144HZ = 3, +N DSI_FRAME_RATE_160HZ = 4, +N DSI_FRAME_RATE_MAX +N} dsi_video_frame_rate_e; +N +N/** +N* @brief dsi rx color coding +N*/ +Ntypedef enum +N{ +N DSI_RGB565 = 1, +N DSI_RGB666 = 2, /*!< 18 bbp(18bits per pixel) */ +N DSI_RGB666_LOOSELY = 3, /*!< 24 bbp(24bits per pixel) */ +N DSI_RGB888 = 4, /*!< 24 bbp(24bits per pixel) */ +N DSI_RGB10_10_10 = 5, +N DSI_RGB12_12_12 = 6, +N DSI_YCbCr422_16 = 7, +N DSI_PENTILE_16 = DSI_YCbCr422_16, +N DSI_YCbCr422_20_LOOSELY = 8, +N DSI_YCbCr422_24 = 9, +N DSI_YCbCr420_12 = 10, +N DSI_DSC_STREAM = 11, +N DSI_COLOR_CODE_MAX +N} dsi_color_code_e; +N +N/** +N* @brief dsi endianness type +N*/ +Ntypedef enum +N{ +N DPI_ENDIAN_RGB = 0, +N DPI_ENDIAN_BGR +N} dsi_endianness_e; +N +N/** +N* @brief mipi lane number +N*/ +Ntypedef enum +N{ +N DSI_LANE_1 = 1, +N DSI_LANE_2 = 2, +N DSI_LANE_3 = 3, +N DSI_LANE_4 = 4, +N DSI_LANE_NUME_MAX +N} dsi_lane_nume_e; +N +N/** +N* @brief video mode +N*/ +Ntypedef enum +N{ +N DSI_NONBURST_PULSE = 0, +N DSI_NONBURST_EVENT = 1, +N DSI_BURST_MODE = 2, +N DSI_VIDEO_MODE_MAX +N} dsi_video_mode_type_e; +N +N/** +N* @brief panel init cmd transfer type +N*/ +Ntypedef enum +N{ +N DSI_CMD_TX_HS = 0, +N DSI_CMD_TX_LP = 1 +N} dsi_tx_cmd_tx_type_e; +N +N/** +N* @brief angle of rotation +N*/ +Ntypedef enum +N{ +N VIDOE_ROT_ANGLE_0 = 0, /* 不旋转 */ +N VIDOE_ROT_ANGLE_90 = 1, /* 旋转90度 */ +N VIDOE_ROT_ANGLE_180 = 2, /* 旋转180度 */ +N VIDOE_ROT_ANGLE_270 = 3, /* 转转270度 */ +N VIDOE_ROT_ANGLE_MAX +N} video_rotate_angle_e; +N +N/** +N* @brief mipi rx lane swap +N软件配置 PIN28&PIN27 PIN26&PIN25 PIN24&PIN23 PIN22&PIN21 PIN20&PIN19 +NRX_LANE_SWAP_0123 D0P&D0N D1P&D1N CLKP&CLKN D2P&D2N D3P&D3N +NRX_LANE_SWAP_3210 D3P&D3N D2P&D2N CLKP&CLKN D1P&D1N D0P&D0N +NRX_LANE_SWAP_2103(default) D2P&D2N D1P&D1N CLKP&CLKN D0P&D0N D3P&D3N +NRX_LANE_SWAP_3012 D3P&D3N D0P&D0N CLKP&CLKN D1P&D1N D2P&D2N +N*/ +Ntypedef enum +N{ +N RX_LANE_SWAP_0123 = 0x0, +N RX_LANE_SWAP_3210 = 0x1, +N RX_LANE_SWAP_2103 = 0x2, +N RX_LANE_SWAP_DEFAULT_ORDER = 0x2, /* 默认原理图为2103顺序 */ +N RX_LANE_SWAP_3012 = 0x3, +N RX_LANE_SWAP_MAX +N} dsi_rx_lane_swap_e; +N +N/** +N* @brief mipi P/N lane swap flag +N* eg: pn_swap = RX_LANE_0_PN_SWAP | RX_LANE_CLK_PN_SWAP; +N* 表示 lane0 与 CLK 的P跟N交换，其他lane不变。 +N* 注意这里的lane表示的是进行完lane swap的lane,如lane swap配置RX_LANE_SWAP_3012,再配置RX_LANE_0_PN_SWAP则表示PIN26&PIN25进行PN交换,由D0P&D0N变成D0N&D0P +N*/ +Ntypedef enum +N{ +N RX_LANE_0_PN_SWAP = 0x1, +N RX_LANE_1_PN_SWAP = 0x2, +N RX_LANE_2_PN_SWAP = 0x4, +N RX_LANE_3_PN_SWAP = 0x8, +N RX_LANE_CLK_PN_SWAP = 0x10 +N} dsi_rx_lane_pn_swap_e; +N +N/** +N* @brief error processing level +N*/ +Ntypedef enum +N{ +N ERR_HANDLE_NONE = 0, +N ERR_HANDLE_L1 = 1, +N ERR_HANDLE_L2 = 2, +N ERR_HANDLE_L3 = 3, +N ERR_HANDLE_MAX +N} hal_err_handle_level_e; +N +N/** +N* @brief flow control mode +N*/ +Ntypedef enum +N{ +N FC_AUTO_MODE = 0, /* 自动匹配模式,根据base info配置匹配1-4 */ +N FC_V2V_NORMAL_MODE = 1, /* Video to Video 模式转换 */ +N FC_V2C_NORMAL_MODE = 2, /* Video to Command 模式转换 */ +N FC_C2V_NORMAL_MODE = 3, /* Command to Video 模式转换 */ +N FC_C2C_NORMAL_MODE = 4, /* Command to Command 模式转换 */ +N FC_PRO_MOTION_MODE = 6, /* 自适应帧率转换(LTPO模式) */ +N FC_PRO_MOTION_MODE_2 = 5, /* 自适应帧率转换(LTPO模式) */ +N FC_PRO_MOTION_WITH_PU_MODE = 7, /* 自适应帧率带PU */ +N FC_V2V_AUTO_SYCN_MODE = 8, /* Video to Video 软件同步 */ +N FC_V2V_DIRECT_MODE = 9, /* Video to Video 直通模式 */ +N FC_MODE_MAX +N} flow_control_mode_e; +N +N/** +N* @brief transform 基本信息 +N*/ +Ntypedef struct +N{ +N uint16_t top; +N uint16_t bottom; +N uint16_t left; +N uint16_t right; +N bool enable; +X _Bool enable; +N} pic_edge_info_t; +N +N/** +N* @brief transform 基本信息 +N*/ +Ntypedef struct +N{ +N uint32_t src_w; /* mipi rx 接收的 width */ +N uint32_t src_h; /* mipi rx 接收的 height */ +N uint32_t dst_w; /* mipi tx 发送的 width */ +N uint32_t dst_h; /* mipi tx 发送的 height */ +N dsi_video_frame_rate_e src_frate; /* mipi rx 接收的frame rate */ +N dsi_video_data_mode_e src_mode; /* mipi rx 接收video 数据传输模式(video/cmd mode) */ +N dsi_video_data_mode_e dst_mode; /* mipi tx 输出video 数据传输模式(video/cmd mode) */ +N uint16_t pn_swap; /* mipi P/N swap标志位, rx可配置/tx暂不支持 */ +N} dsi_base_trans_info_t; +N +N/** +N* @brief transform 基本信息 +N*/ +Ntypedef struct +N{ +N bool mirror_en; /* 对video 做水平镜像标志位 */ +X _Bool mirror_en; +N bool pu_optimize; /* 用于优化PU显示效果，默认为false;true:优化PU显示显示效果,高功耗;false:普通PU模式,低功耗 */ +X _Bool pu_optimize; +N video_rotate_angle_e rot_angle; /* 对video 做旋转的角度 */ +N flow_control_mode_e flow_control_mode; /* 图像数据流控制模式 */ +N pic_edge_info_t crop_info; /* 图像边缘裁剪配置 not impletmented */ +N pic_edge_info_t blank_info; /* 图像边缘补黑配置 not impletmented */ +N bool bw_optimize; /* 带宽自动检查,默认打开 */ +X _Bool bw_optimize; +N uint8_t pq_type; /* picture quality,参数为 pq_type_e */ +N} dsi_base_extra_info_t; +N +N/** +N* @brief ccm系数 +N*/ +Ntypedef struct +N{ +N uint32_t coef_c00; +N uint32_t coef_c01; +N uint32_t coef_c02; +N uint32_t coef_c10; +N uint32_t coef_c11; +N uint32_t coef_c12; +N uint32_t coef_c20; +N uint32_t coef_c21; +N uint32_t coef_c22; +N} ccm_coef_t; +N +N/** +N* @brief hight performan mode level +N*/ +Ntypedef enum +N{ +N HIGHT_PERFORMAN_NONE = 0, +N HIGHT_PERFORMAN_L1 = 1, +N HIGHT_PERFORMAN_L2 = 2, +N HIGHT_PERFORMAN_MAX +N} hight_performan_mode_e; +N +N/** +N* @brief TX False color去伪彩参数结构体 +N*/ +Ntypedef struct +N{ +N uint16_t edgemedslope; +N uint16_t desatslope; +N} dsi_tx_fc_t; +N +N/** +N* @brief TX 边缘增强参数结构体 +N*/ +Ntypedef struct +N{ +N bool y_enh_method; +X _Bool y_enh_method; +N uint8_t enhance_str; +N uint16_t enhance_slope; +N uint16_t boundscale_low; +N uint16_t boundscale_high; +N} dsi_tx_edge_enh_t; +N +N/** +N* @brief TX 边缘检测参数结构体 +N*/ +Ntypedef struct +N{ +N uint8_t edge_thr; +N bool use_large_kernel; +X _Bool use_large_kernel; +N} dsi_tx_edge_dect_t; +N +N/** +N* @brief TX bcsa 参数结构体 +N*/ +Ntypedef struct +N{ +N int8_t brightness; /* 亮度调整, 范围-127 - 127 */ +N uint16_t contrast; /* 对比度调整,范围0 - 4095 */ +N uint16_t saturation; /* 饱和度调整,范围0 - 4095 */ +N} dsi_tx_bcs_t; +N +N/** +N* @brief partial display 参数结构体 +N*/ +Ntypedef struct +N{ +N uint32_t st_line; /*部分显示起始行位置*/ +N uint32_t st_col; /*部分显示起始列位置*/ +N uint32_t end_line; /*部分显示结束行位置*/ +N uint32_t end_col; /*部分显示结束列位置*/ +N uint8_t value_r; /*部分显示背景色R值*/ +N uint8_t value_g; /*部分显示背景色G值*/ +N uint8_t value_b; /*部分显示背景色B值*/ +N} dsi_tx_par_dis_t; +N +N#endif //__MIPI_DSI_COMMON_H__ +L 17 "..\..\src\sdk\include\hal_dsi_rx_ctrl.h" 2 +N#include "tau_common.h" +N#include "tau_log.h" +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N#define RX_DCS_QUEUE_MAX_SIZE 20 /* DCS存储队列长度 */ +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +Ntypedef struct hal_dcs_execute_entry_t hal_dcs_execute_entry_t; +N +Ntypedef struct hal_dcs_packet_t hal_dcs_packet_t; +N +Ntypedef struct hal_dsi_rx_ctrl_handle_t hal_dsi_rx_ctrl_handle_t; +N +N/* DCS CMD 回调函数, 注册进cus_dcs_entry_table里, 匹配对应的DCS 后回调*/ +Ntypedef bool (*hal_dsi_rx_ctrl_dcs_execute)(hal_dsi_rx_ctrl_handle_t *rx_handle, hal_dcs_packet_t *dcs_packet); +Xtypedef _Bool (*hal_dsi_rx_ctrl_dcs_execute)(hal_dsi_rx_ctrl_handle_t *rx_handle, hal_dcs_packet_t *dcs_packet); +N +N/* AP 读cmd 回调, 需要快速回CMD 时可注册, 为NULL 时DSC 读指令与写指令经过parse后由cus_dcs_entry_table回调 */ +Ntypedef bool (*hal_dsi_rx_ctrl_read_entry)(uint8_t data_type, uint8_t dcs_cmd, uint8_t param); +Xtypedef _Bool (*hal_dsi_rx_ctrl_read_entry)(uint8_t data_type, uint8_t dcs_cmd, uint8_t param); +N +N/* AP PPS 更新回调,参数为PPS 以及从PPS 里解析出来的picture width/height, 用于分辨率切换, 不注册该接口时内部处理PPS */ +Ntypedef bool (*hal_dsi_rx_ctrl_pps_entry)(uint8_t *pps, uint8_t size, uint32_t pic_width, uint32_t pic_height); +Xtypedef _Bool (*hal_dsi_rx_ctrl_pps_entry)(uint8_t *pps, uint8_t size, uint32_t pic_width, uint32_t pic_height); +N +N/** +N* @brief hal_rx_event_e select +N*/ +Ntypedef enum hal_rx_event_e +N{ +N HAL_RX_FS_EVENT = 0x1, /* Frame start event */ +N HAL_RX_LINE_EVENT = 0x2, /* Frame receive line event */ +N HAL_RX_END_EVENT = 0x4, /* Frame end event */ +N} hal_rx_event_e; +N +N/** +N* @brief rx pq filter index +N* 默认使用linear,特殊场景使用OPT filter +N* RX_FLT_OPT_0最模糊,边缘最平滑,index越大越清晰,边缘锯齿会加重 +N*/ +Ntypedef enum +N{ +N RX_FLT_OPT_0 = 0, +N RX_FLT_OPT_1 = 1, +N RX_FLT_OPT_2 = 2, +N RX_FLT_OPT_3 = 3, +N RX_FLT_OPT_4 = 4, +N RX_FLT_OPT_5 = 5, +N RX_FLT_OPT_6 = 6, +N RX_FLT_OPT_7 = 7, +N RX_FLT_OPT_8 = 8, +N RX_FLT_OPT_9 = 9, +N RX_FLT_OPT_10 = 10, +N RX_FLT_LINEAR = 11, +N RX_FLT_MAX +N} hal_dsi_rx_pq_filter_e; +N +N/* RX debug 回调函数,用于获取frame start 等功能debug */ +Ntypedef void (*hal_dsi_rx_ctrl_event_entry)(hal_rx_event_e event, void *data); +N +N/** +N* @brief dsi rx ctrl handle struct +N*/ +Ntypedef struct hal_dsi_rx_ctrl_handle_t +N{ +N dsi_base_trans_info_t base_info; /* mipi video 转换基本信息 */ +N dsi_base_extra_info_t extra_info; /* 新增旋转、镜像配置 */ +N dsi_color_code_e rx_color_mode; /* 输入color mode */ +N dsi_lane_nume_e rx_lanes; /* mipi data lane */ +N dsi_video_mode_type_e rx_nonburst_models; /* transmission packet sequences */ +N bool compress_en; /* DSC 压缩标志 */ +X _Bool compress_en; +N uint32_t rx_hsclk_rate; /* mipi 高速信号lane rate */ +N uint8_t rx_dsc_pps[DSC_PPS_SIZE]; /* DSC 压缩PPS参数 */ +X uint8_t rx_dsc_pps[128]; +N const hal_dcs_execute_entry_t *cus_dcs_entry_table; /* DCS处理函数列表 */ +N hal_dsi_rx_ctrl_read_entry rx_dcs_read_entry; /* Host读指令数据函数,为NULL时由rx_dcs_queue注册cmd处理 */ +N hal_dsi_rx_ctrl_pps_entry pps_update_entry; /* PPS Update 时回调函数,用于分辨率切换更新PPS,为NULL时内部处理 */ +N bool used; /* handle使用标志位 */ +X _Bool used; +N hal_err_handle_level_e err_handler_level; /* RX接收错误的时候对模块做reset等级, 等级越高reset模块越多 */ +N uint8_t rx_strength; /* 用于调节RX信号强度，仅适用于开启内阻校准模式，档位0~7，默认3 */ +N hight_performan_mode_e hight_performan_mode; /* 高性能模式等级,参考hight_performan_mode_e */ +N dsi_rx_lane_swap_e rx_lane_swap; /* lane swap default order is 2103*/ +N hal_dsi_rx_pq_filter_e rx_pq_index; /* 画质调整滤波器,默认为linear最优效果,特殊场景使用OPT filter */ +N} hal_dsi_rx_ctrl_handle_t; +N +N/** +N* @brief DCS command execute entry +N*/ +Ntypedef struct hal_dcs_execute_entry_t +N{ +N uint32_t dcs_command; /* DCS command */ +N hal_dsi_rx_ctrl_dcs_execute execute_func; /* command 对应处理函数 */ +N bool immediately_func; /* 执行机制:true-在中断里立即执行,false-加入DCS队列异步执行 */ +X _Bool immediately_func; +N} hal_dcs_execute_entry_t; +N +N/** +N* @brief 存储 DCS packet 结构体 +N*/ +Ntypedef struct hal_dcs_packet_t +N{ +N uint32_t data_type; /* data type */ +N uint32_t dcs_command; /* dcs command */ +N uint32_t param_length; /* dcs param length */ +N uint8_t *packet_param; /* dcs param */ +N uint16_t crc_data; /* dcs crc */ +N const hal_dcs_execute_entry_t *dcs_execute_entry; /* dcs packet 处理函数入口*/ +N} hal_dcs_packet_t; +N +N/** +N* @brief video mode 下 RX pattern参数结构体 +N*/ +Ntypedef struct +N{ +N uint32_t ipi_pg_hsa; +N uint32_t ipi_pg_hbp; +N uint32_t ipi_pg_hfp; +N uint32_t ipi_pg_vsa; +N uint32_t ipi_pg_vbp; +N uint32_t ipi_pg_vfp; +N uint32_t frame_rate; +N} hal_dsi_rx_ipi_pg_t; +N +N +N/** +N* @brief dcs command filter select +N*/ +Ntypedef enum +N{ +N HAL_RX_DCS_FILTER_0 = 0x0, +N HAL_RX_DCS_FILTER_1 = 0x1, +N HAL_RX_DCS_FILTER_2 = 0x2, +N HAL_RX_DCS_FILTER_3 = 0x3, +N HAL_RX_DCS_FILTER_4 = 0x4, +N HAL_RX_DCS_FILTER_5 = 0x5, +N HAL_RX_DCS_FILTER_6 = 0x6, +N HAL_RX_DCS_FILTER_7 = 0x7, +N HAL_RX_DCS_FILTER_8 = 0x8, +N HAL_RX_DCS_FILTER_9 = 0x9, +N HAL_RX_DCS_FILTER_A = 0xA, +N HAL_RX_DCS_FILTER_B = 0xB, +N HAL_RX_DCS_FILTER_MAX +N} hal_rx_dcs_filter_sel_e; +N +N +N/** +N* @brief dcs command filter select +N*/ +Ntypedef enum +N{ +N HAL_RX_QRESP_CODE0 = 0, +N HAL_RX_QRESP_CODE1 = 1, +N HAL_RX_QRESP_CODE2 = 2, +N HAL_RX_QRESP_CODE3 = 3, +N HAL_RX_QRESP_CODE4 = 4, +N HAL_RX_QRESP_CODE5 = 5, +N HAL_RX_QRESP_CODE6 = 6, +N HAL_RX_QRESP_CODE7 = 7, +N HAL_RX_QRESP_MAX +N} hal_rx_dcs_qresp_e; +N +N/** +N* @brief pentile source color format +N*/ +Ntypedef enum +N{ +N PENTILE_SRC_FORMAT_RGB = 0x0, +N PENTILE_SRC_FORMAT_BGR = 0x1, +N PENTILE_SRC_FORMAT_RGBG_BGRG = 0x8, +N PENTILE_SRC_FORMAT_GBGR_GRGB = 0x9, +N PENTILE_SRC_FORMAT_BGRG_RGBG = 0xA, +N PENTILE_SRC_FORMAT_GRGB_GBGR = 0xB, +N PENTILE_SRC_FORMAT_RGBG_RGBG = 0xC, +N PENTILE_SRC_FORMAT_GBGR_GBGR = 0xD, +N PENTILE_SRC_FORMAT_BGRG_BGRG = 0xE, +N PENTILE_SRC_FORMAT_GRGB_GRGB = 0xF, +N PENTILE_SRC_FORMAT_MAX +N} pentile_src_format_e; +N +N/** +N* @brief 设置RX CLK +N*/ +Ntypedef enum +N{ +N RX_CLK_100M = 0, +N RX_CLK_150M = 1, +N RX_CLK_200M = 2, +N RX_CLK_300M = 3, +N RX_CLK_40M = 4, +N RX_CLK_80M = 5, +N RX_CLK_MAX +N} hal_rx_clk_e; +N +N/** +N* @brief pq_type_e select +N*/ +Ntypedef enum +N{ +N PQ_TYPE_DEFAULT = 0x0, +N PQ_TYPE_LIMIT = 0x1, +N PQ_TYPE_MAX +N} pq_type_e; +N +N/** +N* @brief 线的粗细 +N*/ +Ntypedef enum +N{ +N LINE_WEIGHT_FINE = 0, +N LINE_WEIGHT_MEDIUM = 1, +N LINE_WEIGHT_BOLD = 2, +N LINE_WEIGHT_MAX +N} line_weight_e; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N +N/** +N* @brief 创建dsi rx ctrl handle (释放时需调用hal_dsi_rx_ctrl_release_handle) +N* @param none +N* @retval dsi rx handle +N*/ +Nhal_dsi_rx_ctrl_handle_t *hal_dsi_rx_ctrl_create_handle(void); +N +N/** +N* @brief 释放dsi rx ctrl handle +N* @param rx_ctrl_handle: dsi rx handle +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_release_handle(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +X_Bool hal_dsi_rx_ctrl_release_handle(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +N +N/** +N* @brief 设置rx ctrl handle 里的 PPS 参数 +N* @param rx_ctrl_handle: dsi rx handle +N* @param pps: pps 参数 +N* @param pps_size: pps 参数长度 +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_pre_init_pps(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint8_t pps[], uint32_t pps_size); +X_Bool hal_dsi_rx_ctrl_pre_init_pps(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint8_t pps[], uint32_t pps_size); +N +N/** +N* @brief 初始化dsi rx 模块 +N* @param rx_ctrl_handle: dsi rx handle +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_init(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +X_Bool hal_dsi_rx_ctrl_init(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +N +N/** +N* @brief dsi rx 模块去初始化 +N* @param rx_ctrl_handle: dsi rx handle +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_deinit(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +X_Bool hal_dsi_rx_ctrl_deinit(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +N +N/** +N* @brief 启动dsi rx +N* @param rx_ctrl_handle: dsi rx handle +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_start(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +X_Bool hal_dsi_rx_ctrl_start(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +N +N/** +N* @brief 重新配置dsi rx参数并恢复状态 (debug使用, 重新配置rx_ctrl_handle参数后调用该接口重启) +N* @param rx_ctrl_handle: dsi rx handle +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_restart(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +X_Bool hal_dsi_rx_ctrl_restart(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +N +N/** +N* @brief 停止dsi rx +N* @param rx_ctrl_handle: dsi rx handle +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_stop(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +X_Bool hal_dsi_rx_ctrl_stop(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +N +N/** +N* @brief 手动设置RX clk,一般RX CLK 由底层自动计算,用于特殊video mode场景出现FIFO FULL情况调试使用 +N* @param rxbr_clk: rx clk, 需要大于hs_lane_rate/8 +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_set_rx_clk(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_rx_clk_e rxbr_clk); +X_Bool hal_dsi_rx_ctrl_set_rx_clk(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_rx_clk_e rxbr_clk); +N +N/** +N* @brief 发送 MIPI HOST的读响应 CMD +N* @param rx_ctrl_handle: dsi rx handle +N* @param data_type: data type +N* @param vc: virtual channel +N* @param cmd_count: ack command 的长度 +N* @param ... : 需要发送的command(数量与cmd_count 配置一致) +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_send_ack_cmd(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, dsi_ack_data_type_e data_type, dsi_virtual_channel_e vc, uint8_t cmd_count, ...); +X_Bool hal_dsi_rx_ctrl_send_ack_cmd(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, dsi_ack_data_type_e data_type, dsi_virtual_channel_e vc, uint8_t cmd_count, ...); +N +N/** +N* @brief 使用数组方式回复短包,与hal_dsi_rx_ctrl_send_ack_cmd功能一致 +N* @param rx_ctrl_handle: dsi rx handle +N* @param data_size: 数组长度,固定为4 +N* @param data: 回复cmd数据,数据排列有严格规定: +N* data[0]:DI(data type) +N* data[1]:data 0 +N* data[2]:data 1 +N* data[3]:内部pkt type,短包固定为0 +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_ack_short_cmd(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint8_t data_size, uint8_t data[]); +X_Bool hal_dsi_rx_ctrl_ack_short_cmd(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint8_t data_size, uint8_t data[]); +N +N/** +N* @brief 使用数组方式回复长包,与hal_dsi_rx_ctrl_send_ack_cmd功能一致 +N* @param rx_ctrl_handle: dsi rx handle +N* @param data_size: 数组长度,为Word Count + header长度 (header固定为4) +N* @param data: 回复cmd数据,数据排列有严格规定: +N* data[0]:DI(data type) +N* data[1]:wc 0 (Word Count 低八位) +N* data[2]:wc 1 (Word Count 高八位) +N* data[3]:内部pkt type,长包固定为1 +N* data[N]:长包数据 +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_ack_long_cmd(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint32_t data_size, uint8_t data[]); +X_Bool hal_dsi_rx_ctrl_ack_long_cmd(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint32_t data_size, uint8_t data[]); +N +N/** +N* @brief 异步处理DSC接口,执行cus_dcs_entry_table里对应DCS immediately_func为false的函数 +N* @param rx_ctrl_handle: dsi rx handle +N* @retval true - 正常处理1个DSC , false - 无DSC 处理 +N*/ +Nbool hal_dsi_rx_ctrl_dcs_async_handler(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +X_Bool hal_dsi_rx_ctrl_dcs_async_handler(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +N +N/** +N* @brief 使用硬件filter丢弃不需要处理的CMD,避免MCU资源被无效CMD占用 +N* @param rx_ctrl_handle: dsi rx handle +N* @param filter_number: filter 编号(0-7) +N* @param cmd_start: 需要丢弃command code起始位 +N* @param cmd_end: 需要丢弃command code终止位 +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_set_hw_cmd_filter(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, +X_Bool hal_dsi_rx_ctrl_set_hw_cmd_filter(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, +N hal_rx_dcs_filter_sel_e filter_number, +N uint32_t cmd_start, uint32_t cmd_end); +N +N/** +N* @brief 使用内置pattern代替mipi输入(用于测试) +N* @param rx_ctrl_handle: dsi rx handle +N* @param pg_orient: pattern 方向(0:Vertical mode ; 1:Horizontal mode) +N* @param enable: 开启/关闭pattern +N* @param frame_rate: pattern 帧率 +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_enable_test_pattern(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint8_t pg_orient, bool enable, int frame_rate); +X_Bool hal_dsi_rx_ctrl_enable_test_pattern(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint8_t pg_orient, _Bool enable, int frame_rate); +N +N +N/** +N* @brief 获取AP 配置 BTA回复数据最大size +N* @param rx_ctrl_handle: dsi rx handle +N* @retval 返回数据大小 +N*/ +Nuint32_t hal_dsi_rx_ctrl_get_max_ret_size(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +N +N/** +N* @brief 获取AP Compression Mode Command配置,默认为0,谨慎使用 +N* @param rx_ctrl_handle: dsi rx handle +N* @retval AP 配置compressen_en +N*/ +Nbool hal_dsi_rx_ctrl_get_compressen_en(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +X_Bool hal_dsi_rx_ctrl_get_compressen_en(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +N +N/** +N* @brief 输入分辨率切换接口 +N* @param rx_ctrl_handle: dsi rx handle +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_toggle_resolution(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +X_Bool hal_dsi_rx_ctrl_toggle_resolution(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +N +N/** +N* @brief 配置 RX escape clk +N* @param rx_ctrl_handle: dsi rx handle +N* @param esc_clk: escape clk 单位Hz,10000000时回CMD为10Mhz +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_set_cus_esc_clk(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint32_t esc_clk); +X_Bool hal_dsi_rx_ctrl_set_cus_esc_clk(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint32_t esc_clk); +N +N/** +N* @brief 自动计算并配置硬件filter +N* @param rx_ctrl_handle: dsi rx handle +N* @param enable: 启动/关闭 硬件filter +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_set_auto_hw_filter(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, bool enable); +X_Bool hal_dsi_rx_ctrl_set_auto_hw_filter(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, _Bool enable); +N +N/* +N* @brief 输入帧率修改(针对video mode) +N* @param rx_ctrl_handle: dsi rx handle +N* @param frame_rate：frame rate +N*/ +Nbool hal_dsi_rx_ctrl_toggle_input_frame_rate(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, dsi_video_frame_rate_e frame_rate); +X_Bool hal_dsi_rx_ctrl_toggle_input_frame_rate(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, dsi_video_frame_rate_e frame_rate); +N +N/* +N* @brief 注册写命令的回调函数,用于特殊命令序列时写命令的处理. +N 可配合hal_dsi_rx_ctrl_set_auto_hw_filter关闭hw filter用于获取所有软件CMD +N* @param rx_ctrl_handle: dsi rx handle +N* @param 写命令处理函数 +N* @retval none +N*/ +Nvoid hal_dsi_rx_ctrl_register_write_cmd_entry(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_dsi_rx_ctrl_dcs_execute execute_func); +N +N/** +N* @brief 配置硬件自动回复命令 +N* 最大回复长度64,AP需要配置set_max_return_size后并且对比一直才会自动回复,不需要软件再参与 +N* 应用于所有回复固定数据的场景 +N* @param RXBR: registers struct +N* @param qresp_number: qresp 编号(0-7) +N* @param data_type: 需要回复的读命令的datatype +N* @param cmd_code: 需要回复的读命令 +N* @param cmd_count: 需要回复的命令的大小,长包最大size为64,与set_max_return_size一致才会回复 +N* @param ...: 需要回复的参数 +N* @retval true/false +N*/ +Nbool hal_dsi_rx_ctrl_set_auto_ack(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_rx_dcs_qresp_e qresp_number, dsi_ack_data_type_e data_type, uint32_t cmd_code, uint8_t cmd_count, ...); +X_Bool hal_dsi_rx_ctrl_set_auto_ack(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_rx_dcs_qresp_e qresp_number, dsi_ack_data_type_e data_type, uint32_t cmd_code, uint8_t cmd_count, ...); +N +N/* +N* @brief 初始化画点模式 +N* @param rx_ctrl_handle: dsi rx handle +N* @param draw_en: 画点模式使能 +N* @param pxl_init_en: 是否对全屏数据赋值,true:使用init_value赋值,false:使用上一帧数据作为初始值 +N* @param color_mode: 画点模式数据源格式见dsi_color_code_e +N* @param init_value: 全屏初始化数据,bit[23:16]--R，bit[15:8]--G，bit[7:0]--B +N* @retval none +N*/ +Nvoid hal_dsi_rx_ctrl_draw_mode_init(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, bool draw_en, bool pxl_init_en, dsi_color_code_e color_mode, uint32_t init_value); +Xvoid hal_dsi_rx_ctrl_draw_mode_init(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, _Bool draw_en, _Bool pxl_init_en, dsi_color_code_e color_mode, uint32_t init_value); +N +N/* +N* @brief 配置像素颜色 +N* @param rx_ctrl_handle: dsi rx handle +N* @param x: 像素点的x 坐标 +N* @param y: 像素点的y 坐标 +N* @param red_data: 像素点R分量 +N* @param green_data: 像素点G分量 +N* @param blue_data: 像素点B分量 +N* @retval none +N*/ +Nvoid hal_dsi_rx_ctrl_set_pixel_data(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, int x, int y, uint8_t red_data, uint8_t green_data, uint8_t blue_data); +N +N +N/** +N* @brief video mode下强制将数据设置为特定的color mode,具体type见dsi_color_code_e +N* @param rx_ctrl_handle: dsi rx handle +N* @param enable: 使能强制数据模式 +N* @param frc_vid_code: 强制的数据格式 +N* @retval none +N*/ +Nvoid hal_dsi_rx_ctrl_force_video_crtl(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, bool enable, dsi_color_code_e frc_vid_code); +Xvoid hal_dsi_rx_ctrl_force_video_crtl(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, _Bool enable, dsi_color_code_e frc_vid_code); +N +N/** +N* @brief 注册RX 事件回调函数 +N* @param rx_ctrl_handle: dsi rx handle +N* @param event_cb: 回调函数 +N* @param event_mask: 接收事件掩码,见hal_rx_event_e(eg:HAL_RX_FS_EVENT|HAL_RX_LINE_EVENT) +N* @param enable: 事件回调开关 +N* @param user_data: 预留扩展参数,不同事件事件配置不同参数 +N* @retval none +N*/ +Nvoid hal_dsi_rx_ctrl_register_callback(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_dsi_rx_ctrl_event_entry event_cb, uint32_t event_mask, bool enable, void *user_data); +Xvoid hal_dsi_rx_ctrl_register_callback(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_dsi_rx_ctrl_event_entry event_cb, uint32_t event_mask, _Bool enable, void *user_data); +N +N/** +N* @brief 配置是否打开长包CRC检查 +N* @param rx_ctrl_handle: dsi rx handle +N* @param enable: 开启或者屏蔽CRC检测 +N* @retval none +N*/ +Nvoid hal_dsi_rx_ctrl_set_check_crc(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, bool enable); +Xvoid hal_dsi_rx_ctrl_set_check_crc(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, _Bool enable); +N +N/** +N* @brief 配置rx log 等级 +N* @param rx_drv_level: rx log等级见枚举log_level_e +N* @retval none +N*/ +Nvoid hal_dsi_rx_ctrl_set_log_level(log_level_e rx_drv_level); +N +N/** +N * @brief 带颜色画线函数(直线、斜线) +N * @param x1,y1 起点坐标 +N * @param x2,y2 终点坐标 +N * @param red_data: 像素点R分量 +N * @param green_data: 像素点G分量 +N * @param blue_data: 像素点B分量 +N * @param line_weight: 线粗 +N * @return none +N */ +Nvoid hal_dsi_rx_ctrl_draw_line(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint8_t red_data, uint8_t green_data, uint8_t blue_data, line_weight_e line_weight); +N +N/** +N * @brief 设置需要获取pixel的坐标 +N * @param cap_x: 抓取pixel的x坐标 +N * @param cap_y: 抓取pixel的y坐标 +N * @return none +N */ +Nvoid hal_dsi_rx_ctrl_set_cap_pixel_pos(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x0, uint16_t y0); +N +N/** +N * @brief 获取指定坐标颜色,必须先设置获取颜色的坐标 +N * @return 返回指定坐标颜色 +N */ +Nuint32_t hal_dsi_rx_ctrl_get_cap_pixel_color(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); +N +N#endif //__HAL_DSI_RX_CTRL_H__ +L 17 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "hal_dsi_tx_ctrl.h" +L 1 "..\..\src\sdk\include\hal_dsi_tx_ctrl.h" 1 +N/******************************************************************************* +N* +N* +N* File: hal_dsi_tx_ctrl.h +N* Description: hal mipi dsi tx 头文件 +N* Version: V0.1 +N* Date: 2021-04-23 +N* Author: jaya +N *******************************************************************************/ +N#ifndef __HAL_DSI_TX_CTRL_H__ +N#define __HAL_DSI_TX_CTRL_H__ +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_dsi_datatype.h" +N#include "tau_device_datatype.h" +N#include "hal_gpio.h" +L 1 "..\..\src\sdk\include\hal_gpio.h" 1 +N/******************************************************************************* +N* +N* +N* File: hal_gpio.h +N* Description： gpio HAL层头文件 +N* Version： V0.1 +N* Date： 2023-07-27 +N* Author： kevin +N *******************************************************************************/ +N#ifndef __HAL_GPIO_H__ +N#define __HAL_GPIO_H__ +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_device_datatype.h" +N#include "tau_common.h" +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N/** +N* @brief GPIO pin +N*/ +Ntypedef enum +N{ +N /*以GPIO命名PIN*/ +N IO_PAD_GPIO0 = 0, +N IO_PAD_GPIO1, +N IO_PAD_GPIO2, +N IO_PAD_GPIO3, +N IO_PAD_GPIO4, +N IO_PAD_GPIO5, +N IO_PAD_GPIO6, +N IO_PAD_GPIO7, +N IO_PAD_GPIO8, +N IO_PAD_GPIO9, +N IO_PAD_GPIO10, +N IO_PAD_GPIO11, +N IO_PAD_GPIO12, +N IO_PAD_GPIO13, +N IO_PAD_GPIO14, +N IO_PAD_GPIO15, +N IO_PAD_GPIO16, +N IO_PAD_GPIO17, +N IO_PAD_GPIO18, +N IO_PAD_GPIO19, +N IO_PAD_GPIO20, +N IO_PAD_GPIO21, +N IO_PAD_GPIO22, +N IO_PAD_GPIO23, +N IO_PAD_GPIO24, +N IO_PAD_GPIO25, +N +N /*以实际PAD NAME命名PIN*/ +N IO_PAD_AP_SPIS_MISO = IO_PAD_GPIO0, +N IO_PAD_AP_SPIS_MOSI = IO_PAD_GPIO1, +N IO_PAD_AP_INT = IO_PAD_GPIO2, +N IO_PAD_AP_TE = IO_PAD_GPIO3, +N IO_PAD_AP_SWIRE = IO_PAD_GPIO4, +N IO_PAD_TD_SPIM_MISO = IO_PAD_GPIO5, +N IO_PAD_TD_SPIM_MOSI = IO_PAD_GPIO6, +N IO_PAD_TD_RSTN = IO_PAD_GPIO7, +N IO_PAD_AP_PWMEN = IO_PAD_GPIO8, +N IO_PAD_AP_SPIS_CLK = IO_PAD_GPIO9, +N IO_PAD_AP_SPIS_CSN = IO_PAD_GPIO10, +N IO_PAD_TD_FC_CLK = IO_PAD_GPIO11, +N IO_PAD_TD_FC_CSN = IO_PAD_GPIO12, +N IO_PAD_TD_FC_IO0 = IO_PAD_GPIO13, +N IO_PAD_TD_FC_IO1 = IO_PAD_GPIO14, +N IO_PAD_SWD_CLK = IO_PAD_GPIO15, +N IO_PAD_SWD_DIO = IO_PAD_GPIO16, +N IO_PAD_AP_RSTN = IO_PAD_GPIO17, +N IO_PAD_UART0_TX = IO_PAD_GPIO18, +N IO_PAD_TD_SPIM_CLK = IO_PAD_GPIO19, +N IO_PAD_TD_SPIM_CSN = IO_PAD_GPIO20, +N IO_PAD_AP_TPRSTN = IO_PAD_GPIO21, +N IO_PAD_TD_INT = IO_PAD_GPIO22, +N IO_PAD_TD_TP_RESX = IO_PAD_GPIO23, +N IO_PAD_UART1_TX = IO_PAD_GPIO24, +N IO_PAD_UART0_RX = IO_PAD_GPIO25, +N +N IO_PAD_MAX, +N +N +N /*以实际引脚序号命名PIN*/ +N IO_PIN_1 = IO_PAD_SWD_CLK, +N IO_PIN_2 = IO_PAD_UART0_TX, +N IO_PIN_3 = IO_PAD_SWD_DIO, +N IO_PIN_4 = IO_PAD_TD_SPIM_MOSI, +N IO_PIN_5 = IO_PAD_TD_SPIM_CLK, +N IO_PIN_6 = IO_PAD_TD_SPIM_CSN, +N IO_PIN_7 = IO_PAD_TD_SPIM_MISO, +N IO_PIN_8 = IO_PAD_TD_RSTN, +N IO_PIN_9 = IO_PAD_TD_FC_CSN, +N IO_PIN_10 = IO_PAD_TD_FC_CLK, +N IO_PIN_11 = IO_PAD_TD_FC_IO0, +N IO_PIN_12 = IO_PAD_TD_FC_IO1, +N IO_PIN_13 = IO_PAD_TD_TP_RESX, +N IO_PIN_14 = IO_PAD_UART1_TX, +N IO_PIN_15 = IO_PAD_AP_SWIRE, +N IO_PIN_16 = IO_PAD_AP_INT, +N IO_PIN_17 = IO_PAD_AP_PWMEN, +N IO_PIN_18 = IO_PAD_AP_TPRSTN, +N +N IO_PIN_29 = IO_PAD_AP_TE, +N IO_PIN_30 = IO_PAD_AP_SPIS_MISO, +N IO_PIN_31 = IO_PAD_AP_SPIS_CSN, +N IO_PIN_32 = IO_PAD_AP_SPIS_CLK, +N IO_PIN_33 = IO_PAD_AP_SPIS_MOSI, +N IO_PIN_34 = IO_PAD_AP_RSTN, +N IO_PIN_35 = IO_PAD_TD_INT, +N IO_PIN_36 = IO_PAD_UART0_RX, +N +N} io_pad_e; +N +N +N/* +N芯片引脚 | 默认mode | 可选mode +N---------------------------------------------------------------- +NIO_PIN_1 | IO_PAD_SWCLK, | PIN1_MODE_SWDCLK +N | | PIN1_MODE_GPIO15 +N---------------------------------------------------------------- +NIO_PIN_2 | IO_PAD_UART0_TX, | PIN2_MODE_UART0_TX +N | | PIN2_MODE_PWMO +N | | PIN2_MODE_GPIO18 +N | | PIN2_MODE_PWMI +N | | PIN2_MODE_TEAR1 +N---------------------------------------------------------------- +NIO_PIN_3 | IO_PAD_SWDIO, | PIN3_MODE_SWDIO +N | | PIN3_MODE_GPIO16 +N---------------------------------------------------------------- +NIO_PIN_4 | IO_PAD_TD_SPIM_MOSI, | PIN4_MODE_SPIM_MOSI +N | | PIN4_MODE_I2C02_SDA +N | | PIN4_MODE_GPIO6 +N | | PIN4_MODE_UART0_TX +N---------------------------------------------------------------- +NIO_PIN_5 | IO_PAD_TD_SPIM_CLK, | PIN5_MODE_SPIM_SCLK +N | | PIN5_MODE_I2C1_SCL +N | | PIN5_MODE_GPIO19 +N---------------------------------------------------------------- +NIO_PIN_6 | IO_PAD_TD_SPIM_CSN, | PIN6_MODE_SPIM_CSN +N | | PIN6_MODE_I2C1_SDA +N | | PIN6_MODE_GPIO20 +N---------------------------------------------------------------- +NIO_PIN_7 | IO_PAD_TD_SPIM_MISO, | PIN7_MODE_SPIM_MISO +N | | PIN7_MODE_I2C02_SCL +N | | PIN7_MODE_GPIO5 +N---------------------------------------------------------------- +NIO_PIN_8 | IO_PAD_TD_RSTN, | PIN8_MODE_GPIO7 +N | | PIN8_MODE_I2C02_SDA +N---------------------------------------------------------------- +NIO_PIN_9 | IO_PAD_TD_FC_CSN, | PIN9_MODE_TSPIS_CSN +N | | PIN9_MODE_GPIO12 +N---------------------------------------------------------------- +NIO_PIN_10 | IO_PAD_TD_FC_CLK, | PIN10_MODE_TSPIS_CLK +N | | PIN10_MODE_GPIO11 +N---------------------------------------------------------------- +NIO_PIN_11 | IO_PAD_TD_FC_IO0, | PIN11_MODE_TSPIS_IO0 +N | | PIN11_MODE_GPIO13 +N | | PIN11_MODE_I2C02_SDA +N---------------------------------------------------------------- +NIO_PIN_12 | IO_PAD_TD_FC_IO1, | PIN12_MODE_TSPIS_IO1 +N | | PIN12_MODE_GPIO14 +N | | PIN12_MODE_I2C02_SCL +N---------------------------------------------------------------- +NIO_PIN_13 | IO_PAD_TD_TP_RESX, | PIN13_MODE_GPIO23 +N | | PIN13_MODE_PWMO +N | | PIN13_MODE_UART1_RX +N | | PIN13_MODE_UART1_RX +N---------------------------------------------------------------- +NIO_PIN_14 | IO_PAD_UART1_TX, | PIN14_MODE_GPIO24 +N | | PIN14_MODE_UART0_RX +N | | PIN14_MODE_UART1_TX +N | | +N---------------------------------------------------------------- +NIO_PIN_15 | IO_PAD_AP_SWIRE, | PIN15_MODE_SWIRE +N | | PIN15_MODE_PWMO +N | | PIN15_MODE_GPIO4 +N---------------------------------------------------------------- +NIO_PIN_16 | IO_PAD_AP_INT, | PIN16_MODE_GPIO2 +N---------------------------------------------------------------- +NIO_PIN_17 | IO_PAD_AP_PWMEN, | PIN17_MODE_UART0_RX +N | | PIN17_MODE_GPIO8 +N | | PIN17_MODE_PWMO +N---------------------------------------------------------------- +NIO_PIN_18 | IO_PAD_AP_TPRSTN, | PIN18_MODE_UART0_RX +N | | PIN18_MODE_GPIO21 +N | | PIN18_MODE_I2C02_SCL +N---------------------------------------------------------------- +NIO_PIN_29 | IO_PAD_AP_TE, | PIN29_MODE_JTAG_TRSTN +N | | PIN29_MODE_TEAR +N | | PIN29_MODE_GPIO3 +N---------------------------------------------------------------- +NIO_PIN_30 | IO_PAD_AP_SPIS_MISO, | PIN30_MODE_JTAG_TDO +N | | PIN30_MODE_SPIS_MISO +N | | PIN30_MODE_GPIO0 +N | | PIN30_MODE_UART0_RX +N | | PIN30_MODE_I2C1_SCL +N---------------------------------------------------------------- +NIO_PIN_31 | IO_PAD_AP_SPIS_CSN, | PIN31_MODE_JTAG_TMS +N | | PIN31_MODE_SPIS_CSN +N | | PIN31_MODE_GPIO10 +N | | PIN31_MODE_I2C02_SDA +N---------------------------------------------------------------- +NIO_PIN_32 | IO_PAD_AP_SPIS_CLK, | PIN32_MODE_JTAG_TCK +N | | PIN32_MODE_SPIS_SCLK +N | | PIN32_MODE_GPIO9 +N | | PIN32_MODE_I2C02_SCL +N---------------------------------------------------------------- +NIO_PIN_33 | IO_PAD_AP_SPIS_MOSI, | PIN33_MODE_JTAG_TDI +N | | PIN33_MODE_SPIS_MOSI +N | | PIN33_MODE_GPIO1 +N | | PIN33_MODE_UART0_TX +N | | PIN33_MODE_I2C1_SDA_0 +N---------------------------------------------------------------- +NIO_PIN_34 | IO_PAD_AP_RSTN, | PIN34_MODE_GPIO17 +N---------------------------------------------------------------- +NIO_PIN_35 | IO_PAD_TD_INT, | PIN35_MODE_GPIO22 +N---------------------------------------------------------------- +NIO_PIN_36 | IO_PAD_UART0_RX, | PIN36_MODE_UART0_RX +N | | PIN36_MODE_PWMO +N | | PIN36_MODE_GPIO25 +N---------------------------------------------------------------- +N*/ +N +N +N/** +N* @brief PIN1 IO_PAD_SWD_CLK 可选的mode +N*/ +Ntypedef enum +N{ +N PIN1_MODE_SWDCLK = 0, +N PIN1_MODE_GPIO15 = 2, +N} pin1_mode_e; +N +N +N/** +N* @brief PIN2 PAD_UART0_TX可选的mode +N*/ +Ntypedef enum +N{ +N PIN2_MODE_UART0_TX = 0, +N PIN2_MODE_PWMO = 1, +N PIN2_MODE_GPIO18 = 2, +N PIN2_MODE_PWMI = 3, +N PIN2_MODE_TEAR1 = 4, +N} pin2_mode_e; +N +N/** +N* @brief PIN3 IO_PAD_SWD_DIO 可选的mode +N*/ +Ntypedef enum +N{ +N PIN3_MODE_SWDIO = 0, +N PIN3_MODE_GPIO16 = 2, +N} pin3_mode_e; +N +N +N/** +N* @brief PIN4 PAD_TD_SPIM_MOSI可选的mode +N*/ +Ntypedef enum +N{ +N PIN4_MODE_SPIM_MOSI = 0, +N PIN4_MODE_I2C02_SDA = 1, +N PIN4_MODE_GPIO6 = 2, +N PIN4_MODE_UART0_TX = 3, +N} pin4_mode_e; +N +N/** +N* @brief PIN5 PAD_TD_SPIM_CLK可选的mode +N*/ +Ntypedef enum +N{ +N PIN5_MODE_SPIM_SCLK = 0, +N PIN5_MODE_I2C1_SCL = 1, +N PIN5_MODE_GPIO19 = 2, +N} pin5_mode_e; +N +N/** +N* @brief PIN6 PAD_TD_SPIM_CSN可选的mode +N*/ +Ntypedef enum +N{ +N PIN6_MODE_SPIM_CSN = 0, +N PIN6_MODE_I2C1_SDA = 1, +N PIN6_MODE_GPIO20 = 2, +N} pin6_mode_e; +N +N/** +N* @brief PIN7 PAD_TD_SPIM_MISO可选的mode +N*/ +Ntypedef enum +N{ +N PIN7_MODE_SPIM_MISO = 0, +N PIN7_MODE_I2C02_SCL = 1, +N PIN7_MODE_GPIO5 = 2, +N} pin7_mode_e; +N +N/** +N* @brief PIN8 PAD_TD_RSTN可选的mode +N*/ +Ntypedef enum +N{ +N PIN8_MODE_GPIO7 = 2, +N PIN8_MODE_I2C02_SDA = 3, +N} pin8_mode_e; +N +N/** +N* @brief PIN9 PAD_TD_FC_CSN可选的mode +N*/ +Ntypedef enum +N{ +N PIN9_MODE_TSPIS_CSN = 0, +N PIN9_MODE_GPIO12 = 2, +N} pin9_mode_e; +N +N/** +N* @brief PIN10 PAD_TD_FC_CLK可选的mode +N*/ +Ntypedef enum +N{ +N PIN10_MODE_TSPIS_CLK = 0, +N PIN10_MODE_GPIO11 = 2, +N} pin10_mode_e; +N +N +N/** +N* @brief PIN11 PAD_TD_FC_IO0可选的mode +N*/ +Ntypedef enum +N{ +N PIN11_MODE_TSPIS_IO0 = 0, +N PIN11_MODE_GPIO13 = 2, +N PIN11_MODE_I2C02_SDA = 3, +N} pin11_mode_e; +N +N/** +N* @brief PIN12 PAD_TD_FC_IO1可选的mode +N*/ +Ntypedef enum +N{ +N PIN12_MODE_TSPIS_IO1 = 0, +N PIN12_MODE_GPIO14 = 2, +N PIN12_MODE_I2C02_SCL = 3, +N} pin12_mode_e; +N +N/** +N* @brief PIN13 PAD_TD_TP_RESX可选的mode +N*/ +Ntypedef enum +N{ +N PIN13_MODE_GPIO23 = 2, +N PIN13_MODE_PWMO = 3, +N PIN13_MODE_UART1_RX = 4, +N} pin13_mode_e; +N +N/** +N* @brief PIN14 PAD_UART1_TX可选的mode +N*/ +Ntypedef enum +N{ +N PIN14_MODE_GPIO24 = 2, +N PIN14_MODE_UART0_RX = 3, +N PIN14_MODE_UART1_TX = 4, +N} pin14_mode_e; +N +N +N +N/** +N* @brief PIN15 PAD_AP_SWIRE可选的mode +N*/ +Ntypedef enum +N{ +N PIN15_MODE_SWIRE = 0, +N PIN15_MODE_PWMO = 1, +N PIN15_MODE_GPIO4 = 2, +N} pin15_mode_e; +N +N/** +N* @brief PIN16 IO_PAD_AP_INT 可选的mode +N*/ +Ntypedef enum +N{ +N PIN16_MODE_GPIO2 = 2, +N} pin16_mode_e; +N +N/** +N* @brief PIN17 PAD_AP_PWMEN可选的mode +N*/ +Ntypedef enum +N{ +N PIN17_MODE_UART0_RX = 1, +N PIN17_MODE_GPIO8 = 2, +N PIN17_MODE_PWMO = 3, +N} pin17_mode_e; +N +N/** +N* @brief PIN18 IO_PAD_AP_TPRSTN 可选的mode +N*/ +Ntypedef enum +N{ +N PIN18_MODE_UART0_RX = 0, +N PIN18_MODE_GPIO21 = 2, +N PIN18_MODE_I2C02_SCL = 3, +N} pin18_mode_e; +N +N +N//---------- +N +N/** +N* @brief PIN29 IO_PAD_AP_TE 可选的mode +N*/ +Ntypedef enum +N{ +N PIN29_MODE_JTAG_TRSTN = 0, +N PIN29_MODE_TEAR = 1, +N PIN29_MODE_GPIO3 = 2, +N} pin29_mode_e; +N +N +N/** +N* @brief PIN30 IO_PAD_AP_SPIS_MISO 可选的mode +N*/ +Ntypedef enum +N{ +N PIN30_MODE_JTAG_TDO = 0, +N PIN30_MODE_SPIS_MISO = 1, +N PIN30_MODE_GPIO0 = 2, +N PIN30_MODE_UART0_RX = 3, +N PIN30_MODE_I2C1_SCL = 6, +N} pin30_mode_e; +N +N/** +N* @brief PIN31 IO_PAD_AP_SPIS_CSN 可选的mode +N*/ +Ntypedef enum +N{ +N PIN31_MODE_JTAG_TMS = 0, +N PIN31_MODE_SPIS_CSN = 1, +N PIN31_MODE_GPIO10 = 2, +N PIN31_MODE_I2C02_SDA = 3, +N} pin31_mode_e; +N +N/** +N* @brief PIN32 IO_PAD_AP_SPIS_CLK 可选的mode +N*/ +Ntypedef enum +N{ +N PIN32_MODE_JTAG_TCK = 0, +N PIN32_MODE_SPIS_SCLK = 1, +N PIN32_MODE_GPIO9 = 2, +N PIN32_MODE_I2C02_SCL = 3, +N} pin32_mode_e; +N +N/** +N* @brief PIN33 IO_PAD_AP_SPIS_MOSI 可选的mode +N*/ +Ntypedef enum +N{ +N PIN33_MODE_JTAG_TDI = 0, +N PIN33_MODE_SPIS_MOSI = 1, +N PIN33_MODE_GPIO1 = 2, +N PIN33_MODE_UART0_TX = 3, +N PIN33_MODE_I2C1_SDA_0 = 6, +N} pin33_mode_e; +N +N/** +N* @brief PIN34 PAD_AP_RST可选的mode +N*/ +Ntypedef enum +N{ +N PIN34_MODE_GPIO17 = 2, +N} pin34_mode_e; +N +N +N/** +N* @brief PIN35 PAD_TD_INT可选的mode +N*/ +Ntypedef enum +N{ +N PIN35_MODE_GPIO22 = 2, +N} pin35_mode_e; +N +N +N/** +N* @brief PIN36 PAD_UART_RX可选的mode +N*/ +Ntypedef enum +N{ +N PIN36_MODE_UART0_RX = 0, +N PIN36_MODE_PWMO = 1, +N PIN36_MODE_GPIO25 = 2, +N} pin36_mode_e; +N +N +N +N//------------------------------------------------------------------------- +N/** +N* @brief PAD_SFC_CLK可选的mode 内部PAD +N*/ +Ntypedef enum +N{ +N IO_MODE_INTER_FC_CLK = 0, +N IO_MODE_TSPIS_CLK_EN = 2, +N} pad_sfc_clk_mode_e; +N +N/** +N* @brief PAD_SFC_CSN可选的mode 内部PAD +N*/ +Ntypedef enum +N{ +N IO_MODE_INTER_FC_CSN = 0, +N IO_MODE_TSPIS_CSN_EN = 2, +N} pad_sfc_csn_mode_e; +N +N/** +N* @brief PAD_SFC_IO0可选的mode 内部PAD +N*/ +Ntypedef enum +N{ +N IO_MODE_INTER_FC_IO0 = 0, +N IO_MODE_TSPIS_IO0_EN = 2, +N} pad_sfc_io0_mode_e; +N +N/** +N* @brief PAD_SFC_IO1可选的mode 内部PAD +N*/ +Ntypedef enum +N{ +N IO_MODE_INTER_FC_IO1 = 0, +N IO_MODE_TSPIS_IO1_EN = 2, +N} pad_sfc_io1_mode_e; +N +N/** +N* @brief PAD电压转换速率 +N*/ +Ntypedef enum +N{ +N IO_SLEW_RATE_SLOW = 0, +N IO_SLEW_RATE_FAST = 1, +N} pad_slew_rate_e; +N +N/******************************************************************************* +N* IOE +N*******************************************************************************/ +N/** +N* @brief GPIO io方向 +N*/ +Ntypedef enum +N{ +N IO_IOE_INPUT = 0, +N IO_IOE_OUTPUT, +N IO_IOE_NONE +N} gpio_ioe_e; +N +N/** +N* @brief GPIO level +N*/ +Ntypedef enum +N{ +N IO_LVL_LOW = 0, +N IO_LVL_HIGH, +N IO_LVL_NONE +N} gpio_level_e; +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/** +N* @brief PAD与MODE的MAP结构体 +N*/ +Ntypedef struct +N{ +N io_pad_e pad; +N uint8_t mode; +N gpio_ioe_e ioe; +N gpio_level_e lvl; +N} io_pad_attr_t; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N/** +N* @brief 配置指定PAD为GPIO mode，方向为input，指定中断触发方式 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param trig：4种中断触发方式，参考枚举类型sys_cfg_trigger_e +N* @retval 无 +N*/ +Nvoid hal_gpio_init_eint(io_pad_e pad, sys_cfg_trigger_e trig); +N +N/** +N* @brief 注册GPIO中断回调函数 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param cb_func：回调函数地址 +N* @param data：回调函数参数地址 +N* @retval 无 +N*/ +Nvoid hal_gpio_reg_eint_cb(io_pad_e pad, fcb_type cb_func); +N +N/** +N* @brief 开关GPIO中断 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param state：开关控制 +N* @retval 无 +N*/ +Nvoid hal_gpio_ctrl_eint(io_pad_e pad, bool state); +Xvoid hal_gpio_ctrl_eint(io_pad_e pad, _Bool state); +N +N/** +N* @brief 获取GPIO中断类型 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @retval 无 +N*/ +Ngpio_int_e hal_gpio_get_int_type(io_pad_e pad); +N +N/** +N* @brief 配置指定PAD为GPIO mode，方向为output，指定初始电平 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param lvl：初始电平，参考枚举类型gpio_level_e +N* @retval 无 +N*/ +Nvoid hal_gpio_init_output(io_pad_e pad, gpio_level_e lvl); +N +N/** +N* @brief 封装设置输出接口 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param lvl：初始电平，参考枚举类型gpio_level_e +N* @retval 无 +N*/ +Nvoid hal_gpio_set_output_data(io_pad_e pad, gpio_level_e lvl); +N +N/** +N* @brief 配置指定PAD为GPIO mode，方向为input +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @retval 无 +N*/ +Nvoid hal_gpio_init_input(io_pad_e pad); +N +N/** +N* @brief 读取输入电平 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @retval 无 +N*/ +Ngpio_level_e hal_gpio_get_input_data(io_pad_e pad); +N +N/** +N* @brief 设置io mode +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param mode：工作模式，参考各PAD对应的mode枚举类型 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_mode(io_pad_e pad, uint8_t mode); +N +N/** +N* @brief 设置io 为高阻态 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @retval 无 +N*/ +Nvoid hal_gpio_set_high_impedance(io_pad_e pad); +N +N/** +N* @brief 获取指定PAD的默认上拉、下拉状态 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param up_enable：默认上拉状态 +N* @param down_enable：默认下拉状态 +N* @retval 无 +N*/ +Nvoid hal_gpio_get_pull_state(io_pad_e pad, bool *up_enable, bool *down_enable); +Xvoid hal_gpio_get_pull_state(io_pad_e pad, _Bool *up_enable, _Bool *down_enable); +N +N/** +N* @brief 配置指定PAD的默认上拉、下拉状态 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param up_enable：默认上拉状态 +N* @param down_enable：默认下拉状态 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_pull_state(io_pad_e pad, bool up_enable, bool down_enable); +Xvoid hal_gpio_set_pull_state(io_pad_e pad, _Bool up_enable, _Bool down_enable); +N +N/** +N* @brief 配置指定PAD是否为施密特触发 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param st_enable：1为施密特触发，0为正常触发 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_schmitt_trigger(io_pad_e pad, bool st_enable); +Xvoid hal_gpio_set_schmitt_trigger(io_pad_e pad, _Bool st_enable); +N +N/** +N* @brief 配置指定PAD的驱动能力 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param strength：驱动强度，取值为0~3 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_driving_strength(io_pad_e pad, uint8_t strength); +N +N/** +N* @brief 配置指定PAD的电压转换速率 +N* @param pad：GPIO序号，参考枚举类型gpio_pad_e +N* @param rate：驱动强度，取值为0~3 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_slew_rate(io_pad_e pad, pad_slew_rate_e rate); +N +N/** +N* @brief 配置AP_RSTN引脚中断 +N* @param enable: 中断开关 +N* @param cb_func：回调函数 +N* @param trig：触发模式 +N* @retval 无 +N*/ +Nvoid hal_gpio_set_ap_reset_int(bool enable, fcb_type cb_func, sys_cfg_trigger_e trig); +Xvoid hal_gpio_set_ap_reset_int(_Bool enable, fcb_type cb_func, sys_cfg_trigger_e trig); +N +N/** +N* @brief 批量设置IO参数 +N* @param attrs: PAD属性 +N* @param size: 数组成员个数 +N* @retval 无 +N*/ +Nvoid hal_gpio_config_pad(io_pad_attr_t *attrs, uint8_t size); +N +N#endif /* __HAL_GPIO_H__ */ +L 19 "..\..\src\sdk\include\hal_dsi_tx_ctrl.h" 2 +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/** +N* @brief blank display configure type +N*/ +Ntypedef struct +N{ +N uint16_t st_col; /* 补黑区域起始坐标，RGBG格式以子像素计数*/ +N uint16_t width; /* 补黑区域宽度，RGBG格式以子像素计数*/ +N uint8_t remap_en; /* 补黑区域是否参与子像素重排*/ +N uint8_t blank_en; /* 补黑区域开关*/ +N} blank_disp_t; +N +N/** +N* @brief pentile remap rule configuration type in rom code +N*/ +Ntypedef uint8_t (remap_rule_t)[24]; +N +N/** +N* @brief 客制化MIPI TX参数结构体 +N*/ +Ntypedef struct +N{ +N bool pentile_enable; /* 是否pentile输出*/ +X _Bool pentile_enable; +N bool pentile_reverse_en; /* 是否打开芯片本身行翻转功能*/ +X _Bool pentile_reverse_en; +N bool pentile_24b; /* 是否以RGB IC搭配RGBG玻璃*/ +X _Bool pentile_24b; +N uint32_t rgb_hact; /* RGB IC搭配RGBG玻璃使用时IC水平方向分辨率*/ +N remap_rule_t *remapl_rule; /* RGB IC搭配RGBG玻璃使用时remap规则1*/ +N remap_rule_t *remapr_rule; /* RGB IC搭配RGBG玻璃使用时remap规则2*/ +N blank_disp_t blank_info0; /* 补黑参数配置信息*/ +N blank_disp_t blank_info1; /* 补黑参数配置信息*/ +N} dsi_tx_pent_info_t; +N +N/** +N* @brief MIPI TX clk/data lane是否自动进LP控制枚举类型 +N* 不同driver IC spec不同,对Lane rate范围要求也不同 +N* 无法点亮时可尝试替换不同的模式 +N*/ +Ntypedef enum +N{ +N ALWAYS_HS = 0, // vid输出默认此模式，仅VSA自动进LP; cmd输出暂不支持此模式 +N ONLY_DATA_LANE_AUTO_LP = 1, // cmd输出默认此模式，data lane行间自动进LP， clk保持HS +N CLK_DATA_LANE_AUTO_LP = 2, // data/clk lane行间自动进LP +N} dsi_tx_lane_lp_e; +N +N/** +N* @brief tx pq filter index +N* 默认使用OPT +N*/ +Ntypedef enum +N{ +N TX_FLT_OPT = 0, +N TX_FLT_LINEAR = 1, +N TX_FLT_MAX +N} hal_dsi_tx_pq_filter_e; +N +N/** +N* @brief 客制化MIPI TX参数结构体 +N*/ +Ntypedef struct +N{ +N dsi_base_trans_info_t base_info; /* mipi video 转换基本信息 */ +N uint32_t dpi_vsa; /* DPI VSA*/ +N uint32_t dpi_vbp; /* DPI VBP*/ +N uint32_t dpi_vfp; /* DPI VFP*/ +N uint32_t dpi_hsa; /* DPI HSA*/ +N uint32_t dpi_hbp; /* DPI HBP*/ +N uint32_t dpi_hfp; /* DPI HFP*/ +N float tx_frame_rate; /* 默认60Hz输出,不建议配置为其他,仅作为debug使用 */ +N uint8_t lane_num; /* TX 使用的 lane 数量*/ +N bool used; /* handle使用标志位 内部自动更新状态，不需要操作*/ +X _Bool used; +N bool lp_exit_lpdt; /* 每一条LP CMD都退出LPDT */ +X _Bool lp_exit_lpdt; +N dsi_tx_lane_lp_e tx_lane_lp; /* clk/data lane是否自动进LP模式配置 */ +N dsi_virtual_channel_e channel_id; /* 虚拟通道ID，默认为0*/ +N dsi_video_mode_type_e vid_mode; /* video输出时选择输出的vid模式种类 */ +N dsi_tx_cmd_tx_type_e cmd_tx_type; /* 初始化模式传输命令方式，0:HS; 1:LP */ +N dsi_tx_pent_info_t pentile_info; /* pentile屏基本信息 */ +N hal_dsi_tx_pq_filter_e tx_pq_index; /* 画质调整滤波器,默认为OPT最优效果 */ +N} hal_dsi_tx_ctrl_handle_t; +N +N/** +N* @brief TE 信号产生模式 +N*/ +Ntypedef enum +N{ +N TE_60HZ_MODE = 0, +N TE_USER_MODE = 1, /* 底层不产生TE, 由hal_dsi_tx_ctrl_gen_a_tear_signal 接口产生 */ +N TE_STOP_MODE = 1, +N TE_90HZ_MODE = 2, +N TE_120HZ_MODE = 3, +N TE_144HZ_MODE = 4, +N TE_160HZ_MODE = 5, +N TE_MODE_MAX +N} te_mode_e; +N +N/** +N* @brief dpi tx vpg style +N*/ +Ntypedef enum +N{ +N TX_VPG_V_COLOR = 0, +N TX_VPG_H_COLOR = 1, +N TX_VPG_V_BER = 2, +N TX_VPG_FLICKER = 3, +N TX_VPG_MAX +N} dsi_tx_vpg_style_e; +N +N/** +N* @brief MIPI TX初始化 +N* @param tx_ctrl_handle: MIPI TX实例 +N* @retval true/false +N*/ +Nbool hal_dsi_tx_ctrl_init(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); +X_Bool hal_dsi_tx_ctrl_init(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); +N +N/** +N* @brief MIPI TX反初始化 +N* @param tx_ctrl_handle: MIPI TX实例 +N* @retval true/false +N*/ +Nbool hal_dsi_tx_ctrl_deinit(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); +X_Bool hal_dsi_tx_ctrl_deinit(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); +N +N/** +N* @brief MIPI TX创建实例 +N* @param None +N* @retval tx_ctrl_handle: MIPI TX实例 +N*/ +Nhal_dsi_tx_ctrl_handle_t *hal_dsi_tx_ctrl_create_handle(void); +N +N/** +N* @brief MIPI TX释放实例 +N* @param tx_ctrl_handle: MIPI TX实例 +N* @retval true/false +N*/ +Nbool hal_dsi_tx_ctrl_release_handle(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); +X_Bool hal_dsi_tx_ctrl_release_handle(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); +N +N/** +N* @brief MIPI TX开始运行 +N* @param tx_ctrl_handle: MIPI TX实例 +N* @retval true/false +N*/ +Nbool hal_dsi_tx_ctrl_start(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); +X_Bool hal_dsi_tx_ctrl_start(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); +N +N/** +N* @brief MIPI TX停止运行 +N* @param tx_ctrl_handle: MIPI TX实例 +N* @retval true/false +N*/ +Nbool hal_dsi_tx_ctrl_stop(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); +X_Bool hal_dsi_tx_ctrl_stop(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); +N +N/** +N* @brief MIPI TX接收命令 +N* @param data_type: 数据类型，参考枚举类型dsi_data_type_e +N* @param vc: 虚拟通道编号，参考枚举类型dsi_virtual_channel_e +N* @param cmd: DCS指令 +N* @param size: 读取数据长度 +N* @param data: 数据存放地址 +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_read_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd, uint8_t size, uint8_t *data); +N +N/** +N* @brief video高速数据传输时V porch阶段进行bta回读接口 +N* @param data_type: 数据类型，参考枚举类型dsi_data_type_e +N* @param cmd: DCS指令 +N* @param size: 读取数据长度 +N* @param data: 数据存放地址 +N* @retval true-BTA回复获取有效，false-BTA回复未获得 +N* @attention 需要考虑V porch时长是否足够size长度的寄存器回读，否则造成TX数据通路出错 +N*/ +Nbool hal_dsi_tx_ctrl_vporch_bta_opera(uint8_t data_type, uint8_t cmd, uint8_t size, uint8_t *data); +X_Bool hal_dsi_tx_ctrl_vporch_bta_opera(uint8_t data_type, uint8_t cmd, uint8_t size, uint8_t *data); +N +N/** +N* @brief MIPI TX发送命令 +N* @param data_type: 数据类型，参考枚举类型dsi_data_type_e +N* @param vc: 虚拟通道编号，参考枚举类型dsi_virtual_channel_e +N* @param cmd_count: 可变参数个数 +N* @param ...: 可变参数 +N* @retval true-command发送正常；false-TX当前状态不能发送command +N*/ +Nbool hal_dsi_tx_ctrl_write_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd_count, ...); +X_Bool hal_dsi_tx_ctrl_write_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd_count, ...); +N +N/** +N* @brief MIPI TX发送命令 +N* @param data_type: 数据类型，参考枚举类型dsi_data_type_e +N* @param vc: 虚拟通道编号，参考枚举类型dsi_virtual_channel_e +N* @param size: data个数 +N* @param data: data数组 +N* @retval true-command发送正常；false-TX当前状态不能发送command +N*/ +Nbool hal_dsi_tx_ctrl_write_array_cmd(uint8_t data_type, uint8_t vc, uint8_t size, const uint8_t *data); +X_Bool hal_dsi_tx_ctrl_write_array_cmd(uint8_t data_type, uint8_t vc, uint8_t size, const uint8_t *data); +N +N/** +N* @brief 切换至 LP cmd发送模式 +N* @param enable: true-进行cmd发送；false-结束LP cmd发送 +N* @retval None +N* @attention 应用场景：AP enter sleep后传输发送LP cmd +N*/ +Nvoid hal_dsi_tx_ctrl_cmd_mode(bool enable); +Xvoid hal_dsi_tx_ctrl_cmd_mode(_Bool enable); +N +N/** +N* @brief 设置TX escape mode时钟 +N* @param esc_clk: escape clk 单位Hz,10000000时CMD为10Mhz +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_set_escape_clock_div(uint32_t esc_clk); +N +N/** +N* @brief 设置RGB或BGR +N* @param endianness: 选择RGB或BGR显示，参考dsi_endianness_e +N* @attention 接口需要在初始化接口hal_dsi_tx_ctrl_init调用前才能生效 +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_set_endianness(dsi_endianness_e endianness); +N +N/** +N* @brief 设置CCM参数 +N* @param coef: 客制化参数，参考结构体ccm_coef_t +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_set_ccm(ccm_coef_t *ccm); +N +N/** +N* @brief 设置边缘检测算法参数 +N* @param edge_dect_para: 边缘检测算法参数，参考 dsi_tx_edge_dect_t;关闭模块时可以传参NULL +N* @param edge_dect_en: 是否开启边缘检测模块 +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_set_edge_dect(dsi_tx_edge_dect_t *edge_dect_para, bool edge_dect_en); +Xvoid hal_dsi_tx_ctrl_set_edge_dect(dsi_tx_edge_dect_t *edge_dect_para, _Bool edge_dect_en); +N +N/** +N* @brief 设置边缘增强效果算法参数 +N* @param edge_enh_para: 边缘增强算法参数，参考 dsi_tx_edge_enh_t;关闭模块时可以传参NULL +N* @param edge_enh_en: 是否开启边缘增强模块 +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_set_edge_enhance(dsi_tx_edge_enh_t *edge_enh_para, bool edge_enh_en); +Xvoid hal_dsi_tx_ctrl_set_edge_enhance(dsi_tx_edge_enh_t *edge_enh_para, _Bool edge_enh_en); +N +N/** +N* @brief 设置False Color remove算法参数 +N* @param fc_para: false color参数，参考 dsi_tx_fc_t;关闭模块时可以传参NULL +N* @param fc_en: 是否开启false color配置模块 +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_set_fc(dsi_tx_fc_t *fc_para, bool fc_en); +Xvoid hal_dsi_tx_ctrl_set_fc(dsi_tx_fc_t *fc_para, _Bool fc_en); +N +N/** +N* @brief 设置bcs参数 +N* @param bcs_para: 明亮度/对比度/饱和度，参考 dsi_tx_bcs_t;关闭模块时可以传参NULL +N* @param bcs_en: 是否开启bcs配置模块 +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_set_bcs(dsi_tx_bcs_t *bcs_para, bool bcs_en); +Xvoid hal_dsi_tx_ctrl_set_bcs(dsi_tx_bcs_t *bcs_para, _Bool bcs_en); +N +N/** +N* @brief 设置复写颜色 +N* @param R: RGB的R分量 +N* @param G: RGB的G分量 +N* @param B: RGB的B分量 +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_set_overwrite_rgb(uint8_t R, uint8_t G, uint8_t B); +N +N/** +N* @brief 打开overwrite功能 +N* @param enable: true-打开overwrite； false-关闭overwrite +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_overwrite_enable(bool enable); +Xvoid hal_dsi_tx_ctrl_overwrite_enable(_Bool enable); +N +N/** +N* @brief 设置部分显示 +N* @param enable: true-打开partial显示； false-关闭partial显示 +N* @param par_disp_cfg display区域和背景色设置，参考 dsi_tx_par_dis_t; 关闭模块功能时可以传参NULL +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_partial_disp_enable(bool enable, dsi_tx_par_dis_t *par_disp_cfg); +Xvoid hal_dsi_tx_ctrl_partial_disp_enable(_Bool enable, dsi_tx_par_dis_t *par_disp_cfg); +N +N/** +N* @brief 控制TX VPG的输出 +N* @param vpg_en: 使能VPG +N* @param style: VPG的样式 +N* @param vpg_hline_adj: false-正常情况使用，true-VPG显示滚动情况下使用 +N* @attention vpg_hline_adj此参数只能解决带宽余量相差不大的情况，如果带宽需求超出过多，依然无法解决带宽不足引起的VPG显示滚动问题 +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_set_vpg(bool vpg_en, dsi_tx_vpg_style_e style, bool vpg_hline_adj); +Xvoid hal_dsi_tx_ctrl_set_vpg(_Bool vpg_en, dsi_tx_vpg_style_e style, _Bool vpg_hline_adj); +N +N/** +N* @brief 配置TE模式 +N* @param tx_ctrl_handle: dsi tx handle +N* @param te: te mode +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_set_tear_mode(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle, te_mode_e te); +N +N/** +N* @brief 生成一个TE信号 +N* @param None +N* @retval None +N*/ +Nvoid hal_dsi_tx_ctrl_gen_a_tear_signal(void); +N +N/** +N* @brief command mode输出模式下产生一帧数据 +N* @param None +N* @retval None +N*/ +Nbool hal_dsi_tx_ctrl_gen_a_frame(void); +X_Bool hal_dsi_tx_ctrl_gen_a_frame(void); +N +N/** +N* @brief 配置输入输出同步行数,用于调整图像撕裂问题 +N* @param tx_ctrl_handle: dsi tx handle +N* @param line_num: 同步行号,范围1 ~ output height +N* @retval true/false +N*/ +Nbool hal_dsi_tx_ctrl_set_cus_sync_line(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle, uint32_t line_num); +X_Bool hal_dsi_tx_ctrl_set_cus_sync_line(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle, uint32_t line_num); +N +N/** +N* @brief 获取TX当前显示行号 +N* @param tx_ctrl_handle: dsi tx handle +N* @retval 当前显示行号,包括vsa + vbp + vactive + vfp +N*/ +Nuint32_t hal_dsi_tx_ctrl_get_disp_line(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); +N +N#endif //__HAL_DSI_TX_CTRL_H__ +L 18 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "hal_swire.h" +L 1 "..\..\src\sdk\include\hal_swire.h" 1 +N/******************************************************************************* +N* +N* +N* File: hal_swire.h +N* Description： swire HAL层头文件 +N* Version： V0.1 +N* Date： 2021-03-17 +N* Author： jaya +N *******************************************************************************/ +N#ifndef __HAL_SWIRE_H__ +N#define __HAL_SWIRE_H__ +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_device_datatype.h" +N#include "tau_common.h" +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N/** +N* @brief SWIRE初始化 +N* @param 无 +N* @retval 无 +N*/ +Nvoid hal_swire_init(void); +N +N/** +N* @brief SWIRE去初始化 +N* @param 无 +N* @retval 无 +N*/ +Nvoid hal_swire_deinit(void); +N +N/** +N* @brief 配置SWIRE波形 +N* @param start_time：起始时长，单位us +N* @param stop_time：结束时长，单位us，必须大于300us +N* @param high_time：高电平时长，单位us +N* @param low_time：低电平时长，单位us +N* @retval 无 +N*/ +Nvoid hal_swire_set_waveform(uint32_t start_time, uint32_t stop_time, +N uint32_t high_time, uint32_t low_time); +N +N +N/** +N* @brief 配置SWIRE脉冲个数 +N* @param pulse：脉冲数 +N* @retval 无 +N*/ +Nvoid hal_swire_set_pulse(uint32_t pulse); +N +N/** +N* @brief 开关swire输出,不绑定timer的情况下,每次调用hal_swire_set_pulse产生一个swire波形 +N* @param state：开关控制 +N* @retval 无 +N*/ +Nvoid hal_swire_enable(bool state); +Xvoid hal_swire_enable(_Bool state); +N +N/** +N* @brief 配置swire选择的timer +N* @param timer_num_e index：定时器编号 +N* @param uint32_t ms：超时时间 +N* @param repeat :是否重复 +N* @retval 无 +N*/ +Nvoid hal_swire_set_timer(timer_num_e index, uint32_t ms, bool repeat); +Xvoid hal_swire_set_timer(timer_num_e index, uint32_t ms, _Bool repeat); +N +N/** +N* @brief 注册回调函数,每次swire 发送完成后会产生回调 +N* @param cb_func：回调函数地址 +N* @retval 无 +N*/ +Nvoid hal_swire_register_callback(fcb_type cb_func); +N +N#endif /* __HAL_SWIRE_H__ */ +L 19 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "hal_timer.h" +L 1 "..\..\src\sdk\include\hal_timer.h" 1 +N/******************************************************************************* +N* +N* +N* File: hal_timer.h +N* Description： timer HAL层头文件 +N* Version： V0.1 +N* Date： 2021-03-16 +N* Author： jaya +N *******************************************************************************/ +N#ifndef __HAL_TIMER_H__ +N#define __HAL_TIMER_H__ +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_device_datatype.h" +N#include "tau_common.h" +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N/** +N* @brief 指定定时器初始化 +N* @param index：实例序号(0~3)，参考枚举类型timer_num_e +N* @retval None +N*/ +Nvoid hal_timer_init(timer_num_e index); +N +N/** +N* @brief 指定定时器反初始化 +N* @param index：实例序号(0~3)，参考枚举类型timer_num_e +N* @retval None +N*/ +Nvoid hal_timer_deinit(timer_num_e index); +N +N/** +N* @brief 启动指定定时器 +N* @param index：实例序号(0~3)，参考枚举类型timer_num_e +N* @param ms：超时时间，单位ms。由于应用场景一般是ms级别的，应用开发不需要计数具体时针数， +N 故直接输入时间，在接口内部换算成时钟数进行寄存器设置。 +N* @param cb_func：回调函数地址，不需要则填NULL +N* @param data：回调函数的参数地址，不需要则填NULL +N* @retval None +N*/ +Nvoid hal_timer_start(timer_num_e index, uint32_t ms, fcb_type cb_func, void *data); +N +N/** +N* @brief 启动指定定时器 +N* @param index：实例序号(0~3)，参考枚举类型timer_num_e +N* @param us：超时时间，单位us。由于应用场景一般是us级别的，应用开发不需要计数具体时针数， +N 故直接输入时间，在接口内部换算成时钟数进行寄存器设置。 +N* @param cb_func：回调函数地址，不需要则填NULL +N* @param data：回调函数的参数地址，不需要则填NULL +N* @retval None +N*/ +Nvoid hal_timer_start_ex(timer_num_e index, uint32_t us, fcb_type cb_func, void *data); +N +N/** +N* @brief 停止指定定时器 +N* @param index：实例序号(0~3)，参考枚举类型timer_num_e +N* @retval None +N*/ +Nvoid hal_timer_stop(timer_num_e index); +N +N/** +N* @brief 设置定时器是否循环超时 +N* @param index：实例序号(0~3)，参考枚举类型timer_num_e +N* @param bool enable：循环超时使能 +N* @retval None +N*/ +Nvoid hal_timer_set_repeat(timer_num_e index, bool repeat); +Xvoid hal_timer_set_repeat(timer_num_e index, _Bool repeat); +N +N/** +N* @brief 获取指定指示器状态 +N* @param index：实例序号(0~3)，参考枚举类型timer_num_e +N* @retval 参考timer_status_e +N*/ +Ntimer_status_e hal_timer_get_status(timer_num_e index); +N +N#endif /* __HAL_TIMER_H__ */ +L 20 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "hal_system.h" +L 1 "..\..\src\sdk\include\hal_system.h" 1 +N/******************************************************************************* +N* +N* +N* File: hal_system.h +N* Description hal 通用系统接口头文件 +N* Version V0.1 +N* Date 2021-05-21 +N* Author lzy +N *******************************************************************************/ +N#ifndef __HAL_SYSTEM_H__ +N#define __HAL_SYSTEM_H__ +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_common.h" +N#include "hal_gpio.h" +N#include "tau_log.h" +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/** +N* @brief 系统时钟配置 +N*/ +Ntypedef enum +N{ +N HAL_SYSCLK_80M = 80000000, +N HAL_SYSCLK_100M = 100000000, +N HAL_SYSCLK_150M = 150000000 +N} hal_system_clk_e; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N +N/** +N* @brief system 初始化 +N* @param sysclk:系统时钟 +N* @retval none +N*/ +Nvoid hal_system_init(hal_system_clk_e sysclk); +N +N/** +N* @brief mcu进入idle模式,等待中断唤醒 +N* @param disable_systick: 进入idle时是否关闭systick(退出idle 恢复systick) +N* @retval none +N*/ +Nvoid hal_system_idle_mode(bool disable_systick); +Xvoid hal_system_idle_mode(_Bool disable_systick); +N +N/** +N* @brief 注册systick回调函数 +N* @param cb_func：回调函数地址 +N* @retval 无 +N*/ +Nvoid hal_system_register_systick_cb(fcb_type cb_func); +N +N/** +N* @brief 启动sys tickt +N* @param ms: sys tickt 间隔, 范围1-10ms +N* @retval true/false +N*/ +Nbool hal_system_enable_systick(uint8_t ms); +X_Bool hal_system_enable_systick(uint8_t ms); +N +N/** +N* @brief 获取systickt +N* @param none +N* @retval 当前systickt值 +N*/ +Nbool hal_system_disable_systick(void); +X_Bool hal_system_disable_systick(void); +N +N/** +N* @brief 获取systickt +N* @param none +N* @retval 当前systickt值 +N*/ +Nuint32_t hal_system_get_tick(void); +N +N/** +N* @brief reset chip +N* @param none +N* @retval none +N*/ +Nvoid hal_system_reset_chip(void); +N +N/** +N* @brief 获取上位机设置的debug state(debug only) +N* @param none +N* @retval debug state +N*/ +Nuint32_t hal_system_get_debug_state(void); +N +N/** +N* @brief clear debug state(debug only) +N* @param none +N* @retval none +N*/ +Nvoid hal_system_clear_debug_state(void); +N +N/** +N* @brief 更新MCU时钟 +N* @param sysclk:系统时钟 +N* @retval true/false +N*/ +Nbool hal_system_updata_sysclk(hal_system_clk_e sysclk); +X_Bool hal_system_updata_sysclk(hal_system_clk_e sysclk); +N +N#endif //__HAL_SYSTEM_H__ +L 21 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "hal_gpio.h" +N#include "test_cfg_global.h" +L 1 "..\..\src\app\test_cfg_global.h" 1 +N/******************************************************************************* +N* +N* File: test_cfg_global.h +N* Description： 测试用例全局配置头文件 +N* Version： V0.1 +N* Date： 2021-05-01 +N* Author： kevin +N *******************************************************************************/ +N +N#ifndef __TEST_GLOBAL_CONFIG_H__ +N#define __TEST_GLOBAL_CONFIG_H__ +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N/* 模块demo 宏定义 */ +N#define _MODULE_DEMO_ENABLE 0 +N#define _MODULE_DEMO_TIMER_EN 0 +N#define _MODULE_DEMO_DSI_TX_EN 0 +N#define _MODULE_DEMO_DSI_RX_EN 0 +N#define _MODULE_DEMO_PWM_EN 0 +N#define _MODULE_DEMO_SWIRE_EN 0 +N#define _MODULE_DEMO_WDG_EN 0 +N#define _MODULE_DEMO_GPIO_EN 0 +N#define _MODULE_DEMO_I2C_EN 0 +N#define _MODULE_DEMO_SPI_EN 0 +N#define _MODULE_DEMO_PWR_EN 0 +N/* ap demo 宏定义 */ +N#define _DEMO_GOOGLE_P8P_EN 1 +N +N +N#if _DEMO_GOOGLE_P8P_EN +X#if 1 +N #include "p8p_demo.h" +N#endif +N#endif +N +L 23 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "hal_pwr.h" +L 1 "..\..\src\sdk\include\hal_pwr.h" 1 +N/******************************************************************************* +N* +N* +N* File: hal_pwr.h +N* Description： pwr hal层头文件 +N* Version： V0.1 +N* Date： 2023-07-21 +N* Author： lyw +N *******************************************************************************/ +N#ifndef __HAL_PWR_H__ +N#define __HAL_PWR_H__ +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_device_datatype.h" +N#include "tau_common.h" +N#include "hal_gpio.h" +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N/** +N* @brief IC主供电电源选择 +N*/ +Ntypedef enum +N{ +N PWR_SEL_IOV18 = 0, /* IC选择IOV18主供电(默认值) */ +N PWR_SEL_TP18 = 1, /* IC选择TP18主供电 */ +N PWR_SEL_VCC = 2, /* IC选择VCC主供电 */ +N PWR_SEL_VDD13CP = 3, /* IC选择VDD13CP外接电源主供电*/ +N} pwr_main_power_sel_e; +N +N/** +N* @brief Sleep mode 供电模式 +N*/ +Ntypedef enum +N{ +N PWR_SLEEP_IN_NON = 0, /* Sleep Mode期间无外部供电(默认值) */ +N PWR_SLEEP_IN_TP18 = 1, /* Sleep Mode期间TP18有电,其他电源掉电或不存在 */ +N PWR_SLEEP_IN_VCC = 2, /* Sleep Mode期间VCC有电,其他电源掉电或不存在 */ +N PWR_SLEEP_IN_VCC_TP18 = 3, /* Sleep Mode期间TP18与VCC有电,其他电源掉电或不存在 */ +N PWR_SLEEP_IN_IOV18 = 4, /* Sleep Mode期间IOV18有电,其他电源掉电或不存在 */ +N PWR_SLEEP_IN_IOV18_TP18 = 5, /* Sleep Mode期间IOV18与TP18有电,其他电源掉电或不存在 */ +N PWR_SLEEP_IN_IOV18_VCC = 6, /* Sleep Mode期间IOV18与VCC有电,其他电源掉电或不存在 */ +N PWR_SLEEP_IN_IOV18_VCC_TP18 = 7, /* Sleep Mode期间IOV18、TP18、VCC均有电,其他电源掉电或不存在 */ +N} pwr_sleep_power_sel_e; +N +N/** +N* @brief sleep mode 唤醒沿配置 +N*/ +Ntypedef enum +N{ +N WUP_RISING_EDGE = 2, /* 上升沿唤醒 */ +N WUP_FALLING_EDGE = 3 /* 下降沿唤醒 */ +N} pwr_wakeup_trigger_e; +N +N/** +N* @brief 软件启动原因 +N*/ +Ntypedef enum +N{ +N RF_POWER_ON = 0, /* Power On,正常上电 */ +N RF_CORE_RST = 1, /* 软件reset, 调用NVIC_SystemReset产生reset */ +N RF_WDT_RST = 2, /* WDT reset */ +N RF_CHIP_RST = 3, /* Chip reset,调用hal_system_reset_chip产生的reset */ +N RF_APRSTN_WAKEUP = 4, /* deep sleep mode 下AP_RSTN reset */ +N RF_TDINT_WAKEUP = 5 /* deep sleep mode 下TD_INT reset */ +N} pwr_reset_flag_e; +N +N/** +N* @brief pwr sleep mode type +N* 不同sleep mode具体应用场景见《PWR说明文档》 +N*/ +Ntypedef enum +N{ +N PWR_NORMAL_SLEEP_MODE = 0, /* 待机下需要处理外设(I2C)等事件使用,调用hal_pwr_enter_normal_sleep_mode 进入,hal_pwr_exit_sleep_mode退出 */ +N PWR_STOP_SLEEP_MODE = 1, /* 待机下需要通过任意GPIO唤醒时使用此模式,进入之前关闭所有模块以及MCU,通过hal_pwr_set_stop_sleep_wakeup_pin 注册GPIO中唤醒源,调用hal_pwr_enter_stop_sleep_mode 进入,hal_pwr_exit_sleep_mode退出 */ +N PWR_DEEP_SLEEP_MODE = 2 /* 待机下只需要通过AP RSTN跟TD INT引脚唤醒使用时使用此模式,调用hal_pwr_enter_deep_sleep_mode 唤醒后重启,通过hal_pwr_get_reset_flag确定唤醒源 */ +N} pwr_sleep_mode_e; +N +N/*! @brief HV LDO输出电压配置*/ +Ntypedef enum _pwr_hv_ldo_e +N{ +N HV_LDO_0 = 0, /*1.20V*/ +N HV_LDO_1 = 1, /*1.26V*/ +N HV_LDO_2 = 2, /*1.32V*/ +N HV_LDO_3 = 3, /*1.38V*/ +N HV_LDO_4 = 4, /*1.44V*/ +N HV_LDO_5 = 5, /*1.50V*/ +N HV_LDO_6 = 6, /*1.56V*/ +N HV_LDO_7 = 7, /*1.62V*/ +N HV_LDO_8 = 8, /*1.68V*/ +N HV_LDO_9 = 9, /*1.74V*/ +N HV_LDO_10 = 10, /*1.80V*/ +N HV_LDO_11 = 11, /*1.86V*/ +N HV_LDO_12 = 12, /*2.04V*/ +N HV_LDO_13 = 13, /*2.46V*/ +N HV_LDO_14 = 14, /*3.00V*/ +N HV_LDO_15 = 15, /*3.30V*/ +N} pwr_hv_ldo_e; +N +N/*! @brief LDO 13S输出电压配置*/ +Ntypedef enum _pwr_ldo_13s_e +N{ +N LDO_13S_0 = 0, /*1.22V*/ +N LDO_13S_1 = 1, /*1.25V*/ +N LDO_13S_2 = 2, /*1.27V*/ +N LDO_13S_3 = 3, /*1.30V*/ +N LDO_13S_4 = 4, /*1.33V*/ +N LDO_13S_5 = 5, /*1.37V*/ +N LDO_13S_6 = 6, /*1.40V*/ +N LDO_13S_7 = 7, /*1.43V*/ +N} pwr_ldo_13s_e; +N +N/*! @brief LDO 18S输出电压配置*/ +Ntypedef enum _pwr_ldo_18s_e +N{ +N LDO_18S_0 = 0, /*1.61V*/ +N LDO_18S_1 = 1, /*1.64V*/ +N LDO_18S_2 = 2, /*1.67V*/ +N LDO_18S_3 = 3, /*1.70V*/ +N LDO_18S_4 = 4, /*1.74V*/ +N LDO_18S_5 = 5, /*1.77V*/ +N LDO_18S_6 = 6, /*1.80V*/ +N LDO_18S_7 = 7, /*1.83V*/ +N} pwr_ldo_18s_e; +N +N/*! @brief PWR PVD index */ +Ntypedef enum +N{ +N PVD_IOVCC = 3, +N PVD_VCI = 15, +N} pwr_pvd_index_e; +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N/** +N* @brief IC主供电选择,如果是配置vcc主供电，可通过hal_pwr_get_vcc_power_ready获取电源状态 +N* 注:上电只能配置一次,不可随意切换 +N* @param power_sel 主供电选择,见枚举描述 +N* @retval none +N*/ +Nvoid hal_pwr_set_main_power(pwr_main_power_sel_e power_sel); +N +N/** +N* @brief 获取VCC电源稳定状态,使用hal_pwr_set_main_power切换电源后,通过此接口获取电源稳定状态 +N* eg: 使用hal_pwr_set_main_power切换至VCC主供电,在VCC电源接口上电之前,此接口返回值为false +N* @param None +N* @retval true-电源切换完成 false-电源未切换完成 +N*/ +Nbool hal_pwr_get_vcc_power_ready(void); +X_Bool hal_pwr_get_vcc_power_ready(void); +N +N/** +N* @brief 配置VCC开关,芯片启动默认打开VCC CP,不存在VCC的情况下可关闭 +N* @param enable: true:打开CP, false:关闭CP +N* @retval none +N*/ +Nvoid hal_pwr_set_vcc_enable(bool enable); +Xvoid hal_pwr_set_vcc_enable(_Bool enable); +N +N/** +N* @brief sleep mode 期间电源情况配置 +N* 调用sleep mode之前配置,根据配置情况在sleep mode自动切换电源 +N* exit sleep mode后切换回hal_pwr_set_main_power的电源 +N* @param powerin =000 息屏期间状态，IOV18掉电0，VCC掉电0，TP18也掉电0； +N* @retval none +N*/ +Nvoid hal_pwr_set_sleep_mode_power(pwr_sleep_power_sel_e power_sel); +N +N/** +N* @brief 进入normal sleep mode 模式（详细使用方法见《PWR说明文档》） +N* 待机下需要处理外设(I2C)等事件使用,图像通路关闭,MCU&外设正常运行 +N* 调用hal_pwr_exit_sleep_mode退出 +N* @param none +N* @retval bool true/false +N*/ +Nbool hal_pwr_enter_normal_sleep_mode(void); +X_Bool hal_pwr_enter_normal_sleep_mode(void); +N +N/** +N* @brief 进入stop sleep mode 模式（详细使用方法见《PWR说明文档》） +N* 待机下需要通过任意GPIO唤醒时使用此模式，进入之前关闭所有模块,通过hal_pwr_set_stop_sleep_wakeup_pin 注册GPIO中唤醒源。 +N* 调用此接口后MCU会停止运行,等待中断唤醒后该函数才返回,调用hal_pwr_exit_sleep_mode真正退出stop sleep mode +N* @param none +N* @retval io_pad_e:唤醒接口 +N*/ +Nio_pad_e hal_pwr_enter_stop_sleep_mode(void); +N +N/** +N* @brief 注册 stop sleep mode 唤醒IO （详细使用方法见文档） +N* @param pad ：Pin name +N* @param trig：唤醒触发模式 +N* @retval true/false +N*/ +Nbool hal_pwr_set_stop_sleep_wakeup_pin(io_pad_e pad, pwr_wakeup_trigger_e trig); +X_Bool hal_pwr_set_stop_sleep_wakeup_pin(io_pad_e pad, pwr_wakeup_trigger_e trig); +N +N/** +N* @brief 进入deep sleep mode 模式, 等待AP_RSTN 或者TD_INT 唤醒 +N* 待机下只需要通过AP RSTN跟TD INT引脚唤醒使用时使用此模式，唤醒后重启,通过hal_pwr_get_reset_flag确定唤醒源 +N* 注意, 如果需要使用deep sleep mode,TD INT引脚不能悬空,必须有上拉或者下拉保证确定电平,否则会导致误唤醒 +N* @param polarity true:上升沿唤醒 false:下降沿唤醒 +N* @retval none +N*/ +Nvoid hal_pwr_enter_deep_sleep_mode(pwr_wakeup_trigger_e ap_rstn_trig, pwr_wakeup_trigger_e td_int_trig); +N +N/** +N* @brief 退出sleep mode, normal/stop sleep mode都需要通过此接口退出 +N* @param none +N* @retval true/false +N*/ +Nbool hal_pwr_exit_sleep_mode(void); +X_Bool hal_pwr_exit_sleep_mode(void); +N +N/** +N* @brief 获取系统复位原因 +N* @param none +N* @retval reset flag,见pwr_reset_flag_e +N*/ +Npwr_reset_flag_e hal_pwr_get_reset_flag(void); +N +N/** +N* @brief 打开ELVCC作为供电电源 +N* @param none +N* @retval +N*/ +Nvoid hal_pwr_elvcc_ldo_en(bool enable); +Xvoid hal_pwr_elvcc_ldo_en(_Bool enable); +N +N +N/** +N* @brief +N* @param HV LDO输出电压配置 +N =0000：1.20V， +N =0001：1.26V， +N =0010：1.32V， +N =0011：1.38V， +N =0100：1.44V， +N =0101：1.50V， +N =0110：1.56V， +N =0111：1.62V， +N =1000：1.68V， +N =1001：1.74V， +N =1010：1.80V， +N =1011：1.86V， +N =1100：2.04V， +N =1101：2.46V， +N =1110：3.00V， +N =1111：3.30V +N* @retval none +N*/ +Nvoid hal_pwr_elvcc_vol_set(pwr_hv_ldo_e voltage); +N +N/** +N* @brief +N* @param LDO18_S模块使能控制，=0关闭，默认关闭；=1开启 +N* @retval none +N*/ +Nvoid hal_pwr_ldo18s_en(bool enable); +Xvoid hal_pwr_ldo18s_en(_Bool enable); +N +N +N/** +N* @brief +N* @param LDO18_S输出电压配置， +N 000=1.61V +N 001=1.64V +N 010=1.67V +N 011=1.70V +N 100=1.74V +N 101=1.77V +N 110=1.80V +N 111=1.83V +N* @retval none +N*/ +Nvoid hal_pwr_ldo18s_set(pwr_ldo_18s_e voltage); +N +N/** +N* @brief +N* @param LDO13_S模块使能控制，=0关闭，默认关闭；=1开启 +N* @retval none +N*/ +Nvoid hal_pwr_ldo13s_en(bool enable); +Xvoid hal_pwr_ldo13s_en(_Bool enable); +N +N +N/** +N* @brief +N* @param LDO13_S输出电压配置， +N 000=1.22V, +N 001=1.25V, +N 010=1.27V, +N 011=1.30V, +N 100=1.33V， +N 101=1.37V， +N 110=1.40V， +N 111=1.43V +N* @retval none +N*/ +Nvoid hal_pwr_ldo13s_set(pwr_ldo_13s_e voltage); +N +N/** +N* @brief PVD(电源检查)开关接口, +N* PVD默认均为打开,注意!电源切换(如主供电切换,进出sleep mode)必须打开PVD! +N* @param index: PVD选择 IOVCC/VCI +N* @param enable: PVD开关 +N* @retval none +N*/ +Nvoid hal_pwr_set_pvd(pwr_pvd_index_e index, bool enable); +Xvoid hal_pwr_set_pvd(pwr_pvd_index_e index, _Bool enable); +N +N/** +N* @brief 使能TP18给VDD18供电 +N* @warning info!!! 1:进入休眠的电源要选择TP18供电 eg： hal_pwr_set_sleep_mode_power(PWR_SLEEP_IN_TP18); +N* @warning info!!! 2:唤醒之后，关闭改使能 eg： hal_pwr_sw_tp18_en(DISENABLE); +N* @param enable: +N* @retval none +N*/ +Nvoid hal_pwr_sw_tp18_en(bool enable); +Xvoid hal_pwr_sw_tp18_en(_Bool enable); +N +N +N +N#endif /* __HAL_PWR_H__ */ +L 24 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "hal_pwm.h" +L 1 "..\..\src\sdk\include\hal_pwm.h" 1 +N/******************************************************************************* +N* +N* +N* File: hal_pwm.h +N* Description： pwm HAL层头文件 +N* Version： V0.1 +N* Date： 2021-03-17 +N* Author： jaya +N *******************************************************************************/ +N#ifndef __HAL_PWM_H__ +N#define __HAL_PWM_H__ +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_device_datatype.h" +N#include "tau_common.h" +N +N/******************************************************************************* +N* 2.Global constant and macro definitions using #define +N*******************************************************************************/ +N +N/******************************************************************************* +N* 3.Global structures, unions and enumerations using typedef +N*******************************************************************************/ +N +N/******************************************************************************* +N* 4.Global variable extern declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Global function prototypes +N*******************************************************************************/ +N/** +N* @brief pwm 初始化 +N* @param frequency: PWM 频率 < 30000 (30K) +N* @param duty_step: 占空比调试阶数,与硬件相关,不能超过硬件限制（建议配置255） +N 最大阶数 = (1000000000/130)/frequency，常见如下 +N frequency, max step(最大step可配置) +N { 30000, 255 } +N { 4000, 1923} +N { 3000, 2564} +N* @retval true/false +N*/ +Nbool hal_pwm_init(uint32_t frequency, uint32_t duty_step); +X_Bool hal_pwm_init(uint32_t frequency, uint32_t duty_step); +N +N/** +N* @brief pwm 启动停止控制 +N* @param enable: 启动/停止 +N* @retval none +N*/ +Nvoid hal_pwm_enable(bool enable); +Xvoid hal_pwm_enable(_Bool enable); +N +N/** +N* @brief pwm 设置占空比 +N* @param duty_ratio: 占空比,范围为0 - duty_step(hal_pwm_init配置的参数) +N* @retval none +N*/ +Nvoid hal_pwm_set_duty(uint32_t duty_ratio); +N +N/** +N* @brief pwm 配置从elvcc直接输出背光电源 +N* @param enable: ELVCC输出启停 +N* @retval none +N*/ +Nbool hal_pwm_set_elvcc_output(bool enable); +X_Bool hal_pwm_set_elvcc_output(_Bool enable); +N +N/** +N* @brief 配置elvcc PWM 驱动背光能力,范围 0 - 15, capactiy为15时驱动能力最强,ELVCC输出电流最大 +N* @param capacity: 0 - 15,hal_pwm_set_elvcc_output配置时会恢复默认值15 +N* @retval none +N*/ +Nvoid hal_pwm_set_elvcc_capacity(uint8_t capacity); +N +N/** +N* @brief pwm 去初始化 +N* @param none +N* @retval true/false +N*/ +Nbool hal_pwm_deinit(void); +X_Bool hal_pwm_deinit(void); +N +N#endif /* __HAL_PWM_H__ */ +L 25 "..\..\src\app\P8P\p8p_demo.c" 2 +N#include "hal_crc.h" +L 1 "..\..\src\sdk\include\hal_crc.h" 1 +N/******************************************************************************* +N* +N* +N* File: hal_crc.h +N* Description: hal crc ͷ�ļ� +N* Version: V0.1 +N* Date: 2023-07-27 +N* Author: zzf +N *******************************************************************************/ +N#ifndef __HAL_CRC_H +N#define __HAL_CRC_H +N +N#ifdef __cplusplus +Sextern "C" { +N#endif +N +N/******************************************************************************* +N* 1.Included files +N*******************************************************************************/ +N#include "tau_device_datatype.h" +N#include "tau_common.h" +N +N/******************************************************************************* +N* 2.Exported constant and macro definitions +N*******************************************************************************/ +N +N/******************************************************************************* +N* 3.Exported structures, unions and enumerations +N*******************************************************************************/ +N/** +N* @brief crc calculation unit structure +N*/ +Ntypedef struct +N{ +N uint32_t polynomial_value; +N uint32_t initial_seed_value; +N crc_protocol_type_e crc_protocol; +N crc_fxor_function_e crc_foxr; +N crc_reversal_type_e crc_reversal_in; +N crc_reversal_type_e crc_reversal_out; +N} crc_ctrl_handle_t; +N +N/** +N* @brief crc dma callback function define +N*/ +Ntypedef void (*crc_dma_callback)(uint32_t crc_result); +N +N/******************************************************************************* +N* 4.Exported variable declarations +N*******************************************************************************/ +N +N/******************************************************************************* +N* 5.Exported function declarations +N*******************************************************************************/ +N/** +N* @brief The initialization for CRC calculation unit +N* @param crc_ctrl_handle: configuration parameters in initialization +N* @retval true or false +N**/ +Nbool hal_crc_init(const crc_ctrl_handle_t *crc_ctrl_handle); +X_Bool hal_crc_init(const crc_ctrl_handle_t *crc_ctrl_handle); +N +N/** +N* @brief The initialization for CRC calculation unit +N* @param None +N* @retval true or false +N**/ +Nbool hal_crc_deinit(void); +X_Bool hal_crc_deinit(void); +N +N/** +N* @brief Reset CRC calculation unit and DR to CRCR_INIT value +N* @param None +N* @retval true or false +N**/ +Nbool hal_crc_reset(void); +X_Bool hal_crc_reset(void); +N +N/** +N* @brief Get the result of CRC calculation uint +N* @param buffer_address: 16-bit or 32-bit crc calculate buffer address +N* @param buffer_length: the length of buffer +N* @retval 32-bit crc calculate result +N**/ +Nuint32_t hal_crc_cal(const void *buffer_address, uint32_t buffer_length); +N +N/** +N* @brief initial DMA transfer +N* @param crc_ctrl_handle: configuration parameters in initialization +N* @param buffer_address: 16-bit or 32-bit crc calculate buffer address +N* @param buffer_length: the length of buffer(0~65535) +N* @param cb_func: dma interrupt callback function to get the result of crc calculation +N* @retval true or false +N**/ +Nbool hal_crc_dma_init(const crc_ctrl_handle_t *crc_ctrl_handle, crc_dma_callback cb_func, const void *buffer_address, uint16_t buffer_length); +X_Bool hal_crc_dma_init(const crc_ctrl_handle_t *crc_ctrl_handle, crc_dma_callback cb_func, const void *buffer_address, uint16_t buffer_length); +N +N/** +N* @brief deinitial DMA transfer +N* @param None +N* @retval true or false +N**/ +Nbool hal_crc_dma_deinit(void); +X_Bool hal_crc_dma_deinit(void); +N +N/** +N* @brief start DMA transfer +N* @param None +N* @retval true or false +N**/ +Nbool hal_crc_dma_start(void); +X_Bool hal_crc_dma_start(void); +N +N#ifdef __cplusplus +S} +N#endif +N +N#endif /* __HAL_CRC_H */ +N +N/***************** (C) COPYRIGHT ISP Systems (R) END OF FILE ******************/ +L 26 "..\..\src\app\P8P\p8p_demo.c" 2 +N +N#ifdef LOG_TAG +N#undef LOG_TAG +N#endif +N#define LOG_TAG "p8p" +N +N#if _DEMO_GOOGLE_P8P_EN +X#if 1 +N +N/******************** FEATURE开关 ********************/ +N#define TOUCH_ENABLE false /* Touch转换开关 */ +N#define RX_START_WITHOUT_RST true /* 不等待AP RESET直接启动RX,仅作为调试使用 */ +N#define RX_WAIT_TEAR_ON false /* 等待AP_TEAR_ON */ +N#define RX_RESOLUTION_CHANGE_ENABLE true /* 支持分辨率切换开关, AP存在分辨率切换时需要打开 */ +N#define RX_READ_HW_ACK false /* AP DCS读命令使用硬件回复 */ +N#define TX_START_AFTER_APRST false /* 等待AP_reset 后做Panel初始化, 用于热拔插电源不稳定导致初始化失败 */ +N#define TX_USE_CMD_MODE false /* command mode输出开关 配置为True时需要把TD TE与 AP TE 接一起*/ +N#define TX_CMD_MODE_WITHOUT_TE false /* 屏端TE直接输出给AP,Scaler不看TE信号,AP每输入一帧输出一帧(C2C 60Hz->60Hz) */ +N#define AP_SWIRE_OUTPUT true /* swire信号输出,OLED项目配置 */ +N#define ANALOG_PWM_OUTPUT false /* 模拟PWM 调光开关 */ +N#define SHARE_FLASH_ENABLE false /* 共享flash开关 */ +N/*****************************************************/ +N +N/******************** 输出屏幕选择 ********************/ +N#define AMOLED_ICNA3508 1 /* 4lane FHD Panel */ +N/*****************************************************/ +N +N/****************** 系统相关参数配置 ******************/ +N#define MAIN_POWER_SELECT PWR_SEL_VCC /* 主供电电源选择 */ +N#define SLEEP_MODE_POWER PWR_SLEEP_IN_IOV18 //PWR_SLEEP_IN_TP18 /* 息屏电源选择 */ +N#define SLEEP_MODE_SELECT PWR_DEEP_SLEEP_MODE //PWR_DEEP_SLEEP_MODE //PWR_NORMAL_SLEEP_MODE // /* sleep mode 配置 */ +N#define SWIRE_DEFAULT_PULSE 31 // 41 //31 /* SWIRE 波形配置 */ +N#define PWM_FREQUENCY 30000 /* PWM输出频率30Khz */ +N#define PWM_DUTY_STEP 255 /* PWM调光阶数255阶 */ +N/*****************************************************/ +N +N/********************RX 基本参数配置*******************/ +N//AP MIPI数据信息 +N/* 输入分辨率 */ +N#define INPUT_WIDTH 1344 +N#define INPUT_HEIGHT 2992 +N/* 输入 MIPI lane rate,需要正确配置,可50M step调整 */ +N#define INPUT_MIPI_LANE_RATE 1600000000 +N/* 输入图像格式 */ +N#define INPUT_COLOR_MODE DSI_RGB888 +N/* 输出数据格式(DSI_DATA_CMD_MODE , DSI_DATA_VIDEO_MODE) */ +N#define INPUT_DATA_MODE DSI_DATA_CMD_MODE +N/* 输入mipi lane数量(DSI_RX_LANE_x x为1-4) */ +N#define INPUT_MIPI_LANE_NUM DSI_LANE_4 +N/* 输入为video mode 时数据格式 */ +N#define INPUT_VIDEO_MODEL DSI_NONBURST_EVENT +N/* 输入虚拟通道(0-3) */ +N#define INPUT_VC DSI_VC_0 +N/* 输入的帧率(60/90/120/144Hz) */ +N#define INPUT_FRAME_RATE DSI_FRAME_RATE_120HZ +N/* 输入数据是否DSC压缩 */ +N#define INPUT_COMPRESS true +N/*****************************************************/ +N +N/********************TX 基本参数配置*******************/ +N#if AMOLED_ICNA3508 +X#if 1 +N//almoled NT37280输出MIPI数据信息 +N/* 输出分辨率配置 */ +N#define OUTPUT_WIDTH 1080 +N#define OUTPUT_HEIGHT 2400 +N/* 输出虚拟通道(0-3) */ +N#define OUTPUT_VC DSI_VC_0 +N/* 输出mipi lane数量(DSI_RX_LANE_x x为1-4) */ +N#define OUTPUT_LANE_NUMBER DSI_LANE_4 +N/* 输出数据格式(DSI_DATA_CMD_MODE , DSI_DATA_VIDEO_MODE) */ +N#if TX_USE_CMD_MODE +X#if 0 +S#define OUTPUT_DATA_MODE DSI_DATA_CMD_MODE +N#else +N#define OUTPUT_DATA_MODE DSI_DATA_VIDEO_MODE +N#endif +N/* 输出为video mode时的数据格式 */ +N#define OUTPUT_VIDEO_MODEL DSI_BURST_MODE +N/* 输出 VSA */ +N#define OUTPUT_VSA 1 //1 +N/* 输出 VBP */ +N#define OUTPUT_VBP 19 //19 +N/* 输出 VBP */ +N#define OUTPUT_VFP 12 //12 +N/* 输出 VSA */ +N#define OUTPUT_HSA 1 +N/* 输出 HBP */ +N#define OUTPUT_HBP 27 +N/* 输出 HFP */ +N#define OUTPUT_HFP 77 +N/* 初始化模式命令传输类型 LP/HS */ +N#define TX_INIT_TYPE DSI_CMD_TX_LP +N#endif +N/******************************************************/ +N +N#if TOUCH_ENABLE +X#if 0 +S#include "app_tp_transfer.h" +N#endif +N +N/* 全局handle */ +Nstatic hal_dsi_rx_ctrl_handle_t *g_rx_ctrl_handle = NULL; +Xstatic hal_dsi_rx_ctrl_handle_t *g_rx_ctrl_handle = 0; +Nstatic hal_dsi_tx_ctrl_handle_t *g_tx_ctrl_handle = NULL; +Xstatic hal_dsi_tx_ctrl_handle_t *g_tx_ctrl_handle = 0; +N +N/* 屏初始化完成标志位 */ +Nstatic bool panel_display_done = false; +Xstatic _Bool panel_display_done = 0; +Nstatic bool sg_system_resume = false; +Xstatic _Bool sg_system_resume = 0; +Nstatic bool sg_system_suspend = false; +Xstatic _Bool sg_system_suspend = 0; +Nstatic bool sg_exit_idle_mode_flag = false; +Xstatic _Bool sg_exit_idle_mode_flag = 0; +N +Nstatic volatile bool g_resolution_change = false; +Xstatic volatile _Bool g_resolution_change = 0; +Nstatic uint32_t pps_renew_flag = 0; +Nstatic uint32_t pwr_rst_flag = 0; +N +N#if RX_WAIT_TEAR_ON +X#if 0 +Sstatic bool sg_ap_set_tear_on = false; +N#endif +N#if TX_START_AFTER_APRST +X#if 0 +Sstatic bool sg_tx_start_in_process = false; +N#endif +N +Nuint16_t rd_51_val,rd_51_val2; +N +N/* AP reset 回调函数声明 */ +Nstatic void ap_rstn_pull_high_cb(void *data); +Nstatic void ap_rstn_pull_down_cb(void *data); +Nstatic void app_mipi_rx_start_cb(void *data); +N +N +N/*************************DCS 命令处理函数 BEGIN*************************/ +N#if RX_READ_HW_ACK +X#if 0 +S/** +S* @brief 配置AP硬件回读 +S* @param none +S* @retval none +S*/ +Sstatic void app_set_dcs_hw_ack() +S{ +S hal_dsi_rx_ctrl_set_auto_ack(g_rx_ctrl_handle, HAL_RX_QRESP_CODE0, DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, 0xFA, 1, 0x00); +S} +N#endif +N/** +N* @brief ap 读回调函数 +N* @param handler：rx_ctrl_handle +N* dcs_packet: dcs 命令 +N* @retval true/false +N*/ +Nstatic bool ap_dcs_read(uint8_t data_type, uint8_t dcs_cmd, uint8_t param) +Xstatic _Bool ap_dcs_read(uint8_t data_type, uint8_t dcs_cmd, uint8_t param) +N{ +N if (dcs_cmd == 0x04) +N { +N hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +N DSI_ACK_DT_DCS_LONG_RESPONSE, +N DSI_VC_0, +N 3, 0x0A,0x60,0x20); +N } +N else if (dcs_cmd == 0xa1) +N { +N hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +N DSI_ACK_DT_DCS_LONG_RESPONSE, +N DSI_VC_0, +N 13, 0x0C,0x21,0x0C,0xC6,0x01,0xF3,0xAA,0x11,0x06,0x2B,0x25,0x21,0xF6); +N } +N else if (dcs_cmd == 0xDA) +N { +N hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +N DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, +N DSI_VC_0, +N 1, 0x0A); +N } +N else if (dcs_cmd == 0xDB) +N { +N hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +N DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, +N DSI_VC_0, +N 1, 0x68); +N } +N else if (dcs_cmd == 0xDC) +N { +N hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +N DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, +N DSI_VC_0, +N 1, 0x07); +N } +N else if (dcs_cmd == 0xD6) +N { +N hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +N DSI_ACK_DT_DCS_LONG_RESPONSE, +N DSI_VC_0, +N 5, 0xF0, 0xEA, 0x85, 0x61, 0x86); +N } +N else +N { +N uint32_t return_size = hal_dsi_rx_ctrl_get_max_ret_size(g_rx_ctrl_handle); +N hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +N DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, +N DSI_VC_0, +N 1, 0); +N TAU_LOGD("r[%x] [%d] err!!!!!!\n", dcs_cmd, return_size); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "r[%x] [%d] err!!!!!!\n", "p8p", 221,dcs_cmd, return_size); } while (0); +N } +N +N// TAU_LOGD("r %x\n",dcs_cmd); +N return true; +X return 1; +N} +N +Nuint8_t pps[128] = {0x11,0x00,0x00,0x89,0x30,0x80,0x0B,0xB0, +N 0x05,0x40,0x00,0xBB,0x02,0xA0,0x02,0xA0, +N 0x02,0x00,0x02,0x50,0x00,0x20,0x14,0x39, +N 0x00,0x09,0x00,0x0C,0x00,0x85,0x00,0x70, +N 0x18,0x00,0x10,0xF0,0x03,0x0C,0x20,0x00, +N 0x06,0x0B,0x0B,0x33,0x0E,0x1C,0x2A,0x38, +N 0x46,0x54,0x62,0x69,0x70,0x77,0x79,0x7B, +N 0x7D,0x7E,0x01,0x02,0x01,0x00,0x09,0x40, +N 0x09,0xBE,0x19,0xFC,0x19,0xFA,0x19,0xF8, +N 0x1A,0x38,0x1A,0x78,0x1A,0xB6,0x2A,0xF6, +N 0x2B,0x34,0x2B,0x74,0x3B,0x74,0x6B,0xF4, +N 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; +Nuint8_t pps_fhd[128] = {0x11,0x00,0x00,0x89,0x30,0x80,0x08,0xC4, +N 0x03,0xF0,0x00,0xBB,0x01,0xF8,0x01,0xF8, +N 0x02,0x00,0x01,0xF8,0x00,0x20,0x11,0x82, +N 0x00,0x07,0x00,0x0C,0x00,0x85,0x00,0x96, +N 0x18,0x00,0x10,0xF0,0x03,0x0C,0x20,0x00, +N 0x06,0x0B,0x0B,0x33,0x0E,0x1C,0x2A,0x38, +N 0x46,0x54,0x62,0x69,0x70,0x77,0x79,0x7B, +N 0x7D,0x7E,0x01,0x02,0x01,0x00,0x09,0x40, +N 0x09,0xBE,0x19,0xFC,0x19,0xFA,0x19,0xF8, +N 0x1A,0x38,0x1A,0x78,0x1A,0xB6,0x2A,0xF6, +N 0x2B,0x34,0x2B,0x74,0x3B,0x74,0x6B,0xF4, +N 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; +N +N +N#if RX_RESOLUTION_CHANGE_ENABLE +X#if 1 +N/* PPS update callback 用于分辨率切换case */ +Nstatic bool pps_update_handle(uint8_t *pps, uint8_t size, uint32_t pic_width, uint32_t pic_height) +Xstatic _Bool pps_update_handle(uint8_t *pps, uint8_t size, uint32_t pic_width, uint32_t pic_height) +N{ +N// for (uint8_t i =0; i< 128; i++) +N// { +N// TAU_LOGD("PPS_0A[i]=[0x%02X]\n",i,pps[i]); +N// } +N +N /* AVDD 上电, 用于解决息屏开屏PPS不更新问题 */ +N // hal_gpio_set_output_data(IO_PAD_AP_PWMEN, IO_LVL_HIGH); +N if (pic_width != g_rx_ctrl_handle->base_info.src_w || pic_height != g_rx_ctrl_handle->base_info.src_h) +N { +N hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_USER_MODE); +N /* PPS Update 且分辨率发生变化 */ +N g_rx_ctrl_handle->base_info.src_w = pic_width; +N g_rx_ctrl_handle->base_info.src_h = pic_height; +N /* 注意部分基板更新PPS前不发 Compression Mode Command的情况 */ +N g_rx_ctrl_handle->compress_en = true; +X g_rx_ctrl_handle->compress_en = 1; +N g_resolution_change = true; +X g_resolution_change = 1; +N if(pic_width > 720) +N { +N g_tx_ctrl_handle->base_info.src_w = pic_width; +N g_tx_ctrl_handle->base_info.src_h = pic_height; +N } +N// hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x22); // ic刷黑处理 +N// delayMs(5); +N +N// hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps, 128); +N hal_dsi_rx_ctrl_toggle_resolution(g_rx_ctrl_handle); +N // hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x13); // 退出刷黑 +N } +N hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); +N //TAU_LOGD("PPS Update[%d][%d] [%d][%d]\n", pic_width, pic_height, g_rx_ctrl_handle->base_info.src_w, g_rx_ctrl_handle->base_info.src_h); +N return true; +X return 1; +N} +N#endif +N +N +N +N/** +N* @brief ap display on处理函数 +N* @param handler：rx_ctrl_handle +N* dcs_packet: dcs 命令 +N* @retval true/false +N*/ +Nstatic bool ap_dcs_set_display_on(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +Xstatic _Bool ap_dcs_set_display_on(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +N{ +N +N if(g_resolution_change) +N { +N hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps_fhd, 128); +N hal_dsi_rx_ctrl_toggle_resolution(g_rx_ctrl_handle); +N g_resolution_change = false; +X g_resolution_change = 0; +N TAU_LOGD("pps_update_1\r\n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "pps_update_1\r\n", "p8p", 316); } while (0); +N } +N// TAU_LOGD("disp on"); +N// if (start_display_on == false){ +N hal_dsi_tx_ctrl_write_cmd(0x05, 0, 2, 0x29); +N// } +N TAU_LOGD("disp on \n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "disp on \n", "p8p", 322); } while (0); +N return true; +X return 1; +N} +N +N +Nvoid REG_51_OFF_output(uint16_t REG_51_VALUE) +N{ +N uint8_t i; +N uint16_t REG_51; +N +N +N +N for (i =0; i< 50; i++) +N { +N REG_51=REG_51_VALUE*(50-i)/50; +N hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, REG_51>>8, REG_51&0x00FF);; +N delayMs(17); +N // TAU_LOGD("reg_51_off[0x%04X]\n",REG_51); +N } +N +N} +N +N/** +N* @brief ap display off处理函数 +N* @param handler：rx_ctrl_handle +N* dcs_packet: dcs 命令 +N* @retval true/false +N*/ +Nstatic bool ap_dcs_set_display_off(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +Xstatic _Bool ap_dcs_set_display_off(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +N{ +N#if ANALOG_PWM_OUTPUT +X#if 0 +S hal_pwm_enable(false); +N#endif +N +N TAU_LOGD("disp off %d\n", panel_display_done); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "disp off %d\n", "p8p", 356,panel_display_done); } while (0); +N return true; +X return 1; +N} +N +N +N/***************************************************************************** +N*GPIO发送swire波形 +N*flag: =0, SWIRE=0; =1,仅发送SWIRE信号; =2, 先置高再发SWIRE信号 +N*num: 发几个脉冲 +N*注意FLAG=1时无GPIO初始化!!!!!! +N*****************************************************************************/ +Nvoid Gpio_swire_output(uint8_t flag, uint8_t num) +N{ +N uint8_t ii; +N +N if (flag) +N { +N if (flag ==2) +N { +N hal_gpio_init_output(IO_PAD_AP_SWIRE, IO_LVL_HIGH); +N delayMs(2); +N } +N for (ii =0; ii< num; ii++) +N { +N hal_gpio_set_output_data(IO_PAD_AP_SWIRE, IO_LVL_LOW); +N delayUs(10); +N hal_gpio_set_output_data(IO_PAD_AP_SWIRE, IO_LVL_HIGH); +N delayUs(9); +N } +N } +N else +N { +N hal_gpio_init_output(IO_PAD_AP_SWIRE, IO_LVL_LOW); +N } +N} +N +N +N +N/** +N* @brief ap enter sleep mode处理函数 +N* @param handler：rx_ctrl_handle +N* dcs_packet: dcs 命令 +N* @retval true/false +N*/ +Nstatic bool ap_dcs_set_enter_sleep_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +Xstatic _Bool ap_dcs_set_enter_sleep_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +N{ +N hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x28); +N hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_STOP_MODE); +N delayMs(10); +N +N // delayMs(10); +N#if AP_SWIRE_OUTPUT +X#if 1 +N /* Swire close */ +N hal_swire_enable(false); +X hal_swire_enable(0); +N delayMs(10); +N hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x10); +N delayMs(20); +N /* AVDD_EN close*/ +N hal_gpio_set_output_data(IO_PAD_AP_PWMEN, IO_LVL_LOW); +N#endif +N /* Wait AP reset down*/ +N hal_gpio_set_ap_reset_int(ENABLE, ap_rstn_pull_down_cb, DETECT_LOW_LVL); +N // sg_system_suspend=true; +N TAU_LOGD("enter sleep mode\n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "enter sleep mode\n", "p8p", 419); } while (0); +N// delayMs(500); +N return true; +X return 1; +N} +N +N/** +N* @brief ap exit sleep mode处理函数 +N* @param handler：rx_ctrl_handle +N* dcs_packet: dcs 命令 +N* @retval true/false +N*/ +Nstatic bool ap_dcs_set_exit_sleep_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +Xstatic _Bool ap_dcs_set_exit_sleep_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +N{ +N//#if AP_SWIRE_OUTPUT +N// /* AVDD 上电, 用于解决息屏开屏PPS不更新问题 */ +N// hal_gpio_set_output_data(IO_PAD_AP_PWMEN, IO_LVL_HIGH); +N//#endif +N +N#if TX_START_AFTER_APRST +X#if 0 +S if (panel_display_done == false) +S { +S sg_tx_start_in_process = true; +S } +N#endif +N +N TAU_LOGD("exit sleep mode \n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "exit sleep mode \n", "p8p", 444); } while (0); +N +N return true; +X return 1; +N} +N +N +N +N/** +N* @brief 调光处理函数 +N* @param handler：rx_ctrl_handle +N* dcs_packet: dcs 命令 +N* @retval true/false +N*/ +N +Nuint8_t value_51H,value_51L; +Nstatic bool reg53_E8_fg=0; +Xstatic _Bool reg53_E8_fg=0; +Nstatic bool ap_dcs_set_backlight(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +Xstatic _Bool ap_dcs_set_backlight(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +N{ +N //手机端0xC4~CEB(2043) 映射0x9FF +N#if 0 +S value_51H = dcs_packet->packet_param[0]; +S value_51L = dcs_packet->packet_param[1]; +S hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, value_51H, value_51L); +N#else +N rd_51_val = dcs_packet->packet_param[0]; +N rd_51_val <<=8; +N rd_51_val |= dcs_packet->packet_param[1]; +N +N// rd_51_val2 = (rd_51_val-0x04)*2555/2043+0x04; //0x9FF max +W "..\..\src\app\P8P\p8p_demo.c" 473 16 pointless comparison of unsigned integer with zero +N if((rd_51_val >=0x00)&&(rd_51_val <= 0xFFF) ){ +N +N rd_51_val2 = (rd_51_val-0xC4)*2555/3889+0x04; //0x9FF max +N +N } +N else if(rd_51_val >0xFFF) { +N +N rd_51_val2 = 0x9FF; +N +N } +N hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, rd_51_val2>>8, rd_51_val2&0x00FF); +N#endif +N // TAU_LOGD("AP_51[0x%04X],IC_51[0x%04X]\n",rd_51_val,rd_51_val2); +N return true; +X return 1; +N} +N +N#if RX_WAIT_TEAR_ON +X#if 0 +S/** +S* @brief ap set tear on 处理函数 +S* @param handler：rx_ctrl_handle +S* dcs_packet: dcs 命令 +S* @retval true/false +S*/ +Sstatic bool ap_dcs_set_tear_on(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +S{ +S TAU_LOGD("ap_set_tear_on\n"); +S sg_ap_set_tear_on = true; +S if (panel_display_done == false) +S { +S TAU_LOGD("gen a tear\n"); +S hal_dsi_tx_ctrl_gen_a_tear_signal(); +S } +S else +S { +S hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); +S } +S return true; +S} +S +S/** +S* @brief ap set tear off 处理函数 +S* @param handler：rx_ctrl_handle +S* dcs_packet: dcs 命令 +S* @retval true/false +S*/ +Sstatic bool ap_dcs_set_tear_off(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +S{ +S TAU_LOGD("ap_set_tear_off \n"); +S sg_ap_set_tear_on = false; +S hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_USER_MODE); +S return true; +S} +N#endif +N +N/** +N* @brief 护眼模式回调函数 +N* @param rx_ctrl_handle: dsi rx handle; +N* dcs packet: dcs_packet +N* @retval true/false +N*/ +Nstatic bool ap_dcs_set_exit_idle_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +Xstatic _Bool ap_dcs_set_exit_idle_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +N{ +N sg_exit_idle_mode_flag = true; +X sg_exit_idle_mode_flag = 1; +N hal_dsi_rx_ctrl_set_hw_cmd_filter(g_rx_ctrl_handle, HAL_RX_DCS_FILTER_B, 0x2C, 0x2C); +N TAU_LOGD("exit idle mode,skip 0x2C\n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "exit idle mode,skip 0x2C\n", "p8p", 537); } while (0); +N return true; +X return 1; +N} +N +N#define TE_TIMER TIMER_NUM2 +Nstatic void soft_te_timer_cb(void *data) +N{ +N /* +N S8 的屏接的是TP1.8V, AC 启动后需要等到TP1.8 起来后再初始化屏, 所以在TP 起来前需要通过软件产生TE给手机，避免手机卡死 +N */ +N// if (panel_display_done == false) +N// { +N hal_dsi_tx_ctrl_gen_a_tear_signal(); +N hal_timer_start(TE_TIMER, 8, soft_te_timer_cb, NULL); +X hal_timer_start(TIMER_NUM2, 8, soft_te_timer_cb, 0); +N// } +N// else +N// { +N// hal_dsi_rx_ctrl_set_hw_tear_mode(g_rx_ctrl_handle); +N// } +N} +N +Nstatic void soft_te_timer_init() +N{ +N// TAU_LOGD("soft_te_timer_init"); +N hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle,TE_USER_MODE); +N hal_timer_init(TE_TIMER); +X hal_timer_init(TIMER_NUM2); +N hal_timer_start(TE_TIMER, 1, soft_te_timer_cb, NULL); +X hal_timer_start(TIMER_NUM2, 1, soft_te_timer_cb, 0); +N} +N +N/** +N* @brief 帧率切换处理函数 +N* @param handler：rx_ctrl_handle +N* dcs_packet: dcs 命令 +N* @retval true/false +N*/ +Nstatic bool ap_dcs_set_frame_change(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +Xstatic _Bool ap_dcs_set_frame_change(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +N{ +N if (dcs_packet->param_length == 1) +N { +N if (dcs_packet->packet_param[0] == 0x18) +N { +N // hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle,TE_USER_MODE); +N hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); +N } +N else +N { +N // soft_te_timer_init(); +N hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_120HZ_MODE); +N } +N } +N // TAU_LOGD("frame_change %x ,size %d, data %d\n", dcs_packet->dcs_command, dcs_packet->param_length, dcs_packet->packet_param[0]); +N return true; +X return 1; +N} +N +Nstatic bool ap_set_FPS_53(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +Xstatic _Bool ap_set_FPS_53(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +N{ +N uint8_t value_53 =0; +N +N value_53 = dcs_packet->packet_param[0]; +N +N if(value_53 == 0x30) // AP FPS ON +N { +N +N hal_dsi_tx_ctrl_write_cmd( 0x39, 0, 4, 0x97, 0x11, 0xCF, 0xFF); // DDIC FPS ON +N +N } +N else if(value_53 == 0x20) // AP FPS OFF +N { +N +N hal_dsi_tx_ctrl_write_cmd( 0x39, 0, 4, 0x97, 0x00, 0xCF, 0xFF); // DDIC FPS OFF +N +N +N } +N +N// TAU_LOGD("B1[%x]", value_b1); +N return true; +X return 1; +N} +N +N/*************************DCS 命令处理函数 END*************************/ +N +N/* 客制化DCS command 处理函数表格 */ +Nstatic const hal_dcs_execute_entry_t g_cus_rx_dcs_execute_table[] = +N{ +N {DCS_SET_DISPLAY_ON, ap_dcs_set_display_on, false}, +X {DCS_SET_DISPLAY_ON, ap_dcs_set_display_on, 0}, +N {DCS_SET_DISPLAY_OFF, ap_dcs_set_display_off, true}, +X {DCS_SET_DISPLAY_OFF, ap_dcs_set_display_off, 1}, +N {0x51, ap_dcs_set_backlight, false}, +X {0x51, ap_dcs_set_backlight, 0}, +N {0x53, ap_set_FPS_53, true}, //FPS Switch: P6P-0xB1; P7P-0x53 +X {0x53, ap_set_FPS_53, 1}, +N {DCS_ENTER_SLEEP_MODE, ap_dcs_set_enter_sleep_mode, true}, +X {DCS_ENTER_SLEEP_MODE, ap_dcs_set_enter_sleep_mode, 1}, +N {DCS_EXIT_SLEEP_MODE, ap_dcs_set_exit_sleep_mode, true}, +X {DCS_EXIT_SLEEP_MODE, ap_dcs_set_exit_sleep_mode, 1}, +N {0x60, ap_dcs_set_frame_change, true}, +X {0x60, ap_dcs_set_frame_change, 1}, +N#if RX_WAIT_TEAR_ON +X#if 0 +S {DCS_SET_TEAR_ON, ap_dcs_set_tear_on, true}, +S {DCS_SET_TEAR_OFF, ap_dcs_set_tear_off, true}, +N#endif +N {0, NULL, false} //{0,NULL,false} 数组最后一个固定成员，作为table结尾的判断标准 +X {0, 0, 0} +N}; +N +N/** +N* @brief panel reset +N* @param none +N* @retval none +N*/ +Nstatic void app_tx_panel_reset(void) +N{ +N#if SHARE_FLASH_ENABLE +X#if 0 +S hal_flash_share_mode(true); +N#endif +N hal_gpio_set_output_data(IO_PAD_TD_RSTN, IO_LVL_HIGH); +N delayMs(10); +N hal_gpio_set_output_data(IO_PAD_TD_RSTN, IO_LVL_LOW); +N delayMs(10); +N hal_gpio_set_output_data(IO_PAD_TD_RSTN, IO_LVL_HIGH); +N delayMs(40); +N} +N +N#if PANEL_INIT_CODE_ARRAY +X#if 1 +Nstatic void send_panel_init_code(uint32_t size, uint8_t * data) +N{ +N uint32_t data_offeset = 0; +N uint8_t data_type; +N uint8_t vc; +N uint8_t data_size; +N uint8_t * p_data; +N +N while(data_offeset < size) +N { +N data_type = data[data_offeset]; +N vc = data[data_offeset + 1]; +N data_size = data[data_offeset + 2]; +N p_data = &data[data_offeset + 3]; +N hal_dsi_tx_ctrl_write_array_cmd(data_type, vc, data_size, p_data); +N data_offeset = data_offeset + data_size + 3; +N delayUs(50); +N } +N} +N +Nconst uint8_t panel_init_code[] = { +N#if 1 +N0x39,0,3,0x9C,0xA5,0xA5, +N0x39,0,3,0xFD,0x5A,0x5A, +N0x39,0,2,0x9F,0x0F, +N0x39,0,2,0xB3,0x00, +N0x39,0,2,0xD7,0x11, +N0x39,0,2,0x9F,0x01, +N0x39,0,4,0xB2,0x5A,0x04,0xAF, +N0x39,0,36,0xB3,0x00,0xBA,0x00,0x14,0x0C,0x22,0x00,0xBA,0x30,0x14,0x2C,0x00,0x00,0xBA,0x90,0x14,0x4C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xBA,0x00,0x14,0x0C,0x44,0x1C,0x1C,0x1C,0x1C,0x1C, +N0x39,0,19,0xCD,0x06,0x1F,0x1F,0x06,0x00,0x09,0x00,0x96,0x1F,0x03,0x28,0x00,0x96,0x1F,0x09,0x46,0x00,0x96, +N0x39,0,2,0xD0,0x01, +N0x39,0,3,0xE2,0x46,0x20, +N0x39,0,3,0xEA,0x04,0x0B, +N0x39,0,9,0xEE,0x40,0x38,0x28,0x28,0x28,0x28,0x28,0xC2,//add for ICNA5608 +N0x39,0,2,0x9F,0x02, +N0x39,0,26,0xB2,0x00,0xC9,0x32,0x10,0x11,0x12,0x12,0x00,0x08,0x78,0x21,0x11,0x14,0x13,0x11,0x11,0x11,0x11,0x11,0x11,0x11,0x21,0x21,0x11,0x1A, +N0x39,0,14,0xB4,0x00,0x00,0x8C,0x00,0x00,0x00,0x00,0x00,0x25,0x25,0x25,0x25,0x25, +N0x39,0,7,0xB5,0x00,0x30,0x30,0x30,0x30,0x2A, +N0x39,0,20,0xB6,0x05,0x00,0x00,0x11,0x11,0x11,0x1C,0x08,0x1C,0x21,0x21,0x21,0x21,0x21,0x21,0x21,0x21,0x21,0x21, +N0x39,0,17,0xB7,0x00,0x00,0x00,0x00,0x00,0x15,0x00,0x06,0x06,0x03,0x06,0x06,0x03,0x06,0x06,0x03, +N0x39,0,14,0xB8,0x00,0x00,0x00,0x73,0x28,0x73,0x28,0x73,0x28,0x73,0x28,0x73,0x28, +N0x39,0,9,0xB9,0x00,0x00,0x50,0x00,0x00,0x0F,0x0F,0x00, +N0x39,0,14,0xBA,0x0E,0xFF,0xFF,0xFF,0x00,0x54,0x00,0x44,0x04,0x44,0x04,0x04,0x00, +N0x39,0,26,0xBB,0x00,0x5A,0x91,0x91,0x5A,0x00,0x5A,0x91,0x91,0x5A,0x00,0x5A,0x91,0x91,0x5A,0x00,0x5A,0x91,0x91,0x5A,0x00,0x3C,0x78,0x78,0x3C, +N0x39,0,5,0xBE,0x5B,0x17,0x04,0x5B, +N0x39,0,17,0xBF,0x0C,0x8F,0xFF,0x10,0x00,0x07,0x00,0x0A,0x01,0x20,0x00,0x00,0x00,0x00,0x00,0x00, +N0x39,0,17,0xC1,0x05,0x21,0x22,0x1D,0x1F,0x1E,0x20,0x01,0x30,0x31,0x32,0x33,0x3D,0x3D,0x3D,0x3D, +N0x39,0,17,0xC2,0x05,0x21,0x22,0x1D,0x1F,0x1E,0x20,0x01,0x30,0x31,0x32,0x33,0x3D,0x3D,0x3D,0x3D, +N0x39,0,10,0xC3,0x11,0x60,0x00,0x40,0x00,0x40,0x00,0x00,0x00, +N0x39,0,26,0xC4,0x00,0x0C,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x1F,0x1F,0x00,0x00,0x0D,0x00,0x00,0x00,0x00, +N0x39,0,17,0xD2,0x00,0x00,0x13,0x00,0x00,0x13,0x00,0x00,0x17,0x00,0x00,0x17,0x00,0x00,0x17,0x00, +N0x39,0,14,0xC7,0x00,0x04,0x04,0x04,0x04,0x00,0x04,0x04,0x04,0x04,0x00,0x04,0x04, +N0x39,0,14,0xC8,0x00,0xB1,0xB1,0xB1,0xB1,0x00,0xB1,0xB1,0xB1,0xB1,0x00,0xB1,0xB1, +N0x39,0,27,0xC6,0x00,0x00,0x0f,0x00,0x00,0x11,0x00,0x00,0x00,0x90,0x00,0x00,0x00,0x00,0x08,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x55,0x01,0x01,0x00, +N0x39,0,27,0xCB,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x92,0x90,0x92,0x00,0x90,0x92,0x90,0x92,0x00,0x90,0x92, +N0x39,0,27,0xCC,0x00,0x76,0xff,0x76,0xff,0x00,0x76,0xff,0x76,0xff,0x00,0x76,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N0x39,0,19,0xD7,0x4D,0xC3,0x20,0x7A,0x33,0x00,0x02,0x02,0x00,0xF7,0xF7,0xF4,0xA9,0xA9,0xAE,0xF0,0x00,0x00, +N0x39,0,41,0xD8,0x00,0x04,0x76,0x22,0xFF,0x00,0x04,0x76,0x22,0xFF,0x00,0x04,0x76,0x22,0xFF,0x00,0x04,0x76,0x22,0xFF,0x00,0x04,0x76,0x22,0xFF,0x90,0x76,0xFF,0x90,0x76,0xFF,0x90,0x76,0xFF,0x90,0x76,0xFF,0x90,0x76,0xFF, +N0x39,0,12,0xD9,0x10,0x40,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10, +N0x39,0,4,0xE0,0x00,0x00,0x60, +N0x39,0,6,0xE1,0x43,0x00,0x11,0x60,0x0D, +N0x39,0,51,0xE2,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24, +N0x39,0,4,0xED,0x00,0x01,0x80, +N0x39,0,18,0xEE,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x88,0x88,0x29,0x00,0x00,0x00,0x00, +N0x39,0,6,0xEF,0x00,0x85,0x88,0x87,0x87, +N0x39,0,2,0x9F,0x03, +N0x39,0,33,0xB2,0x11,0x00,0x00,0x89,0x30,0x80,0x09,0x60,0x04,0x38,0x00,0x0C,0x02,0x1C,0x02,0x1C,0x02,0x00,0x02,0x0E,0x00,0x20,0x01,0x1F,0x00,0x07,0x00,0x0C,0x08,0xBB,0x08,0x7A, +N0x39,0,33,0xB3,0x18,0x00,0x10,0xF0,0x03,0x0C,0x20,0x00,0x06,0x0B,0x0B,0x33,0x0E,0x1C,0x2A,0x38,0x46,0x54,0x62,0x69,0x70,0x77,0x79,0x7B,0x7D,0x7E,0x01,0x02,0x01,0x00,0x09,0x40, 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+N0x39,0,43,0xB4,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00, +N0x39,0,43,0xB5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00, +N0x39,0,12,0xBE,0x00,0x1F,0xFF,0x13,0x91,0x0F,0x04,0x00,0x24,0x80,0xFF, +N0x39,0,2,0x9F,0x0B, //Middle circle setting REG 0xBE +N0x39,0,10,0xB2,0x01,0x3F,0x3F,0x0F,0x3F,0x0F,0x5F,0x0F,0x0F, +N0x39,0,49,0xB9,0x32,0x00,0x00,0x00,0x00,0x00,0x6B,0x54,0x24,0x1C,0xB0,0x14,0xC8,0x5C,0x24,0x1C,0xB0,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N0x39,0,49,0xBA,0x32,0x00,0x00,0x00,0x00,0x00,0x54,0x69,0x24,0x1C,0xB0,0x14,0xC8,0x5C,0x24,0x1C,0xB0,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N0x39,0,49,0xBC,0x32,0x00,0x00,0x00,0x00,0x00,0x4b,0x4b,0x24,0x1C,0xB0,0x14,0xD1,0x65,0x24,0x1C,0xB0,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N0x39,0,49,0xBE,0x32,0x00,0x00,0x00,0x00,0x00,0x25,0x25,0x20,0x1C,0x33,0x00,0x00,0x00,0x00,0x25,0x25,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N0x39,0,20,0xC6,0x8F,0x04,0x04,0x04,0x04,0xFF,0xFF,0xFF,0xFF,0x00,0x22,0x22,0x22,0x22,0x00,0x1E,0x1E,0x1E,0x1E, +N0x39,0,20,0xC7,0x0F,0x04,0x04,0x04,0x04,0xFF,0xFF,0xFF,0xFF,0x00,0x22,0x22,0x22,0x22,0x00,0x1E,0x1E,0x1E,0x1E, +N0x39,0,16,0xC8,0xF9,0x05,0x05,0xB0,0xE0,0xB0,0x50,0xBA,0xF0,0xB0,0xE0,0xB0,0x20,0xD0,0x50, +N0x39,0,2,0x9F,0x0D, +N0x39,0,16,0xB2,0x25,0x10,0x21,0x01,0x02,0x10,0x00,0x00,0x16,0x10,0x00,0x00,0x01,0xAA,0x90, +N0x39,0,2,0xB3,0xB0, +N0x39,0,13,0xB5,0x00,0x24,0x07,0x01,0x00,0x00,0x00,0x00,0x20,0x04,0xEE,0x21, +N0x39,0,4,0xB6,0x02,0x12,0x22, +N0x39,0,5,0xB7,0x20,0xF0,0xC0,0xE0, +N0x39,0,13,0xB8,0x20,0xF0,0xC0,0xE0,0x20,0xF0,0xC0,0xE0,0x20,0xF0,0xC0,0xE0, +N0x39,0,5,0xB9,0x01,0x01,0x01,0x01, +N0x39,0,3,0xBA,0x00,0x00, +N0x39,0,2,0xBB,0x01, +N0x39,0,21,0xBC,0x0F,0xFF,0x07,0xFF,0x03,0x33,0x01,0x47,0x01,0x46,0x00,0xCD,0x00,0x66,0x00,0x3A,0x00,0x14,0x00,0x08, +N0x39,0,6,0xBD,0x02,0x00,0x02,0x06,0x5B, +N0x39,0,12,0xC7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2A,0x00, +N0x39,0,2,0x48,0x03, //0x03：120hz 0x23:60hz +N0x39,0,1,0x11, +N0x39,0,3,0x51,0x00,0x0F, +N0x39,0,2,0x53,0xE0, +N0x39,0,1,0x35, +N//0x39,0,1,0x29, +N#endif +N#if 0 //AMOLED_ICNA3508_gamma_correct --old version +S0x39,0,3,0x9C,0xA5,0xA5, +S0x39,0,3,0xFD,0x5A,0x5A, +S0x39,0,2,0x9F,0x0F, +S0x39,0,2,0xB3,0x00, +S0x39,0,2,0xD7,0x11, +S0x39,0,2,0x9F,0x01, +S0x39,0,4,0xB2,0x5A,0x04,0xAF, +S0x39,0,36,0xB3,0x00,0xBA,0x00,0x14,0x0C,0x22,0x00,0xBA,0x30,0x14,0x2C,0x00,0x00,0xBA,0x90,0x14,0x4C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xBA,0x00,0x14,0x0C,0x44,0x1C,0x1C,0x1C,0x1C,0x1C, +S0x39,0,19,0xCD,0x06,0x1F,0x1F,0x06,0x00,0x09,0x00,0x96,0x1F,0x03,0x28,0x00,0x96,0x1F,0x09,0x46,0x00,0x96, +S0x39,0,2,0xD0,0x01, +S0x39,0,3,0xE2,0x46,0x20, +S0x39,0,3,0xEA,0x04,0x0B, +S0x39,0,9,0xEE,0x40,0x38,0x28,0x28,0x28,0x28,0x28,0xC2,//add for ICNA5608 +S0x39,0,2,0x9F,0x02, +S0x39,0,26,0xB2,0x00,0xC9,0x32,0x10,0x11,0x12,0x12,0x00,0x08,0x78,0x21,0x11,0x14,0x13,0x11,0x11,0x11,0x11,0x11,0x11,0x11,0x21,0x21,0x11,0x1A, +S0x39,0,14,0xB4,0x00,0x00,0x8C,0x00,0x00,0x00,0x00,0x00,0x25,0x25,0x25,0x25,0x25, +S0x39,0,7,0xB5,0x00,0x30,0x30,0x30,0x30,0x2A, +S0x39,0,20,0xB6,0x05,0x00,0x00,0x11,0x11,0x11,0x1C,0x08,0x1C,0x21,0x21,0x21,0x21,0x21,0x21,0x21,0x21,0x21,0x21, +S//0x39,0,17,0xB7,0x00,0x00,0x00,0x00,0x00,0x15,0x00,0x06,0x06,0x03,0x06,0x06,0x03,0x06,0x06,0x03, +S0x39,0,17,0xB7,0x05,0x00,0x15,0x00,0x00,0x15,0x70,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03, //ver2.0 +S0x39,0,14,0xB8,0x00,0x00,0x00,0x73,0x28,0x73,0x28,0x73,0x28,0x73,0x28,0x73,0x28, +S0x39,0,9,0xB9,0x00,0x00,0x50,0x00,0x00,0x0F,0x0F,0x00, +S0x39,0,14,0xBA,0x0E,0xFF,0xFF,0xFF,0x00,0x54,0x00,0x44,0x04,0x44,0x04,0x04,0x00, +S0x39,0,26,0xBB,0x00,0x5A,0x91,0x91,0x5A,0x00,0x5A,0x91,0x91,0x5A,0x00,0x5A,0x91,0x91,0x5A,0x00,0x5A,0x91,0x91,0x5A,0x00,0x3C,0x78,0x78,0x3C, +S0x39,0,5,0xBE,0x5B,0x17,0x04,0x5B, +S0x39,0,17,0xBF,0x0C,0x8F,0xFF,0x10,0x00,0x07,0x00,0x0A,0x01,0x20,0x00,0x00,0x00,0x00,0x00,0x00, +S0x39,0,17,0xC1,0x05,0x21,0x22,0x1D,0x1F,0x1E,0x20,0x01,0x30,0x31,0x32,0x33,0x3D,0x3D,0x3D,0x3D, +S0x39,0,17,0xC2,0x05,0x21,0x22,0x1D,0x1F,0x1E,0x20,0x01,0x30,0x31,0x32,0x33,0x3D,0x3D,0x3D,0x3D, +S0x39,0,10,0xC3,0x11,0x60,0x00,0x40,0x00,0x40,0x00,0x00,0x00, +S0x39,0,26,0xC4,0x00,0x0C,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x1F,0x1F,0x00,0x00,0x0D,0x00,0x00,0x00,0x00, +S0x39,0,17,0xD2,0x00,0x00,0x13,0x00,0x00,0x13,0x00,0x00,0x17,0x00,0x00,0x17,0x00,0x00,0x17,0x00, +S0x39,0,14,0xC7,0x00,0x04,0x04,0x04,0x04,0x00,0x04,0x04,0x04,0x04,0x00,0x04,0x04, +S0x39,0,14,0xC8,0x00,0xB1,0xB1,0xB1,0xB1,0x00,0xB1,0xB1,0xB1,0xB1,0x00,0xB1,0xB1, +S0x39,0,27,0xC6,0x00,0x00,0x0f,0x00,0x00,0x11,0x00,0x00,0x00,0x90,0x00,0x00,0x00,0x00,0x08,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x55,0x01,0x01,0x00, +S0x39,0,27,0xCB,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x92,0x90,0x92,0x00,0x90,0x92,0x90,0x92,0x00,0x90,0x92, +S0x39,0,27,0xCC,0x00,0x76,0xff,0x76,0xff,0x00,0x76,0xff,0x76,0xff,0x00,0x76,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +S//0x39,0,19,0xD7,0x49,0xC3,0x20,0x7A,0x44,0x00,0x04,0x04,0x00,0xF9,0xF9,0xF4,0xAB,0xA9,0xAE,0xF0,0x00,0x00, +S//0x39,0,19,0xD7,0x4D,0xC3,0x20,0x7A,0x53,0x00,0x66,0x02,0x00,0xCC,0xF7,0xF4,0xCC,0xA9,0xAE,0xF0,0x00,0x00, //功耗高 +S0x39,0,19,0xD7,0x4D,0xC3,0x20,0x7A,0x53,0x00,0x66,0x02,0x00,0xCC,0xF7,0xF4,0xCC,0xA9,0xAE,0xF0,0x00,0x00, +S0x39,0,41,0xD8,0x00,0x04,0x76,0x22,0xFF,0x00,0x04,0x76,0x22,0xFF,0x00,0x04,0x76,0x22,0xFF,0x00,0x04,0x76,0x22,0xFF,0x00,0x04,0x76,0x22,0xFF,0x90,0x76,0xFF,0x90,0x76,0xFF,0x90,0x76,0xFF,0x90,0x76,0xFF,0x90,0x76,0xFF, +S0x39,0,12,0xD9,0x10,0x40,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10, +S0x39,0,4,0xE0,0x00,0x00,0x60, +S0x39,0,6,0xE1,0x43,0x00,0x11,0x60,0x0D, +S0x39,0,51,0xE2,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24, +S0x39,0,4,0xED,0x00,0x01,0x80, +S0x39,0,18,0xEE,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x88,0x88,0x29,0x00,0x00,0x00,0x00, +S0x39,0,6,0xEF,0x00,0x85,0x88,0x87,0x87, +S0x39,0,2,0x9F,0x03, +S0x39,0,33,0xB2,0x11,0x00,0x00,0x89,0x30,0x80,0x09,0x60,0x04,0x38,0x00,0x0C,0x02,0x1C,0x02,0x1C,0x02,0x00,0x02,0x0E,0x00,0x20,0x01,0x1F,0x00,0x07,0x00,0x0C,0x08,0xBB,0x08,0x7A, +S0x39,0,33,0xB3,0x18,0x00,0x10,0xF0,0x03,0x0C,0x20,0x00,0x06,0x0B,0x0B,0x33,0x0E,0x1C,0x2A,0x38,0x46,0x54,0x62,0x69,0x70,0x77,0x79,0x7B,0x7D,0x7E,0x01,0x02,0x01,0x00,0x09,0x40, +S0x39,0,25,0xB4,0x09,0xBE,0x19,0xFC,0x19,0xFA,0x19,0xF8,0x1A,0x38,0x1A,0x78,0x1A,0xB6,0x2A,0xF6,0x2B,0x34,0x2B,0x74,0x3B,0x74,0x6B,0xF4, +S0x39,0,2,0xC0,0x11, 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+S0x39,0,49,0xBA,0x32,0x00,0x00,0x00,0x00,0x00,0x54,0x69,0x24,0x1C,0xB0,0x14,0xC8,0x5C,0x24,0x1C,0xB0,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +S0x39,0,49,0xBC,0x32,0x00,0x00,0x00,0x00,0x00,0x4b,0x4b,0x24,0x1C,0xB0,0x14,0xD1,0x65,0x24,0x1C,0xB0,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +S0x39,0,49,0xBE,0x32,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x20,0x1C,0x33,0x00,0x00,0x00,0x00,0x20,0x20,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +S0x39,0,20,0xC6,0x8F,0x04,0x04,0x04,0x04,0xFF,0xFF,0xFF,0xFF,0x00,0x22,0x22,0x22,0x22,0x00,0x1E,0x1E,0x1E,0x1E, +S0x39,0,20,0xC7,0x0F,0x04,0x04,0x04,0x04,0xFF,0xFF,0xFF,0xFF,0x00,0x22,0x22,0x22,0x22,0x00,0x1E,0x1E,0x1E,0x1E, +S0x39,0,16,0xC8,0xF9,0x05,0x05,0xB0,0xE0,0xB0,0x50,0xBA,0xF0,0xB0,0xE0,0xB0,0x20,0xD0,0x50, +S0x39,0,2,0x9F,0x0D, +S0x39,0,16,0xB2,0x25,0x10,0x21,0x01,0x02,0x10,0x00,0x00,0x16,0x10,0x00,0x00,0x01,0xAA,0x90, +S0x39,0,2,0xB3,0xB0, +S0x39,0,13,0xB5,0x00,0x24,0x07,0x01,0x00,0x00,0x00,0x00,0x20,0x04,0xEE,0x21, +S0x39,0,4,0xB6,0x02,0x12,0x22, +S0x39,0,5,0xB7,0x20,0xF0,0xC0,0xE0, +S0x39,0,13,0xB8,0x20,0xF0,0xC0,0xE0,0x20,0xF0,0xC0,0xE0,0x20,0xF0,0xC0,0xE0, +S0x39,0,5,0xB9,0x01,0x01,0x01,0x01, +S0x39,0,3,0xBA,0x00,0x00, +S0x39,0,2,0xBB,0x01, +S0x39,0,21,0xBC,0x0F,0xFF,0x07,0xFF,0x03,0x33,0x01,0x47,0x01,0x46,0x00,0xCD,0x00,0x66,0x00,0x3A,0x00,0x14,0x00,0x08, +S0x39,0,6,0xBD,0x02,0x00,0x02,0x06,0x5B, +S0x39,0,12,0xC7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2A,0x00, +S0x39,0,2,0x48,0x03, //00 cmd 0x03 vdo +S//// bist mode +S//0x39,0,2,0x9F,0x01, +S////0x39,0,5,0xC6,0x01,0x20,0x18,0x02, +S//0x39,0,3,0xC6,0x03,0x08, +S0x39,0,1,0x11, +S//0x39,0,3,0x51,0x00,0x00, +S0x39,0,2,0x53,0xE0, +S0x39,0,1,0x35, +S//0x39,0,1,0x29, +S +N#endif +N#if DDIC_FPS_SETTING +X#if 1 +N0x39,0,2,0x9F,0x04, +N0x39,0,14,0xB5,0x00,0x17,0x27,0x1B,0x17,0x00,0x75,0x75,0x10,0x3B,0x08,0xA8,0x48, // 0x3B,0x10,0xB8,0x40,(美版ANDROID 13放久过后指纹解会失效) +N//1226 0x3B,0x08,0xA8,0x48(ANDROID 13+++/14+++) 0x3B,0x10,0xA8,0x50(ANDROID 13++/14++) 0x3B,0x00,0xAF,0x58(ANDROID 13++/14+) +N//1225 0x3B,0x08,0xA0,0x48(ANDROID 13+++/14++) 0x3B,0x10,0xA8,0x48(ANDROID 13++/14++) 0x3B,0x10,0xA8,0x4F(ANDROID 13++/14++) 0x3B,0x10,0xA0,0x48(ANDROID 13++/14++) 0x3B,0x10,0xB0,0x4F(ANDROID 13++/14+) , 0x3B,0x10,0xB8,0x4F(ANDROID 13++/14+) 0x3B,0x18,0xB8,0x4F(ANDROID 13++/14) 0x3B,0x08,0x98,0x2F(ANDROID 13++/14-); 0x3B,0x28,0xB8,0x4F(ANDROID 13++/14--); , 0x3B,0x20,0xB0,0x40 (ANDROID 13/14 JP NG) +N//1222 0x2B,0xF0,0x98,0x7F(ALL OK) 0x2B,0xF0,0x98,0x2F (ALL OK 2nd) 0x2B,0xF0,0x98,0x00, (ALL OK 3rd )0x2B,0xF0,0x9F,0x3F 0x2B,0xDF,0x8F,0x4F(ANDROID 12 FAIL ) +N//1214 0x2B,0xFF,0x9F,0x5F 0x2B,0xFF,0xCF,0x5F +N//ANDROID 14 0x2B,0xF0,0x90,0x20 秒解 LAST VERSION 0x3B,0x3F,0xDF,0x6F +N// 1211 fail FOR ALL VERSION 0x3B,0x3F,0xEF,0x6F; 0x3B,0x2F,0xDF,0x5F; 0x3B,0x1F,0xCF,0x4F; 0x3B,0x1F,0xCF,0x4F; 0x3B,0x0F,0xBF,0x3F; 0x2B,0xFF,0xAF,0x3F +N0x39,0,18,0xBE,0x00,0xCF,0xFF,0xFF,0xFF,0x3F,0xFF,0xFF,0xFF,0x3F,0xFF,0xFF,0xFF,0x3F,0xFF,0xFF,0xFF, +N0x39,0,46,0xE9,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0xFF,0x3F,0x3F,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +N0x39,0,28,0xEA,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +N0x39,0,46,0xEB,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0xFF,0x3F,0x3F,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +N0x39,0,28,0xEC,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +N0x39,0,46,0xED,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0xFF,0x3F,0x3F,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +N0x39,0,28,0xEE,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +N0x39,0,10,0xF8,0x1E,0xE0,0xE0,0xE0,0x00,0x18,0x15,0x00,0xE0, +N0x39,0,10,0xF9,0xE1,0x18,0x15,0x00,0xF0,0xF8,0xF0,0xEE,0x00, +N0x39,0,10,0xFA,0x1E,0xE0,0xE0,0xE0,0x00,0x18,0x15,0x00,0xE0, +N0x39,0,2,0x9F,0x05, +N0x39,0,13,0xB4,0x02,0x0F,0x3E,0x00,0x00,0x10,0x06,0x00,0x00,0x02,0x40,0x8D, +N0x39,0,41,0xE6,0x0F,0xFF,0x07,0xFF,0x03,0x33,0x01,0x47,0x01,0x46,0x00,0xCD,0x00,0x66,0x00,0x3A,0x00,0x14,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N0x39,0,31,0xE7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N0x39,0,41,0xE8,0x0F,0xFF,0x0F,0xFF,0x0F,0xFF,0x0F,0xFF,0x0F,0xFF,0x0C,0xF0,0x09,0x71,0x07,0x54,0x04,0x8C,0x03,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N//0x39,0,41,0xE8,0x01,0xFF,0x00,0x1F,0x00,0x2F,0x00,0x1F,0x00,0x1F,0x0C,0xF0,0x09,0x71,0x07,0x54,0x04,0x8C,0x03,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N0x39,0,31,0xE9,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +N +N +N#endif +N}; +N +N#endif +N +N +N/** +N* @brief panel init +N* @param none +N* @retval none +N*/ +Nstatic void app_init_panel(void) +N{ +N /* reset panel*/ +N app_tx_panel_reset(); +N#if PANEL_INIT_CODE_ARRAY +X#if 1 +N send_panel_init_code(sizeof(panel_init_code), (uint8_t *) panel_init_code); +N#endif +N hal_gpio_init_output(IO_PAD_AP_PWMEN, IO_LVL_HIGH); +N delayMs(90); +N#if AP_SWIRE_OUTPUT +X#if 1 +N hal_swire_enable(true); +X hal_swire_enable(1); +N hal_swire_set_pulse(SWIRE_DEFAULT_PULSE); +X hal_swire_set_pulse(31); +N#endif +N// hal_gpio_init_output(IO_PAD_AP_SWIRE, IO_LVL_HIGH); +N// Gpio_swire_output(2, 40); +N +N// TAU_LOGD("Panel init!\n\r"); +N} +N +N#if TX_CMD_MODE_WITHOUT_TE +X#if 0 +S/** +S* @brief MIPI RX事件处理函数,demo code 用于command mode 输出发送数据（模式1） +S* @param event:RX事件 +S* @param data: user data +S* @retval none +S*/ +Sstatic void app_rx_event_cb(hal_rx_event_e event, void *data) +S{ +S if (panel_display_done && event == HAL_RX_LINE_EVENT) +S { +S hal_dsi_tx_ctrl_gen_a_frame(); +S } +S} +N#endif +N +N#if TX_USE_CMD_MODE +X#if 0 +S/** +S* @brief TE引脚作为GPIO 输入回调函数,demo code 用于command mode 输出发送数据（模式2） +S* @param none +S* @retval none +S*/ +Sstatic void app_tx_cmd_panel_te_cb(void *data) +S{ +S if (panel_display_done) +S { +S //delayUs(25); /* 撕裂调试 */ +S hal_dsi_tx_ctrl_gen_a_frame(); +S } +S} +S +S/** +S* @brief 注册屏端TE信号输入引脚回调函数 +S* @param pad :TE输入pad +S* @param trig:触发中断沿配置 +S* @retval none +S*/ +Sstatic void app_tx_cmd_app_init_panel_te_int(io_pad_e pad, sys_cfg_trigger_e trig) +S{ +S /*1.关闭中断*/ +S hal_gpio_ctrl_eint(pad, DISABLE); +S +S /*2.中断初始化*/ +S hal_gpio_init_eint(pad, trig); +S +S /*3.注册回调*/ +S hal_gpio_reg_eint_cb(pad, app_tx_cmd_panel_te_cb); +S +S /*4.使能中断*/ +S hal_gpio_ctrl_eint(pad, ENABLE); +S} +N#endif +N +N/** +N* @brief mipi rx 初始化 +N* @param none +N* @retval none +N*/ +Nstatic void app_mipi_rx_init(void) +N{ +N if (g_rx_ctrl_handle == NULL) +X if (g_rx_ctrl_handle == 0) +N { +N /* 创建rx ctrl handle */ +N g_rx_ctrl_handle = hal_dsi_rx_ctrl_create_handle(); +N } +N /* 配置参数 */ +N g_rx_ctrl_handle->base_info.src_w = INPUT_WIDTH; +X g_rx_ctrl_handle->base_info.src_w = 1344; +N g_rx_ctrl_handle->base_info.src_h = INPUT_HEIGHT; +X g_rx_ctrl_handle->base_info.src_h = 2992; +N g_rx_ctrl_handle->base_info.dst_w = OUTPUT_WIDTH; +X g_rx_ctrl_handle->base_info.dst_w = 1080; +N g_rx_ctrl_handle->base_info.dst_h = OUTPUT_HEIGHT; +X g_rx_ctrl_handle->base_info.dst_h = 2400; +N g_rx_ctrl_handle->base_info.src_frate = INPUT_FRAME_RATE; +X g_rx_ctrl_handle->base_info.src_frate = DSI_FRAME_RATE_120HZ; +N g_rx_ctrl_handle->base_info.src_mode = INPUT_DATA_MODE; +X g_rx_ctrl_handle->base_info.src_mode = DSI_DATA_CMD_MODE; +N g_rx_ctrl_handle->base_info.dst_mode = OUTPUT_DATA_MODE; +X g_rx_ctrl_handle->base_info.dst_mode = DSI_DATA_VIDEO_MODE; +N g_rx_ctrl_handle->rx_color_mode = INPUT_COLOR_MODE; +X g_rx_ctrl_handle->rx_color_mode = DSI_RGB888; +N g_rx_ctrl_handle->rx_lanes = INPUT_MIPI_LANE_NUM; +X g_rx_ctrl_handle->rx_lanes = DSI_LANE_4; +N g_rx_ctrl_handle->rx_nonburst_models = INPUT_VIDEO_MODEL; /* 可不配置 */ +X g_rx_ctrl_handle->rx_nonburst_models = DSI_NONBURST_EVENT; +N g_rx_ctrl_handle->compress_en = INPUT_COMPRESS; +X g_rx_ctrl_handle->compress_en = 1; +N g_rx_ctrl_handle->rx_hsclk_rate = INPUT_MIPI_LANE_RATE; +X g_rx_ctrl_handle->rx_hsclk_rate = 1600000000; +N g_rx_ctrl_handle->cus_dcs_entry_table = g_cus_rx_dcs_execute_table; /* 注册 DCS处理列表 */ +N g_rx_ctrl_handle->rx_dcs_read_entry = ap_dcs_read; /* 注册dsc read 回调函数,可选,此函数为空时由cus_dcs_entry_table执行 */ +N// g_rx_ctrl_handle->hight_performan_mode=HIGHT_PERFORMAN_L2; +N g_rx_ctrl_handle->extra_info.crop_info.top =12; //4 8 的倍数 +N g_rx_ctrl_handle->extra_info.crop_info.enable=1; +N#if RX_RESOLUTION_CHANGE_ENABLE +X#if 1 +N g_rx_ctrl_handle->pps_update_entry = pps_update_handle; +N#endif +N /* 提前预置PPS, AP 有PPS cmd也会更新 */ +N if (g_rx_ctrl_handle->compress_en == true) +X if (g_rx_ctrl_handle->compress_en == 1) +N { +N hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps, 128); +N } +N +N /* 初始化rx ctrl */ +N hal_dsi_rx_ctrl_init(g_rx_ctrl_handle); +N +N#if RX_READ_HW_ACK +X#if 0 +S /* 配置硬件回复 */ +S app_set_dcs_hw_ack(); +N#endif +N +N#if TX_CMD_MODE_WITHOUT_TE +X#if 0 +S /* 注册接收一帧帧头事件回调,每接收一帧数据TX再往外发一帧 */ +S //hal_dsi_rx_ctrl_register_callback(g_rx_ctrl_handle, app_rx_event_cb, HAL_RX_FS_EVENT, true, NULL); +S /* 注册接收第0行数据事件,接收到数据后再往外发送数据,确保不撕裂 */ +S uint32_t line = 0; +S hal_dsi_rx_ctrl_register_callback(g_rx_ctrl_handle, app_rx_event_cb, HAL_RX_LINE_EVENT, true, &line); +N#endif +N +N#if RX_START_WITHOUT_RST +X#if 1 +N /* 等待ap reset置位再启动rx,否则容易收到错误数据 */ +N hal_dsi_rx_ctrl_start(g_rx_ctrl_handle); +N#else +S /* 注册RX start callback,确认RX LP11时再启动RX,防止接收错误数据 */ +S hal_gpio_set_ap_reset_int(ENABLE, app_mipi_rx_start_cb, DETECT_HIGH_LVL); +N#endif +N TAU_LOGD("rx init!\n\r"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "rx init!\n\r", "p8p", 1607); } while (0); +N} +N +N/** +N* @brief mipi tx 初始化 +N* @param none +N* @retval none +N*/ +Nstatic void app_mipi_tx_init(void) +N{ +N if (g_tx_ctrl_handle == NULL) +X if (g_tx_ctrl_handle == 0) +N { +N g_tx_ctrl_handle = hal_dsi_tx_ctrl_create_handle(); +N } +N g_tx_ctrl_handle->channel_id = OUTPUT_VC; +X g_tx_ctrl_handle->channel_id = DSI_VC_0; +N g_tx_ctrl_handle->lane_num = OUTPUT_LANE_NUMBER; +X g_tx_ctrl_handle->lane_num = DSI_LANE_4; +N g_tx_ctrl_handle->vid_mode = OUTPUT_VIDEO_MODEL; +X g_tx_ctrl_handle->vid_mode = DSI_BURST_MODE; +N g_tx_ctrl_handle->cmd_tx_type = TX_INIT_TYPE; +X g_tx_ctrl_handle->cmd_tx_type = DSI_CMD_TX_LP; +N g_tx_ctrl_handle->dpi_vsa = OUTPUT_VSA; +X g_tx_ctrl_handle->dpi_vsa = 1; +N g_tx_ctrl_handle->dpi_vbp = OUTPUT_VBP; +X g_tx_ctrl_handle->dpi_vbp = 19; +N g_tx_ctrl_handle->dpi_vfp = OUTPUT_VFP; +X g_tx_ctrl_handle->dpi_vfp = 12; +N g_tx_ctrl_handle->dpi_hsa = OUTPUT_HSA; +X g_tx_ctrl_handle->dpi_hsa = 1; +N g_tx_ctrl_handle->dpi_hbp = OUTPUT_HBP; +X g_tx_ctrl_handle->dpi_hbp = 27; +N g_tx_ctrl_handle->dpi_hfp = OUTPUT_HFP; +X g_tx_ctrl_handle->dpi_hfp = 77; +N g_tx_ctrl_handle->base_info.src_w = INPUT_WIDTH; +X g_tx_ctrl_handle->base_info.src_w = 1344; +N g_tx_ctrl_handle->base_info.src_h = INPUT_HEIGHT; +X g_tx_ctrl_handle->base_info.src_h = 2992; +N g_tx_ctrl_handle->base_info.dst_w = OUTPUT_WIDTH; +X g_tx_ctrl_handle->base_info.dst_w = 1080; +N g_tx_ctrl_handle->base_info.dst_h = OUTPUT_HEIGHT; +X g_tx_ctrl_handle->base_info.dst_h = 2400; +N g_tx_ctrl_handle->base_info.src_frate = INPUT_FRAME_RATE; +X g_tx_ctrl_handle->base_info.src_frate = DSI_FRAME_RATE_120HZ; +N g_tx_ctrl_handle->base_info.src_mode = INPUT_DATA_MODE; +X g_tx_ctrl_handle->base_info.src_mode = DSI_DATA_CMD_MODE; +N g_tx_ctrl_handle->base_info.dst_mode = OUTPUT_DATA_MODE; +X g_tx_ctrl_handle->base_info.dst_mode = DSI_DATA_VIDEO_MODE; +N g_tx_ctrl_handle->tx_frame_rate=58; +N// g_tx_ctrl_handle->tx_lane_lp = 2; +N +N /* 初始化屏时每一条LP CMD都退出LPDT 再进入发送下一条 */ +N /* 解决FT8720 TDDI 显示翻转问题 */ +N // g_tx_ctrl_handle->lp_exit_lpdt = true; +N +N hal_dsi_tx_ctrl_init(g_tx_ctrl_handle); +N// hal_dsi_tx_ctrl_set_cus_sync_line(g_tx_ctrl_handle,1200); //1200 +N +N /* FIXME set tear on*/ +N // hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); +N +N /* AP 没有发送数据时默认的显示颜色, 量产为0 0 0(黑色), 配置其他颜色仅为debug使用 */ +N hal_dsi_tx_ctrl_set_overwrite_rgb(0x00, 0x00, 0x00); +N TAU_LOGD("tx init!\n\r"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "tx init!\n\r", "p8p", 1653); } while (0); +N} +N +N#if !RX_START_WITHOUT_RST +X#if !1 +S/** +S* @brief mipi rx start函数,开启AP RSTN等待启动配置后使用 +S* @param none +S* @retval none +S*/ +Sstatic void app_mipi_rx_start_cb(void *data) +S{ +S /* RX start */ +S hal_dsi_rx_ctrl_start(g_rx_ctrl_handle); +S /* close cb */ +S hal_gpio_set_ap_reset_int(DISABLE, NULL, DETECT_HIGH_LVL); +S TAU_LOGD("rx start\n"); +S} +N#endif +N +Nvoid Panel_CCM(void) +N{ +N ccm_coef_t ccm; +N ccm.coef_c00 = 255; // 260 +N ccm.coef_c01 = 0; +N ccm.coef_c02 = 0; +N ccm.coef_c10 = 0; +N ccm.coef_c11 = 246; // 247 +N ccm.coef_c12 = 0; +N ccm.coef_c20 = 0; +N ccm.coef_c21 = 0; +N ccm.coef_c22 = 247; //248 +N +N hal_dsi_tx_ctrl_set_ccm(&ccm); +N} +N +N +N/** +N* @brief mipi tx 启动 +N* @param none +N* @retval none +N*/ +Nstatic void app_mipi_tx_start(void) +N{ +N // TAU_LOGD("tx_start \n"); +N /* Init panel */ +N app_init_panel(); +N /* TX start */ +N hal_dsi_tx_ctrl_start(g_tx_ctrl_handle); +N +N#if RX_WAIT_TEAR_ON +X#if 0 +S te_mode_e default_te = sg_ap_set_tear_on ? TE_60HZ_MODE : TE_USER_MODE; +S hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, default_te); +N#else +N hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); +N#endif +N +N panel_display_done = true; +X panel_display_done = 1; +N if(g_tx_ctrl_handle->base_info.src_w==1008) +N { +N hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps_fhd, 128); +N hal_dsi_rx_ctrl_toggle_resolution(g_rx_ctrl_handle); +N g_resolution_change = false; +X g_resolution_change = 0; +N // TAU_LOGD("pps_update!!\r\n"); +N } +N // soft_te_timer_init(); +N delayMs(80); +N// Panel_CCM(); +N// delayMs(20); +N /* Display on */ +N hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x29); +N +N#if AP_SWIRE_OUTPUT +X#if 1 +N hal_swire_set_pulse(SWIRE_DEFAULT_PULSE); +X hal_swire_set_pulse(31); +N#endif +N +N#if (TX_USE_CMD_MODE & (!TX_CMD_MODE_WITHOUT_TE)) +X#if (0 & (!0)) +S // hal_dsi_tx_ctrl_gen_a_frame(); /* FIXME */ +S app_tx_cmd_app_init_panel_te_int(IO_PIN_14, DETECT_RISING_EDGE); /* 注册屏端TE中断 */ +N#endif +N +N TAU_LOGD("tx_start \n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "tx_start \n", "p8p", 1733); } while (0); +N} +N +N/** +N* @brief ap rstn 拉高中断回调,用于息屏唤醒 +N* @param none +N* @retval none +N*/ +Nstatic void ap_rstn_pull_high_cb(void *data) +N{ +N /* system resume begin */ +N sg_system_resume = true; +X sg_system_resume = 1; +N /* 关闭AP reset检查 */ +N hal_gpio_set_ap_reset_int(DISABLE, NULL, DETECT_RISING_EDGE); +X hal_gpio_set_ap_reset_int(DISABLE, 0, DETECT_RISING_EDGE); +N} +N +N/** +N* @brief ap rstn 拉高中断回调,用于息屏待机 +N* @param none +N* @retval none +N*/ +Nstatic void ap_rstn_pull_down_cb(void *data) +N{ +N TAU_LOGD("ap_rstn_pull_down_cb\n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "ap_rstn_pull_down_cb\n", "p8p", 1756); } while (0); +N sg_system_suspend = true; +X sg_system_suspend = 1; +N /* 关闭AP reset检查 */ +N hal_gpio_set_ap_reset_int(DISABLE, NULL, DETECT_RISING_EDGE); +X hal_gpio_set_ap_reset_int(DISABLE, 0, DETECT_RISING_EDGE); +N// TAU_LOGD("ap_rstn_pull_down_cb\n"); +N} +N +N/** +N* @brief GPIO初始化配置,根据实际原理图提前配置IO功能以及状态,默认功能可不配置 +N* TP相关I2C/SPI 在tp_transfer.c,也可以挪到此函数初始化 +N* @param none +N* @retval none +N*/ +Nvoid app_gpio_init(void) +N{ +N io_pad_attr_t attrs[] = +N { +N {IO_PIN_8, PIN8_MODE_GPIO7, IO_IOE_OUTPUT, IO_LVL_LOW},/* PIN_8(TD_RSTN), GPIO,输出,低电平 */ +N {IO_PIN_17, PIN17_MODE_GPIO8, IO_IOE_OUTPUT, IO_LVL_LOW}, /* PIN_17(PWMEN), GPIO,输出,低电平 */ +N {IO_PIN_16, PIN16_MODE_GPIO2, IO_IOE_OUTPUT, IO_LVL_LOW}, /* PIN_16(AP_INT),GPIO,输出,低电平 */ +N#if (TX_USE_CMD_MODE & (!TX_CMD_MODE_WITHOUT_TE)) +X#if (0 & (!0)) +S {IO_PIN_14, PIN14_MODE_GPIO24, IO_IOE_INPUT, IO_LVL_NONE}, /* PIN_29(AP_TE), cmd mode输出, 并且看屏TE,配置AP TE为GPIO输入 */ +N#endif +N {IO_PIN_29, PIN29_MODE_TEAR, IO_IOE_NONE, IO_LVL_NONE}, /* PIN_29(AP_TE), 硬件TEAR输出模式 */ +N +N }; +N uint8_t size = sizeof(attrs) / sizeof(io_pad_attr_t); +N hal_gpio_config_pad(attrs, size); +N} +N +N +N/** +N* @brief 显示相关模块初始化,包括MIPI RX/TX/PWM/SWIRE/GPIO等 +N* @param none +N* @retval none +N*/ +Nvoid app_display_init(void) +N{ +N /* mipi rx初始化 */ +N app_mipi_rx_init(); +N /* VCC 主供电,等待VCC Power Ready,此时RX初始化完成可以响应MIPI命令 */ +N if (MAIN_POWER_SELECT == PWR_SEL_VCC) +X if (PWR_SEL_VCC == PWR_SEL_VCC) +N { +N +N while (hal_pwr_get_vcc_power_ready() == false); +X while (hal_pwr_get_vcc_power_ready() == 0); +N } +N +N /* GPIO 初始化 */ +N app_gpio_init(); +N//TAU_LOGD("app_gpio_init \n"); +N /* 背光初始化 */ +N#if AP_SWIRE_OUTPUT +X#if 1 +N hal_swire_init(); /* swire init */ +N hal_swire_set_timer(TIMER_NUM0, 8, true); /* swire连续发送,绑定timer进行发送 */ +X hal_swire_set_timer(TIMER_NUM0, 8, 1); +N#endif +N#if ANALOG_PWM_OUTPUT +X#if 0 +S if (hal_pwm_init(PWM_FREQUENCY, PWM_DUTY_STEP)) +S { +S hal_pwm_enable(true); +S hal_pwm_set_elvcc_output(true); +S } +N#endif +N +N /* mipi tx 初始化*/ +N app_mipi_tx_init(); +N// soft_te_timer_init(); +N#if TX_START_AFTER_APRST +X#if 0 +S TAU_LOGD("wait exit sleep mode\n"); +N#else +N app_mipi_tx_start(); +N#endif +N} +N +N/** +N* @brief 系统resume +N* @param sleep_mode: sleep 模式 +N* @retval none +N*/ +Nstatic void app_system_resume(pwr_sleep_mode_e sleep_mode) +N{ +N /* 退出sleep mode, 电源切换 */ +N hal_pwr_exit_sleep_mode(); +N +N /* display resume */ +N app_display_init(); +N +N#if TOUCH_ENABLE +X#if 0 +S /* touch resume */ +S app_tp_write_other_operations(NULL, 0); +N#endif +N TAU_LOGD("system resume\n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "system resume\n", "p8p", 1846); } while (0); +N} +N +N/** +N* @brief 系统suspend,进入sleep mode +N* @param sleep_mode: sleep 模式 +N* @retval none +N*/ +Nstatic void app_system_suspend(pwr_sleep_mode_e sleep_mode) +N{ +N// TAU_LOGD("SLEEP_MODE\n"); +N /* 关闭图像通路 */ +N hal_dsi_tx_ctrl_stop(g_tx_ctrl_handle); +N hal_dsi_tx_ctrl_deinit(g_tx_ctrl_handle); +N hal_dsi_rx_ctrl_stop(g_rx_ctrl_handle); +N hal_dsi_rx_ctrl_deinit(g_rx_ctrl_handle); +N +N /* Tear拉低 */ +N hal_gpio_init_output(IO_PAD_AP_TE, IO_LVL_LOW); +N panel_display_done = false; +X panel_display_done = 0; +N#if RX_WAIT_TEAR_ON +X#if 0 +S sg_ap_set_tear_on = false; +N#endif +N +N /* 关闭外设 比如Swire/I2C/Flash 等 */ +N#if AP_SWIRE_OUTPUT +X#if 1 +N hal_swire_deinit(); +N#endif +N#if ANALOG_PWM_OUTPUT +X#if 0 +S hal_pwm_deinit(); +N#endif +N +N#if SHARE_FLASH_ENABLE +X#if 0 +S hal_flash_share_mode(false); +N#endif +N +N /* 切换TP18 供电 */ +N hal_pwr_set_sleep_mode_power(SLEEP_MODE_POWER); +X hal_pwr_set_sleep_mode_power(PWR_SLEEP_IN_IOV18); +N +N if (sleep_mode == PWR_NORMAL_SLEEP_MODE) +N { +N /* normal sleep mode, MCU可以正常工作 */ +N hal_gpio_set_ap_reset_int(ENABLE, ap_rstn_pull_high_cb, DETECT_HIGH_LVL); +N hal_pwr_enter_normal_sleep_mode(); +N TAU_LOGD("PWR_NORMAL_SLEEP_MODE\n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "PWR_NORMAL_SLEEP_MODE\n", "p8p", 1890); } while (0); +N } +N else if (sleep_mode == PWR_STOP_SLEEP_MODE) +N { +N TAU_LOGD("PWR_STOP_SLEEP_MODE\n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "PWR_STOP_SLEEP_MODE\n", "p8p", 1894); } while (0); +N +N /* 注册对应 wakeup IO */ +N hal_pwr_set_stop_sleep_wakeup_pin(IO_PAD_AP_RSTN, WUP_RISING_EDGE); +N //hal_pwr_set_stop_sleep_wakeup_pin(IO_PAD_AP_SPIS_CSN, WUP_FALLING_EDGE); +N //hal_pwr_set_stop_sleep_wakeup_pin(IO_PAD_TD_INT, WUP_FALLING_EDGE); +N io_pad_e wakeup_io = hal_pwr_enter_stop_sleep_mode(); +N if (wakeup_io == IO_PAD_AP_RSTN) +N { +N sg_system_resume = true; +X sg_system_resume = 1; +N } +N else +N { +N /* Not impletmented */ +N TAU_LOGD("wakeup_io %d FIXME touch wakeup convert to AP\n", wakeup_io); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "wakeup_io %d FIXME touch wakeup convert to AP\n", "p8p", 1908,wakeup_io); } while (0); +N hal_gpio_set_ap_reset_int(ENABLE, ap_rstn_pull_high_cb, DETECT_HIGH_LVL); +N } +N } +N else +N { +N /* deep sleep mode,配置AP RSTN 上升沿,TD INT 下降沿唤醒 */ +N hal_pwr_enter_deep_sleep_mode(WUP_RISING_EDGE, WUP_FALLING_EDGE); +N TAU_LOGD("PWR_DEEP_SLEEP_MODE\n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "PWR_DEEP_SLEEP_MODE\n", "p8p", 1916); } while (0); +N } +N +N} +N +N/** +N* @brief 系统process处理函数,处理待机唤醒等 +N* @param none +N* @retval none +N*/ +Nstatic void app_system_process(void) +N{ +N +N if (sg_system_suspend) +N { +N TAU_LOGD("app_system_process\n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "app_system_process\n", "p8p", 1931); } while (0); +N /* 系统进入sleep mode */ +N app_system_suspend(SLEEP_MODE_SELECT); +X app_system_suspend(PWR_DEEP_SLEEP_MODE); +N sg_system_suspend = false; +X sg_system_suspend = 0; +N } +N +N if (sg_system_resume) +N { +N /* 系统退出sleep mode */ +N app_system_resume(SLEEP_MODE_SELECT); +X app_system_resume(PWR_DEEP_SLEEP_MODE); +N sg_system_resume = false; +X sg_system_resume = 0; +N } +N +N#if TX_START_AFTER_APRST +X#if 0 +S if (sg_tx_start_in_process) +S { +S app_mipi_tx_start(); +S sg_tx_start_in_process = false; +S } +N#endif +N} +N +N +N +N/** +N* @brief mi12 lite demo 主函数 +N* @param none +N* @retval none +N*/ +Nvoid google_p8p_demo(void) +N{ +N// hal_gpio_set_high_impedance(IO_PIN_14); +N// TAU_LOGD("p6p demo reset flag=%d \n", hal_pwr_get_reset_flag()); +N +N /* 电源选择,上电只需要选择一次 */ +N hal_pwr_set_main_power(MAIN_POWER_SELECT); /* 切换供电*/ +X hal_pwr_set_main_power(PWR_SEL_VCC); +N// if (MAIN_POWER_SELECT == PWR_SEL_VCC) +N// { +N// while (hal_pwr_get_vcc_power_ready() == false); +N// } +N /* 显示模块初始 */ +N app_display_init(); +N +N /* touch 相关模块初始化 */ +N#if TOUCH_ENABLE +X#if 0 +S /* TP 初始化 */ +S app_tp_init(); +S app_tp_phone_clear_reset_on(); +S /* 与屏的TP 模块通讯并初始化 */ +S app_tp_transfer_screen_start(); +N#endif +N +N TAU_LOGD("p8p demo init done \n"); +X do { tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " "p8p demo init done \n", "p8p", 1983); } while (0); +N +N while (1) +N { +N +N ///hal_dsi_tx_ctrl_set_vpg(1, TX_VPG_H_COLOR, true); +N#if TOUCH_ENABLE +X#if 0 +S /* 等待屏TP中断上报做TP协议转换,注意接口实现不可阻塞!否则会影响sleep mode */ +S app_tp_transfer_screen_int(); +N#endif +N /* DCS 命令异步处理 */ +N while (hal_dsi_rx_ctrl_dcs_async_handler(g_rx_ctrl_handle)); +N +N /* 系统事件处理(sleep mode) */ +N app_system_process(); +N } +N} +N#endif +W "..\..\src\app\P8P\p8p_demo.c" 131 13 variable "sg_exit_idle_mode_flag" was set but never used +W "..\..\src\app\P8P\p8p_demo.c" 134 17 variable "pps_renew_flag" was declared but never referenced +W "..\..\src\app\P8P\p8p_demo.c" 135 17 variable "pwr_rst_flag" was declared but never referenced +W "..\..\src\app\P8P\p8p_demo.c" 149 13 function "app_mipi_rx_start_cb" was declared but never referenced +W "..\..\src\app\P8P\p8p_demo.c" 459 13 variable "reg53_E8_fg" was declared but never referenced +W "..\..\src\app\P8P\p8p_demo.c" 533 13 function "ap_dcs_set_exit_idle_mode" was declared but never referenced +W "..\..\src\app\P8P\p8p_demo.c" 558 13 function "soft_te_timer_init" was declared but never referenced diff --git a/project/WL668/Listings/p8p_demo.txt b/project/WL668/Listings/p8p_demo.txt new file mode 100644 index 0000000..2a3555e --- /dev/null +++ b/project/WL668/Listings/p8p_demo.txt @@ -0,0 +1,4611 @@ +; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] +; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave --gnu -o.\objects\p8p_demo.o --asm_dir=.\Listings\ --list_dir=.\Listings\ --depend=.\objects\p8p_demo.d --cpu=Cortex-M0 --apcs=interwork -O0 --diag_suppress=9931 -I..\..\src -I..\..\src\board -I..\..\src\common -I..\..\src\sdk\include -I..\..\src\sdk\include\M0 -I..\..\src\app -I..\..\src\app\S8 -I..\..\src\app\touch -I..\..\src\app\module_demo -I..\..\src\app\P8P -I.\RTE\_WL668 -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include -D__MICROLIB -D__UVISION_VERSION=528 -D_RTE_ -DARMCM0 --omf_browse=.\objects\p8p_demo.crf ..\..\src\app\P8P\p8p_demo.c] + THUMB + + AREA ||i.Gpio_swire_output||, CODE, READONLY, ALIGN=1 + + Gpio_swire_output PROC +;;;366 *****************************************************************************/ +;;;367 void Gpio_swire_output(uint8_t flag, uint8_t num) +000000 b570 PUSH {r4-r6,lr} +;;;368 { +000002 4604 MOV r4,r0 +000004 460e MOV r6,r1 +;;;369 uint8_t ii; +;;;370 +;;;371 if (flag) +000006 2c00 CMP r4,#0 +000008 d01d BEQ |L1.70| +;;;372 { +;;;373 if (flag ==2) +00000a 2c02 CMP r4,#2 +00000c d106 BNE |L1.28| +;;;374 { +;;;375 hal_gpio_init_output(IO_PAD_AP_SWIRE, IO_LVL_HIGH); +00000e 2101 MOVS r1,#1 +000010 2004 MOVS r0,#4 +000012 f7fffffe BL hal_gpio_init_output +;;;376 delayMs(2); +000016 2002 MOVS r0,#2 +000018 f7fffffe BL delayMs + |L1.28| +;;;377 } +;;;378 for (ii =0; ii< num; ii++) +00001c 2500 MOVS r5,#0 +00001e e00f B |L1.64| + |L1.32| +;;;379 { +;;;380 hal_gpio_set_output_data(IO_PAD_AP_SWIRE, IO_LVL_LOW); +000020 2100 MOVS r1,#0 +000022 2004 MOVS r0,#4 +000024 f7fffffe BL hal_gpio_set_output_data +;;;381 delayUs(10); +000028 200a MOVS r0,#0xa +00002a f7fffffe BL delayUs +;;;382 hal_gpio_set_output_data(IO_PAD_AP_SWIRE, IO_LVL_HIGH); +00002e 2101 MOVS r1,#1 +000030 2004 MOVS r0,#4 +000032 f7fffffe BL hal_gpio_set_output_data +;;;383 delayUs(9); +000036 2009 MOVS r0,#9 +000038 f7fffffe BL delayUs +00003c 1c68 ADDS r0,r5,#1 ;378 +00003e b2c5 UXTB r5,r0 ;378 + |L1.64| +000040 42b5 CMP r5,r6 ;378 +000042 dbed BLT |L1.32| +000044 e003 B |L1.78| + |L1.70| +;;;384 } +;;;385 } +;;;386 else +;;;387 { +;;;388 hal_gpio_init_output(IO_PAD_AP_SWIRE, IO_LVL_LOW); +000046 2100 MOVS r1,#0 +000048 2004 MOVS r0,#4 +00004a f7fffffe BL hal_gpio_init_output + |L1.78| +;;;389 } +;;;390 } +00004e bd70 POP {r4-r6,pc} +;;;391 + ENDP + + + AREA ||i.Panel_CCM||, CODE, READONLY, ALIGN=1 + + Panel_CCM PROC +;;;1671 +;;;1672 void Panel_CCM(void) +000000 b500 PUSH {lr} +;;;1673 { +000002 b089 SUB sp,sp,#0x24 +;;;1674 ccm_coef_t ccm; +;;;1675 ccm.coef_c00 = 255; // 260 +000004 20ff MOVS r0,#0xff +000006 9000 STR r0,[sp,#0] +;;;1676 ccm.coef_c01 = 0; +000008 2000 MOVS r0,#0 +00000a 9001 STR r0,[sp,#4] +;;;1677 ccm.coef_c02 = 0; +00000c 9002 STR r0,[sp,#8] +;;;1678 ccm.coef_c10 = 0; +00000e 9003 STR r0,[sp,#0xc] +;;;1679 ccm.coef_c11 = 246; // 247 +000010 20f6 MOVS r0,#0xf6 +000012 9004 STR r0,[sp,#0x10] +;;;1680 ccm.coef_c12 = 0; +000014 2000 MOVS r0,#0 +000016 9005 STR r0,[sp,#0x14] +;;;1681 ccm.coef_c20 = 0; +000018 9006 STR r0,[sp,#0x18] +;;;1682 ccm.coef_c21 = 0; +00001a 9007 STR r0,[sp,#0x1c] +;;;1683 ccm.coef_c22 = 247; //248 +00001c 20f7 MOVS r0,#0xf7 +00001e 9008 STR r0,[sp,#0x20] +;;;1684 +;;;1685 hal_dsi_tx_ctrl_set_ccm(&ccm); +000020 4668 MOV r0,sp +000022 f7fffffe BL hal_dsi_tx_ctrl_set_ccm +;;;1686 } +000026 b009 ADD sp,sp,#0x24 +000028 bd00 POP {pc} +;;;1687 + ENDP + + + AREA ||i.REG_51_OFF_output||, CODE, READONLY, ALIGN=1 + + REG_51_OFF_output PROC +;;;326 +;;;327 void REG_51_OFF_output(uint16_t REG_51_VALUE) +000000 b57c PUSH {r2-r6,lr} +;;;328 { +000002 4606 MOV r6,r0 +;;;329 uint8_t i; +;;;330 uint16_t REG_51; +;;;331 +;;;332 +;;;333 +;;;334 for (i =0; i< 50; i++) +000004 2400 MOVS r4,#0 +000006 e016 B |L3.54| + |L3.8| +;;;335 { +;;;336 REG_51=REG_51_VALUE*(50-i)/50; +000008 2132 MOVS r1,#0x32 +00000a 1b09 SUBS r1,r1,r4 +00000c 4371 MULS r1,r6,r1 +00000e 4608 MOV r0,r1 +000010 2132 MOVS r1,#0x32 +000012 f7fffffe BL __aeabi_idivmod +000016 b285 UXTH r5,r0 +;;;337 hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, REG_51>>8, REG_51&0x00FF);; +000018 b2e8 UXTB r0,r5 +00001a 1229 ASRS r1,r5,#8 +00001c 2351 MOVS r3,#0x51 +00001e 2203 MOVS r2,#3 +000020 9100 STR r1,[sp,#0] +000022 9001 STR r0,[sp,#4] +000024 2100 MOVS r1,#0 +000026 2039 MOVS r0,#0x39 +000028 f7fffffe BL hal_dsi_tx_ctrl_write_cmd +;;;338 delayMs(17); +00002c 2011 MOVS r0,#0x11 +00002e f7fffffe BL delayMs +000032 1c60 ADDS r0,r4,#1 ;334 +000034 b2c4 UXTB r4,r0 ;334 + |L3.54| +000036 2c32 CMP r4,#0x32 ;334 +000038 dbe6 BLT |L3.8| +;;;339 // TAU_LOGD("reg_51_off[0x%04X]\n",REG_51); +;;;340 } +;;;341 +;;;342 } +00003a bd7c POP {r2-r6,pc} +;;;343 + ENDP + + + AREA ||i.ap_dcs_read||, CODE, READONLY, ALIGN=2 + + ap_dcs_read PROC +;;;169 */ +;;;170 static bool ap_dcs_read(uint8_t data_type, uint8_t dcs_cmd, uint8_t param) +000000 b5f0 PUSH {r4-r7,lr} +;;;171 { +000002 b08d SUB sp,sp,#0x34 +000004 4606 MOV r6,r0 +000006 460c MOV r4,r1 +000008 4617 MOV r7,r2 +;;;172 if (dcs_cmd == 0x04) +00000a 2c04 CMP r4,#4 +00000c d10d BNE |L4.42| +;;;173 { +;;;174 hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +00000e 2020 MOVS r0,#0x20 +000010 2160 MOVS r1,#0x60 +000012 220a MOVS r2,#0xa +000014 2303 MOVS r3,#3 +000016 9200 STR r2,[sp,#0] +000018 9101 STR r1,[sp,#4] +00001a 9002 STR r0,[sp,#8] +00001c 2200 MOVS r2,#0 +00001e 211c MOVS r1,#0x1c +000020 483d LDR r0,|L4.280| +000022 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000024 f7fffffe BL hal_dsi_rx_ctrl_send_ack_cmd +000028 e073 B |L4.274| + |L4.42| +;;;175 DSI_ACK_DT_DCS_LONG_RESPONSE, +;;;176 DSI_VC_0, +;;;177 3, 0x0A,0x60,0x20); +;;;178 } +;;;179 else if (dcs_cmd == 0xa1) +00002a 2ca1 CMP r4,#0xa1 +00002c d120 BNE |L4.112| +;;;180 { +;;;181 hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +00002e 20f6 MOVS r0,#0xf6 +000030 2121 MOVS r1,#0x21 +000032 2225 MOVS r2,#0x25 +000034 232b MOVS r3,#0x2b +000036 9309 STR r3,[sp,#0x24] +000038 920a STR r2,[sp,#0x28] +00003a 910b STR r1,[sp,#0x2c] +00003c 900c STR r0,[sp,#0x30] +00003e 2006 MOVS r0,#6 +000040 2111 MOVS r1,#0x11 +000042 22aa MOVS r2,#0xaa +000044 23f3 MOVS r3,#0xf3 +000046 9305 STR r3,[sp,#0x14] +000048 9206 STR r2,[sp,#0x18] +00004a 9107 STR r1,[sp,#0x1c] +00004c 9008 STR r0,[sp,#0x20] +00004e 2001 MOVS r0,#1 +000050 21c6 MOVS r1,#0xc6 +000052 220c MOVS r2,#0xc +000054 2321 MOVS r3,#0x21 +000056 9202 STR r2,[sp,#8] +000058 9301 STR r3,[sp,#4] +00005a 9200 STR r2,[sp,#0] +00005c 9103 STR r1,[sp,#0xc] +00005e 9004 STR r0,[sp,#0x10] +000060 230d MOVS r3,#0xd +000062 2200 MOVS r2,#0 +000064 211c MOVS r1,#0x1c +000066 482c LDR r0,|L4.280| +000068 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +00006a f7fffffe BL hal_dsi_rx_ctrl_send_ack_cmd +00006e e050 B |L4.274| + |L4.112| +;;;182 DSI_ACK_DT_DCS_LONG_RESPONSE, +;;;183 DSI_VC_0, +;;;184 13, 0x0C,0x21,0x0C,0xC6,0x01,0xF3,0xAA,0x11,0x06,0x2B,0x25,0x21,0xF6); +;;;185 } +;;;186 else if (dcs_cmd == 0xDA) +000070 2cda CMP r4,#0xda +000072 d109 BNE |L4.136| +;;;187 { +;;;188 hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +000074 200a MOVS r0,#0xa +000076 2301 MOVS r3,#1 +000078 2200 MOVS r2,#0 +00007a 2121 MOVS r1,#0x21 +00007c 9000 STR r0,[sp,#0] +00007e 4826 LDR r0,|L4.280| +000080 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000082 f7fffffe BL hal_dsi_rx_ctrl_send_ack_cmd +000086 e044 B |L4.274| + |L4.136| +;;;189 DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, +;;;190 DSI_VC_0, +;;;191 1, 0x0A); +;;;192 } +;;;193 else if (dcs_cmd == 0xDB) +000088 2cdb CMP r4,#0xdb +00008a d109 BNE |L4.160| +;;;194 { +;;;195 hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +00008c 2068 MOVS r0,#0x68 +00008e 2301 MOVS r3,#1 +000090 2200 MOVS r2,#0 +000092 2121 MOVS r1,#0x21 +000094 9000 STR r0,[sp,#0] +000096 4820 LDR r0,|L4.280| +000098 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +00009a f7fffffe BL hal_dsi_rx_ctrl_send_ack_cmd +00009e e038 B |L4.274| + |L4.160| +;;;196 DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, +;;;197 DSI_VC_0, +;;;198 1, 0x68); +;;;199 } +;;;200 else if (dcs_cmd == 0xDC) +0000a0 2cdc CMP r4,#0xdc +0000a2 d109 BNE |L4.184| +;;;201 { +;;;202 hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +0000a4 2007 MOVS r0,#7 +0000a6 2301 MOVS r3,#1 +0000a8 2200 MOVS r2,#0 +0000aa 2121 MOVS r1,#0x21 +0000ac 9000 STR r0,[sp,#0] +0000ae 481a LDR r0,|L4.280| +0000b0 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +0000b2 f7fffffe BL hal_dsi_rx_ctrl_send_ack_cmd +0000b6 e02c B |L4.274| + |L4.184| +;;;203 DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, +;;;204 DSI_VC_0, +;;;205 1, 0x07); +;;;206 } +;;;207 else if (dcs_cmd == 0xD6) +0000b8 2cd6 CMP r4,#0xd6 +0000ba d111 BNE |L4.224| +;;;208 { +;;;209 hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +0000bc 2086 MOVS r0,#0x86 +0000be 2161 MOVS r1,#0x61 +0000c0 2285 MOVS r2,#0x85 +0000c2 23ea MOVS r3,#0xea +0000c4 9301 STR r3,[sp,#4] +0000c6 9202 STR r2,[sp,#8] +0000c8 9103 STR r1,[sp,#0xc] +0000ca 9004 STR r0,[sp,#0x10] +0000cc 20f0 MOVS r0,#0xf0 +0000ce 2305 MOVS r3,#5 +0000d0 2200 MOVS r2,#0 +0000d2 211c MOVS r1,#0x1c +0000d4 9000 STR r0,[sp,#0] +0000d6 4810 LDR r0,|L4.280| +0000d8 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +0000da f7fffffe BL hal_dsi_rx_ctrl_send_ack_cmd +0000de e018 B |L4.274| + |L4.224| +;;;210 DSI_ACK_DT_DCS_LONG_RESPONSE, +;;;211 DSI_VC_0, +;;;212 5, 0xF0, 0xEA, 0x85, 0x61, 0x86); +;;;213 } +;;;214 else +;;;215 { +;;;216 uint32_t return_size = hal_dsi_rx_ctrl_get_max_ret_size(g_rx_ctrl_handle); +0000e0 480d LDR r0,|L4.280| +0000e2 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +0000e4 f7fffffe BL hal_dsi_rx_ctrl_get_max_ret_size +0000e8 4605 MOV r5,r0 +;;;217 hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, +0000ea 2000 MOVS r0,#0 +0000ec 2301 MOVS r3,#1 +0000ee 4602 MOV r2,r0 +0000f0 2121 MOVS r1,#0x21 +0000f2 9000 STR r0,[sp,#0] +0000f4 4808 LDR r0,|L4.280| +0000f6 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +0000f8 f7fffffe BL hal_dsi_rx_ctrl_send_ack_cmd +;;;218 DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, +;;;219 DSI_VC_0, +;;;220 1, 0); +;;;221 TAU_LOGD("r[%x] [%d] err!!!!!!\n", dcs_cmd, return_size); +0000fc bf00 NOP +0000fe 23dd MOVS r3,#0xdd +000100 a206 ADR r2,|L4.284| +000102 a107 ADR r1,|L4.288| +000104 2000 MOVS r0,#0 +000106 9501 STR r5,[sp,#4] +000108 9400 STR r4,[sp,#0] +00010a f7fffffe BL tau_log_printf +00010e bf00 NOP +;;;222 } +000110 bf00 NOP + |L4.274| +;;;223 +;;;224 // TAU_LOGD("r %x\n",dcs_cmd); +;;;225 return true; +000112 2001 MOVS r0,#1 +;;;226 } +000114 b00d ADD sp,sp,#0x34 +000116 bdf0 POP {r4-r7,pc} +;;;227 + ENDP + + |L4.280| + DCD g_rx_ctrl_handle + |L4.284| +00011c 70387000 DCB "p8p",0 + |L4.288| +000120 5b25735d DCB "[%s] (%04d) r[%x] [%d] err!!!!!!\n",0 +000124 20282530 +000128 34642920 +00012c 725b2578 +000130 5d205b25 +000134 645d2065 +000138 72722121 +00013c 21212121 +000140 0a00 +000142 00 DCB 0 +000143 00 DCB 0 + + AREA ||i.ap_dcs_set_backlight||, CODE, READONLY, ALIGN=2 + + ap_dcs_set_backlight PROC +;;;459 static bool reg53_E8_fg=0; +;;;460 static bool ap_dcs_set_backlight(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +000000 b57c PUSH {r2-r6,lr} +;;;461 { +000002 4605 MOV r5,r0 +000004 460c MOV r4,r1 +;;;462 //手机端0xC4~CEB(2043) 映射0x9FF +;;;463 #if 0 +;;;464 value_51H = dcs_packet->packet_param[0]; +;;;465 value_51L = dcs_packet->packet_param[1]; +;;;466 hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, value_51H, value_51L); +;;;467 #else +;;;468 rd_51_val = dcs_packet->packet_param[0]; +000006 68e0 LDR r0,[r4,#0xc] +000008 7800 LDRB r0,[r0,#0] +00000a 491e LDR r1,|L5.132| +00000c 8008 STRH r0,[r1,#0] +;;;469 rd_51_val <<=8; +00000e 4608 MOV r0,r1 +000010 7800 LDRB r0,[r0,#0] ; rd_51_val +000012 0600 LSLS r0,r0,#24 +000014 0c00 LSRS r0,r0,#16 +000016 8008 STRH r0,[r1,#0] +;;;470 rd_51_val |= dcs_packet->packet_param[1]; +000018 68e0 LDR r0,[r4,#0xc] +00001a 7840 LDRB r0,[r0,#1] +00001c 8809 LDRH r1,[r1,#0] ; rd_51_val +00001e 4308 ORRS r0,r0,r1 +000020 4918 LDR r1,|L5.132| +000022 8008 STRH r0,[r1,#0] +;;;471 +;;;472 // rd_51_val2 = (rd_51_val-0x04)*2555/2043+0x04; //0x9FF max +;;;473 if((rd_51_val >=0x00)&&(rd_51_val <= 0xFFF) ){ +000024 4608 MOV r0,r1 +000026 8800 LDRH r0,[r0,#0] ; rd_51_val +000028 2800 CMP r0,#0 +00002a db12 BLT |L5.82| +00002c 4608 MOV r0,r1 +00002e 8800 LDRH r0,[r0,#0] ; rd_51_val +000030 4915 LDR r1,|L5.136| +000032 4288 CMP r0,r1 +000034 dc0d BGT |L5.82| +;;;474 +;;;475 rd_51_val2 = (rd_51_val-0xC4)*2555/3889+0x04; //0x9FF max +000036 4913 LDR r1,|L5.132| +000038 8809 LDRH r1,[r1,#0] ; rd_51_val +00003a 39c4 SUBS r1,r1,#0xc4 +00003c 4a13 LDR r2,|L5.140| +00003e 4351 MULS r1,r2,r1 +000040 4608 MOV r0,r1 +000042 4911 LDR r1,|L5.136| +000044 39ce SUBS r1,r1,#0xce +000046 f7fffffe BL __aeabi_idivmod +00004a 1d00 ADDS r0,r0,#4 +00004c 4910 LDR r1,|L5.144| +00004e 8008 STRH r0,[r1,#0] +000050 e008 B |L5.100| + |L5.82| +;;;476 +;;;477 } +;;;478 else if(rd_51_val >0xFFF) { +000052 480c LDR r0,|L5.132| +000054 8800 LDRH r0,[r0,#0] ; rd_51_val +000056 490c LDR r1,|L5.136| +000058 4288 CMP r0,r1 +00005a dd03 BLE |L5.100| +;;;479 +;;;480 rd_51_val2 = 0x9FF; +00005c 480b LDR r0,|L5.140| +00005e 1d00 ADDS r0,r0,#4 +000060 490b LDR r1,|L5.144| +000062 8008 STRH r0,[r1,#0] + |L5.100| +;;;481 +;;;482 } +;;;483 hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, rd_51_val2>>8, rd_51_val2&0x00FF); +000064 480a LDR r0,|L5.144| +000066 7800 LDRB r0,[r0,#0] ; rd_51_val2 +000068 4909 LDR r1,|L5.144| +00006a 8809 LDRH r1,[r1,#0] ; rd_51_val2 +00006c 1209 ASRS r1,r1,#8 +00006e 2351 MOVS r3,#0x51 +000070 2203 MOVS r2,#3 +000072 9100 STR r1,[sp,#0] +000074 9001 STR r0,[sp,#4] +000076 2100 MOVS r1,#0 +000078 2039 MOVS r0,#0x39 +00007a f7fffffe BL hal_dsi_tx_ctrl_write_cmd +;;;484 #endif +;;;485 // TAU_LOGD("AP_51[0x%04X],IC_51[0x%04X]\n",rd_51_val,rd_51_val2); +;;;486 return true; +00007e 2001 MOVS r0,#1 +;;;487 } +000080 bd7c POP {r2-r6,pc} +;;;488 + ENDP + +000082 0000 DCW 0x0000 + |L5.132| + DCD rd_51_val + |L5.136| + DCD 0x00000fff + |L5.140| + DCD 0x000009fb + |L5.144| + DCD rd_51_val2 + + AREA ||i.ap_dcs_set_display_off||, CODE, READONLY, ALIGN=2 + + ap_dcs_set_display_off PROC +;;;349 */ +;;;350 static bool ap_dcs_set_display_off(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +000000 b538 PUSH {r3-r5,lr} +;;;351 { +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +;;;352 #if ANALOG_PWM_OUTPUT +;;;353 hal_pwm_enable(false); +;;;354 #endif +;;;355 +;;;356 TAU_LOGD("disp off %d\n", panel_display_done); +000006 bf00 NOP +000008 4806 LDR r0,|L6.36| +00000a 7800 LDRB r0,[r0,#0] ; panel_display_done +00000c 23ff MOVS r3,#0xff +00000e 3365 ADDS r3,r3,#0x65 +000010 a205 ADR r2,|L6.40| +000012 a106 ADR r1,|L6.44| +000014 9000 STR r0,[sp,#0] +000016 2000 MOVS r0,#0 +000018 f7fffffe BL tau_log_printf +00001c bf00 NOP +;;;357 return true; +00001e 2001 MOVS r0,#1 +;;;358 } +000020 bd38 POP {r3-r5,pc} +;;;359 + ENDP + +000022 0000 DCW 0x0000 + |L6.36| + DCD panel_display_done + |L6.40| +000028 70387000 DCB "p8p",0 + |L6.44| +00002c 5b25735d DCB "[%s] (%04d) disp off %d\n",0 +000030 20282530 +000034 34642920 +000038 64697370 +00003c 206f6666 +000040 2025640a +000044 00 +000045 00 DCB 0 +000046 00 DCB 0 +000047 00 DCB 0 + + AREA ||i.ap_dcs_set_display_on||, CODE, READONLY, ALIGN=2 + + ap_dcs_set_display_on PROC +;;;307 */ +;;;308 static bool ap_dcs_set_display_on(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +000000 b570 PUSH {r4-r6,lr} +;;;309 { +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +;;;310 +;;;311 if(g_resolution_change) +000006 4815 LDR r0,|L7.92| +000008 7800 LDRB r0,[r0,#0] ; g_resolution_change +00000a 2800 CMP r0,#0 +00000c d014 BEQ |L7.56| +;;;312 { +;;;313 hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps_fhd, 128); +00000e 2280 MOVS r2,#0x80 +000010 4913 LDR r1,|L7.96| +000012 4814 LDR r0,|L7.100| +000014 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000016 f7fffffe BL hal_dsi_rx_ctrl_pre_init_pps +;;;314 hal_dsi_rx_ctrl_toggle_resolution(g_rx_ctrl_handle); +00001a 4812 LDR r0,|L7.100| +00001c 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +00001e f7fffffe BL hal_dsi_rx_ctrl_toggle_resolution +;;;315 g_resolution_change = false; +000022 2000 MOVS r0,#0 +000024 490d LDR r1,|L7.92| +000026 7008 STRB r0,[r1,#0] +;;;316 TAU_LOGD("pps_update_1\r\n"); +000028 bf00 NOP +00002a 23ff MOVS r3,#0xff +00002c 333d ADDS r3,r3,#0x3d +00002e a20e ADR r2,|L7.104| +000030 a10e ADR r1,|L7.108| +000032 f7fffffe BL tau_log_printf +000036 bf00 NOP + |L7.56| +;;;317 } +;;;318 // TAU_LOGD("disp on"); +;;;319 // if (start_display_on == false){ +;;;320 hal_dsi_tx_ctrl_write_cmd(0x05, 0, 2, 0x29); +000038 2329 MOVS r3,#0x29 +00003a 2202 MOVS r2,#2 +00003c 2100 MOVS r1,#0 +00003e 2005 MOVS r0,#5 +000040 f7fffffe BL hal_dsi_tx_ctrl_write_cmd +;;;321 // } +;;;322 TAU_LOGD("disp on \n"); +000044 bf00 NOP +000046 23ff MOVS r3,#0xff +000048 3343 ADDS r3,r3,#0x43 +00004a a207 ADR r2,|L7.104| +00004c a10e ADR r1,|L7.136| +00004e 2000 MOVS r0,#0 +000050 f7fffffe BL tau_log_printf +000054 bf00 NOP +;;;323 return true; +000056 2001 MOVS r0,#1 +;;;324 } +000058 bd70 POP {r4-r6,pc} +;;;325 + ENDP + +00005a 0000 DCW 0x0000 + |L7.92| + DCD g_resolution_change + |L7.96| + DCD pps_fhd + |L7.100| + DCD g_rx_ctrl_handle + |L7.104| +000068 70387000 DCB "p8p",0 + |L7.108| +00006c 5b25735d DCB "[%s] (%04d) pps_update_1\r\n",0 +000070 20282530 +000074 34642920 +000078 7070735f +00007c 75706461 +000080 74655f31 +000084 0d0a00 +000087 00 DCB 0 + |L7.136| +000088 5b25735d DCB "[%s] (%04d) disp on \n",0 +00008c 20282530 +000090 34642920 +000094 64697370 +000098 206f6e20 +00009c 0a00 +00009e 00 DCB 0 +00009f 00 DCB 0 + + AREA ||i.ap_dcs_set_enter_sleep_mode||, CODE, READONLY, ALIGN=2 + + ap_dcs_set_enter_sleep_mode PROC +;;;399 */ +;;;400 static bool ap_dcs_set_enter_sleep_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +000000 b570 PUSH {r4-r6,lr} +;;;401 { +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +;;;402 hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x28); +000006 2328 MOVS r3,#0x28 +000008 2201 MOVS r2,#1 +00000a 2100 MOVS r1,#0 +00000c 2005 MOVS r0,#5 +00000e f7fffffe BL hal_dsi_tx_ctrl_write_cmd +;;;403 hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_STOP_MODE); +000012 2101 MOVS r1,#1 +000014 4814 LDR r0,|L8.104| +000016 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000018 f7fffffe BL hal_dsi_tx_ctrl_set_tear_mode +;;;404 delayMs(10); +00001c 200a MOVS r0,#0xa +00001e f7fffffe BL delayMs +;;;405 +;;;406 // delayMs(10); +;;;407 #if AP_SWIRE_OUTPUT +;;;408 /* Swire close */ +;;;409 hal_swire_enable(false); +000022 2000 MOVS r0,#0 +000024 f7fffffe BL hal_swire_enable +;;;410 delayMs(10); +000028 200a MOVS r0,#0xa +00002a f7fffffe BL delayMs +;;;411 hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x10); +00002e 2310 MOVS r3,#0x10 +000030 2201 MOVS r2,#1 +000032 2100 MOVS r1,#0 +000034 2005 MOVS r0,#5 +000036 f7fffffe BL hal_dsi_tx_ctrl_write_cmd +;;;412 delayMs(20); +00003a 2014 MOVS r0,#0x14 +00003c f7fffffe BL delayMs +;;;413 /* AVDD_EN close*/ +;;;414 hal_gpio_set_output_data(IO_PAD_AP_PWMEN, IO_LVL_LOW); +000040 2100 MOVS r1,#0 +000042 2008 MOVS r0,#8 +000044 f7fffffe BL hal_gpio_set_output_data +;;;415 #endif +;;;416 /* Wait AP reset down*/ +;;;417 hal_gpio_set_ap_reset_int(ENABLE, ap_rstn_pull_down_cb, DETECT_LOW_LVL); +000048 2201 MOVS r2,#1 +00004a 4908 LDR r1,|L8.108| +00004c 4610 MOV r0,r2 +00004e f7fffffe BL hal_gpio_set_ap_reset_int +;;;418 // sg_system_suspend=true; +;;;419 TAU_LOGD("enter sleep mode\n"); +000052 bf00 NOP +000054 23ff MOVS r3,#0xff +000056 33a4 ADDS r3,r3,#0xa4 +000058 a205 ADR r2,|L8.112| +00005a a106 ADR r1,|L8.116| +00005c 2000 MOVS r0,#0 +00005e f7fffffe BL tau_log_printf +000062 bf00 NOP +;;;420 // delayMs(500); +;;;421 return true; +000064 2001 MOVS r0,#1 +;;;422 } +000066 bd70 POP {r4-r6,pc} +;;;423 + ENDP + + |L8.104| + DCD g_tx_ctrl_handle + |L8.108| + DCD ap_rstn_pull_down_cb + |L8.112| +000070 70387000 DCB "p8p",0 + |L8.116| +000074 5b25735d DCB "[%s] (%04d) enter sleep mode\n",0 +000078 20282530 +00007c 34642920 +000080 656e7465 +000084 7220736c +000088 65657020 +00008c 6d6f6465 +000090 0a00 +000092 00 DCB 0 +000093 00 DCB 0 + + AREA ||i.ap_dcs_set_exit_idle_mode||, CODE, READONLY, ALIGN=2 + + ap_dcs_set_exit_idle_mode PROC +;;;532 */ +;;;533 static bool ap_dcs_set_exit_idle_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +000000 b570 PUSH {r4-r6,lr} +;;;534 { +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +;;;535 sg_exit_idle_mode_flag = true; +000006 2001 MOVS r0,#1 +000008 4909 LDR r1,|L9.48| +00000a 7008 STRB r0,[r1,#0] +;;;536 hal_dsi_rx_ctrl_set_hw_cmd_filter(g_rx_ctrl_handle, HAL_RX_DCS_FILTER_B, 0x2C, 0x2C); +00000c 232c MOVS r3,#0x2c +00000e 461a MOV r2,r3 +000010 210b MOVS r1,#0xb +000012 4808 LDR r0,|L9.52| +000014 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000016 f7fffffe BL hal_dsi_rx_ctrl_set_hw_cmd_filter +;;;537 TAU_LOGD("exit idle mode,skip 0x2C\n"); +00001a bf00 NOP +00001c 4b06 LDR r3,|L9.56| +00001e a207 ADR r2,|L9.60| +000020 a107 ADR r1,|L9.64| +000022 2000 MOVS r0,#0 +000024 f7fffffe BL tau_log_printf +000028 bf00 NOP +;;;538 return true; +00002a 2001 MOVS r0,#1 +;;;539 } +00002c bd70 POP {r4-r6,pc} +;;;540 + ENDP + +00002e 0000 DCW 0x0000 + |L9.48| + DCD sg_exit_idle_mode_flag + |L9.52| + DCD g_rx_ctrl_handle + |L9.56| + DCD 0x00000219 + |L9.60| +00003c 70387000 DCB "p8p",0 + |L9.64| +000040 5b25735d DCB "[%s] (%04d) exit idle mode,skip 0x2C\n",0 +000044 20282530 +000048 34642920 +00004c 65786974 +000050 2069646c +000054 65206d6f +000058 64652c73 +00005c 6b697020 +000060 30783243 +000064 0a00 +000066 00 DCB 0 +000067 00 DCB 0 + + AREA ||i.ap_dcs_set_exit_sleep_mode||, CODE, READONLY, ALIGN=2 + + ap_dcs_set_exit_sleep_mode PROC +;;;429 */ +;;;430 static bool ap_dcs_set_exit_sleep_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +000000 b570 PUSH {r4-r6,lr} +;;;431 { +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +;;;432 //#if AP_SWIRE_OUTPUT +;;;433 // /* AVDD 上电, 用于解决息屏开屏PPS不更新问题 */ +;;;434 // hal_gpio_set_output_data(IO_PAD_AP_PWMEN, IO_LVL_HIGH); +;;;435 //#endif +;;;436 +;;;437 #if TX_START_AFTER_APRST +;;;438 if (panel_display_done == false) +;;;439 { +;;;440 sg_tx_start_in_process = true; +;;;441 } +;;;442 #endif +;;;443 +;;;444 TAU_LOGD("exit sleep mode \n"); +000006 bf00 NOP +000008 23ff MOVS r3,#0xff +00000a 33bd ADDS r3,r3,#0xbd +00000c a203 ADR r2,|L10.28| +00000e a104 ADR r1,|L10.32| +000010 2000 MOVS r0,#0 +000012 f7fffffe BL tau_log_printf +000016 bf00 NOP +;;;445 +;;;446 return true; +000018 2001 MOVS r0,#1 +;;;447 } +00001a bd70 POP {r4-r6,pc} +;;;448 + ENDP + + |L10.28| +00001c 70387000 DCB "p8p",0 + |L10.32| +000020 5b25735d DCB "[%s] (%04d) exit sleep mode \n",0 +000024 20282530 +000028 34642920 +00002c 65786974 +000030 20736c65 +000034 6570206d +000038 6f646520 +00003c 0a00 +00003e 00 DCB 0 +00003f 00 DCB 0 + + AREA ||i.ap_dcs_set_frame_change||, CODE, READONLY, ALIGN=2 + + ap_dcs_set_frame_change PROC +;;;571 */ +;;;572 static bool ap_dcs_set_frame_change(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +000000 b570 PUSH {r4-r6,lr} +;;;573 { +000002 4605 MOV r5,r0 +000004 460c MOV r4,r1 +;;;574 if (dcs_packet->param_length == 1) +000006 68a0 LDR r0,[r4,#8] +000008 2801 CMP r0,#1 +00000a d10e BNE |L11.42| +;;;575 { +;;;576 if (dcs_packet->packet_param[0] == 0x18) +00000c 68e0 LDR r0,[r4,#0xc] +00000e 7800 LDRB r0,[r0,#0] +000010 2818 CMP r0,#0x18 +000012 d105 BNE |L11.32| +;;;577 { +;;;578 // hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle,TE_USER_MODE); +;;;579 hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); +000014 2100 MOVS r1,#0 +000016 4806 LDR r0,|L11.48| +000018 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +00001a f7fffffe BL hal_dsi_tx_ctrl_set_tear_mode +00001e e004 B |L11.42| + |L11.32| +;;;580 } +;;;581 else +;;;582 { +;;;583 // soft_te_timer_init(); +;;;584 hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_120HZ_MODE); +000020 2103 MOVS r1,#3 +000022 4803 LDR r0,|L11.48| +000024 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000026 f7fffffe BL hal_dsi_tx_ctrl_set_tear_mode + |L11.42| +;;;585 } +;;;586 } +;;;587 // TAU_LOGD("frame_change %x ,size %d, data %d\n", dcs_packet->dcs_command, dcs_packet->param_length, dcs_packet->packet_param[0]); +;;;588 return true; +00002a 2001 MOVS r0,#1 +;;;589 } +00002c bd70 POP {r4-r6,pc} +;;;590 + ENDP + +00002e 0000 DCW 0x0000 + |L11.48| + DCD g_tx_ctrl_handle + + AREA ||i.ap_rstn_pull_down_cb||, CODE, READONLY, ALIGN=2 + + ap_rstn_pull_down_cb PROC +;;;1753 */ +;;;1754 static void ap_rstn_pull_down_cb(void *data) +000000 b510 PUSH {r4,lr} +;;;1755 { +000002 4604 MOV r4,r0 +;;;1756 TAU_LOGD("ap_rstn_pull_down_cb\n"); +000004 bf00 NOP +000006 4b08 LDR r3,|L12.40| +000008 a208 ADR r2,|L12.44| +00000a a109 ADR r1,|L12.48| +00000c 2000 MOVS r0,#0 +00000e f7fffffe BL tau_log_printf +000012 bf00 NOP +;;;1757 sg_system_suspend = true; +000014 2001 MOVS r0,#1 +000016 490f LDR r1,|L12.84| +000018 7008 STRB r0,[r1,#0] +;;;1758 /* 关闭AP reset检查 */ +;;;1759 hal_gpio_set_ap_reset_int(DISABLE, NULL, DETECT_RISING_EDGE); +00001a 2202 MOVS r2,#2 +00001c 2100 MOVS r1,#0 +00001e 4608 MOV r0,r1 +000020 f7fffffe BL hal_gpio_set_ap_reset_int +;;;1760 // TAU_LOGD("ap_rstn_pull_down_cb\n"); +;;;1761 } +000024 bd10 POP {r4,pc} +;;;1762 + ENDP + +000026 0000 DCW 0x0000 + |L12.40| + DCD 0x000006dc + |L12.44| +00002c 70387000 DCB "p8p",0 + |L12.48| +000030 5b25735d DCB "[%s] (%04d) ap_rstn_pull_down_cb\n",0 +000034 20282530 +000038 34642920 +00003c 61705f72 +000040 73746e5f +000044 70756c6c +000048 5f646f77 +00004c 6e5f6362 +000050 0a00 +000052 00 DCB 0 +000053 00 DCB 0 + |L12.84| + DCD sg_system_suspend + + AREA ||i.ap_rstn_pull_high_cb||, CODE, READONLY, ALIGN=2 + + ap_rstn_pull_high_cb PROC +;;;1740 */ +;;;1741 static void ap_rstn_pull_high_cb(void *data) +000000 b510 PUSH {r4,lr} +;;;1742 { +000002 4604 MOV r4,r0 +;;;1743 /* system resume begin */ +;;;1744 sg_system_resume = true; +000004 2001 MOVS r0,#1 +000006 4904 LDR r1,|L13.24| +000008 7008 STRB r0,[r1,#0] +;;;1745 /* 关闭AP reset检查 */ +;;;1746 hal_gpio_set_ap_reset_int(DISABLE, NULL, DETECT_RISING_EDGE); +00000a 2202 MOVS r2,#2 +00000c 2100 MOVS r1,#0 +00000e 4608 MOV r0,r1 +000010 f7fffffe BL hal_gpio_set_ap_reset_int +;;;1747 } +000014 bd10 POP {r4,pc} +;;;1748 + ENDP + +000016 0000 DCW 0x0000 + |L13.24| + DCD sg_system_resume + + AREA ||i.ap_set_FPS_53||, CODE, READONLY, ALIGN=1 + + ap_set_FPS_53 PROC +;;;590 +;;;591 static bool ap_set_FPS_53(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +000000 b5fe PUSH {r1-r7,lr} +;;;592 { +000002 4606 MOV r6,r0 +000004 460c MOV r4,r1 +;;;593 uint8_t value_53 =0; +000006 2500 MOVS r5,#0 +;;;594 +;;;595 value_53 = dcs_packet->packet_param[0]; +000008 68e0 LDR r0,[r4,#0xc] +00000a 7805 LDRB r5,[r0,#0] +;;;596 +;;;597 if(value_53 == 0x30) // AP FPS ON +00000c 2d30 CMP r5,#0x30 +00000e d10c BNE |L14.42| +;;;598 { +;;;599 +;;;600 hal_dsi_tx_ctrl_write_cmd( 0x39, 0, 4, 0x97, 0x11, 0xCF, 0xFF); // DDIC FPS ON +000010 20ff MOVS r0,#0xff +000012 21cf MOVS r1,#0xcf +000014 2211 MOVS r2,#0x11 +000016 2397 MOVS r3,#0x97 +000018 9200 STR r2,[sp,#0] +00001a 9101 STR r1,[sp,#4] +00001c 9002 STR r0,[sp,#8] +00001e 2204 MOVS r2,#4 +000020 2100 MOVS r1,#0 +000022 2039 MOVS r0,#0x39 +000024 f7fffffe BL hal_dsi_tx_ctrl_write_cmd +000028 e00d B |L14.70| + |L14.42| +;;;601 +;;;602 } +;;;603 else if(value_53 == 0x20) // AP FPS OFF +00002a 2d20 CMP r5,#0x20 +00002c d10b BNE |L14.70| +;;;604 { +;;;605 +;;;606 hal_dsi_tx_ctrl_write_cmd( 0x39, 0, 4, 0x97, 0x00, 0xCF, 0xFF); // DDIC FPS OFF +00002e 20ff MOVS r0,#0xff +000030 21cf MOVS r1,#0xcf +000032 2200 MOVS r2,#0 +000034 2397 MOVS r3,#0x97 +000036 9200 STR r2,[sp,#0] +000038 9101 STR r1,[sp,#4] +00003a 9002 STR r0,[sp,#8] +00003c 2204 MOVS r2,#4 +00003e 2100 MOVS r1,#0 +000040 2039 MOVS r0,#0x39 +000042 f7fffffe BL hal_dsi_tx_ctrl_write_cmd + |L14.70| +;;;607 +;;;608 +;;;609 } +;;;610 +;;;611 // TAU_LOGD("B1[%x]", value_b1); +;;;612 return true; +000046 2001 MOVS r0,#1 +;;;613 } +000048 bdfe POP {r1-r7,pc} +;;;614 + ENDP + + + AREA ||i.app_display_init||, CODE, READONLY, ALIGN=1 + + app_display_init PROC +;;;1791 */ +;;;1792 void app_display_init(void) +000000 b510 PUSH {r4,lr} +;;;1793 { +;;;1794 /* mipi rx初始化 */ +;;;1795 app_mipi_rx_init(); +000002 f7fffffe BL app_mipi_rx_init +;;;1796 /* VCC 主供电,等待VCC Power Ready,此时RX初始化完成可以响应MIPI命令 */ +;;;1797 if (MAIN_POWER_SELECT == PWR_SEL_VCC) +;;;1798 { +;;;1799 +;;;1800 while (hal_pwr_get_vcc_power_ready() == false); +000006 bf00 NOP + |L15.8| +000008 f7fffffe BL hal_pwr_get_vcc_power_ready +00000c 2800 CMP r0,#0 +00000e d0fb BEQ |L15.8| +;;;1801 } +;;;1802 +;;;1803 /* GPIO 初始化 */ +;;;1804 app_gpio_init(); +000010 f7fffffe BL app_gpio_init +;;;1805 //TAU_LOGD("app_gpio_init \n"); +;;;1806 /* 背光初始化 */ +;;;1807 #if AP_SWIRE_OUTPUT +;;;1808 hal_swire_init(); /* swire init */ +000014 f7fffffe BL hal_swire_init +;;;1809 hal_swire_set_timer(TIMER_NUM0, 8, true); /* swire连续发送,绑定timer进行发送 */ +000018 2201 MOVS r2,#1 +00001a 2108 MOVS r1,#8 +00001c 2000 MOVS r0,#0 +00001e f7fffffe BL hal_swire_set_timer +;;;1810 #endif +;;;1811 #if ANALOG_PWM_OUTPUT +;;;1812 if (hal_pwm_init(PWM_FREQUENCY, PWM_DUTY_STEP)) +;;;1813 { +;;;1814 hal_pwm_enable(true); +;;;1815 hal_pwm_set_elvcc_output(true); +;;;1816 } +;;;1817 #endif +;;;1818 +;;;1819 /* mipi tx 初始化*/ +;;;1820 app_mipi_tx_init(); +000022 f7fffffe BL app_mipi_tx_init +;;;1821 // soft_te_timer_init(); +;;;1822 #if TX_START_AFTER_APRST +;;;1823 TAU_LOGD("wait exit sleep mode\n"); +;;;1824 #else +;;;1825 app_mipi_tx_start(); +000026 f7fffffe BL app_mipi_tx_start +;;;1826 #endif +;;;1827 } +00002a bd10 POP {r4,pc} +;;;1828 + ENDP + + + AREA ||i.app_gpio_init||, CODE, READONLY, ALIGN=2 + + app_gpio_init PROC +;;;1768 */ +;;;1769 void app_gpio_init(void) +000000 b51f PUSH {r0-r4,lr} +;;;1770 { +;;;1771 io_pad_attr_t attrs[] = +000002 4b05 LDR r3,|L16.24| +000004 cb0f LDM r3,{r0-r3} +000006 466c MOV r4,sp +000008 c40f STM r4!,{r0-r3} +;;;1772 { +;;;1773 {IO_PIN_8, PIN8_MODE_GPIO7, IO_IOE_OUTPUT, IO_LVL_LOW},/* PIN_8(TD_RSTN), GPIO,输出,低电平 */ +;;;1774 {IO_PIN_17, PIN17_MODE_GPIO8, IO_IOE_OUTPUT, IO_LVL_LOW}, /* PIN_17(PWMEN), GPIO,输出,低电平 */ +;;;1775 {IO_PIN_16, PIN16_MODE_GPIO2, IO_IOE_OUTPUT, IO_LVL_LOW}, /* PIN_16(AP_INT),GPIO,输出,低电平 */ +;;;1776 #if (TX_USE_CMD_MODE & (!TX_CMD_MODE_WITHOUT_TE)) +;;;1777 {IO_PIN_14, PIN14_MODE_GPIO24, IO_IOE_INPUT, IO_LVL_NONE}, /* PIN_29(AP_TE), cmd mode输出, 并且看屏TE,配置AP TE为GPIO输入 */ +;;;1778 #endif +;;;1779 {IO_PIN_29, PIN29_MODE_TEAR, IO_IOE_NONE, IO_LVL_NONE}, /* PIN_29(AP_TE), 硬件TEAR输出模式 */ +;;;1780 +;;;1781 }; +;;;1782 uint8_t size = sizeof(attrs) / sizeof(io_pad_attr_t); +00000a 2404 MOVS r4,#4 +;;;1783 hal_gpio_config_pad(attrs, size); +00000c 4621 MOV r1,r4 +00000e 4668 MOV r0,sp +000010 f7fffffe BL hal_gpio_config_pad +;;;1784 } +000014 bd1f POP {r0-r4,pc} +;;;1785 + ENDP + +000016 0000 DCW 0x0000 + |L16.24| + DCD ||.constdata||+0x20ac + + AREA ||i.app_init_panel||, CODE, READONLY, ALIGN=2 + + app_init_panel PROC +;;;1472 */ +;;;1473 static void app_init_panel(void) +000000 b510 PUSH {r4,lr} +;;;1474 { +;;;1475 /* reset panel*/ +;;;1476 app_tx_panel_reset(); +000002 f7fffffe BL app_tx_panel_reset +;;;1477 #if PANEL_INIT_CODE_ARRAY +;;;1478 send_panel_init_code(sizeof(panel_init_code), (uint8_t *) panel_init_code); +000006 4909 LDR r1,|L17.44| +000008 4809 LDR r0,|L17.48| +00000a f7fffffe BL send_panel_init_code +;;;1479 #endif +;;;1480 hal_gpio_init_output(IO_PAD_AP_PWMEN, IO_LVL_HIGH); +00000e 2101 MOVS r1,#1 +000010 2008 MOVS r0,#8 +000012 f7fffffe BL hal_gpio_init_output +;;;1481 delayMs(90); +000016 205a MOVS r0,#0x5a +000018 f7fffffe BL delayMs +;;;1482 #if AP_SWIRE_OUTPUT +;;;1483 hal_swire_enable(true); +00001c 2001 MOVS r0,#1 +00001e f7fffffe BL hal_swire_enable +;;;1484 hal_swire_set_pulse(SWIRE_DEFAULT_PULSE); +000022 201f MOVS r0,#0x1f +000024 f7fffffe BL hal_swire_set_pulse +;;;1485 #endif +;;;1486 // hal_gpio_init_output(IO_PAD_AP_SWIRE, IO_LVL_HIGH); +;;;1487 // Gpio_swire_output(2, 40); +;;;1488 +;;;1489 // TAU_LOGD("Panel init!\n\r"); +;;;1490 } +000028 bd10 POP {r4,pc} +;;;1491 + ENDP + +00002a 0000 DCW 0x0000 + |L17.44| + DCD panel_init_code + |L17.48| + DCD 0x0000204c + + AREA ||i.app_mipi_rx_init||, CODE, READONLY, ALIGN=2 + + app_mipi_rx_init PROC +;;;1549 */ +;;;1550 static void app_mipi_rx_init(void) +000000 b510 PUSH {r4,lr} +;;;1551 { +;;;1552 if (g_rx_ctrl_handle == NULL) +000002 4839 LDR r0,|L18.232| +000004 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000006 2800 CMP r0,#0 +000008 d103 BNE |L18.18| +;;;1553 { +;;;1554 /* 创建rx ctrl handle */ +;;;1555 g_rx_ctrl_handle = hal_dsi_rx_ctrl_create_handle(); +00000a f7fffffe BL hal_dsi_rx_ctrl_create_handle +00000e 4936 LDR r1,|L18.232| +000010 6008 STR r0,[r1,#0] ; g_rx_ctrl_handle + |L18.18| +;;;1556 } +;;;1557 /* 配置参数 */ +;;;1558 g_rx_ctrl_handle->base_info.src_w = INPUT_WIDTH; +000012 2015 MOVS r0,#0x15 +000014 0180 LSLS r0,r0,#6 +000016 4934 LDR r1,|L18.232| +000018 6809 LDR r1,[r1,#0] ; g_rx_ctrl_handle +00001a 6008 STR r0,[r1,#0] +;;;1559 g_rx_ctrl_handle->base_info.src_h = INPUT_HEIGHT; +00001c 20bb MOVS r0,#0xbb +00001e 0100 LSLS r0,r0,#4 +000020 4931 LDR r1,|L18.232| +000022 6809 LDR r1,[r1,#0] ; g_rx_ctrl_handle +000024 6048 STR r0,[r1,#4] +;;;1560 g_rx_ctrl_handle->base_info.dst_w = OUTPUT_WIDTH; +000026 2087 MOVS r0,#0x87 +000028 00c0 LSLS r0,r0,#3 +00002a 492f LDR r1,|L18.232| +00002c 6809 LDR r1,[r1,#0] ; g_rx_ctrl_handle +00002e 6088 STR r0,[r1,#8] +;;;1561 g_rx_ctrl_handle->base_info.dst_h = OUTPUT_HEIGHT; +000030 204b MOVS r0,#0x4b +000032 0140 LSLS r0,r0,#5 +000034 492c LDR r1,|L18.232| +000036 6809 LDR r1,[r1,#0] ; g_rx_ctrl_handle +000038 60c8 STR r0,[r1,#0xc] +;;;1562 g_rx_ctrl_handle->base_info.src_frate = INPUT_FRAME_RATE; +00003a 2002 MOVS r0,#2 +00003c 492a LDR r1,|L18.232| +00003e 6809 LDR r1,[r1,#0] ; g_rx_ctrl_handle +000040 7408 STRB r0,[r1,#0x10] +;;;1563 g_rx_ctrl_handle->base_info.src_mode = INPUT_DATA_MODE; +000042 2001 MOVS r0,#1 +000044 4928 LDR r1,|L18.232| +000046 6809 LDR r1,[r1,#0] ; g_rx_ctrl_handle +000048 7448 STRB r0,[r1,#0x11] +;;;1564 g_rx_ctrl_handle->base_info.dst_mode = OUTPUT_DATA_MODE; +00004a 2000 MOVS r0,#0 +00004c 4926 LDR r1,|L18.232| +00004e 6809 LDR r1,[r1,#0] ; g_rx_ctrl_handle +000050 7488 STRB r0,[r1,#0x12] +;;;1565 g_rx_ctrl_handle->rx_color_mode = INPUT_COLOR_MODE; +000052 2104 MOVS r1,#4 +000054 4824 LDR r0,|L18.232| +000056 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000058 3020 ADDS r0,r0,#0x20 +00005a 7481 STRB r1,[r0,#0x12] +;;;1566 g_rx_ctrl_handle->rx_lanes = INPUT_MIPI_LANE_NUM; +00005c 4822 LDR r0,|L18.232| +00005e 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000060 3020 ADDS r0,r0,#0x20 +000062 74c1 STRB r1,[r0,#0x13] +;;;1567 g_rx_ctrl_handle->rx_nonburst_models = INPUT_VIDEO_MODEL; /* 可不配置 */ +000064 2101 MOVS r1,#1 +000066 4820 LDR r0,|L18.232| +000068 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +00006a 3020 ADDS r0,r0,#0x20 +00006c 7501 STRB r1,[r0,#0x14] +;;;1568 g_rx_ctrl_handle->compress_en = INPUT_COMPRESS; +00006e 481e LDR r0,|L18.232| +000070 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000072 3020 ADDS r0,r0,#0x20 +000074 7541 STRB r1,[r0,#0x15] +;;;1569 g_rx_ctrl_handle->rx_hsclk_rate = INPUT_MIPI_LANE_RATE; +000076 481d LDR r0,|L18.236| +000078 491b LDR r1,|L18.232| +00007a 6809 LDR r1,[r1,#0] ; g_rx_ctrl_handle +00007c 6388 STR r0,[r1,#0x38] +;;;1570 g_rx_ctrl_handle->cus_dcs_entry_table = g_cus_rx_dcs_execute_table; /* 注册 DCS处理列表 */ +00007e 491c LDR r1,|L18.240| +000080 4819 LDR r0,|L18.232| +000082 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000084 3080 ADDS r0,r0,#0x80 +000086 63c1 STR r1,[r0,#0x3c] +;;;1571 g_rx_ctrl_handle->rx_dcs_read_entry = ap_dcs_read; /* 注册dsc read 回调函数,可选,此函数为空时由cus_dcs_entry_table执行 */ +000088 491a LDR r1,|L18.244| +00008a 4817 LDR r0,|L18.232| +00008c 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +00008e 3080 ADDS r0,r0,#0x80 +000090 6401 STR r1,[r0,#0x40] +;;;1572 // g_rx_ctrl_handle->hight_performan_mode=HIGHT_PERFORMAN_L2; +;;;1573 g_rx_ctrl_handle->extra_info.crop_info.top =12; //4 8 的倍数 +000092 210c MOVS r1,#0xc +000094 4814 LDR r0,|L18.232| +000096 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000098 8381 STRH r1,[r0,#0x1c] +;;;1574 g_rx_ctrl_handle->extra_info.crop_info.enable=1; +00009a 2101 MOVS r1,#1 +00009c 4812 LDR r0,|L18.232| +00009e 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +0000a0 3018 ADDS r0,r0,#0x18 +0000a2 7301 STRB r1,[r0,#0xc] +;;;1575 #if RX_RESOLUTION_CHANGE_ENABLE +;;;1576 g_rx_ctrl_handle->pps_update_entry = pps_update_handle; +0000a4 4914 LDR r1,|L18.248| +0000a6 4810 LDR r0,|L18.232| +0000a8 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +0000aa 3080 ADDS r0,r0,#0x80 +0000ac 6441 STR r1,[r0,#0x44] +;;;1577 #endif +;;;1578 /* 提前预置PPS, AP 有PPS cmd也会更新 */ +;;;1579 if (g_rx_ctrl_handle->compress_en == true) +0000ae 480e LDR r0,|L18.232| +0000b0 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +0000b2 3020 ADDS r0,r0,#0x20 +0000b4 7d40 LDRB r0,[r0,#0x15] +0000b6 2801 CMP r0,#1 +0000b8 d105 BNE |L18.198| +;;;1580 { +;;;1581 hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps, 128); +0000ba 2280 MOVS r2,#0x80 +0000bc 490f LDR r1,|L18.252| +0000be 480a LDR r0,|L18.232| +0000c0 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +0000c2 f7fffffe BL hal_dsi_rx_ctrl_pre_init_pps + |L18.198| +;;;1582 } +;;;1583 +;;;1584 /* 初始化rx ctrl */ +;;;1585 hal_dsi_rx_ctrl_init(g_rx_ctrl_handle); +0000c6 4808 LDR r0,|L18.232| +0000c8 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +0000ca f7fffffe BL hal_dsi_rx_ctrl_init +;;;1586 +;;;1587 #if RX_READ_HW_ACK +;;;1588 /* 配置硬件回复 */ +;;;1589 app_set_dcs_hw_ack(); +;;;1590 #endif +;;;1591 +;;;1592 #if TX_CMD_MODE_WITHOUT_TE +;;;1593 /* 注册接收一帧帧头事件回调,每接收一帧数据TX再往外发一帧 */ +;;;1594 //hal_dsi_rx_ctrl_register_callback(g_rx_ctrl_handle, app_rx_event_cb, HAL_RX_FS_EVENT, true, NULL); +;;;1595 /* 注册接收第0行数据事件,接收到数据后再往外发送数据,确保不撕裂 */ +;;;1596 uint32_t line = 0; +;;;1597 hal_dsi_rx_ctrl_register_callback(g_rx_ctrl_handle, app_rx_event_cb, HAL_RX_LINE_EVENT, true, &line); +;;;1598 #endif +;;;1599 +;;;1600 #if RX_START_WITHOUT_RST +;;;1601 /* 等待ap reset置位再启动rx,否则容易收到错误数据 */ +;;;1602 hal_dsi_rx_ctrl_start(g_rx_ctrl_handle); +0000ce 4806 LDR r0,|L18.232| +0000d0 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +0000d2 f7fffffe BL hal_dsi_rx_ctrl_start +;;;1603 #else +;;;1604 /* 注册RX start callback,确认RX LP11时再启动RX,防止接收错误数据 */ +;;;1605 hal_gpio_set_ap_reset_int(ENABLE, app_mipi_rx_start_cb, DETECT_HIGH_LVL); +;;;1606 #endif +;;;1607 TAU_LOGD("rx init!\n\r"); +0000d6 bf00 NOP +0000d8 4b09 LDR r3,|L18.256| +0000da a20a ADR r2,|L18.260| +0000dc a10a ADR r1,|L18.264| +0000de 2000 MOVS r0,#0 +0000e0 f7fffffe BL tau_log_printf +0000e4 bf00 NOP +;;;1608 } +0000e6 bd10 POP {r4,pc} +;;;1609 + ENDP + + |L18.232| + DCD g_rx_ctrl_handle + |L18.236| + DCD 0x5f5e1000 + |L18.240| + DCD g_cus_rx_dcs_execute_table + |L18.244| + DCD ap_dcs_read + |L18.248| + DCD pps_update_handle + |L18.252| + DCD pps + |L18.256| + DCD 0x00000647 + |L18.260| +000104 70387000 DCB "p8p",0 + |L18.264| +000108 5b25735d DCB "[%s] (%04d) rx init!\n\r",0 +00010c 20282530 +000110 34642920 +000114 72782069 +000118 6e697421 +00011c 0a0d00 +00011f 00 DCB 0 + + AREA ||i.app_mipi_tx_init||, CODE, READONLY, ALIGN=2 + + app_mipi_tx_init PROC +;;;1614 */ +;;;1615 static void app_mipi_tx_init(void) +000000 b510 PUSH {r4,lr} +;;;1616 { +;;;1617 if (g_tx_ctrl_handle == NULL) +000002 4835 LDR r0,|L19.216| +000004 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000006 2800 CMP r0,#0 +000008 d103 BNE |L19.18| +;;;1618 { +;;;1619 g_tx_ctrl_handle = hal_dsi_tx_ctrl_create_handle(); +00000a f7fffffe BL hal_dsi_tx_ctrl_create_handle +00000e 4932 LDR r1,|L19.216| +000010 6008 STR r0,[r1,#0] ; g_tx_ctrl_handle + |L19.18| +;;;1620 } +;;;1621 g_tx_ctrl_handle->channel_id = OUTPUT_VC; +000012 2100 MOVS r1,#0 +000014 4830 LDR r0,|L19.216| +000016 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000018 3020 ADDS r0,r0,#0x20 +00001a 7601 STRB r1,[r0,#0x18] +;;;1622 g_tx_ctrl_handle->lane_num = OUTPUT_LANE_NUMBER; +00001c 2104 MOVS r1,#4 +00001e 482e LDR r0,|L19.216| +000020 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000022 3020 ADDS r0,r0,#0x20 +000024 7501 STRB r1,[r0,#0x14] +;;;1623 g_tx_ctrl_handle->vid_mode = OUTPUT_VIDEO_MODEL; +000026 2102 MOVS r1,#2 +000028 482b LDR r0,|L19.216| +00002a 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +00002c 3020 ADDS r0,r0,#0x20 +00002e 7641 STRB r1,[r0,#0x19] +;;;1624 g_tx_ctrl_handle->cmd_tx_type = TX_INIT_TYPE; +000030 2101 MOVS r1,#1 +000032 4829 LDR r0,|L19.216| +000034 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000036 3020 ADDS r0,r0,#0x20 +000038 7681 STRB r1,[r0,#0x1a] +;;;1625 g_tx_ctrl_handle->dpi_vsa = OUTPUT_VSA; +00003a 2001 MOVS r0,#1 +00003c 4926 LDR r1,|L19.216| +00003e 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +000040 6188 STR r0,[r1,#0x18] +;;;1626 g_tx_ctrl_handle->dpi_vbp = OUTPUT_VBP; +000042 2013 MOVS r0,#0x13 +000044 4924 LDR r1,|L19.216| +000046 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +000048 61c8 STR r0,[r1,#0x1c] +;;;1627 g_tx_ctrl_handle->dpi_vfp = OUTPUT_VFP; +00004a 200c MOVS r0,#0xc +00004c 4922 LDR r1,|L19.216| +00004e 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +000050 6208 STR r0,[r1,#0x20] +;;;1628 g_tx_ctrl_handle->dpi_hsa = OUTPUT_HSA; +000052 2001 MOVS r0,#1 +000054 4920 LDR r1,|L19.216| +000056 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +000058 6248 STR r0,[r1,#0x24] +;;;1629 g_tx_ctrl_handle->dpi_hbp = OUTPUT_HBP; +00005a 201b MOVS r0,#0x1b +00005c 491e LDR r1,|L19.216| +00005e 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +000060 6288 STR r0,[r1,#0x28] +;;;1630 g_tx_ctrl_handle->dpi_hfp = OUTPUT_HFP; +000062 204d MOVS r0,#0x4d +000064 491c LDR r1,|L19.216| +000066 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +000068 62c8 STR r0,[r1,#0x2c] +;;;1631 g_tx_ctrl_handle->base_info.src_w = INPUT_WIDTH; +00006a 2015 MOVS r0,#0x15 +00006c 0180 LSLS r0,r0,#6 +00006e 491a LDR r1,|L19.216| +000070 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +000072 6008 STR r0,[r1,#0] +;;;1632 g_tx_ctrl_handle->base_info.src_h = INPUT_HEIGHT; +000074 20bb MOVS r0,#0xbb +000076 0100 LSLS r0,r0,#4 +000078 4917 LDR r1,|L19.216| +00007a 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +00007c 6048 STR r0,[r1,#4] +;;;1633 g_tx_ctrl_handle->base_info.dst_w = OUTPUT_WIDTH; +00007e 2087 MOVS r0,#0x87 +000080 00c0 LSLS r0,r0,#3 +000082 4915 LDR r1,|L19.216| +000084 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +000086 6088 STR r0,[r1,#8] +;;;1634 g_tx_ctrl_handle->base_info.dst_h = OUTPUT_HEIGHT; +000088 204b MOVS r0,#0x4b +00008a 0140 LSLS r0,r0,#5 +00008c 4912 LDR r1,|L19.216| +00008e 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +000090 60c8 STR r0,[r1,#0xc] +;;;1635 g_tx_ctrl_handle->base_info.src_frate = INPUT_FRAME_RATE; +000092 2002 MOVS r0,#2 +000094 4910 LDR r1,|L19.216| +000096 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +000098 7408 STRB r0,[r1,#0x10] +;;;1636 g_tx_ctrl_handle->base_info.src_mode = INPUT_DATA_MODE; +00009a 2001 MOVS r0,#1 +00009c 490e LDR r1,|L19.216| +00009e 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +0000a0 7448 STRB r0,[r1,#0x11] +;;;1637 g_tx_ctrl_handle->base_info.dst_mode = OUTPUT_DATA_MODE; +0000a2 2000 MOVS r0,#0 +0000a4 490c LDR r1,|L19.216| +0000a6 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +0000a8 7488 STRB r0,[r1,#0x12] +;;;1638 g_tx_ctrl_handle->tx_frame_rate=58; +0000aa 480c LDR r0,|L19.220| +0000ac 490a LDR r1,|L19.216| +0000ae 6809 LDR r1,[r1,#0] ; g_tx_ctrl_handle +0000b0 6308 STR r0,[r1,#0x30] +;;;1639 // g_tx_ctrl_handle->tx_lane_lp = 2; +;;;1640 +;;;1641 /* 初始化屏时每一条LP CMD都退出LPDT 再进入发送下一条 */ +;;;1642 /* 解决FT8720 TDDI 显示翻转问题 */ +;;;1643 // g_tx_ctrl_handle->lp_exit_lpdt = true; +;;;1644 +;;;1645 hal_dsi_tx_ctrl_init(g_tx_ctrl_handle); +0000b2 4809 LDR r0,|L19.216| +0000b4 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +0000b6 f7fffffe BL hal_dsi_tx_ctrl_init +;;;1646 // hal_dsi_tx_ctrl_set_cus_sync_line(g_tx_ctrl_handle,1200); //1200 +;;;1647 +;;;1648 /* FIXME set tear on*/ +;;;1649 // hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); +;;;1650 +;;;1651 /* AP 没有发送数据时默认的显示颜色, 量产为0 0 0(黑色), 配置其他颜色仅为debug使用 */ +;;;1652 hal_dsi_tx_ctrl_set_overwrite_rgb(0x00, 0x00, 0x00); +0000ba 2200 MOVS r2,#0 +0000bc 4611 MOV r1,r2 +0000be 4610 MOV r0,r2 +0000c0 f7fffffe BL hal_dsi_tx_ctrl_set_overwrite_rgb +;;;1653 TAU_LOGD("tx init!\n\r"); +0000c4 bf00 NOP +0000c6 4b06 LDR r3,|L19.224| +0000c8 a206 ADR r2,|L19.228| +0000ca a107 ADR r1,|L19.232| +0000cc 2000 MOVS r0,#0 +0000ce f7fffffe BL tau_log_printf +0000d2 bf00 NOP +;;;1654 } +0000d4 bd10 POP {r4,pc} +;;;1655 + ENDP + +0000d6 0000 DCW 0x0000 + |L19.216| + DCD g_tx_ctrl_handle + |L19.220| + DCD 0x42680000 + |L19.224| + DCD 0x00000675 + |L19.228| +0000e4 70387000 DCB "p8p",0 + |L19.232| +0000e8 5b25735d DCB "[%s] (%04d) tx init!\n\r",0 +0000ec 20282530 +0000f0 34642920 +0000f4 74782069 +0000f8 6e697421 +0000fc 0a0d00 +0000ff 00 DCB 0 + + AREA ||i.app_mipi_tx_start||, CODE, READONLY, ALIGN=2 + + app_mipi_tx_start PROC +;;;1693 */ +;;;1694 static void app_mipi_tx_start(void) +000000 b510 PUSH {r4,lr} +;;;1695 { +;;;1696 // TAU_LOGD("tx_start \n"); +;;;1697 /* Init panel */ +;;;1698 app_init_panel(); +000002 f7fffffe BL app_init_panel +;;;1699 /* TX start */ +;;;1700 hal_dsi_tx_ctrl_start(g_tx_ctrl_handle); +000006 481a LDR r0,|L20.112| +000008 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +00000a f7fffffe BL hal_dsi_tx_ctrl_start +;;;1701 +;;;1702 #if RX_WAIT_TEAR_ON +;;;1703 te_mode_e default_te = sg_ap_set_tear_on ? TE_60HZ_MODE : TE_USER_MODE; +;;;1704 hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, default_te); +;;;1705 #else +;;;1706 hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); +00000e 2100 MOVS r1,#0 +000010 4817 LDR r0,|L20.112| +000012 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000014 f7fffffe BL hal_dsi_tx_ctrl_set_tear_mode +;;;1707 #endif +;;;1708 +;;;1709 panel_display_done = true; +000018 2001 MOVS r0,#1 +00001a 4916 LDR r1,|L20.116| +00001c 7008 STRB r0,[r1,#0] +;;;1710 if(g_tx_ctrl_handle->base_info.src_w==1008) +00001e 4814 LDR r0,|L20.112| +000020 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000022 6800 LDR r0,[r0,#0] +000024 213f MOVS r1,#0x3f +000026 0109 LSLS r1,r1,#4 +000028 4288 CMP r0,r1 +00002a d10c BNE |L20.70| +;;;1711 { +;;;1712 hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps_fhd, 128); +00002c 2280 MOVS r2,#0x80 +00002e 4912 LDR r1,|L20.120| +000030 4812 LDR r0,|L20.124| +000032 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000034 f7fffffe BL hal_dsi_rx_ctrl_pre_init_pps +;;;1713 hal_dsi_rx_ctrl_toggle_resolution(g_rx_ctrl_handle); +000038 4810 LDR r0,|L20.124| +00003a 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +00003c f7fffffe BL hal_dsi_rx_ctrl_toggle_resolution +;;;1714 g_resolution_change = false; +000040 2000 MOVS r0,#0 +000042 490f LDR r1,|L20.128| +000044 7008 STRB r0,[r1,#0] + |L20.70| +;;;1715 // TAU_LOGD("pps_update!!\r\n"); +;;;1716 } +;;;1717 // soft_te_timer_init(); +;;;1718 delayMs(80); +000046 2050 MOVS r0,#0x50 +000048 f7fffffe BL delayMs +;;;1719 // Panel_CCM(); +;;;1720 // delayMs(20); +;;;1721 /* Display on */ +;;;1722 hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x29); +00004c 2329 MOVS r3,#0x29 +00004e 2201 MOVS r2,#1 +000050 2100 MOVS r1,#0 +000052 2005 MOVS r0,#5 +000054 f7fffffe BL hal_dsi_tx_ctrl_write_cmd +;;;1723 +;;;1724 #if AP_SWIRE_OUTPUT +;;;1725 hal_swire_set_pulse(SWIRE_DEFAULT_PULSE); +000058 201f MOVS r0,#0x1f +00005a f7fffffe BL hal_swire_set_pulse +;;;1726 #endif +;;;1727 +;;;1728 #if (TX_USE_CMD_MODE & (!TX_CMD_MODE_WITHOUT_TE)) +;;;1729 // hal_dsi_tx_ctrl_gen_a_frame(); /* FIXME */ +;;;1730 app_tx_cmd_app_init_panel_te_int(IO_PIN_14, DETECT_RISING_EDGE); /* 注册屏端TE中断 */ +;;;1731 #endif +;;;1732 +;;;1733 TAU_LOGD("tx_start \n"); +00005e bf00 NOP +000060 4b08 LDR r3,|L20.132| +000062 a209 ADR r2,|L20.136| +000064 a109 ADR r1,|L20.140| +000066 2000 MOVS r0,#0 +000068 f7fffffe BL tau_log_printf +00006c bf00 NOP +;;;1734 } +00006e bd10 POP {r4,pc} +;;;1735 + ENDP + + |L20.112| + DCD g_tx_ctrl_handle + |L20.116| + DCD panel_display_done + |L20.120| + DCD pps_fhd + |L20.124| + DCD g_rx_ctrl_handle + |L20.128| + DCD g_resolution_change + |L20.132| + DCD 0x000006c5 + |L20.136| +000088 70387000 DCB "p8p",0 + |L20.140| +00008c 5b25735d DCB "[%s] (%04d) tx_start \n",0 +000090 20282530 +000094 34642920 +000098 74785f73 +00009c 74617274 +0000a0 200a00 +0000a3 00 DCB 0 + + AREA ||i.app_system_process||, CODE, READONLY, ALIGN=2 + + app_system_process PROC +;;;1925 */ +;;;1926 static void app_system_process(void) +000000 b510 PUSH {r4,lr} +;;;1927 { +;;;1928 +;;;1929 if (sg_system_suspend) +000002 480e LDR r0,|L21.60| +000004 7800 LDRB r0,[r0,#0] ; sg_system_suspend +000006 2800 CMP r0,#0 +000008 d00d BEQ |L21.38| +;;;1930 { +;;;1931 TAU_LOGD("app_system_process\n"); +00000a bf00 NOP +00000c 4b0c LDR r3,|L21.64| +00000e a20d ADR r2,|L21.68| +000010 a10d ADR r1,|L21.72| +000012 2000 MOVS r0,#0 +000014 f7fffffe BL tau_log_printf +000018 bf00 NOP +;;;1932 /* 系统进入sleep mode */ +;;;1933 app_system_suspend(SLEEP_MODE_SELECT); +00001a 2002 MOVS r0,#2 +00001c f7fffffe BL app_system_suspend +;;;1934 sg_system_suspend = false; +000020 2000 MOVS r0,#0 +000022 4906 LDR r1,|L21.60| +000024 7008 STRB r0,[r1,#0] + |L21.38| +;;;1935 } +;;;1936 +;;;1937 if (sg_system_resume) +000026 4810 LDR r0,|L21.104| +000028 7800 LDRB r0,[r0,#0] ; sg_system_resume +00002a 2800 CMP r0,#0 +00002c d005 BEQ |L21.58| +;;;1938 { +;;;1939 /* 系统退出sleep mode */ +;;;1940 app_system_resume(SLEEP_MODE_SELECT); +00002e 2002 MOVS r0,#2 +000030 f7fffffe BL app_system_resume +;;;1941 sg_system_resume = false; +000034 2000 MOVS r0,#0 +000036 490c LDR r1,|L21.104| +000038 7008 STRB r0,[r1,#0] + |L21.58| +;;;1942 } +;;;1943 +;;;1944 #if TX_START_AFTER_APRST +;;;1945 if (sg_tx_start_in_process) +;;;1946 { +;;;1947 app_mipi_tx_start(); +;;;1948 sg_tx_start_in_process = false; +;;;1949 } +;;;1950 #endif +;;;1951 } +00003a bd10 POP {r4,pc} +;;;1952 + ENDP + + |L21.60| + DCD sg_system_suspend + |L21.64| + DCD 0x0000078b + |L21.68| +000044 70387000 DCB "p8p",0 + |L21.72| +000048 5b25735d DCB "[%s] (%04d) app_system_process\n",0 +00004c 20282530 +000050 34642920 +000054 6170705f +000058 73797374 +00005c 656d5f70 +000060 726f6365 +000064 73730a00 + |L21.104| + DCD sg_system_resume + + AREA ||i.app_system_resume||, CODE, READONLY, ALIGN=2 + + app_system_resume PROC +;;;1833 */ +;;;1834 static void app_system_resume(pwr_sleep_mode_e sleep_mode) +000000 b510 PUSH {r4,lr} +;;;1835 { +000002 4604 MOV r4,r0 +;;;1836 /* 退出sleep mode, 电源切换 */ +;;;1837 hal_pwr_exit_sleep_mode(); +000004 f7fffffe BL hal_pwr_exit_sleep_mode +;;;1838 +;;;1839 /* display resume */ +;;;1840 app_display_init(); +000008 f7fffffe BL app_display_init +;;;1841 +;;;1842 #if TOUCH_ENABLE +;;;1843 /* touch resume */ +;;;1844 app_tp_write_other_operations(NULL, 0); +;;;1845 #endif +;;;1846 TAU_LOGD("system resume\n"); +00000c bf00 NOP +00000e 4b04 LDR r3,|L22.32| +000010 a204 ADR r2,|L22.36| +000012 a105 ADR r1,|L22.40| +000014 2000 MOVS r0,#0 +000016 f7fffffe BL tau_log_printf +00001a bf00 NOP +;;;1847 } +00001c bd10 POP {r4,pc} +;;;1848 + ENDP + +00001e 0000 DCW 0x0000 + |L22.32| + DCD 0x00000736 + |L22.36| +000024 70387000 DCB "p8p",0 + |L22.40| +000028 5b25735d DCB "[%s] (%04d) system resume\n",0 +00002c 20282530 +000030 34642920 +000034 73797374 +000038 656d2072 +00003c 6573756d +000040 650a00 +000043 00 DCB 0 + + AREA ||i.app_system_suspend||, CODE, READONLY, ALIGN=2 + + app_system_suspend PROC +;;;1853 */ +;;;1854 static void app_system_suspend(pwr_sleep_mode_e sleep_mode) +000000 b538 PUSH {r3-r5,lr} +;;;1855 { +000002 4605 MOV r5,r0 +;;;1856 // TAU_LOGD("SLEEP_MODE\n"); +;;;1857 /* 关闭图像通路 */ +;;;1858 hal_dsi_tx_ctrl_stop(g_tx_ctrl_handle); +000004 4831 LDR r0,|L23.204| +000006 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000008 f7fffffe BL hal_dsi_tx_ctrl_stop +;;;1859 hal_dsi_tx_ctrl_deinit(g_tx_ctrl_handle); +00000c 482f LDR r0,|L23.204| +00000e 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000010 f7fffffe BL hal_dsi_tx_ctrl_deinit +;;;1860 hal_dsi_rx_ctrl_stop(g_rx_ctrl_handle); +000014 482e LDR r0,|L23.208| +000016 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000018 f7fffffe BL hal_dsi_rx_ctrl_stop +;;;1861 hal_dsi_rx_ctrl_deinit(g_rx_ctrl_handle); +00001c 482c LDR r0,|L23.208| +00001e 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000020 f7fffffe BL hal_dsi_rx_ctrl_deinit +;;;1862 +;;;1863 /* Tear拉低 */ +;;;1864 hal_gpio_init_output(IO_PAD_AP_TE, IO_LVL_LOW); +000024 2100 MOVS r1,#0 +000026 2003 MOVS r0,#3 +000028 f7fffffe BL hal_gpio_init_output +;;;1865 panel_display_done = false; +00002c 2000 MOVS r0,#0 +00002e 4929 LDR r1,|L23.212| +000030 7008 STRB r0,[r1,#0] +;;;1866 #if RX_WAIT_TEAR_ON +;;;1867 sg_ap_set_tear_on = false; +;;;1868 #endif +;;;1869 +;;;1870 /* 关闭外设 比如Swire/I2C/Flash 等 */ +;;;1871 #if AP_SWIRE_OUTPUT +;;;1872 hal_swire_deinit(); +000032 f7fffffe BL hal_swire_deinit +;;;1873 #endif +;;;1874 #if ANALOG_PWM_OUTPUT +;;;1875 hal_pwm_deinit(); +;;;1876 #endif +;;;1877 +;;;1878 #if SHARE_FLASH_ENABLE +;;;1879 hal_flash_share_mode(false); +;;;1880 #endif +;;;1881 +;;;1882 /* 切换TP18 供电 */ +;;;1883 hal_pwr_set_sleep_mode_power(SLEEP_MODE_POWER); +000036 2004 MOVS r0,#4 +000038 f7fffffe BL hal_pwr_set_sleep_mode_power +;;;1884 +;;;1885 if (sleep_mode == PWR_NORMAL_SLEEP_MODE) +00003c 2d00 CMP r5,#0 +00003e d10e BNE |L23.94| +;;;1886 { +;;;1887 /* normal sleep mode, MCU可以正常工作 */ +;;;1888 hal_gpio_set_ap_reset_int(ENABLE, ap_rstn_pull_high_cb, DETECT_HIGH_LVL); +000040 2200 MOVS r2,#0 +000042 4925 LDR r1,|L23.216| +000044 2001 MOVS r0,#1 +000046 f7fffffe BL hal_gpio_set_ap_reset_int +;;;1889 hal_pwr_enter_normal_sleep_mode(); +00004a f7fffffe BL hal_pwr_enter_normal_sleep_mode +;;;1890 TAU_LOGD("PWR_NORMAL_SLEEP_MODE\n"); +00004e bf00 NOP +000050 4b22 LDR r3,|L23.220| +000052 a223 ADR r2,|L23.224| +000054 a123 ADR r1,|L23.228| +000056 2000 MOVS r0,#0 +000058 f7fffffe BL tau_log_printf +00005c e034 B |L23.200| + |L23.94| +;;;1891 } +;;;1892 else if (sleep_mode == PWR_STOP_SLEEP_MODE) +00005e 2d01 CMP r5,#1 +000060 d125 BNE |L23.174| +;;;1893 { +;;;1894 TAU_LOGD("PWR_STOP_SLEEP_MODE\n"); +000062 bf00 NOP +000064 4b1d LDR r3,|L23.220| +000066 1d1b ADDS r3,r3,#4 +000068 a21d ADR r2,|L23.224| +00006a a127 ADR r1,|L23.264| +00006c 2000 MOVS r0,#0 +00006e f7fffffe BL tau_log_printf +000072 bf00 NOP +;;;1895 +;;;1896 /* 注册对应 wakeup IO */ +;;;1897 hal_pwr_set_stop_sleep_wakeup_pin(IO_PAD_AP_RSTN, WUP_RISING_EDGE); +000074 2102 MOVS r1,#2 +000076 2011 MOVS r0,#0x11 +000078 f7fffffe BL hal_pwr_set_stop_sleep_wakeup_pin +;;;1898 //hal_pwr_set_stop_sleep_wakeup_pin(IO_PAD_AP_SPIS_CSN, WUP_FALLING_EDGE); +;;;1899 //hal_pwr_set_stop_sleep_wakeup_pin(IO_PAD_TD_INT, WUP_FALLING_EDGE); +;;;1900 io_pad_e wakeup_io = hal_pwr_enter_stop_sleep_mode(); +00007c f7fffffe BL hal_pwr_enter_stop_sleep_mode +000080 4604 MOV r4,r0 +;;;1901 if (wakeup_io == IO_PAD_AP_RSTN) +000082 2c11 CMP r4,#0x11 +000084 d103 BNE |L23.142| +;;;1902 { +;;;1903 sg_system_resume = true; +000086 2001 MOVS r0,#1 +000088 4928 LDR r1,|L23.300| +00008a 7008 STRB r0,[r1,#0] +00008c e00e B |L23.172| + |L23.142| +;;;1904 } +;;;1905 else +;;;1906 { +;;;1907 /* Not impletmented */ +;;;1908 TAU_LOGD("wakeup_io %d FIXME touch wakeup convert to AP\n", wakeup_io); +00008e bf00 NOP +000090 4b12 LDR r3,|L23.220| +000092 3312 ADDS r3,r3,#0x12 +000094 a212 ADR r2,|L23.224| +000096 a126 ADR r1,|L23.304| +000098 2000 MOVS r0,#0 +00009a 9400 STR r4,[sp,#0] +00009c f7fffffe BL tau_log_printf +0000a0 bf00 NOP +;;;1909 hal_gpio_set_ap_reset_int(ENABLE, ap_rstn_pull_high_cb, DETECT_HIGH_LVL); +0000a2 2200 MOVS r2,#0 +0000a4 490c LDR r1,|L23.216| +0000a6 2001 MOVS r0,#1 +0000a8 f7fffffe BL hal_gpio_set_ap_reset_int + |L23.172| +;;;1910 } +;;;1911 } +0000ac e00c B |L23.200| + |L23.174| +;;;1912 else +;;;1913 { +;;;1914 /* deep sleep mode,配置AP RSTN 上升沿,TD INT 下降沿唤醒 */ +;;;1915 hal_pwr_enter_deep_sleep_mode(WUP_RISING_EDGE, WUP_FALLING_EDGE); +0000ae 2103 MOVS r1,#3 +0000b0 2002 MOVS r0,#2 +0000b2 f7fffffe BL hal_pwr_enter_deep_sleep_mode +;;;1916 TAU_LOGD("PWR_DEEP_SLEEP_MODE\n"); +0000b6 bf00 NOP +0000b8 4b08 LDR r3,|L23.220| +0000ba 331a ADDS r3,r3,#0x1a +0000bc a208 ADR r2,|L23.224| +0000be a12b ADR r1,|L23.364| +0000c0 2000 MOVS r0,#0 +0000c2 f7fffffe BL tau_log_printf +0000c6 bf00 NOP + |L23.200| +;;;1917 } +;;;1918 +;;;1919 } +0000c8 bd38 POP {r3-r5,pc} +;;;1920 + ENDP + +0000ca 0000 DCW 0x0000 + |L23.204| + DCD g_tx_ctrl_handle + |L23.208| + DCD g_rx_ctrl_handle + |L23.212| + DCD panel_display_done + |L23.216| + DCD ap_rstn_pull_high_cb + |L23.220| + DCD 0x00000762 + |L23.224| +0000e0 70387000 DCB "p8p",0 + |L23.228| +0000e4 5b25735d DCB "[%s] (%04d) PWR_NORMAL_SLEEP_MODE\n",0 +0000e8 20282530 +0000ec 34642920 +0000f0 5057525f +0000f4 4e4f524d +0000f8 414c5f53 +0000fc 4c454550 +000100 5f4d4f44 +000104 450a00 +000107 00 DCB 0 + |L23.264| +000108 5b25735d DCB "[%s] (%04d) PWR_STOP_SLEEP_MODE\n",0 +00010c 20282530 +000110 34642920 +000114 5057525f +000118 53544f50 +00011c 5f534c45 +000120 45505f4d +000124 4f44450a +000128 00 +000129 00 DCB 0 +00012a 00 DCB 0 +00012b 00 DCB 0 + |L23.300| + DCD sg_system_resume + |L23.304| +000130 5b25735d DCB "[%s] (%04d) wakeup_io %d FIXME touch wakeup convert to " +000134 20282530 +000138 34642920 +00013c 77616b65 +000140 75705f69 +000144 6f202564 +000148 20464958 +00014c 4d452074 +000150 6f756368 +000154 2077616b +000158 65757020 +00015c 636f6e76 +000160 65727420 +000164 746f20 +000167 41500a00 DCB "AP\n",0 +00016b 00 DCB 0 + |L23.364| +00016c 5b25735d DCB "[%s] (%04d) PWR_DEEP_SLEEP_MODE\n",0 +000170 20282530 +000174 34642920 +000178 5057525f +00017c 44454550 +000180 5f534c45 +000184 45505f4d +000188 4f44450a +00018c 00 +00018d 00 DCB 0 +00018e 00 DCB 0 +00018f 00 DCB 0 + + AREA ||i.app_tx_panel_reset||, CODE, READONLY, ALIGN=1 + + app_tx_panel_reset PROC +;;;638 */ +;;;639 static void app_tx_panel_reset(void) +000000 b510 PUSH {r4,lr} +;;;640 { +;;;641 #if SHARE_FLASH_ENABLE +;;;642 hal_flash_share_mode(true); +;;;643 #endif +;;;644 hal_gpio_set_output_data(IO_PAD_TD_RSTN, IO_LVL_HIGH); +000002 2101 MOVS r1,#1 +000004 2007 MOVS r0,#7 +000006 f7fffffe BL hal_gpio_set_output_data +;;;645 delayMs(10); +00000a 200a MOVS r0,#0xa +00000c f7fffffe BL delayMs +;;;646 hal_gpio_set_output_data(IO_PAD_TD_RSTN, IO_LVL_LOW); +000010 2100 MOVS r1,#0 +000012 2007 MOVS r0,#7 +000014 f7fffffe BL hal_gpio_set_output_data +;;;647 delayMs(10); +000018 200a MOVS r0,#0xa +00001a f7fffffe BL delayMs +;;;648 hal_gpio_set_output_data(IO_PAD_TD_RSTN, IO_LVL_HIGH); +00001e 2101 MOVS r1,#1 +000020 2007 MOVS r0,#7 +000022 f7fffffe BL hal_gpio_set_output_data +;;;649 delayMs(40); +000026 2028 MOVS r0,#0x28 +000028 f7fffffe BL delayMs +;;;650 } +00002c bd10 POP {r4,pc} +;;;651 + ENDP + + + AREA ||i.google_p8p_demo||, CODE, READONLY, ALIGN=2 + + google_p8p_demo PROC +;;;1959 */ +;;;1960 void google_p8p_demo(void) +000000 2002 MOVS r0,#2 +;;;1961 { +;;;1962 // hal_gpio_set_high_impedance(IO_PIN_14); +;;;1963 // TAU_LOGD("p6p demo reset flag=%d \n", hal_pwr_get_reset_flag()); +;;;1964 +;;;1965 /* 电源选择,上电只需要选择一次 */ +;;;1966 hal_pwr_set_main_power(MAIN_POWER_SELECT); /* 切换供电*/ +000002 f7fffffe BL hal_pwr_set_main_power +;;;1967 // if (MAIN_POWER_SELECT == PWR_SEL_VCC) +;;;1968 // { +;;;1969 // while (hal_pwr_get_vcc_power_ready() == false); +;;;1970 // } +;;;1971 /* 显示模块初始 */ +;;;1972 app_display_init(); +000006 f7fffffe BL app_display_init +;;;1973 +;;;1974 /* touch 相关模块初始化 */ +;;;1975 #if TOUCH_ENABLE +;;;1976 /* TP 初始化 */ +;;;1977 app_tp_init(); +;;;1978 app_tp_phone_clear_reset_on(); +;;;1979 /* 与屏的TP 模块通讯并初始化 */ +;;;1980 app_tp_transfer_screen_start(); +;;;1981 #endif +;;;1982 +;;;1983 TAU_LOGD("p8p demo init done \n"); +00000a bf00 NOP +00000c 4b08 LDR r3,|L25.48| +00000e a209 ADR r2,|L25.52| +000010 a109 ADR r1,|L25.56| +000012 2000 MOVS r0,#0 +000014 f7fffffe BL tau_log_printf +000018 bf00 NOP +;;;1984 +;;;1985 while (1) +00001a e008 B |L25.46| + |L25.28| +;;;1986 { +;;;1987 +;;;1988 ///hal_dsi_tx_ctrl_set_vpg(1, TX_VPG_H_COLOR, true); +;;;1989 #if TOUCH_ENABLE +;;;1990 /* 等待屏TP中断上报做TP协议转换,注意接口实现不可阻塞!否则会影响sleep mode */ +;;;1991 app_tp_transfer_screen_int(); +;;;1992 #endif +;;;1993 /* DCS 命令异步处理 */ +;;;1994 while (hal_dsi_rx_ctrl_dcs_async_handler(g_rx_ctrl_handle)); +00001c bf00 NOP + |L25.30| +00001e 480f LDR r0,|L25.92| +000020 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000022 f7fffffe BL hal_dsi_rx_ctrl_dcs_async_handler +000026 2800 CMP r0,#0 +000028 d1f9 BNE |L25.30| +;;;1995 +;;;1996 /* 系统事件处理(sleep mode) */ +;;;1997 app_system_process(); +00002a f7fffffe BL app_system_process + |L25.46| +00002e e7f5 B |L25.28| +;;;1998 } +;;;1999 } +;;;2000 #endif + ENDP + + |L25.48| + DCD 0x000007bf + |L25.52| +000034 70387000 DCB "p8p",0 + |L25.56| +000038 5b25735d DCB "[%s] (%04d) p8p demo init done \n",0 +00003c 20282530 +000040 34642920 +000044 70387020 +000048 64656d6f +00004c 20696e69 +000050 7420646f +000054 6e65200a +000058 00 +000059 00 DCB 0 +00005a 00 DCB 0 +00005b 00 DCB 0 + |L25.92| + DCD g_rx_ctrl_handle + + AREA ||i.pps_update_handle||, CODE, READONLY, ALIGN=2 + + pps_update_handle PROC +;;;263 /* PPS update callback 用于分辨率切换case */ +;;;264 static bool pps_update_handle(uint8_t *pps, uint8_t size, uint32_t pic_width, uint32_t pic_height) +000000 b5f8 PUSH {r3-r7,lr} +;;;265 { +000002 4606 MOV r6,r0 +000004 460f MOV r7,r1 +000006 4614 MOV r4,r2 +000008 461d MOV r5,r3 +;;;266 // for (uint8_t i =0; i< 128; i++) +;;;267 // { +;;;268 // TAU_LOGD("PPS_0A[i]=[0x%02X]\n",i,pps[i]); +;;;269 // } +;;;270 +;;;271 /* AVDD 上电, 用于解决息屏开屏PPS不更新问题 */ +;;;272 // hal_gpio_set_output_data(IO_PAD_AP_PWMEN, IO_LVL_HIGH); +;;;273 if (pic_width != g_rx_ctrl_handle->base_info.src_w || pic_height != g_rx_ctrl_handle->base_info.src_h) +00000a 4819 LDR r0,|L26.112| +00000c 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +00000e 6800 LDR r0,[r0,#0] +000010 42a0 CMP r0,r4 +000012 d104 BNE |L26.30| +000014 4816 LDR r0,|L26.112| +000016 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000018 6840 LDR r0,[r0,#4] +00001a 42a8 CMP r0,r5 +00001c d020 BEQ |L26.96| + |L26.30| +;;;274 { +;;;275 hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_USER_MODE); +00001e 2101 MOVS r1,#1 +000020 4814 LDR r0,|L26.116| +000022 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000024 f7fffffe BL hal_dsi_tx_ctrl_set_tear_mode +;;;276 /* PPS Update 且分辨率发生变化 */ +;;;277 g_rx_ctrl_handle->base_info.src_w = pic_width; +000028 4811 LDR r0,|L26.112| +00002a 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +00002c 6004 STR r4,[r0,#0] +;;;278 g_rx_ctrl_handle->base_info.src_h = pic_height; +00002e 4810 LDR r0,|L26.112| +000030 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +000032 6045 STR r5,[r0,#4] +;;;279 /* 注意部分基板更新PPS前不发 Compression Mode Command的情况 */ +;;;280 g_rx_ctrl_handle->compress_en = true; +000034 2101 MOVS r1,#1 +000036 480e LDR r0,|L26.112| +000038 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +00003a 3020 ADDS r0,r0,#0x20 +00003c 7541 STRB r1,[r0,#0x15] +;;;281 g_resolution_change = true; +00003e 2001 MOVS r0,#1 +000040 490d LDR r1,|L26.120| +000042 7008 STRB r0,[r1,#0] +;;;282 if(pic_width > 720) +000044 202d MOVS r0,#0x2d +000046 0100 LSLS r0,r0,#4 +000048 4284 CMP r4,r0 +00004a d905 BLS |L26.88| +;;;283 { +;;;284 g_tx_ctrl_handle->base_info.src_w = pic_width; +00004c 4809 LDR r0,|L26.116| +00004e 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000050 6004 STR r4,[r0,#0] +;;;285 g_tx_ctrl_handle->base_info.src_h = pic_height; +000052 4808 LDR r0,|L26.116| +000054 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000056 6045 STR r5,[r0,#4] + |L26.88| +;;;286 } +;;;287 // hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x22); // ic刷黑处理 +;;;288 // delayMs(5); +;;;289 +;;;290 // hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps, 128); +;;;291 hal_dsi_rx_ctrl_toggle_resolution(g_rx_ctrl_handle); +000058 4805 LDR r0,|L26.112| +00005a 6800 LDR r0,[r0,#0] ; g_rx_ctrl_handle +00005c f7fffffe BL hal_dsi_rx_ctrl_toggle_resolution + |L26.96| +;;;292 // hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x13); // 退出刷黑 +;;;293 } +;;;294 hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); +000060 2100 MOVS r1,#0 +000062 4804 LDR r0,|L26.116| +000064 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000066 f7fffffe BL hal_dsi_tx_ctrl_set_tear_mode +;;;295 //TAU_LOGD("PPS Update[%d][%d] [%d][%d]\n", pic_width, pic_height, g_rx_ctrl_handle->base_info.src_w, g_rx_ctrl_handle->base_info.src_h); +;;;296 return true; +00006a 2001 MOVS r0,#1 +;;;297 } +00006c bdf8 POP {r3-r7,pc} +;;;298 #endif + ENDP + +00006e 0000 DCW 0x0000 + |L26.112| + DCD g_rx_ctrl_handle + |L26.116| + DCD g_tx_ctrl_handle + |L26.120| + DCD g_resolution_change + + AREA ||i.send_panel_init_code||, CODE, READONLY, ALIGN=1 + + send_panel_init_code PROC +;;;652 #if PANEL_INIT_CODE_ARRAY +;;;653 static void send_panel_init_code(uint32_t size, uint8_t * data) +000000 b5fe PUSH {r1-r7,lr} +;;;654 { +000002 4607 MOV r7,r0 +000004 460d MOV r5,r1 +;;;655 uint32_t data_offeset = 0; +000006 2400 MOVS r4,#0 +;;;656 uint8_t data_type; +;;;657 uint8_t vc; +;;;658 uint8_t data_size; +;;;659 uint8_t * p_data; +;;;660 +;;;661 while(data_offeset < size) +000008 e014 B |L27.52| + |L27.10| +;;;662 { +;;;663 data_type = data[data_offeset]; +00000a 5d28 LDRB r0,[r5,r4] +00000c 9002 STR r0,[sp,#8] +;;;664 vc = data[data_offeset + 1]; +00000e 1c60 ADDS r0,r4,#1 +000010 5c28 LDRB r0,[r5,r0] +000012 9001 STR r0,[sp,#4] +;;;665 data_size = data[data_offeset + 2]; +000014 1ca0 ADDS r0,r4,#2 +000016 5c2e LDRB r6,[r5,r0] +;;;666 p_data = &data[data_offeset + 3]; +000018 1ce0 ADDS r0,r4,#3 +00001a 1828 ADDS r0,r5,r0 +00001c 9000 STR r0,[sp,#0] +;;;667 hal_dsi_tx_ctrl_write_array_cmd(data_type, vc, data_size, p_data); +00001e 4632 MOV r2,r6 +000020 9b00 LDR r3,[sp,#0] +000022 9901 LDR r1,[sp,#4] +000024 9802 LDR r0,[sp,#8] +000026 f7fffffe BL hal_dsi_tx_ctrl_write_array_cmd +;;;668 data_offeset = data_offeset + data_size + 3; +00002a 19a0 ADDS r0,r4,r6 +00002c 1cc4 ADDS r4,r0,#3 +;;;669 delayUs(50); +00002e 2032 MOVS r0,#0x32 +000030 f7fffffe BL delayUs + |L27.52| +000034 42bc CMP r4,r7 ;661 +000036 d3e8 BCC |L27.10| +;;;670 } +;;;671 } +000038 bdfe POP {r1-r7,pc} +;;;672 + ENDP + + + AREA ||i.soft_te_timer_cb||, CODE, READONLY, ALIGN=2 + + soft_te_timer_cb PROC +;;;541 #define TE_TIMER TIMER_NUM2 +;;;542 static void soft_te_timer_cb(void *data) +000000 b510 PUSH {r4,lr} +;;;543 { +000002 4604 MOV r4,r0 +;;;544 /* +;;;545 S8 的屏接的是TP1.8V, AC 启动后需要等到TP1.8 起来后再初始化屏, 所以在TP 起来前需要通过软件产生TE给手机，避免手机卡死 +;;;546 */ +;;;547 // if (panel_display_done == false) +;;;548 // { +;;;549 hal_dsi_tx_ctrl_gen_a_tear_signal(); +000004 f7fffffe BL hal_dsi_tx_ctrl_gen_a_tear_signal +;;;550 hal_timer_start(TE_TIMER, 8, soft_te_timer_cb, NULL); +000008 2300 MOVS r3,#0 +00000a 4a03 LDR r2,|L28.24| +00000c 2108 MOVS r1,#8 +00000e 2002 MOVS r0,#2 +000010 f7fffffe BL hal_timer_start +;;;551 // } +;;;552 // else +;;;553 // { +;;;554 // hal_dsi_rx_ctrl_set_hw_tear_mode(g_rx_ctrl_handle); +;;;555 // } +;;;556 } +000014 bd10 POP {r4,pc} +;;;557 + ENDP + +000016 0000 DCW 0x0000 + |L28.24| + DCD soft_te_timer_cb + + AREA ||i.soft_te_timer_init||, CODE, READONLY, ALIGN=2 + + soft_te_timer_init PROC +;;;557 +;;;558 static void soft_te_timer_init() +000000 b510 PUSH {r4,lr} +;;;559 { +;;;560 // TAU_LOGD("soft_te_timer_init"); +;;;561 hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle,TE_USER_MODE); +000002 2101 MOVS r1,#1 +000004 4806 LDR r0,|L29.32| +000006 6800 LDR r0,[r0,#0] ; g_tx_ctrl_handle +000008 f7fffffe BL hal_dsi_tx_ctrl_set_tear_mode +;;;562 hal_timer_init(TE_TIMER); +00000c 2002 MOVS r0,#2 +00000e f7fffffe BL hal_timer_init +;;;563 hal_timer_start(TE_TIMER, 1, soft_te_timer_cb, NULL); +000012 2300 MOVS r3,#0 +000014 4a03 LDR r2,|L29.36| +000016 2101 MOVS r1,#1 +000018 2002 MOVS r0,#2 +00001a f7fffffe BL hal_timer_start +;;;564 } +00001e bd10 POP {r4,pc} +;;;565 + ENDP + + |L29.32| + DCD g_tx_ctrl_handle + |L29.36| + DCD soft_te_timer_cb + + AREA ||.constdata||, DATA, READONLY, ALIGN=2 + + g_cus_rx_dcs_execute_table + DCD 0x00000029 + DCD ap_dcs_set_display_on +000008 00000000 DCB 0x00,0x00,0x00,0x00 + DCD 0x00000028 + DCD ap_dcs_set_display_off +000014 01000000 DCB 0x01,0x00,0x00,0x00 + DCD 0x00000051 + DCD ap_dcs_set_backlight +000020 00000000 DCB 0x00,0x00,0x00,0x00 + DCD 0x00000053 + DCD ap_set_FPS_53 +00002c 01000000 DCB 0x01,0x00,0x00,0x00 + DCD 0x00000010 + DCD ap_dcs_set_enter_sleep_mode +000038 01000000 DCB 0x01,0x00,0x00,0x00 + DCD 0x00000011 + DCD ap_dcs_set_exit_sleep_mode +000044 01000000 DCB 0x01,0x00,0x00,0x00 + DCD 0x00000060 + DCD ap_dcs_set_frame_change +000050 01000000 DCB 0x01,0x00,0x00,0x00 + DCD 0x00000000 + DCD 0x00000000 +00005c 00000000 DCB 0x00,0x00,0x00,0x00 + panel_init_code +000060 3900039c DCB 0x39,0x00,0x03,0x9c +000064 a5a53900 DCB 0xa5,0xa5,0x39,0x00 +000068 03fd5a5a DCB 0x03,0xfd,0x5a,0x5a +00006c 3900029f DCB 0x39,0x00,0x02,0x9f +000070 0f390002 DCB 0x0f,0x39,0x00,0x02 +000074 b3003900 DCB 0xb3,0x00,0x39,0x00 +000078 02d71139 DCB 0x02,0xd7,0x11,0x39 +00007c 00029f01 DCB 0x00,0x02,0x9f,0x01 +000080 390004b2 DCB 0x39,0x00,0x04,0xb2 +000084 5a04af39 DCB 0x5a,0x04,0xaf,0x39 +000088 0024b300 DCB 0x00,0x24,0xb3,0x00 +00008c ba00140c DCB 0xba,0x00,0x14,0x0c +000090 2200ba30 DCB 0x22,0x00,0xba,0x30 +000094 142c0000 DCB 0x14,0x2c,0x00,0x00 +000098 ba90144c DCB 0xba,0x90,0x14,0x4c +00009c 00000000 DCB 0x00,0x00,0x00,0x00 +0000a0 00000000 DCB 0x00,0x00,0x00,0x00 +0000a4 ba00140c DCB 0xba,0x00,0x14,0x0c +0000a8 441c1c1c DCB 0x44,0x1c,0x1c,0x1c +0000ac 1c1c3900 DCB 0x1c,0x1c,0x39,0x00 +0000b0 13cd061f DCB 0x13,0xcd,0x06,0x1f +0000b4 1f060009 DCB 0x1f,0x06,0x00,0x09 +0000b8 00961f03 DCB 0x00,0x96,0x1f,0x03 +0000bc 2800961f DCB 0x28,0x00,0x96,0x1f +0000c0 09460096 DCB 0x09,0x46,0x00,0x96 +0000c4 390002d0 DCB 0x39,0x00,0x02,0xd0 +0000c8 01390003 DCB 0x01,0x39,0x00,0x03 +0000cc e2462039 DCB 0xe2,0x46,0x20,0x39 +0000d0 0003ea04 DCB 0x00,0x03,0xea,0x04 +0000d4 0b390009 DCB 0x0b,0x39,0x00,0x09 +0000d8 ee403828 DCB 0xee,0x40,0x38,0x28 +0000dc 28282828 DCB 0x28,0x28,0x28,0x28 +0000e0 c2390002 DCB 0xc2,0x39,0x00,0x02 +0000e4 9f023900 DCB 0x9f,0x02,0x39,0x00 +0000e8 1ab200c9 DCB 0x1a,0xb2,0x00,0xc9 +0000ec 32101112 DCB 0x32,0x10,0x11,0x12 +0000f0 12000878 DCB 0x12,0x00,0x08,0x78 +0000f4 21111413 DCB 0x21,0x11,0x14,0x13 +0000f8 11111111 DCB 0x11,0x11,0x11,0x11 +0000fc 11111121 DCB 0x11,0x11,0x11,0x21 +000100 21111a39 DCB 0x21,0x11,0x1a,0x39 +000104 000eb400 DCB 0x00,0x0e,0xb4,0x00 +000108 008c0000 DCB 0x00,0x8c,0x00,0x00 +00010c 00000025 DCB 0x00,0x00,0x00,0x25 +000110 25252525 DCB 0x25,0x25,0x25,0x25 +000114 390007b5 DCB 0x39,0x00,0x07,0xb5 +000118 00303030 DCB 0x00,0x30,0x30,0x30 +00011c 302a3900 DCB 0x30,0x2a,0x39,0x00 +000120 14b60500 DCB 0x14,0xb6,0x05,0x00 +000124 00111111 DCB 0x00,0x11,0x11,0x11 +000128 1c081c21 DCB 0x1c,0x08,0x1c,0x21 +00012c 21212121 DCB 0x21,0x21,0x21,0x21 +000130 21212121 DCB 0x21,0x21,0x21,0x21 +000134 21390011 DCB 0x21,0x39,0x00,0x11 +000138 b7000000 DCB 0xb7,0x00,0x00,0x00 +00013c 00001500 DCB 0x00,0x00,0x15,0x00 +000140 06060306 DCB 0x06,0x06,0x03,0x06 +000144 06030606 DCB 0x06,0x03,0x06,0x06 +000148 0339000e DCB 0x03,0x39,0x00,0x0e +00014c b8000000 DCB 0xb8,0x00,0x00,0x00 +000150 73287328 DCB 0x73,0x28,0x73,0x28 +000154 73287328 DCB 0x73,0x28,0x73,0x28 +000158 73283900 DCB 0x73,0x28,0x39,0x00 +00015c 09b90000 DCB 0x09,0xb9,0x00,0x00 +000160 5000000f DCB 0x50,0x00,0x00,0x0f +000164 0f003900 DCB 0x0f,0x00,0x39,0x00 +000168 0eba0eff DCB 0x0e,0xba,0x0e,0xff +00016c ffff0054 DCB 0xff,0xff,0x00,0x54 +000170 00440444 DCB 0x00,0x44,0x04,0x44 +000174 04040039 DCB 0x04,0x04,0x00,0x39 +000178 001abb00 DCB 0x00,0x1a,0xbb,0x00 +00017c 5a91915a DCB 0x5a,0x91,0x91,0x5a +000180 005a9191 DCB 0x00,0x5a,0x91,0x91 +000184 5a005a91 DCB 0x5a,0x00,0x5a,0x91 +000188 915a005a DCB 0x91,0x5a,0x00,0x5a +00018c 91915a00 DCB 0x91,0x91,0x5a,0x00 +000190 3c78783c DCB 0x3c,0x78,0x78,0x3c +000194 390005be DCB 0x39,0x00,0x05,0xbe +000198 5b17045b DCB 0x5b,0x17,0x04,0x5b +00019c 390011bf DCB 0x39,0x00,0x11,0xbf +0001a0 0c8fff10 DCB 0x0c,0x8f,0xff,0x10 +0001a4 0007000a DCB 0x00,0x07,0x00,0x0a +0001a8 01200000 DCB 0x01,0x20,0x00,0x00 +0001ac 00000000 DCB 0x00,0x00,0x00,0x00 +0001b0 390011c1 DCB 0x39,0x00,0x11,0xc1 +0001b4 0521221d DCB 0x05,0x21,0x22,0x1d +0001b8 1f1e2001 DCB 0x1f,0x1e,0x20,0x01 +0001bc 30313233 DCB 0x30,0x31,0x32,0x33 +0001c0 3d3d3d3d DCB 0x3d,0x3d,0x3d,0x3d +0001c4 390011c2 DCB 0x39,0x00,0x11,0xc2 +0001c8 0521221d DCB 0x05,0x21,0x22,0x1d +0001cc 1f1e2001 DCB 0x1f,0x1e,0x20,0x01 +0001d0 30313233 DCB 0x30,0x31,0x32,0x33 +0001d4 3d3d3d3d DCB 0x3d,0x3d,0x3d,0x3d +0001d8 39000ac3 DCB 0x39,0x00,0x0a,0xc3 +0001dc 11600040 DCB 0x11,0x60,0x00,0x40 +0001e0 00400000 DCB 0x00,0x40,0x00,0x00 +0001e4 0039001a DCB 0x00,0x39,0x00,0x1a +0001e8 c4000c01 DCB 0xc4,0x00,0x0c,0x01 +0001ec 00000000 DCB 0x00,0x00,0x00,0x00 +0001f0 00000000 DCB 0x00,0x00,0x00,0x00 +0001f4 00000008 DCB 0x00,0x00,0x00,0x08 +0001f8 001f1f00 DCB 0x00,0x1f,0x1f,0x00 +0001fc 000d0000 DCB 0x00,0x0d,0x00,0x00 +000200 00003900 DCB 0x00,0x00,0x39,0x00 +000204 11d20000 DCB 0x11,0xd2,0x00,0x00 +000208 13000013 DCB 0x13,0x00,0x00,0x13 +00020c 00001700 DCB 0x00,0x00,0x17,0x00 +000210 00170000 DCB 0x00,0x17,0x00,0x00 +000214 17003900 DCB 0x17,0x00,0x39,0x00 +000218 0ec70004 DCB 0x0e,0xc7,0x00,0x04 +00021c 04040400 DCB 0x04,0x04,0x04,0x00 +000220 04040404 DCB 0x04,0x04,0x04,0x04 +000224 00040439 DCB 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0xff,0xff,0x33,0xff +001f08 ff33ffff DCB 0xff,0x33,0xff,0xff +001f0c 33ffff33 DCB 0x33,0xff,0xff,0x33 +001f10 ffff33ff DCB 0xff,0xff,0x33,0xff +001f14 ff39001c DCB 0xff,0x39,0x00,0x1c +001f18 ea33ffff DCB 0xea,0x33,0xff,0xff +001f1c 33ffff33 DCB 0x33,0xff,0xff,0x33 +001f20 ffff33ff DCB 0xff,0xff,0x33,0xff +001f24 ff33ffff DCB 0xff,0x33,0xff,0xff +001f28 33ffff33 DCB 0x33,0xff,0xff,0x33 +001f2c ffff33ff DCB 0xff,0xff,0x33,0xff +001f30 ff33ffff DCB 0xff,0x33,0xff,0xff +001f34 39002eeb DCB 0x39,0x00,0x2e,0xeb +001f38 ffffff00 DCB 0xff,0xff,0xff,0x00 +001f3c ffff00ff DCB 0xff,0xff,0x00,0xff +001f40 ff00ffff DCB 0xff,0x00,0xff,0xff +001f44 ff3f3f33 DCB 0xff,0x3f,0x3f,0x33 +001f48 ffff33ff DCB 0xff,0xff,0x33,0xff +001f4c ff33ffff DCB 0xff,0x33,0xff,0xff +001f50 33ffff33 DCB 0x33,0xff,0xff,0x33 +001f54 ffff33ff DCB 0xff,0xff,0x33,0xff +001f58 ff33ffff DCB 0xff,0x33,0xff,0xff +001f5c 33ffff33 DCB 0x33,0xff,0xff,0x33 +001f60 ffff33ff DCB 0xff,0xff,0x33,0xff +001f64 ff39001c DCB 0xff,0x39,0x00,0x1c +001f68 ec33ffff DCB 0xec,0x33,0xff,0xff +001f6c 33ffff33 DCB 0x33,0xff,0xff,0x33 +001f70 ffff33ff DCB 0xff,0xff,0x33,0xff +001f74 ff33ffff DCB 0xff,0x33,0xff,0xff +001f78 33ffff33 DCB 0x33,0xff,0xff,0x33 +001f7c ffff33ff DCB 0xff,0xff,0x33,0xff +001f80 ff33ffff DCB 0xff,0x33,0xff,0xff +001f84 39002eed DCB 0x39,0x00,0x2e,0xed +001f88 ffffff00 DCB 0xff,0xff,0xff,0x00 +001f8c ffff00ff DCB 0xff,0xff,0x00,0xff +001f90 ff00ffff DCB 0xff,0x00,0xff,0xff +001f94 ff3f3f33 DCB 0xff,0x3f,0x3f,0x33 +001f98 ffff33ff DCB 0xff,0xff,0x33,0xff +001f9c ff33ffff DCB 0xff,0x33,0xff,0xff +001fa0 33ffff33 DCB 0x33,0xff,0xff,0x33 +001fa4 ffff33ff DCB 0xff,0xff,0x33,0xff +001fa8 ff33ffff DCB 0xff,0x33,0xff,0xff +001fac 33ffff33 DCB 0x33,0xff,0xff,0x33 +001fb0 ffff33ff DCB 0xff,0xff,0x33,0xff +001fb4 ff39001c DCB 0xff,0x39,0x00,0x1c +001fb8 ee33ffff DCB 0xee,0x33,0xff,0xff +001fbc 33ffff33 DCB 0x33,0xff,0xff,0x33 +001fc0 ffff33ff DCB 0xff,0xff,0x33,0xff +001fc4 ff33ffff DCB 0xff,0x33,0xff,0xff +001fc8 33ffff33 DCB 0x33,0xff,0xff,0x33 +001fcc ffff33ff DCB 0xff,0xff,0x33,0xff +001fd0 ff33ffff DCB 0xff,0x33,0xff,0xff +001fd4 39000af8 DCB 0x39,0x00,0x0a,0xf8 +001fd8 1ee0e0e0 DCB 0x1e,0xe0,0xe0,0xe0 +001fdc 00181500 DCB 0x00,0x18,0x15,0x00 +001fe0 e039000a DCB 0xe0,0x39,0x00,0x0a +001fe4 f9e11815 DCB 0xf9,0xe1,0x18,0x15 +001fe8 00f0f8f0 DCB 0x00,0xf0,0xf8,0xf0 +001fec ee003900 DCB 0xee,0x00,0x39,0x00 +001ff0 0afa1ee0 DCB 0x0a,0xfa,0x1e,0xe0 +001ff4 e0e00018 DCB 0xe0,0xe0,0x00,0x18 +001ff8 1500e039 DCB 0x15,0x00,0xe0,0x39 +001ffc 00029f05 DCB 0x00,0x02,0x9f,0x05 +002000 39000db4 DCB 0x39,0x00,0x0d,0xb4 +002004 020f3e00 DCB 0x02,0x0f,0x3e,0x00 +002008 00100600 DCB 0x00,0x10,0x06,0x00 +00200c 0002408d DCB 0x00,0x02,0x40,0x8d +002010 390029e6 DCB 0x39,0x00,0x29,0xe6 +002014 0fff07ff DCB 0x0f,0xff,0x07,0xff +002018 03330147 DCB 0x03,0x33,0x01,0x47 +00201c 014600cd DCB 0x01,0x46,0x00,0xcd +002020 0066003a DCB 0x00,0x66,0x00,0x3a +002024 00140008 DCB 0x00,0x14,0x00,0x08 +002028 00000000 DCB 0x00,0x00,0x00,0x00 +00202c 00000000 DCB 0x00,0x00,0x00,0x00 +002030 00000000 DCB 0x00,0x00,0x00,0x00 +002034 00000000 DCB 0x00,0x00,0x00,0x00 +002038 00000000 DCB 0x00,0x00,0x00,0x00 +00203c 39001fe7 DCB 0x39,0x00,0x1f,0xe7 +002040 00000000 DCB 0x00,0x00,0x00,0x00 +002044 00000000 DCB 0x00,0x00,0x00,0x00 +002048 00000000 DCB 0x00,0x00,0x00,0x00 +00204c 00000000 DCB 0x00,0x00,0x00,0x00 +002050 00000000 DCB 0x00,0x00,0x00,0x00 +002054 00000000 DCB 0x00,0x00,0x00,0x00 +002058 00000000 DCB 0x00,0x00,0x00,0x00 +00205c 00003900 DCB 0x00,0x00,0x39,0x00 +002060 29e80fff DCB 0x29,0xe8,0x0f,0xff +002064 0fff0fff DCB 0x0f,0xff,0x0f,0xff +002068 0fff0fff DCB 0x0f,0xff,0x0f,0xff +00206c 0cf00971 DCB 0x0c,0xf0,0x09,0x71 +002070 0754048c DCB 0x07,0x54,0x04,0x8c +002074 03010000 DCB 0x03,0x01,0x00,0x00 +002078 00000000 DCB 0x00,0x00,0x00,0x00 +00207c 00000000 DCB 0x00,0x00,0x00,0x00 +002080 00000000 DCB 0x00,0x00,0x00,0x00 +002084 00000000 DCB 0x00,0x00,0x00,0x00 +002088 00003900 DCB 0x00,0x00,0x39,0x00 +00208c 1fe90000 DCB 0x1f,0xe9,0x00,0x00 +002090 00000000 DCB 0x00,0x00,0x00,0x00 +002094 00000000 DCB 0x00,0x00,0x00,0x00 +002098 00000000 DCB 0x00,0x00,0x00,0x00 +00209c 00000000 DCB 0x00,0x00,0x00,0x00 +0020a0 00000000 DCB 0x00,0x00,0x00,0x00 +0020a4 00000000 DCB 0x00,0x00,0x00,0x00 +0020a8 00000000 DCB 0x00,0x00,0x00,0x00 +0020ac 07020100 DCB 0x07,0x02,0x01,0x00 +0020b0 08020100 DCB 0x08,0x02,0x01,0x00 +0020b4 02020100 DCB 0x02,0x02,0x01,0x00 +0020b8 03010202 DCB 0x03,0x01,0x02,0x02 + + AREA ||.data||, DATA, ALIGN=2 + + g_rx_ctrl_handle + DCD 0x00000000 + g_tx_ctrl_handle + DCD 0x00000000 + panel_display_done +000008 00 DCB 0x00 + sg_system_resume +000009 00 DCB 0x00 + sg_system_suspend +00000a 00 DCB 0x00 + sg_exit_idle_mode_flag +00000b 00 DCB 0x00 + g_resolution_change +00000c 00000000 DCB 0x00,0x00,0x00,0x00 + pps_renew_flag + DCD 0x00000000 + pwr_rst_flag + DCD 0x00000000 + rd_51_val +000018 0000 DCB 0x00,0x00 + rd_51_val2 +00001a 0000 DCB 0x00,0x00 + pps +00001c 11000089 DCB 0x11,0x00,0x00,0x89 +000020 30800bb0 DCB 0x30,0x80,0x0b,0xb0 +000024 054000bb DCB 0x05,0x40,0x00,0xbb +000028 02a002a0 DCB 0x02,0xa0,0x02,0xa0 +00002c 02000250 DCB 0x02,0x00,0x02,0x50 +000030 00201439 DCB 0x00,0x20,0x14,0x39 +000034 0009000c DCB 0x00,0x09,0x00,0x0c +000038 00850070 DCB 0x00,0x85,0x00,0x70 +00003c 180010f0 DCB 0x18,0x00,0x10,0xf0 +000040 030c2000 DCB 0x03,0x0c,0x20,0x00 +000044 060b0b33 DCB 0x06,0x0b,0x0b,0x33 +000048 0e1c2a38 DCB 0x0e,0x1c,0x2a,0x38 +00004c 46546269 DCB 0x46,0x54,0x62,0x69 +000050 7077797b DCB 0x70,0x77,0x79,0x7b +000054 7d7e0102 DCB 0x7d,0x7e,0x01,0x02 +000058 01000940 DCB 0x01,0x00,0x09,0x40 +00005c 09be19fc DCB 0x09,0xbe,0x19,0xfc +000060 19fa19f8 DCB 0x19,0xfa,0x19,0xf8 +000064 1a381a78 DCB 0x1a,0x38,0x1a,0x78 +000068 1ab62af6 DCB 0x1a,0xb6,0x2a,0xf6 +00006c 2b342b74 DCB 0x2b,0x34,0x2b,0x74 +000070 3b746bf4 DCB 0x3b,0x74,0x6b,0xf4 +000074 00000000 DCB 0x00,0x00,0x00,0x00 +000078 00000000 DCB 0x00,0x00,0x00,0x00 +00007c 00000000 DCB 0x00,0x00,0x00,0x00 +000080 00000000 DCB 0x00,0x00,0x00,0x00 +000084 00000000 DCB 0x00,0x00,0x00,0x00 +000088 00000000 DCB 0x00,0x00,0x00,0x00 +00008c 00000000 DCB 0x00,0x00,0x00,0x00 +000090 00000000 DCB 0x00,0x00,0x00,0x00 +000094 00000000 DCB 0x00,0x00,0x00,0x00 +000098 00000000 DCB 0x00,0x00,0x00,0x00 + pps_fhd +00009c 11000089 DCB 0x11,0x00,0x00,0x89 +0000a0 308008c4 DCB 0x30,0x80,0x08,0xc4 +0000a4 03f000bb DCB 0x03,0xf0,0x00,0xbb +0000a8 01f801f8 DCB 0x01,0xf8,0x01,0xf8 +0000ac 020001f8 DCB 0x02,0x00,0x01,0xf8 +0000b0 00201182 DCB 0x00,0x20,0x11,0x82 +0000b4 0007000c DCB 0x00,0x07,0x00,0x0c +0000b8 00850096 DCB 0x00,0x85,0x00,0x96 +0000bc 180010f0 DCB 0x18,0x00,0x10,0xf0 +0000c0 030c2000 DCB 0x03,0x0c,0x20,0x00 +0000c4 060b0b33 DCB 0x06,0x0b,0x0b,0x33 +0000c8 0e1c2a38 DCB 0x0e,0x1c,0x2a,0x38 +0000cc 46546269 DCB 0x46,0x54,0x62,0x69 +0000d0 7077797b DCB 0x70,0x77,0x79,0x7b +0000d4 7d7e0102 DCB 0x7d,0x7e,0x01,0x02 +0000d8 01000940 DCB 0x01,0x00,0x09,0x40 +0000dc 09be19fc DCB 0x09,0xbe,0x19,0xfc +0000e0 19fa19f8 DCB 0x19,0xfa,0x19,0xf8 +0000e4 1a381a78 DCB 0x1a,0x38,0x1a,0x78 +0000e8 1ab62af6 DCB 0x1a,0xb6,0x2a,0xf6 +0000ec 2b342b74 DCB 0x2b,0x34,0x2b,0x74 +0000f0 3b746bf4 DCB 0x3b,0x74,0x6b,0xf4 +0000f4 00000000 DCB 0x00,0x00,0x00,0x00 +0000f8 00000000 DCB 0x00,0x00,0x00,0x00 +0000fc 00000000 DCB 0x00,0x00,0x00,0x00 +000100 00000000 DCB 0x00,0x00,0x00,0x00 +000104 00000000 DCB 0x00,0x00,0x00,0x00 +000108 00000000 DCB 0x00,0x00,0x00,0x00 +00010c 00000000 DCB 0x00,0x00,0x00,0x00 +000110 00000000 DCB 0x00,0x00,0x00,0x00 +000114 00000000 DCB 0x00,0x00,0x00,0x00 +000118 00000000 DCB 0x00,0x00,0x00,0x00 + value_51H +00011c 00 DCB 0x00 + value_51L +00011d 00 DCB 0x00 + reg53_E8_fg +00011e 00 DCB 0x00 + +;*** Start embedded assembler *** + +#line 1 "..\\..\\src\\app\\P8P\\p8p_demo.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___10_p8p_demo_c_pps____REV16| +#line 467 "C:\\Users\\Markin\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.5.1\\CMSIS\\Core\\Include\\cmsis_armcc.h" +|__asm___10_p8p_demo_c_pps____REV16| PROC +#line 468 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___10_p8p_demo_c_pps____REVSH| +#line 482 +|__asm___10_p8p_demo_c_pps____REVSH| PROC +#line 483 + + revsh r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/project/WL668/Listings/startup_armcm0.lst b/project/WL668/Listings/startup_armcm0.lst new file mode 100644 index 0000000..cbbd37b --- /dev/null +++ b/project/WL668/Listings/startup_armcm0.lst @@ -0,0 +1,1333 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;/****************************************************** + ********************//** + 2 00000000 ; * @file startup_ARMCM0.s + 3 00000000 ; * @brief CMSIS Core Device Startup File for + 4 00000000 ; * ARMCM0 Device + 5 00000000 ; * @version V5.4.0 + 6 00000000 ; * @date 12. December 2018 + 7 00000000 ; ****************************************************** + ************************/ + 8 00000000 ;/* + 9 00000000 ; * Copyright (c) 2009-2018 Arm Limited. All rights rese + rved. + 10 00000000 ; * + 11 00000000 ; * SPDX-License-Identifier: Apache-2.0 + 12 00000000 ; * + 13 00000000 ; * Licensed under the Apache License, Version 2.0 (the + License); you may + 14 00000000 ; * not use this file except in compliance with the Lice + nse. + 15 00000000 ; * You may obtain a copy of the License at + 16 00000000 ; * + 17 00000000 ; * www.apache.org/licenses/LICENSE-2.0 + 18 00000000 ; * + 19 00000000 ; * Unless required by applicable law or agreed to in wr + iting, software + 20 00000000 ; * distributed under the License is distributed on an A + S IS BASIS, WITHOUT + 21 00000000 ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express + or implied. + 22 00000000 ; * See the License for the specific language governing + permissions and + 23 00000000 ; * limitations under the License. + 24 00000000 ; */ + 25 00000000 + 26 00000000 ;//-------- <<< Use Configuration Wizard in Context Menu + >>> ------------------ + 27 00000000 + 28 00000000 + 29 00000000 ; Stack Configuration + 30 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 31 00000000 ; + 32 00000000 + 33 00000000 00001000 + Stack_Size + EQU 0x00001000 + 34 00000000 + 35 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 36 00000000 __stack_limit + 37 00000000 Stack_Mem + SPACE Stack_Size + 38 00001000 __initial_sp + 39 00001000 + 40 00001000 + 41 00001000 ; Heap Configuration + 42 00001000 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 43 00001000 ; + 44 00001000 + 45 00001000 00000C00 + + + +ARM Macro Assembler Page 2 + + + Heap_Size + EQU 0x00000C00 + 46 00001000 + 47 00001000 IF Heap_Size != 0 + ; Heap is provided + 48 00001000 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 49 00000000 __heap_base + 50 00000000 Heap_Mem + SPACE Heap_Size + 51 00000C00 __heap_limit + 52 00000C00 ENDIF + 53 00000C00 + 54 00000C00 + 55 00000C00 PRESERVE8 + 56 00000C00 THUMB + 57 00000C00 + 58 00000C00 + 59 00000C00 ; Vector Table Mapped to Address 0 at Reset + 60 00000C00 + 61 00000C00 AREA RESET, DATA, READONLY + 62 00000000 EXPORT __Vectors + 63 00000000 EXPORT __Vectors_End + 64 00000000 EXPORT __Vectors_Size + 65 00000000 + 66 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + + 67 00000004 00000000 DCD Reset_Handler + ; Reset Handler + + 68 00000008 00000000 DCD NMI_Handler ; -14 NMI Handler + 69 0000000C 00000000 DCD HardFault_Handler ; -13 Hard Fa + ult Handler + 70 00000010 00000000 DCD 0 ; Reserved + 71 00000014 00000000 DCD 0 ; Reserved + 72 00000018 00000000 DCD 0 ; Reserved + 73 0000001C 00000000 DCD 0 ; Reserved + 74 00000020 00000000 DCD 0 ; Reserved + 75 00000024 00000000 DCD 0 ; Reserved + 76 00000028 00000000 DCD 0 ; Reserved + 77 0000002C 00000000 DCD SVC_Handler ; -5 SVCall Handle + r + 78 00000030 00000000 DCD 0 ; Reserved + 79 00000034 00000000 DCD 0 ; Reserved + 80 00000038 00000000 DCD PendSV_Handler ; -2 PendSV Han + dler + 81 0000003C 00000000 DCD SysTick_Handler ; -1 SysTick H + andler + 82 00000040 + 83 00000040 + 84 00000040 ; Interrupts + 85 00000040 00000000 DCD VIDC_IRQn_Handler + ; 0 Interrupt 0 + 86 00000044 00000000 DCD LCDC_IRQn_Handler + ; 1 Interrupt 1 + 87 00000048 00000000 DCD MIPI_RX_IRQn_Handler + ; 2 Interrupt 2 + + + +ARM Macro Assembler Page 3 + + + 88 0000004C 00000000 DCD MIPI_TX_IRQn_Handler + ; 3 Interrupt 3 + 89 00000050 00000000 DCD MEMC_IRQn_Handler + ; 4 Interrupt 4 + 90 00000054 00000000 DCD VPRE_IRQn_Handler + ; 5 Interrupt 5 + 91 00000058 00000000 DCD FLSCTRL_IRQn_Handler + ; 6 Interrupt 6 + 92 0000005C 00000000 DCD DMA_IRQn_Handler + ; 7 Interrupt 7 + 93 00000060 00000000 DCD TIMER0_IRQn_Handler + ; 8 Interrupt 8 + 94 00000064 00000000 DCD TIMER1_IRQn_Handler + ; 9 Interrupt 9 + 95 00000068 00000000 DCD TIMER2_IRQn_Handler + ; 10 Interrupt 10 + + 96 0000006C 00000000 DCD TIMER3_IRQn_Handler + ; 11 Interrupt 11 + + 97 00000070 00000000 DCD WDG_IRQn_Handler + ; 12 Interrupt 12 + + 98 00000074 00000000 DCD UART_IRQn_Handler + ; 13 Interrupt 13 + + 99 00000078 00000000 DCD I2C0_IRQn_Handler + ; 14 Interrupt 14 + + 100 0000007C 00000000 DCD I2C1_IRQn_Handler + ; 15 Interrupt 15 + + 101 00000080 00000000 DCD SPIS_IRQn_Handler + ; 16 Interrupt 16 + + 102 00000084 00000000 DCD SPIM_IRQn_Handler + ; 17 Interrupt 17 + + 103 00000088 00000000 DCD VPRE1_IRQn_Handler + ; 18 Interrupt 18 + + 104 0000008C 00000000 DCD I2C2_IRQn_Handler + ; 19 Interrupt 19 + + 105 00000090 00000000 DCD OTP_IRQn_Handler + ; 20 Interrupt 20 + + 106 00000094 00000000 DCD SWIRE_IRQn_Handler + ; 21 Interrupt 21 + + 107 00000098 00000000 DCD PVD_IRQn_Handler + ; 22 Interrupt 22 + + 108 0000009C 00000000 DCD AP_NRESET_IRQn_Handler + ; 23 Interrupt 23 + + 109 000000A0 00000000 DCD EXTI_INT0_IRQn_Handler + ; 24 Interrupt 24 + + + + +ARM Macro Assembler Page 4 + + + 110 000000A4 00000000 DCD EXTI_INT1_IRQn_Handler + ; 25 Interrupt 25 + + 111 000000A8 00000000 DCD EXTI_INT2_IRQn_Handler + ; 26 Interrupt 26 + + 112 000000AC 00000000 DCD EXTI_INT3_IRQn_Handler + ; 27 Interrupt 27 + + 113 000000B0 00000000 DCD EXTI_INT4_IRQn_Handler + ; 28 Interrupt 28 + + 114 000000B4 00000000 DCD EXTI_INT5_IRQn_Handler + ; 29 Interrupt 29 + + 115 000000B8 00000000 DCD EXTI_INT6_IRQn_Handler + ; 30 Interrupt 30 + + 116 000000BC 00000000 DCD EXTI_INT7_IRQn_Handler + ; 31 Interrupt 31 + + 117 000000C0 + 118 000000C0 SPACE ( 0 * 4) ; Interrupts 10 .. + 31 are left out + 119 000000C0 + 120 000000C0 __Vectors_End + 121 000000C0 000000C0 + __Vectors_Size + EQU __Vectors_End - __Vectors + 122 000000C0 E000E180 + _NVIC_ICER0 + EQU 0xE000E180 ;清中断使能寄 + 存器地址 + 123 000000C0 E000E280 + _NVIC_ICPR0 + EQU 0xE000E280 ;清中断pending + 存器地址 + 124 000000C0 + 125 000000C0 AREA |.text|, CODE, READONLY + 126 00000000 + 127 00000000 ; Reset Handler + 128 00000000 + 129 00000000 Reset_Handler + PROC + 130 00000000 EXPORT Reset_Handler [WEAK +] + 131 00000000 IMPORT __main + 132 00000000 + 133 00000000 ;清中断使能和pending ——开始—— + 134 00000000 B672 CPSID I ; 屏蔽中断 + 135 00000002 4819 LDR R0, =_NVIC_ICER0 + 136 00000004 4919 LDR R1, =_NVIC_ICPR0 + 137 00000006 4A1A LDR R2, =0xFFFFFFFF + 138 00000008 2301 MOVS R3, #1 ; 设置循环次 + M0只有1组(32 + )中断，故只 + 要循环1次 + 139 0000000A _irq_clear + 140 0000000A ;CBZ R3, _irq_clear_end + + + +ARM Macro Assembler Page 5 + + + 141 0000000A 2B00 CMP R3,#0 ; 循环次数等 + 0，跳转到_irq_ + clear_end + 142 0000000C D103 BNE _irq_clear_end + 143 0000000E 6002 STR R2, [R0] ;,#4 ; NVIC_ICE + R0 - 清 enable IRQ + 寄存器 + 144 00000010 600A STR R2, [R1] ;,#4 ; NVIC_ICP + R0 - 清 pending IR + Q 寄存器 + 145 00000012 3B01 SUBS R3, #1 ; 循环数自减1 + + 146 00000014 E7F9 B _irq_clear + 147 00000016 _irq_clear_end + 148 00000016 ;清中断使能和pending ——结束—— + 149 00000016 B662 CPSIE I ; 开启中断 + 150 00000018 4816 LDR R0, =__main + 151 0000001A 4700 BX R0 + 152 0000001C ENDP + 153 0000001C + 154 0000001C + 155 0000001C ; Macro to define default exception/interrupt handlers. + 156 0000001C ; Default handler are weak symbols with an endless loop. + + 157 0000001C ; They can be overwritten by real handlers. + 158 0000001C MACRO + 159 0000001C Set_Default_Handler + $Handler_Name + 160 0000001C $Handler_Name + PROC + 161 0000001C EXPORT $Handler_Name [WEAK +] + 162 0000001C B . + 163 0000001C ENDP + 164 0000001C MEND + 165 0000001C + 166 0000001C + 167 0000001C ; Default exception/interrupt handler + 168 0000001C + 169 0000001C Set_Default_Handler + NMI_Handler + 160 0000001C NMI_Handler + PROC + 161 0000001C EXPORT NMI_Handler [WEAK] + 162 0000001C E7FE B . + 163 0000001E ENDP + 170 0000001E Set_Default_Handler + HardFault_Handler + 160 0000001E HardFault_Handler + PROC + 161 0000001E EXPORT HardFault_Handler [ +WEAK] + 162 0000001E E7FE B . + 163 00000020 ENDP + 171 00000020 Set_Default_Handler + SVC_Handler + 160 00000020 SVC_Handler + PROC + 161 00000020 EXPORT SVC_Handler [WEAK] + + + +ARM Macro Assembler Page 6 + + + 162 00000020 E7FE B . + 163 00000022 ENDP + 172 00000022 Set_Default_Handler + PendSV_Handler + 160 00000022 PendSV_Handler + PROC + 161 00000022 EXPORT PendSV_Handler [WEA +K] + 162 00000022 E7FE B . + 163 00000024 ENDP + 173 00000024 Set_Default_Handler + SysTick_Handler + 160 00000024 SysTick_Handler + PROC + 161 00000024 EXPORT SysTick_Handler [WE +AK] + 162 00000024 E7FE B . + 163 00000026 ENDP + 174 00000026 + 175 00000026 Set_Default_Handler + VIDC_IRQn_Handler + 160 00000026 VIDC_IRQn_Handler + PROC + 161 00000026 EXPORT VIDC_IRQn_Handler [ +WEAK] + 162 00000026 E7FE B . + 163 00000028 ENDP + 176 00000028 Set_Default_Handler + LCDC_IRQn_Handler + 160 00000028 LCDC_IRQn_Handler + PROC + 161 00000028 EXPORT LCDC_IRQn_Handler [ +WEAK] + 162 00000028 E7FE B . + 163 0000002A ENDP + 177 0000002A Set_Default_Handler + MIPI_RX_IRQn_Handler + 160 0000002A MIPI_RX_IRQn_Handler + PROC + 161 0000002A EXPORT MIPI_RX_IRQn_Handler + [WEAK] + 162 0000002A E7FE B . + 163 0000002C ENDP + 178 0000002C Set_Default_Handler + MIPI_TX_IRQn_Handler + 160 0000002C MIPI_TX_IRQn_Handler + PROC + 161 0000002C EXPORT MIPI_TX_IRQn_Handler + [WEAK] + 162 0000002C E7FE B . + 163 0000002E ENDP + 179 0000002E Set_Default_Handler + MEMC_IRQn_Handler + 160 0000002E MEMC_IRQn_Handler + PROC + 161 0000002E EXPORT MEMC_IRQn_Handler [ +WEAK] + 162 0000002E E7FE B . + 163 00000030 ENDP + + + +ARM Macro Assembler Page 7 + + + 180 00000030 Set_Default_Handler + VPRE_IRQn_Handler + 160 00000030 VPRE_IRQn_Handler + PROC + 161 00000030 EXPORT VPRE_IRQn_Handler [ +WEAK] + 162 00000030 E7FE B . + 163 00000032 ENDP + 181 00000032 Set_Default_Handler + FLSCTRL_IRQn_Handler + 160 00000032 FLSCTRL_IRQn_Handler + PROC + 161 00000032 EXPORT FLSCTRL_IRQn_Handler + [WEAK] + 162 00000032 E7FE B . + 163 00000034 ENDP + 182 00000034 Set_Default_Handler + DMA_IRQn_Handler + 160 00000034 DMA_IRQn_Handler + PROC + 161 00000034 EXPORT DMA_IRQn_Handler [W +EAK] + 162 00000034 E7FE B . + 163 00000036 ENDP + 183 00000036 Set_Default_Handler + TIMER0_IRQn_Handler + 160 00000036 TIMER0_IRQn_Handler + PROC + 161 00000036 EXPORT TIMER0_IRQn_Handler + [WEAK] + 162 00000036 E7FE B . + 163 00000038 ENDP + 184 00000038 Set_Default_Handler + TIMER1_IRQn_Handler + 160 00000038 TIMER1_IRQn_Handler + PROC + 161 00000038 EXPORT TIMER1_IRQn_Handler + [WEAK] + 162 00000038 E7FE B . + 163 0000003A ENDP + 185 0000003A + 186 0000003A Set_Default_Handler + TIMER2_IRQn_Handler + 160 0000003A TIMER2_IRQn_Handler + PROC + 161 0000003A EXPORT TIMER2_IRQn_Handler + [WEAK] + 162 0000003A E7FE B . + 163 0000003C ENDP + 187 0000003C Set_Default_Handler + TIMER3_IRQn_Handler + 160 0000003C TIMER3_IRQn_Handler + PROC + 161 0000003C EXPORT TIMER3_IRQn_Handler + [WEAK] + 162 0000003C E7FE B . + 163 0000003E ENDP + 188 0000003E Set_Default_Handler + WDG_IRQn_Handler + + + +ARM Macro Assembler Page 8 + + + 160 0000003E WDG_IRQn_Handler + PROC + 161 0000003E EXPORT WDG_IRQn_Handler [W +EAK] + 162 0000003E E7FE B . + 163 00000040 ENDP + 189 00000040 Set_Default_Handler + UART_IRQn_Handler + 160 00000040 UART_IRQn_Handler + PROC + 161 00000040 EXPORT UART_IRQn_Handler [ +WEAK] + 162 00000040 E7FE B . + 163 00000042 ENDP + 190 00000042 Set_Default_Handler + I2C0_IRQn_Handler + 160 00000042 I2C0_IRQn_Handler + PROC + 161 00000042 EXPORT I2C0_IRQn_Handler [ +WEAK] + 162 00000042 E7FE B . + 163 00000044 ENDP + 191 00000044 Set_Default_Handler + I2C1_IRQn_Handler + 160 00000044 I2C1_IRQn_Handler + PROC + 161 00000044 EXPORT I2C1_IRQn_Handler [ +WEAK] + 162 00000044 E7FE B . + 163 00000046 ENDP + 192 00000046 Set_Default_Handler + SPIS_IRQn_Handler + 160 00000046 SPIS_IRQn_Handler + PROC + 161 00000046 EXPORT SPIS_IRQn_Handler [ +WEAK] + 162 00000046 E7FE B . + 163 00000048 ENDP + 193 00000048 Set_Default_Handler + SPIM_IRQn_Handler + 160 00000048 SPIM_IRQn_Handler + PROC + 161 00000048 EXPORT SPIM_IRQn_Handler [ +WEAK] + 162 00000048 E7FE B . + 163 0000004A ENDP + 194 0000004A Set_Default_Handler + VPRE1_IRQn_Handler + 160 0000004A VPRE1_IRQn_Handler + PROC + 161 0000004A EXPORT VPRE1_IRQn_Handler +[WEAK] + 162 0000004A E7FE B . + 163 0000004C ENDP + 195 0000004C Set_Default_Handler + I2C2_IRQn_Handler + 160 0000004C I2C2_IRQn_Handler + PROC + 161 0000004C EXPORT I2C2_IRQn_Handler [ + + + +ARM Macro Assembler Page 9 + + +WEAK] + 162 0000004C E7FE B . + 163 0000004E ENDP + 196 0000004E + 197 0000004E Set_Default_Handler + OTP_IRQn_Handler + 160 0000004E OTP_IRQn_Handler + PROC + 161 0000004E EXPORT OTP_IRQn_Handler [W +EAK] + 162 0000004E E7FE B . + 163 00000050 ENDP + 198 00000050 Set_Default_Handler + SWIRE_IRQn_Handler + 160 00000050 SWIRE_IRQn_Handler + PROC + 161 00000050 EXPORT SWIRE_IRQn_Handler +[WEAK] + 162 00000050 E7FE B . + 163 00000052 ENDP + 199 00000052 Set_Default_Handler + PVD_IRQn_Handler + 160 00000052 PVD_IRQn_Handler + PROC + 161 00000052 EXPORT PVD_IRQn_Handler [W +EAK] + 162 00000052 E7FE B . + 163 00000054 ENDP + 200 00000054 Set_Default_Handler + AP_NRESET_IRQn_Handler + 160 00000054 AP_NRESET_IRQn_Handler + PROC + 161 00000054 EXPORT AP_NRESET_IRQn_Handler + [WEAK] + 162 00000054 E7FE B . + 163 00000056 ENDP + 201 00000056 Set_Default_Handler + EXTI_INT0_IRQn_Handler + 160 00000056 EXTI_INT0_IRQn_Handler + PROC + 161 00000056 EXPORT EXTI_INT0_IRQn_Handler + [WEAK] + 162 00000056 E7FE B . + 163 00000058 ENDP + 202 00000058 Set_Default_Handler + EXTI_INT1_IRQn_Handler + 160 00000058 EXTI_INT1_IRQn_Handler + PROC + 161 00000058 EXPORT EXTI_INT1_IRQn_Handler + [WEAK] + 162 00000058 E7FE B . + 163 0000005A ENDP + 203 0000005A Set_Default_Handler + EXTI_INT2_IRQn_Handler + 160 0000005A EXTI_INT2_IRQn_Handler + PROC + 161 0000005A EXPORT EXTI_INT2_IRQn_Handler + [WEAK] + 162 0000005A E7FE B . + + + +ARM Macro Assembler Page 10 + + + 163 0000005C ENDP + 204 0000005C Set_Default_Handler + EXTI_INT3_IRQn_Handler + 160 0000005C EXTI_INT3_IRQn_Handler + PROC + 161 0000005C EXPORT EXTI_INT3_IRQn_Handler + [WEAK] + 162 0000005C E7FE B . + 163 0000005E ENDP + 205 0000005E Set_Default_Handler + EXTI_INT4_IRQn_Handler + 160 0000005E EXTI_INT4_IRQn_Handler + PROC + 161 0000005E EXPORT EXTI_INT4_IRQn_Handler + [WEAK] + 162 0000005E E7FE B . + 163 00000060 ENDP + 206 00000060 Set_Default_Handler + EXTI_INT5_IRQn_Handler + 160 00000060 EXTI_INT5_IRQn_Handler + PROC + 161 00000060 EXPORT EXTI_INT5_IRQn_Handler + [WEAK] + 162 00000060 E7FE B . + 163 00000062 ENDP + 207 00000062 + 208 00000062 Set_Default_Handler + EXTI_INT6_IRQn_Handler + 160 00000062 EXTI_INT6_IRQn_Handler + PROC + 161 00000062 EXPORT EXTI_INT6_IRQn_Handler + [WEAK] + 162 00000062 E7FE B . + 163 00000064 ENDP + 209 00000064 Set_Default_Handler + EXTI_INT7_IRQn_Handler + 160 00000064 EXTI_INT7_IRQn_Handler + PROC + 161 00000064 EXPORT EXTI_INT7_IRQn_Handler + [WEAK] + 162 00000064 E7FE B . + 163 00000066 ENDP + 210 00000066 00 00 ALIGN + 211 00000068 + 212 00000068 + 213 00000068 ; User setup Stack & Heap + 214 00000068 + 215 00000068 IF :LNOT::DEF:__MICROLIB + 217 ENDIF + 218 00000068 + 219 00000068 EXPORT __stack_limit + 220 00000068 EXPORT __initial_sp + 221 00000068 IF Heap_Size != 0 + ; Heap is provided + 222 00000068 EXPORT __heap_base + 223 00000068 EXPORT __heap_limit + 224 00000068 ENDIF + 225 00000068 + 226 00000068 END + + + +ARM Macro Assembler Page 11 + + + E000E180 + E000E280 + FFFFFFFF + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M0 --apcs=interw +ork --depend=.\objects\startup_armcm0.d -o.\objects\startup_armcm0.o -I.\RTE\_W +L668 -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Inclu +de -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\ +Include --predefine="__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 528 +" --predefine="_RTE_ SETA 1" --predefine="ARMCM0 SETA 1" --list=.\listings\star +tup_armcm0.lst ..\..\src\board\startup\startup_ARMCM0.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 35 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 37 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + None +Comment: Stack_Mem unused +__initial_sp 00001000 + +Symbol: __initial_sp + Definitions + At line 38 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 66 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 220 in file ..\..\src\board\startup\startup_ARMCM0.s + +__stack_limit 00000000 + +Symbol: __stack_limit + Definitions + At line 36 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 219 in file ..\..\src\board\startup\startup_ARMCM0.s +Comment: __stack_limit used once +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 48 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 50 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + None +Comment: Heap_Mem unused +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 49 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 222 in file ..\..\src\board\startup\startup_ARMCM0.s +Comment: __heap_base used once +__heap_limit 00000C00 + +Symbol: __heap_limit + Definitions + At line 51 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 223 in file ..\..\src\board\startup\startup_ARMCM0.s +Comment: __heap_limit used once +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 61 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 66 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 62 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 121 in file ..\..\src\board\startup\startup_ARMCM0.s + +__Vectors_End 000000C0 + +Symbol: __Vectors_End + Definitions + At line 120 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 63 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 121 in file ..\..\src\board\startup\startup_ARMCM0.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 125 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + None +Comment: .text unused +AP_NRESET_IRQn_Handler 00000054 + +Symbol: AP_NRESET_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 200 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 108 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 200 in file ..\..\src\board\startup\startup_ARMCM0.s + +DMA_IRQn_Handler 00000034 + +Symbol: DMA_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 182 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 92 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 182 in file ..\..\src\board\startup\startup_ARMCM0.s + +EXTI_INT0_IRQn_Handler 00000056 + +Symbol: EXTI_INT0_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 201 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 109 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 201 in file ..\..\src\board\startup\startup_ARMCM0.s + +EXTI_INT1_IRQn_Handler 00000058 + +Symbol: EXTI_INT1_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 202 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 110 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 202 in file ..\..\src\board\startup\startup_ARMCM0.s + +EXTI_INT2_IRQn_Handler 0000005A + +Symbol: EXTI_INT2_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 203 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + At line 111 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 203 in file ..\..\src\board\startup\startup_ARMCM0.s + +EXTI_INT3_IRQn_Handler 0000005C + +Symbol: EXTI_INT3_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 204 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 112 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 204 in file ..\..\src\board\startup\startup_ARMCM0.s + +EXTI_INT4_IRQn_Handler 0000005E + +Symbol: EXTI_INT4_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 205 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 113 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 205 in file ..\..\src\board\startup\startup_ARMCM0.s + +EXTI_INT5_IRQn_Handler 00000060 + +Symbol: EXTI_INT5_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 206 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 114 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 206 in file ..\..\src\board\startup\startup_ARMCM0.s + +EXTI_INT6_IRQn_Handler 00000062 + +Symbol: EXTI_INT6_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 208 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 115 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 208 in file ..\..\src\board\startup\startup_ARMCM0.s + +EXTI_INT7_IRQn_Handler 00000064 + +Symbol: EXTI_INT7_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 209 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 116 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 209 in file ..\..\src\board\startup\startup_ARMCM0.s + + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + +FLSCTRL_IRQn_Handler 00000032 + +Symbol: FLSCTRL_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 181 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 91 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 181 in file ..\..\src\board\startup\startup_ARMCM0.s + +HardFault_Handler 0000001E + +Symbol: HardFault_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 170 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 69 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 170 in file ..\..\src\board\startup\startup_ARMCM0.s + +I2C0_IRQn_Handler 00000042 + +Symbol: I2C0_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 190 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 99 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 190 in file ..\..\src\board\startup\startup_ARMCM0.s + +I2C1_IRQn_Handler 00000044 + +Symbol: I2C1_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 191 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 100 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 191 in file ..\..\src\board\startup\startup_ARMCM0.s + +I2C2_IRQn_Handler 0000004C + +Symbol: I2C2_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 195 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 104 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 195 in file ..\..\src\board\startup\startup_ARMCM0.s + +LCDC_IRQn_Handler 00000028 + +Symbol: LCDC_IRQn_Handler + Definitions + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + At line 160 in macro Set_Default_Handler + at line 176 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 86 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 176 in file ..\..\src\board\startup\startup_ARMCM0.s + +MEMC_IRQn_Handler 0000002E + +Symbol: MEMC_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 179 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 89 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 179 in file ..\..\src\board\startup\startup_ARMCM0.s + +MIPI_RX_IRQn_Handler 0000002A + +Symbol: MIPI_RX_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 177 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 87 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 177 in file ..\..\src\board\startup\startup_ARMCM0.s + +MIPI_TX_IRQn_Handler 0000002C + +Symbol: MIPI_TX_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 178 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 88 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 178 in file ..\..\src\board\startup\startup_ARMCM0.s + +NMI_Handler 0000001C + +Symbol: NMI_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 169 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 68 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 169 in file ..\..\src\board\startup\startup_ARMCM0.s + +OTP_IRQn_Handler 0000004E + +Symbol: OTP_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 197 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 105 in file ..\..\src\board\startup\startup_ARMCM0.s + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + At line 161 in macro Set_Default_Handler + at line 197 in file ..\..\src\board\startup\startup_ARMCM0.s + +PVD_IRQn_Handler 00000052 + +Symbol: PVD_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 199 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 107 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 199 in file ..\..\src\board\startup\startup_ARMCM0.s + +PendSV_Handler 00000022 + +Symbol: PendSV_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 172 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 80 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 172 in file ..\..\src\board\startup\startup_ARMCM0.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 129 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 67 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 130 in file ..\..\src\board\startup\startup_ARMCM0.s + +SPIM_IRQn_Handler 00000048 + +Symbol: SPIM_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 193 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 102 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 193 in file ..\..\src\board\startup\startup_ARMCM0.s + +SPIS_IRQn_Handler 00000046 + +Symbol: SPIS_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 192 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 101 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 192 in file ..\..\src\board\startup\startup_ARMCM0.s + +SVC_Handler 00000020 + +Symbol: SVC_Handler + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 160 in macro Set_Default_Handler + at line 171 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 77 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 171 in file ..\..\src\board\startup\startup_ARMCM0.s + +SWIRE_IRQn_Handler 00000050 + +Symbol: SWIRE_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 198 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 106 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 198 in file ..\..\src\board\startup\startup_ARMCM0.s + +SysTick_Handler 00000024 + +Symbol: SysTick_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 173 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 81 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 173 in file ..\..\src\board\startup\startup_ARMCM0.s + +TIMER0_IRQn_Handler 00000036 + +Symbol: TIMER0_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 183 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 93 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 183 in file ..\..\src\board\startup\startup_ARMCM0.s + +TIMER1_IRQn_Handler 00000038 + +Symbol: TIMER1_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 184 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 94 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 184 in file ..\..\src\board\startup\startup_ARMCM0.s + +TIMER2_IRQn_Handler 0000003A + +Symbol: TIMER2_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 186 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + + At line 95 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 186 in file ..\..\src\board\startup\startup_ARMCM0.s + +TIMER3_IRQn_Handler 0000003C + +Symbol: TIMER3_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 187 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 96 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 187 in file ..\..\src\board\startup\startup_ARMCM0.s + +UART_IRQn_Handler 00000040 + +Symbol: UART_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 189 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 98 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 189 in file ..\..\src\board\startup\startup_ARMCM0.s + +VIDC_IRQn_Handler 00000026 + +Symbol: VIDC_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 175 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 85 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 175 in file ..\..\src\board\startup\startup_ARMCM0.s + +VPRE1_IRQn_Handler 0000004A + +Symbol: VPRE1_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 194 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 103 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 194 in file ..\..\src\board\startup\startup_ARMCM0.s + +VPRE_IRQn_Handler 00000030 + +Symbol: VPRE_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 180 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 90 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 180 in file ..\..\src\board\startup\startup_ARMCM0.s + + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + +WDG_IRQn_Handler 0000003E + +Symbol: WDG_IRQn_Handler + Definitions + At line 160 in macro Set_Default_Handler + at line 188 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 97 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 161 in macro Set_Default_Handler + at line 188 in file ..\..\src\board\startup\startup_ARMCM0.s + +_irq_clear 0000000A + +Symbol: _irq_clear + Definitions + At line 139 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 146 in file ..\..\src\board\startup\startup_ARMCM0.s +Comment: _irq_clear used once +_irq_clear_end 00000016 + +Symbol: _irq_clear_end + Definitions + At line 147 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 142 in file ..\..\src\board\startup\startup_ARMCM0.s +Comment: _irq_clear_end used once +41 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000C00 + +Symbol: Heap_Size + Definitions + At line 45 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 47 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 50 in file ..\..\src\board\startup\startup_ARMCM0.s + At line 221 in file ..\..\src\board\startup\startup_ARMCM0.s + +Stack_Size 00001000 + +Symbol: Stack_Size + Definitions + At line 33 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 37 in file ..\..\src\board\startup\startup_ARMCM0.s +Comment: Stack_Size used once +_NVIC_ICER0 E000E180 + +Symbol: _NVIC_ICER0 + Definitions + At line 122 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 135 in file ..\..\src\board\startup\startup_ARMCM0.s +Comment: _NVIC_ICER0 used once +_NVIC_ICPR0 E000E280 + +Symbol: _NVIC_ICPR0 + Definitions + At line 123 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 136 in file ..\..\src\board\startup\startup_ARMCM0.s +Comment: _NVIC_ICPR0 used once +__Vectors_Size 000000C0 + +Symbol: __Vectors_Size + Definitions + At line 121 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 64 in file ..\..\src\board\startup\startup_ARMCM0.s +Comment: __Vectors_Size used once +5 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +__main 00000000 + +Symbol: __main + Definitions + At line 131 in file ..\..\src\board\startup\startup_ARMCM0.s + Uses + At line 150 in file ..\..\src\board\startup\startup_ARMCM0.s +Comment: __main used once +1 symbol +394 symbols in table diff --git a/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.axf b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.axf new file mode 100644 index 0000000..e85de55 Binary files /dev/null and b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.axf differ diff --git a/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.bin b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.bin new file mode 100644 index 0000000..8a031ef Binary files /dev/null and b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.bin differ diff --git a/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.build_log.htm b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.build_log.htm new file mode 100644 index 0000000..5b33201 --- /dev/null +++ b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.build_log.htm @@ -0,0 +1,77 @@ + + +
+
Vision Build Log

+
Tool Versions:

+IDE-Version: Vision V5.28.0.0
+Copyright (C) 2019 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: HAHA Markin, HAHA, LIC=VGXG8-3CKFQ-63XMB-246PQ-J4CUG-RTS7K
+ 
+Tool Versions:
+Toolchain:       MDK-ARM Plus  Version: 5.28.0.0
+Toolchain Path:  C:\Keil_v5\ARM\ARMCC\Bin
+C Compiler:      Armcc.exe V5.06 update 6 (build 750)
+Assembler:       Armasm.exe V5.06 update 6 (build 750)
+Linker/Locator:  ArmLink.exe V5.06 update 6 (build 750)
+Library Manager: ArmAr.exe V5.06 update 6 (build 750)
+Hex Converter:   FromElf.exe V5.06 update 6 (build 750)
+CPU DLL:         SARMCM3.DLL V5.28.0.0
+Dialog DLL:      DARMCM1.DLL V1.19.2.0
+Target DLL:      UL2CM3.DLL V1.162.16.0
+Dialog DLL:      TARMCM1.DLL V1.14.1.0
+ 
+
Project:

+D:\Custom\\WL668_Pixel 8 Pro_TM667_ICNA3508(RAMLESS)_ CST6656S_OLED\Դ\WL668_GOOGLEP8P_TM667_ICNA3508_OLED_FHD_20240315\WL668_GOOGLEP8P_TM667_ICNA3508_20240306_5608\project\WL668\WL668.uvprojx
+Project File Date:  04/01/2024
+
+
Output:

+*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
+Rebuild target 'WL668'
+creating preprocessor file for main.c...
+compiling main.c...
+creating preprocessor file for p8p_demo.c...
+compiling p8p_demo.c...
+..\..\src\app\P8P\p8p_demo.c(131): warning:  #550-D: variable "sg_exit_idle_mode_flag"  was set but never used
+  static bool sg_exit_idle_mode_flag = false;
+..\..\src\app\P8P\p8p_demo.c(134): warning:  #177-D: variable "pps_renew_flag"  was declared but never referenced
+  static uint32_t pps_renew_flag = 0;
+..\..\src\app\P8P\p8p_demo.c(135): warning:  #177-D: variable "pwr_rst_flag"  was declared but never referenced
+  static uint32_t pwr_rst_flag = 0;
+..\..\src\app\P8P\p8p_demo.c(149): warning:  #177-D: function "app_mipi_rx_start_cb"  was declared but never referenced
+  static void app_mipi_rx_start_cb(void *data);
+..\..\src\app\P8P\p8p_demo.c(459): warning:  #177-D: variable "reg53_E8_fg"  was declared but never referenced
+  static bool reg53_E8_fg=0;
+..\..\src\app\P8P\p8p_demo.c(538): warning:  #177-D: function "ap_dcs_set_exit_idle_mode"  was declared but never referenced
+  static bool ap_dcs_set_exit_idle_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet)
+..\..\src\app\P8P\p8p_demo.c(563): warning:  #177-D: function "soft_te_timer_init"  was declared but never referenced
+  static void soft_te_timer_init()
+..\..\src\app\P8P\p8p_demo.c: 7 warnings, 0 errors
+creating preprocessor file for board.c...
+compiling board.c...
+assembling startup_ARMCM0.s...
+linking...
+Program Size: Code=37316 RO-data=9156 RW-data=1040 ZI-data=11608  
+FromELF: creating hex file...
+After Build - User command #1: fromelf  --bin  -o  .\Objects\WL668_P8P_TM667_ICNA3508_20240401.bin  .\Objects\WL668_P8P_TM667_ICNA3508_20240401.axf
+".\Objects\WL668_P8P_TM667_ICNA3508_20240401.axf" - 0 Error(s), 7 Warning(s).
+
+
Software Packages used:

+
+Package Vendor: ARM
+                http://www.keil.com/pack/ARM.CMSIS.5.5.1.pack
+                ARM.CMSIS.5.5.1
+                CMSIS (Cortex Microcontroller Software Interface Standard)
+   * Component: CORE Version: 5.2.0
+
+
Collection of Component include folders:

+  .\RTE\_WL668
+  C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include
+  C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include
+
+
Collection of Component Files used:

+
+   * Component: ARM::CMSIS:CORE:5.2.0
+Build Time Elapsed:  00:00:02
+
+ + diff --git a/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.hex b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.hex new file mode 100644 index 0000000..d8b2f0d --- /dev/null +++ b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.hex @@ -0,0 +1,2931 @@ +:020000040001F9 +:1000000068310700D5000100F1000100A90B0100D3 +:1000100000000000000000000000000000000000E0 +:10002000000000000000000000000000F5000100DA +:100030000000000000000000F7000100750E010044 +:10004000B50E0100F10B0100451001008D0D0100FE +:10005000F10C0100ED0E010007010100FD0A010095 +:100060008D0E0100970E0100A10E0100AB0E0100E4 +:1000700013010100A913010017010100190101007A +:100080001B0101001D010100D10E01002101010031 +:1000900023010100450E010027010100E10A0100D2 +:1000A000590B0100630B01006D0B0100770B010080 +:1000B000810B01008B0B0100950B01009F0B0100D0 +:1000C0000348854600F0CEFC0048004761870100E8 +:1000D0006831070072B6194819491A4A0123002BE2 +:1000E00003D102600A60013BF9E762B61648004797 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+

Static Call Graph for image .\Objects\WL668_P8P_TM667_ICNA3508_20240401.axf

+

#<CALLGRAPH># ARM Linker, 5060750: Last Updated: Wed Apr 03 15:42:24 2024 +

+

Maximum Stack Usage = 656 bytes + Unknown(Cycles, Untraceable Function Pointers)

+Call chain for Maximum Stack Depth:

+main ⇒ google_p8p_demo ⇒ app_system_process ⇒ app_system_resume ⇒ app_display_init ⇒ app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +

+

+Mutually Recursive functions +

  • NMI_Handler   ⇒   NMI_Handler
    +
  • SVC_Handler   ⇒   SVC_Handler
    +
  • PendSV_Handler   ⇒   PendSV_Handler
    +
  • FLSCTRL_IRQn_Handler   ⇒   FLSCTRL_IRQn_Handler
    +
  • WDG_IRQn_Handler   ⇒   WDG_IRQn_Handler
    +
  • I2C0_IRQn_Handler   ⇒   I2C0_IRQn_Handler
    +
  • I2C1_IRQn_Handler   ⇒   I2C1_IRQn_Handler
    +
  • SPIS_IRQn_Handler   ⇒   SPIS_IRQn_Handler
    +
  • SPIM_IRQn_Handler   ⇒   SPIM_IRQn_Handler
    +
  • I2C2_IRQn_Handler   ⇒   I2C2_IRQn_Handler
    +
  • OTP_IRQn_Handler   ⇒   OTP_IRQn_Handler
    +
  • PVD_IRQn_Handler   ⇒   PVD_IRQn_Handler
    + +

    +

    +Function Pointers +

      +
    • AP_NRESET_IRQn_Handler from drv_gpio.o(i.AP_NRESET_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • DMA_IRQn_Handler from drv_dma.o(i.DMA_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT0_IRQn_Handler from drv_gpio.o(i.EXTI_INT0_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT1_IRQn_Handler from drv_gpio.o(i.EXTI_INT1_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT2_IRQn_Handler from drv_gpio.o(i.EXTI_INT2_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT3_IRQn_Handler from drv_gpio.o(i.EXTI_INT3_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT4_IRQn_Handler from drv_gpio.o(i.EXTI_INT4_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT5_IRQn_Handler from drv_gpio.o(i.EXTI_INT5_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT6_IRQn_Handler from drv_gpio.o(i.EXTI_INT6_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT7_IRQn_Handler from drv_gpio.o(i.EXTI_INT7_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • FLSCTRL_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • HardFault_Handler from drv_common.o(i.HardFault_Handler) referenced from startup_armcm0.o(RESET) +
    • I2C0_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • I2C1_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • I2C2_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • LCDC_IRQn_Handler from hal_internal_vsync.o(i.LCDC_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • MEMC_IRQn_Handler from drv_memc.o(i.MEMC_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • MIPI_RX_IRQn_Handler from drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • MIPI_TX_IRQn_Handler from drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • NMI_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • OTP_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • PVD_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • PendSV_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • Reset_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • SPIM_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • SPIS_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • SVC_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • SWIRE_IRQn_Handler from drv_swire.o(i.SWIRE_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • SysTick_Handler from drv_common.o(i.SysTick_Handler) referenced from startup_armcm0.o(RESET) +
    • TIMER0_IRQn_Handler from drv_timer.o(i.TIMER0_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • TIMER1_IRQn_Handler from drv_timer.o(i.TIMER1_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • TIMER2_IRQn_Handler from drv_timer.o(i.TIMER2_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • TIMER3_IRQn_Handler from drv_timer.o(i.TIMER3_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • UART_IRQn_Handler from drv_uart.o(i.UART_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • VIDC_IRQn_Handler from drv_vidc.o(i.VIDC_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • VPRE1_IRQn_Handler from drv_rxbr.o(i.VPRE1_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • VPRE_IRQn_Handler from hal_internal_dcs.o(i.VPRE_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • WDG_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_armcm0.o(.text) +
    • _sputc from printfa.o(i._sputc) referenced from printfa.o(i.__0vsprintf) +
    • ap_dcs_read from p8p_demo.o(i.ap_dcs_read) referenced from p8p_demo.o(i.app_mipi_rx_init) +
    • ap_dcs_set_backlight from p8p_demo.o(i.ap_dcs_set_backlight) referenced from p8p_demo.o(.constdata) +
    • ap_dcs_set_display_off from p8p_demo.o(i.ap_dcs_set_display_off) referenced from p8p_demo.o(.constdata) +
    • ap_dcs_set_display_on from p8p_demo.o(i.ap_dcs_set_display_on) referenced from p8p_demo.o(.constdata) +
    • ap_dcs_set_enter_sleep_mode from p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) referenced from p8p_demo.o(.constdata) +
    • ap_dcs_set_exit_sleep_mode from p8p_demo.o(i.ap_dcs_set_exit_sleep_mode) referenced from p8p_demo.o(.constdata) +
    • ap_dcs_set_frame_change from p8p_demo.o(i.ap_dcs_set_frame_change) referenced from p8p_demo.o(.constdata) +
    • ap_rstn_pull_down_cb from p8p_demo.o(i.ap_rstn_pull_down_cb) referenced from p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) +
    • ap_rstn_pull_high_cb from p8p_demo.o(i.ap_rstn_pull_high_cb) referenced from p8p_demo.o(i.app_system_suspend) +
    • ap_set_FPS_53 from p8p_demo.o(i.ap_set_FPS_53) referenced from p8p_demo.o(.constdata) +
    • fputc from tau_log.o(i.fputc) referenced from printfa.o(i.__0printf) +
    • hal_nonshadow_func_update from hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) referenced from hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) +
    • hal_tx_frame_rate_adjust from hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) referenced from hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) +
    • hal_vsync_func_update from hal_dsi_tx_ctrl.o(i.hal_vsync_func_update) referenced from hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) +
    • main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B) +
    • pps_update_handle from p8p_demo.o(i.pps_update_handle) referenced from p8p_demo.o(i.app_mipi_rx_init) +
    • rxbr_irq1_callback from hal_internal_vsync.o(i.rxbr_irq1_callback) referenced from hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    • soft_gen_te from hal_internal_vsync.o(i.soft_gen_te) referenced from hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    • soft_gen_te_double_buffer from hal_internal_vsync.o(i.soft_gen_te_double_buffer) referenced from hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    • stop_sleep_cb from hal_pwr.o(i.stop_sleep_cb) referenced from hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) +
    • svs_sync_handle from hal_internal_svs.o(i.svs_sync_handle) referenced from hal_internal_svs.o(i.svs_wait_fr_stab) +
    • svs_wait_fr_stab from hal_internal_svs.o(i.svs_wait_fr_stab) referenced from hal_internal_svs.o(i.svs_wait_start) +
    • svs_wait_start from hal_internal_svs.o(i.svs_wait_start) referenced from hal_internal_svs.o(i.hal_intl_svs_deinit_rx) +
    • svs_wait_start from hal_internal_svs.o(i.svs_wait_start) referenced from hal_internal_svs.o(i.hal_intl_svs_init_rx) +
    • vidc_callback from hal_internal_vsync.o(i.vidc_callback) referenced from hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    +

    +

    +Global Symbols +

    +

    __main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000)) +
    [Address Reference Count : 1]

    • startup_armcm0.o(.text) +
    +

    _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001)) + +

    _main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Calls]

    • >>   __scatterload +
    + +

    __main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Called By]

    • >>   __scatterload +
    + +

    _main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008)) + +

    _main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A)) + +

    _main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B)) + +

    __rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D)) + +

    __rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F)) + +

    Reset_Handler (Thumb, 28 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_armcm0.o(RESET) +
    +

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   NMI_Handler +
    +
    [Called By]
    • >>   NMI_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   SVC_Handler +
    +
    [Called By]
    • >>   SVC_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   PendSV_Handler +
    +
    [Called By]
    • >>   PendSV_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    FLSCTRL_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   FLSCTRL_IRQn_Handler +
    +
    [Called By]
    • >>   FLSCTRL_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    WDG_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   WDG_IRQn_Handler +
    +
    [Called By]
    • >>   WDG_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    I2C0_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   I2C0_IRQn_Handler +
    +
    [Called By]
    • >>   I2C0_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    I2C1_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   I2C1_IRQn_Handler +
    +
    [Called By]
    • >>   I2C1_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    SPIS_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   SPIS_IRQn_Handler +
    +
    [Called By]
    • >>   SPIS_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    SPIM_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   SPIM_IRQn_Handler +
    +
    [Called By]
    • >>   SPIM_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    I2C2_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   I2C2_IRQn_Handler +
    +
    [Called By]
    • >>   I2C2_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    OTP_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   OTP_IRQn_Handler +
    +
    [Called By]
    • >>   OTP_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    PVD_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   PVD_IRQn_Handler +
    +
    [Called By]
    • >>   PVD_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    __aeabi_uidiv (Thumb, 0 bytes, Stack size 12 bytes, uidiv.o(.text), UNUSED) + +

    __aeabi_uidivmod (Thumb, 44 bytes, Stack size 12 bytes, uidiv.o(.text)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_internal_vsync_set_tear_mode +
    • >>   drv_dsi_tx_phy_test_setup +
    • >>   hal_lcdc_upscaler_config +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_timing_info_update +
    • >>   hal_dsi_tx_init_dpi_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   drv_dsi_rx_set_up_phy +
    • >>   drv_crgu_get_rxbr_clk +
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    • >>   hal_swire_init +
    • >>   hal_dsi_rx_ctrl_init +
    • >>   svs_wait_fr_stab +
    • >>   svs_get_rel_intv +
    • >>   svs_direct_mode_setting +
    • >>   hal_intl_fb_edge_resize +
    • >>   hal_intl_fb_check_bandwidth +
    • >>   ha_intl_fb_check_pu_size +
    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_vsync_reset_lcdc_scaler +
    • >>   drv_timer_set_compare_val +
    • >>   __aeabi_idivmod +
    • >>   drv_uart_set_baud_rate +
    • >>   _printf_core +
    + +

    __aeabi_idiv (Thumb, 0 bytes, Stack size 16 bytes, idiv.o(.text), UNUSED) + +

    __aeabi_idivmod (Thumb, 40 bytes, Stack size 16 bytes, idiv.o(.text)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = __aeabi_idivmod ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   ap_dcs_set_backlight +
    + +

    __aeabi_memcpy (Thumb, 36 bytes, Stack size 0 bytes, memcpya.o(.text)) +

    [Called By]

    • >>   hal_intl_fb_cal_fb_info +
    • >>   tau_log_push_log +
    + +

    __aeabi_memcpy4 (Thumb, 0 bytes, Stack size 0 bytes, memcpya.o(.text)) +

    [Called By]

    • >>   hal_intl_fb_get_tx_fb_info +
    • >>   hal_internal_vsync_init_tx +
    • >>   hal_dsi_tx_init_dpi_timing +
    • >>   hal_intl_fb_get_rx_fb_info +
    • >>   hal_internal_vsync_init_rx +
    • >>   hal_internal_sync_input_resolution_change +
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   hal_intl_fb_cal_fb_info +
    + +

    __aeabi_memcpy8 (Thumb, 0 bytes, Stack size 0 bytes, memcpya.o(.text), UNUSED) + +

    __aeabi_memset (Thumb, 14 bytes, Stack size 0 bytes, memseta.o(.text)) +

    [Called By]

    • >>   hal_intl_dcs_set_auto_hw_filter +
    • >>   _memset$wrapper +
    • >>   __aeabi_memclr +
    + +

    __aeabi_memset4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED) + +

    __aeabi_memset8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED) + +

    __aeabi_memclr (Thumb, 4 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_memset +
    + +

    __aeabi_memclr4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text)) +

    [Called By]

    • >>   hal_internal_vsync_init_tx +
    • >>   hal_dsi_tx_init_cfg +
    • >>   hal_dsi_tx_ctrl_deinit +
    • >>   hal_dsi_tx_ctrl_create_handle +
    • >>   hal_dsi_rx_ctrl_create_handle +
    • >>   tau_log_printf +
    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_intl_svs_init_rx +
    • >>   hal_intl_fb_cal_fb_info +
    • >>   hal_internal_vsync_deinit +
    • >>   drv_uart_trans_create_handle +
    • >>   hal_uart_init +
    + +

    __aeabi_memclr8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED) + +

    _memset$wrapper (Thumb, 18 bytes, Stack size 8 bytes, memseta.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_memset +
    + +

    strlen (Thumb, 14 bytes, Stack size 0 bytes, strlen.o(.text)) +

    [Called By]

    • >>   tau_log_printf +
    + +

    __aeabi_fadd (Thumb, 162 bytes, Stack size 24 bytes, fadd.o(.text)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = __aeabi_fadd ⇒ _float_epilogue +
    +
    [Calls]
    • >>   _float_round +
    • >>   _float_epilogue +
    +
    [Called By]
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   __aeabi_fsub +
    • >>   __aeabi_frsub +
    + +

    __aeabi_fsub (Thumb, 8 bytes, Stack size 0 bytes, fadd.o(.text)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = __aeabi_fsub ⇒ __aeabi_fadd ⇒ _float_epilogue +
    +
    [Calls]
    • >>   __aeabi_fadd +
    +
    [Called By]
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    + +

    __aeabi_frsub (Thumb, 8 bytes, Stack size 0 bytes, fadd.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_fadd +
    + +

    __aeabi_fmul (Thumb, 122 bytes, Stack size 16 bytes, fmul.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_fmul +
    +
    [Called By]
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   svs_wait_start +
    • >>   svs_wait_fr_stab +
    • >>   svs_sync_handle +
    + +

    __aeabi_fdiv (Thumb, 124 bytes, Stack size 16 bytes, fdiv.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_fdiv +
    +
    [Calls]
    • >>   _float_round +
    +
    [Called By]
    • >>   hal_lcdc_init_clk +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   svs_wait_start +
    • >>   svs_sync_handle +
    + +

    __ARM_scalbnf (Thumb, 24 bytes, Stack size 0 bytes, fscalb.o(.text)) +

    [Called By]

    • >>   hal_lcdc_init_clk +
    + +

    scalbnf (Thumb, 0 bytes, Stack size 0 bytes, fscalb.o(.text), UNUSED) + +

    __aeabi_dadd (Thumb, 328 bytes, Stack size 48 bytes, dadd.o(.text)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_lasr +
    • >>   __aeabi_llsl +
    • >>   _double_round +
    • >>   _double_epilogue +
    +
    [Called By]
    • >>   hal_lcdc_upscaler_config +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   svs_sync_handle +
    • >>   hal_vsync_reset_lcdc_scaler +
    • >>   __aeabi_drsub +
    • >>   ceil +
    • >>   __aeabi_dsub +
    • >>   _fp_digits +
    + +

    __aeabi_dsub (Thumb, 12 bytes, Stack size 8 bytes, dadd.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_dadd +
    + +

    __aeabi_drsub (Thumb, 12 bytes, Stack size 8 bytes, dadd.o(.text)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_dadd +
    +
    [Called By]
    • >>   ceil +
    + +

    __aeabi_dmul (Thumb, 202 bytes, Stack size 72 bytes, dmul.o(.text)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   _double_epilogue +
    +
    [Called By]
    • >>   hal_intl_svs_update_rxbr_clk +
    • >>   _fp_digits +
    + +

    __aeabi_ui2f (Thumb, 14 bytes, Stack size 8 bytes, ffltui.o(.text)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = __aeabi_ui2f ⇒ _float_epilogue +
    +
    [Calls]
    • >>   _float_epilogue +
    +
    [Called By]
    • >>   hal_lcdc_init_clk +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   svs_wait_start +
    • >>   svs_wait_fr_stab +
    • >>   svs_sync_handle +
    + +

    __aeabi_ui2d (Thumb, 24 bytes, Stack size 16 bytes, dfltui.o(.text)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = __aeabi_ui2d ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   _double_epilogue +
    +
    [Called By]
    • >>   hal_lcdc_upscaler_config +
    • >>   hal_intl_svs_update_rxbr_clk +
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   hal_vsync_reset_lcdc_scaler +
    + +

    __aeabi_f2uiz (Thumb, 40 bytes, Stack size 0 bytes, ffixui.o(.text)) +

    [Called By]

    • >>   svs_wait_fr_stab +
    + +

    __aeabi_d2uiz (Thumb, 50 bytes, Stack size 8 bytes, dfixui.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_d2uiz ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_llsr +
    +
    [Called By]
    • >>   hal_lcdc_upscaler_config +
    • >>   hal_lcdc_init_clk +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   hal_intl_svs_update_rxbr_clk +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   svs_wait_start +
    • >>   svs_sync_handle +
    • >>   hal_vsync_reset_lcdc_scaler +
    + +

    __aeabi_f2d (Thumb, 40 bytes, Stack size 0 bytes, f2d.o(.text)) +

    [Called By]

    • >>   hal_lcdc_init_clk +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   svs_wait_start +
    • >>   svs_sync_handle +
    + +

    __aeabi_d2f (Thumb, 56 bytes, Stack size 8 bytes, d2f.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_d2f +
    +
    [Calls]
    • >>   _float_round +
    +
    [Called By]
    • >>   hal_dsi_tx_timing_info_update +
    + +

    __aeabi_cfcmpeq (Thumb, 0 bytes, Stack size 0 bytes, cfcmple.o(.text), UNUSED) + +

    __aeabi_cfcmple (Thumb, 20 bytes, Stack size 0 bytes, cfcmple.o(.text)) +

    [Called By]

    • >>   hal_tx_frame_rate_adjust +
    + +

    __aeabi_cfrcmple (Thumb, 20 bytes, Stack size 0 bytes, cfrcmple.o(.text)) +

    [Called By]

    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    + +

    __aeabi_uldivmod (Thumb, 96 bytes, Stack size 48 bytes, uldiv.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_llsr +
    • >>   __aeabi_llsl +
    +
    [Called By]
    • >>   _printf_core +
    • >>   _fp_digits +
    + +

    __aeabi_llsl (Thumb, 32 bytes, Stack size 8 bytes, llshl.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_llsl +
    +
    [Called By]
    • >>   __aeabi_dadd +
    • >>   __aeabi_uldivmod +
    • >>   _double_epilogue +
    • >>   __aeabi_d2ulz +
    + +

    _ll_shift_l (Thumb, 0 bytes, Stack size 8 bytes, llshl.o(.text), UNUSED) + +

    __aeabi_llsr (Thumb, 34 bytes, Stack size 8 bytes, llushr.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_llsr +
    +
    [Called By]
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_uldivmod +
    • >>   _double_epilogue +
    • >>   __aeabi_d2ulz +
    + +

    _ll_ushift_r (Thumb, 0 bytes, Stack size 8 bytes, llushr.o(.text), UNUSED) + +

    __aeabi_lasr (Thumb, 38 bytes, Stack size 8 bytes, llsshr.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_lasr +
    +
    [Called By]
    • >>   __aeabi_dadd +
    + +

    _ll_sshift_r (Thumb, 0 bytes, Stack size 8 bytes, llsshr.o(.text), UNUSED) + +

    __I$use$fp (Thumb, 0 bytes, Stack size 0 bytes, iusefp.o(.text), UNUSED) + +

    _float_round (Thumb, 16 bytes, Stack size 0 bytes, fepilogue.o(.text)) +

    [Called By]

    • >>   __aeabi_fdiv +
    • >>   __aeabi_fadd +
    • >>   __aeabi_d2f +
    + +

    _float_epilogue (Thumb, 114 bytes, Stack size 12 bytes, fepilogue.o(.text)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = _float_epilogue +
    +
    [Called By]
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fadd +
    + +

    _double_round (Thumb, 26 bytes, Stack size 8 bytes, depilogue.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = _double_round +
    +
    [Called By]
    • >>   __aeabi_dadd +
    • >>   _double_epilogue +
    • >>   __aeabi_ddiv +
    + +

    _double_epilogue (Thumb, 164 bytes, Stack size 48 bytes, depilogue.o(.text)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __ARM_clz +
    • >>   __aeabi_llsr +
    • >>   __aeabi_llsl +
    • >>   _double_round +
    +
    [Called By]
    • >>   __aeabi_ui2d +
    • >>   __aeabi_dadd +
    • >>   __aeabi_dmul +
    + +

    __aeabi_ddiv (Thumb, 234 bytes, Stack size 40 bytes, ddiv.o(.text), UNUSED) +

    [Calls]

    • >>   _double_round +
    +
    [Called By]
    • >>   _fp_digits +
    + +

    __aeabi_d2ulz (Thumb, 54 bytes, Stack size 8 bytes, dfixul.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_llsr +
    • >>   __aeabi_llsl +
    +
    [Called By]
    • >>   _fp_digits +
    + +

    __aeabi_cdrcmple (Thumb, 38 bytes, Stack size 0 bytes, cdrcmple.o(.text)) +

    [Called By]

    • >>   ceil +
    • >>   _fp_digits +
    + +

    __scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text)) +

    [Calls]

    • >>   __main_after_scatterload +
    +
    [Called By]
    • >>   _main_scatterload +
    + +

    __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED) + +

    __decompress (Thumb, 0 bytes, Stack size unknown bytes, __dczerorl2.o(.text), UNUSED) + +

    __decompress1 (Thumb, 86 bytes, Stack size unknown bytes, __dczerorl2.o(.text), UNUSED) + +

    AP_NRESET_IRQn_Handler (Thumb, 22 bytes, Stack size 8 bytes, drv_gpio.o(i.AP_NRESET_IRQn_Handler)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = AP_NRESET_IRQn_Handler ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    DMA_IRQn_Handler (Thumb, 78 bytes, Stack size 24 bytes, drv_dma.o(i.DMA_IRQn_Handler)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = DMA_IRQn_Handler ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    • >>   drv_dma_clear_status +
    • >>   drv_dma_get_int_source +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT0_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT0_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT0_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT1_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT1_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT1_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT2_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT2_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT2_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT3_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT3_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT3_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT4_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT4_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT4_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT5_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT5_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT5_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT6_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT6_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT6_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT7_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT7_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT7_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    HardFault_Handler (Thumb, 14 bytes, Stack size 0 bytes, drv_common.o(i.HardFault_Handler)) +

    [Stack]

    • Max Depth = 336
    • Call Chain = HardFault_Handler ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    LCDC_IRQn_Handler (Thumb, 118 bytes, Stack size 24 bytes, hal_internal_vsync.o(i.LCDC_IRQn_Handler)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = LCDC_IRQn_Handler ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    MEMC_IRQn_Handler (Thumb, 154 bytes, Stack size 8 bytes, drv_memc.o(i.MEMC_IRQn_Handler)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = MEMC_IRQn_Handler ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    • >>   drv_memc_get_status +
    • >>   drv_memc_clear_status +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    MIPI_TX_IRQn_Handler (Thumb, 70 bytes, Stack size 24 bytes, drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = MIPI_TX_IRQn_Handler ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    SWIRE_IRQn_Handler (Thumb, 38 bytes, Stack size 8 bytes, drv_swire.o(i.SWIRE_IRQn_Handler)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = SWIRE_IRQn_Handler ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    SysTick_Handler (Thumb, 20 bytes, Stack size 0 bytes, drv_common.o(i.SysTick_Handler)) +
    [Address Reference Count : 1]

    • startup_armcm0.o(RESET) +
    +

    TIMER0_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_timer.o(i.TIMER0_IRQn_Handler)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = TIMER0_IRQn_Handler ⇒ drv_timer_handle_interrupt ⇒ drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_timer_handle_interrupt +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    TIMER1_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_timer.o(i.TIMER1_IRQn_Handler)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = TIMER1_IRQn_Handler ⇒ drv_timer_handle_interrupt ⇒ drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_timer_handle_interrupt +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    TIMER2_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_timer.o(i.TIMER2_IRQn_Handler)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = TIMER2_IRQn_Handler ⇒ drv_timer_handle_interrupt ⇒ drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_timer_handle_interrupt +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    TIMER3_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_timer.o(i.TIMER3_IRQn_Handler)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = TIMER3_IRQn_Handler ⇒ drv_timer_handle_interrupt ⇒ drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_timer_handle_interrupt +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    VIDC_IRQn_Handler (Thumb, 22 bytes, Stack size 8 bytes, drv_vidc.o(i.VIDC_IRQn_Handler)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = VIDC_IRQn_Handler ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    VPRE1_IRQn_Handler (Thumb, 22 bytes, Stack size 8 bytes, drv_rxbr.o(i.VPRE1_IRQn_Handler)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = VPRE1_IRQn_Handler ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    VPRE_IRQn_Handler (Thumb, 116 bytes, Stack size 16 bytes, hal_internal_dcs.o(i.VPRE_IRQn_Handler)) +

    [Stack]

    • Max Depth = 544
    • Call Chain = VPRE_IRQn_Handler ⇒ hal_intl_dcs_rx_receive_packet ⇒ hal_intl_dcs_rx_receive_pps ⇒ drv_dsc_dec_enable ⇒ drv_se_set_dsc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_crgu_set_dsc_clk +
    • >>   drv_dsc_dec_get_nslc +
    • >>   hal_intl_dcs_rx_receive_packet +
    • >>   drv_rxbr_get_status0 +
    • >>   drv_rxbr_clear_status0 +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    __0printf (Thumb, 24 bytes, Stack size 24 bytes, printfa.o(i.__0printf), UNUSED) +

    [Calls]

    • >>   _printf_core +
    + +

    __1printf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0printf), UNUSED) + +

    __2printf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0printf)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = __2printf +
    +
    [Called By]
    • >>   tau_log_printf +
    + +

    __c89printf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0printf), UNUSED) + +

    printf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0printf), UNUSED) + +

    __0vsprintf (Thumb, 30 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf), UNUSED) +

    [Calls]

    • >>   _sputc +
    • >>   _printf_core +
    + +

    __1vsprintf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf), UNUSED) + +

    __2vsprintf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf), UNUSED) + +

    __c89vsprintf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf), UNUSED) + +

    vsprintf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = vsprintf +
    +
    [Called By]
    • >>   tau_log_printf +
    + +

    __ARM_clz (Thumb, 46 bytes, Stack size 0 bytes, depilogue.o(i.__ARM_clz)) +

    [Called By]

    • >>   _double_epilogue +
    + +

    __ARM_common_switch8 (Thumb, 26 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.__ARM_common_switch8)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __ARM_common_switch8 +
    +
    [Called By]
    • >>   drv_dsi_tx_phy_status_stopstate +
    • >>   hal_dsi_rx_ctrl_init_memc +
    • >>   drv_dsi_rx_get_color_bpp +
    + +

    __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED) + +

    MIPI_RX_IRQn_Handler (Thumb, 354 bytes, Stack size 24 bytes, drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = MIPI_RX_IRQn_Handler ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    UART_IRQn_Handler (Thumb, 364 bytes, Stack size 32 bytes, drv_uart.o(i.UART_IRQn_Handler)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = UART_IRQn_Handler ⇒ drv_uart_abort_send ⇒ drv_uart_reset_tx_fifo ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    • >>   drv_uart_config_int +
    • >>   drv_uart_abort_send +
    • >>   drv_uart_abort_recv +
    • >>   drv_uart_int_trans_handle +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    __scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED) + +

    __scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED) + +

    app_display_init (Thumb, 44 bytes, Stack size 8 bytes, p8p_demo.o(i.app_display_init)) +

    [Stack]

    • Max Depth = 640
    • Call Chain = app_display_init ⇒ app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_swire_set_timer +
    • >>   hal_swire_init +
    • >>   hal_pwr_get_vcc_power_ready +
    • >>   app_gpio_init +
    • >>   app_mipi_tx_start +
    • >>   app_mipi_tx_init +
    • >>   app_mipi_rx_init +
    +
    [Called By]
    • >>   app_system_resume +
    • >>   google_p8p_demo +
    + +

    app_gpio_init (Thumb, 22 bytes, Stack size 24 bytes, p8p_demo.o(i.app_gpio_init)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = app_gpio_init ⇒ hal_gpio_config_pad ⇒ hal_gpio_init_output ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   hal_gpio_config_pad +
    +
    [Called By]
    • >>   app_display_init +
    + +

    board_Init (Thumb, 20 bytes, Stack size 8 bytes, board.o(i.board_Init)) +

    [Stack]

    • Max Depth = 140
    • Call Chain = board_Init ⇒ tau_log_init ⇒ hal_uart_init ⇒ drv_uart_init ⇒ drv_uart_set_baud_rate ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   tau_log_init +
    • >>   hal_system_init +
    +
    [Called By]
    • >>   main +
    + +

    ceil (Thumb, 180 bytes, Stack size 24 bytes, ceil.o(i.ceil)) +

    [Stack]

    • Max Depth = 136
    • Call Chain = ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_dadd +
    • >>   __aeabi_drsub +
    • >>   __aeabi_cdrcmple +
    +
    [Called By]
    • >>   hal_lcdc_init_clk +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   svs_wait_start +
    + +

    dcs_packet_fifo_alloc (Thumb, 80 bytes, Stack size 12 bytes, dcs_packet_fifo.o(i.dcs_packet_fifo_alloc)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = dcs_packet_fifo_alloc +
    +
    [Called By]
    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    + +

    dcs_packet_fifo_init (Thumb, 18 bytes, Stack size 0 bytes, dcs_packet_fifo.o(i.dcs_packet_fifo_init)) +

    [Called By]

    • >>   hal_internal_vsync_init_rx +
    + +

    dcs_packet_free_fifo_header (Thumb, 60 bytes, Stack size 0 bytes, dcs_packet_fifo.o(i.dcs_packet_free_fifo_header)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_dcs_async_handler +
    + +

    dcs_packet_get_fifo_header (Thumb, 26 bytes, Stack size 0 bytes, dcs_packet_fifo.o(i.dcs_packet_get_fifo_header)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_dcs_async_handler +
    + +

    delayMs (Thumb, 24 bytes, Stack size 8 bytes, tau_delay.o(i.delayMs)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = delayMs ⇒ delayUs +
    +
    [Calls]
    • >>   delayUs +
    +
    [Called By]
    • >>   app_tx_panel_reset +
    • >>   app_mipi_tx_start +
    • >>   app_init_panel +
    • >>   ap_dcs_set_enter_sleep_mode +
    + +

    delayUs (Thumb, 40 bytes, Stack size 8 bytes, tau_delay.o(i.delayUs)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = delayUs +
    +
    [Called By]
    • >>   hal_internal_sync_input_resolution_change +
    • >>   delayMs +
    • >>   send_panel_init_code +
    • >>   tau_log_push_log +
    + +

    drv_common_system_init (Thumb, 8 bytes, Stack size 8 bytes, drv_common.o(i.drv_common_system_init)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = drv_common_system_init ⇒ drv_se_init ⇒ drv_efuse_read +
    +
    [Calls]
    • >>   drv_se_init +
    +
    [Called By]
    • >>   hal_system_init +
    + +

    drv_crgu_enable_clock (Thumb, 54 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_enable_clock)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_init_clk +
    • >>   hal_dsi_rx_ctrl_init_clk +
    • >>   hal_system_init +
    • >>   hal_timer_init +
    • >>   hal_swire_init +
    • >>   hal_swire_deinit +
    • >>   hal_dsi_tx_ctrl_deinit +
    • >>   hal_dsi_rx_ctrl_deinit +
    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_timer_deinit +
    • >>   drv_uart_enable_clk +
    • >>   drv_efuse_enter_inactive +
    + +

    drv_crgu_get_rxbr_clk (Thumb, 70 bytes, Stack size 8 bytes, drv_crgu.o(i.drv_crgu_get_rxbr_clk)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = drv_crgu_get_rxbr_clk ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_intl_svs_update_rxbr_clk +
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    • >>   svs_wait_start +
    + +

    drv_crgu_reset_modules (Thumb, 10 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_reset_modules)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_deinit +
    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    drv_crgu_set_ahb_clk (Thumb, 34 bytes, Stack size 8 bytes, drv_crgu.o(i.drv_crgu_set_ahb_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_crgu_set_ahb_clk +
    +
    [Called By]
    • >>   hal_system_updata_sysclk +
    + +

    drv_crgu_set_clock_div (Thumb, 12 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_clock_div)) +

    [Called By]

    • >>   hal_swire_init +
    + +

    drv_crgu_set_dpi_clk (Thumb, 54 bytes, Stack size 12 bytes, drv_crgu.o(i.drv_crgu_set_dpi_clk)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_crgu_set_dpi_clk +
    +
    [Called By]
    • >>   hal_dsi_tx_init_dpi_timing +
    + +

    drv_crgu_set_dsc_clk (Thumb, 52 bytes, Stack size 12 bytes, drv_crgu.o(i.drv_crgu_set_dsc_clk)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_crgu_set_dsc_clk +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_clk +
    • >>   VPRE_IRQn_Handler +
    + +

    drv_crgu_set_fb_clk (Thumb, 34 bytes, Stack size 8 bytes, drv_crgu.o(i.drv_crgu_set_fb_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_crgu_set_fb_clk +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_clk +
    + +

    drv_crgu_set_lcdc_clk (Thumb, 36 bytes, Stack size 8 bytes, drv_crgu.o(i.drv_crgu_set_lcdc_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_crgu_set_lcdc_clk +
    +
    [Called By]
    • >>   hal_lcdc_init_clk +
    + +

    drv_crgu_set_reset (Thumb, 20 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_reset)) +

    [Called By]

    • >>   hal_swire_deinit +
    • >>   hal_dsi_rx_ctrl_deinit +
    • >>   vpre_err_reset +
    • >>   hal_timer_deinit +
    + +

    drv_crgu_set_rxbr_clk (Thumb, 34 bytes, Stack size 8 bytes, drv_crgu.o(i.drv_crgu_set_rxbr_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_crgu_set_rxbr_clk +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_clk +
    + +

    drv_crgu_set_vidc_clk (Thumb, 36 bytes, Stack size 8 bytes, drv_crgu.o(i.drv_crgu_set_vidc_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_crgu_set_vidc_clk +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_clk +
    + +

    drv_dma_clear_status (Thumb, 20 bytes, Stack size 0 bytes, drv_dma.o(i.drv_dma_clear_status)) +

    [Called By]

    • >>   DMA_IRQn_Handler +
    + +

    drv_dsc_dec_disable (Thumb, 20 bytes, Stack size 0 bytes, drv_dsc_dec.o(i.drv_dsc_dec_disable)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    drv_dsc_dec_enable (Thumb, 44 bytes, Stack size 8 bytes, drv_dsc_dec.o(i.drv_dsc_dec_enable)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = drv_dsc_dec_enable ⇒ drv_se_set_dsc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_dsc +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    • >>   hal_intl_dcs_rx_receive_pps +
    + +

    drv_dsc_dec_get_nslc (Thumb, 22 bytes, Stack size 0 bytes, drv_dsc_dec.o(i.drv_dsc_dec_get_nslc)) +

    [Called By]

    • >>   VPRE_IRQn_Handler +
    + +

    drv_dsc_dec_set_irqen (Thumb, 24 bytes, Stack size 0 bytes, drv_dsc_dec.o(i.drv_dsc_dec_set_irqen)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init +
    + +

    drv_dsi_rx_calc_ipi_tx_delay (Thumb, 252 bytes, Stack size 56 bytes, drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay)) +

    [Stack]

    • Max Depth = 160
    • Call Chain = drv_dsi_rx_calc_ipi_tx_delay ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fmul +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_fadd +
    • >>   __aeabi_f2d +
    • >>   __aeabi_dadd +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_fsub +
    • >>   __aeabi_cfrcmple +
    • >>   drv_dsi_rx_get_color_pcc +
    • >>   drv_dsi_rx_get_color_bpp +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_set_ipi_cfg +
    + +

    drv_dsi_rx_enable_irq (Thumb, 58 bytes, Stack size 8 bytes, drv_dsi_rx.o(i.drv_dsi_rx_enable_irq)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_dsi_rx_enable_irq ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    drv_dsi_rx_get_compression_en (Thumb, 10 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en)) +

    [Called By]

    • >>   hal_intl_dcs_rx_receive_pps +
    + +

    drv_dsi_rx_get_ddi_crc_en (Thumb, 10 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_ddi_crc_en)) +

    [Called By]

    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    + +

    drv_dsi_rx_get_max_ret_size (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_max_ret_size)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_get_max_ret_size +
    + +

    drv_dsi_rx_power_up (Thumb, 14 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_power_up)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_start +
    + +

    drv_dsi_rx_set_check_crc (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_check_crc)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_ctrl_cfg (Thumb, 32 bytes, Stack size 12 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_ctrl_cfg)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_dsi_rx_set_ctrl_cfg +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_ddi_cfg (Thumb, 10 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_ddi_crc_en (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_crc_en)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_inten (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_inten)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_ipi_cfg (Thumb, 12 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_cfg)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_set_ipi_cfg +
    + +

    drv_dsi_rx_set_ipi_ycbcr_frmt (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_ycbcr_frmt)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_lane_swap (Thumb, 16 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_lane_swap)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_resp_cnt (Thumb, 32 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_resp_cnt)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_tear_resp_en (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_tear_resp_en)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_up_phy (Thumb, 224 bytes, Stack size 32 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = drv_dsi_rx_set_up_phy ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    • >>   drv_phy_test_lock +
    • >>   drv_phy_test_clear +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_shut_down (Thumb, 14 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_shut_down)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_stop +
    + +

    drv_dsi_tx_command_header (Thumb, 18 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_command_header)) +

    [Called By]

    • >>   hal_dsi_tx_send_cmd +
    + +

    drv_dsi_tx_command_mode_cfg (Thumb, 82 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_dsi_tx_command_put_payload (Thumb, 6 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_tx_ctrl_write_array_cmd +
    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    + +

    drv_dsi_tx_config_eotp (Thumb, 26 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_config_eotp)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_dsi_tx_config_int (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_config_int)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_dpi_lpcmd_time (Thumb, 10 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_dpi_lpcmd_time)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_dpi_mode (Thumb, 12 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_dpi_mode)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_dpi_polarity (Thumb, 32 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_dpi_polarity)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_edpi_cmd_size (Thumb, 6 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_edpi_cmd_size)) +

    [Called By]

    • >>   hal_dsi_tx_init_timing +
    + +

    drv_dsi_tx_get_cmd_status (Thumb, 6 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status)) +

    [Called By]

    • >>   hal_dsi_tx_send_cmd +
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_tx_ctrl_write_array_cmd +
    + +

    drv_dsi_tx_mode (Thumb, 6 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_mode)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_dsi_tx_phy_clock_lane_auto_lp (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_phy_clock_lane_req_hs (Thumb, 26 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    • >>   rxbr_irq1_callback +
    + +

    drv_dsi_tx_phy_lane_mode (Thumb, 12 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_lane_mode)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_phy_status_ready (Thumb, 100 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_init +
    + +

    drv_dsi_tx_phy_status_stopstate (Thumb, 62 bytes, Stack size 4 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   __ARM_common_switch8 +
    +
    [Called By]
    • >>   hal_dsi_tx_send_cmd +
    + +

    drv_dsi_tx_phy_test_setup (Thumb, 314 bytes, Stack size 32 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = drv_dsi_tx_phy_test_setup ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    • >>   drv_tx_phy_test_write_code +
    • >>   drv_tx_phy_test_exit +
    • >>   drv_tx_phy_test_enter +
    • >>   drv_phy_test_clear +
    +
    [Called By]
    • >>   hal_dsi_tx_init_phy_cfg +
    + +

    drv_dsi_tx_phy_time_cfg (Thumb, 28 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg)) +

    [Called By]

    • >>   hal_dsi_tx_init_phy_cfg +
    + +

    drv_dsi_tx_powerup (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_powerup)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_start +
    • >>   hal_dsi_tx_ctrl_init +
    + +

    drv_dsi_tx_response_mode (Thumb, 30 bytes, Stack size 12 bytes, drv_dsi_tx.o(i.drv_dsi_tx_response_mode)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_dsi_tx_response_mode +
    +
    [Called By]
    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_set_bta_ack (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_bta_ack)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_set_esc_div (Thumb, 14 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_set_int (Thumb, 58 bytes, Stack size 8 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_int)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_dsi_tx_set_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   hal_dsi_tx_init_cfg +
    • >>   hal_dsi_tx_ctrl_stop +
    + +

    drv_dsi_tx_set_time_out_div (Thumb, 18 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_time_out_div)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_set_video_chunk (Thumb, 14 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_video_chunk)) +

    [Called By]

    • >>   hal_dsi_tx_init_vid_timing +
    + +

    drv_dsi_tx_set_video_timing (Thumb, 30 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_video_timing)) +

    [Called By]

    • >>   hal_dsi_tx_init_vid_timing +
    + +

    drv_dsi_tx_shutdown (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_shutdown)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_stop +
    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_dsi_tx_timeout_cfg (Thumb, 38 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_timeout_cfg)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_video_mode_cfg (Thumb, 226 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_video_mode_cfg)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_efuse_enter_inactive (Thumb, 54 bytes, Stack size 8 bytes, drv_efuse.o(i.drv_efuse_enter_inactive)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_efuse_enter_inactive +
    +
    [Calls]
    • >>   drv_crgu_enable_clock +
    • >>   drv_efuse_int_enable +
    +
    [Called By]
    • >>   drv_se_init +
    + +

    drv_efuse_int_enable (Thumb, 12 bytes, Stack size 0 bytes, drv_efuse.o(i.drv_efuse_int_enable)) +

    [Called By]

    • >>   drv_efuse_enter_inactive +
    + +

    drv_efuse_read (Thumb, 58 bytes, Stack size 16 bytes, drv_efuse.o(i.drv_efuse_read)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_efuse_read +
    +
    [Calls]
    • >>   drv_pwr_efuse_pd +
    • >>   drv_efuse_read_req +
    +
    [Called By]
    • >>   drv_se_init +
    + +

    drv_efuse_read_req (Thumb, 24 bytes, Stack size 0 bytes, drv_efuse.o(i.drv_efuse_read_req)) +

    [Called By]

    • >>   drv_efuse_read +
    + +

    drv_gpio_register_ap_reset_callback (Thumb, 6 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_register_ap_reset_callback)) +

    [Called By]

    • >>   hal_gpio_set_ap_reset_int +
    + +

    drv_gpio_register_callback (Thumb, 14 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_register_callback)) +

    [Called By]

    • >>   hal_gpio_reg_eint_cb +
    + +

    drv_gpio_set_int (Thumb, 62 bytes, Stack size 16 bytes, drv_gpio.o(i.drv_gpio_set_int)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_gpio_set_int +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    +
    [Called By]
    • >>   hal_gpio_ctrl_eint +
    + +

    drv_gpio_set_ioe (Thumb, 26 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_set_ioe)) +

    [Called By]

    • >>   hal_gpio_init_output +
    • >>   hal_gpio_init_input +
    • >>   hal_gpio_init_eint +
    + +

    drv_gpio_set_mode (Thumb, 16 bytes, Stack size 8 bytes, drv_gpio.o(i.drv_gpio_set_mode)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_gpio_set_mode +
    +
    [Called By]
    • >>   hal_gpio_set_mode +
    + +

    drv_lcdc_bcsa_config (Thumb, 30 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_bcsa_config)) +

    [Called By]

    • >>   hal_nonshadow_func_update +
    • >>   hal_lcdc_postproc_config +
    + +

    drv_lcdc_cfg_int_frame (Thumb, 34 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_cfg_int_frame)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_lcdc_cmd_start (Thumb, 46 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_cmd_start)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = drv_lcdc_cmd_start ⇒ drv_se_set_lcdc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_lcdc +
    +
    [Called By]
    • >>   hal_lcdc_start +
    • >>   rxbr_irq1_callback +
    + +

    drv_lcdc_config_acc_command_mode (Thumb, 14 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_acc_command_mode)) +

    [Called By]

    • >>   hal_internal_vsync_set_tear_mode +
    + +

    drv_lcdc_config_int (Thumb, 50 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_int)) +

    [Called By]

    • >>   hal_lcdc_init_cfg +
    + +

    drv_lcdc_config_int_single (Thumb, 34 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_config_int_single)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_lcdc_config_int_single +
    +
    [Called By]
    • >>   hal_internal_vsync_set_tear_mode +
    • >>   hal_vsync_func_update +
    • >>   hal_nonshadow_func_update +
    + +

    drv_lcdc_config_overwrite_rgb (Thumb, 18 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_overwrite_rgb)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_set_overwrite_rgb +
    + +

    drv_lcdc_config_src_parameter (Thumb, 72 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_src_parameter)) +

    [Called By]

    • >>   hal_lcdc_timinggen_config +
    + +

    drv_lcdc_crop_hact (Thumb, 10 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_crop_hact)) +

    [Called By]

    • >>   hal_lcdc_displayproc_config +
    + +

    drv_lcdc_ctrl_flow (Thumb, 50 bytes, Stack size 16 bytes, drv_lcdc.o(i.drv_lcdc_ctrl_flow)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_lcdc_ctrl_flow +
    +
    [Calls]
    • >>   drv_lcdc_function_enable +
    +
    [Called By]
    • >>   hal_lcdc_timinggen_config +
    + +

    drv_lcdc_dith_config (Thumb, 40 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_dith_config)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_lcdc_dith_config +
    +
    [Called By]
    • >>   hal_lcdc_postproc_config +
    + +

    drv_lcdc_edge_dect_config (Thumb, 50 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_edge_dect_config)) +

    [Called By]

    • >>   hal_nonshadow_func_update +
    • >>   hal_lcdc_postproc_config +
    + +

    drv_lcdc_edge_enh_config (Thumb, 86 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_edge_enh_config)) +

    [Called By]

    • >>   hal_nonshadow_func_update +
    • >>   hal_lcdc_postproc_config +
    + +

    drv_lcdc_enable_shadow_reg (Thumb, 32 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_enable_shadow_reg)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_lcdc_endianness_config (Thumb, 24 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_endianness_config)) +

    [Called By]

    • >>   hal_lcdc_displayproc_config +
    + +

    drv_lcdc_fc_config (Thumb, 24 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_fc_config)) +

    [Called By]

    • >>   hal_nonshadow_func_update +
    • >>   hal_lcdc_postproc_config +
    + +

    drv_lcdc_fldc_config (Thumb, 32 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_fldc_config)) +

    [Called By]

    • >>   hal_lcdc_postproc_config +
    + +

    drv_lcdc_function_disable (Thumb, 30 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_function_disable)) +

    [Called By]

    • >>   hal_internal_vsync_set_tx_state +
    • >>   hal_internal_vsync_set_tear_mode +
    • >>   hal_lcdc_postproc_config +
    • >>   vidc_callback +
    + +

    drv_lcdc_function_enable (Thumb, 30 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_function_enable)) +

    [Called By]

    • >>   hal_internal_vsync_set_tear_mode +
    • >>   drv_lcdc_ctrl_flow +
    • >>   hal_lcdc_upscaler_config +
    • >>   hal_lcdc_postproc_config +
    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_lcdc_set_int (Thumb, 54 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_set_int)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = drv_lcdc_set_int ⇒ drv_lcdc_clear_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_lcdc_clear_int +
    +
    [Called By]
    • >>   hal_lcdc_init_cfg +
    • >>   hal_dsi_tx_ctrl_stop +
    + +

    drv_lcdc_set_prefetch (Thumb, 24 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_set_prefetch)) +

    [Called By]

    • >>   hal_lcdc_timinggen_config +
    + +

    drv_lcdc_set_tear_line (Thumb, 24 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_set_tear_line)) +

    [Called By]

    • >>   hal_internal_vsync_set_tear_mode +
    + +

    drv_lcdc_stop_display (Thumb, 12 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_stop_display)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_stop +
    + +

    drv_lcdc_vid_hw_start (Thumb, 56 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_vid_hw_start)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = drv_lcdc_vid_hw_start ⇒ drv_se_set_lcdc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_lcdc +
    +
    [Called By]
    • >>   hal_lcdc_start +
    + +

    drv_lcdc_vintp_mode_config (Thumb, 18 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_vintp_mode_config)) +

    [Called By]

    • >>   hal_lcdc_postproc_config +
    + +

    drv_memc_clear_status (Thumb, 14 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_clear_status)) +

    [Called By]

    • >>   MEMC_IRQn_Handler +
    + +

    drv_memc_enable_irq (Thumb, 58 bytes, Stack size 8 bytes, drv_memc.o(i.drv_memc_enable_irq)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_memc_enable_irq ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_memc +
    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    drv_memc_gen_a_tear_signal (Thumb, 12 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_gen_a_tear_signal)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_gen_a_tear_signal +
    + +

    drv_memc_get_status (Thumb, 20 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_get_status)) +

    [Called By]

    • >>   MEMC_IRQn_Handler +
    + +

    drv_memc_get_tear_mode (Thumb, 10 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_get_tear_mode)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_gen_a_tear_signal +
    + +

    drv_memc_rate_transfer_sel (Thumb, 22 bytes, Stack size 8 bytes, drv_memc.o(i.drv_memc_rate_transfer_sel)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = drv_memc_rate_transfer_sel ⇒ drv_se_set_memc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_memc +
    +
    [Called By]
    • >>   hal_internal_vsync_set_tear_mode +
    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_sel_vsync (Thumb, 16 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_sel_vsync)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_active_height (Thumb, 16 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_active_height)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_circ_mode_enable (Thumb, 24 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_circ_mode_enable)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_data_mode (Thumb, 14 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_data_mode)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_double_buffer (Thumb, 18 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_double_buffer)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_frame_drop_select (Thumb, 24 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_frame_drop_select)) +

    [Called By]

    • >>   hal_internal_vsync_set_tear_mode +
    + +

    drv_memc_set_fs_en_conditions (Thumb, 18 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_fs_en_conditions)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_lcdc_st_conditions (Thumb, 20 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_lcdc_st_conditions)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_ltpo_mode (Thumb, 28 bytes, Stack size 8 bytes, drv_memc.o(i.drv_memc_set_ltpo_mode)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = drv_memc_set_ltpo_mode ⇒ drv_se_set_memc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_memc +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_ltpo_pu_thres (Thumb, 18 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_ltpo_pu_thres)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_tear_mode (Thumb, 16 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_tear_mode)) +

    [Called By]

    • >>   hal_internal_vsync_set_tear_mode +
    • >>   hal_internal_sync_input_resolution_change +
    • >>   hal_dsi_rx_ctrl_init_memc +
    • >>   hal_dsi_tx_ctrl_gen_a_tear_signal +
    + +

    drv_memc_set_tear_waveform (Thumb, 36 bytes, Stack size 8 bytes, drv_memc.o(i.drv_memc_set_tear_waveform)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_memc_set_tear_waveform +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_vidc_sync_cnt (Thumb, 16 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_vidc_sync_cnt)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_phy_test_clear (Thumb, 16 bytes, Stack size 0 bytes, drv_phy_common.o(i.drv_phy_test_clear)) +

    [Called By]

    • >>   drv_dsi_tx_phy_test_setup +
    • >>   drv_dsi_rx_set_up_phy +
    + +

    drv_phy_test_lock (Thumb, 24 bytes, Stack size 0 bytes, drv_phy_common.o(i.drv_phy_test_lock)) +

    [Called By]

    • >>   drv_dsi_rx_set_up_phy +
    + +

    drv_pwr_efuse_pd (Thumb, 36 bytes, Stack size 0 bytes, drv_pwr.o(i.drv_pwr_efuse_pd)) +

    [Called By]

    • >>   drv_efuse_read +
    + +

    drv_pwr_enter_deep_sleep_mode (Thumb, 60 bytes, Stack size 8 bytes, drv_pwr.o(i.drv_pwr_enter_deep_sleep_mode)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_pwr_enter_deep_sleep_mode +
    +
    [Called By]
    • >>   hal_pwr_enter_deep_sleep_mode +
    + +

    drv_pwr_enter_sleep_mode_ex (Thumb, 34 bytes, Stack size 0 bytes, drv_pwr.o(i.drv_pwr_enter_sleep_mode_ex)) +

    [Called By]

    • >>   hal_pwr_enter_normal_sleep_mode +
    + +

    drv_pwr_enter_stop_sleep_mode (Thumb, 132 bytes, Stack size 24 bytes, drv_pwr.o(i.drv_pwr_enter_stop_sleep_mode)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = drv_pwr_enter_stop_sleep_mode +
    +
    [Calls]
    • >>   drv_pwr_write_lock +
    +
    [Called By]
    • >>   hal_pwr_enter_stop_sleep_mode +
    + +

    drv_pwr_exit_sleep_mode (Thumb, 32 bytes, Stack size 4 bytes, drv_pwr.o(i.drv_pwr_exit_sleep_mode)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = drv_pwr_exit_sleep_mode +
    +
    [Calls]
    • >>   drv_pwr_write_lock +
    +
    [Called By]
    • >>   hal_pwr_exit_sleep_mode +
    + +

    drv_pwr_get_power_ready_st (Thumb, 10 bytes, Stack size 0 bytes, drv_pwr.o(i.drv_pwr_get_power_ready_st)) +

    [Called By]

    • >>   hal_pwr_get_vcc_power_ready +
    + +

    drv_pwr_set_breath_screen_power_sel (Thumb, 34 bytes, Stack size 8 bytes, drv_pwr.o(i.drv_pwr_set_breath_screen_power_sel)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_pwr_set_breath_screen_power_sel +
    +
    [Calls]
    • >>   drv_pwr_write_lock +
    +
    [Called By]
    • >>   hal_pwr_set_sleep_mode_power +
    + +

    drv_pwr_set_digit_power_sel (Thumb, 34 bytes, Stack size 8 bytes, drv_pwr.o(i.drv_pwr_set_digit_power_sel)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_pwr_set_digit_power_sel +
    +
    [Calls]
    • >>   drv_pwr_write_lock +
    +
    [Called By]
    • >>   hal_pwr_set_main_power +
    + +

    drv_pwr_set_pll_clk (Thumb, 30 bytes, Stack size 0 bytes, drv_pwr.o(i.drv_pwr_set_pll_clk)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_clk +
    • >>   hal_system_init +
    + +

    drv_pwr_set_wakeup_type (Thumb, 40 bytes, Stack size 4 bytes, drv_pwr.o(i.drv_pwr_set_wakeup_type)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = drv_pwr_set_wakeup_type +
    +
    [Calls]
    • >>   drv_pwr_write_lock +
    +
    [Called By]
    • >>   hal_pwr_enter_deep_sleep_mode +
    + +

    drv_pwr_write_lock (Thumb, 18 bytes, Stack size 0 bytes, drv_pwr.o(i.drv_pwr_write_lock)) +

    [Called By]

    • >>   drv_pwr_set_wakeup_type +
    • >>   drv_pwr_set_digit_power_sel +
    • >>   drv_pwr_set_breath_screen_power_sel +
    • >>   drv_pwr_exit_sleep_mode +
    • >>   drv_pwr_enter_stop_sleep_mode +
    + +

    drv_rxbr_clear_pkt_buffer (Thumb, 12 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer)) +

    [Called By]

    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_intl_dcs_rx_receive_packet +
    • >>   check_pkt_buf_rev +
    • >>   rxbr_irq1_callback +
    + +

    drv_rxbr_clear_status0 (Thumb, 6 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_clear_status0)) +

    [Called By]

    • >>   hal_internal_sync_input_resolution_change +
    • >>   svs_wait_start +
    • >>   svs_direct_mode_setting +
    • >>   VPRE_IRQn_Handler +
    • >>   hal_intl_dcs_rx_receive_packet +
    • >>   check_pkt_buf_rev +
    • >>   rxbr_irq1_callback +
    + +

    drv_rxbr_enable_irq (Thumb, 90 bytes, Stack size 8 bytes, drv_rxbr.o(i.drv_rxbr_enable_irq)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_rxbr_enable_irq ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_sys_cfg_clear_pending +
    • >>   __NVIC_EnableIRQ +
    • >>   __NVIC_DisableIRQ +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    drv_rxbr_frame_drop_cfg (Thumb, 18 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_frame_drop_cfg)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_rxbr +
    • >>   svs_wait_fr_stab +
    + +

    drv_rxbr_hline_rcv1_cfg (Thumb, 14 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg)) +

    [Called By]

    • >>   svs_wait_start +
    • >>   svs_direct_mode_setting +
    + +

    drv_rxbr_hline_rcv_cfg (Thumb, 10 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_hline_rcv_cfg)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    drv_rxbr_register_irq1_callback (Thumb, 6 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_register_irq1_callback)) +

    [Called By]

    • >>   hal_internal_vsync_init_rx +
    + +

    drv_rxbr_set_ack_pkt_header (Thumb, 18 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_ack_pkt_header)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_send_ack_cmd +
    + +

    drv_rxbr_set_color_format (Thumb, 24 bytes, Stack size 8 bytes, drv_rxbr.o(i.drv_rxbr_set_color_format)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = drv_rxbr_set_color_format ⇒ drv_se_set_rxbr ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_rxbr +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    drv_rxbr_set_filter_regs (Thumb, 32 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_filter_regs)) +

    [Called By]

    • >>   hal_intl_dcs_set_auto_hw_filter +
    + +

    drv_rxbr_set_inten (Thumb, 22 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_inten)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_rxbr +
    • >>   svs_wait_start +
    • >>   hal_intl_svs_init_rx +
    • >>   hal_intl_svs_deinit_rx +
    • >>   rxbr_irq1_callback +
    + +

    drv_rxbr_set_ltpo_drop_th (Thumb, 18 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_ltpo_drop_th)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    drv_rxbr_set_usr_cfg (Thumb, 56 bytes, Stack size 20 bytes, drv_rxbr.o(i.drv_rxbr_set_usr_cfg)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = drv_rxbr_set_usr_cfg +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    drv_rxbr_set_usr_col (Thumb, 10 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_usr_col)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    drv_rxbr_set_usr_row (Thumb, 10 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_usr_row)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    drv_se_init (Thumb, 106 bytes, Stack size 16 bytes, drv_se.o(i.drv_se_init)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = drv_se_init ⇒ drv_efuse_read +
    +
    [Calls]
    • >>   drv_efuse_read +
    • >>   drv_efuse_enter_inactive +
    +
    [Called By]
    • >>   drv_common_system_init +
    + +

    drv_se_set_dsc (Thumb, 162 bytes, Stack size 16 bytes, drv_se.o(i.drv_se_set_dsc)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = drv_se_set_dsc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   drv_dsc_dec_enable +
    + +

    drv_se_set_lcdc (Thumb, 88 bytes, Stack size 16 bytes, drv_se.o(i.drv_se_set_lcdc)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = drv_se_set_lcdc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   drv_lcdc_vid_hw_start +
    • >>   drv_lcdc_cmd_start +
    + +

    drv_se_set_memc (Thumb, 96 bytes, Stack size 16 bytes, drv_se.o(i.drv_se_set_memc)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = drv_se_set_memc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   drv_memc_set_ltpo_mode +
    • >>   drv_memc_rate_transfer_sel +
    + +

    drv_se_set_rxbr (Thumb, 158 bytes, Stack size 16 bytes, drv_se.o(i.drv_se_set_rxbr)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = drv_se_set_rxbr ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   drv_rxbr_set_color_format +
    + +

    drv_se_set_vidc (Thumb, 122 bytes, Stack size 16 bytes, drv_se.o(i.drv_se_set_vidc)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   drv_vidc_set_src_parameter +
    + +

    drv_se_start_rx (Thumb, 16 bytes, Stack size 0 bytes, drv_se.o(i.drv_se_start_rx)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init +
    + +

    drv_swire_enable (Thumb, 24 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_enable)) +

    [Called By]

    • >>   hal_swire_init +
    • >>   hal_swire_deinit +
    + +

    drv_swire_get_pulse_count (Thumb, 6 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_get_pulse_count)) +

    [Called By]

    • >>   hal_swire_enable +
    + +

    drv_swire_register_callback (Thumb, 6 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_register_callback)) +

    [Called By]

    • >>   hal_swire_deinit +
    + +

    drv_swire_set_bit_time (Thumb, 18 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_set_bit_time)) +

    [Called By]

    • >>   hal_swire_init +
    + +

    drv_swire_set_int (Thumb, 64 bytes, Stack size 16 bytes, drv_swire.o(i.drv_swire_set_int)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_swire_set_int +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    +
    [Called By]
    • >>   hal_swire_enable +
    • >>   hal_swire_deinit +
    + +

    drv_swire_set_power_down (Thumb, 24 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_set_power_down)) +

    [Called By]

    • >>   hal_swire_init +
    • >>   hal_swire_enable +
    + +

    drv_swire_set_pulse_count (Thumb, 6 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_set_pulse_count)) +

    [Called By]

    • >>   hal_swire_set_pulse +
    + +

    drv_swire_set_trig_mode (Thumb, 24 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_set_trig_mode)) +

    [Called By]

    • >>   hal_swire_set_timer +
    • >>   hal_swire_set_pulse +
    • >>   hal_swire_enable +
    + +

    drv_sys_cfg_clear_all_int (Thumb, 8 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_clear_all_int)) +

    [Called By]

    • >>   hal_system_init +
    + +

    drv_sys_cfg_clear_pending (Thumb, 32 bytes, Stack size 8 bytes, drv_sys_cfg.o(i.drv_sys_cfg_clear_pending)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   drv_dsi_tx_set_int +
    • >>   drv_vidc_enable_irq +
    • >>   drv_rxbr_enable_irq +
    • >>   drv_memc_enable_irq +
    • >>   drv_dsi_rx_enable_irq +
    • >>   hal_gpio_set_ap_reset_int +
    • >>   SWIRE_IRQn_Handler +
    • >>   AP_NRESET_IRQn_Handler +
    • >>   drv_gpio_handle_int +
    • >>   VPRE_IRQn_Handler +
    • >>   LCDC_IRQn_Handler +
    • >>   hal_gpio_init_eint +
    • >>   UART_IRQn_Handler +
    • >>   DMA_IRQn_Handler +
    • >>   VIDC_IRQn_Handler +
    • >>   VPRE1_IRQn_Handler +
    • >>   MEMC_IRQn_Handler +
    • >>   drv_lcdc_clear_int +
    • >>   MIPI_TX_IRQn_Handler +
    • >>   MIPI_RX_IRQn_Handler +
    • >>   drv_timer_clear_status_flags +
    + +

    drv_sys_cfg_sel_ap_rst_trig (Thumb, 30 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_trig)) +

    [Called By]

    • >>   hal_gpio_set_ap_reset_int +
    + +

    drv_sys_cfg_sel_gpio_group (Thumb, 30 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_sel_gpio_group)) +

    [Called By]

    • >>   hal_gpio_init_eint +
    + +

    drv_sys_cfg_sel_int_trig (Thumb, 32 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_sel_int_trig)) +

    [Called By]

    • >>   hal_gpio_init_eint +
    + +

    drv_sys_cfg_sel_swire_timer (Thumb, 18 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_sel_swire_timer)) +

    [Called By]

    • >>   hal_swire_set_timer +
    + +

    drv_sys_cfg_set_int (Thumb, 30 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_set_int)) +

    [Called By]

    • >>   drv_lcdc_set_int +
    • >>   drv_dsi_tx_set_int +
    • >>   drv_vidc_enable_irq +
    • >>   drv_rxbr_enable_irq +
    • >>   drv_memc_enable_irq +
    • >>   drv_dsi_rx_enable_irq +
    • >>   hal_pwr_enter_stop_sleep_mode +
    • >>   hal_gpio_set_ap_reset_int +
    • >>   drv_timer_set_int +
    • >>   drv_swire_set_int +
    • >>   drv_gpio_set_int +
    • >>   drv_uart_enable_int +
    + +

    drv_timer_enable (Thumb, 32 bytes, Stack size 4 bytes, drv_timer.o(i.drv_timer_enable)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = drv_timer_enable +
    +
    [Calls]
    • >>   drv_timer_get_instance +
    +
    [Called By]
    • >>   hal_swire_enable +
    • >>   hal_timer_deinit +
    + +

    drv_timer_get_instance (Thumb, 10 bytes, Stack size 0 bytes, drv_timer.o(i.drv_timer_get_instance)) +

    [Called By]

    • >>   drv_timer_set_prescaler +
    • >>   drv_timer_set_compare_val +
    • >>   drv_timer_enable +
    • >>   drv_timer_clear_status_flags +
    + +

    drv_timer_set_compare_val (Thumb, 50 bytes, Stack size 16 bytes, drv_timer.o(i.drv_timer_set_compare_val)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    • >>   drv_timer_get_instance +
    +
    [Called By]
    • >>   hal_swire_set_timer +
    • >>   drv_timer_handle_interrupt +
    + +

    drv_timer_set_int (Thumb, 68 bytes, Stack size 16 bytes, drv_timer.o(i.drv_timer_set_int)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_timer_set_int +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    +
    [Called By]
    • >>   hal_timer_deinit +
    • >>   drv_timer_handle_interrupt +
    + +

    drv_timer_set_prescaler (Thumb, 36 bytes, Stack size 12 bytes, drv_timer.o(i.drv_timer_set_prescaler)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_timer_set_prescaler +
    +
    [Calls]
    • >>   drv_timer_get_instance +
    +
    [Called By]
    • >>   hal_timer_init +
    + +

    drv_timer_set_repeat (Thumb, 12 bytes, Stack size 0 bytes, drv_timer.o(i.drv_timer_set_repeat)) +

    [Called By]

    • >>   hal_timer_set_repeat +
    • >>   hal_timer_deinit +
    + +

    drv_tx_phy_test_enter (Thumb, 28 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_tx_phy_test_enter)) +

    [Called By]

    • >>   drv_dsi_tx_phy_test_setup +
    + +

    drv_tx_phy_test_exit (Thumb, 28 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_tx_phy_test_exit)) +

    [Called By]

    • >>   drv_dsi_tx_phy_test_setup +
    + +

    drv_tx_phy_test_write_code (Thumb, 34 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_tx_phy_test_write_code)) +

    [Called By]

    • >>   drv_dsi_tx_phy_test_setup +
    + +

    drv_uart_abort_recv (Thumb, 46 bytes, Stack size 12 bytes, drv_uart.o(i.drv_uart_abort_recv)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = drv_uart_abort_recv ⇒ drv_uart_reset_rx_fifo ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   drv_uart_reset_rx_fifo +
    • >>   drv_uart_get_instance +
    • >>   drv_uart_config_int +
    +
    [Called By]
    • >>   UART_IRQn_Handler +
    + +

    drv_uart_abort_send (Thumb, 46 bytes, Stack size 12 bytes, drv_uart.o(i.drv_uart_abort_send)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = drv_uart_abort_send ⇒ drv_uart_reset_tx_fifo ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   drv_uart_reset_tx_fifo +
    • >>   drv_uart_get_instance +
    • >>   drv_uart_config_int +
    +
    [Called By]
    • >>   UART_IRQn_Handler +
    + +

    drv_uart_config_int (Thumb, 20 bytes, Stack size 0 bytes, drv_uart.o(i.drv_uart_config_int)) +

    [Called By]

    • >>   drv_uart_abort_send +
    • >>   drv_uart_abort_recv +
    • >>   UART_IRQn_Handler +
    + +

    drv_uart_enable_int (Thumb, 84 bytes, Stack size 24 bytes, drv_uart.o(i.drv_uart_enable_int)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = drv_uart_enable_int ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_uart_get_instance +
    +
    [Called By]
    • >>   drv_uart_init +
    + +

    drv_uart_get_instance (Thumb, 36 bytes, Stack size 12 bytes, drv_uart.o(i.drv_uart_get_instance)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_uart_get_instance +
    +
    [Called By]
    • >>   drv_uart_trans_create_handle +
    • >>   drv_uart_init +
    • >>   drv_uart_reset_tx_fifo +
    • >>   drv_uart_reset_rx_fifo +
    • >>   drv_uart_enable_int +
    • >>   drv_uart_abort_send +
    • >>   drv_uart_abort_recv +
    + +

    drv_uart_init (Thumb, 206 bytes, Stack size 16 bytes, drv_uart.o(i.drv_uart_init)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = drv_uart_init ⇒ drv_uart_set_baud_rate ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_uart_set_baud_rate +
    • >>   drv_uart_get_instance +
    • >>   drv_uart_enable_int +
    • >>   drv_uart_enable_clk +
    +
    [Called By]
    • >>   hal_uart_init +
    + +

    drv_uart_reset_rx_fifo (Thumb, 28 bytes, Stack size 8 bytes, drv_uart.o(i.drv_uart_reset_rx_fifo)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = drv_uart_reset_rx_fifo ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   drv_uart_get_instance +
    +
    [Called By]
    • >>   drv_uart_abort_recv +
    + +

    drv_uart_reset_tx_fifo (Thumb, 28 bytes, Stack size 8 bytes, drv_uart.o(i.drv_uart_reset_tx_fifo)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = drv_uart_reset_tx_fifo ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   drv_uart_get_instance +
    +
    [Called By]
    • >>   drv_uart_abort_send +
    + +

    drv_uart_send_blocking (Thumb, 26 bytes, Stack size 0 bytes, drv_uart.o(i.drv_uart_send_blocking)) +

    [Called By]

    • >>   hal_uart_send_blocking +
    + +

    drv_uart_set_baud_rate (Thumb, 84 bytes, Stack size 24 bytes, drv_uart.o(i.drv_uart_set_baud_rate)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = drv_uart_set_baud_rate ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   drv_uart_init +
    + +

    drv_uart_trans_create_handle (Thumb, 72 bytes, Stack size 24 bytes, drv_uart.o(i.drv_uart_trans_create_handle)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = drv_uart_trans_create_handle ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   __aeabi_memclr4 +
    • >>   drv_uart_get_instance +
    +
    [Called By]
    • >>   hal_uart_init +
    + +

    drv_vidc_clear_irq (Thumb, 10 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_clear_irq)) +

    [Called By]

    • >>   vidc_callback +
    + +

    drv_vidc_enable (Thumb, 26 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_enable)) +

    [Called By]

    • >>   hal_internal_sync_input_resolution_change +
    • >>   hal_dsi_rx_ctrl_stop +
    • >>   hal_dsi_rx_ctrl_start +
    • >>   rxbr_irq1_callback +
    + +

    drv_vidc_enable_irq (Thumb, 58 bytes, Stack size 8 bytes, drv_vidc.o(i.drv_vidc_enable_irq)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_vidc_enable_irq ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    drv_vidc_get_int_source (Thumb, 40 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_get_int_source)) +

    [Called By]

    • >>   vidc_callback +
    + +

    drv_vidc_get_irq_status (Thumb, 20 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_get_irq_status)) +

    [Called By]

    • >>   vidc_callback +
    + +

    drv_vidc_init_module_enable (Thumb, 36 bytes, Stack size 12 bytes, drv_vidc.o(i.drv_vidc_init_module_enable)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_vidc_init_module_enable +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_register_callback (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_register_callback)) +

    [Called By]

    • >>   hal_internal_vsync_init_rx +
    + +

    drv_vidc_reset (Thumb, 8 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_reset)) +

    [Called By]

    • >>   hal_internal_sync_input_resolution_change +
    • >>   vpre_err_reset +
    + +

    drv_vidc_set_circ_mode_enable (Thumb, 24 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_circ_mode_enable)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_dither_config (Thumb, 50 bytes, Stack size 8 bytes, drv_vidc.o(i.drv_vidc_set_dither_config)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_vidc_set_dither_config +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_dst_parameter (Thumb, 86 bytes, Stack size 16 bytes, drv_vidc.o(i.drv_vidc_set_dst_parameter)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_vidc_set_dst_parameter +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_honly_hcoef0 (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_honly_hcoef0)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_honly_hinitb (Thumb, 38 bytes, Stack size 12 bytes, drv_vidc.o(i.drv_vidc_set_honly_hinitb)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_vidc_set_honly_hinitb +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_honly_hinitr (Thumb, 42 bytes, Stack size 16 bytes, drv_vidc.o(i.drv_vidc_set_honly_hinitr)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_vidc_set_honly_hinitr +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_irqen (Thumb, 22 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_irqen)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   vidc_callback +
    + +

    drv_vidc_set_mirror (Thumb, 16 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_mirror)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_pentile_swap (Thumb, 20 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_pentile_swap)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_pu_ctrl (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_pu_ctrl)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_rotation (Thumb, 18 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_rotation)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_scld_hcoef0 (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_hcoef0)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_scld_hcoef1 (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_hcoef1)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_scld_step (Thumb, 14 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_step)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_scld_vcoef0 (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_vcoef0)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_scld_vcoef1 (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_vcoef1)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_src_parameter (Thumb, 28 bytes, Stack size 16 bytes, drv_vidc.o(i.drv_vidc_set_src_parameter)) +

    [Stack]

    • Max Depth = 368
    • Call Chain = drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_vidc +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_vintp_config (Thumb, 52 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_vintp_config)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    fputc (Thumb, 42 bytes, Stack size 24 bytes, tau_log.o(i.fputc)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = fputc ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_uart_send_blocking +
    • >>   tau_log_push_log +
    +
    [Address Reference Count : 1]
    • printfa.o(i.__0printf) +
    +

    google_p8p_demo (Thumb, 48 bytes, Stack size 0 bytes, p8p_demo.o(i.google_p8p_demo)) +

    [Stack]

    • Max Depth = 656
    • Call Chain = google_p8p_demo ⇒ app_system_process ⇒ app_system_resume ⇒ app_display_init ⇒ app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_pwr_set_main_power +
    • >>   hal_dsi_rx_ctrl_dcs_async_handler +
    • >>   app_display_init +
    • >>   app_system_process +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   main +
    + +

    hal_dsi_rx_ctrl_create_handle (Thumb, 60 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_rx_ctrl_create_handle +
    +
    [Calls]
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   app_mipi_rx_init +
    + +

    hal_dsi_rx_ctrl_dcs_async_handler (Thumb, 60 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_rx_ctrl_dcs_async_handler +
    +
    [Calls]
    • >>   dcs_packet_get_fifo_header +
    • >>   dcs_packet_free_fifo_header +
    +
    [Called By]
    • >>   google_p8p_demo +
    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    + +

    hal_dsi_rx_ctrl_deinit (Thumb, 132 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_dsi_rx_ctrl_deinit ⇒ hal_internal_vsync_set_rx_state ⇒ hal_intl_svs_deinit_rx +
    +
    [Calls]
    • >>   hal_internal_vsync_set_rx_state +
    • >>   hal_internal_vsync_get_tx_state +
    • >>   hal_internal_vsync_get_rx_state +
    • >>   drv_vidc_enable_irq +
    • >>   drv_rxbr_enable_irq +
    • >>   drv_memc_enable_irq +
    • >>   drv_dsi_rx_enable_irq +
    • >>   drv_dsc_dec_disable +
    • >>   drv_crgu_set_reset +
    • >>   drv_crgu_reset_modules +
    • >>   drv_crgu_enable_clock +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_dsi_rx_ctrl_get_max_ret_size (Thumb, 28 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_rx_ctrl_get_max_ret_size +
    +
    [Calls]
    • >>   drv_dsi_rx_get_max_ret_size +
    +
    [Called By]
    • >>   ap_dcs_read +
    + +

    hal_dsi_rx_ctrl_init (Thumb, 158 bytes, Stack size 16 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init)) +

    [Stack]

    • Max Depth = 552
    • Call Chain = hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_internal_vsync_set_rx_state +
    • >>   hal_internal_vsync_init_rx +
    • >>   drv_se_start_rx +
    • >>   drv_dsc_dec_set_irqen +
    • >>   drv_dsc_dec_enable +
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    • >>   hal_dsi_rx_ctrl_init_memc +
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    • >>   hal_dsi_rx_ctrl_init_clk +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_internal_sync_input_resolution_change +
    • >>   app_mipi_rx_init +
    + +

    hal_dsi_rx_ctrl_pre_init_pps (Thumb, 50 bytes, Stack size 12 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = hal_dsi_rx_ctrl_pre_init_pps +
    +
    [Called By]
    • >>   app_mipi_tx_start +
    • >>   app_mipi_rx_init +
    • >>   ap_dcs_set_display_on +
    + +

    hal_dsi_rx_ctrl_send_ack_cmd (Thumb, 210 bytes, Stack size 48 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd)) +

    [Stack]

    • Max Depth = 384
    • Call Chain = hal_dsi_rx_ctrl_send_ack_cmd ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_rxbr_set_ack_pkt_header +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   ap_dcs_read +
    + +

    hal_dsi_rx_ctrl_start (Thumb, 42 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_dsi_rx_ctrl_start ⇒ hal_internal_vsync_set_rx_state ⇒ hal_intl_svs_deinit_rx +
    +
    [Calls]
    • >>   hal_internal_vsync_set_rx_state +
    • >>   drv_vidc_enable +
    • >>   drv_dsi_rx_power_up +
    +
    [Called By]
    • >>   hal_internal_sync_input_resolution_change +
    • >>   app_mipi_rx_init +
    + +

    hal_dsi_rx_ctrl_stop (Thumb, 42 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_dsi_rx_ctrl_stop ⇒ hal_internal_vsync_set_rx_state ⇒ hal_intl_svs_deinit_rx +
    +
    [Calls]
    • >>   hal_internal_vsync_set_rx_state +
    • >>   drv_vidc_enable +
    • >>   drv_dsi_rx_shut_down +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_dsi_rx_ctrl_toggle_resolution (Thumb, 28 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution)) +

    [Stack]

    • Max Depth = 624
    • Call Chain = hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_internal_sync_input_resolution_change +
    +
    [Called By]
    • >>   pps_update_handle +
    • >>   app_mipi_tx_start +
    • >>   ap_dcs_set_display_on +
    + +

    hal_dsi_tx_ctrl_create_handle (Thumb, 48 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_tx_ctrl_create_handle +
    +
    [Calls]
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   app_mipi_tx_init +
    + +

    hal_dsi_tx_ctrl_deinit (Thumb, 102 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = hal_dsi_tx_ctrl_deinit ⇒ hal_internal_vsync_set_tx_state ⇒ hal_internal_vsync_deinit +
    +
    [Calls]
    • >>   hal_internal_vsync_set_tx_state +
    • >>   hal_internal_sync_register_lcdc_cb +
    • >>   drv_crgu_reset_modules +
    • >>   drv_crgu_enable_clock +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_dsi_tx_ctrl_gen_a_tear_signal (Thumb, 34 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_tx_ctrl_gen_a_tear_signal +
    +
    [Calls]
    • >>   drv_memc_get_tear_mode +
    • >>   drv_memc_gen_a_tear_signal +
    • >>   drv_memc_set_tear_mode +
    +
    [Called By]
    • >>   hal_internal_sync_input_resolution_change +
    + +

    hal_dsi_tx_ctrl_init (Thumb, 110 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init)) +

    [Stack]

    • Max Depth = 424
    • Call Chain = hal_dsi_tx_ctrl_init ⇒ hal_dsi_tx_init_timing ⇒ hal_dsi_tx_cmd_mode_cal_timing ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_internal_vsync_set_tx_state +
    • >>   hal_internal_vsync_init_tx +
    • >>   hal_internal_sync_register_lcdc_cb +
    • >>   drv_dsi_tx_powerup +
    • >>   drv_dsi_tx_phy_status_ready +
    • >>   hal_lcdc_init_clk +
    • >>   hal_lcdc_init_cfg +
    • >>   hal_dsi_tx_init_timing +
    • >>   hal_dsi_tx_init_cfg +
    • >>   hal_dsi_tx_ctrl_init_clk +
    +
    [Called By]
    • >>   hal_tx_frame_rate_adjust +
    • >>   app_mipi_tx_init +
    + +

    hal_dsi_tx_ctrl_set_overwrite_rgb (Thumb, 8 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_tx_ctrl_set_overwrite_rgb +
    +
    [Calls]
    • >>   drv_lcdc_config_overwrite_rgb +
    +
    [Called By]
    • >>   app_mipi_tx_init +
    + +

    hal_dsi_tx_ctrl_set_tear_mode (Thumb, 10 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode)) +

    [Stack]

    • Max Depth = 392
    • Call Chain = hal_dsi_tx_ctrl_set_tear_mode ⇒ hal_internal_vsync_set_tear_mode ⇒ drv_memc_rate_transfer_sel ⇒ drv_se_set_memc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_internal_vsync_set_tear_mode +
    +
    [Called By]
    • >>   pps_update_handle +
    • >>   app_mipi_tx_start +
    • >>   ap_dcs_set_frame_change +
    • >>   ap_dcs_set_enter_sleep_mode +
    + +

    hal_dsi_tx_ctrl_start (Thumb, 116 bytes, Stack size 24 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start)) +

    [Stack]

    • Max Depth = 392
    • Call Chain = hal_dsi_tx_ctrl_start ⇒ hal_lcdc_start ⇒ drv_lcdc_vid_hw_start ⇒ drv_se_set_lcdc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_internal_vsync_set_tx_state +
    • >>   drv_lcdc_function_enable +
    • >>   drv_lcdc_enable_shadow_reg +
    • >>   drv_lcdc_cfg_int_frame +
    • >>   drv_dsi_tx_shutdown +
    • >>   drv_dsi_tx_powerup +
    • >>   drv_dsi_tx_mode +
    • >>   drv_dsi_tx_config_eotp +
    • >>   drv_dsi_tx_command_mode_cfg +
    • >>   hal_lcdc_start +
    • >>   hal_intl_fb_get_memc_flow_mode +
    +
    [Called By]
    • >>   app_mipi_tx_start +
    + +

    hal_dsi_tx_ctrl_stop (Thumb, 52 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = hal_dsi_tx_ctrl_stop ⇒ hal_internal_vsync_set_tx_state ⇒ hal_internal_vsync_deinit +
    +
    [Calls]
    • >>   hal_internal_vsync_set_tx_state +
    • >>   drv_lcdc_stop_display +
    • >>   drv_lcdc_set_int +
    • >>   drv_dsi_tx_shutdown +
    • >>   drv_dsi_tx_set_int +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_dsi_tx_ctrl_write_array_cmd (Thumb, 238 bytes, Stack size 48 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = hal_dsi_tx_ctrl_write_array_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   drv_dsi_tx_get_cmd_status +
    • >>   drv_dsi_tx_command_put_payload +
    • >>   hal_dsi_tx_send_cmd +
    • >>   hal_internal_vsync_get_tx_state +
    +
    [Called By]
    • >>   send_panel_init_code +
    + +

    hal_dsi_tx_ctrl_write_cmd (Thumb, 202 bytes, Stack size 48 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = hal_dsi_tx_ctrl_write_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   drv_dsi_tx_get_cmd_status +
    • >>   drv_dsi_tx_command_put_payload +
    • >>   hal_dsi_tx_send_cmd +
    • >>   hal_internal_vsync_get_tx_state +
    +
    [Called By]
    • >>   app_mipi_tx_start +
    • >>   ap_set_FPS_53 +
    • >>   ap_dcs_set_enter_sleep_mode +
    • >>   ap_dcs_set_display_on +
    • >>   ap_dcs_set_backlight +
    + +

    hal_gpio_config_pad (Thumb, 58 bytes, Stack size 16 bytes, hal_gpio.o(i.hal_gpio_config_pad)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = hal_gpio_config_pad ⇒ hal_gpio_init_output ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   hal_gpio_init_output +
    • >>   hal_gpio_set_mode +
    • >>   hal_gpio_init_input +
    +
    [Called By]
    • >>   app_gpio_init +
    + +

    hal_gpio_ctrl_eint (Thumb, 18 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_ctrl_eint)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_gpio_ctrl_eint ⇒ drv_gpio_set_int +
    +
    [Calls]
    • >>   drv_gpio_set_int +
    +
    [Called By]
    • >>   hal_pwr_set_stop_sleep_wakeup_pin +
    + +

    hal_gpio_init_eint (Thumb, 58 bytes, Stack size 24 bytes, hal_gpio.o(i.hal_gpio_init_eint)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = hal_gpio_init_eint ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   drv_sys_cfg_sel_int_trig +
    • >>   drv_sys_cfg_sel_gpio_group +
    • >>   drv_sys_cfg_clear_pending +
    • >>   drv_gpio_set_ioe +
    • >>   hal_gpio_set_mode +
    +
    [Called By]
    • >>   hal_pwr_set_stop_sleep_wakeup_pin +
    + +

    hal_gpio_init_input (Thumb, 22 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_init_input)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_gpio_init_input ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   drv_gpio_set_ioe +
    • >>   hal_gpio_set_mode +
    +
    [Called By]
    • >>   hal_gpio_config_pad +
    + +

    hal_gpio_init_output (Thumb, 28 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_init_output)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_gpio_init_output ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   drv_gpio_set_ioe +
    • >>   hal_gpio_set_mode +
    • >>   drv_gpio_set_output_data +
    +
    [Called By]
    • >>   hal_gpio_config_pad +
    • >>   app_system_suspend +
    • >>   app_init_panel +
    + +

    hal_gpio_reg_eint_cb (Thumb, 22 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_reg_eint_cb)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_gpio_reg_eint_cb +
    +
    [Calls]
    • >>   drv_gpio_register_callback +
    +
    [Called By]
    • >>   hal_pwr_set_stop_sleep_wakeup_pin +
    + +

    hal_gpio_set_ap_reset_int (Thumb, 76 bytes, Stack size 16 bytes, hal_gpio.o(i.hal_gpio_set_ap_reset_int)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_gpio_set_ap_reset_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_sys_cfg_sel_ap_rst_trig +
    • >>   drv_sys_cfg_clear_pending +
    • >>   drv_gpio_register_ap_reset_callback +
    +
    [Called By]
    • >>   hal_pwr_set_stop_sleep_wakeup_pin +
    • >>   app_system_suspend +
    • >>   ap_rstn_pull_high_cb +
    • >>   ap_rstn_pull_down_cb +
    • >>   ap_dcs_set_enter_sleep_mode +
    + +

    hal_gpio_set_mode (Thumb, 94 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_set_mode)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   drv_gpio_set_mode +
    +
    [Called By]
    • >>   hal_system_init +
    • >>   hal_swire_init +
    • >>   hal_gpio_init_output +
    • >>   hal_gpio_config_pad +
    • >>   hal_gpio_init_input +
    • >>   hal_gpio_init_eint +
    + +

    hal_gpio_set_output_data (Thumb, 8 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_set_output_data)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_gpio_set_output_data +
    +
    [Calls]
    • >>   drv_gpio_set_output_data +
    +
    [Called By]
    • >>   app_tx_panel_reset +
    • >>   ap_dcs_set_enter_sleep_mode +
    + +

    hal_internal_sync_get_hight_performan_mode (Thumb, 10 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode)) +

    [Called By]

    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   hal_intl_fb_check_bandwidth +
    + +

    hal_internal_sync_input_resolution_change (Thumb, 330 bytes, Stack size 64 bytes, hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change)) +

    [Stack]

    • Max Depth = 616
    • Call Chain = hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_internal_vsync_get_sync_line +
    • >>   drv_vidc_enable +
    • >>   drv_memc_set_tear_mode +
    • >>   hal_dsi_tx_ctrl_gen_a_tear_signal +
    • >>   hal_dsi_rx_ctrl_start +
    • >>   hal_dsi_rx_ctrl_init +
    • >>   delayUs +
    • >>   tau_log_printf +
    • >>   hal_intl_fb_cal_fb_info +
    • >>   drv_vidc_reset +
    • >>   drv_rxbr_clear_status0 +
    • >>   hal_vsync_reset_lcdc_scaler +
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_toggle_resolution +
    + +

    hal_internal_sync_register_lcdc_cb (Thumb, 8 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.hal_internal_sync_register_lcdc_cb)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_init +
    • >>   hal_dsi_tx_ctrl_deinit +
    + +

    hal_internal_vsync_deinit (Thumb, 22 bytes, Stack size 8 bytes, hal_internal_vsync.o(i.hal_internal_vsync_deinit)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_internal_vsync_deinit +
    +
    [Calls]
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   hal_internal_vsync_set_tx_state +
    • >>   hal_internal_vsync_set_rx_state +
    + +

    hal_internal_vsync_get_rx_state (Thumb, 6 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.hal_internal_vsync_get_rx_state)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    hal_internal_vsync_get_sync_line (Thumb, 16 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line)) +

    [Called By]

    • >>   hal_internal_vsync_set_tear_mode +
    • >>   hal_lcdc_timinggen_config +
    • >>   hal_internal_sync_input_resolution_change +
    + +

    hal_internal_vsync_get_tx_state (Thumb, 6 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state)) +

    [Called By]

    • >>   hal_tx_frame_rate_adjust +
    • >>   hal_dsi_tx_send_cmd +
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_tx_ctrl_write_array_cmd +
    • >>   hal_dsi_rx_ctrl_deinit +
    • >>   svs_wait_start +
    + +

    hal_internal_vsync_init_rx (Thumb, 190 bytes, Stack size 56 bytes, hal_internal_vsync.o(i.hal_internal_vsync_init_rx)) +

    [Stack]

    • Max Depth = 216
    • Call Chain = hal_internal_vsync_init_rx ⇒ hal_intl_svs_init_rx ⇒ hal_intl_svs_update_rxbr_clk ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   hal_intl_svs_init_rx +
    • >>   hal_intl_fb_cal_fb_info +
    • >>   hal_intl_dcs_init_sw_fltr +
    • >>   drv_vidc_register_callback +
    • >>   drv_rxbr_register_irq1_callback +
    • >>   dcs_packet_fifo_init +
    • >>   check_mipi_rx_tx_video_info +
    • >>   hal_intl_fb_get_user_flow +
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    + +

    hal_internal_vsync_init_tx (Thumb, 194 bytes, Stack size 80 bytes, hal_internal_vsync.o(i.hal_internal_vsync_init_tx)) +

    [Stack]

    • Max Depth = 220
    • Call Chain = hal_internal_vsync_init_tx ⇒ hal_intl_fb_cal_fb_info ⇒ hal_intl_fb_edge_resize ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   hal_intl_fb_cal_fb_info +
    • >>   check_mipi_rx_tx_video_info +
    • >>   __aeabi_memclr4 +
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_init +
    + +

    hal_internal_vsync_set_rx_state (Thumb, 28 bytes, Stack size 8 bytes, hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_internal_vsync_set_rx_state ⇒ hal_intl_svs_deinit_rx +
    +
    [Calls]
    • >>   hal_intl_svs_deinit_rx +
    • >>   hal_internal_vsync_deinit +
    • >>   hal_intl_fb_get_user_flow +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_stop +
    • >>   hal_dsi_rx_ctrl_start +
    • >>   hal_dsi_rx_ctrl_init +
    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    hal_internal_vsync_set_tear_mode (Thumb, 262 bytes, Stack size 24 bytes, hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode)) +

    [Stack]

    • Max Depth = 384
    • Call Chain = hal_internal_vsync_set_tear_mode ⇒ drv_memc_rate_transfer_sel ⇒ drv_se_set_memc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_internal_vsync_get_sync_line +
    • >>   drv_lcdc_function_enable +
    • >>   drv_lcdc_function_disable +
    • >>   drv_lcdc_config_int_single +
    • >>   drv_memc_set_tear_mode +
    • >>   drv_memc_rate_transfer_sel +
    • >>   drv_memc_set_frame_drop_select +
    • >>   drv_lcdc_set_tear_line +
    • >>   drv_lcdc_config_acc_command_mode +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_set_tear_mode +
    + +

    hal_internal_vsync_set_tx_state (Thumb, 92 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_internal_vsync_set_tx_state ⇒ hal_internal_vsync_deinit +
    +
    [Calls]
    • >>   drv_lcdc_function_disable +
    • >>   hal_intl_svs_deinit_tx +
    • >>   hal_internal_vsync_deinit +
    • >>   hal_intl_fb_get_user_flow +
    +
    [Called By]
    • >>   hal_tx_frame_rate_adjust +
    • >>   hal_dsi_tx_ctrl_stop +
    • >>   hal_dsi_tx_ctrl_start +
    • >>   hal_dsi_tx_ctrl_init +
    • >>   hal_dsi_tx_ctrl_deinit +
    + +

    hal_intl_dcs_init_sw_fltr (Thumb, 90 bytes, Stack size 28 bytes, hal_internal_dcs.o(i.hal_intl_dcs_init_sw_fltr)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = hal_intl_dcs_init_sw_fltr +
    +
    [Called By]
    • >>   hal_internal_vsync_init_rx +
    + +

    hal_intl_dcs_set_auto_hw_filter (Thumb, 130 bytes, Stack size 48 bytes, hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = hal_intl_dcs_set_auto_hw_filter +
    +
    [Calls]
    • >>   drv_rxbr_set_filter_regs +
    • >>   __aeabi_memset +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    hal_intl_fb_cal_fb_info (Thumb, 738 bytes, Stack size 80 bytes, hal_internal_fb.o(i.hal_intl_fb_cal_fb_info)) +

    [Stack]

    • Max Depth = 140
    • Call Chain = hal_intl_fb_cal_fb_info ⇒ hal_intl_fb_edge_resize ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   hal_intl_fb_flow_control_adapter +
    • >>   hal_intl_fb_edge_resize +
    • >>   hal_intl_fb_check_bandwidth +
    • >>   ha_intl_fb_check_pu_size +
    • >>   __aeabi_memclr4 +
    • >>   __aeabi_memcpy4 +
    • >>   __aeabi_memcpy +
    +
    [Called By]
    • >>   hal_internal_vsync_init_tx +
    • >>   hal_internal_vsync_init_rx +
    • >>   hal_internal_sync_input_resolution_change +
    + +

    hal_intl_fb_get_memc_flow_mode (Thumb, 6 bytes, Stack size 0 bytes, hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode)) +

    [Called By]

    • >>   hal_lcdc_timinggen_config +
    • >>   hal_lcdc_start +
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    • >>   hal_dsi_rx_ctrl_init_memc +
    • >>   hal_dsi_tx_ctrl_start +
    + +

    hal_intl_fb_get_rx_fb_info (Thumb, 12 bytes, Stack size 8 bytes, hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_intl_fb_get_rx_fb_info +
    +
    [Calls]
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    • >>   hal_dsi_rx_ctrl_init_memc +
    • >>   svs_direct_mode_setting +
    + +

    hal_intl_fb_get_tx_fb_info (Thumb, 12 bytes, Stack size 8 bytes, hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_intl_fb_get_tx_fb_info +
    +
    [Calls]
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_lcdc_postproc_config +
    • >>   hal_lcdc_init_cfg +
    + +

    hal_intl_fb_get_user_flow (Thumb, 6 bytes, Stack size 0 bytes, hal_internal_fb.o(i.hal_intl_fb_get_user_flow)) +

    [Called By]

    • >>   hal_internal_vsync_set_tx_state +
    • >>   hal_lcdc_start +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_internal_vsync_set_rx_state +
    • >>   hal_internal_vsync_init_rx +
    • >>   hal_intl_svs_init_rx +
    • >>   rxbr_irq1_callback +
    + +

    hal_intl_svs_deinit_rx (Thumb, 32 bytes, Stack size 8 bytes, hal_internal_svs.o(i.hal_intl_svs_deinit_rx)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_intl_svs_deinit_rx +
    +
    [Calls]
    • >>   drv_rxbr_set_inten +
    +
    [Called By]
    • >>   hal_internal_vsync_set_rx_state +
    + +

    hal_intl_svs_deinit_tx (Thumb, 10 bytes, Stack size 0 bytes, hal_internal_svs.o(i.hal_intl_svs_deinit_tx)) +

    [Called By]

    • >>   hal_internal_vsync_set_tx_state +
    + +

    hal_intl_svs_handle (Thumb, 24 bytes, Stack size 8 bytes, hal_internal_svs.o(i.hal_intl_svs_handle)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_intl_svs_handle +
    +
    [Called By]
    • >>   rxbr_irq1_callback +
    + +

    hal_intl_svs_init_rx (Thumb, 120 bytes, Stack size 16 bytes, hal_internal_svs.o(i.hal_intl_svs_init_rx)) +

    [Stack]

    • Max Depth = 160
    • Call Chain = hal_intl_svs_init_rx ⇒ hal_intl_svs_update_rxbr_clk ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   hal_intl_svs_update_rxbr_clk +
    • >>   drv_rxbr_set_inten +
    • >>   hal_intl_fb_get_user_flow +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   hal_internal_vsync_init_rx +
    + +

    hal_intl_svs_init_tx (Thumb, 16 bytes, Stack size 8 bytes, hal_internal_svs.o(i.hal_intl_svs_init_tx)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_intl_svs_init_tx +
    +
    [Called By]
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    + +

    hal_intl_svs_set_rx_vtt (Thumb, 6 bytes, Stack size 0 bytes, hal_internal_svs.o(i.hal_intl_svs_set_rx_vtt)) +

    [Called By]

    • >>   rxbr_irq1_callback +
    + +

    hal_intl_svs_update_rxbr_clk (Thumb, 52 bytes, Stack size 16 bytes, hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk)) +

    [Stack]

    • Max Depth = 144
    • Call Chain = hal_intl_svs_update_rxbr_clk ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   drv_crgu_get_rxbr_clk +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_dmul +
    +
    [Called By]
    • >>   hal_intl_svs_init_rx +
    + +

    hal_lcdc_displayproc_config (Thumb, 94 bytes, Stack size 24 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_lcdc_displayproc_config +
    +
    [Calls]
    • >>   drv_lcdc_endianness_config +
    • >>   drv_lcdc_crop_hact +
    +
    [Called By]
    • >>   hal_lcdc_init_cfg +
    + +

    hal_lcdc_postproc_config (Thumb, 276 bytes, Stack size 88 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config)) +

    [Stack]

    • Max Depth = 232
    • Call Chain = hal_lcdc_postproc_config ⇒ hal_lcdc_upscaler_config ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   hal_intl_fb_get_tx_fb_info +
    • >>   drv_lcdc_vintp_mode_config +
    • >>   drv_lcdc_function_enable +
    • >>   drv_lcdc_function_disable +
    • >>   drv_lcdc_fldc_config +
    • >>   drv_lcdc_fc_config +
    • >>   drv_lcdc_edge_enh_config +
    • >>   drv_lcdc_edge_dect_config +
    • >>   drv_lcdc_dith_config +
    • >>   drv_lcdc_bcsa_config +
    • >>   hal_lcdc_upscaler_config +
    +
    [Called By]
    • >>   hal_lcdc_init_cfg +
    + +

    hal_lcdc_upscaler_config (Thumb, 202 bytes, Stack size 40 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config)) +

    [Stack]

    • Max Depth = 144
    • Call Chain = hal_lcdc_upscaler_config ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   drv_lcdc_function_enable +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_dadd +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_lcdc_postproc_config +
    + +

    hal_nonshadow_func_update (Thumb, 180 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_nonshadow_func_update ⇒ drv_lcdc_config_int_single +
    +
    [Calls]
    • >>   drv_lcdc_fc_config +
    • >>   drv_lcdc_edge_enh_config +
    • >>   drv_lcdc_edge_dect_config +
    • >>   drv_lcdc_config_int_single +
    • >>   drv_lcdc_bcsa_config +
    +
    [Address Reference Count : 1]
    • hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) +
    +

    hal_pwr_enter_deep_sleep_mode (Thumb, 42 bytes, Stack size 8 bytes, hal_pwr.o(i.hal_pwr_enter_deep_sleep_mode)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_pwr_enter_deep_sleep_mode ⇒ drv_pwr_enter_deep_sleep_mode +
    +
    [Calls]
    • >>   drv_pwr_set_wakeup_type +
    • >>   drv_pwr_enter_deep_sleep_mode +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_pwr_enter_normal_sleep_mode (Thumb, 8 bytes, Stack size 8 bytes, hal_pwr.o(i.hal_pwr_enter_normal_sleep_mode)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_pwr_enter_normal_sleep_mode +
    +
    [Calls]
    • >>   drv_pwr_enter_sleep_mode_ex +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_pwr_enter_stop_sleep_mode (Thumb, 88 bytes, Stack size 16 bytes, hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = hal_pwr_enter_stop_sleep_mode ⇒ drv_pwr_enter_stop_sleep_mode +
    +
    [Calls]
    • >>   drv_pwr_enter_stop_sleep_mode +
    • >>   drv_sys_cfg_set_int +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_pwr_exit_sleep_mode (Thumb, 10 bytes, Stack size 8 bytes, hal_pwr.o(i.hal_pwr_exit_sleep_mode)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = hal_pwr_exit_sleep_mode ⇒ drv_pwr_exit_sleep_mode +
    +
    [Calls]
    • >>   drv_pwr_exit_sleep_mode +
    +
    [Called By]
    • >>   app_system_resume +
    + +

    hal_pwr_get_vcc_power_ready (Thumb, 8 bytes, Stack size 8 bytes, hal_pwr.o(i.hal_pwr_get_vcc_power_ready)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_pwr_get_vcc_power_ready +
    +
    [Calls]
    • >>   drv_pwr_get_power_ready_st +
    +
    [Called By]
    • >>   app_display_init +
    + +

    hal_pwr_set_main_power (Thumb, 8 bytes, Stack size 8 bytes, hal_pwr.o(i.hal_pwr_set_main_power)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_pwr_set_main_power ⇒ drv_pwr_set_digit_power_sel +
    +
    [Calls]
    • >>   drv_pwr_set_digit_power_sel +
    +
    [Called By]
    • >>   google_p8p_demo +
    + +

    hal_pwr_set_sleep_mode_power (Thumb, 8 bytes, Stack size 8 bytes, hal_pwr.o(i.hal_pwr_set_sleep_mode_power)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_pwr_set_sleep_mode_power ⇒ drv_pwr_set_breath_screen_power_sel +
    +
    [Calls]
    • >>   drv_pwr_set_breath_screen_power_sel +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_pwr_set_stop_sleep_wakeup_pin (Thumb, 86 bytes, Stack size 24 bytes, hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = hal_pwr_set_stop_sleep_wakeup_pin ⇒ hal_gpio_init_eint ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   hal_gpio_set_ap_reset_int +
    • >>   hal_gpio_reg_eint_cb +
    • >>   hal_gpio_init_eint +
    • >>   hal_gpio_ctrl_eint +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_swire_deinit (Thumb, 60 bytes, Stack size 8 bytes, hal_swire.o(i.hal_swire_deinit)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = hal_swire_deinit ⇒ hal_timer_deinit ⇒ drv_timer_set_int +
    +
    [Calls]
    • >>   drv_crgu_set_reset +
    • >>   drv_crgu_enable_clock +
    • >>   hal_timer_deinit +
    • >>   drv_swire_set_int +
    • >>   drv_swire_register_callback +
    • >>   drv_swire_enable +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_swire_enable (Thumb, 86 bytes, Stack size 8 bytes, hal_swire.o(i.hal_swire_enable)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_swire_enable ⇒ drv_swire_set_int +
    +
    [Calls]
    • >>   drv_timer_enable +
    • >>   drv_swire_set_trig_mode +
    • >>   drv_swire_set_power_down +
    • >>   drv_swire_set_int +
    • >>   drv_swire_get_pulse_count +
    +
    [Called By]
    • >>   app_init_panel +
    • >>   ap_dcs_set_enter_sleep_mode +
    + +

    hal_swire_init (Thumb, 74 bytes, Stack size 8 bytes, hal_swire.o(i.hal_swire_init)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_swire_init ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   drv_crgu_enable_clock +
    • >>   drv_swire_set_power_down +
    • >>   drv_swire_set_bit_time +
    • >>   drv_swire_enable +
    • >>   drv_crgu_set_clock_div +
    • >>   hal_gpio_set_mode +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   app_display_init +
    + +

    hal_swire_set_pulse (Thumb, 32 bytes, Stack size 8 bytes, hal_swire.o(i.hal_swire_set_pulse)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_swire_set_pulse +
    +
    [Calls]
    • >>   drv_swire_set_trig_mode +
    • >>   drv_swire_set_pulse_count +
    +
    [Called By]
    • >>   app_mipi_tx_start +
    • >>   app_init_panel +
    + +

    hal_swire_set_timer (Thumb, 60 bytes, Stack size 24 bytes, hal_swire.o(i.hal_swire_set_timer)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = hal_swire_set_timer ⇒ drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   hal_timer_init +
    • >>   hal_timer_set_repeat +
    • >>   drv_timer_set_compare_val +
    • >>   drv_sys_cfg_sel_swire_timer +
    • >>   drv_swire_set_trig_mode +
    +
    [Called By]
    • >>   app_display_init +
    + +

    hal_system_init (Thumb, 192 bytes, Stack size 8 bytes, hal_system.o(i.hal_system_init)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = hal_system_init ⇒ drv_common_system_init ⇒ drv_se_init ⇒ drv_efuse_read +
    +
    [Calls]
    • >>   drv_pwr_set_pll_clk +
    • >>   drv_crgu_enable_clock +
    • >>   drv_sys_cfg_clear_all_int +
    • >>   drv_common_system_init +
    • >>   hal_system_updata_sysclk +
    • >>   hal_gpio_set_mode +
    +
    [Called By]
    • >>   board_Init +
    + +

    hal_system_updata_sysclk (Thumb, 60 bytes, Stack size 8 bytes, hal_system.o(i.hal_system_updata_sysclk)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_system_updata_sysclk ⇒ drv_crgu_set_ahb_clk +
    +
    [Calls]
    • >>   drv_crgu_set_ahb_clk +
    +
    [Called By]
    • >>   hal_system_init +
    + +

    hal_timer_deinit (Thumb, 48 bytes, Stack size 8 bytes, hal_timer.o(i.hal_timer_deinit)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_timer_deinit ⇒ drv_timer_set_int +
    +
    [Calls]
    • >>   drv_crgu_set_reset +
    • >>   drv_crgu_enable_clock +
    • >>   drv_timer_set_repeat +
    • >>   drv_timer_set_int +
    • >>   drv_timer_enable +
    +
    [Called By]
    • >>   hal_swire_deinit +
    + +

    hal_timer_init (Thumb, 28 bytes, Stack size 8 bytes, hal_timer.o(i.hal_timer_init)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = hal_timer_init ⇒ drv_timer_set_prescaler +
    +
    [Calls]
    • >>   drv_crgu_enable_clock +
    • >>   drv_timer_set_prescaler +
    +
    [Called By]
    • >>   hal_swire_set_timer +
    + +

    hal_timer_set_repeat (Thumb, 8 bytes, Stack size 8 bytes, hal_timer.o(i.hal_timer_set_repeat)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_timer_set_repeat +
    +
    [Calls]
    • >>   drv_timer_set_repeat +
    +
    [Called By]
    • >>   hal_swire_set_timer +
    + +

    hal_uart_init (Thumb, 134 bytes, Stack size 48 bytes, hal_uart.o(i.hal_uart_init)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = hal_uart_init ⇒ drv_uart_init ⇒ drv_uart_set_baud_rate ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_uart_trans_create_handle +
    • >>   drv_uart_init +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   tau_log_init +
    + +

    hal_uart_send_blocking (Thumb, 24 bytes, Stack size 16 bytes, hal_uart.o(i.hal_uart_send_blocking)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_uart_send_blocking +
    +
    [Calls]
    • >>   drv_uart_send_blocking +
    +
    [Called By]
    • >>   fputc +
    + +

    hal_vsync_func_update (Thumb, 18 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_vsync_func_update)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_vsync_func_update ⇒ drv_lcdc_config_int_single +
    +
    [Calls]
    • >>   drv_lcdc_config_int_single +
    +
    [Address Reference Count : 1]
    • hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) +
    +

    hal_vsync_reset_lcdc_scaler (Thumb, 188 bytes, Stack size 40 bytes, hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler)) +

    [Stack]

    • Max Depth = 144
    • Call Chain = hal_vsync_reset_lcdc_scaler ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_ui2d +
    • >>   __aeabi_dadd +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_internal_sync_input_resolution_change +
    + +

    main (Thumb, 32 bytes, Stack size 0 bytes, main.o(i.main)) +

    [Stack]

    • Max Depth = 656
    • Call Chain = main ⇒ google_p8p_demo ⇒ app_system_process ⇒ app_system_resume ⇒ app_display_init ⇒ app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    • >>   google_p8p_demo +
    • >>   board_Init +
    +
    [Address Reference Count : 1]
    • entry9a.o(.ARM.Collect$$$$0000000B) +
    +

    tau_log_init (Thumb, 48 bytes, Stack size 32 bytes, tau_log.o(i.tau_log_init)) +

    [Stack]

    • Max Depth = 132
    • Call Chain = tau_log_init ⇒ hal_uart_init ⇒ drv_uart_init ⇒ drv_uart_set_baud_rate ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   hal_uart_init +
    +
    [Called By]
    • >>   board_Init +
    + +

    tau_log_printf (Thumb, 116 bytes, Stack size 296 bytes, tau_log.o(i.tau_log_printf)) +

    [Stack]

    • Max Depth = 336
    • Call Chain = tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_push_log +
    • >>   strlen +
    • >>   __aeabi_memclr4 +
    • >>   vsprintf +
    • >>   __2printf +
    +
    [Called By]
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   hal_internal_sync_input_resolution_change +
    • >>   hal_dsi_rx_ctrl_send_ack_cmd +
    • >>   app_system_suspend +
    • >>   app_system_resume +
    • >>   app_system_process +
    • >>   app_mipi_tx_start +
    • >>   app_mipi_tx_init +
    • >>   app_mipi_rx_init +
    • >>   ap_rstn_pull_down_cb +
    • >>   ap_dcs_set_exit_sleep_mode +
    • >>   ap_dcs_set_enter_sleep_mode +
    • >>   ap_dcs_set_display_on +
    • >>   ap_dcs_set_display_off +
    • >>   ap_dcs_read +
    • >>   google_p8p_demo +
    • >>   main +
    • >>   drv_se_set_dsc +
    • >>   HardFault_Handler +
    • >>   svs_wait_fr_stab +
    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    • >>   check_pkt_buf_rev +
    • >>   LCDC_IRQn_Handler +
    • >>   vidc_callback +
    • >>   rxbr_irq1_callback +
    • >>   MIPI_TX_IRQn_Handler +
    • >>   MIPI_RX_IRQn_Handler +
    • >>   drv_se_set_vidc +
    • >>   drv_se_set_rxbr +
    • >>   drv_se_set_memc +
    • >>   drv_se_set_lcdc +
    + +

    tau_log_push_log (Thumb, 118 bytes, Stack size 32 bytes, tau_log.o(i.tau_log_push_log)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   delayUs +
    • >>   __aeabi_memcpy +
    +
    [Called By]
    • >>   tau_log_printf +
    • >>   fputc +
    +

    +

    +Local Symbols +

    +

    ap_dcs_read (Thumb, 280 bytes, Stack size 72 bytes, p8p_demo.o(i.ap_dcs_read)) +

    [Stack]

    • Max Depth = 456
    • Call Chain = ap_dcs_read ⇒ hal_dsi_rx_ctrl_send_ack_cmd ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_dsi_rx_ctrl_send_ack_cmd +
    • >>   hal_dsi_rx_ctrl_get_max_ret_size +
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(i.app_mipi_rx_init) +
    +

    ap_dcs_set_backlight (Thumb, 146 bytes, Stack size 24 bytes, p8p_demo.o(i.ap_dcs_set_backlight)) +

    [Stack]

    • Max Depth = 108
    • Call Chain = ap_dcs_set_backlight ⇒ hal_dsi_tx_ctrl_write_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   __aeabi_idivmod +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    ap_dcs_set_display_off (Thumb, 34 bytes, Stack size 16 bytes, p8p_demo.o(i.ap_dcs_set_display_off)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = ap_dcs_set_display_off ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    ap_dcs_set_display_on (Thumb, 90 bytes, Stack size 16 bytes, p8p_demo.o(i.ap_dcs_set_display_on)) +

    [Stack]

    • Max Depth = 640
    • Call Chain = ap_dcs_set_display_on ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_rx_ctrl_toggle_resolution +
    • >>   hal_dsi_rx_ctrl_pre_init_pps +
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    ap_dcs_set_enter_sleep_mode (Thumb, 104 bytes, Stack size 16 bytes, p8p_demo.o(i.ap_dcs_set_enter_sleep_mode)) +

    [Stack]

    • Max Depth = 408
    • Call Chain = ap_dcs_set_enter_sleep_mode ⇒ hal_dsi_tx_ctrl_set_tear_mode ⇒ hal_internal_vsync_set_tear_mode ⇒ drv_memc_rate_transfer_sel ⇒ drv_se_set_memc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_swire_enable +
    • >>   hal_gpio_set_output_data +
    • >>   hal_gpio_set_ap_reset_int +
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_tx_ctrl_set_tear_mode +
    • >>   delayMs +
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    ap_dcs_set_exit_sleep_mode (Thumb, 28 bytes, Stack size 16 bytes, p8p_demo.o(i.ap_dcs_set_exit_sleep_mode)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = ap_dcs_set_exit_sleep_mode ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    ap_dcs_set_frame_change (Thumb, 46 bytes, Stack size 16 bytes, p8p_demo.o(i.ap_dcs_set_frame_change)) +

    [Stack]

    • Max Depth = 408
    • Call Chain = ap_dcs_set_frame_change ⇒ hal_dsi_tx_ctrl_set_tear_mode ⇒ hal_internal_vsync_set_tear_mode ⇒ drv_memc_rate_transfer_sel ⇒ drv_se_set_memc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_set_tear_mode +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    ap_rstn_pull_down_cb (Thumb, 38 bytes, Stack size 8 bytes, p8p_demo.o(i.ap_rstn_pull_down_cb)) +

    [Stack]

    • Max Depth = 344
    • Call Chain = ap_rstn_pull_down_cb ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_gpio_set_ap_reset_int +
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) +
    +

    ap_rstn_pull_high_cb (Thumb, 22 bytes, Stack size 8 bytes, p8p_demo.o(i.ap_rstn_pull_high_cb)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = ap_rstn_pull_high_cb ⇒ hal_gpio_set_ap_reset_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   hal_gpio_set_ap_reset_int +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(i.app_system_suspend) +
    +

    ap_set_FPS_53 (Thumb, 74 bytes, Stack size 32 bytes, p8p_demo.o(i.ap_set_FPS_53)) +

    [Stack]

    • Max Depth = 116
    • Call Chain = ap_set_FPS_53 ⇒ hal_dsi_tx_ctrl_write_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_write_cmd +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    app_init_panel (Thumb, 42 bytes, Stack size 8 bytes, p8p_demo.o(i.app_init_panel)) +

    [Stack]

    • Max Depth = 124
    • Call Chain = app_init_panel ⇒ send_panel_init_code ⇒ hal_dsi_tx_ctrl_write_array_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   hal_swire_set_pulse +
    • >>   hal_swire_enable +
    • >>   hal_gpio_init_output +
    • >>   delayMs +
    • >>   send_panel_init_code +
    • >>   app_tx_panel_reset +
    +
    [Called By]
    • >>   app_mipi_tx_start +
    + +

    app_mipi_rx_init (Thumb, 232 bytes, Stack size 8 bytes, p8p_demo.o(i.app_mipi_rx_init)) +

    [Stack]

    • Max Depth = 560
    • Call Chain = app_mipi_rx_init ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_dsi_rx_ctrl_start +
    • >>   hal_dsi_rx_ctrl_pre_init_pps +
    • >>   hal_dsi_rx_ctrl_init +
    • >>   hal_dsi_rx_ctrl_create_handle +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   app_display_init +
    + +

    app_mipi_tx_init (Thumb, 214 bytes, Stack size 8 bytes, p8p_demo.o(i.app_mipi_tx_init)) +

    [Stack]

    • Max Depth = 432
    • Call Chain = app_mipi_tx_init ⇒ hal_dsi_tx_ctrl_init ⇒ hal_dsi_tx_init_timing ⇒ hal_dsi_tx_cmd_mode_cal_timing ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_set_overwrite_rgb +
    • >>   hal_dsi_tx_ctrl_init +
    • >>   hal_dsi_tx_ctrl_create_handle +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   app_display_init +
    + +

    app_mipi_tx_start (Thumb, 118 bytes, Stack size 8 bytes, p8p_demo.o(i.app_mipi_tx_start)) +

    [Stack]

    • Max Depth = 632
    • Call Chain = app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_swire_set_pulse +
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_tx_ctrl_start +
    • >>   hal_dsi_tx_ctrl_set_tear_mode +
    • >>   hal_dsi_rx_ctrl_toggle_resolution +
    • >>   hal_dsi_rx_ctrl_pre_init_pps +
    • >>   delayMs +
    • >>   app_init_panel +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   app_display_init +
    + +

    app_system_process (Thumb, 60 bytes, Stack size 8 bytes, p8p_demo.o(i.app_system_process)) +

    [Stack]

    • Max Depth = 656
    • Call Chain = app_system_process ⇒ app_system_resume ⇒ app_display_init ⇒ app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   app_system_suspend +
    • >>   app_system_resume +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   google_p8p_demo +
    + +

    app_system_resume (Thumb, 30 bytes, Stack size 8 bytes, p8p_demo.o(i.app_system_resume)) +

    [Stack]

    • Max Depth = 648
    • Call Chain = app_system_resume ⇒ app_display_init ⇒ app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_pwr_exit_sleep_mode +
    • >>   app_display_init +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   app_system_process +
    + +

    app_system_suspend (Thumb, 202 bytes, Stack size 16 bytes, p8p_demo.o(i.app_system_suspend)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = app_system_suspend ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_swire_deinit +
    • >>   hal_pwr_set_stop_sleep_wakeup_pin +
    • >>   hal_pwr_set_sleep_mode_power +
    • >>   hal_pwr_enter_stop_sleep_mode +
    • >>   hal_pwr_enter_normal_sleep_mode +
    • >>   hal_pwr_enter_deep_sleep_mode +
    • >>   hal_gpio_set_ap_reset_int +
    • >>   hal_gpio_init_output +
    • >>   hal_dsi_tx_ctrl_stop +
    • >>   hal_dsi_tx_ctrl_deinit +
    • >>   hal_dsi_rx_ctrl_stop +
    • >>   hal_dsi_rx_ctrl_deinit +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   app_system_process +
    + +

    app_tx_panel_reset (Thumb, 46 bytes, Stack size 8 bytes, p8p_demo.o(i.app_tx_panel_reset)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = app_tx_panel_reset ⇒ delayMs ⇒ delayUs +
    +
    [Calls]
    • >>   hal_gpio_set_output_data +
    • >>   delayMs +
    +
    [Called By]
    • >>   app_init_panel +
    + +

    pps_update_handle (Thumb, 110 bytes, Stack size 24 bytes, p8p_demo.o(i.pps_update_handle)) +

    [Stack]

    • Max Depth = 648
    • Call Chain = pps_update_handle ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_set_tear_mode +
    • >>   hal_dsi_rx_ctrl_toggle_resolution +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(i.app_mipi_rx_init) +
    +

    send_panel_init_code (Thumb, 58 bytes, Stack size 32 bytes, p8p_demo.o(i.send_panel_init_code)) +

    [Stack]

    • Max Depth = 116
    • Call Chain = send_panel_init_code ⇒ hal_dsi_tx_ctrl_write_array_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_write_array_cmd +
    • >>   delayUs +
    +
    [Called By]
    • >>   app_init_panel +
    + +

    hal_dsi_rx_ctrl_init_clk (Thumb, 222 bytes, Stack size 32 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = hal_dsi_rx_ctrl_init_clk ⇒ drv_crgu_set_dsc_clk +
    +
    [Calls]
    • >>   drv_pwr_set_pll_clk +
    • >>   drv_crgu_set_vidc_clk +
    • >>   drv_crgu_set_rxbr_clk +
    • >>   drv_crgu_set_fb_clk +
    • >>   drv_crgu_set_dsc_clk +
    • >>   drv_crgu_enable_clock +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    + +

    hal_dsi_rx_ctrl_init_dsi_rx (Thumb, 218 bytes, Stack size 32 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx)) +

    [Stack]

    • Max Depth = 216
    • Call Chain = hal_dsi_rx_ctrl_init_dsi_rx ⇒ hal_dsi_rx_ctrl_set_ipi_cfg ⇒ drv_dsi_rx_calc_ipi_tx_delay ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   drv_dsi_rx_set_up_phy +
    • >>   drv_dsi_rx_set_tear_resp_en +
    • >>   drv_dsi_rx_set_resp_cnt +
    • >>   drv_dsi_rx_set_lane_swap +
    • >>   drv_dsi_rx_set_ipi_ycbcr_frmt +
    • >>   drv_dsi_rx_set_inten +
    • >>   drv_dsi_rx_set_ddi_crc_en +
    • >>   drv_dsi_rx_set_ddi_cfg +
    • >>   drv_dsi_rx_set_ctrl_cfg +
    • >>   drv_dsi_rx_set_check_crc +
    • >>   drv_dsi_rx_enable_irq +
    • >>   drv_crgu_get_rxbr_clk +
    • >>   hal_dsi_rx_ctrl_set_ipi_cfg +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    + +

    hal_dsi_rx_ctrl_init_memc (Thumb, 294 bytes, Stack size 80 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc)) +

    [Stack]

    • Max Depth = 440
    • Call Chain = hal_dsi_rx_ctrl_init_memc ⇒ drv_memc_set_ltpo_mode ⇒ drv_se_set_memc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_intl_fb_get_rx_fb_info +
    • >>   hal_intl_fb_get_memc_flow_mode +
    • >>   drv_memc_set_vidc_sync_cnt +
    • >>   drv_memc_set_tear_waveform +
    • >>   drv_memc_set_tear_mode +
    • >>   drv_memc_set_ltpo_pu_thres +
    • >>   drv_memc_set_ltpo_mode +
    • >>   drv_memc_set_lcdc_st_conditions +
    • >>   drv_memc_set_fs_en_conditions +
    • >>   drv_memc_set_double_buffer +
    • >>   drv_memc_set_data_mode +
    • >>   drv_memc_set_circ_mode_enable +
    • >>   drv_memc_set_active_height +
    • >>   drv_memc_sel_vsync +
    • >>   drv_memc_rate_transfer_sel +
    • >>   drv_memc_enable_irq +
    • >>   __ARM_common_switch8 +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    + +

    hal_dsi_rx_ctrl_init_rxbr (Thumb, 314 bytes, Stack size 144 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr)) +

    [Stack]

    • Max Depth = 504
    • Call Chain = hal_dsi_rx_ctrl_init_rxbr ⇒ drv_rxbr_set_color_format ⇒ drv_se_set_rxbr ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_intl_fb_get_rx_fb_info +
    • >>   hal_intl_fb_get_memc_flow_mode +
    • >>   hal_intl_dcs_set_auto_hw_filter +
    • >>   drv_rxbr_set_usr_row +
    • >>   drv_rxbr_set_usr_col +
    • >>   drv_rxbr_set_usr_cfg +
    • >>   drv_rxbr_set_ltpo_drop_th +
    • >>   drv_rxbr_set_inten +
    • >>   drv_rxbr_set_color_format +
    • >>   drv_rxbr_hline_rcv_cfg +
    • >>   drv_rxbr_frame_drop_cfg +
    • >>   drv_rxbr_enable_irq +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    + +

    hal_dsi_rx_ctrl_init_vidc (Thumb, 624 bytes, Stack size 168 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc)) +

    [Stack]

    • Max Depth = 536
    • Call Chain = hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_intl_fb_get_rx_fb_info +
    • >>   drv_vidc_set_vintp_config +
    • >>   drv_vidc_set_src_parameter +
    • >>   drv_vidc_set_scld_vcoef1 +
    • >>   drv_vidc_set_scld_vcoef0 +
    • >>   drv_vidc_set_scld_step +
    • >>   drv_vidc_set_scld_hcoef1 +
    • >>   drv_vidc_set_scld_hcoef0 +
    • >>   drv_vidc_set_rotation +
    • >>   drv_vidc_set_pu_ctrl +
    • >>   drv_vidc_set_pentile_swap +
    • >>   drv_vidc_set_mirror +
    • >>   drv_vidc_set_irqen +
    • >>   drv_vidc_set_honly_hinitr +
    • >>   drv_vidc_set_honly_hinitb +
    • >>   drv_vidc_set_honly_hcoef0 +
    • >>   drv_vidc_set_dst_parameter +
    • >>   drv_vidc_set_dither_config +
    • >>   drv_vidc_set_circ_mode_enable +
    • >>   drv_vidc_init_module_enable +
    • >>   drv_vidc_enable_irq +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_dadd +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_memcpy4 +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    + +

    hal_dsi_rx_ctrl_set_ipi_cfg (Thumb, 48 bytes, Stack size 24 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg)) +

    [Stack]

    • Max Depth = 184
    • Call Chain = hal_dsi_rx_ctrl_set_ipi_cfg ⇒ drv_dsi_rx_calc_ipi_tx_delay ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   drv_dsi_rx_set_ipi_cfg +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    hal_dsi_tx_cmd_mode_cal_timing (Thumb, 506 bytes, Stack size 56 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing)) +

    [Stack]

    • Max Depth = 392
    • Call Chain = hal_dsi_tx_cmd_mode_cal_timing ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_internal_sync_get_hight_performan_mode +
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fmul +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_fadd +
    • >>   __aeabi_f2d +
    • >>   __aeabi_d2uiz +
    • >>   tau_log_printf +
    • >>   __aeabi_idivmod +
    • >>   __aeabi_uidivmod +
    • >>   ceil +
    +
    [Called By]
    • >>   hal_dsi_tx_init_timing +
    + +

    hal_dsi_tx_ctrl_init_clk (Thumb, 12 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_tx_ctrl_init_clk +
    +
    [Calls]
    • >>   drv_crgu_enable_clock +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_init +
    + +

    hal_dsi_tx_init_cfg (Thumb, 258 bytes, Stack size 80 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = hal_dsi_tx_init_cfg ⇒ drv_dsi_tx_set_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_dsi_tx_video_mode_cfg +
    • >>   drv_dsi_tx_timeout_cfg +
    • >>   drv_dsi_tx_set_time_out_div +
    • >>   drv_dsi_tx_set_int +
    • >>   drv_dsi_tx_set_esc_div +
    • >>   drv_dsi_tx_set_bta_ack +
    • >>   drv_dsi_tx_response_mode +
    • >>   drv_dsi_tx_phy_lane_mode +
    • >>   drv_dsi_tx_phy_clock_lane_req_hs +
    • >>   drv_dsi_tx_phy_clock_lane_auto_lp +
    • >>   drv_dsi_tx_mode +
    • >>   drv_dsi_tx_dpi_polarity +
    • >>   drv_dsi_tx_dpi_mode +
    • >>   drv_dsi_tx_dpi_lpcmd_time +
    • >>   drv_dsi_tx_config_int +
    • >>   drv_dsi_tx_config_eotp +
    • >>   drv_dsi_tx_command_mode_cfg +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_init +
    + +

    hal_dsi_tx_init_dpi_timing (Thumb, 46 bytes, Stack size 40 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = hal_dsi_tx_init_dpi_timing ⇒ drv_crgu_set_dpi_clk +
    +
    [Calls]
    • >>   drv_crgu_set_dpi_clk +
    • >>   __aeabi_memcpy4 +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_dsi_tx_init_timing +
    + +

    hal_dsi_tx_init_phy_cfg (Thumb, 22 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = hal_dsi_tx_init_phy_cfg ⇒ drv_dsi_tx_phy_test_setup ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_dsi_tx_phy_time_cfg +
    • >>   drv_dsi_tx_phy_test_setup +
    +
    [Called By]
    • >>   hal_dsi_tx_init_timing +
    + +

    hal_dsi_tx_init_timing (Thumb, 82 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing)) +

    [Stack]

    • Max Depth = 408
    • Call Chain = hal_dsi_tx_init_timing ⇒ hal_dsi_tx_cmd_mode_cal_timing ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_dsi_tx_edpi_cmd_size +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_timing_info_update +
    • >>   hal_dsi_tx_init_vid_timing +
    • >>   hal_dsi_tx_init_phy_cfg +
    • >>   hal_dsi_tx_init_dpi_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_init +
    + +

    hal_dsi_tx_init_vid_timing (Thumb, 70 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_vid_timing)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_dsi_tx_init_vid_timing +
    +
    [Calls]
    • >>   drv_dsi_tx_set_video_timing +
    • >>   drv_dsi_tx_set_video_chunk +
    +
    [Called By]
    • >>   hal_dsi_tx_init_timing +
    + +

    hal_dsi_tx_send_cmd (Thumb, 58 bytes, Stack size 24 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   drv_dsi_tx_phy_status_stopstate +
    • >>   drv_dsi_tx_get_cmd_status +
    • >>   drv_dsi_tx_command_header +
    • >>   hal_internal_vsync_get_tx_state +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_tx_ctrl_write_array_cmd +
    + +

    hal_dsi_tx_timing_info_update (Thumb, 142 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_timing_info_update)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = hal_dsi_tx_timing_info_update ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_d2f +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_dsi_tx_init_timing +
    + +

    hal_dsi_tx_vid_mode_cal_timing (Thumb, 766 bytes, Stack size 96 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing)) +

    [Stack]

    • Max Depth = 232
    • Call Chain = hal_dsi_tx_vid_mode_cal_timing ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   hal_internal_sync_get_hight_performan_mode +
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fmul +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_f2d +
    • >>   __aeabi_d2uiz +
    • >>   hal_intl_svs_init_tx +
    • >>   hal_intl_fb_get_user_flow +
    • >>   __aeabi_idivmod +
    • >>   __aeabi_uidivmod +
    • >>   ceil +
    +
    [Called By]
    • >>   hal_dsi_tx_init_timing +
    + +

    hal_lcdc_init_cfg (Thumb, 62 bytes, Stack size 88 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg)) +

    [Stack]

    • Max Depth = 320
    • Call Chain = hal_lcdc_init_cfg ⇒ hal_lcdc_postproc_config ⇒ hal_lcdc_upscaler_config ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   hal_intl_fb_get_tx_fb_info +
    • >>   drv_lcdc_set_int +
    • >>   drv_lcdc_config_int +
    • >>   hal_lcdc_postproc_config +
    • >>   hal_lcdc_displayproc_config +
    • >>   hal_lcdc_timinggen_config +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_init +
    + +

    hal_lcdc_init_clk (Thumb, 112 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = hal_lcdc_init_clk ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   drv_crgu_set_lcdc_clk +
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_f2d +
    • >>   __ARM_scalbnf +
    • >>   __aeabi_d2uiz +
    • >>   ceil +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_init +
    + +

    hal_lcdc_start (Thumb, 36 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_start)) +

    [Stack]

    • Max Depth = 368
    • Call Chain = hal_lcdc_start ⇒ drv_lcdc_vid_hw_start ⇒ drv_se_set_lcdc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_lcdc_vid_hw_start +
    • >>   drv_lcdc_cmd_start +
    • >>   hal_intl_fb_get_memc_flow_mode +
    • >>   hal_intl_fb_get_user_flow +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_start +
    + +

    hal_lcdc_timinggen_config (Thumb, 60 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_lcdc_timinggen_config ⇒ drv_lcdc_ctrl_flow +
    +
    [Calls]
    • >>   hal_internal_vsync_get_sync_line +
    • >>   drv_lcdc_set_prefetch +
    • >>   drv_lcdc_ctrl_flow +
    • >>   drv_lcdc_config_src_parameter +
    • >>   hal_intl_fb_get_memc_flow_mode +
    +
    [Called By]
    • >>   hal_lcdc_init_cfg +
    + +

    hal_tx_frame_rate_adjust (Thumb, 44 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust)) +

    [Stack]

    • Max Depth = 440
    • Call Chain = hal_tx_frame_rate_adjust ⇒ hal_dsi_tx_ctrl_init ⇒ hal_dsi_tx_init_timing ⇒ hal_dsi_tx_cmd_mode_cal_timing ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_internal_vsync_set_tx_state +
    • >>   __aeabi_cfcmple +
    • >>   hal_internal_vsync_get_tx_state +
    • >>   hal_dsi_tx_ctrl_init +
    +
    [Address Reference Count : 1]
    • hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) +
    +

    drv_gpio_set_output_data (Thumb, 26 bytes, Stack size 0 bytes, hal_gpio.o(i.drv_gpio_set_output_data)) +

    [Called By]

    • >>   hal_gpio_set_output_data +
    • >>   hal_gpio_init_output +
    + +

    stop_sleep_cb (Thumb, 18 bytes, Stack size 0 bytes, hal_pwr.o(i.stop_sleep_cb)) +
    [Address Reference Count : 1]

    • hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) +
    +

    check_mipi_rx_tx_video_info (Thumb, 44 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.check_mipi_rx_tx_video_info)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = check_mipi_rx_tx_video_info +
    +
    [Called By]
    • >>   hal_internal_vsync_init_tx +
    • >>   hal_internal_vsync_init_rx +
    + +

    drv_rxbr_get_int_source (Thumb, 20 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.drv_rxbr_get_int_source)) +

    [Called By]

    • >>   rxbr_irq1_callback +
    + +

    rxbr_irq1_callback (Thumb, 466 bytes, Stack size 40 bytes, hal_internal_vsync.o(i.rxbr_irq1_callback)) +

    [Stack]

    • Max Depth = 400
    • Call Chain = rxbr_irq1_callback ⇒ drv_lcdc_cmd_start ⇒ drv_se_set_lcdc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_lcdc_cmd_start +
    • >>   drv_dsi_tx_phy_clock_lane_req_hs +
    • >>   drv_vidc_enable +
    • >>   drv_rxbr_set_inten +
    • >>   tau_log_printf +
    • >>   hal_intl_svs_set_rx_vtt +
    • >>   hal_intl_svs_handle +
    • >>   drv_rxbr_clear_status0 +
    • >>   drv_rxbr_clear_pkt_buffer +
    • >>   vpre_err_reset +
    • >>   soft_double_buffer_update +
    • >>   drv_rxbr_get_int_source +
    • >>   hal_intl_fb_get_user_flow +
    +
    [Address Reference Count : 1]
    • hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    +

    soft_double_buffer_update (Thumb, 56 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.soft_double_buffer_update)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = soft_double_buffer_update +
    +
    [Called By]
    • >>   rxbr_irq1_callback +
    + +

    soft_gen_te (Thumb, 102 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.soft_gen_te)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = soft_gen_te +
    +
    [Address Reference Count : 1]
    • hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    +

    soft_gen_te_double_buffer (Thumb, 122 bytes, Stack size 20 bytes, hal_internal_vsync.o(i.soft_gen_te_double_buffer)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = soft_gen_te_double_buffer +
    +
    [Address Reference Count : 1]
    • hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    +

    vidc_callback (Thumb, 150 bytes, Stack size 24 bytes, hal_internal_vsync.o(i.vidc_callback)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = vidc_callback ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_lcdc_function_disable +
    • >>   drv_vidc_set_irqen +
    • >>   tau_log_printf +
    • >>   drv_vidc_get_irq_status +
    • >>   drv_vidc_get_int_source +
    • >>   drv_vidc_clear_irq +
    +
    [Address Reference Count : 1]
    • hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    +

    vpre_err_reset (Thumb, 254 bytes, Stack size 64 bytes, hal_internal_vsync.o(i.vpre_err_reset)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = vpre_err_reset +
    +
    [Calls]
    • >>   drv_crgu_set_reset +
    • >>   drv_vidc_reset +
    +
    [Called By]
    • >>   rxbr_irq1_callback +
    + +

    check_pkt_buf_rev (Thumb, 84 bytes, Stack size 24 bytes, hal_internal_dcs.o(i.check_pkt_buf_rev)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = check_pkt_buf_rev ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    • >>   drv_rxbr_get_status0 +
    • >>   drv_rxbr_clear_status0 +
    • >>   drv_rxbr_clear_pkt_buffer +
    +
    [Called By]
    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    + +

    drv_rxbr_get_status0 (Thumb, 20 bytes, Stack size 0 bytes, hal_internal_dcs.o(i.drv_rxbr_get_status0)) +

    [Called By]

    • >>   VPRE_IRQn_Handler +
    • >>   check_pkt_buf_rev +
    + +

    hal_intl_dcs_rx_get_dcs_packet_data (Thumb, 806 bytes, Stack size 64 bytes, hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data)) +

    [Stack]

    • Max Depth = 424
    • Call Chain = hal_intl_dcs_rx_get_dcs_packet_data ⇒ check_pkt_buf_rev ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_dsi_tx_command_put_payload +
    • >>   hal_dsi_rx_ctrl_dcs_async_handler +
    • >>   tau_log_printf +
    • >>   drv_dsi_rx_get_ddi_crc_en +
    • >>   dcs_packet_fifo_alloc +
    • >>   hal_intl_dcs_sw_filter_handle +
    • >>   check_pkt_buf_rev +
    +
    [Called By]
    • >>   hal_intl_dcs_rx_receive_packet +
    + +

    hal_intl_dcs_rx_receive_packet (Thumb, 122 bytes, Stack size 8 bytes, hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet)) +

    [Stack]

    • Max Depth = 528
    • Call Chain = hal_intl_dcs_rx_receive_packet ⇒ hal_intl_dcs_rx_receive_pps ⇒ drv_dsc_dec_enable ⇒ drv_se_set_dsc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    • >>   drv_rxbr_clear_status0 +
    • >>   drv_rxbr_clear_pkt_buffer +
    +
    [Called By]
    • >>   VPRE_IRQn_Handler +
    + +

    hal_intl_dcs_rx_receive_pps (Thumb, 268 bytes, Stack size 160 bytes, hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps)) +

    [Stack]

    • Max Depth = 520
    • Call Chain = hal_intl_dcs_rx_receive_pps ⇒ drv_dsc_dec_enable ⇒ drv_se_set_dsc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_dsi_rx_get_compression_en +
    • >>   drv_dsc_dec_enable +
    • >>   drv_crgu_enable_clock +
    • >>   tau_log_printf +
    • >>   check_pkt_buf_rev +
    • >>   drv_rxbr_clear_pkt_buffer +
    • >>   __aeabi_memclr4 +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_intl_dcs_rx_receive_packet +
    + +

    hal_intl_dcs_sw_filter_handle (Thumb, 36 bytes, Stack size 0 bytes, hal_internal_dcs.o(i.hal_intl_dcs_sw_filter_handle)) +

    [Called By]

    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    + +

    ha_intl_fb_check_pu_size (Thumb, 58 bytes, Stack size 16 bytes, hal_internal_fb.o(i.ha_intl_fb_check_pu_size)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = ha_intl_fb_check_pu_size ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_intl_fb_cal_fb_info +
    + +

    hal_intl_fb_check_bandwidth (Thumb, 92 bytes, Stack size 40 bytes, hal_internal_fb.o(i.hal_intl_fb_check_bandwidth)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = hal_intl_fb_check_bandwidth ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   hal_internal_sync_get_hight_performan_mode +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_intl_fb_cal_fb_info +
    + +

    hal_intl_fb_edge_resize (Thumb, 214 bytes, Stack size 48 bytes, hal_internal_fb.o(i.hal_intl_fb_edge_resize)) +

    [Stack]

    • Max Depth = 60
    • Call Chain = hal_intl_fb_edge_resize ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_intl_fb_cal_fb_info +
    + +

    hal_intl_fb_flow_control_adapter (Thumb, 94 bytes, Stack size 16 bytes, hal_internal_fb.o(i.hal_intl_fb_flow_control_adapter)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_intl_fb_flow_control_adapter +
    +
    [Called By]
    • >>   hal_intl_fb_cal_fb_info +
    + +

    svs_direct_mode_setting (Thumb, 154 bytes, Stack size 88 bytes, hal_internal_svs.o(i.svs_direct_mode_setting)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = svs_direct_mode_setting ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   hal_intl_fb_get_rx_fb_info +
    • >>   drv_rxbr_hline_rcv1_cfg +
    • >>   drv_rxbr_clear_status0 +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   svs_wait_start +
    + +

    svs_get_rel_intv (Thumb, 20 bytes, Stack size 8 bytes, hal_internal_svs.o(i.svs_get_rel_intv)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = svs_get_rel_intv ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   svs_wait_start +
    • >>   svs_wait_fr_stab +
    • >>   svs_sync_handle +
    + +

    svs_sync_handle (Thumb, 158 bytes, Stack size 24 bytes, hal_internal_svs.o(i.svs_sync_handle)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = svs_sync_handle ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fmul +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_f2d +
    • >>   __aeabi_dadd +
    • >>   __aeabi_d2uiz +
    • >>   svs_get_rel_intv +
    +
    [Address Reference Count : 1]
    • hal_internal_svs.o(i.svs_wait_fr_stab) +
    +

    svs_wait_fr_stab (Thumb, 148 bytes, Stack size 16 bytes, hal_internal_svs.o(i.svs_wait_fr_stab)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = svs_wait_fr_stab ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fmul +
    • >>   drv_rxbr_frame_drop_cfg +
    • >>   tau_log_printf +
    • >>   __aeabi_f2uiz +
    • >>   svs_get_rel_intv +
    • >>   __aeabi_uidivmod +
    +
    [Address Reference Count : 1]
    • hal_internal_svs.o(i.svs_wait_start) +
    +

    svs_wait_start (Thumb, 250 bytes, Stack size 24 bytes, hal_internal_svs.o(i.svs_wait_start)) +

    [Stack]

    • Max Depth = 160
    • Call Chain = svs_wait_start ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fmul +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_f2d +
    • >>   hal_internal_vsync_get_tx_state +
    • >>   drv_rxbr_set_inten +
    • >>   drv_crgu_get_rxbr_clk +
    • >>   __aeabi_d2uiz +
    • >>   drv_rxbr_hline_rcv1_cfg +
    • >>   svs_get_rel_intv +
    • >>   svs_direct_mode_setting +
    • >>   drv_rxbr_clear_status0 +
    • >>   ceil +
    +
    [Address Reference Count : 2]
    • hal_internal_svs.o(i.hal_intl_svs_deinit_rx) +
    • hal_internal_svs.o(i.hal_intl_svs_init_rx) +
    +

    drv_gpio_handle_int (Thumb, 30 bytes, Stack size 8 bytes, drv_gpio.o(i.drv_gpio_handle_int)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   EXTI_INT7_IRQn_Handler +
    • >>   EXTI_INT6_IRQn_Handler +
    • >>   EXTI_INT5_IRQn_Handler +
    • >>   EXTI_INT4_IRQn_Handler +
    • >>   EXTI_INT3_IRQn_Handler +
    • >>   EXTI_INT2_IRQn_Handler +
    • >>   EXTI_INT1_IRQn_Handler +
    • >>   EXTI_INT0_IRQn_Handler +
    + +

    drv_timer_clear_status_flags (Thumb, 26 bytes, Stack size 8 bytes, drv_timer.o(i.drv_timer_clear_status_flags)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_timer_clear_status_flags ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    • >>   drv_timer_get_instance +
    +
    [Called By]
    • >>   drv_timer_handle_interrupt +
    + +

    drv_timer_handle_interrupt (Thumb, 54 bytes, Stack size 16 bytes, drv_timer.o(i.drv_timer_handle_interrupt)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = drv_timer_handle_interrupt ⇒ drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_timer_set_int +
    • >>   drv_timer_set_compare_val +
    • >>   drv_timer_clear_status_flags +
    +
    [Called By]
    • >>   TIMER3_IRQn_Handler +
    • >>   TIMER2_IRQn_Handler +
    • >>   TIMER1_IRQn_Handler +
    • >>   TIMER0_IRQn_Handler +
    + +

    drv_dsi_rx_get_color_bpp (Thumb, 62 bytes, Stack size 4 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_dsi_rx_get_color_bpp ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   __ARM_common_switch8 +
    +
    [Called By]
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    + +

    drv_dsi_rx_get_color_pcc (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_color_pcc)) +

    [Called By]

    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    + +

    drv_lcdc_clear_int (Thumb, 20 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_clear_int)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_lcdc_clear_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   drv_lcdc_set_int +
    + +

    __NVIC_DisableIRQ (Thumb, 26 bytes, Stack size 0 bytes, drv_rxbr.o(i.__NVIC_DisableIRQ)) +

    [Called By]

    • >>   drv_rxbr_enable_irq +
    + +

    __NVIC_EnableIRQ (Thumb, 18 bytes, Stack size 0 bytes, drv_rxbr.o(i.__NVIC_EnableIRQ)) +

    [Called By]

    • >>   drv_rxbr_enable_irq +
    + +

    drv_dma_get_int_source (Thumb, 16 bytes, Stack size 0 bytes, drv_dma.o(i.drv_dma_get_int_source)) +

    [Called By]

    • >>   DMA_IRQn_Handler +
    + +

    drv_uart_enable_clk (Thumb, 24 bytes, Stack size 8 bytes, drv_uart.o(i.drv_uart_enable_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_uart_enable_clk +
    +
    [Calls]
    • >>   drv_crgu_enable_clock +
    +
    [Called By]
    • >>   drv_uart_init +
    + +

    drv_uart_int_trans_handle (Thumb, 54 bytes, Stack size 8 bytes, drv_uart.o(i.drv_uart_int_trans_handle)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_uart_int_trans_handle +
    +
    [Called By]
    • >>   UART_IRQn_Handler +
    + +

    _fp_digits (Thumb, 344 bytes, Stack size 64 bytes, printfa.o(i._fp_digits), UNUSED) +

    [Calls]

    • >>   __aeabi_dadd +
    • >>   __aeabi_dmul +
    • >>   __aeabi_cdrcmple +
    • >>   __aeabi_uldivmod +
    • >>   __aeabi_ddiv +
    • >>   __aeabi_d2ulz +
    +
    [Called By]
    • >>   _printf_core +
    + +

    _printf_core (Thumb, 1754 bytes, Stack size 128 bytes, printfa.o(i._printf_core), UNUSED) +

    [Calls]

    • >>   __aeabi_uidivmod +
    • >>   __aeabi_uldivmod +
    • >>   _printf_pre_padding +
    • >>   _printf_post_padding +
    • >>   _fp_digits +
    +
    [Called By]
    • >>   __0vsprintf +
    • >>   __0printf +
    + +

    _printf_post_padding (Thumb, 32 bytes, Stack size 24 bytes, printfa.o(i._printf_post_padding), UNUSED) +

    [Called By]

    • >>   _printf_core +
    + +

    _printf_pre_padding (Thumb, 44 bytes, Stack size 40 bytes, printfa.o(i._printf_pre_padding), UNUSED) +

    [Called By]

    • >>   _printf_core +
    + +

    _sputc (Thumb, 10 bytes, Stack size 0 bytes, printfa.o(i._sputc)) +

    [Called By]

    • >>   __0vsprintf +
    +
    [Address Reference Count : 1]
    • printfa.o(i.__0vsprintf) +

    +

    +Undefined Global Symbols +

    diff --git a/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.lnp b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.lnp new file mode 100644 index 0000000..4f2c228 --- /dev/null +++ b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.lnp @@ -0,0 +1,10 @@ +--cpu Cortex-M0 +".\objects\main.o" +".\objects\p8p_demo.o" +"..\..\src\sdk\CVWL668\lib\CVWL668.lib" +".\objects\board.o" +".\objects\startup_armcm0.o" +--library_type=microlib --strict --scatter ".\Objects\WL668_P8P_TM667_ICNA3508_20240401.sct" +--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list ".\Listings\WL668_P8P_TM667_ICNA3508_20240401.map" -o .\Objects\WL668_P8P_TM667_ICNA3508_20240401.axf \ No newline at end of file diff --git a/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.sct b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.sct new file mode 100644 index 0000000..8775845 --- /dev/null +++ b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240401.sct @@ -0,0 +1,16 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM2 0x00010000 0x00010000 { ; load region size_region + ER_IROM2 0x00010000 0x00010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x00070000 0x00008000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.axf b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.axf new file mode 100644 index 0000000..dcc0206 Binary files /dev/null and b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.axf differ diff --git a/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.bin b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.bin new file mode 100644 index 0000000..49d6b53 Binary files /dev/null and b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.bin differ diff --git a/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.build_log.htm b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.build_log.htm new file mode 100644 index 0000000..b20326a --- /dev/null +++ b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.build_log.htm @@ -0,0 +1,79 @@ + + +
    +
    Vision Build Log
    
+
    Tool Versions:
    
+IDE-Version: Vision V5.28.0.0
+Copyright (C) 2019 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: HAHA Markin, HAHA, LIC=VGXG8-3CKFQ-63XMB-246PQ-J4CUG-RTS7K
+ 
+Tool Versions:
+Toolchain:       MDK-ARM Plus  Version: 5.28.0.0
+Toolchain Path:  C:\Keil_v5\ARM\ARMCC\Bin
+C Compiler:      Armcc.exe V5.06 update 6 (build 750)
+Assembler:       Armasm.exe V5.06 update 6 (build 750)
+Linker/Locator:  ArmLink.exe V5.06 update 6 (build 750)
+Library Manager: ArmAr.exe V5.06 update 6 (build 750)
+Hex Converter:   FromElf.exe V5.06 update 6 (build 750)
+CPU DLL:         SARMCM3.DLL V5.28.0.0
+Dialog DLL:      DARMCM1.DLL V1.19.2.0
+Target DLL:      UL2CM3.DLL V1.162.16.0
+Dialog DLL:      TARMCM1.DLL V1.14.1.0
+ 
+
    Project:
    
+D:\Custom\\WL668_Pixel 8 Pro_TM667_ICNA3508(RAMLESS)_ CST6656S_OLED\Դ\WL668_GOOGLEP8P_TM667_ICNA3508_OLED_FHD_20240315\WL668_GOOGLEP8P_TM667_ICNA3508_20240306_5608\project\WL668\WL668.uvprojx
+Project File Date:  04/07/2024
+
+
    Output:
    
+*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
+Rebuild target 'WL668'
+creating preprocessor file for main.c...
+compiling main.c...
+creating preprocessor file for p8p_demo.c...
+compiling p8p_demo.c...
+..\..\src\app\P8P\p8p_demo.c(473): warning:  #186-D: pointless comparison of unsigned integer with zero
+        if((rd_51_val >=0x00)&&(rd_51_val <= 0xFFF) ){
+..\..\src\app\P8P\p8p_demo.c(131): warning:  #550-D: variable "sg_exit_idle_mode_flag"  was set but never used
+  static bool sg_exit_idle_mode_flag = false;
+..\..\src\app\P8P\p8p_demo.c(134): warning:  #177-D: variable "pps_renew_flag"  was declared but never referenced
+  static uint32_t pps_renew_flag = 0;
+..\..\src\app\P8P\p8p_demo.c(135): warning:  #177-D: variable "pwr_rst_flag"  was declared but never referenced
+  static uint32_t pwr_rst_flag = 0;
+..\..\src\app\P8P\p8p_demo.c(149): warning:  #177-D: function "app_mipi_rx_start_cb"  was declared but never referenced
+  static void app_mipi_rx_start_cb(void *data);
+..\..\src\app\P8P\p8p_demo.c(459): warning:  #177-D: variable "reg53_E8_fg"  was declared but never referenced
+  static bool reg53_E8_fg=0;
+..\..\src\app\P8P\p8p_demo.c(533): warning:  #177-D: function "ap_dcs_set_exit_idle_mode"  was declared but never referenced
+  static bool ap_dcs_set_exit_idle_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet)
+..\..\src\app\P8P\p8p_demo.c(558): warning:  #177-D: function "soft_te_timer_init"  was declared but never referenced
+  static void soft_te_timer_init()
+..\..\src\app\P8P\p8p_demo.c: 8 warnings, 0 errors
+creating preprocessor file for board.c...
+compiling board.c...
+assembling startup_ARMCM0.s...
+linking...
+Program Size: Code=37772 RO-data=9272 RW-data=1048 ZI-data=11632  
+FromELF: creating hex file...
+After Build - User command #1: fromelf  --bin  -o  .\Objects\WL668_P8P_TM667_ICNA3508_20240407.bin  .\Objects\WL668_P8P_TM667_ICNA3508_20240407.axf
+".\Objects\WL668_P8P_TM667_ICNA3508_20240407.axf" - 0 Error(s), 8 Warning(s).
+
+
    Software Packages used:
    
+
+Package Vendor: ARM
+                http://www.keil.com/pack/ARM.CMSIS.5.5.1.pack
+                ARM.CMSIS.5.5.1
+                CMSIS (Cortex Microcontroller Software Interface Standard)
+   * Component: CORE Version: 5.2.0
+
+
    Collection of Component include folders:
    
+  .\RTE\_WL668
+  C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include
+  C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include
+
+
    Collection of Component Files used:
    
+
+   * Component: ARM::CMSIS:CORE:5.2.0
+Build Time Elapsed:  00:00:02
+
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+:04000005000100C135 +:00000001FF diff --git a/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.htm b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.htm new file mode 100644 index 0000000..98733da --- /dev/null +++ b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.htm @@ -0,0 +1,4007 @@ + + +Static Call Graph - [.\Objects\WL668_P8P_TM667_ICNA3508_20240407.axf] +
    +

    Static Call Graph for image .\Objects\WL668_P8P_TM667_ICNA3508_20240407.axf

    +

    #<CALLGRAPH># ARM Linker, 5060750: Last Updated: Tue Apr 09 11:46:48 2024 +

    +

    Maximum Stack Usage = 656 bytes + Unknown(Cycles, Untraceable Function Pointers)

    +Call chain for Maximum Stack Depth:

    +main ⇒ google_p8p_demo ⇒ app_system_process ⇒ app_system_resume ⇒ app_display_init ⇒ app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +

    +

    +Mutually Recursive functions +

  • NMI_Handler   ⇒   NMI_Handler
    +
  • SVC_Handler   ⇒   SVC_Handler
    +
  • PendSV_Handler   ⇒   PendSV_Handler
    +
  • FLSCTRL_IRQn_Handler   ⇒   FLSCTRL_IRQn_Handler
    +
  • WDG_IRQn_Handler   ⇒   WDG_IRQn_Handler
    +
  • I2C0_IRQn_Handler   ⇒   I2C0_IRQn_Handler
    +
  • I2C1_IRQn_Handler   ⇒   I2C1_IRQn_Handler
    +
  • SPIS_IRQn_Handler   ⇒   SPIS_IRQn_Handler
    +
  • SPIM_IRQn_Handler   ⇒   SPIM_IRQn_Handler
    +
  • I2C2_IRQn_Handler   ⇒   I2C2_IRQn_Handler
    +
  • OTP_IRQn_Handler   ⇒   OTP_IRQn_Handler
    +
  • PVD_IRQn_Handler   ⇒   PVD_IRQn_Handler
    + +

    +

    +Function Pointers +

      +
    • AP_NRESET_IRQn_Handler from drv_gpio.o(i.AP_NRESET_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • DMA_IRQn_Handler from drv_dma.o(i.DMA_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT0_IRQn_Handler from drv_gpio.o(i.EXTI_INT0_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT1_IRQn_Handler from drv_gpio.o(i.EXTI_INT1_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT2_IRQn_Handler from drv_gpio.o(i.EXTI_INT2_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT3_IRQn_Handler from drv_gpio.o(i.EXTI_INT3_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT4_IRQn_Handler from drv_gpio.o(i.EXTI_INT4_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT5_IRQn_Handler from drv_gpio.o(i.EXTI_INT5_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT6_IRQn_Handler from drv_gpio.o(i.EXTI_INT6_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • EXTI_INT7_IRQn_Handler from drv_gpio.o(i.EXTI_INT7_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • FLSCTRL_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • HardFault_Handler from drv_common.o(i.HardFault_Handler) referenced from startup_armcm0.o(RESET) +
    • I2C0_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • I2C1_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • I2C2_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • LCDC_IRQn_Handler from hal_internal_vsync.o(i.LCDC_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • MEMC_IRQn_Handler from drv_memc.o(i.MEMC_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • MIPI_RX_IRQn_Handler from drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • MIPI_TX_IRQn_Handler from drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • NMI_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • OTP_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • PVD_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • PendSV_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • Reset_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • SPIM_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • SPIS_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • SVC_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • SWIRE_IRQn_Handler from drv_swire.o(i.SWIRE_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • SysTick_Handler from drv_common.o(i.SysTick_Handler) referenced from startup_armcm0.o(RESET) +
    • TIMER0_IRQn_Handler from drv_timer.o(i.TIMER0_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • TIMER1_IRQn_Handler from drv_timer.o(i.TIMER1_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • TIMER2_IRQn_Handler from drv_timer.o(i.TIMER2_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • TIMER3_IRQn_Handler from drv_timer.o(i.TIMER3_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • UART_IRQn_Handler from drv_uart.o(i.UART_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • VIDC_IRQn_Handler from drv_vidc.o(i.VIDC_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • VPRE1_IRQn_Handler from drv_rxbr.o(i.VPRE1_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • VPRE_IRQn_Handler from hal_internal_dcs.o(i.VPRE_IRQn_Handler) referenced from startup_armcm0.o(RESET) +
    • WDG_IRQn_Handler from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET) +
    • __main from entry.o(.ARM.Collect$$$$00000000) referenced from startup_armcm0.o(.text) +
    • _sputc from printfa.o(i._sputc) referenced from printfa.o(i.__0vsprintf) +
    • ap_dcs_read from p8p_demo.o(i.ap_dcs_read) referenced from p8p_demo.o(i.app_mipi_rx_init) +
    • ap_dcs_set_backlight from p8p_demo.o(i.ap_dcs_set_backlight) referenced from p8p_demo.o(.constdata) +
    • ap_dcs_set_display_off from p8p_demo.o(i.ap_dcs_set_display_off) referenced from p8p_demo.o(.constdata) +
    • ap_dcs_set_display_on from p8p_demo.o(i.ap_dcs_set_display_on) referenced from p8p_demo.o(.constdata) +
    • ap_dcs_set_enter_sleep_mode from p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) referenced from p8p_demo.o(.constdata) +
    • ap_dcs_set_exit_sleep_mode from p8p_demo.o(i.ap_dcs_set_exit_sleep_mode) referenced from p8p_demo.o(.constdata) +
    • ap_dcs_set_frame_change from p8p_demo.o(i.ap_dcs_set_frame_change) referenced from p8p_demo.o(.constdata) +
    • ap_rstn_pull_down_cb from p8p_demo.o(i.ap_rstn_pull_down_cb) referenced from p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) +
    • ap_rstn_pull_high_cb from p8p_demo.o(i.ap_rstn_pull_high_cb) referenced from p8p_demo.o(i.app_system_suspend) +
    • ap_set_FPS_53 from p8p_demo.o(i.ap_set_FPS_53) referenced from p8p_demo.o(.constdata) +
    • fputc from tau_log.o(i.fputc) referenced from printfa.o(i.__0printf) +
    • hal_nonshadow_func_update from hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update) referenced from hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) +
    • hal_tx_frame_rate_adjust from hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) referenced from hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) +
    • hal_vsync_func_update from hal_dsi_tx_ctrl.o(i.hal_vsync_func_update) referenced from hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) +
    • main from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B) +
    • pps_update_handle from p8p_demo.o(i.pps_update_handle) referenced from p8p_demo.o(i.app_mipi_rx_init) +
    • rxbr_irq1_callback from hal_internal_vsync.o(i.rxbr_irq1_callback) referenced from hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    • soft_gen_te from hal_internal_vsync.o(i.soft_gen_te) referenced from hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    • soft_gen_te_double_buffer from hal_internal_vsync.o(i.soft_gen_te_double_buffer) referenced from hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    • stop_sleep_cb from hal_pwr.o(i.stop_sleep_cb) referenced from hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) +
    • svs_sync_handle from hal_internal_svs.o(i.svs_sync_handle) referenced from hal_internal_svs.o(i.svs_wait_fr_stab) +
    • svs_wait_fr_stab from hal_internal_svs.o(i.svs_wait_fr_stab) referenced from hal_internal_svs.o(i.svs_wait_start) +
    • svs_wait_start from hal_internal_svs.o(i.svs_wait_start) referenced from hal_internal_svs.o(i.hal_intl_svs_deinit_rx) +
    • svs_wait_start from hal_internal_svs.o(i.svs_wait_start) referenced from hal_internal_svs.o(i.hal_intl_svs_init_rx) +
    • vidc_callback from hal_internal_vsync.o(i.vidc_callback) referenced from hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    +

    +

    +Global Symbols +

    +

    __main (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000)) +
    [Address Reference Count : 1]

    • startup_armcm0.o(.text) +
    +

    _main_stk (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001)) + +

    _main_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Calls]

    • >>   __scatterload +
    + +

    __main_after_scatterload (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004)) +

    [Called By]

    • >>   __scatterload +
    + +

    _main_clock (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008)) + +

    _main_cpp_init (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A)) + +

    _main_init (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B)) + +

    __rt_final_cpp (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D)) + +

    __rt_final_exit (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F)) + +

    Reset_Handler (Thumb, 28 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +
    [Address Reference Count : 1]

    • startup_armcm0.o(RESET) +
    +

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   NMI_Handler +
    +
    [Called By]
    • >>   NMI_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   SVC_Handler +
    +
    [Called By]
    • >>   SVC_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   PendSV_Handler +
    +
    [Called By]
    • >>   PendSV_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    FLSCTRL_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   FLSCTRL_IRQn_Handler +
    +
    [Called By]
    • >>   FLSCTRL_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    WDG_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   WDG_IRQn_Handler +
    +
    [Called By]
    • >>   WDG_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    I2C0_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   I2C0_IRQn_Handler +
    +
    [Called By]
    • >>   I2C0_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    I2C1_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   I2C1_IRQn_Handler +
    +
    [Called By]
    • >>   I2C1_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    SPIS_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   SPIS_IRQn_Handler +
    +
    [Called By]
    • >>   SPIS_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    SPIM_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   SPIM_IRQn_Handler +
    +
    [Called By]
    • >>   SPIM_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    I2C2_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   I2C2_IRQn_Handler +
    +
    [Called By]
    • >>   I2C2_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    OTP_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   OTP_IRQn_Handler +
    +
    [Called By]
    • >>   OTP_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    PVD_IRQn_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text)) +

    [Calls]

    • >>   PVD_IRQn_Handler +
    +
    [Called By]
    • >>   PVD_IRQn_Handler +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    __aeabi_uidiv (Thumb, 0 bytes, Stack size 12 bytes, uidiv.o(.text), UNUSED) + +

    __aeabi_uidivmod (Thumb, 44 bytes, Stack size 12 bytes, uidiv.o(.text)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = __aeabi_uidivmod +
    +
    [Called By]
    • >>   drv_dsi_tx_phy_test_setup +
    • >>   hal_lcdc_upscaler_config +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_timing_info_update +
    • >>   hal_dsi_tx_init_dpi_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   drv_dsi_rx_set_up_phy +
    • >>   drv_crgu_get_rxbr_clk +
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    • >>   hal_swire_init +
    • >>   hal_dsi_rx_ctrl_init +
    • >>   svs_wait_fr_stab +
    • >>   svs_get_rel_intv +
    • >>   svs_direct_mode_setting +
    • >>   hal_intl_fb_edge_resize +
    • >>   hal_intl_fb_check_bandwidth +
    • >>   ha_intl_fb_check_pu_size +
    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_vsync_reset_lcdc_scaler +
    • >>   drv_timer_set_compare_val +
    • >>   hal_internal_vsync_set_tear_mode +
    • >>   __aeabi_idivmod +
    • >>   drv_uart_set_baud_rate +
    • >>   _printf_core +
    + +

    __aeabi_idiv (Thumb, 0 bytes, Stack size 16 bytes, idiv.o(.text), UNUSED) + +

    __aeabi_idivmod (Thumb, 40 bytes, Stack size 16 bytes, idiv.o(.text)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = __aeabi_idivmod ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   ap_dcs_set_backlight +
    • >>   hal_internal_vsync_set_tear_mode +
    + +

    __aeabi_memcpy (Thumb, 36 bytes, Stack size 0 bytes, memcpya.o(.text)) +

    [Called By]

    • >>   hal_intl_fb_cal_fb_info +
    • >>   tau_log_push_log +
    + +

    __aeabi_memcpy4 (Thumb, 0 bytes, Stack size 0 bytes, memcpya.o(.text)) +

    [Called By]

    • >>   hal_dsi_tx_init_dpi_timing +
    • >>   hal_intl_fb_get_rx_fb_info +
    • >>   hal_internal_vsync_init_rx +
    • >>   hal_internal_sync_input_resolution_change +
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_intl_fb_cal_fb_info +
    • >>   hal_intl_fb_get_tx_fb_info +
    • >>   hal_internal_vsync_init_tx +
    + +

    __aeabi_memcpy8 (Thumb, 0 bytes, Stack size 0 bytes, memcpya.o(.text), UNUSED) + +

    __aeabi_memset (Thumb, 14 bytes, Stack size 0 bytes, memseta.o(.text)) +

    [Called By]

    • >>   hal_intl_dcs_set_auto_hw_filter +
    • >>   _memset$wrapper +
    • >>   __aeabi_memclr +
    + +

    __aeabi_memset4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED) + +

    __aeabi_memset8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED) + +

    __aeabi_memclr (Thumb, 4 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_memset +
    + +

    __aeabi_memclr4 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    • >>   hal_dsi_tx_ctrl_deinit +
    • >>   hal_dsi_tx_ctrl_create_handle +
    • >>   hal_dsi_rx_ctrl_create_handle +
    • >>   tau_log_printf +
    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_intl_svs_init_rx +
    • >>   hal_intl_fb_cal_fb_info +
    • >>   hal_internal_vsync_deinit +
    • >>   soft_pro_motion_init +
    • >>   drv_uart_trans_create_handle +
    • >>   hal_uart_init +
    • >>   hal_internal_vsync_init_tx +
    + +

    __aeabi_memclr8 (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED) + +

    _memset$wrapper (Thumb, 18 bytes, Stack size 8 bytes, memseta.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_memset +
    + +

    strlen (Thumb, 14 bytes, Stack size 0 bytes, strlen.o(.text)) +

    [Called By]

    • >>   tau_log_printf +
    + +

    memcmp (Thumb, 26 bytes, Stack size 12 bytes, memcmp.o(.text)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = memcmp +
    +
    [Called By]
    • >>   hal_intl_dcs_rx_receive_pps +
    + +

    __aeabi_fadd (Thumb, 162 bytes, Stack size 24 bytes, fadd.o(.text)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = __aeabi_fadd ⇒ _float_epilogue +
    +
    [Calls]
    • >>   _float_round +
    • >>   _float_epilogue +
    +
    [Called By]
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   __aeabi_fsub +
    • >>   __aeabi_frsub +
    + +

    __aeabi_fsub (Thumb, 8 bytes, Stack size 0 bytes, fadd.o(.text)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = __aeabi_fsub ⇒ __aeabi_fadd ⇒ _float_epilogue +
    +
    [Calls]
    • >>   __aeabi_fadd +
    +
    [Called By]
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    + +

    __aeabi_frsub (Thumb, 8 bytes, Stack size 0 bytes, fadd.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_fadd +
    + +

    __aeabi_fmul (Thumb, 122 bytes, Stack size 16 bytes, fmul.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_fmul +
    +
    [Called By]
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   svs_wait_start +
    • >>   svs_wait_fr_stab +
    • >>   svs_sync_handle +
    + +

    __aeabi_fdiv (Thumb, 124 bytes, Stack size 16 bytes, fdiv.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_fdiv +
    +
    [Calls]
    • >>   _float_round +
    +
    [Called By]
    • >>   hal_lcdc_init_clk +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   svs_wait_start +
    • >>   svs_sync_handle +
    + +

    __ARM_scalbnf (Thumb, 24 bytes, Stack size 0 bytes, fscalb.o(.text)) +

    [Called By]

    • >>   hal_lcdc_init_clk +
    + +

    scalbnf (Thumb, 0 bytes, Stack size 0 bytes, fscalb.o(.text), UNUSED) + +

    __aeabi_dadd (Thumb, 328 bytes, Stack size 48 bytes, dadd.o(.text)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_lasr +
    • >>   __aeabi_llsl +
    • >>   _double_round +
    • >>   _double_epilogue +
    +
    [Called By]
    • >>   hal_lcdc_upscaler_config +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   svs_sync_handle +
    • >>   hal_vsync_reset_lcdc_scaler +
    • >>   __aeabi_drsub +
    • >>   ceil +
    • >>   __aeabi_dsub +
    • >>   _fp_digits +
    + +

    __aeabi_dsub (Thumb, 12 bytes, Stack size 8 bytes, dadd.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_dadd +
    + +

    __aeabi_drsub (Thumb, 12 bytes, Stack size 8 bytes, dadd.o(.text)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_dadd +
    +
    [Called By]
    • >>   ceil +
    + +

    __aeabi_dmul (Thumb, 202 bytes, Stack size 72 bytes, dmul.o(.text)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   _double_epilogue +
    +
    [Called By]
    • >>   hal_intl_svs_update_rxbr_clk +
    • >>   _fp_digits +
    + +

    __aeabi_ui2f (Thumb, 14 bytes, Stack size 8 bytes, ffltui.o(.text)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = __aeabi_ui2f ⇒ _float_epilogue +
    +
    [Calls]
    • >>   _float_epilogue +
    +
    [Called By]
    • >>   hal_lcdc_init_clk +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   svs_wait_start +
    • >>   svs_wait_fr_stab +
    • >>   svs_sync_handle +
    + +

    __aeabi_ui2d (Thumb, 24 bytes, Stack size 16 bytes, dfltui.o(.text)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = __aeabi_ui2d ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   _double_epilogue +
    +
    [Called By]
    • >>   hal_lcdc_upscaler_config +
    • >>   hal_intl_svs_update_rxbr_clk +
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   hal_vsync_reset_lcdc_scaler +
    + +

    __aeabi_f2uiz (Thumb, 40 bytes, Stack size 0 bytes, ffixui.o(.text)) +

    [Called By]

    • >>   svs_wait_fr_stab +
    + +

    __aeabi_d2uiz (Thumb, 50 bytes, Stack size 8 bytes, dfixui.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_d2uiz ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_llsr +
    +
    [Called By]
    • >>   hal_lcdc_upscaler_config +
    • >>   hal_lcdc_init_clk +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   hal_intl_svs_update_rxbr_clk +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   svs_wait_start +
    • >>   svs_sync_handle +
    • >>   hal_vsync_reset_lcdc_scaler +
    + +

    __aeabi_f2d (Thumb, 40 bytes, Stack size 0 bytes, f2d.o(.text)) +

    [Called By]

    • >>   hal_lcdc_init_clk +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    • >>   svs_wait_start +
    • >>   svs_sync_handle +
    + +

    __aeabi_d2f (Thumb, 56 bytes, Stack size 8 bytes, d2f.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_d2f +
    +
    [Calls]
    • >>   _float_round +
    +
    [Called By]
    • >>   hal_dsi_tx_timing_info_update +
    + +

    __aeabi_cfcmpeq (Thumb, 0 bytes, Stack size 0 bytes, cfcmple.o(.text), UNUSED) + +

    __aeabi_cfcmple (Thumb, 20 bytes, Stack size 0 bytes, cfcmple.o(.text)) +

    [Called By]

    • >>   hal_tx_frame_rate_adjust +
    + +

    __aeabi_cfrcmple (Thumb, 20 bytes, Stack size 0 bytes, cfrcmple.o(.text)) +

    [Called By]

    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    + +

    __aeabi_uldivmod (Thumb, 96 bytes, Stack size 48 bytes, uldiv.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_llsr +
    • >>   __aeabi_llsl +
    +
    [Called By]
    • >>   _printf_core +
    • >>   _fp_digits +
    + +

    __aeabi_llsl (Thumb, 32 bytes, Stack size 8 bytes, llshl.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_llsl +
    +
    [Called By]
    • >>   __aeabi_dadd +
    • >>   __aeabi_uldivmod +
    • >>   _double_epilogue +
    • >>   __aeabi_d2ulz +
    + +

    _ll_shift_l (Thumb, 0 bytes, Stack size 8 bytes, llshl.o(.text), UNUSED) + +

    __aeabi_llsr (Thumb, 34 bytes, Stack size 8 bytes, llushr.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_llsr +
    +
    [Called By]
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_uldivmod +
    • >>   _double_epilogue +
    • >>   __aeabi_d2ulz +
    + +

    _ll_ushift_r (Thumb, 0 bytes, Stack size 8 bytes, llushr.o(.text), UNUSED) + +

    __aeabi_lasr (Thumb, 38 bytes, Stack size 8 bytes, llsshr.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_lasr +
    +
    [Called By]
    • >>   __aeabi_dadd +
    + +

    _ll_sshift_r (Thumb, 0 bytes, Stack size 8 bytes, llsshr.o(.text), UNUSED) + +

    __I$use$fp (Thumb, 0 bytes, Stack size 0 bytes, iusefp.o(.text), UNUSED) + +

    _float_round (Thumb, 16 bytes, Stack size 0 bytes, fepilogue.o(.text)) +

    [Called By]

    • >>   __aeabi_fadd +
    • >>   __aeabi_d2f +
    • >>   __aeabi_fdiv +
    + +

    _float_epilogue (Thumb, 114 bytes, Stack size 12 bytes, fepilogue.o(.text)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = _float_epilogue +
    +
    [Called By]
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fadd +
    + +

    _double_round (Thumb, 26 bytes, Stack size 8 bytes, depilogue.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = _double_round +
    +
    [Called By]
    • >>   __aeabi_dadd +
    • >>   _double_epilogue +
    • >>   __aeabi_ddiv +
    + +

    _double_epilogue (Thumb, 164 bytes, Stack size 48 bytes, depilogue.o(.text)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __ARM_clz +
    • >>   __aeabi_llsr +
    • >>   __aeabi_llsl +
    • >>   _double_round +
    +
    [Called By]
    • >>   __aeabi_ui2d +
    • >>   __aeabi_dadd +
    • >>   __aeabi_dmul +
    + +

    __aeabi_ddiv (Thumb, 234 bytes, Stack size 40 bytes, ddiv.o(.text), UNUSED) +

    [Calls]

    • >>   _double_round +
    +
    [Called By]
    • >>   _fp_digits +
    + +

    __aeabi_d2ulz (Thumb, 54 bytes, Stack size 8 bytes, dfixul.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_llsr +
    • >>   __aeabi_llsl +
    +
    [Called By]
    • >>   _fp_digits +
    + +

    __aeabi_cdrcmple (Thumb, 38 bytes, Stack size 0 bytes, cdrcmple.o(.text)) +

    [Called By]

    • >>   ceil +
    • >>   _fp_digits +
    + +

    __scatterload (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text)) +

    [Calls]

    • >>   __main_after_scatterload +
    +
    [Called By]
    • >>   _main_scatterload +
    + +

    __scatterload_rt2 (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED) + +

    __decompress (Thumb, 0 bytes, Stack size unknown bytes, __dczerorl2.o(.text), UNUSED) + +

    __decompress1 (Thumb, 86 bytes, Stack size unknown bytes, __dczerorl2.o(.text), UNUSED) + +

    AP_NRESET_IRQn_Handler (Thumb, 22 bytes, Stack size 8 bytes, drv_gpio.o(i.AP_NRESET_IRQn_Handler)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = AP_NRESET_IRQn_Handler ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    DMA_IRQn_Handler (Thumb, 78 bytes, Stack size 24 bytes, drv_dma.o(i.DMA_IRQn_Handler)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = DMA_IRQn_Handler ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    • >>   drv_dma_clear_status +
    • >>   drv_dma_get_int_source +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT0_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT0_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT0_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT1_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT1_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT1_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT2_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT2_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT2_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT3_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT3_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT3_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT4_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT4_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT4_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT5_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT5_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT5_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT6_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT6_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT6_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    EXTI_INT7_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_gpio.o(i.EXTI_INT7_IRQn_Handler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = EXTI_INT7_IRQn_Handler ⇒ drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_gpio_handle_int +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    HardFault_Handler (Thumb, 14 bytes, Stack size 0 bytes, drv_common.o(i.HardFault_Handler)) +

    [Stack]

    • Max Depth = 336
    • Call Chain = HardFault_Handler ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    LCDC_IRQn_Handler (Thumb, 118 bytes, Stack size 24 bytes, hal_internal_vsync.o(i.LCDC_IRQn_Handler)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = LCDC_IRQn_Handler ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    MEMC_IRQn_Handler (Thumb, 154 bytes, Stack size 8 bytes, drv_memc.o(i.MEMC_IRQn_Handler)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = MEMC_IRQn_Handler ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    • >>   drv_memc_get_status +
    • >>   drv_memc_clear_status +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    MIPI_TX_IRQn_Handler (Thumb, 70 bytes, Stack size 24 bytes, drv_dsi_tx.o(i.MIPI_TX_IRQn_Handler)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = MIPI_TX_IRQn_Handler ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    SWIRE_IRQn_Handler (Thumb, 38 bytes, Stack size 8 bytes, drv_swire.o(i.SWIRE_IRQn_Handler)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = SWIRE_IRQn_Handler ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    SysTick_Handler (Thumb, 20 bytes, Stack size 0 bytes, drv_common.o(i.SysTick_Handler)) +
    [Address Reference Count : 1]

    • startup_armcm0.o(RESET) +
    +

    TIMER0_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_timer.o(i.TIMER0_IRQn_Handler)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = TIMER0_IRQn_Handler ⇒ drv_timer_handle_interrupt ⇒ drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_timer_handle_interrupt +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    TIMER1_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_timer.o(i.TIMER1_IRQn_Handler)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = TIMER1_IRQn_Handler ⇒ drv_timer_handle_interrupt ⇒ drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_timer_handle_interrupt +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    TIMER2_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_timer.o(i.TIMER2_IRQn_Handler)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = TIMER2_IRQn_Handler ⇒ drv_timer_handle_interrupt ⇒ drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_timer_handle_interrupt +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    TIMER3_IRQn_Handler (Thumb, 10 bytes, Stack size 8 bytes, drv_timer.o(i.TIMER3_IRQn_Handler)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = TIMER3_IRQn_Handler ⇒ drv_timer_handle_interrupt ⇒ drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_timer_handle_interrupt +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    VIDC_IRQn_Handler (Thumb, 22 bytes, Stack size 8 bytes, drv_vidc.o(i.VIDC_IRQn_Handler)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = VIDC_IRQn_Handler ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    VPRE1_IRQn_Handler (Thumb, 22 bytes, Stack size 8 bytes, drv_rxbr.o(i.VPRE1_IRQn_Handler)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = VPRE1_IRQn_Handler ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    VPRE_IRQn_Handler (Thumb, 104 bytes, Stack size 8 bytes, hal_internal_dcs.o(i.VPRE_IRQn_Handler)) +

    [Stack]

    • Max Depth = 536
    • Call Chain = VPRE_IRQn_Handler ⇒ hal_intl_dcs_rx_receive_packet ⇒ hal_intl_dcs_rx_receive_pps ⇒ drv_dsc_dec_enable ⇒ drv_se_set_dsc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_crgu_set_dsc_clk +
    • >>   drv_dsc_dec_get_nslc +
    • >>   hal_intl_dcs_rx_receive_packet +
    • >>   drv_rxbr_get_status0 +
    • >>   drv_rxbr_clear_status0 +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    __0printf (Thumb, 24 bytes, Stack size 24 bytes, printfa.o(i.__0printf), UNUSED) +

    [Calls]

    • >>   _printf_core +
    + +

    __1printf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0printf), UNUSED) + +

    __2printf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0printf)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = __2printf +
    +
    [Called By]
    • >>   tau_log_printf +
    + +

    __c89printf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0printf), UNUSED) + +

    printf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0printf), UNUSED) + +

    __0vsprintf (Thumb, 30 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf), UNUSED) +

    [Calls]

    • >>   _sputc +
    • >>   _printf_core +
    + +

    __1vsprintf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf), UNUSED) + +

    __2vsprintf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf), UNUSED) + +

    __c89vsprintf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf), UNUSED) + +

    vsprintf (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = vsprintf +
    +
    [Called By]
    • >>   tau_log_printf +
    + +

    __ARM_clz (Thumb, 46 bytes, Stack size 0 bytes, depilogue.o(i.__ARM_clz)) +

    [Called By]

    • >>   _double_epilogue +
    + +

    __ARM_common_switch8 (Thumb, 26 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.__ARM_common_switch8)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __ARM_common_switch8 +
    +
    [Called By]
    • >>   drv_dsi_tx_phy_status_stopstate +
    • >>   hal_dsi_rx_ctrl_init_memc +
    • >>   drv_dsi_rx_get_color_bpp +
    + +

    __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED) + +

    MIPI_RX_IRQn_Handler (Thumb, 354 bytes, Stack size 24 bytes, drv_dsi_rx.o(i.MIPI_RX_IRQn_Handler)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = MIPI_RX_IRQn_Handler ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    UART_IRQn_Handler (Thumb, 364 bytes, Stack size 32 bytes, drv_uart.o(i.UART_IRQn_Handler)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = UART_IRQn_Handler ⇒ drv_uart_abort_send ⇒ drv_uart_reset_tx_fifo ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    • >>   drv_uart_config_int +
    • >>   drv_uart_abort_send +
    • >>   drv_uart_abort_recv +
    • >>   drv_uart_int_trans_handle +
    +
    [Address Reference Count : 1]
    • startup_armcm0.o(RESET) +
    +

    __scatterload_copy (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED) + +

    __scatterload_zeroinit (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED) + +

    app_display_init (Thumb, 44 bytes, Stack size 8 bytes, p8p_demo.o(i.app_display_init)) +

    [Stack]

    • Max Depth = 640
    • Call Chain = app_display_init ⇒ app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_swire_set_timer +
    • >>   hal_swire_init +
    • >>   hal_pwr_get_vcc_power_ready +
    • >>   app_gpio_init +
    • >>   app_mipi_tx_start +
    • >>   app_mipi_tx_init +
    • >>   app_mipi_rx_init +
    +
    [Called By]
    • >>   app_system_resume +
    • >>   google_p8p_demo +
    + +

    app_gpio_init (Thumb, 22 bytes, Stack size 24 bytes, p8p_demo.o(i.app_gpio_init)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = app_gpio_init ⇒ hal_gpio_config_pad ⇒ hal_gpio_init_output ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   hal_gpio_config_pad +
    +
    [Called By]
    • >>   app_display_init +
    + +

    board_Init (Thumb, 20 bytes, Stack size 8 bytes, board.o(i.board_Init)) +

    [Stack]

    • Max Depth = 140
    • Call Chain = board_Init ⇒ tau_log_init ⇒ hal_uart_init ⇒ drv_uart_init ⇒ drv_uart_set_baud_rate ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   tau_log_init +
    • >>   hal_system_init +
    +
    [Called By]
    • >>   main +
    + +

    ceil (Thumb, 180 bytes, Stack size 24 bytes, ceil.o(i.ceil)) +

    [Stack]

    • Max Depth = 136
    • Call Chain = ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_dadd +
    • >>   __aeabi_drsub +
    • >>   __aeabi_cdrcmple +
    +
    [Called By]
    • >>   hal_lcdc_init_clk +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   svs_wait_start +
    + +

    dcs_packet_fifo_alloc (Thumb, 80 bytes, Stack size 12 bytes, dcs_packet_fifo.o(i.dcs_packet_fifo_alloc)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = dcs_packet_fifo_alloc +
    +
    [Called By]
    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    + +

    dcs_packet_fifo_init (Thumb, 18 bytes, Stack size 0 bytes, dcs_packet_fifo.o(i.dcs_packet_fifo_init)) +

    [Called By]

    • >>   hal_internal_vsync_init_rx +
    + +

    dcs_packet_free_fifo_header (Thumb, 60 bytes, Stack size 0 bytes, dcs_packet_fifo.o(i.dcs_packet_free_fifo_header)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_dcs_async_handler +
    + +

    dcs_packet_get_fifo_header (Thumb, 26 bytes, Stack size 0 bytes, dcs_packet_fifo.o(i.dcs_packet_get_fifo_header)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_dcs_async_handler +
    + +

    delayMs (Thumb, 24 bytes, Stack size 8 bytes, tau_delay.o(i.delayMs)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = delayMs ⇒ delayUs +
    +
    [Calls]
    • >>   delayUs +
    +
    [Called By]
    • >>   app_tx_panel_reset +
    • >>   app_mipi_tx_start +
    • >>   app_init_panel +
    • >>   ap_dcs_set_enter_sleep_mode +
    + +

    delayUs (Thumb, 40 bytes, Stack size 8 bytes, tau_delay.o(i.delayUs)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = delayUs +
    +
    [Called By]
    • >>   hal_internal_sync_input_resolution_change +
    • >>   delayMs +
    • >>   send_panel_init_code +
    • >>   tau_log_push_log +
    + +

    drv_common_system_init (Thumb, 8 bytes, Stack size 8 bytes, drv_common.o(i.drv_common_system_init)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = drv_common_system_init ⇒ drv_se_init ⇒ drv_efuse_read +
    +
    [Calls]
    • >>   drv_se_init +
    +
    [Called By]
    • >>   hal_system_init +
    + +

    drv_crgu_enable_clock (Thumb, 54 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_enable_clock)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_init_clk +
    • >>   hal_dsi_rx_ctrl_init_clk +
    • >>   hal_system_init +
    • >>   hal_timer_init +
    • >>   hal_swire_init +
    • >>   hal_swire_deinit +
    • >>   hal_dsi_tx_ctrl_deinit +
    • >>   hal_dsi_rx_ctrl_deinit +
    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_timer_deinit +
    • >>   drv_uart_enable_clk +
    • >>   drv_efuse_enter_inactive +
    + +

    drv_crgu_get_rxbr_clk (Thumb, 70 bytes, Stack size 8 bytes, drv_crgu.o(i.drv_crgu_get_rxbr_clk)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = drv_crgu_get_rxbr_clk ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_intl_svs_update_rxbr_clk +
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    • >>   svs_wait_start +
    + +

    drv_crgu_reset_modules (Thumb, 10 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_reset_modules)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_deinit +
    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    drv_crgu_set_ahb_clk (Thumb, 34 bytes, Stack size 8 bytes, drv_crgu.o(i.drv_crgu_set_ahb_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_crgu_set_ahb_clk +
    +
    [Called By]
    • >>   hal_system_updata_sysclk +
    + +

    drv_crgu_set_clock_div (Thumb, 12 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_clock_div)) +

    [Called By]

    • >>   hal_swire_init +
    + +

    drv_crgu_set_dpi_clk (Thumb, 54 bytes, Stack size 12 bytes, drv_crgu.o(i.drv_crgu_set_dpi_clk)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_crgu_set_dpi_clk +
    +
    [Called By]
    • >>   hal_dsi_tx_init_dpi_timing +
    + +

    drv_crgu_set_dsc_clk (Thumb, 52 bytes, Stack size 12 bytes, drv_crgu.o(i.drv_crgu_set_dsc_clk)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_crgu_set_dsc_clk +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_clk +
    • >>   VPRE_IRQn_Handler +
    + +

    drv_crgu_set_fb_clk (Thumb, 34 bytes, Stack size 8 bytes, drv_crgu.o(i.drv_crgu_set_fb_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_crgu_set_fb_clk +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_clk +
    + +

    drv_crgu_set_lcdc_clk (Thumb, 36 bytes, Stack size 8 bytes, drv_crgu.o(i.drv_crgu_set_lcdc_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_crgu_set_lcdc_clk +
    +
    [Called By]
    • >>   hal_lcdc_init_clk +
    + +

    drv_crgu_set_reset (Thumb, 20 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_reset)) +

    [Called By]

    • >>   hal_swire_deinit +
    • >>   hal_dsi_rx_ctrl_deinit +
    • >>   vpre_err_reset +
    • >>   hal_timer_deinit +
    + +

    drv_crgu_set_rxbr_clk (Thumb, 34 bytes, Stack size 8 bytes, drv_crgu.o(i.drv_crgu_set_rxbr_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_crgu_set_rxbr_clk +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_clk +
    + +

    drv_crgu_set_vidc_clk (Thumb, 36 bytes, Stack size 8 bytes, drv_crgu.o(i.drv_crgu_set_vidc_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_crgu_set_vidc_clk +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_clk +
    + +

    drv_dma_clear_status (Thumb, 20 bytes, Stack size 0 bytes, drv_dma.o(i.drv_dma_clear_status)) +

    [Called By]

    • >>   DMA_IRQn_Handler +
    + +

    drv_dsc_dec_disable (Thumb, 20 bytes, Stack size 0 bytes, drv_dsc_dec.o(i.drv_dsc_dec_disable)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    drv_dsc_dec_enable (Thumb, 44 bytes, Stack size 8 bytes, drv_dsc_dec.o(i.drv_dsc_dec_enable)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = drv_dsc_dec_enable ⇒ drv_se_set_dsc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_dsc +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    • >>   hal_intl_dcs_rx_receive_pps +
    + +

    drv_dsc_dec_get_nslc (Thumb, 22 bytes, Stack size 0 bytes, drv_dsc_dec.o(i.drv_dsc_dec_get_nslc)) +

    [Called By]

    • >>   VPRE_IRQn_Handler +
    + +

    drv_dsc_dec_set_irqen (Thumb, 24 bytes, Stack size 0 bytes, drv_dsc_dec.o(i.drv_dsc_dec_set_irqen)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init +
    + +

    drv_dsi_rx_calc_ipi_tx_delay (Thumb, 252 bytes, Stack size 56 bytes, drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay)) +

    [Stack]

    • Max Depth = 160
    • Call Chain = drv_dsi_rx_calc_ipi_tx_delay ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fmul +
    • >>   __aeabi_fadd +
    • >>   __aeabi_f2d +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_dadd +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_fsub +
    • >>   __aeabi_cfrcmple +
    • >>   drv_dsi_rx_get_color_pcc +
    • >>   drv_dsi_rx_get_color_bpp +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_set_ipi_cfg +
    + +

    drv_dsi_rx_enable_irq (Thumb, 58 bytes, Stack size 8 bytes, drv_dsi_rx.o(i.drv_dsi_rx_enable_irq)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_dsi_rx_enable_irq ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    drv_dsi_rx_get_compression_en (Thumb, 10 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en)) +

    [Called By]

    • >>   hal_intl_dcs_rx_receive_pps +
    + +

    drv_dsi_rx_get_ddi_crc_en (Thumb, 10 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_ddi_crc_en)) +

    [Called By]

    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    + +

    drv_dsi_rx_get_max_ret_size (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_max_ret_size)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_get_max_ret_size +
    + +

    drv_dsi_rx_power_up (Thumb, 14 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_power_up)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_start +
    + +

    drv_dsi_rx_set_check_crc (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_check_crc)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_ctrl_cfg (Thumb, 32 bytes, Stack size 12 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_ctrl_cfg)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_dsi_rx_set_ctrl_cfg +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_ddi_cfg (Thumb, 10 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_ddi_crc_en (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_crc_en)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_inten (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_inten)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_ipi_cfg (Thumb, 12 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_cfg)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_set_ipi_cfg +
    + +

    drv_dsi_rx_set_ipi_ycbcr_frmt (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_ycbcr_frmt)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_lane_swap (Thumb, 16 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_lane_swap)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_resp_cnt (Thumb, 32 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_resp_cnt)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_tear_resp_en (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_tear_resp_en)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_set_up_phy (Thumb, 224 bytes, Stack size 32 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = drv_dsi_rx_set_up_phy ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    • >>   drv_phy_test_lock +
    • >>   drv_phy_test_clear +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    drv_dsi_rx_shut_down (Thumb, 14 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_shut_down)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_stop +
    + +

    drv_dsi_tx_command_header (Thumb, 18 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_command_header)) +

    [Called By]

    • >>   hal_dsi_tx_send_cmd +
    + +

    drv_dsi_tx_command_mode_cfg (Thumb, 82 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_dsi_tx_command_put_payload (Thumb, 6 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_tx_ctrl_write_array_cmd +
    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    + +

    drv_dsi_tx_config_eotp (Thumb, 26 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_config_eotp)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_dsi_tx_config_int (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_config_int)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_dpi_lpcmd_time (Thumb, 10 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_dpi_lpcmd_time)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_dpi_mode (Thumb, 12 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_dpi_mode)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_dpi_polarity (Thumb, 32 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_dpi_polarity)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_edpi_cmd_size (Thumb, 6 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_edpi_cmd_size)) +

    [Called By]

    • >>   hal_dsi_tx_init_timing +
    + +

    drv_dsi_tx_get_cmd_status (Thumb, 6 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status)) +

    [Called By]

    • >>   hal_dsi_tx_send_cmd +
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_tx_ctrl_write_array_cmd +
    + +

    drv_dsi_tx_mode (Thumb, 6 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_mode)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_dsi_tx_phy_clock_lane_auto_lp (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_dsi_tx_phy_clock_lane_req_hs (Thumb, 26 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    • >>   rxbr_irq1_callback +
    + +

    drv_dsi_tx_phy_lane_mode (Thumb, 12 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_lane_mode)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_phy_status_ready (Thumb, 100 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_init +
    + +

    drv_dsi_tx_phy_status_stopstate (Thumb, 62 bytes, Stack size 4 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   __ARM_common_switch8 +
    +
    [Called By]
    • >>   hal_dsi_tx_send_cmd +
    + +

    drv_dsi_tx_phy_test_setup (Thumb, 314 bytes, Stack size 32 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = drv_dsi_tx_phy_test_setup ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    • >>   drv_tx_phy_test_write_code +
    • >>   drv_tx_phy_test_exit +
    • >>   drv_tx_phy_test_enter +
    • >>   drv_phy_test_clear +
    +
    [Called By]
    • >>   hal_dsi_tx_init_phy_cfg +
    + +

    drv_dsi_tx_phy_time_cfg (Thumb, 28 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg)) +

    [Called By]

    • >>   hal_dsi_tx_init_phy_cfg +
    + +

    drv_dsi_tx_powerup (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_powerup)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_start +
    • >>   hal_dsi_tx_ctrl_init +
    + +

    drv_dsi_tx_response_mode (Thumb, 30 bytes, Stack size 12 bytes, drv_dsi_tx.o(i.drv_dsi_tx_response_mode)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_dsi_tx_response_mode +
    +
    [Called By]
    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_set_bta_ack (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_bta_ack)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_set_esc_div (Thumb, 14 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_set_int (Thumb, 58 bytes, Stack size 8 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_int)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_dsi_tx_set_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   hal_dsi_tx_init_cfg +
    • >>   hal_dsi_tx_ctrl_stop +
    + +

    drv_dsi_tx_set_time_out_div (Thumb, 18 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_time_out_div)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_set_video_chunk (Thumb, 14 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_video_chunk)) +

    [Called By]

    • >>   hal_dsi_tx_init_vid_timing +
    + +

    drv_dsi_tx_set_video_timing (Thumb, 30 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_video_timing)) +

    [Called By]

    • >>   hal_dsi_tx_init_vid_timing +
    + +

    drv_dsi_tx_shutdown (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_shutdown)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_stop +
    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_dsi_tx_timeout_cfg (Thumb, 38 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_timeout_cfg)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_dsi_tx_video_mode_cfg (Thumb, 226 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_video_mode_cfg)) +

    [Called By]

    • >>   hal_dsi_tx_init_cfg +
    + +

    drv_efuse_enter_inactive (Thumb, 54 bytes, Stack size 8 bytes, drv_efuse.o(i.drv_efuse_enter_inactive)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_efuse_enter_inactive +
    +
    [Calls]
    • >>   drv_crgu_enable_clock +
    • >>   drv_efuse_int_enable +
    +
    [Called By]
    • >>   drv_se_init +
    + +

    drv_efuse_int_enable (Thumb, 12 bytes, Stack size 0 bytes, drv_efuse.o(i.drv_efuse_int_enable)) +

    [Called By]

    • >>   drv_efuse_enter_inactive +
    + +

    drv_efuse_read (Thumb, 58 bytes, Stack size 16 bytes, drv_efuse.o(i.drv_efuse_read)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_efuse_read +
    +
    [Calls]
    • >>   drv_pwr_efuse_pd +
    • >>   drv_efuse_read_req +
    +
    [Called By]
    • >>   drv_se_init +
    + +

    drv_efuse_read_req (Thumb, 24 bytes, Stack size 0 bytes, drv_efuse.o(i.drv_efuse_read_req)) +

    [Called By]

    • >>   drv_efuse_read +
    + +

    drv_gpio_register_ap_reset_callback (Thumb, 6 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_register_ap_reset_callback)) +

    [Called By]

    • >>   hal_gpio_set_ap_reset_int +
    + +

    drv_gpio_register_callback (Thumb, 14 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_register_callback)) +

    [Called By]

    • >>   hal_gpio_reg_eint_cb +
    + +

    drv_gpio_set_int (Thumb, 62 bytes, Stack size 16 bytes, drv_gpio.o(i.drv_gpio_set_int)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_gpio_set_int +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    +
    [Called By]
    • >>   hal_gpio_ctrl_eint +
    + +

    drv_gpio_set_ioe (Thumb, 26 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_set_ioe)) +

    [Called By]

    • >>   hal_gpio_init_output +
    • >>   hal_gpio_init_input +
    • >>   hal_gpio_init_eint +
    + +

    drv_gpio_set_mode (Thumb, 16 bytes, Stack size 8 bytes, drv_gpio.o(i.drv_gpio_set_mode)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_gpio_set_mode +
    +
    [Called By]
    • >>   hal_gpio_set_mode +
    + +

    drv_lcdc_bcsa_config (Thumb, 30 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_bcsa_config)) +

    [Called By]

    • >>   hal_nonshadow_func_update +
    • >>   hal_lcdc_postproc_config +
    + +

    drv_lcdc_cfg_int_frame (Thumb, 34 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_cfg_int_frame)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_lcdc_cmd_start (Thumb, 46 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_cmd_start)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = drv_lcdc_cmd_start ⇒ drv_se_set_lcdc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_lcdc +
    +
    [Called By]
    • >>   hal_lcdc_start +
    • >>   rxbr_irq1_callback +
    + +

    drv_lcdc_config_acc_command_mode (Thumb, 14 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_acc_command_mode)) +

    [Called By]

    • >>   hal_internal_vsync_set_tear_mode +
    + +

    drv_lcdc_config_int (Thumb, 50 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_int)) +

    [Called By]

    • >>   hal_lcdc_init_cfg +
    + +

    drv_lcdc_config_int_single (Thumb, 34 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_config_int_single)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_lcdc_config_int_single +
    +
    [Called By]
    • >>   hal_vsync_func_update +
    • >>   hal_nonshadow_func_update +
    • >>   hal_internal_vsync_set_tear_mode +
    + +

    drv_lcdc_config_overwrite_rgb (Thumb, 18 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_overwrite_rgb)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_set_overwrite_rgb +
    + +

    drv_lcdc_config_src_parameter (Thumb, 72 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_src_parameter)) +

    [Called By]

    • >>   hal_lcdc_timinggen_config +
    + +

    drv_lcdc_crop_hact (Thumb, 10 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_crop_hact)) +

    [Called By]

    • >>   hal_lcdc_displayproc_config +
    + +

    drv_lcdc_ctrl_flow (Thumb, 50 bytes, Stack size 16 bytes, drv_lcdc.o(i.drv_lcdc_ctrl_flow)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_lcdc_ctrl_flow +
    +
    [Calls]
    • >>   drv_lcdc_function_enable +
    +
    [Called By]
    • >>   hal_lcdc_timinggen_config +
    + +

    drv_lcdc_dith_config (Thumb, 40 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_dith_config)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_lcdc_dith_config +
    +
    [Called By]
    • >>   hal_lcdc_postproc_config +
    + +

    drv_lcdc_edge_dect_config (Thumb, 50 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_edge_dect_config)) +

    [Called By]

    • >>   hal_nonshadow_func_update +
    • >>   hal_lcdc_postproc_config +
    + +

    drv_lcdc_edge_enh_config (Thumb, 86 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_edge_enh_config)) +

    [Called By]

    • >>   hal_nonshadow_func_update +
    • >>   hal_lcdc_postproc_config +
    + +

    drv_lcdc_enable_shadow_reg (Thumb, 32 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_enable_shadow_reg)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_start +
    + +

    drv_lcdc_endianness_config (Thumb, 24 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_endianness_config)) +

    [Called By]

    • >>   hal_lcdc_displayproc_config +
    + +

    drv_lcdc_fc_config (Thumb, 24 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_fc_config)) +

    [Called By]

    • >>   hal_nonshadow_func_update +
    • >>   hal_lcdc_postproc_config +
    + +

    drv_lcdc_fldc_config (Thumb, 32 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_fldc_config)) +

    [Called By]

    • >>   hal_lcdc_postproc_config +
    + +

    drv_lcdc_function_disable (Thumb, 30 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_function_disable)) +

    [Called By]

    • >>   hal_lcdc_postproc_config +
    • >>   vidc_callback +
    • >>   hal_internal_vsync_set_tx_state +
    • >>   hal_internal_vsync_set_tear_mode +
    + +

    drv_lcdc_function_enable (Thumb, 30 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_function_enable)) +

    [Called By]

    • >>   drv_lcdc_ctrl_flow +
    • >>   hal_lcdc_upscaler_config +
    • >>   hal_lcdc_postproc_config +
    • >>   hal_dsi_tx_ctrl_start +
    • >>   hal_internal_vsync_set_tear_mode +
    + +

    drv_lcdc_set_int (Thumb, 54 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_set_int)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = drv_lcdc_set_int ⇒ drv_lcdc_clear_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_lcdc_clear_int +
    +
    [Called By]
    • >>   hal_lcdc_init_cfg +
    • >>   hal_dsi_tx_ctrl_stop +
    + +

    drv_lcdc_set_prefetch (Thumb, 24 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_set_prefetch)) +

    [Called By]

    • >>   hal_lcdc_timinggen_config +
    + +

    drv_lcdc_set_tear_line (Thumb, 24 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_set_tear_line)) +

    [Called By]

    • >>   hal_internal_vsync_set_tear_mode +
    + +

    drv_lcdc_stop_display (Thumb, 12 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_stop_display)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_stop +
    + +

    drv_lcdc_vid_hw_start (Thumb, 56 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_vid_hw_start)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = drv_lcdc_vid_hw_start ⇒ drv_se_set_lcdc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_lcdc +
    +
    [Called By]
    • >>   hal_lcdc_start +
    + +

    drv_lcdc_vintp_mode_config (Thumb, 18 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_vintp_mode_config)) +

    [Called By]

    • >>   hal_lcdc_postproc_config +
    + +

    drv_memc_clear_status (Thumb, 14 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_clear_status)) +

    [Called By]

    • >>   MEMC_IRQn_Handler +
    + +

    drv_memc_enable_irq (Thumb, 58 bytes, Stack size 8 bytes, drv_memc.o(i.drv_memc_enable_irq)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_memc_enable_irq ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_memc +
    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    drv_memc_gen_a_tear_signal (Thumb, 12 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_gen_a_tear_signal)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_gen_a_tear_signal +
    + +

    drv_memc_get_status (Thumb, 20 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_get_status)) +

    [Called By]

    • >>   MEMC_IRQn_Handler +
    + +

    drv_memc_get_tear_mode (Thumb, 10 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_get_tear_mode)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_gen_a_tear_signal +
    + +

    drv_memc_rate_transfer_sel (Thumb, 22 bytes, Stack size 8 bytes, drv_memc.o(i.drv_memc_rate_transfer_sel)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = drv_memc_rate_transfer_sel ⇒ drv_se_set_memc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_memc +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_sel_vsync (Thumb, 16 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_sel_vsync)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_active_height (Thumb, 16 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_active_height)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_circ_mode_enable (Thumb, 24 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_circ_mode_enable)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_data_mode (Thumb, 14 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_data_mode)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_double_buffer (Thumb, 18 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_double_buffer)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_frame_drop_select (Thumb, 24 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_frame_drop_select)) +

    [Called By]

    • >>   hal_internal_vsync_set_tear_mode +
    + +

    drv_memc_set_fs_en_conditions (Thumb, 18 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_fs_en_conditions)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_lcdc_st_conditions (Thumb, 20 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_lcdc_st_conditions)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_ltpo_mode (Thumb, 28 bytes, Stack size 8 bytes, drv_memc.o(i.drv_memc_set_ltpo_mode)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = drv_memc_set_ltpo_mode ⇒ drv_se_set_memc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_memc +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_ltpo_pu_thres (Thumb, 18 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_ltpo_pu_thres)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_tear_mode (Thumb, 16 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_tear_mode)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    • >>   hal_dsi_tx_ctrl_gen_a_tear_signal +
    • >>   hal_internal_vsync_set_tear_mode +
    + +

    drv_memc_set_tear_waveform (Thumb, 36 bytes, Stack size 8 bytes, drv_memc.o(i.drv_memc_set_tear_waveform)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_memc_set_tear_waveform +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_memc_set_vidc_sync_cnt (Thumb, 16 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_vidc_sync_cnt)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_memc +
    + +

    drv_phy_test_clear (Thumb, 16 bytes, Stack size 0 bytes, drv_phy_common.o(i.drv_phy_test_clear)) +

    [Called By]

    • >>   drv_dsi_tx_phy_test_setup +
    • >>   drv_dsi_rx_set_up_phy +
    + +

    drv_phy_test_lock (Thumb, 24 bytes, Stack size 0 bytes, drv_phy_common.o(i.drv_phy_test_lock)) +

    [Called By]

    • >>   drv_dsi_rx_set_up_phy +
    + +

    drv_pwr_efuse_pd (Thumb, 36 bytes, Stack size 0 bytes, drv_pwr.o(i.drv_pwr_efuse_pd)) +

    [Called By]

    • >>   drv_efuse_read +
    + +

    drv_pwr_enter_deep_sleep_mode (Thumb, 60 bytes, Stack size 8 bytes, drv_pwr.o(i.drv_pwr_enter_deep_sleep_mode)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_pwr_enter_deep_sleep_mode +
    +
    [Called By]
    • >>   hal_pwr_enter_deep_sleep_mode +
    + +

    drv_pwr_enter_sleep_mode_ex (Thumb, 34 bytes, Stack size 0 bytes, drv_pwr.o(i.drv_pwr_enter_sleep_mode_ex)) +

    [Called By]

    • >>   hal_pwr_enter_normal_sleep_mode +
    + +

    drv_pwr_enter_stop_sleep_mode (Thumb, 132 bytes, Stack size 24 bytes, drv_pwr.o(i.drv_pwr_enter_stop_sleep_mode)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = drv_pwr_enter_stop_sleep_mode +
    +
    [Calls]
    • >>   drv_pwr_write_lock +
    +
    [Called By]
    • >>   hal_pwr_enter_stop_sleep_mode +
    + +

    drv_pwr_exit_sleep_mode (Thumb, 32 bytes, Stack size 4 bytes, drv_pwr.o(i.drv_pwr_exit_sleep_mode)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = drv_pwr_exit_sleep_mode +
    +
    [Calls]
    • >>   drv_pwr_write_lock +
    +
    [Called By]
    • >>   hal_pwr_exit_sleep_mode +
    + +

    drv_pwr_get_power_ready_st (Thumb, 10 bytes, Stack size 0 bytes, drv_pwr.o(i.drv_pwr_get_power_ready_st)) +

    [Called By]

    • >>   hal_pwr_get_vcc_power_ready +
    + +

    drv_pwr_set_breath_screen_power_sel (Thumb, 34 bytes, Stack size 8 bytes, drv_pwr.o(i.drv_pwr_set_breath_screen_power_sel)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_pwr_set_breath_screen_power_sel +
    +
    [Calls]
    • >>   drv_pwr_write_lock +
    +
    [Called By]
    • >>   hal_pwr_set_sleep_mode_power +
    + +

    drv_pwr_set_digit_power_sel (Thumb, 34 bytes, Stack size 8 bytes, drv_pwr.o(i.drv_pwr_set_digit_power_sel)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_pwr_set_digit_power_sel +
    +
    [Calls]
    • >>   drv_pwr_write_lock +
    +
    [Called By]
    • >>   hal_pwr_set_main_power +
    + +

    drv_pwr_set_pll_clk (Thumb, 30 bytes, Stack size 0 bytes, drv_pwr.o(i.drv_pwr_set_pll_clk)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_clk +
    • >>   hal_system_init +
    + +

    drv_pwr_set_wakeup_type (Thumb, 40 bytes, Stack size 4 bytes, drv_pwr.o(i.drv_pwr_set_wakeup_type)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = drv_pwr_set_wakeup_type +
    +
    [Calls]
    • >>   drv_pwr_write_lock +
    +
    [Called By]
    • >>   hal_pwr_enter_deep_sleep_mode +
    + +

    drv_pwr_write_lock (Thumb, 18 bytes, Stack size 0 bytes, drv_pwr.o(i.drv_pwr_write_lock)) +

    [Called By]

    • >>   drv_pwr_set_wakeup_type +
    • >>   drv_pwr_set_digit_power_sel +
    • >>   drv_pwr_set_breath_screen_power_sel +
    • >>   drv_pwr_exit_sleep_mode +
    • >>   drv_pwr_enter_stop_sleep_mode +
    + +

    drv_rxbr_clear_pkt_buffer (Thumb, 12 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer)) +

    [Called By]

    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_intl_dcs_rx_receive_packet +
    • >>   check_pkt_buf_rev +
    • >>   rxbr_irq1_callback +
    + +

    drv_rxbr_clear_status0 (Thumb, 6 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_clear_status0)) +

    [Called By]

    • >>   hal_internal_sync_input_resolution_change +
    • >>   svs_wait_start +
    • >>   svs_direct_mode_setting +
    • >>   VPRE_IRQn_Handler +
    • >>   hal_intl_dcs_rx_receive_packet +
    • >>   check_pkt_buf_rev +
    • >>   rxbr_irq1_callback +
    + +

    drv_rxbr_enable_irq (Thumb, 90 bytes, Stack size 8 bytes, drv_rxbr.o(i.drv_rxbr_enable_irq)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_rxbr_enable_irq ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_sys_cfg_clear_pending +
    • >>   __NVIC_EnableIRQ +
    • >>   __NVIC_DisableIRQ +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    drv_rxbr_frame_drop_cfg (Thumb, 18 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_frame_drop_cfg)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_rxbr +
    • >>   svs_wait_fr_stab +
    + +

    drv_rxbr_hline_rcv1_cfg (Thumb, 14 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg)) +

    [Called By]

    • >>   svs_wait_start +
    • >>   svs_direct_mode_setting +
    + +

    drv_rxbr_hline_rcv_cfg (Thumb, 10 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_hline_rcv_cfg)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    drv_rxbr_register_irq1_callback (Thumb, 6 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_register_irq1_callback)) +

    [Called By]

    • >>   hal_internal_vsync_init_rx +
    + +

    drv_rxbr_set_ack_pkt_header (Thumb, 18 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_ack_pkt_header)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_send_ack_cmd +
    + +

    drv_rxbr_set_color_format (Thumb, 24 bytes, Stack size 8 bytes, drv_rxbr.o(i.drv_rxbr_set_color_format)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = drv_rxbr_set_color_format ⇒ drv_se_set_rxbr ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_rxbr +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    drv_rxbr_set_filter_regs (Thumb, 32 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_filter_regs)) +

    [Called By]

    • >>   hal_intl_dcs_set_auto_hw_filter +
    + +

    drv_rxbr_set_inten (Thumb, 22 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_inten)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_rxbr +
    • >>   svs_wait_start +
    • >>   hal_intl_svs_init_rx +
    • >>   hal_intl_svs_deinit_rx +
    • >>   rxbr_irq1_callback +
    + +

    drv_rxbr_set_ltpo_drop_th (Thumb, 18 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_ltpo_drop_th)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    drv_rxbr_set_usr_cfg (Thumb, 56 bytes, Stack size 20 bytes, drv_rxbr.o(i.drv_rxbr_set_usr_cfg)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = drv_rxbr_set_usr_cfg +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    drv_rxbr_set_usr_col (Thumb, 10 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_usr_col)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    drv_rxbr_set_usr_row (Thumb, 10 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_usr_row)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    drv_se_init (Thumb, 106 bytes, Stack size 16 bytes, drv_se.o(i.drv_se_init)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = drv_se_init ⇒ drv_efuse_read +
    +
    [Calls]
    • >>   drv_efuse_read +
    • >>   drv_efuse_enter_inactive +
    +
    [Called By]
    • >>   drv_common_system_init +
    + +

    drv_se_set_dsc (Thumb, 162 bytes, Stack size 16 bytes, drv_se.o(i.drv_se_set_dsc)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = drv_se_set_dsc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   drv_dsc_dec_enable +
    + +

    drv_se_set_lcdc (Thumb, 88 bytes, Stack size 16 bytes, drv_se.o(i.drv_se_set_lcdc)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = drv_se_set_lcdc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   drv_lcdc_cmd_start +
    • >>   drv_lcdc_vid_hw_start +
    + +

    drv_se_set_memc (Thumb, 54 bytes, Stack size 8 bytes, drv_se.o(i.drv_se_set_memc)) +

    [Stack]

    • Max Depth = 344
    • Call Chain = drv_se_set_memc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   drv_memc_set_ltpo_mode +
    • >>   drv_memc_rate_transfer_sel +
    + +

    drv_se_set_rxbr (Thumb, 158 bytes, Stack size 16 bytes, drv_se.o(i.drv_se_set_rxbr)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = drv_se_set_rxbr ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   drv_rxbr_set_color_format +
    + +

    drv_se_set_vidc (Thumb, 122 bytes, Stack size 16 bytes, drv_se.o(i.drv_se_set_vidc)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   drv_vidc_set_src_parameter +
    + +

    drv_se_start_rx (Thumb, 16 bytes, Stack size 0 bytes, drv_se.o(i.drv_se_start_rx)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init +
    + +

    drv_swire_enable (Thumb, 24 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_enable)) +

    [Called By]

    • >>   hal_swire_init +
    • >>   hal_swire_deinit +
    + +

    drv_swire_get_pulse_count (Thumb, 6 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_get_pulse_count)) +

    [Called By]

    • >>   hal_swire_enable +
    + +

    drv_swire_register_callback (Thumb, 6 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_register_callback)) +

    [Called By]

    • >>   hal_swire_deinit +
    + +

    drv_swire_set_bit_time (Thumb, 18 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_set_bit_time)) +

    [Called By]

    • >>   hal_swire_init +
    + +

    drv_swire_set_int (Thumb, 64 bytes, Stack size 16 bytes, drv_swire.o(i.drv_swire_set_int)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_swire_set_int +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    +
    [Called By]
    • >>   hal_swire_enable +
    • >>   hal_swire_deinit +
    + +

    drv_swire_set_power_down (Thumb, 24 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_set_power_down)) +

    [Called By]

    • >>   hal_swire_init +
    • >>   hal_swire_enable +
    + +

    drv_swire_set_pulse_count (Thumb, 6 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_set_pulse_count)) +

    [Called By]

    • >>   hal_swire_set_pulse +
    + +

    drv_swire_set_trig_mode (Thumb, 24 bytes, Stack size 0 bytes, drv_swire.o(i.drv_swire_set_trig_mode)) +

    [Called By]

    • >>   hal_swire_set_timer +
    • >>   hal_swire_set_pulse +
    • >>   hal_swire_enable +
    + +

    drv_sys_cfg_clear_all_int (Thumb, 8 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_clear_all_int)) +

    [Called By]

    • >>   hal_system_init +
    + +

    drv_sys_cfg_clear_pending (Thumb, 32 bytes, Stack size 8 bytes, drv_sys_cfg.o(i.drv_sys_cfg_clear_pending)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   drv_dsi_tx_set_int +
    • >>   drv_vidc_enable_irq +
    • >>   drv_rxbr_enable_irq +
    • >>   drv_memc_enable_irq +
    • >>   drv_dsi_rx_enable_irq +
    • >>   hal_gpio_set_ap_reset_int +
    • >>   AP_NRESET_IRQn_Handler +
    • >>   drv_gpio_handle_int +
    • >>   VPRE_IRQn_Handler +
    • >>   LCDC_IRQn_Handler +
    • >>   hal_gpio_init_eint +
    • >>   UART_IRQn_Handler +
    • >>   DMA_IRQn_Handler +
    • >>   VIDC_IRQn_Handler +
    • >>   VPRE1_IRQn_Handler +
    • >>   MEMC_IRQn_Handler +
    • >>   drv_lcdc_clear_int +
    • >>   MIPI_TX_IRQn_Handler +
    • >>   MIPI_RX_IRQn_Handler +
    • >>   drv_timer_clear_status_flags +
    • >>   SWIRE_IRQn_Handler +
    + +

    drv_sys_cfg_sel_ap_rst_trig (Thumb, 30 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_trig)) +

    [Called By]

    • >>   hal_gpio_set_ap_reset_int +
    + +

    drv_sys_cfg_sel_gpio_group (Thumb, 30 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_sel_gpio_group)) +

    [Called By]

    • >>   hal_gpio_init_eint +
    + +

    drv_sys_cfg_sel_int_trig (Thumb, 32 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_sel_int_trig)) +

    [Called By]

    • >>   hal_gpio_init_eint +
    + +

    drv_sys_cfg_sel_swire_timer (Thumb, 18 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_sel_swire_timer)) +

    [Called By]

    • >>   hal_swire_set_timer +
    + +

    drv_sys_cfg_set_int (Thumb, 30 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_set_int)) +

    [Called By]

    • >>   drv_dsi_tx_set_int +
    • >>   drv_vidc_enable_irq +
    • >>   drv_rxbr_enable_irq +
    • >>   drv_memc_enable_irq +
    • >>   drv_dsi_rx_enable_irq +
    • >>   hal_pwr_enter_stop_sleep_mode +
    • >>   hal_gpio_set_ap_reset_int +
    • >>   drv_timer_set_int +
    • >>   drv_swire_set_int +
    • >>   drv_gpio_set_int +
    • >>   drv_lcdc_set_int +
    • >>   drv_uart_enable_int +
    + +

    drv_timer_enable (Thumb, 32 bytes, Stack size 4 bytes, drv_timer.o(i.drv_timer_enable)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = drv_timer_enable +
    +
    [Calls]
    • >>   drv_timer_get_instance +
    +
    [Called By]
    • >>   hal_swire_enable +
    • >>   hal_timer_deinit +
    + +

    drv_timer_get_instance (Thumb, 10 bytes, Stack size 0 bytes, drv_timer.o(i.drv_timer_get_instance)) +

    [Called By]

    • >>   drv_timer_set_prescaler +
    • >>   drv_timer_set_compare_val +
    • >>   drv_timer_enable +
    • >>   drv_timer_clear_status_flags +
    + +

    drv_timer_set_compare_val (Thumb, 50 bytes, Stack size 16 bytes, drv_timer.o(i.drv_timer_set_compare_val)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    • >>   drv_timer_get_instance +
    +
    [Called By]
    • >>   hal_swire_set_timer +
    • >>   drv_timer_handle_interrupt +
    + +

    drv_timer_set_int (Thumb, 68 bytes, Stack size 16 bytes, drv_timer.o(i.drv_timer_set_int)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_timer_set_int +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    +
    [Called By]
    • >>   hal_timer_deinit +
    • >>   drv_timer_handle_interrupt +
    + +

    drv_timer_set_prescaler (Thumb, 36 bytes, Stack size 12 bytes, drv_timer.o(i.drv_timer_set_prescaler)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_timer_set_prescaler +
    +
    [Calls]
    • >>   drv_timer_get_instance +
    +
    [Called By]
    • >>   hal_timer_init +
    + +

    drv_timer_set_repeat (Thumb, 12 bytes, Stack size 0 bytes, drv_timer.o(i.drv_timer_set_repeat)) +

    [Called By]

    • >>   hal_timer_set_repeat +
    • >>   hal_timer_deinit +
    + +

    drv_tx_phy_test_enter (Thumb, 28 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_tx_phy_test_enter)) +

    [Called By]

    • >>   drv_dsi_tx_phy_test_setup +
    + +

    drv_tx_phy_test_exit (Thumb, 28 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_tx_phy_test_exit)) +

    [Called By]

    • >>   drv_dsi_tx_phy_test_setup +
    + +

    drv_tx_phy_test_write_code (Thumb, 34 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_tx_phy_test_write_code)) +

    [Called By]

    • >>   drv_dsi_tx_phy_test_setup +
    + +

    drv_uart_abort_recv (Thumb, 46 bytes, Stack size 12 bytes, drv_uart.o(i.drv_uart_abort_recv)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = drv_uart_abort_recv ⇒ drv_uart_reset_rx_fifo ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   drv_uart_reset_rx_fifo +
    • >>   drv_uart_get_instance +
    • >>   drv_uart_config_int +
    +
    [Called By]
    • >>   UART_IRQn_Handler +
    + +

    drv_uart_abort_send (Thumb, 46 bytes, Stack size 12 bytes, drv_uart.o(i.drv_uart_abort_send)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = drv_uart_abort_send ⇒ drv_uart_reset_tx_fifo ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   drv_uart_reset_tx_fifo +
    • >>   drv_uart_get_instance +
    • >>   drv_uart_config_int +
    +
    [Called By]
    • >>   UART_IRQn_Handler +
    + +

    drv_uart_config_int (Thumb, 20 bytes, Stack size 0 bytes, drv_uart.o(i.drv_uart_config_int)) +

    [Called By]

    • >>   drv_uart_abort_send +
    • >>   drv_uart_abort_recv +
    • >>   UART_IRQn_Handler +
    + +

    drv_uart_enable_int (Thumb, 84 bytes, Stack size 24 bytes, drv_uart.o(i.drv_uart_enable_int)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = drv_uart_enable_int ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_uart_get_instance +
    +
    [Called By]
    • >>   drv_uart_init +
    + +

    drv_uart_get_instance (Thumb, 36 bytes, Stack size 12 bytes, drv_uart.o(i.drv_uart_get_instance)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_uart_get_instance +
    +
    [Called By]
    • >>   drv_uart_trans_create_handle +
    • >>   drv_uart_init +
    • >>   drv_uart_reset_tx_fifo +
    • >>   drv_uart_reset_rx_fifo +
    • >>   drv_uart_enable_int +
    • >>   drv_uart_abort_send +
    • >>   drv_uart_abort_recv +
    + +

    drv_uart_init (Thumb, 206 bytes, Stack size 16 bytes, drv_uart.o(i.drv_uart_init)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = drv_uart_init ⇒ drv_uart_set_baud_rate ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_uart_set_baud_rate +
    • >>   drv_uart_get_instance +
    • >>   drv_uart_enable_int +
    • >>   drv_uart_enable_clk +
    +
    [Called By]
    • >>   hal_uart_init +
    + +

    drv_uart_reset_rx_fifo (Thumb, 28 bytes, Stack size 8 bytes, drv_uart.o(i.drv_uart_reset_rx_fifo)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = drv_uart_reset_rx_fifo ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   drv_uart_get_instance +
    +
    [Called By]
    • >>   drv_uart_abort_recv +
    + +

    drv_uart_reset_tx_fifo (Thumb, 28 bytes, Stack size 8 bytes, drv_uart.o(i.drv_uart_reset_tx_fifo)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = drv_uart_reset_tx_fifo ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   drv_uart_get_instance +
    +
    [Called By]
    • >>   drv_uart_abort_send +
    + +

    drv_uart_send_blocking (Thumb, 26 bytes, Stack size 0 bytes, drv_uart.o(i.drv_uart_send_blocking)) +

    [Called By]

    • >>   hal_uart_send_blocking +
    + +

    drv_uart_set_baud_rate (Thumb, 84 bytes, Stack size 24 bytes, drv_uart.o(i.drv_uart_set_baud_rate)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = drv_uart_set_baud_rate ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   drv_uart_init +
    + +

    drv_uart_trans_create_handle (Thumb, 72 bytes, Stack size 24 bytes, drv_uart.o(i.drv_uart_trans_create_handle)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = drv_uart_trans_create_handle ⇒ drv_uart_get_instance +
    +
    [Calls]
    • >>   drv_uart_get_instance +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   hal_uart_init +
    + +

    drv_vidc_clear_irq (Thumb, 10 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_clear_irq)) +

    [Called By]

    • >>   vidc_callback +
    + +

    drv_vidc_enable (Thumb, 26 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_enable)) +

    [Called By]

    • >>   hal_internal_sync_input_resolution_change +
    • >>   hal_dsi_rx_ctrl_stop +
    • >>   hal_dsi_rx_ctrl_start +
    • >>   rxbr_irq1_callback +
    + +

    drv_vidc_enable_irq (Thumb, 58 bytes, Stack size 8 bytes, drv_vidc.o(i.drv_vidc_enable_irq)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_vidc_enable_irq ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    drv_vidc_get_int_source (Thumb, 40 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_get_int_source)) +

    [Called By]

    • >>   vidc_callback +
    + +

    drv_vidc_get_irq_status (Thumb, 20 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_get_irq_status)) +

    [Called By]

    • >>   vidc_callback +
    + +

    drv_vidc_init_module_enable (Thumb, 36 bytes, Stack size 12 bytes, drv_vidc.o(i.drv_vidc_init_module_enable)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_vidc_init_module_enable +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_register_callback (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_register_callback)) +

    [Called By]

    • >>   hal_internal_vsync_init_rx +
    + +

    drv_vidc_reset (Thumb, 8 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_reset)) +

    [Called By]

    • >>   hal_internal_sync_input_resolution_change +
    • >>   vpre_err_reset +
    + +

    drv_vidc_set_circ_mode_enable (Thumb, 24 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_circ_mode_enable)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_dither_config (Thumb, 50 bytes, Stack size 8 bytes, drv_vidc.o(i.drv_vidc_set_dither_config)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_vidc_set_dither_config +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_dst_parameter (Thumb, 86 bytes, Stack size 16 bytes, drv_vidc.o(i.drv_vidc_set_dst_parameter)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_vidc_set_dst_parameter +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_honly_hcoef0 (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_honly_hcoef0)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_honly_hinitb (Thumb, 38 bytes, Stack size 12 bytes, drv_vidc.o(i.drv_vidc_set_honly_hinitb)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_vidc_set_honly_hinitb +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_honly_hinitr (Thumb, 42 bytes, Stack size 16 bytes, drv_vidc.o(i.drv_vidc_set_honly_hinitr)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_vidc_set_honly_hinitr +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_irqen (Thumb, 22 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_irqen)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   vidc_callback +
    + +

    drv_vidc_set_mirror (Thumb, 16 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_mirror)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_pentile_swap (Thumb, 20 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_pentile_swap)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_pu_ctrl (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_pu_ctrl)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_rotation (Thumb, 18 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_rotation)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_scld_hcoef0 (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_hcoef0)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_scld_hcoef1 (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_hcoef1)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_scld_step (Thumb, 14 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_step)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_scld_vcoef0 (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_vcoef0)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_scld_vcoef1 (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_vcoef1)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_src_parameter (Thumb, 28 bytes, Stack size 16 bytes, drv_vidc.o(i.drv_vidc_set_src_parameter)) +

    [Stack]

    • Max Depth = 368
    • Call Chain = drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_se_set_vidc +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    drv_vidc_set_vintp_config (Thumb, 52 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_vintp_config)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_init_vidc +
    + +

    fputc (Thumb, 42 bytes, Stack size 24 bytes, tau_log.o(i.fputc)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = fputc ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_uart_send_blocking +
    • >>   tau_log_push_log +
    +
    [Address Reference Count : 1]
    • printfa.o(i.__0printf) +
    +

    google_p8p_demo (Thumb, 48 bytes, Stack size 0 bytes, p8p_demo.o(i.google_p8p_demo)) +

    [Stack]

    • Max Depth = 656
    • Call Chain = google_p8p_demo ⇒ app_system_process ⇒ app_system_resume ⇒ app_display_init ⇒ app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_pwr_set_main_power +
    • >>   hal_dsi_rx_ctrl_dcs_async_handler +
    • >>   app_display_init +
    • >>   app_system_process +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   main +
    + +

    hal_dsi_rx_ctrl_create_handle (Thumb, 60 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_rx_ctrl_create_handle +
    +
    [Calls]
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   app_mipi_rx_init +
    + +

    hal_dsi_rx_ctrl_dcs_async_handler (Thumb, 60 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dcs_async_handler)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_rx_ctrl_dcs_async_handler +
    +
    [Calls]
    • >>   dcs_packet_get_fifo_header +
    • >>   dcs_packet_free_fifo_header +
    +
    [Called By]
    • >>   google_p8p_demo +
    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    + +

    hal_dsi_rx_ctrl_deinit (Thumb, 132 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_dsi_rx_ctrl_deinit ⇒ hal_internal_vsync_set_rx_state ⇒ hal_intl_svs_deinit_rx +
    +
    [Calls]
    • >>   hal_internal_vsync_set_rx_state +
    • >>   hal_internal_vsync_get_tx_state +
    • >>   hal_internal_vsync_get_rx_state +
    • >>   drv_vidc_enable_irq +
    • >>   drv_rxbr_enable_irq +
    • >>   drv_memc_enable_irq +
    • >>   drv_dsi_rx_enable_irq +
    • >>   drv_dsc_dec_disable +
    • >>   drv_crgu_set_reset +
    • >>   drv_crgu_reset_modules +
    • >>   drv_crgu_enable_clock +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_dsi_rx_ctrl_get_max_ret_size (Thumb, 28 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_rx_ctrl_get_max_ret_size +
    +
    [Calls]
    • >>   drv_dsi_rx_get_max_ret_size +
    +
    [Called By]
    • >>   ap_dcs_read +
    + +

    hal_dsi_rx_ctrl_init (Thumb, 158 bytes, Stack size 16 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init)) +

    [Stack]

    • Max Depth = 552
    • Call Chain = hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_internal_vsync_set_rx_state +
    • >>   hal_internal_vsync_init_rx +
    • >>   drv_se_start_rx +
    • >>   drv_dsc_dec_set_irqen +
    • >>   drv_dsc_dec_enable +
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    • >>   hal_dsi_rx_ctrl_init_memc +
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    • >>   hal_dsi_rx_ctrl_init_clk +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_internal_sync_input_resolution_change +
    • >>   app_mipi_rx_init +
    + +

    hal_dsi_rx_ctrl_pre_init_pps (Thumb, 50 bytes, Stack size 12 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = hal_dsi_rx_ctrl_pre_init_pps +
    +
    [Called By]
    • >>   app_mipi_tx_start +
    • >>   app_mipi_rx_init +
    • >>   ap_dcs_set_display_on +
    + +

    hal_dsi_rx_ctrl_send_ack_cmd (Thumb, 210 bytes, Stack size 48 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd)) +

    [Stack]

    • Max Depth = 384
    • Call Chain = hal_dsi_rx_ctrl_send_ack_cmd ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_rxbr_set_ack_pkt_header +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   ap_dcs_read +
    + +

    hal_dsi_rx_ctrl_start (Thumb, 42 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_dsi_rx_ctrl_start ⇒ hal_internal_vsync_set_rx_state ⇒ hal_intl_svs_deinit_rx +
    +
    [Calls]
    • >>   hal_internal_vsync_set_rx_state +
    • >>   drv_vidc_enable +
    • >>   drv_dsi_rx_power_up +
    +
    [Called By]
    • >>   hal_internal_sync_input_resolution_change +
    • >>   app_mipi_rx_init +
    + +

    hal_dsi_rx_ctrl_stop (Thumb, 42 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_dsi_rx_ctrl_stop ⇒ hal_internal_vsync_set_rx_state ⇒ hal_intl_svs_deinit_rx +
    +
    [Calls]
    • >>   hal_internal_vsync_set_rx_state +
    • >>   drv_vidc_enable +
    • >>   drv_dsi_rx_shut_down +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_dsi_rx_ctrl_toggle_resolution (Thumb, 28 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution)) +

    [Stack]

    • Max Depth = 624
    • Call Chain = hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_internal_sync_input_resolution_change +
    +
    [Called By]
    • >>   pps_update_handle +
    • >>   app_mipi_tx_start +
    • >>   ap_dcs_set_display_on +
    + +

    hal_dsi_tx_ctrl_create_handle (Thumb, 48 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_tx_ctrl_create_handle +
    +
    [Calls]
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   app_mipi_tx_init +
    + +

    hal_dsi_tx_ctrl_deinit (Thumb, 102 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = hal_dsi_tx_ctrl_deinit ⇒ hal_internal_vsync_set_tx_state ⇒ hal_internal_vsync_deinit +
    +
    [Calls]
    • >>   drv_crgu_reset_modules +
    • >>   drv_crgu_enable_clock +
    • >>   hal_internal_vsync_set_tx_state +
    • >>   hal_internal_sync_register_lcdc_cb +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_dsi_tx_ctrl_gen_a_tear_signal (Thumb, 34 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_gen_a_tear_signal)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_tx_ctrl_gen_a_tear_signal +
    +
    [Calls]
    • >>   drv_memc_set_tear_mode +
    • >>   drv_memc_get_tear_mode +
    • >>   drv_memc_gen_a_tear_signal +
    +
    [Called By]
    • >>   hal_internal_sync_input_resolution_change +
    + +

    hal_dsi_tx_ctrl_init (Thumb, 110 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init)) +

    [Stack]

    • Max Depth = 432
    • Call Chain = hal_dsi_tx_ctrl_init ⇒ hal_dsi_tx_init_timing ⇒ hal_dsi_tx_cmd_mode_cal_timing ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_dsi_tx_powerup +
    • >>   drv_dsi_tx_phy_status_ready +
    • >>   hal_lcdc_init_clk +
    • >>   hal_lcdc_init_cfg +
    • >>   hal_dsi_tx_init_timing +
    • >>   hal_dsi_tx_init_cfg +
    • >>   hal_dsi_tx_ctrl_init_clk +
    • >>   hal_internal_vsync_set_tx_state +
    • >>   hal_internal_vsync_init_tx +
    • >>   hal_internal_sync_register_lcdc_cb +
    +
    [Called By]
    • >>   hal_tx_frame_rate_adjust +
    • >>   app_mipi_tx_init +
    + +

    hal_dsi_tx_ctrl_set_overwrite_rgb (Thumb, 8 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_tx_ctrl_set_overwrite_rgb +
    +
    [Calls]
    • >>   drv_lcdc_config_overwrite_rgb +
    +
    [Called By]
    • >>   app_mipi_tx_init +
    + +

    hal_dsi_tx_ctrl_set_tear_mode (Thumb, 10 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_tear_mode)) +

    [Stack]

    • Max Depth = 376
    • Call Chain = hal_dsi_tx_ctrl_set_tear_mode ⇒ hal_internal_vsync_set_tear_mode ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_internal_vsync_set_tear_mode +
    +
    [Called By]
    • >>   pps_update_handle +
    • >>   app_mipi_tx_start +
    • >>   ap_dcs_set_frame_change +
    • >>   ap_dcs_set_enter_sleep_mode +
    + +

    hal_dsi_tx_ctrl_start (Thumb, 134 bytes, Stack size 24 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start)) +

    [Stack]

    • Max Depth = 392
    • Call Chain = hal_dsi_tx_ctrl_start ⇒ hal_lcdc_start ⇒ drv_lcdc_cmd_start ⇒ drv_se_set_lcdc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_lcdc_enable_shadow_reg +
    • >>   drv_lcdc_cfg_int_frame +
    • >>   drv_dsi_tx_shutdown +
    • >>   drv_dsi_tx_powerup +
    • >>   drv_dsi_tx_phy_clock_lane_auto_lp +
    • >>   drv_dsi_tx_mode +
    • >>   drv_dsi_tx_config_eotp +
    • >>   drv_dsi_tx_command_mode_cfg +
    • >>   hal_lcdc_start +
    • >>   hal_intl_fb_get_memc_flow_mode +
    • >>   hal_internal_vsync_set_tx_state +
    • >>   drv_lcdc_function_enable +
    +
    [Called By]
    • >>   app_mipi_tx_start +
    + +

    hal_dsi_tx_ctrl_stop (Thumb, 52 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = hal_dsi_tx_ctrl_stop ⇒ hal_internal_vsync_set_tx_state ⇒ hal_internal_vsync_deinit +
    +
    [Calls]
    • >>   drv_dsi_tx_shutdown +
    • >>   drv_dsi_tx_set_int +
    • >>   hal_internal_vsync_set_tx_state +
    • >>   drv_lcdc_stop_display +
    • >>   drv_lcdc_set_int +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_dsi_tx_ctrl_write_array_cmd (Thumb, 238 bytes, Stack size 48 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = hal_dsi_tx_ctrl_write_array_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   drv_dsi_tx_get_cmd_status +
    • >>   drv_dsi_tx_command_put_payload +
    • >>   hal_dsi_tx_send_cmd +
    • >>   hal_internal_vsync_get_tx_state +
    +
    [Called By]
    • >>   send_panel_init_code +
    + +

    hal_dsi_tx_ctrl_write_cmd (Thumb, 202 bytes, Stack size 48 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = hal_dsi_tx_ctrl_write_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   drv_dsi_tx_get_cmd_status +
    • >>   drv_dsi_tx_command_put_payload +
    • >>   hal_dsi_tx_send_cmd +
    • >>   hal_internal_vsync_get_tx_state +
    +
    [Called By]
    • >>   app_mipi_tx_start +
    • >>   ap_set_FPS_53 +
    • >>   ap_dcs_set_enter_sleep_mode +
    • >>   ap_dcs_set_display_on +
    • >>   ap_dcs_set_backlight +
    + +

    hal_gpio_config_pad (Thumb, 58 bytes, Stack size 16 bytes, hal_gpio.o(i.hal_gpio_config_pad)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = hal_gpio_config_pad ⇒ hal_gpio_init_output ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   hal_gpio_init_output +
    • >>   hal_gpio_set_mode +
    • >>   hal_gpio_init_input +
    +
    [Called By]
    • >>   app_gpio_init +
    + +

    hal_gpio_ctrl_eint (Thumb, 18 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_ctrl_eint)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_gpio_ctrl_eint ⇒ drv_gpio_set_int +
    +
    [Calls]
    • >>   drv_gpio_set_int +
    +
    [Called By]
    • >>   hal_pwr_set_stop_sleep_wakeup_pin +
    + +

    hal_gpio_init_eint (Thumb, 58 bytes, Stack size 24 bytes, hal_gpio.o(i.hal_gpio_init_eint)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = hal_gpio_init_eint ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   drv_sys_cfg_sel_int_trig +
    • >>   drv_sys_cfg_sel_gpio_group +
    • >>   drv_sys_cfg_clear_pending +
    • >>   drv_gpio_set_ioe +
    • >>   hal_gpio_set_mode +
    +
    [Called By]
    • >>   hal_pwr_set_stop_sleep_wakeup_pin +
    + +

    hal_gpio_init_input (Thumb, 22 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_init_input)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_gpio_init_input ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   drv_gpio_set_ioe +
    • >>   hal_gpio_set_mode +
    +
    [Called By]
    • >>   hal_gpio_config_pad +
    + +

    hal_gpio_init_output (Thumb, 28 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_init_output)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_gpio_init_output ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   drv_gpio_set_ioe +
    • >>   hal_gpio_set_mode +
    • >>   drv_gpio_set_output_data +
    +
    [Called By]
    • >>   hal_gpio_config_pad +
    • >>   app_system_suspend +
    • >>   app_init_panel +
    + +

    hal_gpio_reg_eint_cb (Thumb, 22 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_reg_eint_cb)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_gpio_reg_eint_cb +
    +
    [Calls]
    • >>   drv_gpio_register_callback +
    +
    [Called By]
    • >>   hal_pwr_set_stop_sleep_wakeup_pin +
    + +

    hal_gpio_set_ap_reset_int (Thumb, 76 bytes, Stack size 16 bytes, hal_gpio.o(i.hal_gpio_set_ap_reset_int)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_gpio_set_ap_reset_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_set_int +
    • >>   drv_sys_cfg_sel_ap_rst_trig +
    • >>   drv_sys_cfg_clear_pending +
    • >>   drv_gpio_register_ap_reset_callback +
    +
    [Called By]
    • >>   hal_pwr_set_stop_sleep_wakeup_pin +
    • >>   app_system_suspend +
    • >>   ap_rstn_pull_high_cb +
    • >>   ap_rstn_pull_down_cb +
    • >>   ap_dcs_set_enter_sleep_mode +
    + +

    hal_gpio_set_mode (Thumb, 92 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_set_mode)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   drv_gpio_set_mode +
    +
    [Called By]
    • >>   hal_system_init +
    • >>   hal_swire_init +
    • >>   hal_gpio_init_output +
    • >>   hal_gpio_config_pad +
    • >>   hal_gpio_init_input +
    • >>   hal_gpio_init_eint +
    + +

    hal_gpio_set_output_data (Thumb, 8 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_set_output_data)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_gpio_set_output_data +
    +
    [Calls]
    • >>   drv_gpio_set_output_data +
    +
    [Called By]
    • >>   app_tx_panel_reset +
    • >>   ap_dcs_set_enter_sleep_mode +
    + +

    hal_internal_sync_get_hight_performan_mode (Thumb, 10 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode)) +

    [Called By]

    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_init_dpi_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   hal_intl_fb_check_bandwidth +
    + +

    hal_internal_sync_input_resolution_change (Thumb, 336 bytes, Stack size 64 bytes, hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change)) +

    [Stack]

    • Max Depth = 616
    • Call Chain = hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_vidc_enable +
    • >>   hal_dsi_tx_ctrl_gen_a_tear_signal +
    • >>   hal_dsi_rx_ctrl_start +
    • >>   hal_dsi_rx_ctrl_init +
    • >>   delayUs +
    • >>   tau_log_printf +
    • >>   hal_intl_fb_cal_fb_info +
    • >>   drv_vidc_reset +
    • >>   drv_rxbr_clear_status0 +
    • >>   hal_vsync_reset_lcdc_scaler +
    • >>   hal_internal_vsync_set_tear_mode +
    • >>   hal_internal_vsync_get_sync_line +
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_toggle_resolution +
    + +

    hal_internal_sync_register_lcdc_cb (Thumb, 8 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.hal_internal_sync_register_lcdc_cb)) +

    [Called By]

    • >>   hal_dsi_tx_ctrl_init +
    • >>   hal_dsi_tx_ctrl_deinit +
    + +

    hal_internal_vsync_deinit (Thumb, 22 bytes, Stack size 8 bytes, hal_internal_vsync.o(i.hal_internal_vsync_deinit)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_internal_vsync_deinit +
    +
    [Calls]
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   hal_internal_vsync_set_rx_state +
    • >>   hal_internal_vsync_set_tx_state +
    + +

    hal_internal_vsync_get_rx_state (Thumb, 6 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.hal_internal_vsync_get_rx_state)) +

    [Called By]

    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    hal_internal_vsync_get_sync_line (Thumb, 16 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line)) +

    [Called By]

    • >>   hal_lcdc_timinggen_config +
    • >>   hal_internal_sync_input_resolution_change +
    • >>   hal_internal_vsync_set_tear_mode +
    + +

    hal_internal_vsync_get_tx_state (Thumb, 6 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state)) +

    [Called By]

    • >>   hal_tx_frame_rate_adjust +
    • >>   hal_dsi_tx_send_cmd +
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_tx_ctrl_write_array_cmd +
    • >>   hal_dsi_rx_ctrl_deinit +
    • >>   svs_wait_start +
    + +

    hal_internal_vsync_init_rx (Thumb, 206 bytes, Stack size 56 bytes, hal_internal_vsync.o(i.hal_internal_vsync_init_rx)) +

    [Stack]

    • Max Depth = 216
    • Call Chain = hal_internal_vsync_init_rx ⇒ hal_intl_svs_init_rx ⇒ hal_intl_svs_update_rxbr_clk ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   hal_intl_svs_init_rx +
    • >>   hal_intl_fb_cal_fb_info +
    • >>   hal_intl_dcs_init_sw_fltr +
    • >>   drv_vidc_register_callback +
    • >>   drv_rxbr_register_irq1_callback +
    • >>   dcs_packet_fifo_init +
    • >>   soft_pro_motion_init +
    • >>   check_mipi_rx_tx_video_info +
    • >>   hal_intl_fb_get_user_flow +
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    + +

    hal_internal_vsync_init_tx (Thumb, 194 bytes, Stack size 80 bytes, hal_internal_vsync.o(i.hal_internal_vsync_init_tx)) +

    [Stack]

    • Max Depth = 220
    • Call Chain = hal_internal_vsync_init_tx ⇒ hal_intl_fb_cal_fb_info ⇒ hal_intl_fb_edge_resize ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   hal_intl_fb_cal_fb_info +
    • >>   check_mipi_rx_tx_video_info +
    • >>   __aeabi_memclr4 +
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_init +
    + +

    hal_internal_vsync_set_rx_state (Thumb, 28 bytes, Stack size 8 bytes, hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_internal_vsync_set_rx_state ⇒ hal_intl_svs_deinit_rx +
    +
    [Calls]
    • >>   hal_intl_svs_deinit_rx +
    • >>   hal_internal_vsync_deinit +
    • >>   hal_intl_fb_get_user_flow +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_stop +
    • >>   hal_dsi_rx_ctrl_start +
    • >>   hal_dsi_rx_ctrl_init +
    • >>   hal_dsi_rx_ctrl_deinit +
    + +

    hal_internal_vsync_set_tear_mode (Thumb, 424 bytes, Stack size 32 bytes, hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode)) +

    [Stack]

    • Max Depth = 368
    • Call Chain = hal_internal_vsync_set_tear_mode ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_lcdc_config_int_single +
    • >>   drv_memc_set_tear_mode +
    • >>   tau_log_printf +
    • >>   drv_memc_set_frame_drop_select +
    • >>   drv_lcdc_set_tear_line +
    • >>   drv_lcdc_config_acc_command_mode +
    • >>   hal_internal_vsync_get_sync_line +
    • >>   drv_lcdc_function_enable +
    • >>   drv_lcdc_function_disable +
    • >>   __aeabi_idivmod +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_internal_sync_input_resolution_change +
    • >>   hal_dsi_tx_ctrl_set_tear_mode +
    + +

    hal_internal_vsync_set_tx_state (Thumb, 78 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_internal_vsync_set_tx_state ⇒ hal_internal_vsync_deinit +
    +
    [Calls]
    • >>   hal_intl_svs_deinit_tx +
    • >>   hal_internal_vsync_deinit +
    • >>   soft_pro_motion_init +
    • >>   hal_intl_fb_get_user_flow +
    • >>   drv_lcdc_function_disable +
    +
    [Called By]
    • >>   hal_tx_frame_rate_adjust +
    • >>   hal_dsi_tx_ctrl_stop +
    • >>   hal_dsi_tx_ctrl_start +
    • >>   hal_dsi_tx_ctrl_init +
    • >>   hal_dsi_tx_ctrl_deinit +
    + +

    hal_intl_dcs_init_sw_fltr (Thumb, 90 bytes, Stack size 28 bytes, hal_internal_dcs.o(i.hal_intl_dcs_init_sw_fltr)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = hal_intl_dcs_init_sw_fltr +
    +
    [Called By]
    • >>   hal_internal_vsync_init_rx +
    + +

    hal_intl_dcs_set_auto_hw_filter (Thumb, 130 bytes, Stack size 48 bytes, hal_internal_dcs.o(i.hal_intl_dcs_set_auto_hw_filter)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = hal_intl_dcs_set_auto_hw_filter +
    +
    [Calls]
    • >>   drv_rxbr_set_filter_regs +
    • >>   __aeabi_memset +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    + +

    hal_intl_fb_cal_fb_info (Thumb, 780 bytes, Stack size 80 bytes, hal_internal_fb.o(i.hal_intl_fb_cal_fb_info)) +

    [Stack]

    • Max Depth = 140
    • Call Chain = hal_intl_fb_cal_fb_info ⇒ hal_intl_fb_edge_resize ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   hal_intl_fb_flow_control_adapter +
    • >>   hal_intl_fb_edge_resize +
    • >>   hal_intl_fb_check_bandwidth +
    • >>   ha_intl_fb_check_pu_size +
    • >>   __aeabi_memcpy +
    • >>   __aeabi_memclr4 +
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_internal_vsync_init_rx +
    • >>   hal_internal_sync_input_resolution_change +
    • >>   hal_internal_vsync_init_tx +
    + +

    hal_intl_fb_get_memc_flow_mode (Thumb, 6 bytes, Stack size 0 bytes, hal_internal_fb.o(i.hal_intl_fb_get_memc_flow_mode)) +

    [Called By]

    • >>   hal_lcdc_timinggen_config +
    • >>   hal_lcdc_start +
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    • >>   hal_dsi_rx_ctrl_init_memc +
    • >>   hal_dsi_tx_ctrl_start +
    + +

    hal_intl_fb_get_rx_fb_info (Thumb, 12 bytes, Stack size 8 bytes, hal_internal_fb.o(i.hal_intl_fb_get_rx_fb_info)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_intl_fb_get_rx_fb_info +
    +
    [Calls]
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_vidc +
    • >>   hal_dsi_rx_ctrl_init_rxbr +
    • >>   hal_dsi_rx_ctrl_init_memc +
    • >>   svs_direct_mode_setting +
    + +

    hal_intl_fb_get_tx_fb_info (Thumb, 12 bytes, Stack size 8 bytes, hal_internal_fb.o(i.hal_intl_fb_get_tx_fb_info)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_intl_fb_get_tx_fb_info +
    +
    [Calls]
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_lcdc_postproc_config +
    • >>   hal_lcdc_init_cfg +
    + +

    hal_intl_fb_get_user_flow (Thumb, 6 bytes, Stack size 0 bytes, hal_internal_fb.o(i.hal_intl_fb_get_user_flow)) +

    [Called By]

    • >>   hal_lcdc_start +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_internal_vsync_set_rx_state +
    • >>   hal_internal_vsync_init_rx +
    • >>   hal_intl_svs_init_rx +
    • >>   rxbr_irq1_callback +
    • >>   hal_internal_vsync_set_tx_state +
    + +

    hal_intl_svs_deinit_rx (Thumb, 32 bytes, Stack size 8 bytes, hal_internal_svs.o(i.hal_intl_svs_deinit_rx)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_intl_svs_deinit_rx +
    +
    [Calls]
    • >>   drv_rxbr_set_inten +
    +
    [Called By]
    • >>   hal_internal_vsync_set_rx_state +
    + +

    hal_intl_svs_deinit_tx (Thumb, 10 bytes, Stack size 0 bytes, hal_internal_svs.o(i.hal_intl_svs_deinit_tx)) +

    [Called By]

    • >>   hal_internal_vsync_set_tx_state +
    + +

    hal_intl_svs_handle (Thumb, 24 bytes, Stack size 8 bytes, hal_internal_svs.o(i.hal_intl_svs_handle)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_intl_svs_handle +
    +
    [Called By]
    • >>   rxbr_irq1_callback +
    + +

    hal_intl_svs_init_rx (Thumb, 120 bytes, Stack size 16 bytes, hal_internal_svs.o(i.hal_intl_svs_init_rx)) +

    [Stack]

    • Max Depth = 160
    • Call Chain = hal_intl_svs_init_rx ⇒ hal_intl_svs_update_rxbr_clk ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   hal_intl_svs_update_rxbr_clk +
    • >>   drv_rxbr_set_inten +
    • >>   hal_intl_fb_get_user_flow +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   hal_internal_vsync_init_rx +
    + +

    hal_intl_svs_init_tx (Thumb, 16 bytes, Stack size 8 bytes, hal_internal_svs.o(i.hal_intl_svs_init_tx)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_intl_svs_init_tx +
    +
    [Called By]
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    + +

    hal_intl_svs_set_rx_vtt (Thumb, 6 bytes, Stack size 0 bytes, hal_internal_svs.o(i.hal_intl_svs_set_rx_vtt)) +

    [Called By]

    • >>   rxbr_irq1_callback +
    + +

    hal_intl_svs_update_rxbr_clk (Thumb, 52 bytes, Stack size 16 bytes, hal_internal_svs.o(i.hal_intl_svs_update_rxbr_clk)) +

    [Stack]

    • Max Depth = 144
    • Call Chain = hal_intl_svs_update_rxbr_clk ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   drv_crgu_get_rxbr_clk +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_dmul +
    +
    [Called By]
    • >>   hal_intl_svs_init_rx +
    + +

    hal_lcdc_displayproc_config (Thumb, 94 bytes, Stack size 24 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_displayproc_config)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_lcdc_displayproc_config +
    +
    [Calls]
    • >>   drv_lcdc_endianness_config +
    • >>   drv_lcdc_crop_hact +
    +
    [Called By]
    • >>   hal_lcdc_init_cfg +
    + +

    hal_lcdc_postproc_config (Thumb, 276 bytes, Stack size 88 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_postproc_config)) +

    [Stack]

    • Max Depth = 232
    • Call Chain = hal_lcdc_postproc_config ⇒ hal_lcdc_upscaler_config ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   drv_lcdc_fc_config +
    • >>   drv_lcdc_edge_enh_config +
    • >>   drv_lcdc_edge_dect_config +
    • >>   drv_lcdc_dith_config +
    • >>   drv_lcdc_bcsa_config +
    • >>   hal_lcdc_upscaler_config +
    • >>   hal_intl_fb_get_tx_fb_info +
    • >>   drv_lcdc_vintp_mode_config +
    • >>   drv_lcdc_function_enable +
    • >>   drv_lcdc_function_disable +
    • >>   drv_lcdc_fldc_config +
    +
    [Called By]
    • >>   hal_lcdc_init_cfg +
    + +

    hal_lcdc_upscaler_config (Thumb, 202 bytes, Stack size 40 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_upscaler_config)) +

    [Stack]

    • Max Depth = 144
    • Call Chain = hal_lcdc_upscaler_config ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_ui2d +
    • >>   __aeabi_dadd +
    • >>   __aeabi_d2uiz +
    • >>   drv_lcdc_function_enable +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_lcdc_postproc_config +
    + +

    hal_nonshadow_func_update (Thumb, 180 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_nonshadow_func_update)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_nonshadow_func_update ⇒ drv_lcdc_config_int_single +
    +
    [Calls]
    • >>   drv_lcdc_fc_config +
    • >>   drv_lcdc_edge_enh_config +
    • >>   drv_lcdc_edge_dect_config +
    • >>   drv_lcdc_config_int_single +
    • >>   drv_lcdc_bcsa_config +
    +
    [Address Reference Count : 1]
    • hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) +
    +

    hal_pwr_enter_deep_sleep_mode (Thumb, 42 bytes, Stack size 8 bytes, hal_pwr.o(i.hal_pwr_enter_deep_sleep_mode)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_pwr_enter_deep_sleep_mode ⇒ drv_pwr_enter_deep_sleep_mode +
    +
    [Calls]
    • >>   drv_pwr_set_wakeup_type +
    • >>   drv_pwr_enter_deep_sleep_mode +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_pwr_enter_normal_sleep_mode (Thumb, 8 bytes, Stack size 8 bytes, hal_pwr.o(i.hal_pwr_enter_normal_sleep_mode)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_pwr_enter_normal_sleep_mode +
    +
    [Calls]
    • >>   drv_pwr_enter_sleep_mode_ex +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_pwr_enter_stop_sleep_mode (Thumb, 88 bytes, Stack size 16 bytes, hal_pwr.o(i.hal_pwr_enter_stop_sleep_mode)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = hal_pwr_enter_stop_sleep_mode ⇒ drv_pwr_enter_stop_sleep_mode +
    +
    [Calls]
    • >>   drv_pwr_enter_stop_sleep_mode +
    • >>   drv_sys_cfg_set_int +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_pwr_exit_sleep_mode (Thumb, 10 bytes, Stack size 8 bytes, hal_pwr.o(i.hal_pwr_exit_sleep_mode)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = hal_pwr_exit_sleep_mode ⇒ drv_pwr_exit_sleep_mode +
    +
    [Calls]
    • >>   drv_pwr_exit_sleep_mode +
    +
    [Called By]
    • >>   app_system_resume +
    + +

    hal_pwr_get_vcc_power_ready (Thumb, 8 bytes, Stack size 8 bytes, hal_pwr.o(i.hal_pwr_get_vcc_power_ready)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_pwr_get_vcc_power_ready +
    +
    [Calls]
    • >>   drv_pwr_get_power_ready_st +
    +
    [Called By]
    • >>   app_display_init +
    + +

    hal_pwr_set_main_power (Thumb, 8 bytes, Stack size 8 bytes, hal_pwr.o(i.hal_pwr_set_main_power)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_pwr_set_main_power ⇒ drv_pwr_set_digit_power_sel +
    +
    [Calls]
    • >>   drv_pwr_set_digit_power_sel +
    +
    [Called By]
    • >>   google_p8p_demo +
    + +

    hal_pwr_set_sleep_mode_power (Thumb, 8 bytes, Stack size 8 bytes, hal_pwr.o(i.hal_pwr_set_sleep_mode_power)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_pwr_set_sleep_mode_power ⇒ drv_pwr_set_breath_screen_power_sel +
    +
    [Calls]
    • >>   drv_pwr_set_breath_screen_power_sel +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_pwr_set_stop_sleep_wakeup_pin (Thumb, 86 bytes, Stack size 24 bytes, hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = hal_pwr_set_stop_sleep_wakeup_pin ⇒ hal_gpio_init_eint ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   hal_gpio_set_ap_reset_int +
    • >>   hal_gpio_reg_eint_cb +
    • >>   hal_gpio_init_eint +
    • >>   hal_gpio_ctrl_eint +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_swire_deinit (Thumb, 60 bytes, Stack size 8 bytes, hal_swire.o(i.hal_swire_deinit)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = hal_swire_deinit ⇒ hal_timer_deinit ⇒ drv_timer_set_int +
    +
    [Calls]
    • >>   drv_crgu_set_reset +
    • >>   drv_crgu_enable_clock +
    • >>   hal_timer_deinit +
    • >>   drv_swire_set_int +
    • >>   drv_swire_register_callback +
    • >>   drv_swire_enable +
    +
    [Called By]
    • >>   app_system_suspend +
    + +

    hal_swire_enable (Thumb, 86 bytes, Stack size 8 bytes, hal_swire.o(i.hal_swire_enable)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_swire_enable ⇒ drv_swire_set_int +
    +
    [Calls]
    • >>   drv_timer_enable +
    • >>   drv_swire_set_trig_mode +
    • >>   drv_swire_set_power_down +
    • >>   drv_swire_set_int +
    • >>   drv_swire_get_pulse_count +
    +
    [Called By]
    • >>   app_init_panel +
    • >>   ap_dcs_set_enter_sleep_mode +
    + +

    hal_swire_init (Thumb, 74 bytes, Stack size 8 bytes, hal_swire.o(i.hal_swire_init)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_swire_init ⇒ hal_gpio_set_mode ⇒ drv_gpio_set_mode +
    +
    [Calls]
    • >>   drv_crgu_enable_clock +
    • >>   drv_swire_set_power_down +
    • >>   drv_swire_set_bit_time +
    • >>   drv_swire_enable +
    • >>   drv_crgu_set_clock_div +
    • >>   hal_gpio_set_mode +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   app_display_init +
    + +

    hal_swire_set_pulse (Thumb, 32 bytes, Stack size 8 bytes, hal_swire.o(i.hal_swire_set_pulse)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_swire_set_pulse +
    +
    [Calls]
    • >>   drv_swire_set_trig_mode +
    • >>   drv_swire_set_pulse_count +
    +
    [Called By]
    • >>   app_mipi_tx_start +
    • >>   app_init_panel +
    + +

    hal_swire_set_timer (Thumb, 60 bytes, Stack size 24 bytes, hal_swire.o(i.hal_swire_set_timer)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = hal_swire_set_timer ⇒ drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   hal_timer_init +
    • >>   hal_timer_set_repeat +
    • >>   drv_timer_set_compare_val +
    • >>   drv_sys_cfg_sel_swire_timer +
    • >>   drv_swire_set_trig_mode +
    +
    [Called By]
    • >>   app_display_init +
    + +

    hal_system_init (Thumb, 192 bytes, Stack size 8 bytes, hal_system.o(i.hal_system_init)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = hal_system_init ⇒ drv_common_system_init ⇒ drv_se_init ⇒ drv_efuse_read +
    +
    [Calls]
    • >>   drv_pwr_set_pll_clk +
    • >>   drv_crgu_enable_clock +
    • >>   drv_sys_cfg_clear_all_int +
    • >>   drv_common_system_init +
    • >>   hal_system_updata_sysclk +
    • >>   hal_gpio_set_mode +
    +
    [Called By]
    • >>   board_Init +
    + +

    hal_system_updata_sysclk (Thumb, 60 bytes, Stack size 8 bytes, hal_system.o(i.hal_system_updata_sysclk)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_system_updata_sysclk ⇒ drv_crgu_set_ahb_clk +
    +
    [Calls]
    • >>   drv_crgu_set_ahb_clk +
    +
    [Called By]
    • >>   hal_system_init +
    + +

    hal_timer_deinit (Thumb, 48 bytes, Stack size 8 bytes, hal_timer.o(i.hal_timer_deinit)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_timer_deinit ⇒ drv_timer_set_int +
    +
    [Calls]
    • >>   drv_crgu_set_reset +
    • >>   drv_crgu_enable_clock +
    • >>   drv_timer_set_repeat +
    • >>   drv_timer_set_int +
    • >>   drv_timer_enable +
    +
    [Called By]
    • >>   hal_swire_deinit +
    + +

    hal_timer_init (Thumb, 28 bytes, Stack size 8 bytes, hal_timer.o(i.hal_timer_init)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = hal_timer_init ⇒ drv_timer_set_prescaler +
    +
    [Calls]
    • >>   drv_crgu_enable_clock +
    • >>   drv_timer_set_prescaler +
    +
    [Called By]
    • >>   hal_swire_set_timer +
    + +

    hal_timer_set_repeat (Thumb, 8 bytes, Stack size 8 bytes, hal_timer.o(i.hal_timer_set_repeat)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_timer_set_repeat +
    +
    [Calls]
    • >>   drv_timer_set_repeat +
    +
    [Called By]
    • >>   hal_swire_set_timer +
    + +

    hal_uart_init (Thumb, 134 bytes, Stack size 48 bytes, hal_uart.o(i.hal_uart_init)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = hal_uart_init ⇒ drv_uart_init ⇒ drv_uart_set_baud_rate ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_uart_trans_create_handle +
    • >>   drv_uart_init +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   tau_log_init +
    + +

    hal_uart_send_blocking (Thumb, 24 bytes, Stack size 16 bytes, hal_uart.o(i.hal_uart_send_blocking)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_uart_send_blocking +
    +
    [Calls]
    • >>   drv_uart_send_blocking +
    +
    [Called By]
    • >>   fputc +
    + +

    hal_vsync_func_update (Thumb, 18 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_vsync_func_update)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_vsync_func_update ⇒ drv_lcdc_config_int_single +
    +
    [Calls]
    • >>   drv_lcdc_config_int_single +
    +
    [Address Reference Count : 1]
    • hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) +
    +

    hal_vsync_reset_lcdc_scaler (Thumb, 206 bytes, Stack size 48 bytes, hal_internal_vsync.o(i.hal_vsync_reset_lcdc_scaler)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = hal_vsync_reset_lcdc_scaler ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_ui2d +
    • >>   __aeabi_dadd +
    • >>   __aeabi_d2uiz +
    • >>   soft_pro_motion_init +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_internal_sync_input_resolution_change +
    + +

    main (Thumb, 32 bytes, Stack size 0 bytes, main.o(i.main)) +

    [Stack]

    • Max Depth = 656
    • Call Chain = main ⇒ google_p8p_demo ⇒ app_system_process ⇒ app_system_resume ⇒ app_display_init ⇒ app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    • >>   google_p8p_demo +
    • >>   board_Init +
    +
    [Address Reference Count : 1]
    • entry9a.o(.ARM.Collect$$$$0000000B) +
    +

    tau_log_init (Thumb, 48 bytes, Stack size 32 bytes, tau_log.o(i.tau_log_init)) +

    [Stack]

    • Max Depth = 132
    • Call Chain = tau_log_init ⇒ hal_uart_init ⇒ drv_uart_init ⇒ drv_uart_set_baud_rate ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   hal_uart_init +
    +
    [Called By]
    • >>   board_Init +
    + +

    tau_log_printf (Thumb, 116 bytes, Stack size 296 bytes, tau_log.o(i.tau_log_printf)) +

    [Stack]

    • Max Depth = 336
    • Call Chain = tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_push_log +
    • >>   vsprintf +
    • >>   __2printf +
    • >>   strlen +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    • >>   hal_internal_sync_input_resolution_change +
    • >>   hal_dsi_rx_ctrl_send_ack_cmd +
    • >>   app_system_suspend +
    • >>   app_system_resume +
    • >>   app_system_process +
    • >>   app_mipi_tx_start +
    • >>   app_mipi_tx_init +
    • >>   app_mipi_rx_init +
    • >>   ap_rstn_pull_down_cb +
    • >>   ap_dcs_set_exit_sleep_mode +
    • >>   ap_dcs_set_enter_sleep_mode +
    • >>   ap_dcs_set_display_on +
    • >>   ap_dcs_set_display_off +
    • >>   ap_dcs_read +
    • >>   google_p8p_demo +
    • >>   main +
    • >>   drv_se_set_dsc +
    • >>   HardFault_Handler +
    • >>   svs_wait_fr_stab +
    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    • >>   check_pkt_buf_rev +
    • >>   LCDC_IRQn_Handler +
    • >>   vidc_callback +
    • >>   rxbr_irq1_callback +
    • >>   hal_internal_vsync_set_tear_mode +
    • >>   MIPI_TX_IRQn_Handler +
    • >>   MIPI_RX_IRQn_Handler +
    • >>   drv_se_set_vidc +
    • >>   drv_se_set_rxbr +
    • >>   drv_se_set_memc +
    • >>   drv_se_set_lcdc +
    + +

    tau_log_push_log (Thumb, 118 bytes, Stack size 32 bytes, tau_log.o(i.tau_log_push_log)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   delayUs +
    • >>   __aeabi_memcpy +
    +
    [Called By]
    • >>   tau_log_printf +
    • >>   fputc +
    +

    +

    +Local Symbols +

    +

    ap_dcs_read (Thumb, 280 bytes, Stack size 72 bytes, p8p_demo.o(i.ap_dcs_read)) +

    [Stack]

    • Max Depth = 456
    • Call Chain = ap_dcs_read ⇒ hal_dsi_rx_ctrl_send_ack_cmd ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_dsi_rx_ctrl_send_ack_cmd +
    • >>   hal_dsi_rx_ctrl_get_max_ret_size +
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(i.app_mipi_rx_init) +
    +

    ap_dcs_set_backlight (Thumb, 130 bytes, Stack size 24 bytes, p8p_demo.o(i.ap_dcs_set_backlight)) +

    [Stack]

    • Max Depth = 108
    • Call Chain = ap_dcs_set_backlight ⇒ hal_dsi_tx_ctrl_write_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   __aeabi_idivmod +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    ap_dcs_set_display_off (Thumb, 34 bytes, Stack size 16 bytes, p8p_demo.o(i.ap_dcs_set_display_off)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = ap_dcs_set_display_off ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    ap_dcs_set_display_on (Thumb, 90 bytes, Stack size 16 bytes, p8p_demo.o(i.ap_dcs_set_display_on)) +

    [Stack]

    • Max Depth = 640
    • Call Chain = ap_dcs_set_display_on ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_rx_ctrl_toggle_resolution +
    • >>   hal_dsi_rx_ctrl_pre_init_pps +
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    ap_dcs_set_enter_sleep_mode (Thumb, 104 bytes, Stack size 16 bytes, p8p_demo.o(i.ap_dcs_set_enter_sleep_mode)) +

    [Stack]

    • Max Depth = 392
    • Call Chain = ap_dcs_set_enter_sleep_mode ⇒ hal_dsi_tx_ctrl_set_tear_mode ⇒ hal_internal_vsync_set_tear_mode ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_swire_enable +
    • >>   hal_gpio_set_output_data +
    • >>   hal_gpio_set_ap_reset_int +
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_tx_ctrl_set_tear_mode +
    • >>   delayMs +
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    ap_dcs_set_exit_sleep_mode (Thumb, 28 bytes, Stack size 16 bytes, p8p_demo.o(i.ap_dcs_set_exit_sleep_mode)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = ap_dcs_set_exit_sleep_mode ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    ap_dcs_set_frame_change (Thumb, 46 bytes, Stack size 16 bytes, p8p_demo.o(i.ap_dcs_set_frame_change)) +

    [Stack]

    • Max Depth = 392
    • Call Chain = ap_dcs_set_frame_change ⇒ hal_dsi_tx_ctrl_set_tear_mode ⇒ hal_internal_vsync_set_tear_mode ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_set_tear_mode +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    ap_rstn_pull_down_cb (Thumb, 38 bytes, Stack size 8 bytes, p8p_demo.o(i.ap_rstn_pull_down_cb)) +

    [Stack]

    • Max Depth = 344
    • Call Chain = ap_rstn_pull_down_cb ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_gpio_set_ap_reset_int +
    • >>   tau_log_printf +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(i.ap_dcs_set_enter_sleep_mode) +
    +

    ap_rstn_pull_high_cb (Thumb, 22 bytes, Stack size 8 bytes, p8p_demo.o(i.ap_rstn_pull_high_cb)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = ap_rstn_pull_high_cb ⇒ hal_gpio_set_ap_reset_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   hal_gpio_set_ap_reset_int +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(i.app_system_suspend) +
    +

    ap_set_FPS_53 (Thumb, 74 bytes, Stack size 32 bytes, p8p_demo.o(i.ap_set_FPS_53)) +

    [Stack]

    • Max Depth = 116
    • Call Chain = ap_set_FPS_53 ⇒ hal_dsi_tx_ctrl_write_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_write_cmd +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(.constdata) +
    +

    app_init_panel (Thumb, 42 bytes, Stack size 8 bytes, p8p_demo.o(i.app_init_panel)) +

    [Stack]

    • Max Depth = 124
    • Call Chain = app_init_panel ⇒ send_panel_init_code ⇒ hal_dsi_tx_ctrl_write_array_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   hal_swire_set_pulse +
    • >>   hal_swire_enable +
    • >>   hal_gpio_init_output +
    • >>   delayMs +
    • >>   send_panel_init_code +
    • >>   app_tx_panel_reset +
    +
    [Called By]
    • >>   app_mipi_tx_start +
    + +

    app_mipi_rx_init (Thumb, 232 bytes, Stack size 8 bytes, p8p_demo.o(i.app_mipi_rx_init)) +

    [Stack]

    • Max Depth = 560
    • Call Chain = app_mipi_rx_init ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_dsi_rx_ctrl_start +
    • >>   hal_dsi_rx_ctrl_pre_init_pps +
    • >>   hal_dsi_rx_ctrl_init +
    • >>   hal_dsi_rx_ctrl_create_handle +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   app_display_init +
    + +

    app_mipi_tx_init (Thumb, 214 bytes, Stack size 8 bytes, p8p_demo.o(i.app_mipi_tx_init)) +

    [Stack]

    • Max Depth = 440
    • Call Chain = app_mipi_tx_init ⇒ hal_dsi_tx_ctrl_init ⇒ hal_dsi_tx_init_timing ⇒ hal_dsi_tx_cmd_mode_cal_timing ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_set_overwrite_rgb +
    • >>   hal_dsi_tx_ctrl_init +
    • >>   hal_dsi_tx_ctrl_create_handle +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   app_display_init +
    + +

    app_mipi_tx_start (Thumb, 112 bytes, Stack size 8 bytes, p8p_demo.o(i.app_mipi_tx_start)) +

    [Stack]

    • Max Depth = 632
    • Call Chain = app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_swire_set_pulse +
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_tx_ctrl_start +
    • >>   hal_dsi_tx_ctrl_set_tear_mode +
    • >>   hal_dsi_rx_ctrl_toggle_resolution +
    • >>   hal_dsi_rx_ctrl_pre_init_pps +
    • >>   delayMs +
    • >>   app_init_panel +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   app_display_init +
    + +

    app_system_process (Thumb, 60 bytes, Stack size 8 bytes, p8p_demo.o(i.app_system_process)) +

    [Stack]

    • Max Depth = 656
    • Call Chain = app_system_process ⇒ app_system_resume ⇒ app_display_init ⇒ app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   app_system_suspend +
    • >>   app_system_resume +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   google_p8p_demo +
    + +

    app_system_resume (Thumb, 30 bytes, Stack size 8 bytes, p8p_demo.o(i.app_system_resume)) +

    [Stack]

    • Max Depth = 648
    • Call Chain = app_system_resume ⇒ app_display_init ⇒ app_mipi_tx_start ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_pwr_exit_sleep_mode +
    • >>   app_display_init +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   app_system_process +
    + +

    app_system_suspend (Thumb, 202 bytes, Stack size 16 bytes, p8p_demo.o(i.app_system_suspend)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = app_system_suspend ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_swire_deinit +
    • >>   hal_pwr_set_stop_sleep_wakeup_pin +
    • >>   hal_pwr_set_sleep_mode_power +
    • >>   hal_pwr_enter_stop_sleep_mode +
    • >>   hal_pwr_enter_normal_sleep_mode +
    • >>   hal_pwr_enter_deep_sleep_mode +
    • >>   hal_gpio_set_ap_reset_int +
    • >>   hal_gpio_init_output +
    • >>   hal_dsi_tx_ctrl_stop +
    • >>   hal_dsi_tx_ctrl_deinit +
    • >>   hal_dsi_rx_ctrl_stop +
    • >>   hal_dsi_rx_ctrl_deinit +
    • >>   tau_log_printf +
    +
    [Called By]
    • >>   app_system_process +
    + +

    app_tx_panel_reset (Thumb, 46 bytes, Stack size 8 bytes, p8p_demo.o(i.app_tx_panel_reset)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = app_tx_panel_reset ⇒ delayMs ⇒ delayUs +
    +
    [Calls]
    • >>   hal_gpio_set_output_data +
    • >>   delayMs +
    +
    [Called By]
    • >>   app_init_panel +
    + +

    pps_update_handle (Thumb, 110 bytes, Stack size 24 bytes, p8p_demo.o(i.pps_update_handle)) +

    [Stack]

    • Max Depth = 648
    • Call Chain = pps_update_handle ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_rx_ctrl_init ⇒ hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_set_tear_mode +
    • >>   hal_dsi_rx_ctrl_toggle_resolution +
    +
    [Address Reference Count : 1]
    • p8p_demo.o(i.app_mipi_rx_init) +
    +

    send_panel_init_code (Thumb, 58 bytes, Stack size 32 bytes, p8p_demo.o(i.send_panel_init_code)) +

    [Stack]

    • Max Depth = 116
    • Call Chain = send_panel_init_code ⇒ hal_dsi_tx_ctrl_write_array_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   hal_dsi_tx_ctrl_write_array_cmd +
    • >>   delayUs +
    +
    [Called By]
    • >>   app_init_panel +
    + +

    hal_dsi_rx_ctrl_init_clk (Thumb, 222 bytes, Stack size 32 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = hal_dsi_rx_ctrl_init_clk ⇒ drv_crgu_set_dsc_clk +
    +
    [Calls]
    • >>   drv_pwr_set_pll_clk +
    • >>   drv_crgu_set_vidc_clk +
    • >>   drv_crgu_set_rxbr_clk +
    • >>   drv_crgu_set_fb_clk +
    • >>   drv_crgu_set_dsc_clk +
    • >>   drv_crgu_enable_clock +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    + +

    hal_dsi_rx_ctrl_init_dsi_rx (Thumb, 232 bytes, Stack size 32 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx)) +

    [Stack]

    • Max Depth = 216
    • Call Chain = hal_dsi_rx_ctrl_init_dsi_rx ⇒ hal_dsi_rx_ctrl_set_ipi_cfg ⇒ drv_dsi_rx_calc_ipi_tx_delay ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   drv_dsi_rx_set_up_phy +
    • >>   drv_dsi_rx_set_tear_resp_en +
    • >>   drv_dsi_rx_set_resp_cnt +
    • >>   drv_dsi_rx_set_lane_swap +
    • >>   drv_dsi_rx_set_ipi_ycbcr_frmt +
    • >>   drv_dsi_rx_set_inten +
    • >>   drv_dsi_rx_set_ddi_crc_en +
    • >>   drv_dsi_rx_set_ddi_cfg +
    • >>   drv_dsi_rx_set_ctrl_cfg +
    • >>   drv_dsi_rx_set_check_crc +
    • >>   drv_dsi_rx_enable_irq +
    • >>   drv_crgu_get_rxbr_clk +
    • >>   hal_dsi_rx_ctrl_set_ipi_cfg +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    + +

    hal_dsi_rx_ctrl_init_memc (Thumb, 294 bytes, Stack size 80 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc)) +

    [Stack]

    • Max Depth = 432
    • Call Chain = hal_dsi_rx_ctrl_init_memc ⇒ drv_memc_set_ltpo_mode ⇒ drv_se_set_memc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_intl_fb_get_rx_fb_info +
    • >>   hal_intl_fb_get_memc_flow_mode +
    • >>   drv_memc_set_vidc_sync_cnt +
    • >>   drv_memc_set_tear_waveform +
    • >>   drv_memc_set_tear_mode +
    • >>   drv_memc_set_ltpo_pu_thres +
    • >>   drv_memc_set_ltpo_mode +
    • >>   drv_memc_set_lcdc_st_conditions +
    • >>   drv_memc_set_fs_en_conditions +
    • >>   drv_memc_set_double_buffer +
    • >>   drv_memc_set_data_mode +
    • >>   drv_memc_set_circ_mode_enable +
    • >>   drv_memc_set_active_height +
    • >>   drv_memc_sel_vsync +
    • >>   drv_memc_rate_transfer_sel +
    • >>   drv_memc_enable_irq +
    • >>   __ARM_common_switch8 +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    + +

    hal_dsi_rx_ctrl_init_rxbr (Thumb, 314 bytes, Stack size 144 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr)) +

    [Stack]

    • Max Depth = 504
    • Call Chain = hal_dsi_rx_ctrl_init_rxbr ⇒ drv_rxbr_set_color_format ⇒ drv_se_set_rxbr ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_intl_fb_get_rx_fb_info +
    • >>   hal_intl_fb_get_memc_flow_mode +
    • >>   hal_intl_dcs_set_auto_hw_filter +
    • >>   drv_rxbr_set_usr_row +
    • >>   drv_rxbr_set_usr_col +
    • >>   drv_rxbr_set_usr_cfg +
    • >>   drv_rxbr_set_ltpo_drop_th +
    • >>   drv_rxbr_set_inten +
    • >>   drv_rxbr_set_color_format +
    • >>   drv_rxbr_hline_rcv_cfg +
    • >>   drv_rxbr_frame_drop_cfg +
    • >>   drv_rxbr_enable_irq +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    + +

    hal_dsi_rx_ctrl_init_vidc (Thumb, 624 bytes, Stack size 168 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc)) +

    [Stack]

    • Max Depth = 536
    • Call Chain = hal_dsi_rx_ctrl_init_vidc ⇒ drv_vidc_set_src_parameter ⇒ drv_se_set_vidc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_intl_fb_get_rx_fb_info +
    • >>   drv_vidc_set_vintp_config +
    • >>   drv_vidc_set_src_parameter +
    • >>   drv_vidc_set_scld_vcoef1 +
    • >>   drv_vidc_set_scld_vcoef0 +
    • >>   drv_vidc_set_scld_step +
    • >>   drv_vidc_set_scld_hcoef1 +
    • >>   drv_vidc_set_scld_hcoef0 +
    • >>   drv_vidc_set_rotation +
    • >>   drv_vidc_set_pu_ctrl +
    • >>   drv_vidc_set_pentile_swap +
    • >>   drv_vidc_set_mirror +
    • >>   drv_vidc_set_irqen +
    • >>   drv_vidc_set_honly_hinitr +
    • >>   drv_vidc_set_honly_hinitb +
    • >>   drv_vidc_set_honly_hcoef0 +
    • >>   drv_vidc_set_dst_parameter +
    • >>   drv_vidc_set_dither_config +
    • >>   drv_vidc_set_circ_mode_enable +
    • >>   drv_vidc_init_module_enable +
    • >>   drv_vidc_enable_irq +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_dadd +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_uidivmod +
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init +
    + +

    hal_dsi_rx_ctrl_set_ipi_cfg (Thumb, 48 bytes, Stack size 24 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg)) +

    [Stack]

    • Max Depth = 184
    • Call Chain = hal_dsi_rx_ctrl_set_ipi_cfg ⇒ drv_dsi_rx_calc_ipi_tx_delay ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   drv_dsi_rx_set_ipi_cfg +
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    +
    [Called By]
    • >>   hal_dsi_rx_ctrl_init_dsi_rx +
    + +

    hal_dsi_tx_cmd_mode_cal_timing (Thumb, 510 bytes, Stack size 64 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_cmd_mode_cal_timing)) +

    [Stack]

    • Max Depth = 400
    • Call Chain = hal_dsi_tx_cmd_mode_cal_timing ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fmul +
    • >>   __aeabi_fadd +
    • >>   __aeabi_f2d +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_d2uiz +
    • >>   tau_log_printf +
    • >>   hal_internal_sync_get_hight_performan_mode +
    • >>   __aeabi_idivmod +
    • >>   __aeabi_uidivmod +
    • >>   ceil +
    +
    [Called By]
    • >>   hal_dsi_tx_init_timing +
    + +

    hal_dsi_tx_ctrl_init_clk (Thumb, 12 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = hal_dsi_tx_ctrl_init_clk +
    +
    [Calls]
    • >>   drv_crgu_enable_clock +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_init +
    + +

    hal_dsi_tx_init_cfg (Thumb, 250 bytes, Stack size 80 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_cfg)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = hal_dsi_tx_init_cfg ⇒ drv_dsi_tx_set_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_dsi_tx_video_mode_cfg +
    • >>   drv_dsi_tx_timeout_cfg +
    • >>   drv_dsi_tx_set_time_out_div +
    • >>   drv_dsi_tx_set_int +
    • >>   drv_dsi_tx_set_esc_div +
    • >>   drv_dsi_tx_set_bta_ack +
    • >>   drv_dsi_tx_response_mode +
    • >>   drv_dsi_tx_phy_lane_mode +
    • >>   drv_dsi_tx_phy_clock_lane_req_hs +
    • >>   drv_dsi_tx_phy_clock_lane_auto_lp +
    • >>   drv_dsi_tx_mode +
    • >>   drv_dsi_tx_dpi_polarity +
    • >>   drv_dsi_tx_dpi_mode +
    • >>   drv_dsi_tx_dpi_lpcmd_time +
    • >>   drv_dsi_tx_config_int +
    • >>   drv_dsi_tx_config_eotp +
    • >>   drv_dsi_tx_command_mode_cfg +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_init +
    + +

    hal_dsi_tx_init_dpi_timing (Thumb, 58 bytes, Stack size 40 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_timing)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = hal_dsi_tx_init_dpi_timing ⇒ drv_crgu_set_dpi_clk +
    +
    [Calls]
    • >>   drv_crgu_set_dpi_clk +
    • >>   hal_internal_sync_get_hight_performan_mode +
    • >>   __aeabi_uidivmod +
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_dsi_tx_init_timing +
    + +

    hal_dsi_tx_init_phy_cfg (Thumb, 22 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = hal_dsi_tx_init_phy_cfg ⇒ drv_dsi_tx_phy_test_setup ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_dsi_tx_phy_time_cfg +
    • >>   drv_dsi_tx_phy_test_setup +
    +
    [Called By]
    • >>   hal_dsi_tx_init_timing +
    + +

    hal_dsi_tx_init_timing (Thumb, 82 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_timing)) +

    [Stack]

    • Max Depth = 416
    • Call Chain = hal_dsi_tx_init_timing ⇒ hal_dsi_tx_cmd_mode_cal_timing ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_dsi_tx_edpi_cmd_size +
    • >>   hal_dsi_tx_vid_mode_cal_timing +
    • >>   hal_dsi_tx_timing_info_update +
    • >>   hal_dsi_tx_init_vid_timing +
    • >>   hal_dsi_tx_init_phy_cfg +
    • >>   hal_dsi_tx_init_dpi_timing +
    • >>   hal_dsi_tx_cmd_mode_cal_timing +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_init +
    + +

    hal_dsi_tx_init_vid_timing (Thumb, 70 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_vid_timing)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = hal_dsi_tx_init_vid_timing +
    +
    [Calls]
    • >>   drv_dsi_tx_set_video_timing +
    • >>   drv_dsi_tx_set_video_chunk +
    +
    [Called By]
    • >>   hal_dsi_tx_init_timing +
    + +

    hal_dsi_tx_send_cmd (Thumb, 58 bytes, Stack size 24 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   drv_dsi_tx_phy_status_stopstate +
    • >>   drv_dsi_tx_get_cmd_status +
    • >>   drv_dsi_tx_command_header +
    • >>   hal_internal_vsync_get_tx_state +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_write_cmd +
    • >>   hal_dsi_tx_ctrl_write_array_cmd +
    + +

    hal_dsi_tx_timing_info_update (Thumb, 142 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_timing_info_update)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = hal_dsi_tx_timing_info_update ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_d2f +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_dsi_tx_init_timing +
    + +

    hal_dsi_tx_vid_mode_cal_timing (Thumb, 766 bytes, Stack size 96 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing)) +

    [Stack]

    • Max Depth = 232
    • Call Chain = hal_dsi_tx_vid_mode_cal_timing ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fmul +
    • >>   __aeabi_f2d +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_d2uiz +
    • >>   hal_intl_svs_init_tx +
    • >>   hal_intl_fb_get_user_flow +
    • >>   hal_internal_sync_get_hight_performan_mode +
    • >>   __aeabi_idivmod +
    • >>   __aeabi_uidivmod +
    • >>   ceil +
    +
    [Called By]
    • >>   hal_dsi_tx_init_timing +
    + +

    hal_lcdc_init_cfg (Thumb, 62 bytes, Stack size 88 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg)) +

    [Stack]

    • Max Depth = 320
    • Call Chain = hal_lcdc_init_cfg ⇒ hal_lcdc_postproc_config ⇒ hal_lcdc_upscaler_config ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   drv_lcdc_config_int +
    • >>   hal_lcdc_postproc_config +
    • >>   hal_lcdc_displayproc_config +
    • >>   hal_lcdc_timinggen_config +
    • >>   hal_intl_fb_get_tx_fb_info +
    • >>   drv_lcdc_set_int +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_init +
    + +

    hal_lcdc_init_clk (Thumb, 112 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = hal_lcdc_init_clk ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   drv_crgu_set_lcdc_clk +
    • >>   __aeabi_ui2f +
    • >>   __aeabi_f2d +
    • >>   __ARM_scalbnf +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_d2uiz +
    • >>   ceil +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_init +
    + +

    hal_lcdc_start (Thumb, 36 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_start)) +

    [Stack]

    • Max Depth = 368
    • Call Chain = hal_lcdc_start ⇒ drv_lcdc_cmd_start ⇒ drv_se_set_lcdc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_lcdc_cmd_start +
    • >>   hal_intl_fb_get_memc_flow_mode +
    • >>   hal_intl_fb_get_user_flow +
    • >>   drv_lcdc_vid_hw_start +
    +
    [Called By]
    • >>   hal_dsi_tx_ctrl_start +
    + +

    hal_lcdc_timinggen_config (Thumb, 60 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_timinggen_config)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_lcdc_timinggen_config ⇒ drv_lcdc_ctrl_flow +
    +
    [Calls]
    • >>   drv_lcdc_ctrl_flow +
    • >>   drv_lcdc_config_src_parameter +
    • >>   hal_intl_fb_get_memc_flow_mode +
    • >>   hal_internal_vsync_get_sync_line +
    • >>   drv_lcdc_set_prefetch +
    +
    [Called By]
    • >>   hal_lcdc_init_cfg +
    + +

    hal_tx_frame_rate_adjust (Thumb, 44 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust)) +

    [Stack]

    • Max Depth = 448
    • Call Chain = hal_tx_frame_rate_adjust ⇒ hal_dsi_tx_ctrl_init ⇒ hal_dsi_tx_init_timing ⇒ hal_dsi_tx_cmd_mode_cal_timing ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   __aeabi_cfcmple +
    • >>   hal_internal_vsync_get_tx_state +
    • >>   hal_dsi_tx_ctrl_init +
    • >>   hal_internal_vsync_set_tx_state +
    +
    [Address Reference Count : 1]
    • hal_dsi_tx_ctrl.o(i.hal_dsi_tx_vid_mode_cal_timing) +
    +

    drv_gpio_set_output_data (Thumb, 26 bytes, Stack size 0 bytes, hal_gpio.o(i.drv_gpio_set_output_data)) +

    [Called By]

    • >>   hal_gpio_set_output_data +
    • >>   hal_gpio_init_output +
    + +

    stop_sleep_cb (Thumb, 18 bytes, Stack size 0 bytes, hal_pwr.o(i.stop_sleep_cb)) +
    [Address Reference Count : 1]

    • hal_pwr.o(i.hal_pwr_set_stop_sleep_wakeup_pin) +
    +

    check_mipi_rx_tx_video_info (Thumb, 44 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.check_mipi_rx_tx_video_info)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = check_mipi_rx_tx_video_info +
    +
    [Called By]
    • >>   hal_internal_vsync_init_rx +
    • >>   hal_internal_vsync_init_tx +
    + +

    drv_rxbr_get_int_source (Thumb, 20 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.drv_rxbr_get_int_source)) +

    [Called By]

    • >>   rxbr_irq1_callback +
    + +

    rxbr_irq1_callback (Thumb, 496 bytes, Stack size 40 bytes, hal_internal_vsync.o(i.rxbr_irq1_callback)) +

    [Stack]

    • Max Depth = 400
    • Call Chain = rxbr_irq1_callback ⇒ drv_lcdc_cmd_start ⇒ drv_se_set_lcdc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_lcdc_cmd_start +
    • >>   drv_dsi_tx_phy_clock_lane_req_hs +
    • >>   drv_vidc_enable +
    • >>   drv_rxbr_set_inten +
    • >>   tau_log_printf +
    • >>   hal_intl_svs_set_rx_vtt +
    • >>   hal_intl_svs_handle +
    • >>   drv_rxbr_clear_status0 +
    • >>   drv_rxbr_clear_pkt_buffer +
    • >>   vpre_err_reset +
    • >>   soft_double_buffer_update +
    • >>   drv_rxbr_get_int_source +
    • >>   hal_intl_fb_get_user_flow +
    +
    [Address Reference Count : 1]
    • hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    +

    soft_double_buffer_update (Thumb, 56 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.soft_double_buffer_update)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = soft_double_buffer_update +
    +
    [Called By]
    • >>   rxbr_irq1_callback +
    + +

    soft_gen_te (Thumb, 86 bytes, Stack size 8 bytes, hal_internal_vsync.o(i.soft_gen_te)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = soft_gen_te +
    +
    [Calls]
    • >>   soft_tear_adjust_line +
    +
    [Address Reference Count : 1]
    • hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    +

    soft_gen_te_double_buffer (Thumb, 202 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.soft_gen_te_double_buffer)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = soft_gen_te_double_buffer +
    +
    [Calls]
    • >>   soft_tear_adjust_line +
    +
    [Address Reference Count : 1]
    • hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    +

    soft_pro_motion_init (Thumb, 46 bytes, Stack size 8 bytes, hal_internal_vsync.o(i.soft_pro_motion_init)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = soft_pro_motion_init +
    +
    [Calls]
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   hal_internal_vsync_init_rx +
    • >>   hal_vsync_reset_lcdc_scaler +
    • >>   hal_internal_vsync_set_tx_state +
    + +

    soft_tear_adjust_line (Thumb, 26 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.soft_tear_adjust_line)) +

    [Called By]

    • >>   soft_gen_te_double_buffer +
    • >>   soft_gen_te +
    + +

    vidc_callback (Thumb, 150 bytes, Stack size 24 bytes, hal_internal_vsync.o(i.vidc_callback)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = vidc_callback ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_vidc_set_irqen +
    • >>   tau_log_printf +
    • >>   drv_vidc_get_irq_status +
    • >>   drv_vidc_get_int_source +
    • >>   drv_vidc_clear_irq +
    • >>   drv_lcdc_function_disable +
    +
    [Address Reference Count : 1]
    • hal_internal_vsync.o(i.hal_internal_vsync_init_rx) +
    +

    vpre_err_reset (Thumb, 254 bytes, Stack size 64 bytes, hal_internal_vsync.o(i.vpre_err_reset)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = vpre_err_reset +
    +
    [Calls]
    • >>   drv_crgu_set_reset +
    • >>   drv_vidc_reset +
    +
    [Called By]
    • >>   rxbr_irq1_callback +
    + +

    check_pkt_buf_rev (Thumb, 84 bytes, Stack size 24 bytes, hal_internal_dcs.o(i.check_pkt_buf_rev)) +

    [Stack]

    • Max Depth = 360
    • Call Chain = check_pkt_buf_rev ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   tau_log_printf +
    • >>   drv_rxbr_get_status0 +
    • >>   drv_rxbr_clear_status0 +
    • >>   drv_rxbr_clear_pkt_buffer +
    +
    [Called By]
    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    + +

    drv_rxbr_get_status0 (Thumb, 20 bytes, Stack size 0 bytes, hal_internal_dcs.o(i.drv_rxbr_get_status0)) +

    [Called By]

    • >>   VPRE_IRQn_Handler +
    • >>   check_pkt_buf_rev +
    + +

    hal_intl_dcs_rx_get_dcs_packet_data (Thumb, 782 bytes, Stack size 64 bytes, hal_internal_dcs.o(i.hal_intl_dcs_rx_get_dcs_packet_data)) +

    [Stack]

    • Max Depth = 424
    • Call Chain = hal_intl_dcs_rx_get_dcs_packet_data ⇒ check_pkt_buf_rev ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_dsi_tx_command_put_payload +
    • >>   hal_dsi_rx_ctrl_dcs_async_handler +
    • >>   tau_log_printf +
    • >>   drv_dsi_rx_get_ddi_crc_en +
    • >>   dcs_packet_fifo_alloc +
    • >>   hal_intl_dcs_sw_filter_handle +
    • >>   check_pkt_buf_rev +
    +
    [Called By]
    • >>   hal_intl_dcs_rx_receive_packet +
    + +

    hal_intl_dcs_rx_receive_packet (Thumb, 122 bytes, Stack size 8 bytes, hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_packet)) +

    [Stack]

    • Max Depth = 528
    • Call Chain = hal_intl_dcs_rx_receive_packet ⇒ hal_intl_dcs_rx_receive_pps ⇒ drv_dsc_dec_enable ⇒ drv_se_set_dsc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   hal_intl_dcs_rx_receive_pps +
    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    • >>   drv_rxbr_clear_status0 +
    • >>   drv_rxbr_clear_pkt_buffer +
    +
    [Called By]
    • >>   VPRE_IRQn_Handler +
    + +

    hal_intl_dcs_rx_receive_pps (Thumb, 266 bytes, Stack size 160 bytes, hal_internal_dcs.o(i.hal_intl_dcs_rx_receive_pps)) +

    [Stack]

    • Max Depth = 520
    • Call Chain = hal_intl_dcs_rx_receive_pps ⇒ drv_dsc_dec_enable ⇒ drv_se_set_dsc ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   drv_dsi_rx_get_compression_en +
    • >>   drv_dsc_dec_enable +
    • >>   drv_crgu_enable_clock +
    • >>   tau_log_printf +
    • >>   check_pkt_buf_rev +
    • >>   drv_rxbr_clear_pkt_buffer +
    • >>   __aeabi_uidivmod +
    • >>   memcmp +
    • >>   __aeabi_memclr4 +
    • >>   __aeabi_memcpy4 +
    +
    [Called By]
    • >>   hal_intl_dcs_rx_receive_packet +
    + +

    hal_intl_dcs_sw_filter_handle (Thumb, 36 bytes, Stack size 0 bytes, hal_internal_dcs.o(i.hal_intl_dcs_sw_filter_handle)) +

    [Called By]

    • >>   hal_intl_dcs_rx_get_dcs_packet_data +
    + +

    ha_intl_fb_check_pu_size (Thumb, 58 bytes, Stack size 16 bytes, hal_internal_fb.o(i.ha_intl_fb_check_pu_size)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = ha_intl_fb_check_pu_size ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_intl_fb_cal_fb_info +
    + +

    hal_intl_fb_check_bandwidth (Thumb, 92 bytes, Stack size 40 bytes, hal_internal_fb.o(i.hal_intl_fb_check_bandwidth)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = hal_intl_fb_check_bandwidth ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   hal_internal_sync_get_hight_performan_mode +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_intl_fb_cal_fb_info +
    + +

    hal_intl_fb_edge_resize (Thumb, 214 bytes, Stack size 48 bytes, hal_internal_fb.o(i.hal_intl_fb_edge_resize)) +

    [Stack]

    • Max Depth = 60
    • Call Chain = hal_intl_fb_edge_resize ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   hal_intl_fb_cal_fb_info +
    + +

    hal_intl_fb_flow_control_adapter (Thumb, 110 bytes, Stack size 24 bytes, hal_internal_fb.o(i.hal_intl_fb_flow_control_adapter)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = hal_intl_fb_flow_control_adapter +
    +
    [Called By]
    • >>   hal_intl_fb_cal_fb_info +
    + +

    svs_direct_mode_setting (Thumb, 154 bytes, Stack size 88 bytes, hal_internal_svs.o(i.svs_direct_mode_setting)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = svs_direct_mode_setting ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   hal_intl_fb_get_rx_fb_info +
    • >>   drv_rxbr_hline_rcv1_cfg +
    • >>   drv_rxbr_clear_status0 +
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   svs_wait_start +
    + +

    svs_get_rel_intv (Thumb, 20 bytes, Stack size 8 bytes, hal_internal_svs.o(i.svs_get_rel_intv)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = svs_get_rel_intv ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   __aeabi_uidivmod +
    +
    [Called By]
    • >>   svs_wait_start +
    • >>   svs_wait_fr_stab +
    • >>   svs_sync_handle +
    + +

    svs_sync_handle (Thumb, 158 bytes, Stack size 24 bytes, hal_internal_svs.o(i.svs_sync_handle)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = svs_sync_handle ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fmul +
    • >>   __aeabi_f2d +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_dadd +
    • >>   __aeabi_d2uiz +
    • >>   svs_get_rel_intv +
    +
    [Address Reference Count : 1]
    • hal_internal_svs.o(i.svs_wait_fr_stab) +
    +

    svs_wait_fr_stab (Thumb, 148 bytes, Stack size 16 bytes, hal_internal_svs.o(i.svs_wait_fr_stab)) +

    [Stack]

    • Max Depth = 352
    • Call Chain = svs_wait_fr_stab ⇒ tau_log_printf ⇒ tau_log_push_log ⇒ delayUs +
    +
    [Calls]
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fmul +
    • >>   drv_rxbr_frame_drop_cfg +
    • >>   tau_log_printf +
    • >>   __aeabi_f2uiz +
    • >>   svs_get_rel_intv +
    • >>   __aeabi_uidivmod +
    +
    [Address Reference Count : 1]
    • hal_internal_svs.o(i.svs_wait_start) +
    +

    svs_wait_start (Thumb, 250 bytes, Stack size 24 bytes, hal_internal_svs.o(i.svs_wait_start)) +

    [Stack]

    • Max Depth = 160
    • Call Chain = svs_wait_start ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr +
    +
    [Calls]
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fmul +
    • >>   __aeabi_f2d +
    • >>   hal_internal_vsync_get_tx_state +
    • >>   drv_rxbr_set_inten +
    • >>   drv_crgu_get_rxbr_clk +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_d2uiz +
    • >>   drv_rxbr_hline_rcv1_cfg +
    • >>   svs_get_rel_intv +
    • >>   svs_direct_mode_setting +
    • >>   drv_rxbr_clear_status0 +
    • >>   ceil +
    +
    [Address Reference Count : 2]
    • hal_internal_svs.o(i.hal_intl_svs_deinit_rx) +
    • hal_internal_svs.o(i.hal_intl_svs_init_rx) +
    +

    drv_gpio_handle_int (Thumb, 30 bytes, Stack size 8 bytes, drv_gpio.o(i.drv_gpio_handle_int)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_gpio_handle_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   EXTI_INT7_IRQn_Handler +
    • >>   EXTI_INT6_IRQn_Handler +
    • >>   EXTI_INT5_IRQn_Handler +
    • >>   EXTI_INT4_IRQn_Handler +
    • >>   EXTI_INT3_IRQn_Handler +
    • >>   EXTI_INT2_IRQn_Handler +
    • >>   EXTI_INT1_IRQn_Handler +
    • >>   EXTI_INT0_IRQn_Handler +
    + +

    drv_timer_clear_status_flags (Thumb, 26 bytes, Stack size 8 bytes, drv_timer.o(i.drv_timer_clear_status_flags)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_timer_clear_status_flags ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    • >>   drv_timer_get_instance +
    +
    [Called By]
    • >>   drv_timer_handle_interrupt +
    + +

    drv_timer_handle_interrupt (Thumb, 54 bytes, Stack size 16 bytes, drv_timer.o(i.drv_timer_handle_interrupt)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = drv_timer_handle_interrupt ⇒ drv_timer_set_compare_val ⇒ __aeabi_uidivmod +
    +
    [Calls]
    • >>   drv_timer_set_int +
    • >>   drv_timer_set_compare_val +
    • >>   drv_timer_clear_status_flags +
    +
    [Called By]
    • >>   TIMER3_IRQn_Handler +
    • >>   TIMER2_IRQn_Handler +
    • >>   TIMER1_IRQn_Handler +
    • >>   TIMER0_IRQn_Handler +
    + +

    drv_dsi_rx_get_color_bpp (Thumb, 62 bytes, Stack size 4 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = drv_dsi_rx_get_color_bpp ⇒ __ARM_common_switch8 +
    +
    [Calls]
    • >>   __ARM_common_switch8 +
    +
    [Called By]
    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    + +

    drv_dsi_rx_get_color_pcc (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_color_pcc)) +

    [Called By]

    • >>   drv_dsi_rx_calc_ipi_tx_delay +
    + +

    drv_lcdc_clear_int (Thumb, 20 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_clear_int)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = drv_lcdc_clear_int ⇒ drv_sys_cfg_clear_pending +
    +
    [Calls]
    • >>   drv_sys_cfg_clear_pending +
    +
    [Called By]
    • >>   drv_lcdc_set_int +
    + +

    __NVIC_DisableIRQ (Thumb, 26 bytes, Stack size 0 bytes, drv_rxbr.o(i.__NVIC_DisableIRQ)) +

    [Called By]

    • >>   drv_rxbr_enable_irq +
    + +

    __NVIC_EnableIRQ (Thumb, 18 bytes, Stack size 0 bytes, drv_rxbr.o(i.__NVIC_EnableIRQ)) +

    [Called By]

    • >>   drv_rxbr_enable_irq +
    + +

    drv_dma_get_int_source (Thumb, 16 bytes, Stack size 0 bytes, drv_dma.o(i.drv_dma_get_int_source)) +

    [Called By]

    • >>   DMA_IRQn_Handler +
    + +

    drv_uart_enable_clk (Thumb, 24 bytes, Stack size 8 bytes, drv_uart.o(i.drv_uart_enable_clk)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_uart_enable_clk +
    +
    [Calls]
    • >>   drv_crgu_enable_clock +
    +
    [Called By]
    • >>   drv_uart_init +
    + +

    drv_uart_int_trans_handle (Thumb, 54 bytes, Stack size 8 bytes, drv_uart.o(i.drv_uart_int_trans_handle)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = drv_uart_int_trans_handle +
    +
    [Called By]
    • >>   UART_IRQn_Handler +
    + +

    _fp_digits (Thumb, 344 bytes, Stack size 64 bytes, printfa.o(i._fp_digits), UNUSED) +

    [Calls]

    • >>   __aeabi_dadd +
    • >>   __aeabi_dmul +
    • >>   __aeabi_cdrcmple +
    • >>   __aeabi_uldivmod +
    • >>   __aeabi_ddiv +
    • >>   __aeabi_d2ulz +
    +
    [Called By]
    • >>   _printf_core +
    + +

    _printf_core (Thumb, 1754 bytes, Stack size 128 bytes, printfa.o(i._printf_core), UNUSED) +

    [Calls]

    • >>   __aeabi_uidivmod +
    • >>   __aeabi_uldivmod +
    • >>   _printf_pre_padding +
    • >>   _printf_post_padding +
    • >>   _fp_digits +
    +
    [Called By]
    • >>   __0vsprintf +
    • >>   __0printf +
    + +

    _printf_post_padding (Thumb, 32 bytes, Stack size 24 bytes, printfa.o(i._printf_post_padding), UNUSED) +

    [Called By]

    • >>   _printf_core +
    + +

    _printf_pre_padding (Thumb, 44 bytes, Stack size 40 bytes, printfa.o(i._printf_pre_padding), UNUSED) +

    [Called By]

    • >>   _printf_core +
    + +

    _sputc (Thumb, 10 bytes, Stack size 0 bytes, printfa.o(i._sputc)) +

    [Called By]

    • >>   __0vsprintf +
    +
    [Address Reference Count : 1]
    • printfa.o(i.__0vsprintf) +

    +

    +Undefined Global Symbols +

    diff --git a/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.lnp b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.lnp new file mode 100644 index 0000000..62b1259 --- /dev/null +++ b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.lnp @@ -0,0 +1,10 @@ +--cpu Cortex-M0 +".\objects\main.o" +".\objects\p8p_demo.o" +"..\..\src\sdk\CVWL668\lib\CVWL668.lib" +".\objects\board.o" +".\objects\startup_armcm0.o" +--library_type=microlib --strict --scatter ".\Objects\WL668_P8P_TM667_ICNA3508_20240407.sct" +--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list ".\Listings\WL668_P8P_TM667_ICNA3508_20240407.map" -o .\Objects\WL668_P8P_TM667_ICNA3508_20240407.axf \ No newline at end of file diff --git a/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.sct b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.sct new file mode 100644 index 0000000..8775845 --- /dev/null +++ b/project/WL668/Objects/WL668_P8P_TM667_ICNA3508_20240407.sct @@ -0,0 +1,16 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM2 0x00010000 0x00010000 { ; load region size_region + ER_IROM2 0x00010000 0x00010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x00070000 0x00008000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/project/WL668/Objects/WL668_WL668.dep b/project/WL668/Objects/WL668_WL668.dep new file mode 100644 index 0000000..656b544 --- /dev/null +++ b/project/WL668/Objects/WL668_WL668.dep @@ -0,0 +1,70 @@ +Dependencies for Project 'WL668', Target 'WL668': (DO NOT MODIFY !) +F (..\..\src\app\main.c)(0x660A99AE)(--c99 --gnu -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections --asm --interleave --asm_dir ".\\Listings\\" -I ..\..\src -I ..\..\src\board -I ..\..\src\common -I ..\..\src\sdk\include -I ..\..\src\sdk\include\M0 -I ..\..\src\app -I ..\..\src\app\S8 -I ..\..\src\app\touch -I ..\..\src\app\module_demo -I ..\..\src\app\P8P -I.\RTE\_WL668 -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="528" -D_RTE_ -DARMCM0 -o .\objects\main.o --list_dir ".\\Listings\\" --list --omf_browse .\objects\main.crf --depend .\objects\main.d) +I (C:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x5CEB79E2) +I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x5CEB79E2) +I (C:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x5CEB79E2) +I (..\..\src\app\test_cfg_global.h)(0x660A9B22) +I (..\..\src\app\P8P\p8p_demo.h)(0x660A9B17) +I (..\..\src\common\tau_log.h)(0x65E142C4) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5CEB79E2) +I (C:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x5CEB79E4) +I (..\..\src\sdk\include\M0\ArmCM0.h)(0x65E142C4) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h)(0x5C8B5FF6) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_version.h)(0x5B971444) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h)(0x5C8F4DD4) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_armcc.h)(0x5C8F4DD4) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include\system_ARMCM0.h)(0x5BBD6B7A) +I (..\..\src\sdk\include\hal_system.h)(0x65E142C4) +I (..\..\src\common\tau_common.h)(0x65E142C4) +I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x5CEB79D6) +I (..\..\src\sdk\include\hal_gpio.h)(0x65E142C4) +I (..\..\src\common\tau_device_datatype.h)(0x65E142C4) +I (..\..\src\board\board.h)(0x65E142C4) +I (..\..\src\app\module_demo\module_demo_main.h)(0x6513C194) +F (..\..\src\app\P8P\p8p_demo.c)(0x6614B87F)(--c99 --gnu -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections --asm --interleave --asm_dir ".\\Listings\\" -I ..\..\src -I ..\..\src\board -I ..\..\src\common -I ..\..\src\sdk\include -I ..\..\src\sdk\include\M0 -I ..\..\src\app -I ..\..\src\app\S8 -I ..\..\src\app\touch -I ..\..\src\app\module_demo -I ..\..\src\app\P8P -I.\RTE\_WL668 -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="528" -D_RTE_ -DARMCM0 -o .\objects\p8p_demo.o --list_dir ".\\Listings\\" --list --omf_browse .\objects\p8p_demo.crf --depend .\objects\p8p_demo.d) +I (..\..\src\app\P8P\p8p_demo.h)(0x660A9B17) +I (..\..\src\sdk\include\M0\ArmCM0.h)(0x65E142C4) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h)(0x5C8B5FF6) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5CEB79E2) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_version.h)(0x5B971444) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h)(0x5C8F4DD4) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_armcc.h)(0x5C8F4DD4) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include\system_ARMCM0.h)(0x5BBD6B7A) +I (..\..\src\common\tau_device_datatype.h)(0x65E142C4) +I (..\..\src\common\tau_common.h)(0x65E142C4) +I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x5CEB79D6) +I (..\..\src\common\tau_log.h)(0x65E142C4) +I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x5CEB79E2) +I (C:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x5CEB79E4) +I (..\..\src\common\tau_operations.h)(0x65E142C4) +I (..\..\src\common\tau_delay.h)(0x65E142C4) +I (..\..\src\sdk\include\hal_dsi_rx_ctrl.h)(0x65E142C4) +I (..\..\src\common\tau_dsi_datatype.h)(0x65E142C4) +I (..\..\src\sdk\include\hal_dsi_tx_ctrl.h)(0x65E142C4) +I (..\..\src\sdk\include\hal_gpio.h)(0x65E142C4) +I (..\..\src\sdk\include\hal_swire.h)(0x65E142C4) +I (..\..\src\sdk\include\hal_timer.h)(0x65E142C4) +I (..\..\src\sdk\include\hal_system.h)(0x65E142C4) +I (..\..\src\app\test_cfg_global.h)(0x660A9B22) +I (..\..\src\sdk\include\hal_pwr.h)(0x65E142C4) +I (..\..\src\sdk\include\hal_pwm.h)(0x65E142C4) +I (..\..\src\sdk\include\hal_crc.h)(0x65E6BB1A) +F (..\..\src\sdk\CVWL668\lib\CVWL668.lib)(0x65E142A8)() +F (..\..\src\board\board.c)(0x66120E49)(--c99 --gnu -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections --asm --interleave --asm_dir ".\\Listings\\" -I ..\..\src -I ..\..\src\board -I ..\..\src\common -I ..\..\src\sdk\include -I ..\..\src\sdk\include\M0 -I ..\..\src\app -I ..\..\src\app\S8 -I ..\..\src\app\touch -I ..\..\src\app\module_demo -I ..\..\src\app\P8P -I.\RTE\_WL668 -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include -D__UVISION_VERSION="528" -D_RTE_ -DARMCM0 -o .\objects\board.o --list_dir ".\\Listings\\" --list --omf_browse .\objects\board.crf --depend .\objects\board.d) +I (..\..\src\board\board.h)(0x65E142C4) +I (..\..\src\sdk\include\hal_system.h)(0x65E142C4) +I (..\..\src\common\tau_common.h)(0x65E142C4) +I (C:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x5CEB79E2) +I (C:\Keil_v5\ARM\ARMCC\include\math.h)(0x5CEB79D6) +I (..\..\src\sdk\include\hal_gpio.h)(0x65E142C4) +I (..\..\src\common\tau_device_datatype.h)(0x65E142C4) +I (..\..\src\common\tau_log.h)(0x65E142C4) +I (C:\Keil_v5\ARM\ARMCC\include\string.h)(0x5CEB79E2) +I (C:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x5CEB79E4) +I (..\..\src\sdk\include\M0\ArmCM0.h)(0x65E142C4) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h)(0x5C8B5FF6) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_version.h)(0x5B971444) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h)(0x5C8F4DD4) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_armcc.h)(0x5C8F4DD4) +I (C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include\system_ARMCM0.h)(0x5BBD6B7A) +F (..\..\src\board\startup\startup_ARMCM0.s)(0x65E142C4)(--cpu Cortex-M0 --li -g --apcs=interwork --pd "__MICROLIB SETA 1" -I.\RTE\_WL668 -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include -IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include --pd "__UVISION_VERSION SETA 528" --pd "_RTE_ SETA 1" --pd "ARMCM0 SETA 1" --list .\listings\startup_armcm0.lst --xref -o .\objects\startup_armcm0.o --depend .\objects\startup_armcm0.d) diff --git a/project/WL668/Objects/board.__i b/project/WL668/Objects/board.__i new file mode 100644 index 0000000..b2cdcc8 --- /dev/null +++ b/project/WL668/Objects/board.__i @@ -0,0 +1,6 @@ +--c99 --gnu -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections --asm --interleave --asm_dir ".\\Listings\\" -I ..\..\src -I ..\..\src\board -I ..\..\src\common -I ..\..\src\sdk\include -I ..\..\src\sdk\include\M0 -I ..\..\src\app -I ..\..\src\app\S8 -I ..\..\src\app\touch -I ..\..\src\app\module_demo -I ..\..\src\app\P8P +-I.\RTE\_WL668 +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include +-D__UVISION_VERSION="528" -D_RTE_ -DARMCM0 +-o .\objects\board.o --list_dir ".\\Listings\\" --list --omf_browse .\objects\board.crf --depend .\objects\board.d "..\..\src\board\board.c" \ No newline at end of file diff --git a/project/WL668/Objects/board.crf b/project/WL668/Objects/board.crf new file mode 100644 index 0000000..f9ffac5 Binary files /dev/null and b/project/WL668/Objects/board.crf differ diff --git a/project/WL668/Objects/board.d b/project/WL668/Objects/board.d new file mode 100644 index 0000000..7b9216a --- /dev/null +++ b/project/WL668/Objects/board.d @@ -0,0 +1,17 @@ +.\objects\board.o: ..\..\src\board\board.c +.\objects\board.o: ..\..\src\board\board.h +.\objects\board.o: ..\..\src\sdk\include\hal_system.h +.\objects\board.o: ..\..\src\common\tau_common.h +.\objects\board.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\board.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h +.\objects\board.o: ..\..\src\sdk\include\hal_gpio.h +.\objects\board.o: ..\..\src\common\tau_device_datatype.h +.\objects\board.o: ..\..\src\common\tau_log.h +.\objects\board.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h +.\objects\board.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.h +.\objects\board.o: ..\..\src\sdk\include\M0\ArmCM0.h +.\objects\board.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h +.\objects\board.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_version.h +.\objects\board.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h +.\objects\board.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_armcc.h +.\objects\board.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include\system_ARMCM0.h diff --git a/project/WL668/Objects/board.o b/project/WL668/Objects/board.o new file mode 100644 index 0000000..66c7837 Binary files /dev/null and b/project/WL668/Objects/board.o differ diff --git a/project/WL668/Objects/main.__i b/project/WL668/Objects/main.__i new file mode 100644 index 0000000..91389a0 --- /dev/null +++ b/project/WL668/Objects/main.__i @@ -0,0 +1,6 @@ +--c99 --gnu -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections --asm --interleave --asm_dir ".\\Listings\\" -I ..\..\src -I ..\..\src\board -I ..\..\src\common -I ..\..\src\sdk\include -I ..\..\src\sdk\include\M0 -I ..\..\src\app -I ..\..\src\app\S8 -I ..\..\src\app\touch -I ..\..\src\app\module_demo -I ..\..\src\app\P8P +-I.\RTE\_WL668 +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include +-D__UVISION_VERSION="528" -D_RTE_ -DARMCM0 +-o .\objects\main.o --list_dir ".\\Listings\\" --list --omf_browse .\objects\main.crf --depend .\objects\main.d "..\..\src\app\main.c" \ No newline at end of file diff --git a/project/WL668/Objects/main.crf b/project/WL668/Objects/main.crf new file mode 100644 index 0000000..a84681b Binary files /dev/null and b/project/WL668/Objects/main.crf differ diff --git a/project/WL668/Objects/main.d b/project/WL668/Objects/main.d new file mode 100644 index 0000000..3f8e952 --- /dev/null +++ b/project/WL668/Objects/main.d @@ -0,0 +1,22 @@ +.\objects\main.o: ..\..\src\app\main.c +.\objects\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h +.\objects\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h +.\objects\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h +.\objects\main.o: ..\..\src\app\test_cfg_global.h +.\objects\main.o: ..\..\src\app\P8P\p8p_demo.h +.\objects\main.o: ..\..\src\common\tau_log.h +.\objects\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.h +.\objects\main.o: ..\..\src\sdk\include\M0\ArmCM0.h +.\objects\main.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h +.\objects\main.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_version.h +.\objects\main.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h +.\objects\main.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_armcc.h +.\objects\main.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include\system_ARMCM0.h +.\objects\main.o: ..\..\src\sdk\include\hal_system.h +.\objects\main.o: ..\..\src\common\tau_common.h +.\objects\main.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h +.\objects\main.o: ..\..\src\sdk\include\hal_gpio.h +.\objects\main.o: ..\..\src\common\tau_device_datatype.h +.\objects\main.o: ..\..\src\board\board.h +.\objects\main.o: ..\..\src\app\module_demo\module_demo_main.h diff --git a/project/WL668/Objects/main.o b/project/WL668/Objects/main.o new file mode 100644 index 0000000..7c58743 Binary files /dev/null and b/project/WL668/Objects/main.o differ diff --git a/project/WL668/Objects/p8p_demo.__i b/project/WL668/Objects/p8p_demo.__i new file mode 100644 index 0000000..71b66f4 --- /dev/null +++ b/project/WL668/Objects/p8p_demo.__i @@ -0,0 +1,6 @@ +--c99 --gnu -c --cpu Cortex-M0 -D__MICROLIB --li -g -O0 --apcs=interwork --split_sections --asm --interleave --asm_dir ".\\Listings\\" -I ..\..\src -I ..\..\src\board -I ..\..\src\common -I ..\..\src\sdk\include -I ..\..\src\sdk\include\M0 -I ..\..\src\app -I ..\..\src\app\S8 -I ..\..\src\app\touch -I ..\..\src\app\module_demo -I ..\..\src\app\P8P +-I.\RTE\_WL668 +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include +-D__UVISION_VERSION="528" -D_RTE_ -DARMCM0 +-o .\objects\p8p_demo.o --list_dir ".\\Listings\\" --list --omf_browse .\objects\p8p_demo.crf --depend .\objects\p8p_demo.d "..\..\src\app\P8P\p8p_demo.c" \ No newline at end of file diff --git a/project/WL668/Objects/p8p_demo.crf b/project/WL668/Objects/p8p_demo.crf new file mode 100644 index 0000000..491d190 Binary files /dev/null and b/project/WL668/Objects/p8p_demo.crf differ diff --git a/project/WL668/Objects/p8p_demo.d b/project/WL668/Objects/p8p_demo.d new file mode 100644 index 0000000..e930289 --- /dev/null +++ b/project/WL668/Objects/p8p_demo.d @@ -0,0 +1,28 @@ +.\objects\p8p_demo.o: ..\..\src\app\P8P\p8p_demo.c +.\objects\p8p_demo.o: ..\..\src\app\P8P\p8p_demo.h +.\objects\p8p_demo.o: ..\..\src\sdk\include\M0\ArmCM0.h +.\objects\p8p_demo.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h +.\objects\p8p_demo.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +.\objects\p8p_demo.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_version.h +.\objects\p8p_demo.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h +.\objects\p8p_demo.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_armcc.h +.\objects\p8p_demo.o: C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include\system_ARMCM0.h +.\objects\p8p_demo.o: ..\..\src\common\tau_device_datatype.h +.\objects\p8p_demo.o: ..\..\src\common\tau_common.h +.\objects\p8p_demo.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h +.\objects\p8p_demo.o: ..\..\src\common\tau_log.h +.\objects\p8p_demo.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h +.\objects\p8p_demo.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.h +.\objects\p8p_demo.o: ..\..\src\common\tau_operations.h +.\objects\p8p_demo.o: ..\..\src\common\tau_delay.h +.\objects\p8p_demo.o: ..\..\src\sdk\include\hal_dsi_rx_ctrl.h +.\objects\p8p_demo.o: ..\..\src\common\tau_dsi_datatype.h +.\objects\p8p_demo.o: ..\..\src\sdk\include\hal_dsi_tx_ctrl.h +.\objects\p8p_demo.o: ..\..\src\sdk\include\hal_gpio.h +.\objects\p8p_demo.o: ..\..\src\sdk\include\hal_swire.h +.\objects\p8p_demo.o: ..\..\src\sdk\include\hal_timer.h +.\objects\p8p_demo.o: ..\..\src\sdk\include\hal_system.h +.\objects\p8p_demo.o: ..\..\src\app\test_cfg_global.h +.\objects\p8p_demo.o: ..\..\src\sdk\include\hal_pwr.h +.\objects\p8p_demo.o: ..\..\src\sdk\include\hal_pwm.h +.\objects\p8p_demo.o: ..\..\src\sdk\include\hal_crc.h diff --git a/project/WL668/Objects/p8p_demo.o b/project/WL668/Objects/p8p_demo.o new file mode 100644 index 0000000..bb3f1a4 Binary files /dev/null and b/project/WL668/Objects/p8p_demo.o differ diff --git a/project/WL668/Objects/startup_armcm0._ia b/project/WL668/Objects/startup_armcm0._ia new file mode 100644 index 0000000..77d6d22 --- /dev/null +++ b/project/WL668/Objects/startup_armcm0._ia @@ -0,0 +1,6 @@ +--cpu Cortex-M0 --li -g --apcs=interwork --pd "__MICROLIB SETA 1" +-I.\RTE\_WL668 +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include +-IC:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include +--pd "__UVISION_VERSION SETA 528" --pd "_RTE_ SETA 1" --pd "ARMCM0 SETA 1" +--list .\listings\startup_armcm0.lst --xref -o .\objects\startup_armcm0.o --depend .\objects\startup_armcm0.d "..\..\src\board\startup\startup_ARMCM0.s" \ No newline at end of file diff --git a/project/WL668/Objects/startup_armcm0.d b/project/WL668/Objects/startup_armcm0.d new file mode 100644 index 0000000..8dfed58 --- /dev/null +++ b/project/WL668/Objects/startup_armcm0.d @@ -0,0 +1 @@ +.\objects\startup_armcm0.o: ..\..\src\board\startup\startup_ARMCM0.s diff --git a/project/WL668/Objects/startup_armcm0.o b/project/WL668/Objects/startup_armcm0.o new file mode 100644 index 0000000..a763d5d Binary files /dev/null and b/project/WL668/Objects/startup_armcm0.o differ diff --git a/project/WL668/RTE/_WL668/RTE_Components.h b/project/WL668/RTE/_WL668/RTE_Components.h new file mode 100644 index 0000000..c72cd70 --- /dev/null +++ b/project/WL668/RTE/_WL668/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'WL668' + * Target: 'WL668' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/project/WL668/WL668.BAT b/project/WL668/WL668.BAT new file mode 100644 index 0000000..123124e --- /dev/null +++ b/project/WL668/WL668.BAT @@ -0,0 +1,15 @@ +SET PATH=C:\Keil_v5\ARM\ARMCC\Bin;C:\Program Files (x86)\VMware\VMware Workstation\bin\;C:\Program Files\ImageMagick-7.1.0-Q16-HDRI;C:\Program Files (x86)\Common Files\Oracle\Java\javapath;C:\WINDOWS\system32;C:\WINDOWS;C:\WINDOWS\System32\Wbem;C:\WINDOWS\System32\WindowsPowerShell\v1.0\;C:\WINDOWS\System32\OpenSSH\;D:\Tools\;C:\Program Files\nodejs\;D:\Tools\platform-tools;%Android%;C:\Program Files\Git\cmd;C:\Users\Markin\AppData\Local\Programs\Python\Python312\Scripts\;C:\Users\Markin\AppData\Local\Programs\Python\Python312\;C:\Program Files\MySQL\MySQL Shell 8.0\bin\;C:\Users\Markin\AppData\Local\Microsoft\WindowsApps;C:\Users\Markin\AppData\Roaming\npm;D:\Tools\platform-tools_r34.0.1-windows\platform-tools;C:\Users\Markin\AppData\Local\Programs\Microsoft VS Code\bin +SET CPU_TYPE=ARMCM0 +SET CPU_VENDOR=ARM +SET UV2_TARGET=WL668 +SET CPU_CLOCK=0x00B71B00 +"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "listings\main._ip" +"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\objects\main.__i" +"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "listings\p8p_demo._ip" +"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\objects\p8p_demo.__i" +"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via "listings\board._ip" +"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\objects\board.__i" +"C:\Keil_v5\ARM\ARMCC\Bin\ArmAsm" --Via ".\objects\startup_armcm0._ia" +"C:\Keil_v5\ARM\ARMCC\Bin\ArmLink" --Via ".\Objects\WL668_P8P_TM667_ICNA3508_20240407.lnp" +"C:\Keil_v5\ARM\ARMCC\Bin\fromelf.exe" ".\Objects\WL668_P8P_TM667_ICNA3508_20240407.axf" --i32combined --output ".\Objects\WL668_P8P_TM667_ICNA3508_20240407.hex" +fromelf --bin -o .\Objects\WL668_P8P_TM667_ICNA3508_20240407.bin .\Objects\WL668_P8P_TM667_ICNA3508_20240407.axf diff --git a/project/WL668/WL668.uvguix.Markin b/project/WL668/WL668.uvguix.Markin new file mode 100644 index 0000000..ae4f678 --- /dev/null +++ b/project/WL668/WL668.uvguix.Markin @@ -0,0 +1,1914 @@ + + + + -6.1 + +
    ### uVision Project, (C) Keil Software
    + + + + + + + + + + 38003 + Registers + 150 96 + + + 346 + Code Coverage + 994 160 + + + 204 + Performance Analyzer + 1154 + + + + + + 35141 + Event Statistics + + 200 50 700 + + + 1506 + Symbols + + 85 85 85 + + + 1936 + Watch 1 + + 200 133 133 + + + 1937 + Watch 2 + + 200 133 133 + + + 1935 + Call Stack + Locals + + 200 133 133 + + + 2506 + Trace Data + + 75 135 130 95 70 230 200 150 + + + 466 + Source Browser + 500 + 300 + + + + + + + + 1 + 1 + 0 + 0 + -1 + + + + + + + 44 + 2 + 3 + + -1 + -1 + + + -1 + -1 + + + 304 + 512 + 1776 + 1320 + + + + 0 + + 1307 + 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    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + WL668 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + app + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\src\app\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 1 + 0 + 0 + ..\..\src\app\P8P\p8p_demo.c + p8p_demo.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 2 + 3 + 4 + 0 + 0 + 0 + ..\..\src\sdk\CVWL668\lib\CVWL668.lib + CVWL668.lib + 0 + 0 + + + + + board + 0 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\src\board\board.c + board.c + 0 + 0 + + + + + startup + 0 + 0 + 0 + 0 + + 4 + 5 + 2 + 0 + 0 + 0 + ..\..\src\board\startup\startup_ARMCM0.s + startup_ARMCM0.s + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + +     diff --git a/project/WL668/WL668.uvprojx b/project/WL668/WL668.uvprojx new file mode 100644 index 0000000..beac7ba --- /dev/null +++ b/project/WL668/WL668.uvprojx @@ -0,0 +1,461 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + WL668 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM0 + ARM + ARM.CMSIS.5.5.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + WL668_P8P_TM667_ICNA3508_20240407 + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 1 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin -o .\Objects\@L.bin .\Objects\@L.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 16 + 1 + 1 + 0 + 0 + 4 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x2000 + + + 1 + 0x10000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x70000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\src;..\..\src\board;..\..\src\common;..\..\src\sdk\include;..\..\src\sdk\include\M0;..\..\src\app;..\..\src\app\S8;..\..\src\app\touch;..\..\src\app\module_demo;..\..\src\app\P8P + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + app + + + main.c + 1 + ..\..\src\app\main.c + + + p8p_demo.c + 1 + ..\..\src\app\P8P\p8p_demo.c + + + + + driver + + + CVWL668.lib + 4 + ..\..\src\sdk\CVWL668\lib\CVWL668.lib + + + + + board + + + board.c + 1 + ..\..\src\board\board.c + + + + + startup + + + startup_ARMCM0.s + 2 + ..\..\src\board\startup\startup_ARMCM0.s + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\Device\ARMCM0\startup_ARMCM0.s + + + + + + RTE\Device\ARMCM0\system_ARMCM0.c + + + + + + + +     diff --git a/project/WL668T/WL668T.uvoptx b/project/WL668T/WL668T.uvoptx new file mode 100644 index 0000000..d331fc9 --- /dev/null +++ b/project/WL668T/WL668T.uvoptx @@ -0,0 +1,472 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + WL668T + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + app + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\src\app\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\src\app\touch\app_tp_transfer.c + app_tp_transfer.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\src\app\S8\app_tp_for_custom_s8.c + app_tp_for_custom_s8.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\..\src\app\S8\s8_demo.c + s8_demo.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + ..\..\src\app\Mi12Lite\Mi12Lite.c + Mi12Lite.c + 0 + 0 + + + + + driver + 1 + 0 + 0 + 0 + + 2 + 6 + 4 + 0 + 0 + 0 + ..\..\src\sdk\CVWL668T\lib\CVWL668T.lib + CVWL668T.lib + 0 + 0 + + + + + board + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\src\board\board.c + board.c + 0 + 0 + + + + + startup + 1 + 0 + 0 + 0 + + 4 + 8 + 2 + 0 + 0 + 0 + ..\..\src\board\startup\startup_ARMCM0.s + startup_ARMCM0.s + 0 + 0 + + + + + modules_demo + 0 + 0 + 0 + 0 + + 5 + 9 + 1 + 0 + 0 + 0 + ..\..\src\app\module_demo\demo_hal_crc.c + demo_hal_crc.c + 0 + 0 + + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\src\app\module_demo\demo_hal_dsi_rx.c + demo_hal_dsi_rx.c + 0 + 0 + + + 5 + 11 + 1 + 0 + 0 + 0 + ..\..\src\app\module_demo\demo_hal_dsi_tx.c + demo_hal_dsi_tx.c + 0 + 0 + + + 5 + 12 + 1 + 0 + 0 + 0 + ..\..\src\app\module_demo\demo_hal_flash.c + demo_hal_flash.c + 0 + 0 + + + 5 + 13 + 1 + 0 + 0 + 0 + ..\..\src\app\module_demo\demo_hal_gpio.c + demo_hal_gpio.c + 0 + 0 + + + 5 + 14 + 1 + 0 + 0 + 0 + ..\..\src\app\module_demo\demo_hal_i2c.c + demo_hal_i2c.c + 0 + 0 + + + 5 + 15 + 1 + 0 + 0 + 0 + ..\..\src\app\module_demo\demo_hal_spi.c + demo_hal_spi.c + 0 + 0 + + + 5 + 16 + 1 + 0 + 0 + 0 + ..\..\src\app\module_demo\demo_hal_pwm.c + demo_hal_pwm.c + 0 + 0 + + + 5 + 17 + 1 + 0 + 0 + 0 + ..\..\src\app\module_demo\demo_hal_pwr.c + demo_hal_pwr.c + 0 + 0 + + + 5 + 18 + 1 + 0 + 0 + 0 + ..\..\src\app\module_demo\demo_hal_swire.c + demo_hal_swire.c + 0 + 0 + + + 5 + 19 + 1 + 0 + 0 + 0 + ..\..\src\app\module_demo\demo_hal_uart.c + demo_hal_uart.c + 0 + 0 + + + 5 + 20 + 1 + 0 + 0 + 0 + ..\..\src\app\module_demo\demo_hal_wdg.c + demo_hal_wdg.c + 0 + 0 + + + 5 + 21 + 1 + 0 + 0 + 0 + ..\..\src\app\module_demo\module_demo_main.c + module_demo_main.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + +     diff --git a/project/WL668T/WL668T.uvprojx b/project/WL668T/WL668T.uvprojx new file mode 100644 index 0000000..43ba80b --- /dev/null +++ b/project/WL668T/WL668T.uvprojx @@ -0,0 +1,546 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + WL668T + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM0 + ARM + ARM.CMSIS.5.5.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + WL668T_demo + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 1 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin -o .\Objects\@L.bin .\Objects\@L.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 16 + 1 + 1 + 0 + 0 + 4 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x2000 + + + 1 + 0x10000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x70000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\src;..\..\src\board;..\..\src\common;..\..\src\sdk\include;..\..\src\sdk\include\M0;..\..\src\app;..\..\src\app\S8;..\..\src\app\touch;..\..\src\app\module_demo;..\..\src\app\Mi12Lite + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + app + + + main.c + 1 + ..\..\src\app\main.c + + + app_tp_transfer.c + 1 + ..\..\src\app\touch\app_tp_transfer.c + + + app_tp_for_custom_s8.c + 1 + ..\..\src\app\S8\app_tp_for_custom_s8.c + + + s8_demo.c + 1 + ..\..\src\app\S8\s8_demo.c + + + Mi12Lite.c + 1 + ..\..\src\app\Mi12Lite\Mi12Lite.c + + + + + driver + + + CVWL668T.lib + 4 + ..\..\src\sdk\CVWL668T\lib\CVWL668T.lib + + + + + board + + + board.c + 1 + ..\..\src\board\board.c + + + + + startup + + + startup_ARMCM0.s + 2 + ..\..\src\board\startup\startup_ARMCM0.s + + + + + modules_demo + + + demo_hal_crc.c + 1 + ..\..\src\app\module_demo\demo_hal_crc.c + + + demo_hal_dsi_rx.c + 1 + ..\..\src\app\module_demo\demo_hal_dsi_rx.c + + + demo_hal_dsi_tx.c + 1 + ..\..\src\app\module_demo\demo_hal_dsi_tx.c + + + demo_hal_flash.c + 1 + ..\..\src\app\module_demo\demo_hal_flash.c + + + demo_hal_gpio.c + 1 + ..\..\src\app\module_demo\demo_hal_gpio.c + + + demo_hal_i2c.c + 1 + ..\..\src\app\module_demo\demo_hal_i2c.c + + + demo_hal_spi.c + 1 + ..\..\src\app\module_demo\demo_hal_spi.c + + + demo_hal_pwm.c + 1 + ..\..\src\app\module_demo\demo_hal_pwm.c + + + demo_hal_pwr.c + 1 + ..\..\src\app\module_demo\demo_hal_pwr.c + + + demo_hal_swire.c + 1 + ..\..\src\app\module_demo\demo_hal_swire.c + + + demo_hal_uart.c + 1 + ..\..\src\app\module_demo\demo_hal_uart.c + + + demo_hal_wdg.c + 1 + ..\..\src\app\module_demo\demo_hal_wdg.c + + + module_demo_main.c + 1 + ..\..\src\app\module_demo\module_demo_main.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + RTE\Device\ARMCM0\startup_ARMCM0.s + + + + + + RTE\Device\ARMCM0\system_ARMCM0.c + + + + + + + +     diff --git a/project/请先读我（已更新20230927）.txt b/project/请先读我（已更新20230927）.txt new file mode 100644 index 0000000..9bb028c --- /dev/null +++ b/project/请先读我（已更新20230927）.txt @@ -0,0 +1,11 @@ +1. 此目录下所有project文件仅为链接文件（使用宏定义和库文件区分） + +2. 强烈建议将不使用的芯片型号文件夹删除，仅保留使用的芯片型号文件夹，以免串烧导致芯片烧坏 + +3. 如若更换芯片，仅需将提供的原工程下特定型号文件夹拷贝到模板工程，删除原芯片project下原型号文件夹，重新编译即可 + 如原来使用668芯片，后面更换为668T芯片，仅需把客户工程project下668文件夹删除，重新从提供的源工程下的668T文件夹拷贝到客户工程project下，打开重新编译即可 + +注：SDK每次更新会在demo.c中增加代码或注释，请自行阅读。 + + +第三代产品包括：WL668,668T,468 \ No newline at end of file diff --git a/src/app/P8P/p8p_demo.c b/src/app/P8P/p8p_demo.c new file mode 100644 index 0000000..a35286f --- /dev/null +++ b/src/app/P8P/p8p_demo.c @@ -0,0 +1,2000 @@ +/******************************************************************************* +* +* File: p8p_demo.c +* Description: 系统测试文件 +* Version: V0.1 +* Date: 2020-02-22 +* Author: Tempest + *******************************************************************************/ +#include "p8p_demo.h" +#include "ArmCM0.h" +#include "tau_device_datatype.h" +#include "tau_log.h" +#include "tau_operations.h" +#include "tau_common.h" +#include "tau_delay.h" +#include "hal_dsi_rx_ctrl.h" +#include "hal_dsi_tx_ctrl.h" +#include "hal_swire.h" +#include "hal_timer.h" +#include "hal_system.h" +#include "hal_gpio.h" +#include "test_cfg_global.h" +#include "hal_pwr.h" +#include "hal_pwm.h" +#include "hal_crc.h" + +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "p8p" + +#if _DEMO_GOOGLE_P8P_EN + +/******************** FEATURE开关 ********************/ +#define TOUCH_ENABLE false /* Touch转换开关 */ +#define RX_START_WITHOUT_RST true /* 不等待AP RESET直接启动RX,仅作为调试使用 */ +#define RX_WAIT_TEAR_ON false /* 等待AP_TEAR_ON */ +#define RX_RESOLUTION_CHANGE_ENABLE true /* 支持分辨率切换开关, AP存在分辨率切换时需要打开 */ +#define RX_READ_HW_ACK false /* AP DCS读命令使用硬件回复 */ +#define TX_START_AFTER_APRST false /* 等待AP_reset 后做Panel初始化, 用于热拔插电源不稳定导致初始化失败 */ +#define TX_USE_CMD_MODE false /* command mode输出开关 配置为True时需要把TD TE与 AP TE 接一起*/ +#define TX_CMD_MODE_WITHOUT_TE false /* 屏端TE直接输出给AP,Scaler不看TE信号,AP每输入一帧输出一帧(C2C 60Hz->60Hz) */ +#define AP_SWIRE_OUTPUT true /* swire信号输出,OLED项目配置 */ +#define ANALOG_PWM_OUTPUT false /* 模拟PWM 调光开关 */ +#define SHARE_FLASH_ENABLE false /* 共享flash开关 */ +/*****************************************************/ + +/******************** 输出屏幕选择 ********************/ +#define AMOLED_ICNA3508 1 /* 4lane FHD Panel */ +/*****************************************************/ + +/****************** 系统相关参数配置 ******************/ +#define MAIN_POWER_SELECT PWR_SEL_VCC /* 主供电电源选择 */ +#define SLEEP_MODE_POWER PWR_SLEEP_IN_IOV18 //PWR_SLEEP_IN_TP18 /* 息屏电源选择 */ +#define SLEEP_MODE_SELECT PWR_DEEP_SLEEP_MODE //PWR_DEEP_SLEEP_MODE //PWR_NORMAL_SLEEP_MODE // /* sleep mode 配置 */ +#define SWIRE_DEFAULT_PULSE 31 // 41 //31 /* SWIRE 波形配置 */ +#define PWM_FREQUENCY 30000 /* PWM输出频率30Khz */ +#define PWM_DUTY_STEP 255 /* PWM调光阶数255阶 */ +/*****************************************************/ + +/********************RX 基本参数配置*******************/ +//AP MIPI数据信息 +/* 输入分辨率 */ +#define INPUT_WIDTH 1344 +#define INPUT_HEIGHT 2992 +/* 输入 MIPI lane rate,需要正确配置,可50M step调整 */ +#define INPUT_MIPI_LANE_RATE 1600000000 +/* 输入图像格式 */ +#define INPUT_COLOR_MODE DSI_RGB888 +/* 输出数据格式(DSI_DATA_CMD_MODE , DSI_DATA_VIDEO_MODE) */ +#define INPUT_DATA_MODE DSI_DATA_CMD_MODE +/* 输入mipi lane数量(DSI_RX_LANE_x x为1-4) */ +#define INPUT_MIPI_LANE_NUM DSI_LANE_4 +/* 输入为video mode 时数据格式 */ +#define INPUT_VIDEO_MODEL DSI_NONBURST_EVENT +/* 输入虚拟通道(0-3) */ +#define INPUT_VC DSI_VC_0 +/* 输入的帧率(60/90/120/144Hz) */ +#define INPUT_FRAME_RATE DSI_FRAME_RATE_120HZ +/* 输入数据是否DSC压缩 */ +#define INPUT_COMPRESS true +/*****************************************************/ + +/********************TX 基本参数配置*******************/ +#if AMOLED_ICNA3508 +//almoled NT37280输出MIPI数据信息 +/* 输出分辨率配置 */ +#define OUTPUT_WIDTH 1080 +#define OUTPUT_HEIGHT 2400 +/* 输出虚拟通道(0-3) */ +#define OUTPUT_VC DSI_VC_0 +/* 输出mipi lane数量(DSI_RX_LANE_x x为1-4) */ +#define OUTPUT_LANE_NUMBER DSI_LANE_4 +/* 输出数据格式(DSI_DATA_CMD_MODE , DSI_DATA_VIDEO_MODE) */ +#if TX_USE_CMD_MODE +#define OUTPUT_DATA_MODE DSI_DATA_CMD_MODE +#else +#define OUTPUT_DATA_MODE DSI_DATA_VIDEO_MODE +#endif +/* 输出为video mode时的数据格式 */ +#define OUTPUT_VIDEO_MODEL DSI_BURST_MODE +/* 输出 VSA */ +#define OUTPUT_VSA 1 //1 +/* 输出 VBP */ +#define OUTPUT_VBP 19 //19 +/* 输出 VBP */ +#define OUTPUT_VFP 12 //12 +/* 输出 VSA */ +#define OUTPUT_HSA 1 +/* 输出 HBP */ +#define OUTPUT_HBP 27 +/* 输出 HFP */ +#define OUTPUT_HFP 77 +/* 初始化模式命令传输类型 LP/HS */ +#define TX_INIT_TYPE DSI_CMD_TX_LP +#endif +/******************************************************/ + +#if TOUCH_ENABLE +#include "app_tp_transfer.h" +#endif + +/* 全局handle */ +static hal_dsi_rx_ctrl_handle_t *g_rx_ctrl_handle = NULL; +static hal_dsi_tx_ctrl_handle_t *g_tx_ctrl_handle = NULL; + +/* 屏初始化完成标志位 */ +static bool panel_display_done = false; +static bool sg_system_resume = false; +static bool sg_system_suspend = false; +static bool sg_exit_idle_mode_flag = false; + +static volatile bool g_resolution_change = false; +static uint32_t pps_renew_flag = 0; +static uint32_t pwr_rst_flag = 0; + +#if RX_WAIT_TEAR_ON +static bool sg_ap_set_tear_on = false; +#endif +#if TX_START_AFTER_APRST +static bool sg_tx_start_in_process = false; +#endif + +uint16_t rd_51_val,rd_51_val2; + +/* AP reset 回调函数声明 */ +static void ap_rstn_pull_high_cb(void *data); +static void ap_rstn_pull_down_cb(void *data); +static void app_mipi_rx_start_cb(void *data); + + +/*************************DCS 命令处理函数 BEGIN*************************/ +#if RX_READ_HW_ACK +/** +* @brief 配置AP硬件回读 +* @param none +* @retval none +*/ +static void app_set_dcs_hw_ack() +{ + hal_dsi_rx_ctrl_set_auto_ack(g_rx_ctrl_handle, HAL_RX_QRESP_CODE0, DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, 0xFA, 1, 0x00); +} +#endif +/** +* @brief ap 读回调函数 +* @param handler：rx_ctrl_handle +* dcs_packet: dcs 命令 +* @retval true/false +*/ +static bool ap_dcs_read(uint8_t data_type, uint8_t dcs_cmd, uint8_t param) +{ + if (dcs_cmd == 0x04) + { + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_LONG_RESPONSE, + DSI_VC_0, + 3, 0x0A,0x60,0x20); + } + else if (dcs_cmd == 0xa1) + { + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_LONG_RESPONSE, + DSI_VC_0, + 13, 0x0C,0x21,0x0C,0xC6,0x01,0xF3,0xAA,0x11,0x06,0x2B,0x25,0x21,0xF6); + } + else if (dcs_cmd == 0xDA) + { + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, + DSI_VC_0, + 1, 0x0A); + } + else if (dcs_cmd == 0xDB) + { + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, + DSI_VC_0, + 1, 0x68); + } + else if (dcs_cmd == 0xDC) + { + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, + DSI_VC_0, + 1, 0x07); + } + else if (dcs_cmd == 0xD6) + { + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_LONG_RESPONSE, + DSI_VC_0, + 5, 0xF0, 0xEA, 0x85, 0x61, 0x86); + } + else + { + uint32_t return_size = hal_dsi_rx_ctrl_get_max_ret_size(g_rx_ctrl_handle); + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, + DSI_VC_0, + 1, 0); + TAU_LOGD("r[%x] [%d] err!!!!!!\n", dcs_cmd, return_size); + } + +// TAU_LOGD("r %x\n",dcs_cmd); + return true; +} + +uint8_t pps[128] = {0x11,0x00,0x00,0x89,0x30,0x80,0x0B,0xB0, + 0x05,0x40,0x00,0xBB,0x02,0xA0,0x02,0xA0, + 0x02,0x00,0x02,0x50,0x00,0x20,0x14,0x39, + 0x00,0x09,0x00,0x0C,0x00,0x85,0x00,0x70, + 0x18,0x00,0x10,0xF0,0x03,0x0C,0x20,0x00, + 0x06,0x0B,0x0B,0x33,0x0E,0x1C,0x2A,0x38, + 0x46,0x54,0x62,0x69,0x70,0x77,0x79,0x7B, + 0x7D,0x7E,0x01,0x02,0x01,0x00,0x09,0x40, + 0x09,0xBE,0x19,0xFC,0x19,0xFA,0x19,0xF8, + 0x1A,0x38,0x1A,0x78,0x1A,0xB6,0x2A,0xF6, + 0x2B,0x34,0x2B,0x74,0x3B,0x74,0x6B,0xF4, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; +uint8_t pps_fhd[128] = {0x11,0x00,0x00,0x89,0x30,0x80,0x08,0xC4, + 0x03,0xF0,0x00,0xBB,0x01,0xF8,0x01,0xF8, + 0x02,0x00,0x01,0xF8,0x00,0x20,0x11,0x82, + 0x00,0x07,0x00,0x0C,0x00,0x85,0x00,0x96, + 0x18,0x00,0x10,0xF0,0x03,0x0C,0x20,0x00, + 0x06,0x0B,0x0B,0x33,0x0E,0x1C,0x2A,0x38, + 0x46,0x54,0x62,0x69,0x70,0x77,0x79,0x7B, + 0x7D,0x7E,0x01,0x02,0x01,0x00,0x09,0x40, + 0x09,0xBE,0x19,0xFC,0x19,0xFA,0x19,0xF8, + 0x1A,0x38,0x1A,0x78,0x1A,0xB6,0x2A,0xF6, + 0x2B,0x34,0x2B,0x74,0x3B,0x74,0x6B,0xF4, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; + + +#if RX_RESOLUTION_CHANGE_ENABLE +/* PPS update callback 用于分辨率切换case */ +static bool pps_update_handle(uint8_t *pps, uint8_t size, uint32_t pic_width, uint32_t pic_height) +{ +// for (uint8_t i =0; i< 128; i++) +// { +// TAU_LOGD("PPS_0A[i]=[0x%02X]\n",i,pps[i]); +// } + + /* AVDD 上电, 用于解决息屏开屏PPS不更新问题 */ + // hal_gpio_set_output_data(IO_PAD_AP_PWMEN, IO_LVL_HIGH); + if (pic_width != g_rx_ctrl_handle->base_info.src_w || pic_height != g_rx_ctrl_handle->base_info.src_h) + { + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_USER_MODE); + /* PPS Update 且分辨率发生变化 */ + g_rx_ctrl_handle->base_info.src_w = pic_width; + g_rx_ctrl_handle->base_info.src_h = pic_height; + /* 注意部分基板更新PPS前不发 Compression Mode Command的情况 */ + g_rx_ctrl_handle->compress_en = true; + g_resolution_change = true; + if(pic_width > 720) + { + g_tx_ctrl_handle->base_info.src_w = pic_width; + g_tx_ctrl_handle->base_info.src_h = pic_height; + } +// hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x22); // ic刷黑处理 +// delayMs(5); + +// hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps, 128); + hal_dsi_rx_ctrl_toggle_resolution(g_rx_ctrl_handle); + // hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x13); // 退出刷黑 + } + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); + //TAU_LOGD("PPS Update[%d][%d] [%d][%d]\n", pic_width, pic_height, g_rx_ctrl_handle->base_info.src_w, g_rx_ctrl_handle->base_info.src_h); + return true; +} +#endif + + + +/** +* @brief ap display on处理函数 +* @param handler：rx_ctrl_handle +* dcs_packet: dcs 命令 +* @retval true/false +*/ +static bool ap_dcs_set_display_on(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + + if(g_resolution_change) + { + hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps_fhd, 128); + hal_dsi_rx_ctrl_toggle_resolution(g_rx_ctrl_handle); + g_resolution_change = false; + TAU_LOGD("pps_update_1\r\n"); + } +// TAU_LOGD("disp on"); +// if (start_display_on == false){ + hal_dsi_tx_ctrl_write_cmd(0x05, 0, 2, 0x29); +// } + TAU_LOGD("disp on \n"); + return true; +} + + +void REG_51_OFF_output(uint16_t REG_51_VALUE) +{ + uint8_t i; + uint16_t REG_51; + + + + for (i =0; i< 50; i++) + { + REG_51=REG_51_VALUE*(50-i)/50; + hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, REG_51>>8, REG_51&0x00FF);; + delayMs(17); + // TAU_LOGD("reg_51_off[0x%04X]\n",REG_51); + } + +} + +/** +* @brief ap display off处理函数 +* @param handler：rx_ctrl_handle +* dcs_packet: dcs 命令 +* @retval true/false +*/ +static bool ap_dcs_set_display_off(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ +#if ANALOG_PWM_OUTPUT + hal_pwm_enable(false); +#endif + + TAU_LOGD("disp off %d\n", panel_display_done); + return true; +} + + +/***************************************************************************** +*GPIO发送swire波形 +*flag: =0, SWIRE=0; =1,仅发送SWIRE信号; =2, 先置高再发SWIRE信号 +*num: 发几个脉冲 +*注意FLAG=1时无GPIO初始化!!!!!! +*****************************************************************************/ +void Gpio_swire_output(uint8_t flag, uint8_t num) +{ + uint8_t ii; + + if (flag) + { + if (flag ==2) + { + hal_gpio_init_output(IO_PAD_AP_SWIRE, IO_LVL_HIGH); + delayMs(2); + } + for (ii =0; ii< num; ii++) + { + hal_gpio_set_output_data(IO_PAD_AP_SWIRE, IO_LVL_LOW); + delayUs(10); + hal_gpio_set_output_data(IO_PAD_AP_SWIRE, IO_LVL_HIGH); + delayUs(9); + } + } + else + { + hal_gpio_init_output(IO_PAD_AP_SWIRE, IO_LVL_LOW); + } +} + + + +/** +* @brief ap enter sleep mode处理函数 +* @param handler：rx_ctrl_handle +* dcs_packet: dcs 命令 +* @retval true/false +*/ +static bool ap_dcs_set_enter_sleep_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x28); + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_STOP_MODE); + delayMs(10); + + // delayMs(10); +#if AP_SWIRE_OUTPUT + /* Swire close */ + hal_swire_enable(false); + delayMs(10); + hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x10); + delayMs(20); + /* AVDD_EN close*/ + hal_gpio_set_output_data(IO_PAD_AP_PWMEN, IO_LVL_LOW); +#endif + /* Wait AP reset down*/ + hal_gpio_set_ap_reset_int(ENABLE, ap_rstn_pull_down_cb, DETECT_LOW_LVL); + // sg_system_suspend=true; + TAU_LOGD("enter sleep mode\n"); +// delayMs(500); + return true; +} + +/** +* @brief ap exit sleep mode处理函数 +* @param handler：rx_ctrl_handle +* dcs_packet: dcs 命令 +* @retval true/false +*/ +static bool ap_dcs_set_exit_sleep_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ +//#if AP_SWIRE_OUTPUT +// /* AVDD 上电, 用于解决息屏开屏PPS不更新问题 */ +// hal_gpio_set_output_data(IO_PAD_AP_PWMEN, IO_LVL_HIGH); +//#endif + +#if TX_START_AFTER_APRST + if (panel_display_done == false) + { + sg_tx_start_in_process = true; + } +#endif + + TAU_LOGD("exit sleep mode \n"); + + return true; +} + + + +/** +* @brief 调光处理函数 +* @param handler：rx_ctrl_handle +* dcs_packet: dcs 命令 +* @retval true/false +*/ + +uint8_t value_51H,value_51L; +static bool reg53_E8_fg=0; +static bool ap_dcs_set_backlight(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + //手机端0xC4~CEB(2043) 映射0x9FF +#if 0 + value_51H = dcs_packet->packet_param[0]; + value_51L = dcs_packet->packet_param[1]; + hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, value_51H, value_51L); +#else + rd_51_val = dcs_packet->packet_param[0]; + rd_51_val <<=8; + rd_51_val |= dcs_packet->packet_param[1]; + +// rd_51_val2 = (rd_51_val-0x04)*2555/2043+0x04; //0x9FF max + if((rd_51_val >=0x00)&&(rd_51_val <= 0xFFF) ){ + + rd_51_val2 = (rd_51_val-0xC4)*2555/3889+0x04; //0x9FF max + + } + else if(rd_51_val >0xFFF) { + + rd_51_val2 = 0x9FF; + + } + hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, rd_51_val2>>8, rd_51_val2&0x00FF); +#endif + // TAU_LOGD("AP_51[0x%04X],IC_51[0x%04X]\n",rd_51_val,rd_51_val2); + return true; +} + +#if RX_WAIT_TEAR_ON +/** +* @brief ap set tear on 处理函数 +* @param handler：rx_ctrl_handle +* dcs_packet: dcs 命令 +* @retval true/false +*/ +static bool ap_dcs_set_tear_on(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + TAU_LOGD("ap_set_tear_on\n"); + sg_ap_set_tear_on = true; + if (panel_display_done == false) + { + TAU_LOGD("gen a tear\n"); + hal_dsi_tx_ctrl_gen_a_tear_signal(); + } + else + { + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); + } + return true; +} + +/** +* @brief ap set tear off 处理函数 +* @param handler：rx_ctrl_handle +* dcs_packet: dcs 命令 +* @retval true/false +*/ +static bool ap_dcs_set_tear_off(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + TAU_LOGD("ap_set_tear_off \n"); + sg_ap_set_tear_on = false; + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_USER_MODE); + return true; +} +#endif + +/** +* @brief 护眼模式回调函数 +* @param rx_ctrl_handle: dsi rx handle; +* dcs packet: dcs_packet +* @retval true/false +*/ +static bool ap_dcs_set_exit_idle_mode(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + sg_exit_idle_mode_flag = true; + hal_dsi_rx_ctrl_set_hw_cmd_filter(g_rx_ctrl_handle, HAL_RX_DCS_FILTER_B, 0x2C, 0x2C); + TAU_LOGD("exit idle mode,skip 0x2C\n"); + return true; +} + +#define TE_TIMER TIMER_NUM2 +static void soft_te_timer_cb(void *data) +{ + /* + S8 的屏接的是TP1.8V, AC 启动后需要等到TP1.8 起来后再初始化屏, 所以在TP 起来前需要通过软件产生TE给手机，避免手机卡死 + */ +// if (panel_display_done == false) +// { + hal_dsi_tx_ctrl_gen_a_tear_signal(); + hal_timer_start(TE_TIMER, 8, soft_te_timer_cb, NULL); +// } +// else +// { +// hal_dsi_rx_ctrl_set_hw_tear_mode(g_rx_ctrl_handle); +// } +} + +static void soft_te_timer_init() +{ +// TAU_LOGD("soft_te_timer_init"); + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle,TE_USER_MODE); + hal_timer_init(TE_TIMER); + hal_timer_start(TE_TIMER, 1, soft_te_timer_cb, NULL); +} + +/** +* @brief 帧率切换处理函数 +* @param handler：rx_ctrl_handle +* dcs_packet: dcs 命令 +* @retval true/false +*/ +static bool ap_dcs_set_frame_change(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + if (dcs_packet->param_length == 1) + { + if (dcs_packet->packet_param[0] == 0x18) + { + // hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle,TE_USER_MODE); + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); + } + else + { + // soft_te_timer_init(); + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_120HZ_MODE); + } + } + // TAU_LOGD("frame_change %x ,size %d, data %d\n", dcs_packet->dcs_command, dcs_packet->param_length, dcs_packet->packet_param[0]); + return true; +} + +static bool ap_set_FPS_53(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + uint8_t value_53 =0; + + value_53 = dcs_packet->packet_param[0]; + + if(value_53 == 0x30) // AP FPS ON + { + + hal_dsi_tx_ctrl_write_cmd( 0x39, 0, 4, 0x97, 0x11, 0xCF, 0xFF); // DDIC FPS ON + + } + else if(value_53 == 0x20) // AP FPS OFF + { + + hal_dsi_tx_ctrl_write_cmd( 0x39, 0, 4, 0x97, 0x00, 0xCF, 0xFF); // DDIC FPS OFF + + + } + +// TAU_LOGD("B1[%x]", value_b1); + return true; +} + +/*************************DCS 命令处理函数 END*************************/ + +/* 客制化DCS command 处理函数表格 */ +static const hal_dcs_execute_entry_t g_cus_rx_dcs_execute_table[] = +{ + {DCS_SET_DISPLAY_ON, ap_dcs_set_display_on, false}, + {DCS_SET_DISPLAY_OFF, ap_dcs_set_display_off, true}, + {0x51, ap_dcs_set_backlight, false}, + {0x53, ap_set_FPS_53, true}, //FPS Switch: P6P-0xB1; P7P-0x53 + {DCS_ENTER_SLEEP_MODE, ap_dcs_set_enter_sleep_mode, true}, + {DCS_EXIT_SLEEP_MODE, ap_dcs_set_exit_sleep_mode, true}, + {0x60, ap_dcs_set_frame_change, true}, +#if RX_WAIT_TEAR_ON + {DCS_SET_TEAR_ON, ap_dcs_set_tear_on, true}, + {DCS_SET_TEAR_OFF, ap_dcs_set_tear_off, true}, +#endif + {0, NULL, false} //{0,NULL,false} 数组最后一个固定成员，作为table结尾的判断标准 +}; + +/** +* @brief panel reset +* @param none +* @retval none +*/ +static void app_tx_panel_reset(void) +{ +#if SHARE_FLASH_ENABLE + hal_flash_share_mode(true); +#endif + hal_gpio_set_output_data(IO_PAD_TD_RSTN, IO_LVL_HIGH); + delayMs(10); + hal_gpio_set_output_data(IO_PAD_TD_RSTN, IO_LVL_LOW); + delayMs(10); + hal_gpio_set_output_data(IO_PAD_TD_RSTN, IO_LVL_HIGH); + delayMs(40); +} + +#if PANEL_INIT_CODE_ARRAY +static void send_panel_init_code(uint32_t size, uint8_t * data) +{ + uint32_t data_offeset = 0; + uint8_t data_type; + uint8_t vc; + uint8_t data_size; + uint8_t * p_data; + + while(data_offeset < size) + { + data_type = data[data_offeset]; + vc = data[data_offeset + 1]; + data_size = data[data_offeset + 2]; + p_data = &data[data_offeset + 3]; + hal_dsi_tx_ctrl_write_array_cmd(data_type, vc, data_size, p_data); + data_offeset = data_offeset + data_size + 3; + delayUs(50); + } +} + +const uint8_t panel_init_code[] = { +#if 1 +0x39,0,3,0x9C,0xA5,0xA5, +0x39,0,3,0xFD,0x5A,0x5A, +0x39,0,2,0x9F,0x0F, +0x39,0,2,0xB3,0x00, +0x39,0,2,0xD7,0x11, +0x39,0,2,0x9F,0x01, +0x39,0,4,0xB2,0x5A,0x04,0xAF, +0x39,0,36,0xB3,0x00,0xBA,0x00,0x14,0x0C,0x22,0x00,0xBA,0x30,0x14,0x2C,0x00,0x00,0xBA,0x90,0x14,0x4C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xBA,0x00,0x14,0x0C,0x44,0x1C,0x1C,0x1C,0x1C,0x1C, +0x39,0,19,0xCD,0x06,0x1F,0x1F,0x06,0x00,0x09,0x00,0x96,0x1F,0x03,0x28,0x00,0x96,0x1F,0x09,0x46,0x00,0x96, +0x39,0,2,0xD0,0x01, +0x39,0,3,0xE2,0x46,0x20, +0x39,0,3,0xEA,0x04,0x0B, +0x39,0,9,0xEE,0x40,0x38,0x28,0x28,0x28,0x28,0x28,0xC2,//add for ICNA5608 +0x39,0,2,0x9F,0x02, +0x39,0,26,0xB2,0x00,0xC9,0x32,0x10,0x11,0x12,0x12,0x00,0x08,0x78,0x21,0x11,0x14,0x13,0x11,0x11,0x11,0x11,0x11,0x11,0x11,0x21,0x21,0x11,0x1A, +0x39,0,14,0xB4,0x00,0x00,0x8C,0x00,0x00,0x00,0x00,0x00,0x25,0x25,0x25,0x25,0x25, +0x39,0,7,0xB5,0x00,0x30,0x30,0x30,0x30,0x2A, +0x39,0,20,0xB6,0x05,0x00,0x00,0x11,0x11,0x11,0x1C,0x08,0x1C,0x21,0x21,0x21,0x21,0x21,0x21,0x21,0x21,0x21,0x21, +0x39,0,17,0xB7,0x00,0x00,0x00,0x00,0x00,0x15,0x00,0x06,0x06,0x03,0x06,0x06,0x03,0x06,0x06,0x03, +0x39,0,14,0xB8,0x00,0x00,0x00,0x73,0x28,0x73,0x28,0x73,0x28,0x73,0x28,0x73,0x28, +0x39,0,9,0xB9,0x00,0x00,0x50,0x00,0x00,0x0F,0x0F,0x00, +0x39,0,14,0xBA,0x0E,0xFF,0xFF,0xFF,0x00,0x54,0x00,0x44,0x04,0x44,0x04,0x04,0x00, +0x39,0,26,0xBB,0x00,0x5A,0x91,0x91,0x5A,0x00,0x5A,0x91,0x91,0x5A,0x00,0x5A,0x91,0x91,0x5A,0x00,0x5A,0x91,0x91,0x5A,0x00,0x3C,0x78,0x78,0x3C, +0x39,0,5,0xBE,0x5B,0x17,0x04,0x5B, +0x39,0,17,0xBF,0x0C,0x8F,0xFF,0x10,0x00,0x07,0x00,0x0A,0x01,0x20,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,17,0xC1,0x05,0x21,0x22,0x1D,0x1F,0x1E,0x20,0x01,0x30,0x31,0x32,0x33,0x3D,0x3D,0x3D,0x3D, +0x39,0,17,0xC2,0x05,0x21,0x22,0x1D,0x1F,0x1E,0x20,0x01,0x30,0x31,0x32,0x33,0x3D,0x3D,0x3D,0x3D, +0x39,0,10,0xC3,0x11,0x60,0x00,0x40,0x00,0x40,0x00,0x00,0x00, +0x39,0,26,0xC4,0x00,0x0C,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x1F,0x1F,0x00,0x00,0x0D,0x00,0x00,0x00,0x00, +0x39,0,17,0xD2,0x00,0x00,0x13,0x00,0x00,0x13,0x00,0x00,0x17,0x00,0x00,0x17,0x00,0x00,0x17,0x00, +0x39,0,14,0xC7,0x00,0x04,0x04,0x04,0x04,0x00,0x04,0x04,0x04,0x04,0x00,0x04,0x04, +0x39,0,14,0xC8,0x00,0xB1,0xB1,0xB1,0xB1,0x00,0xB1,0xB1,0xB1,0xB1,0x00,0xB1,0xB1, +0x39,0,27,0xC6,0x00,0x00,0x0f,0x00,0x00,0x11,0x00,0x00,0x00,0x90,0x00,0x00,0x00,0x00,0x08,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x55,0x01,0x01,0x00, +0x39,0,27,0xCB,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x92,0x90,0x92,0x00,0x90,0x92,0x90,0x92,0x00,0x90,0x92, +0x39,0,27,0xCC,0x00,0x76,0xff,0x76,0xff,0x00,0x76,0xff,0x76,0xff,0x00,0x76,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,19,0xD7,0x4D,0xC3,0x20,0x7A,0x33,0x00,0x02,0x02,0x00,0xF7,0xF7,0xF4,0xA9,0xA9,0xAE,0xF0,0x00,0x00, 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+0x39,0,43,0xB3,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00, +0x39,0,43,0xB4,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00, +0x39,0,43,0xB5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00, +0x39,0,12,0xBE,0x00,0x1F,0xFF,0x13,0x91,0x0F,0x04,0x00,0x24,0x80,0xFF, +0x39,0,2,0x9F,0x0B, //Middle circle setting REG 0xBE +0x39,0,10,0xB2,0x01,0x3F,0x3F,0x0F,0x3F,0x0F,0x5F,0x0F,0x0F, +0x39,0,49,0xB9,0x32,0x00,0x00,0x00,0x00,0x00,0x6B,0x54,0x24,0x1C,0xB0,0x14,0xC8,0x5C,0x24,0x1C,0xB0,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,49,0xBA,0x32,0x00,0x00,0x00,0x00,0x00,0x54,0x69,0x24,0x1C,0xB0,0x14,0xC8,0x5C,0x24,0x1C,0xB0,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,49,0xBC,0x32,0x00,0x00,0x00,0x00,0x00,0x4b,0x4b,0x24,0x1C,0xB0,0x14,0xD1,0x65,0x24,0x1C,0xB0,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,49,0xBE,0x32,0x00,0x00,0x00,0x00,0x00,0x25,0x25,0x20,0x1C,0x33,0x00,0x00,0x00,0x00,0x25,0x25,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,20,0xC6,0x8F,0x04,0x04,0x04,0x04,0xFF,0xFF,0xFF,0xFF,0x00,0x22,0x22,0x22,0x22,0x00,0x1E,0x1E,0x1E,0x1E, +0x39,0,20,0xC7,0x0F,0x04,0x04,0x04,0x04,0xFF,0xFF,0xFF,0xFF,0x00,0x22,0x22,0x22,0x22,0x00,0x1E,0x1E,0x1E,0x1E, +0x39,0,16,0xC8,0xF9,0x05,0x05,0xB0,0xE0,0xB0,0x50,0xBA,0xF0,0xB0,0xE0,0xB0,0x20,0xD0,0x50, +0x39,0,2,0x9F,0x0D, +0x39,0,16,0xB2,0x25,0x10,0x21,0x01,0x02,0x10,0x00,0x00,0x16,0x10,0x00,0x00,0x01,0xAA,0x90, +0x39,0,2,0xB3,0xB0, +0x39,0,13,0xB5,0x00,0x24,0x07,0x01,0x00,0x00,0x00,0x00,0x20,0x04,0xEE,0x21, +0x39,0,4,0xB6,0x02,0x12,0x22, +0x39,0,5,0xB7,0x20,0xF0,0xC0,0xE0, +0x39,0,13,0xB8,0x20,0xF0,0xC0,0xE0,0x20,0xF0,0xC0,0xE0,0x20,0xF0,0xC0,0xE0, +0x39,0,5,0xB9,0x01,0x01,0x01,0x01, +0x39,0,3,0xBA,0x00,0x00, +0x39,0,2,0xBB,0x01, +0x39,0,21,0xBC,0x0F,0xFF,0x07,0xFF,0x03,0x33,0x01,0x47,0x01,0x46,0x00,0xCD,0x00,0x66,0x00,0x3A,0x00,0x14,0x00,0x08, +0x39,0,6,0xBD,0x02,0x00,0x02,0x06,0x5B, +0x39,0,12,0xC7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2A,0x00, +0x39,0,2,0x48,0x03, //0x03：120hz 0x23:60hz +0x39,0,1,0x11, +0x39,0,3,0x51,0x00,0x0F, +0x39,0,2,0x53,0xE0, +0x39,0,1,0x35, +//0x39,0,1,0x29, +#endif +#if 0 //AMOLED_ICNA3508_gamma_correct --old version +0x39,0,3,0x9C,0xA5,0xA5, +0x39,0,3,0xFD,0x5A,0x5A, +0x39,0,2,0x9F,0x0F, +0x39,0,2,0xB3,0x00, +0x39,0,2,0xD7,0x11, +0x39,0,2,0x9F,0x01, +0x39,0,4,0xB2,0x5A,0x04,0xAF, +0x39,0,36,0xB3,0x00,0xBA,0x00,0x14,0x0C,0x22,0x00,0xBA,0x30,0x14,0x2C,0x00,0x00,0xBA,0x90,0x14,0x4C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xBA,0x00,0x14,0x0C,0x44,0x1C,0x1C,0x1C,0x1C,0x1C, +0x39,0,19,0xCD,0x06,0x1F,0x1F,0x06,0x00,0x09,0x00,0x96,0x1F,0x03,0x28,0x00,0x96,0x1F,0x09,0x46,0x00,0x96, +0x39,0,2,0xD0,0x01, +0x39,0,3,0xE2,0x46,0x20, +0x39,0,3,0xEA,0x04,0x0B, +0x39,0,9,0xEE,0x40,0x38,0x28,0x28,0x28,0x28,0x28,0xC2,//add for ICNA5608 +0x39,0,2,0x9F,0x02, +0x39,0,26,0xB2,0x00,0xC9,0x32,0x10,0x11,0x12,0x12,0x00,0x08,0x78,0x21,0x11,0x14,0x13,0x11,0x11,0x11,0x11,0x11,0x11,0x11,0x21,0x21,0x11,0x1A, +0x39,0,14,0xB4,0x00,0x00,0x8C,0x00,0x00,0x00,0x00,0x00,0x25,0x25,0x25,0x25,0x25, +0x39,0,7,0xB5,0x00,0x30,0x30,0x30,0x30,0x2A, +0x39,0,20,0xB6,0x05,0x00,0x00,0x11,0x11,0x11,0x1C,0x08,0x1C,0x21,0x21,0x21,0x21,0x21,0x21,0x21,0x21,0x21,0x21, +//0x39,0,17,0xB7,0x00,0x00,0x00,0x00,0x00,0x15,0x00,0x06,0x06,0x03,0x06,0x06,0x03,0x06,0x06,0x03, +0x39,0,17,0xB7,0x05,0x00,0x15,0x00,0x00,0x15,0x70,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03, //ver2.0 +0x39,0,14,0xB8,0x00,0x00,0x00,0x73,0x28,0x73,0x28,0x73,0x28,0x73,0x28,0x73,0x28, +0x39,0,9,0xB9,0x00,0x00,0x50,0x00,0x00,0x0F,0x0F,0x00, +0x39,0,14,0xBA,0x0E,0xFF,0xFF,0xFF,0x00,0x54,0x00,0x44,0x04,0x44,0x04,0x04,0x00, +0x39,0,26,0xBB,0x00,0x5A,0x91,0x91,0x5A,0x00,0x5A,0x91,0x91,0x5A,0x00,0x5A,0x91,0x91,0x5A,0x00,0x5A,0x91,0x91,0x5A,0x00,0x3C,0x78,0x78,0x3C, +0x39,0,5,0xBE,0x5B,0x17,0x04,0x5B, +0x39,0,17,0xBF,0x0C,0x8F,0xFF,0x10,0x00,0x07,0x00,0x0A,0x01,0x20,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,17,0xC1,0x05,0x21,0x22,0x1D,0x1F,0x1E,0x20,0x01,0x30,0x31,0x32,0x33,0x3D,0x3D,0x3D,0x3D, +0x39,0,17,0xC2,0x05,0x21,0x22,0x1D,0x1F,0x1E,0x20,0x01,0x30,0x31,0x32,0x33,0x3D,0x3D,0x3D,0x3D, +0x39,0,10,0xC3,0x11,0x60,0x00,0x40,0x00,0x40,0x00,0x00,0x00, +0x39,0,26,0xC4,0x00,0x0C,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x1F,0x1F,0x00,0x00,0x0D,0x00,0x00,0x00,0x00, +0x39,0,17,0xD2,0x00,0x00,0x13,0x00,0x00,0x13,0x00,0x00,0x17,0x00,0x00,0x17,0x00,0x00,0x17,0x00, +0x39,0,14,0xC7,0x00,0x04,0x04,0x04,0x04,0x00,0x04,0x04,0x04,0x04,0x00,0x04,0x04, +0x39,0,14,0xC8,0x00,0xB1,0xB1,0xB1,0xB1,0x00,0xB1,0xB1,0xB1,0xB1,0x00,0xB1,0xB1, +0x39,0,27,0xC6,0x00,0x00,0x0f,0x00,0x00,0x11,0x00,0x00,0x00,0x90,0x00,0x00,0x00,0x00,0x08,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x55,0x01,0x01,0x00, +0x39,0,27,0xCB,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x92,0x90,0x92,0x00,0x90,0x92,0x90,0x92,0x00,0x90,0x92, +0x39,0,27,0xCC,0x00,0x76,0xff,0x76,0xff,0x00,0x76,0xff,0x76,0xff,0x00,0x76,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +//0x39,0,19,0xD7,0x49,0xC3,0x20,0x7A,0x44,0x00,0x04,0x04,0x00,0xF9,0xF9,0xF4,0xAB,0xA9,0xAE,0xF0,0x00,0x00, +//0x39,0,19,0xD7,0x4D,0xC3,0x20,0x7A,0x53,0x00,0x66,0x02,0x00,0xCC,0xF7,0xF4,0xCC,0xA9,0xAE,0xF0,0x00,0x00, //功耗高 +0x39,0,19,0xD7,0x4D,0xC3,0x20,0x7A,0x53,0x00,0x66,0x02,0x00,0xCC,0xF7,0xF4,0xCC,0xA9,0xAE,0xF0,0x00,0x00, +0x39,0,41,0xD8,0x00,0x04,0x76,0x22,0xFF,0x00,0x04,0x76,0x22,0xFF,0x00,0x04,0x76,0x22,0xFF,0x00,0x04,0x76,0x22,0xFF,0x00,0x04,0x76,0x22,0xFF,0x90,0x76,0xFF,0x90,0x76,0xFF,0x90,0x76,0xFF,0x90,0x76,0xFF,0x90,0x76,0xFF, +0x39,0,12,0xD9,0x10,0x40,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10, +0x39,0,4,0xE0,0x00,0x00,0x60, +0x39,0,6,0xE1,0x43,0x00,0x11,0x60,0x0D, +0x39,0,51,0xE2,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24,0x15,0x00,0x39,0x42,0x24, +0x39,0,4,0xED,0x00,0x01,0x80, +0x39,0,18,0xEE,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x88,0x88,0x29,0x00,0x00,0x00,0x00, +0x39,0,6,0xEF,0x00,0x85,0x88,0x87,0x87, +0x39,0,2,0x9F,0x03, +0x39,0,33,0xB2,0x11,0x00,0x00,0x89,0x30,0x80,0x09,0x60,0x04,0x38,0x00,0x0C,0x02,0x1C,0x02,0x1C,0x02,0x00,0x02,0x0E,0x00,0x20,0x01,0x1F,0x00,0x07,0x00,0x0C,0x08,0xBB,0x08,0x7A, +0x39,0,33,0xB3,0x18,0x00,0x10,0xF0,0x03,0x0C,0x20,0x00,0x06,0x0B,0x0B,0x33,0x0E,0x1C,0x2A,0x38,0x46,0x54,0x62,0x69,0x70,0x77,0x79,0x7B,0x7D,0x7E,0x01,0x02,0x01,0x00,0x09,0x40, +0x39,0,25,0xB4,0x09,0xBE,0x19,0xFC,0x19,0xFA,0x19,0xF8,0x1A,0x38,0x1A,0x78,0x1A,0xB6,0x2A,0xF6,0x2B,0x34,0x2B,0x74,0x3B,0x74,0x6B,0xF4, +0x39,0,2,0xC0,0x11, +0x39,0,2,0xC1,0x82, +0x39,0,3,0xC2,0x00,0xC0, +0x39,0,6,0xC6,0x11,0x00,0x00,0x01,0x01, +0x39,0,2,0xE2,0x01, +0x39,0,2,0x9F,0x04, +0x39,0,4,0xB2,0x01,0x80,0x00, +0x39,0,19,0xB3,0x00,0x00,0x10,0x00,0x30,0x50,0x00,0x70,0xB0,0x00,0xD0,0xF0,0x11,0x30,0x70,0x12,0xF0,0x70, +0x39,0,21,0xB4,0x23,0xF0,0x70,0x34,0xF0,0xF0,0x67,0xF0,0xF0,0x8A,0xF0,0xF0,0xCD,0xF0,0xF0,0xEF,0xF0,0xF0,0x0F,0xFF, +0x39,0,8,0xB6,0x01,0x20,0x00,0x0F,0xF0,0x10,0x06, +//0x39,0,3,0xB9,0x91,0xC1, +0x39,0,3,0xB9,0x90,0xC1, +0x39,0,3,0xBA,0x01,0x00, +0x39,0,10,0xBB,0x00,0x00,0x08,0x00,0x00,0x00,0xF2,0x00,0x00, +0x39,0,41,0xC1,0x0F,0xFF,0x07,0xFF,0x03,0x33,0x01,0x47,0x01,0x46,0x00,0xCD,0x00,0x66,0x00,0x3A,0x00,0x14,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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+0x39,0,16,0xC8,0xF9,0x05,0x05,0xB0,0xE0,0xB0,0x50,0xBA,0xF0,0xB0,0xE0,0xB0,0x20,0xD0,0x50, +0x39,0,2,0x9F,0x0D, +0x39,0,16,0xB2,0x25,0x10,0x21,0x01,0x02,0x10,0x00,0x00,0x16,0x10,0x00,0x00,0x01,0xAA,0x90, +0x39,0,2,0xB3,0xB0, +0x39,0,13,0xB5,0x00,0x24,0x07,0x01,0x00,0x00,0x00,0x00,0x20,0x04,0xEE,0x21, +0x39,0,4,0xB6,0x02,0x12,0x22, +0x39,0,5,0xB7,0x20,0xF0,0xC0,0xE0, +0x39,0,13,0xB8,0x20,0xF0,0xC0,0xE0,0x20,0xF0,0xC0,0xE0,0x20,0xF0,0xC0,0xE0, +0x39,0,5,0xB9,0x01,0x01,0x01,0x01, +0x39,0,3,0xBA,0x00,0x00, +0x39,0,2,0xBB,0x01, +0x39,0,21,0xBC,0x0F,0xFF,0x07,0xFF,0x03,0x33,0x01,0x47,0x01,0x46,0x00,0xCD,0x00,0x66,0x00,0x3A,0x00,0x14,0x00,0x08, +0x39,0,6,0xBD,0x02,0x00,0x02,0x06,0x5B, +0x39,0,12,0xC7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2A,0x00, +0x39,0,2,0x48,0x03, //00 cmd 0x03 vdo +//// bist mode +//0x39,0,2,0x9F,0x01, +////0x39,0,5,0xC6,0x01,0x20,0x18,0x02, +//0x39,0,3,0xC6,0x03,0x08, +0x39,0,1,0x11, +//0x39,0,3,0x51,0x00,0x00, +0x39,0,2,0x53,0xE0, +0x39,0,1,0x35, +//0x39,0,1,0x29, + +#endif +#if DDIC_FPS_SETTING +0x39,0,2,0x9F,0x04, +0x39,0,14,0xB5,0x00,0x17,0x27,0x1B,0x17,0x00,0x75,0x75,0x10,0x3B,0x08,0xA8,0x48, // 0x3B,0x10,0xB8,0x40,(美版ANDROID 13放久过后指纹解会失效) +//1226 0x3B,0x08,0xA8,0x48(ANDROID 13+++/14+++) 0x3B,0x10,0xA8,0x50(ANDROID 13++/14++) 0x3B,0x00,0xAF,0x58(ANDROID 13++/14+) +//1225 0x3B,0x08,0xA0,0x48(ANDROID 13+++/14++) 0x3B,0x10,0xA8,0x48(ANDROID 13++/14++) 0x3B,0x10,0xA8,0x4F(ANDROID 13++/14++) 0x3B,0x10,0xA0,0x48(ANDROID 13++/14++) 0x3B,0x10,0xB0,0x4F(ANDROID 13++/14+) , 0x3B,0x10,0xB8,0x4F(ANDROID 13++/14+) 0x3B,0x18,0xB8,0x4F(ANDROID 13++/14) 0x3B,0x08,0x98,0x2F(ANDROID 13++/14-); 0x3B,0x28,0xB8,0x4F(ANDROID 13++/14--); , 0x3B,0x20,0xB0,0x40 (ANDROID 13/14 JP NG) +//1222 0x2B,0xF0,0x98,0x7F(ALL OK) 0x2B,0xF0,0x98,0x2F (ALL OK 2nd) 0x2B,0xF0,0x98,0x00, (ALL OK 3rd )0x2B,0xF0,0x9F,0x3F 0x2B,0xDF,0x8F,0x4F(ANDROID 12 FAIL ) +//1214 0x2B,0xFF,0x9F,0x5F 0x2B,0xFF,0xCF,0x5F +//ANDROID 14 0x2B,0xF0,0x90,0x20 秒解 LAST VERSION 0x3B,0x3F,0xDF,0x6F +// 1211 fail FOR ALL VERSION 0x3B,0x3F,0xEF,0x6F; 0x3B,0x2F,0xDF,0x5F; 0x3B,0x1F,0xCF,0x4F; 0x3B,0x1F,0xCF,0x4F; 0x3B,0x0F,0xBF,0x3F; 0x2B,0xFF,0xAF,0x3F +0x39,0,18,0xBE,0x00,0xCF,0xFF,0xFF,0xFF,0x3F,0xFF,0xFF,0xFF,0x3F,0xFF,0xFF,0xFF,0x3F,0xFF,0xFF,0xFF, +0x39,0,46,0xE9,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0xFF,0x3F,0x3F,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +0x39,0,28,0xEA,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +0x39,0,46,0xEB,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0xFF,0x3F,0x3F,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +0x39,0,28,0xEC,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +0x39,0,46,0xED,0xFF,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0xFF,0xFF,0x3F,0x3F,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +0x39,0,28,0xEE,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF,0x33,0xFF,0xFF, +0x39,0,10,0xF8,0x1E,0xE0,0xE0,0xE0,0x00,0x18,0x15,0x00,0xE0, +0x39,0,10,0xF9,0xE1,0x18,0x15,0x00,0xF0,0xF8,0xF0,0xEE,0x00, +0x39,0,10,0xFA,0x1E,0xE0,0xE0,0xE0,0x00,0x18,0x15,0x00,0xE0, +0x39,0,2,0x9F,0x05, +0x39,0,13,0xB4,0x02,0x0F,0x3E,0x00,0x00,0x10,0x06,0x00,0x00,0x02,0x40,0x8D, +0x39,0,41,0xE6,0x0F,0xFF,0x07,0xFF,0x03,0x33,0x01,0x47,0x01,0x46,0x00,0xCD,0x00,0x66,0x00,0x3A,0x00,0x14,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,31,0xE7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,41,0xE8,0x0F,0xFF,0x0F,0xFF,0x0F,0xFF,0x0F,0xFF,0x0F,0xFF,0x0C,0xF0,0x09,0x71,0x07,0x54,0x04,0x8C,0x03,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +//0x39,0,41,0xE8,0x01,0xFF,0x00,0x1F,0x00,0x2F,0x00,0x1F,0x00,0x1F,0x0C,0xF0,0x09,0x71,0x07,0x54,0x04,0x8C,0x03,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x39,0,31,0xE9,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + + +#endif +}; + +#endif + + +/** +* @brief panel init +* @param none +* @retval none +*/ +static void app_init_panel(void) +{ + /* reset panel*/ + app_tx_panel_reset(); +#if PANEL_INIT_CODE_ARRAY + send_panel_init_code(sizeof(panel_init_code), (uint8_t *) panel_init_code); +#endif + hal_gpio_init_output(IO_PAD_AP_PWMEN, IO_LVL_HIGH); + delayMs(90); +#if AP_SWIRE_OUTPUT + hal_swire_enable(true); + hal_swire_set_pulse(SWIRE_DEFAULT_PULSE); +#endif +// hal_gpio_init_output(IO_PAD_AP_SWIRE, IO_LVL_HIGH); +// Gpio_swire_output(2, 40); + +// TAU_LOGD("Panel init!\n\r"); +} + +#if TX_CMD_MODE_WITHOUT_TE +/** +* @brief MIPI RX事件处理函数,demo code 用于command mode 输出发送数据（模式1） +* @param event:RX事件 +* @param data: user data +* @retval none +*/ +static void app_rx_event_cb(hal_rx_event_e event, void *data) +{ + if (panel_display_done && event == HAL_RX_LINE_EVENT) + { + hal_dsi_tx_ctrl_gen_a_frame(); + } +} +#endif + +#if TX_USE_CMD_MODE +/** +* @brief TE引脚作为GPIO 输入回调函数,demo code 用于command mode 输出发送数据（模式2） +* @param none +* @retval none +*/ +static void app_tx_cmd_panel_te_cb(void *data) +{ + if (panel_display_done) + { + //delayUs(25); /* 撕裂调试 */ + hal_dsi_tx_ctrl_gen_a_frame(); + } +} + +/** +* @brief 注册屏端TE信号输入引脚回调函数 +* @param pad :TE输入pad +* @param trig:触发中断沿配置 +* @retval none +*/ +static void app_tx_cmd_app_init_panel_te_int(io_pad_e pad, sys_cfg_trigger_e trig) +{ + /*1.关闭中断*/ + hal_gpio_ctrl_eint(pad, DISABLE); + + /*2.中断初始化*/ + hal_gpio_init_eint(pad, trig); + + /*3.注册回调*/ + hal_gpio_reg_eint_cb(pad, app_tx_cmd_panel_te_cb); + + /*4.使能中断*/ + hal_gpio_ctrl_eint(pad, ENABLE); +} +#endif + +/** +* @brief mipi rx 初始化 +* @param none +* @retval none +*/ +static void app_mipi_rx_init(void) +{ + if (g_rx_ctrl_handle == NULL) + { + /* 创建rx ctrl handle */ + g_rx_ctrl_handle = hal_dsi_rx_ctrl_create_handle(); + } + /* 配置参数 */ + g_rx_ctrl_handle->base_info.src_w = INPUT_WIDTH; + g_rx_ctrl_handle->base_info.src_h = INPUT_HEIGHT; + g_rx_ctrl_handle->base_info.dst_w = OUTPUT_WIDTH; + g_rx_ctrl_handle->base_info.dst_h = OUTPUT_HEIGHT; + g_rx_ctrl_handle->base_info.src_frate = INPUT_FRAME_RATE; + g_rx_ctrl_handle->base_info.src_mode = INPUT_DATA_MODE; + g_rx_ctrl_handle->base_info.dst_mode = OUTPUT_DATA_MODE; + g_rx_ctrl_handle->rx_color_mode = INPUT_COLOR_MODE; + g_rx_ctrl_handle->rx_lanes = INPUT_MIPI_LANE_NUM; + g_rx_ctrl_handle->rx_nonburst_models = INPUT_VIDEO_MODEL; /* 可不配置 */ + g_rx_ctrl_handle->compress_en = INPUT_COMPRESS; + g_rx_ctrl_handle->rx_hsclk_rate = INPUT_MIPI_LANE_RATE; + g_rx_ctrl_handle->cus_dcs_entry_table = g_cus_rx_dcs_execute_table; /* 注册 DCS处理列表 */ + g_rx_ctrl_handle->rx_dcs_read_entry = ap_dcs_read; /* 注册dsc read 回调函数,可选,此函数为空时由cus_dcs_entry_table执行 */ +// g_rx_ctrl_handle->hight_performan_mode=HIGHT_PERFORMAN_L2; + g_rx_ctrl_handle->extra_info.crop_info.top =12; //4 8 的倍数 + g_rx_ctrl_handle->extra_info.crop_info.enable=1; +#if RX_RESOLUTION_CHANGE_ENABLE + g_rx_ctrl_handle->pps_update_entry = pps_update_handle; +#endif + /* 提前预置PPS, AP 有PPS cmd也会更新 */ + if (g_rx_ctrl_handle->compress_en == true) + { + hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps, 128); + } + + /* 初始化rx ctrl */ + hal_dsi_rx_ctrl_init(g_rx_ctrl_handle); + +#if RX_READ_HW_ACK + /* 配置硬件回复 */ + app_set_dcs_hw_ack(); +#endif + +#if TX_CMD_MODE_WITHOUT_TE + /* 注册接收一帧帧头事件回调,每接收一帧数据TX再往外发一帧 */ + //hal_dsi_rx_ctrl_register_callback(g_rx_ctrl_handle, app_rx_event_cb, HAL_RX_FS_EVENT, true, NULL); + /* 注册接收第0行数据事件,接收到数据后再往外发送数据,确保不撕裂 */ + uint32_t line = 0; + hal_dsi_rx_ctrl_register_callback(g_rx_ctrl_handle, app_rx_event_cb, HAL_RX_LINE_EVENT, true, &line); +#endif + +#if RX_START_WITHOUT_RST + /* 等待ap reset置位再启动rx,否则容易收到错误数据 */ + hal_dsi_rx_ctrl_start(g_rx_ctrl_handle); +#else + /* 注册RX start callback,确认RX LP11时再启动RX,防止接收错误数据 */ + hal_gpio_set_ap_reset_int(ENABLE, app_mipi_rx_start_cb, DETECT_HIGH_LVL); +#endif + TAU_LOGD("rx init!\n\r"); +} + +/** +* @brief mipi tx 初始化 +* @param none +* @retval none +*/ +static void app_mipi_tx_init(void) +{ + if (g_tx_ctrl_handle == NULL) + { + g_tx_ctrl_handle = hal_dsi_tx_ctrl_create_handle(); + } + g_tx_ctrl_handle->channel_id = OUTPUT_VC; + g_tx_ctrl_handle->lane_num = OUTPUT_LANE_NUMBER; + g_tx_ctrl_handle->vid_mode = OUTPUT_VIDEO_MODEL; + g_tx_ctrl_handle->cmd_tx_type = TX_INIT_TYPE; + g_tx_ctrl_handle->dpi_vsa = OUTPUT_VSA; + g_tx_ctrl_handle->dpi_vbp = OUTPUT_VBP; + g_tx_ctrl_handle->dpi_vfp = OUTPUT_VFP; + g_tx_ctrl_handle->dpi_hsa = OUTPUT_HSA; + g_tx_ctrl_handle->dpi_hbp = OUTPUT_HBP; + g_tx_ctrl_handle->dpi_hfp = OUTPUT_HFP; + g_tx_ctrl_handle->base_info.src_w = INPUT_WIDTH; + g_tx_ctrl_handle->base_info.src_h = INPUT_HEIGHT; + g_tx_ctrl_handle->base_info.dst_w = OUTPUT_WIDTH; + g_tx_ctrl_handle->base_info.dst_h = OUTPUT_HEIGHT; + g_tx_ctrl_handle->base_info.src_frate = INPUT_FRAME_RATE; + g_tx_ctrl_handle->base_info.src_mode = INPUT_DATA_MODE; + g_tx_ctrl_handle->base_info.dst_mode = OUTPUT_DATA_MODE; + g_tx_ctrl_handle->tx_frame_rate=58; +// g_tx_ctrl_handle->tx_lane_lp = 2; + + /* 初始化屏时每一条LP CMD都退出LPDT 再进入发送下一条 */ + /* 解决FT8720 TDDI 显示翻转问题 */ + // g_tx_ctrl_handle->lp_exit_lpdt = true; + + hal_dsi_tx_ctrl_init(g_tx_ctrl_handle); +// hal_dsi_tx_ctrl_set_cus_sync_line(g_tx_ctrl_handle,1200); //1200 + + /* FIXME set tear on*/ + // hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); + + /* AP 没有发送数据时默认的显示颜色, 量产为0 0 0(黑色), 配置其他颜色仅为debug使用 */ + hal_dsi_tx_ctrl_set_overwrite_rgb(0x00, 0x00, 0x00); + TAU_LOGD("tx init!\n\r"); +} + +#if !RX_START_WITHOUT_RST +/** +* @brief mipi rx start函数,开启AP RSTN等待启动配置后使用 +* @param none +* @retval none +*/ +static void app_mipi_rx_start_cb(void *data) +{ + /* RX start */ + hal_dsi_rx_ctrl_start(g_rx_ctrl_handle); + /* close cb */ + hal_gpio_set_ap_reset_int(DISABLE, NULL, DETECT_HIGH_LVL); + TAU_LOGD("rx start\n"); +} +#endif + +void Panel_CCM(void) +{ + ccm_coef_t ccm; + ccm.coef_c00 = 255; // 260 + ccm.coef_c01 = 0; + ccm.coef_c02 = 0; + ccm.coef_c10 = 0; + ccm.coef_c11 = 246; // 247 + ccm.coef_c12 = 0; + ccm.coef_c20 = 0; + ccm.coef_c21 = 0; + ccm.coef_c22 = 247; //248 + + hal_dsi_tx_ctrl_set_ccm(&ccm); +} + + +/** +* @brief mipi tx 启动 +* @param none +* @retval none +*/ +static void app_mipi_tx_start(void) +{ + // TAU_LOGD("tx_start \n"); + /* Init panel */ + app_init_panel(); + /* TX start */ + hal_dsi_tx_ctrl_start(g_tx_ctrl_handle); + +#if RX_WAIT_TEAR_ON + te_mode_e default_te = sg_ap_set_tear_on ? TE_60HZ_MODE : TE_USER_MODE; + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, default_te); +#else + hal_dsi_tx_ctrl_set_tear_mode(g_tx_ctrl_handle, TE_60HZ_MODE); +#endif + + panel_display_done = true; + if(g_tx_ctrl_handle->base_info.src_w==1008) + { + hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps_fhd, 128); + hal_dsi_rx_ctrl_toggle_resolution(g_rx_ctrl_handle); + g_resolution_change = false; + // TAU_LOGD("pps_update!!\r\n"); + } + // soft_te_timer_init(); + delayMs(80); +// Panel_CCM(); +// delayMs(20); + /* Display on */ + hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x29); + +#if AP_SWIRE_OUTPUT + hal_swire_set_pulse(SWIRE_DEFAULT_PULSE); +#endif + +#if (TX_USE_CMD_MODE & (!TX_CMD_MODE_WITHOUT_TE)) + // hal_dsi_tx_ctrl_gen_a_frame(); /* FIXME */ + app_tx_cmd_app_init_panel_te_int(IO_PIN_14, DETECT_RISING_EDGE); /* 注册屏端TE中断 */ +#endif + + TAU_LOGD("tx_start \n"); +} + +/** +* @brief ap rstn 拉高中断回调,用于息屏唤醒 +* @param none +* @retval none +*/ +static void ap_rstn_pull_high_cb(void *data) +{ + /* system resume begin */ + sg_system_resume = true; + /* 关闭AP reset检查 */ + hal_gpio_set_ap_reset_int(DISABLE, NULL, DETECT_RISING_EDGE); +} + +/** +* @brief ap rstn 拉高中断回调,用于息屏待机 +* @param none +* @retval none +*/ +static void ap_rstn_pull_down_cb(void *data) +{ + TAU_LOGD("ap_rstn_pull_down_cb\n"); + sg_system_suspend = true; + /* 关闭AP reset检查 */ + hal_gpio_set_ap_reset_int(DISABLE, NULL, DETECT_RISING_EDGE); +// TAU_LOGD("ap_rstn_pull_down_cb\n"); +} + +/** +* @brief GPIO初始化配置,根据实际原理图提前配置IO功能以及状态,默认功能可不配置 +* TP相关I2C/SPI 在tp_transfer.c,也可以挪到此函数初始化 +* @param none +* @retval none +*/ +void app_gpio_init(void) +{ + io_pad_attr_t attrs[] = + { + {IO_PIN_8, PIN8_MODE_GPIO7, IO_IOE_OUTPUT, IO_LVL_LOW},/* PIN_8(TD_RSTN), GPIO,输出,低电平 */ + {IO_PIN_17, PIN17_MODE_GPIO8, IO_IOE_OUTPUT, IO_LVL_LOW}, /* PIN_17(PWMEN), GPIO,输出,低电平 */ + {IO_PIN_16, PIN16_MODE_GPIO2, IO_IOE_OUTPUT, IO_LVL_LOW}, /* PIN_16(AP_INT),GPIO,输出,低电平 */ +#if (TX_USE_CMD_MODE & (!TX_CMD_MODE_WITHOUT_TE)) + {IO_PIN_14, PIN14_MODE_GPIO24, IO_IOE_INPUT, IO_LVL_NONE}, /* PIN_29(AP_TE), cmd mode输出, 并且看屏TE,配置AP TE为GPIO输入 */ +#endif + {IO_PIN_29, PIN29_MODE_TEAR, IO_IOE_NONE, IO_LVL_NONE}, /* PIN_29(AP_TE), 硬件TEAR输出模式 */ + + }; + uint8_t size = sizeof(attrs) / sizeof(io_pad_attr_t); + hal_gpio_config_pad(attrs, size); +} + + +/** +* @brief 显示相关模块初始化,包括MIPI RX/TX/PWM/SWIRE/GPIO等 +* @param none +* @retval none +*/ +void app_display_init(void) +{ + /* mipi rx初始化 */ + app_mipi_rx_init(); + /* VCC 主供电,等待VCC Power Ready,此时RX初始化完成可以响应MIPI命令 */ + if (MAIN_POWER_SELECT == PWR_SEL_VCC) + { + + while (hal_pwr_get_vcc_power_ready() == false); + } + + /* GPIO 初始化 */ + app_gpio_init(); +//TAU_LOGD("app_gpio_init \n"); + /* 背光初始化 */ +#if AP_SWIRE_OUTPUT + hal_swire_init(); /* swire init */ + hal_swire_set_timer(TIMER_NUM0, 8, true); /* swire连续发送,绑定timer进行发送 */ +#endif +#if ANALOG_PWM_OUTPUT + if (hal_pwm_init(PWM_FREQUENCY, PWM_DUTY_STEP)) + { + hal_pwm_enable(true); + hal_pwm_set_elvcc_output(true); + } +#endif + + /* mipi tx 初始化*/ + app_mipi_tx_init(); +// soft_te_timer_init(); +#if TX_START_AFTER_APRST + TAU_LOGD("wait exit sleep mode\n"); +#else + app_mipi_tx_start(); +#endif +} + +/** +* @brief 系统resume +* @param sleep_mode: sleep 模式 +* @retval none +*/ +static void app_system_resume(pwr_sleep_mode_e sleep_mode) +{ + /* 退出sleep mode, 电源切换 */ + hal_pwr_exit_sleep_mode(); + + /* display resume */ + app_display_init(); + +#if TOUCH_ENABLE + /* touch resume */ + app_tp_write_other_operations(NULL, 0); +#endif + TAU_LOGD("system resume\n"); +} + +/** +* @brief 系统suspend,进入sleep mode +* @param sleep_mode: sleep 模式 +* @retval none +*/ +static void app_system_suspend(pwr_sleep_mode_e sleep_mode) +{ +// TAU_LOGD("SLEEP_MODE\n"); + /* 关闭图像通路 */ + hal_dsi_tx_ctrl_stop(g_tx_ctrl_handle); + hal_dsi_tx_ctrl_deinit(g_tx_ctrl_handle); + hal_dsi_rx_ctrl_stop(g_rx_ctrl_handle); + hal_dsi_rx_ctrl_deinit(g_rx_ctrl_handle); + + /* Tear拉低 */ + hal_gpio_init_output(IO_PAD_AP_TE, IO_LVL_LOW); + panel_display_done = false; +#if RX_WAIT_TEAR_ON + sg_ap_set_tear_on = false; +#endif + + /* 关闭外设 比如Swire/I2C/Flash 等 */ +#if AP_SWIRE_OUTPUT + hal_swire_deinit(); +#endif +#if ANALOG_PWM_OUTPUT + hal_pwm_deinit(); +#endif + +#if SHARE_FLASH_ENABLE + hal_flash_share_mode(false); +#endif + + /* 切换TP18 供电 */ + hal_pwr_set_sleep_mode_power(SLEEP_MODE_POWER); + + if (sleep_mode == PWR_NORMAL_SLEEP_MODE) + { + /* normal sleep mode, MCU可以正常工作 */ + hal_gpio_set_ap_reset_int(ENABLE, ap_rstn_pull_high_cb, DETECT_HIGH_LVL); + hal_pwr_enter_normal_sleep_mode(); + TAU_LOGD("PWR_NORMAL_SLEEP_MODE\n"); + } + else if (sleep_mode == PWR_STOP_SLEEP_MODE) + { + TAU_LOGD("PWR_STOP_SLEEP_MODE\n"); + + /* 注册对应 wakeup IO */ + hal_pwr_set_stop_sleep_wakeup_pin(IO_PAD_AP_RSTN, WUP_RISING_EDGE); + //hal_pwr_set_stop_sleep_wakeup_pin(IO_PAD_AP_SPIS_CSN, WUP_FALLING_EDGE); + //hal_pwr_set_stop_sleep_wakeup_pin(IO_PAD_TD_INT, WUP_FALLING_EDGE); + io_pad_e wakeup_io = hal_pwr_enter_stop_sleep_mode(); + if (wakeup_io == IO_PAD_AP_RSTN) + { + sg_system_resume = true; + } + else + { + /* Not impletmented */ + TAU_LOGD("wakeup_io %d FIXME touch wakeup convert to AP\n", wakeup_io); + hal_gpio_set_ap_reset_int(ENABLE, ap_rstn_pull_high_cb, DETECT_HIGH_LVL); + } + } + else + { + /* deep sleep mode,配置AP RSTN 上升沿,TD INT 下降沿唤醒 */ + hal_pwr_enter_deep_sleep_mode(WUP_RISING_EDGE, WUP_FALLING_EDGE); + TAU_LOGD("PWR_DEEP_SLEEP_MODE\n"); + } + +} + +/** +* @brief 系统process处理函数,处理待机唤醒等 +* @param none +* @retval none +*/ +static void app_system_process(void) +{ + + if (sg_system_suspend) + { + TAU_LOGD("app_system_process\n"); + /* 系统进入sleep mode */ + app_system_suspend(SLEEP_MODE_SELECT); + sg_system_suspend = false; + } + + if (sg_system_resume) + { + /* 系统退出sleep mode */ + app_system_resume(SLEEP_MODE_SELECT); + sg_system_resume = false; + } + +#if TX_START_AFTER_APRST + if (sg_tx_start_in_process) + { + app_mipi_tx_start(); + sg_tx_start_in_process = false; + } +#endif +} + + + +/** +* @brief mi12 lite demo 主函数 +* @param none +* @retval none +*/ +void google_p8p_demo(void) +{ +// hal_gpio_set_high_impedance(IO_PIN_14); +// TAU_LOGD("p6p demo reset flag=%d \n", hal_pwr_get_reset_flag()); + + /* 电源选择,上电只需要选择一次 */ + hal_pwr_set_main_power(MAIN_POWER_SELECT); /* 切换供电*/ +// if (MAIN_POWER_SELECT == PWR_SEL_VCC) +// { +// while (hal_pwr_get_vcc_power_ready() == false); +// } + /* 显示模块初始 */ + app_display_init(); + + /* touch 相关模块初始化 */ +#if TOUCH_ENABLE + /* TP 初始化 */ + app_tp_init(); + app_tp_phone_clear_reset_on(); + /* 与屏的TP 模块通讯并初始化 */ + app_tp_transfer_screen_start(); +#endif + + TAU_LOGD("p8p demo init done \n"); + + while (1) + { + + ///hal_dsi_tx_ctrl_set_vpg(1, TX_VPG_H_COLOR, true); +#if TOUCH_ENABLE + /* 等待屏TP中断上报做TP协议转换,注意接口实现不可阻塞!否则会影响sleep mode */ + app_tp_transfer_screen_int(); +#endif + /* DCS 命令异步处理 */ + while (hal_dsi_rx_ctrl_dcs_async_handler(g_rx_ctrl_handle)); + + /* 系统事件处理(sleep mode) */ + app_system_process(); + } +} +#endif diff --git a/src/app/P8P/p8p_demo.h b/src/app/P8P/p8p_demo.h new file mode 100644 index 0000000..5e78fcd --- /dev/null +++ b/src/app/P8P/p8p_demo.h @@ -0,0 +1,21 @@ +/******************************************************************************* +* Copyright (C) 2019-2022, TAU Systems (R),All Rights Reserved. +* +* File: P8P.h +* Description GOOGLE P8P DEMO file +* Version V0.1 +* Date 2023-12-25 +* Author Markin +*******************************************************************************/ +#ifndef __GOOGLE_P8P_DEMO_H__ +#define __GOOGLE_P8P_DEMO_H__ + + +#define PANEL_INIT_CODE_ARRAY 1 +#define DDIC_FPS_SETTING 1 + + + +void google_p8p_demo(void); + +#endif diff --git a/src/app/draw_mode/draw_mode_lib.c b/src/app/draw_mode/draw_mode_lib.c new file mode 100644 index 0000000..9ea817b --- /dev/null +++ b/src/app/draw_mode/draw_mode_lib.c @@ -0,0 +1,288 @@ +/******************************************************************************* +* +* File: draw_mode_lib.c +* Description 画点模式下，提供画线、画圆、画矩阵等函数 +* Version V0.1 +* Date 2022-6-21 +* Author Tempest +*******************************************************************************/ +#include "tau_log.h" +#include "tau_operations.h" +#include "tau_common.h" +#include "tau_delay.h" +#include "hal_dsi_rx_ctrl.h" + +#define FONT_SIZE 50 //如需要显示其他字体大小,按照新的大小重新取模后更新到字库并修改该宏即可 + +/* + *字库软件使用pctolcd2002 + *关键配置:字宽&字高=50;点阵格式:阴码;取模走向:顺向;取模方式:逐列式;每行显示数据:点阵=16,索引=8; + *以下是对“你好”的取模 + * + */static const unsigned char font_50x50[][FONT_SIZE * FONT_SIZE] = +{ + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0xFF, + 0xFF, 0xFF, 0xFE, 0x00, 0x00, 0x7E, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x03, 0xF8, 0xC0, 0x00, 0x00, + 0x7C, 0x00, 0x1F, 0xE0, 0x40, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xC0, 0x00, 0x00, 0x00, 0x40, 0x00, + 0x1F, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x0C, 0x00, 0x02, 0x00, 0x03, 0x00, 0x00, 0x08, 0x00, + 0x04, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, + 0xF0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0xE0, 0x00, 0x00, 0x00, 0x07, 0xC0, 0x3F, 0x80, 0x00, + 0x00, 0x00, 0x1F, 0x01, 0xFE, 0x00, 0x10, 0x00, 0x00, 0xFE, 0x01, 0xF8, 0x00, 0x10, 0x00, 0x07, + 0xFC, 0x00, 0xE0, 0x00, 0x10, 0x00, 0x1F, 0xE4, 0x00, 0x40, 0x00, 0x18, 0x00, 0x1F, 0x84, 0x00, + 0x00, 0x00, 0x1C, 0x00, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00, + 0x1F, 0x00, 0x04, 0x04, 0x80, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x04, 0x7F, 0xFF, 0xFF, 0xFE, 0x00, + 0x00, 0x04, 0x7F, 0xFF, 0xFF, 0xFC, 0x00, 0x00, 0x04, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, + 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x60, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x10, 0x30, 0x00, 0x00, 0x00, 0x00, 0x04, 0x60, 0x1C, 0x00, 0x00, 0x00, 0x00, + 0x05, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x80, 0x07, 0xC0, 0x00, 0x00, 0x00, 0x1F, 0x00, + 0x03, 0xF0, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x01, 0xFE, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x7F, + 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"你"0*/ + }, + + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x04, 0x00, 0x00, 0x01, 0x00, 0x00, 0x80, 0x0C, 0x00, 0x00, 0x01, 0x00, 0x07, 0xC0, 0x18, + 0x00, 0x00, 0x01, 0x00, 0x7F, 0xC0, 0x10, 0x00, 0x00, 0x01, 0x07, 0xFE, 0x40, 0x30, 0x00, 0x00, + 0x01, 0xFF, 0xE0, 0x20, 0x60, 0x00, 0x00, 0x1F, 0xFE, 0x00, 0x20, 0xC0, 0x00, 0x1F, 0xFF, 0xE0, + 0x00, 0x21, 0x80, 0x00, 0x1F, 0xFF, 0x00, 0x00, 0x17, 0x80, 0x00, 0x0F, 0xC1, 0x00, 0x00, 0x1F, + 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0xF8, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x3F, 0xEC, 0x00, 0x00, 0x00, 0x01, 0x07, 0xFF, 0x0E, 0x00, 0x00, 0x00, 0x03, + 0xFF, 0xF8, 0x0F, 0x00, 0x00, 0x00, 0x07, 0xFF, 0x80, 0x07, 0x80, 0x00, 0x00, 0x03, 0xE0, 0x80, + 0x07, 0xC0, 0x00, 0x00, 0x01, 0x00, 0x40, 0x03, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01, 0xC0, + 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x40, 0x00, 0x10, 0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x10, 0x00, 0x00, 0x80, 0x00, + 0x40, 0x00, 0x18, 0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x18, 0x00, 0x00, 0x80, 0x00, 0x40, 0x00, + 0x1C, 0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x1E, 0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x1F, 0x00, + 0x00, 0x81, 0x80, 0x40, 0x00, 0x3E, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x00, 0x80, + 0xFF, 0xFF, 0xFF, 0xF8, 0x00, 0x00, 0x81, 0xE0, 0x40, 0x00, 0x00, 0x00, 0x00, 0x83, 0x40, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x8E, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x9C, 0x00, 0x40, 0x00, 0x00, + 0x00, 0x00, 0xF8, 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 0xF0, 0x00, 0x40, 0x00, 0x00, 0x00, 0x03, + 0xE0, 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 0xC0, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, + 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xC0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*"好"0*/ + }, +}; + +/** + * @brief 带颜色画线函数(直线、斜线) + * @param x1,y1 起点坐标 + * @param x2,y2 终点坐标 + * @param red_data: 像素点R分量 + * @param green_data: 像素点G分量 + * @param blue_data: 像素点B分量 + * @return none + */ +void lcd_draw_colorLine(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint8_t red_data, uint8_t green_data, uint8_t blue_data) +{ + uint16_t i = 0; + int16_t delta_x = 0, delta_y = 0; + int8_t incx = 0, incy = 0; + uint16_t distance = 0; + uint16_t t = 0; + uint16_t x = 0, y = 0; + uint16_t x_temp = 0, y_temp = 0; + + if (y1 == y2) + { + /* 快速画水平线 */ + if (x1 < x2) + { + for (i = x1; i < x2; i++) + { + hal_dsi_rx_ctrl_set_pixel_data(rx_ctrl_handle, i, y1, red_data, green_data, blue_data); + } + } + else + { + for (i = x2; i < x1; i++) + { + hal_dsi_rx_ctrl_set_pixel_data(rx_ctrl_handle, i, y1, red_data, green_data, blue_data); + } + } + return; + } + else + { + /* 画斜线（Bresenham算法） */ + /* 计算两点之间在x和y方向的间距，得到画笔在x和y方向的步进值 */ + delta_x = x2 - x1; + delta_y = y2 - y1; + if (delta_x > 0) + { + //斜线(从左到右) + incx = 1; + } + else if (delta_x == 0) + { + //垂直斜线(竖线) + incx = 0; + } + else + { + //斜线(从右到左) + incx = -1; + delta_x = -delta_x; + } + if (delta_y > 0) + { + //斜线(从左到右) + incy = 1; + } + else if (delta_y == 0) + { + //水平斜线(水平线) + incy = 0; + } + else + { + //斜线(从右到左) + incy = -1; + delta_y = -delta_y; + } + + /* 计算画笔打点距离(取两个间距中的最大值) */ + if (delta_x > delta_y) + { + distance = delta_x; + } + else + { + distance = delta_y; + } + + /* 开始打点 */ + x = x1; + y = y1; + //第一个点无效，所以t的次数加一 + for (t = 0; t <= distance + 1; t++) + { + hal_dsi_rx_ctrl_set_pixel_data(rx_ctrl_handle, x, y, red_data, green_data, blue_data); + + /* 判断离实际值最近的像素点 */ + x_temp += delta_x; + if (x_temp > distance) + { + //x方向越界，减去距离值，为下一次检测做准备 + x_temp -= distance; + //在x方向递增打点 + x += incx; + + } + y_temp += delta_y; + if (y_temp > distance) + { + //y方向越界，减去距离值，为下一次检测做准备 + y_temp -= distance; + //在y方向递增打点 + y += incy; + } + } + } +} + +/** + * @breif 带颜色画矩形函数 + * @param x1,y1: 矩形起始点 + * @param x2,y2 : 矩形终点 + * @param red_data: 像素点R分量 + * @param green_data: 像素点G分量 + * @param blue_data: 像素点B分量 + * @retval none + */ +void lcd_draw_colorRect(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint8_t red_data, uint8_t green_data, uint8_t blue_data) +{ + lcd_draw_colorLine(rx_ctrl_handle, x1, y1, x2, y1, red_data, green_data, blue_data); + lcd_draw_colorLine(rx_ctrl_handle, x1, y1, x1, y2, red_data, green_data, blue_data); + lcd_draw_colorLine(rx_ctrl_handle, x1, y2, x2, y2, red_data, green_data, blue_data); + lcd_draw_colorLine(rx_ctrl_handle, x2, y1, x2, y2, red_data, green_data, blue_data); +} + +/** + * @breif 带颜色画圆函数 + * @param x1,x2: 圆心坐标 + * @param r: 半径 + * @param red_data: 像素点R分量 + * @param green_data: 像素点G分量 + * @param blue_data: 像素点B分量 + * @retval none + */ +void lcd_draw_colorcircle(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x, uint16_t y, uint16_t r, uint8_t red_data, uint8_t green_data, uint8_t blue_data) +{ + int a, b, num; + a = 0; + b = r; + /* 如果圆在屏幕可见区域外，直接退出 */ + if ((x - r < 0) || (x + r > rx_ctrl_handle->base_info.dst_w) || (y - r < 0) || (y + r > rx_ctrl_handle->base_info.dst_h)) + { + TAU_LOGD("circle outof size \n"); + return; + } + while (2 * b * b >= r * r) + { + hal_dsi_rx_ctrl_set_pixel_data(rx_ctrl_handle, x + a, y - b, red_data, green_data, blue_data); + hal_dsi_rx_ctrl_set_pixel_data(rx_ctrl_handle, x - a, y - b, red_data, green_data, blue_data); + hal_dsi_rx_ctrl_set_pixel_data(rx_ctrl_handle, x - a, y + b, red_data, green_data, blue_data); + hal_dsi_rx_ctrl_set_pixel_data(rx_ctrl_handle, x + a, y + b, red_data, green_data, blue_data); + + hal_dsi_rx_ctrl_set_pixel_data(rx_ctrl_handle, x + b, y + a, red_data, green_data, blue_data); + hal_dsi_rx_ctrl_set_pixel_data(rx_ctrl_handle, x + b, y - a, red_data, green_data, blue_data); + hal_dsi_rx_ctrl_set_pixel_data(rx_ctrl_handle, x - b, y - a, red_data, green_data, blue_data); + hal_dsi_rx_ctrl_set_pixel_data(rx_ctrl_handle, x - b, y + a, red_data, green_data, blue_data); + + a++; + num = (a * a + b * b) - r * r; + if (num > 0) + { + b--; + a--; + } + } +} + +/** + * @brief 带颜色输出字体 + * @param x,y: 屏幕的位置 + * @param index: 字所在数组的位置 + * @param font_color: 字的颜色,0xRRGGBB + * @param back_color: 背景颜色,0xRRGGBB + * @return none + */ +void lcd_draw_chinese(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x, uint16_t y, uint16_t index, uint32_t font_color, uint16_t back_color) +{ + uint32_t temp, i, j, size = FONT_SIZE; + uint32_t y0 = y; + uint32_t csize = (size * size) / 8; //得到字体一个字符对应点阵集所占的字节数 + for (i = 0; i < csize; i++) + { + temp = font_50x50[index][i]; + for (j = 0; j < 8; j++) + { + if (temp & 0x80) + { + hal_dsi_rx_ctrl_set_pixel_data(rx_ctrl_handle, x, y, (font_color >> 16) & 0xFF, (font_color >> 8) & 0xFF, font_color & 0xFF); + } + else + { + hal_dsi_rx_ctrl_set_pixel_data(rx_ctrl_handle, x, y, (back_color >> 16) & 0xFF, (back_color >> 8) & 0xFF, back_color & 0xFF); + } + temp <<= 1; + y++; + if ((y - y0) == size) + { + y = y0; + x++; + break; + } + } + } +} + diff --git a/src/app/draw_mode/draw_mode_lib.h b/src/app/draw_mode/draw_mode_lib.h new file mode 100644 index 0000000..b8eed7a --- /dev/null +++ b/src/app/draw_mode/draw_mode_lib.h @@ -0,0 +1,56 @@ +/******************************************************************************* +* +* +* File: draw_mode_lib.h +* Description draw mode 函数申明 +* Version V0.1 +* Date 2022-06-21 +* Author Tempest +*******************************************************************************/ +#ifndef __DRAW_MODE_H__ +#define __DRAW_MODE_H__ + + +/** + * @brief 带颜色画线函数(直线、斜线) + * @param x1,y1: 起点坐标 + * @param x2,y2: 终点坐标 + * @param red_data: 像素点R分量 + * @param green_data: 像素点G分量 + * @param blue_data: 像素点B分量 + * @return none + */ +void lcd_draw_colorLine(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint8_t red_data, uint8_t green_data, uint8_t blue_data); + +/** + * @breif 带颜色画矩形函数 + * @param x1,y1: 矩形起始点 + * @param x2,y2 : 矩形终点 + * @param red_data: 像素点R分量 + * @param green_data: 像素点G分量 + * @param blue_data: 像素点B分量 + * @retval none + */ +void lcd_draw_colorRect(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint8_t red_data, uint8_t green_data, uint8_t blue_data); + +/** + * @breif 带颜色画圆函数 + * @param x,y: 圆心坐标 + * @param r: 半径 + * @param red_data: 像素点R分量 + * @param green_data: 像素点G分量 + * @param blue_data: 像素点B分量 + * @retval none + */ +void lcd_draw_colorcircle(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x, uint16_t y, uint16_t r, uint8_t red_data, uint8_t green_data, uint8_t blue_data); + +/** + * @brief 带颜色输出字体 + * @param x,y: 屏幕的位置 + * @param index: 字所在数组的位置 + * @param font_color: 字的颜色,0xRRGGBB + * @param back_color: 背景颜色,0xRRGGBB + * @return none + */ +void lcd_draw_chinese(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x, uint16_t y, uint16_t index, uint32_t font_color, uint16_t back_color); +#endif diff --git a/src/app/main.c b/src/app/main.c new file mode 100644 index 0000000..c470c3a --- /dev/null +++ b/src/app/main.c @@ -0,0 +1,26 @@ +#include +#include +#include +#include "test_cfg_global.h" +#include "tau_log.h" +#include "hal_system.h" +#include "board.h" +#include "module_demo_main.h" +int main() +{ + board_Init(); + + while (1) + { +#if _MODULE_DEMO_ENABLE + module_demo_main(); +#endif + + +#if _DEMO_GOOGLE_P8P_EN + google_p8p_demo(); +#endif + TAU_LOGD("668 Demo\n"); + while (1); + } +} diff --git a/src/app/module_demo/README.txt b/src/app/module_demo/README.txt new file mode 100644 index 0000000..ed6980f --- /dev/null +++ b/src/app/module_demo/README.txt @@ -0,0 +1 @@ +module_demo:存放hal层给客户的demo code,每个客户都需要release \ No newline at end of file diff --git a/src/app/module_demo/demo_hal_crc.c b/src/app/module_demo/demo_hal_crc.c new file mode 100644 index 0000000..e675e8c --- /dev/null +++ b/src/app/module_demo/demo_hal_crc.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* +* +* File: demo_hal_crc.c +* Description： crc demo源文件 +* Version： V0.1 +* Date: 2023-07-27 +* Author： zzf + *******************************************************************************/ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "demo_hal_crc.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "crc-log" + +/* CRC计算方式，0-CPU方式； 1-DMA方式 */ +#define CRC_DMA_CAL_EN (1) + +/* for max total of test elements */ +#define CRC_ELEMENT_MAX_TATOL (32u) +/* for crc initial POL regs value */ +#define CRC_32_POL_VALUE0 (0x04C11DB7u) +#define CRC_16_POL_VALUE0 (0x8005u) +/* for crc calculate in crc software calculate */ +#define CRC_SEED_VALUE_0 (0u) +#define CRC_SEED_VALUE_F (0xFFFFu) + +/******************************************************************************* +* 3.Global function and Global variable declarations +*******************************************************************************/ +#if CRC_DMA_CAL_EN +/* all the one element value crc calculate for software crc */ +static uint32_t sg_crc32_arry[CRC_ELEMENT_MAX_TATOL] = +{ + 0x00000000, 0xFFFFFFFF, 0xAAAAAAAA, 0xEEEEEEEE, 0x55555555, 0x66666666, 0x11111111, 0x77777777, + 0x12345678, 0x456789AB, 0x89ABCDEF, 0x3456789A, 0x6789ABCD, 0x9ABCDEF0, 0xBCDEF012, 0xFEDCAB98, + 0x5a5aa5a5, 0x37377373, 0x98988989, 0x76767676, 0x41233214, 0x67433467, 0x91DF91DF, 0x76347634, + 0x46378912, 0x57351059, 0xABFC9483, 0x837204AF, 0x41057DBA, 0x893CD024, 0x56378105, 0xFA34610B, +}; +#else +/* all the one element value crc calculate for software crc */ +static uint16_t sg_crc16_element_arry[CRC_ELEMENT_MAX_TATOL] = +{ + 0x0000, 0xFFFF, 0xAAAA, 0x2222, 0x3333, 0xDDDD, 0x9999, 0x8888, + 0x1234, 0x5678, 0x9ABC, 0x2345, 0x4567, 0xABCD, 0xCDEF, 0x789A, + 0x5a5a, 0x2323, 0x6868, 0x5aa5, 0x7887, 0x8558, 0x6336, 0xAFAF, + 0x3194, 0x7853, 0x7733, 0x76DE, 0x89CA, 0x7401, 0x7392, 0xD2A8, +}; +#endif +/******************************************************************************* +* 4.Global function prototypes +*******************************************************************************/ +#if CRC_DMA_CAL_EN +/** +* @brief DMA计算CRC值回调函数 +* @param calculate_result: CRC计算结果 +* @retval None +*/ +void demo_crc_dma_callback(uint32_t calculate_result) +{ + TAU_LOGD("dma demo[0x%x]\n", calculate_result); +} + +/** +* @brief DMA计算CRC值 +* @param None +* @retval true or false +*/ +bool demo_crc_array_dma_cal(void) +{ + crc_ctrl_handle_t crc_cfg_para = + { + CRC_32_POL_VALUE0, + CRC_SEED_VALUE_0, + CRC_32_BIT_PROTOCOL, + CRC_FXOR_ENABLE, + CRC_REV_ONLY_BITS_TRANSPOSE, + CRC_REV_ONLY_BITS_TRANSPOSE + }; + + hal_crc_dma_init(&crc_cfg_para, demo_crc_dma_callback, sg_crc32_arry, CRC_ELEMENT_MAX_TATOL); + + hal_crc_dma_start(); + + return true; +} +#else +/** +* @brief CPU阻塞式计算CRC值 +* @param None +* @retval true or false +*/ +bool demo_crc_array_cal(void) +{ + crc_ctrl_handle_t crc_cfg_para = + { + CRC_16_POL_VALUE0, + CRC_SEED_VALUE_F, + CRC_16_BIT_PROTOCOL, + CRC_FXOR_ENABLE, + CRC_REV_BOTH_TRANSPOSE, + CRC_REV_BOTH_TRANSPOSE + }; + + hal_crc_init(&crc_cfg_para); + uint32_t output_crc = hal_crc_cal(sg_crc16_element_arry, CRC_ELEMENT_MAX_TATOL); + TAU_LOGD("cpu demo[0x%x]\n", output_crc); + + return true; +} +#endif + +/** +* @brief demo测试接口函数 +* @param None +* @retval None +*/ +void demo_hal_crc_case(void) +{ + TAU_LOGD("HAL CRC DEMO.\n"); + +#if CRC_DMA_CAL_EN + demo_crc_array_dma_cal(); // DMA方式计算 +#else + demo_crc_array_cal(); // CPU方式计算 +#endif + +} + diff --git a/src/app/module_demo/demo_hal_crc.h b/src/app/module_demo/demo_hal_crc.h new file mode 100644 index 0000000..3fd8652 --- /dev/null +++ b/src/app/module_demo/demo_hal_crc.h @@ -0,0 +1,41 @@ +/******************************************************************************* +* +* +* File: demo_hal_crc.h +* Description: crc demo头文件 +* Version: V0.1 +* Date: 2023-07-27 +* Author: zzf + *******************************************************************************/ +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "hal_crc.h" +#include "tau_delay.h" +#include "tau_log.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifndef _DEMO_HAL_CRC_H_ +#define _DEMO_HAL_CRC_H_ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief demo测试接口函数 +* @param None +* @retval None +*/ +void demo_hal_crc_case(void); + +#endif //_DEMO_HAL_CRC_H_ diff --git a/src/app/module_demo/demo_hal_dsi_rx.c b/src/app/module_demo/demo_hal_dsi_rx.c new file mode 100644 index 0000000..925de61 --- /dev/null +++ b/src/app/module_demo/demo_hal_dsi_rx.c @@ -0,0 +1,212 @@ +/******************************************************************************* +* +* +* File: demo_hal_dsi_rx.c +* Description: dsi rx 测试文件 +* Version: V0.1 +* Date: 2020-06-12 +* Author: lzy + *******************************************************************************/ + +#include "tau_device_datatype.h" +#include "tau_log.h" +#include "tau_operations.h" +#include "tau_common.h" +#include "hal_dsi_rx_ctrl.h" + +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "demo_hal_dsi_rx" + +//客户可配参数 +//输入配置 +#define INPUT_WIDTH 720 +#define INPUT_HEIGHT 1280 +//输入 MIPI lane rate,video mode 下需要计算delay, command mode可以不设置或者随便设置 +#define INPUT_MIPI_LANE_RATE 481000000 +//输入图像格式 +#define INPUT_COLOR_MODE DSI_RGB888 +//输出数据格式(DSI_DATA_CMD_MODE , DSI_DATA_VIDEO_MODE) +#define INPUT_DATA_MODE DSI_DATA_VIDEO_MODE +//输入mipi lane数量(DSI_RX_LANE_x x为1-4) +#define INPUT_MIPI_LANE_NUM DSI_LANE_4 +//输入为video mode 时数据格式 +#define INPUT_VIDEO_MODEL DSI_NONBURST_EVENT +//输入虚拟通道(0-3) +#define INPUT_VC DSI_VC_0 +//输入的帧率(60/90/120/144Hz) +#define INPUT_FRAME_RATE DSI_FRAME_RATE_60HZ +//输入数据是否DSC压缩 +#define INPUT_COMPRESS false + +//输出配置 +#define OUTPUT_WIDTH 720 +#define OUTPUT_HEIGHT 1280 + +static hal_dsi_rx_ctrl_handle_t *g_rx_ctrl_handle = NULL; + +//客制化DCS处理函数 +static bool cus_dsc_execute(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packet_t *dcs_packet) +{ + TAU_LOGD("cus_dsc_execute DCS[0x%x]\n", dcs_packet->dcs_command); + for (int i = 0; i < dcs_packet->param_length; i ++) + { + TAU_LOGD("cus_dsc_execute param[%d]:0x%x\n", i, dcs_packet->packet_param[i]); + } + +#if 0 + /* ack long cmd */ + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_GEN_LONG_RESPONSE, + DSI_VC_0, + 5, + 0x1, + 0x2, + 0x3, + 0x4, + 0x5); +#else + /* ack short cmd */ + hal_dsi_rx_ctrl_send_ack_cmd(g_rx_ctrl_handle, + DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, + DSI_VC_0, + 1, + 0xC1); +#endif + return true; +} + +static bool ap_dcs_read(uint8_t data_type, uint8_t dcs_cmd, uint8_t param) +{ + if (dcs_cmd == 0xaa) + { + uint8_t cmd[] = {DSI_ACK_DT_DCS_LONG_RESPONSE, + 212, 0, 1, + 0x21, 0x07, 0x2C, 0x27, 0x2B, 0x7A, 0x78, 0x7A, + 0x7D, 0x7D, 0x7E, 0x7F, 0x7E, 0x7E, 0x7F, 0x7F, + 0x71, 0xE8, 0x36, 0x2A, 0x2E, 0x07, 0x89, 0x17, + 0x8B, 0x84, 0x28, 0x26, 0x6D, 0xEB, 0x12, 0x34, + 0x79, 0x78, 0x79, 0x7C, 0x7C, 0x7C, 0x7C, 0x7C, + 0x7D, 0x7D, 0x7E, 0x7F, 0x7E, 0x7E, 0x7F, 0x7F, + 0x7C, 0x67, 0x6E, 0x6c, 0x8A, 0x5B, 0x71, 0x00, + 0x7D, 0x7D, 0x7E, 0x7F, 0x7E, 0x7E, 0x7F, 0x7F, + 0x7d, 0x68, 0x61, 0xd9, 0x1A, 0x5B, 0xa7, 0x00, + 0x7D, 0x7D, 0x7E, 0x7F, 0x7E, 0x7E, 0x7F, 0x7F, + 0x7e, 0x69, 0x63, 0xe9, 0x3c, 0x5B, 0xfE, 0x00, + 0x7D, 0x7D, 0x7E, 0x7F, 0x7E, 0x7E, 0x7F, 0x7F, + 0x7f, 0x60, 0x3E, 0x6f, 0x9b, 0x5B, 0x45, 0x00, + 0x7D, 0x7D, 0x7E, 0x7F, 0x7E, 0x7E, 0x7F, 0x7F, + 0x70, 0x61, 0x4E, 0xc9, 0xdA, 0x5B, 0x69, 0x00, + 0x7D, 0x7D, 0x7E, 0x7F, 0x7E, 0x7E, 0x7F, 0x7F, + 0x71, 0x63, 0xaE, 0x88, 0x0A, 0x5B, 0x30, 0x00, + 0x12, 0x34, 0x56, 0x78, 0x9a, 0xab, 0xcd, 0xef, + 0x11, 0x22, 0x33, 0x44, 0x0A, 0x5B, 0x30, 0x00, + 0x12, 0x34, 0x56, 0x78, 0x9a, 0xab, 0xcd, 0xef, + 0x7f, 0x60, 0x3E, 0x6f, 0x9b, 0x5B, 0x45, 0x00, + 0x7D, 0x7D, 0x7E, 0x7F, 0x7E, 0x7E, 0x7F, 0x7F, + 0x7f, 0x60, 0x3E, 0x6f, 0x9b, 0x5B, 0x45, 0x00, + 0x7D, 0x7D, 0x7E, 0x7F, 0x7E, 0x7E, 0x7F, 0x7F, + 0x71, 0xE8, 0x36, 0x2A, 0x2E, 0x07, 0x89, 0x17, + 0x8B, 0x84, 0x28, 0x26, 0x6D, 0xEB, 0x12, 0x34, + 0x11, 0x22, 0x33, 0x44 + }; + /*长包超128字节发送*/ + hal_dsi_rx_ctrl_ack_long_cmd(g_rx_ctrl_handle, sizeof(cmd) / sizeof(uint8_t), cmd); + } + else if (dcs_cmd == 0xFE) + { + uint16_t return_size; + return_size = hal_dsi_rx_ctrl_get_max_ret_size(g_rx_ctrl_handle); + if (return_size == 3) + { + uint8_t cmd[] = {DSI_ACK_DT_DCS_LONG_RESPONSE, 3, 0, 1, 0x40, 0x00, 0x03}; + + hal_dsi_rx_ctrl_ack_long_cmd(g_rx_ctrl_handle, sizeof(cmd) / sizeof(uint8_t), cmd); + } + else if (return_size == 32) + { + + uint8_t cmd[] = {DSI_ACK_DT_DCS_LONG_RESPONSE, + 32, 0, 1, 0x01, 0xc4, 0x01, 0xcd, 0x01, 0xfb, 0x55, 0x55, + 0x55, 0x4e, 0x4c, 0x4e, 0x2e, 0x2d, 0x31, 0x30, + 0x30, 0x38, 0x49, 0x42, 0x49, 0x3c, 0x39, 0x47, + 0x01, 0x07, 0x2b, 0xfa, 0x22, 0x19, 0x32, 0x02 + }; + + hal_dsi_rx_ctrl_ack_long_cmd(g_rx_ctrl_handle, sizeof(cmd) / sizeof(uint8_t), cmd); + } + } + + TAU_LOGD("r %x\n", dcs_cmd); + return true; +} + + +static const hal_dcs_execute_entry_t g_cus_rx_dcs_execute_table[] = +{ + {0x83, cus_dsc_execute, false}, //cus dcs 0x83, 处理函数为cus_dsc_execute，不需要立即运行，在while里异步即可 + {0, NULL, false} //{0,NULL,false} 数组最后一个固定成员，作为table结尾的判断标准 +}; + +static void open_mipi_rx() +{ + if (g_rx_ctrl_handle == NULL) + { + g_rx_ctrl_handle = hal_dsi_rx_ctrl_create_handle(); + } + + g_rx_ctrl_handle->base_info.src_w = INPUT_WIDTH; + g_rx_ctrl_handle->base_info.src_h = INPUT_HEIGHT; + g_rx_ctrl_handle->base_info.dst_w = OUTPUT_WIDTH; + g_rx_ctrl_handle->base_info.dst_h = OUTPUT_HEIGHT; + g_rx_ctrl_handle->base_info.src_frate = INPUT_FRAME_RATE; + g_rx_ctrl_handle->base_info.src_mode = INPUT_DATA_MODE; + g_rx_ctrl_handle->rx_color_mode = INPUT_COLOR_MODE; + g_rx_ctrl_handle->rx_lanes = INPUT_MIPI_LANE_NUM; + g_rx_ctrl_handle->rx_nonburst_models = INPUT_VIDEO_MODEL; + g_rx_ctrl_handle->compress_en = INPUT_COMPRESS; + g_rx_ctrl_handle->rx_hsclk_rate = INPUT_MIPI_LANE_RATE; + g_rx_ctrl_handle->extra_info.flow_control_mode = FC_AUTO_MODE; + g_rx_ctrl_handle->cus_dcs_entry_table = g_cus_rx_dcs_execute_table; + g_rx_ctrl_handle->rx_dcs_read_entry = ap_dcs_read; + + /*PIN28~PIN19依次为21c03*/ + g_rx_ctrl_handle->rx_lane_swap = RX_LANE_SWAP_2103; + + /* 对 lane0~lane3 以及clk lane 进行PN交换*/ + g_rx_ctrl_handle->base_info.pn_swap = RX_LANE_0_PN_SWAP | RX_LANE_1_PN_SWAP | RX_LANE_2_PN_SWAP | RX_LANE_3_PN_SWAP | RX_LANE_CLK_PN_SWAP; + + if (g_rx_ctrl_handle->compress_en == true) + { + //hal_dsi_rx_ctrl_pre_init_pps(g_rx_ctrl_handle, pps, 128); + } + hal_dsi_rx_ctrl_init(g_rx_ctrl_handle); +#if 0 + //使用盒子发送读命令 0xA,0xB,0xC,0xD,0xE,0xF,0x1E,0x1D + hal_dsi_rx_ctrl_set_auto_ack(g_rx_ctrl_handle, HAL_RX_QRESP_CODE0, DSI_ACK_DT_DCS_SHORT_RESPONSE_1B, 0x0F, 1, 0xab); + hal_dsi_rx_ctrl_set_auto_ack(g_rx_ctrl_handle, HAL_RX_QRESP_CODE1, DSI_ACK_DT_DCS_SHORT_RESPONSE_2B, 0x0e, 2, 0xef, 0xcd); + hal_dsi_rx_ctrl_set_auto_ack(g_rx_ctrl_handle, HAL_RX_QRESP_CODE2, DSI_ACK_DT_GEN_SHORT_RESPONSE_1B, 0x0a, 1, 0x12); + hal_dsi_rx_ctrl_set_auto_ack(g_rx_ctrl_handle, HAL_RX_QRESP_CODE3, DSI_ACK_DT_GEN_SHORT_RESPONSE_2B, 0x0b, 2, 0x34, 0x56); + hal_dsi_rx_ctrl_set_auto_ack(g_rx_ctrl_handle, HAL_RX_QRESP_CODE4, DSI_ACK_DT_DCS_LONG_RESPONSE, 0x0c, 4, 0x12, 0x34, 0x56, 0x78); + hal_dsi_rx_ctrl_set_auto_ack(g_rx_ctrl_handle, HAL_RX_QRESP_CODE5, DSI_ACK_DT_GEN_LONG_RESPONSE, 0x0d, 4, 0xab, 0xcd, 0xef, 0x9a); + hal_dsi_rx_ctrl_set_auto_ack(g_rx_ctrl_handle, HAL_RX_QRESP_CODE6, DSI_ACK_DT_GEN_LONG_RESPONSE, 0x1e, 8, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8); + hal_dsi_rx_ctrl_set_auto_ack(g_rx_ctrl_handle, HAL_RX_QRESP_CODE7, DSI_ACK_DT_DCS_LONG_RESPONSE, 0x1d, 8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x10); +#endif + hal_dsi_rx_ctrl_start(g_rx_ctrl_handle); +} + +/** +* @brief test system 主函数 +* @param none +* @retval none +*/ +void demo_hal_dsi_rx_case() +{ + open_mipi_rx(); + TAU_LOGD("open_mipi_rx done !\n"); + while (1) + { + hal_dsi_rx_ctrl_dcs_async_handler(g_rx_ctrl_handle); + } +} diff --git a/src/app/module_demo/demo_hal_dsi_rx.h b/src/app/module_demo/demo_hal_dsi_rx.h new file mode 100644 index 0000000..18d9ad1 --- /dev/null +++ b/src/app/module_demo/demo_hal_dsi_rx.h @@ -0,0 +1,22 @@ +/******************************************************************************* +* +* +* File: demo_hal_dsi_rx.h +* Description: dsi rx 测试头文件 +* Version: V0.1 +* Date: 2020-06-12 +* Author: lzy + *******************************************************************************/ + +#ifndef __DEMO_HAL_DSI_RX_H__ +#define __DEMO_HAL_DSI_RX_H__ + +/** +* @brief test system 主函数 +* @param none +* @retval none +*/ +void demo_hal_dsi_rx_case(void); + +#endif + diff --git a/src/app/module_demo/demo_hal_dsi_tx.c b/src/app/module_demo/demo_hal_dsi_tx.c new file mode 100644 index 0000000..4aa1c85 --- /dev/null +++ b/src/app/module_demo/demo_hal_dsi_tx.c @@ -0,0 +1,389 @@ +/******************************************************************************* +* +* +* File: demo_hal_dsi_tx.c +* Description： dsi_tx demo源文件 +* Version： V0.1 +* Date: 2023-07-27 +* Author： zzf + *******************************************************************************/ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "demo_hal_dsi_tx.h" +#if AMOLED_NT37280 +#include "hal_swire.h" +#endif + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "tx-log" + +#define DEMO_TX_VPG_EN (0) // 只适用于video模式输入video模式输出 +#define DEMO_RX_GEN_PATTERN (0) // TX VPG和RX pattern不建议同时打开 +#define DEMO_CCM_EN (0) // 基于RX pattern数据通路进行CCM调整 +#define DEMO_ENDIAN_EN (0) // RGB大小端配置 +#define DEMO_OVERWRITE_EN (0) // Overwrite功能配置 +#define DEMO_EDGE_DECT_EN (0) // 边缘检测功能配置 +#define DEMO_EDGE_ENHANCE_EN (0) // 边缘增强功能配置 +#define DEMO_FC_EN (0) // false color功能配置 +#define DEMO_BCS_EN (0) // BCS调整功能配置 +#define DEMO_BTA_LP_EN (0) // LP模式下BTA使用 +#define DEMO_BTA_HS_EN (0) // HS传输过程中BTA使用 + + +/* base_info输入端信息 */ +#define INPUT_WIDTH (1440) +#define INPUT_HEIGHT (2960) +#define INPUT_SRC_FRATE DSI_FRAME_RATE_60HZ +/* 输出数据格式(DSI_DATA_CMD_MODE , DSI_DATA_VIDEO_MODE) */ +#define DSI_INPUT_DATA_MODE DSI_DATA_VIDEO_MODE +#define DSI_OUTPUT_DATA_MODE DSI_DATA_VIDEO_MODE +/* vid模式选择 */ +#define OUTPUT_VID_SEL_MODE DSI_BURST_MODE +/* 虚拟通道(0-3) */ +#define VIRTUAL_CHANNEL DSI_VC_0 +/* TD_RSTN pin脚使用定义宏 */ +#define PIN_TD_RSTN IO_PAD_TD_RSTN + +#if DEMO_RX_GEN_PATTERN +/*输入mipi lane数量(DSI_RX_LANE_x x为1-4)*/ +#define INPUT_MIPI_LANE_NUM DSI_LANE_4 +/*输入图像格式*/ +#define INPUT_COLOR_MODE DSI_RGB888 +/*video mode输入时数据格式*/ +#define INPUT_VIDEO_MODEL DSI_NONBURST_EVENT +/*输入MIPI lane rate,video mode下需要计算delay,command mode可以不设置或者随便设置*/ +#define INPUT_MIPI_LANE_RATE (1200000000) +/*IPI pattern fps*/ +#define PATTERN_FPS (60) +#endif + +/******************************************************************************* +* 3.Global function and Global variable declarations +*******************************************************************************/ +static hal_dsi_tx_ctrl_handle_t *g_tx_ctrl_handle = NULL; +#if DEMO_RX_GEN_PATTERN +static hal_dsi_rx_ctrl_handle_t *g_rx_ctrl_handle = NULL; +static uint8_t g_rx_pattern_sel = 0; // 0:Vertical mode ; 1:Horizontal mode +#endif +static bool panel_init = false; + +#if DEMO_BTA_LP_EN +static uint8_t bta_ack_data = 0; +#endif + +#if DEMO_BTA_HS_EN +static bool sg_bta_need_flag = true; +#endif +/******************************************************************************* +* 4.Global function prototypes +*******************************************************************************/ +#if AMOLED_NT37280 +/** +* @brief timer回调函数用于swire输出 +* @param data: 回调参数 +* @retval 无 +*/ +static void demo_tx_timer_callback(void *data) +{ + hal_swire_set_waveform(12, 12, 12, 12); + hal_swire_set_pulse(32); +} + +/** +* @brief 打开屏背光 +* @param 无 +* @retval 无 +*/ +static void demo_tx_panel_backlight_on(void) +{ + hal_gpio_init_output(IO_PAD_AP_PWMEN, IO_LVL_HIGH); + hal_swire_init(); + hal_swire_enable(true); + + hal_swire_set_waveform(12, 12, 12, 12); + hal_swire_set_pulse(36); + + hal_timer_init(TIMER_NUM1); + hal_timer_start(TIMER_NUM1, 16, demo_tx_timer_callback, NULL); + +} +#endif + +/** +* @brief PANEL初始化 +* @param None +* @retval None +**/ +void demo_panel_init(void) +{ +#if AMOLED_NT37280 + demo_tx_panel_backlight_on(); +#endif + + /*初始化TD_RSTN并产生屏端复位信号*/ + hal_gpio_init_output(PIN_TD_RSTN, IO_LVL_HIGH); + hal_gpio_set_output_data(PIN_TD_RSTN, IO_LVL_HIGH); + delayMs(10); + hal_gpio_set_output_data(PIN_TD_RSTN, IO_LVL_LOW); + delayMs(10); + hal_gpio_set_output_data(PIN_TD_RSTN, IO_LVL_HIGH); + delayMs(10); + + /*bta read register*/ +#if DEMO_BTA_LP_EN + hal_dsi_tx_ctrl_read_cmd(0x06, 0, 0xDA, 1, &bta_ack_data); + TAU_LOGD("DA[0x%x]\n", bta_ack_data); +#endif + + /*initial code*/ +#if LCD_PT628_CSOT + TAU_LOGD("LCD_PT628_CSOT pannel init\n"); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xBF, 0x00); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xC0, 0x00); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x00, 0x00); + hal_dsi_tx_ctrl_write_cmd(0x39, 0, 4, 0xFF, 0x87, 0x56, 0x01); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x00, 0x80); + hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0xFF, 0x87, 0x56); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x00, 0xE8); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xC0, 0x20); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x00, 0x00); + hal_dsi_tx_ctrl_write_cmd(0x39, 0, 4, 0xFF, 0x87, 0x56, 0x01); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x00, 0x80); + hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0xFF, 0x87, 0x56); + hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x11); + delayMs(120); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x35, 0x00); + hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, 0x0F, 0xFF); + hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x29); + +#elif AMOLED_NT37280 + TAU_LOGD("AMOLED_NT37280 pannel init\n"); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xFF, 0xE0); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xFB, 0x01); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x18, 0x80); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x1A, 0x15); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x73, 0x01); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x89, 0x7F); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x0D, 0x9B); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x46, 0x17); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xFF, 0xF0); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xFB, 0x01); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x54, 0x03); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x9C, 0x00); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xFF, 0x20); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xFB, 0x01); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x34, 0x00); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x35, 0x66); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x36, 0x66); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xFF, 0x10); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xFB, 0x01); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x88, 0x07); + hal_dsi_tx_ctrl_write_cmd(0x39, 0, 5, 0x2A, 0x00, 0x00, 0x04, 0x37); + hal_dsi_tx_ctrl_write_cmd(0x39, 0, 5, 0x2B, 0x00, 0x00, 0x08, 0xE7); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x7F, 0x07); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xE9, 0x00); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xBF, 0x00); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0xC0, 0x00); + hal_dsi_tx_ctrl_write_cmd(0x15, 0, 2, 0x35, 0x00); //TE 35=00是标准60Hz; 35=01是有很多小信号 + hal_dsi_tx_ctrl_write_cmd(0x29, 0, 3, 0x51, 0x0F, 0xFF); //CABC + hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x11); + delayMs(120); + hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x29); + delayMs(10); +#endif + +} + +/** +* @brief RX初始化和开启 +* @param None +* @retval None +**/ +static void demo_open_mipi_rx(void) +{ + /*RX demo详细请参考demo_hal_dsi_rx*/ +#if DEMO_RX_GEN_PATTERN + /* 创建rx ctrl handle */ + if (g_rx_ctrl_handle == NULL) + { + g_rx_ctrl_handle = hal_dsi_rx_ctrl_create_handle(); + } + g_rx_ctrl_handle->base_info.src_w = INPUT_WIDTH; + g_rx_ctrl_handle->base_info.src_h = INPUT_HEIGHT; + g_rx_ctrl_handle->base_info.dst_w = __DPI_HACT; + g_rx_ctrl_handle->base_info.dst_h = __DPI_VACT; + g_rx_ctrl_handle->rx_hsclk_rate = INPUT_MIPI_LANE_RATE; + g_rx_ctrl_handle->base_info.src_frate = INPUT_SRC_FRATE; + g_rx_ctrl_handle->base_info.src_mode = DSI_INPUT_DATA_MODE; + g_rx_ctrl_handle->rx_color_mode = INPUT_COLOR_MODE; + g_rx_ctrl_handle->rx_lanes = INPUT_MIPI_LANE_NUM; + g_rx_ctrl_handle->rx_nonburst_models = INPUT_VIDEO_MODEL; + + /* 初始化rx ctrl */ + hal_dsi_rx_ctrl_init(g_rx_ctrl_handle); + + /* 配置RX video pattern */ + hal_dsi_rx_ctrl_enable_test_pattern(g_rx_ctrl_handle, g_rx_pattern_sel, true, PATTERN_FPS); + + /* 启动rx ctrl */ + hal_dsi_rx_ctrl_start(g_rx_ctrl_handle); +#endif + +} + +/** +* @brief TX初始化和开启 +* @param None +* @retval None +**/ +static void demo_open_mipi_tx(void) +{ + /*创建TX实例*/ + if (g_tx_ctrl_handle == NULL) + { + g_tx_ctrl_handle = hal_dsi_tx_ctrl_create_handle(); + } + g_tx_ctrl_handle->lane_num = _LANE_NUMBER; + g_tx_ctrl_handle->channel_id = VIRTUAL_CHANNEL; + g_tx_ctrl_handle->vid_mode = OUTPUT_VID_SEL_MODE; + g_tx_ctrl_handle->cmd_tx_type = _CMD_TYPE; + g_tx_ctrl_handle->dpi_vsa = __DPI_VSA; + g_tx_ctrl_handle->dpi_vbp = __DPI_VBP; + g_tx_ctrl_handle->dpi_vfp = __DPI_VFP; + g_tx_ctrl_handle->dpi_hsa = __DPI_HSA; + g_tx_ctrl_handle->dpi_hbp = __DPI_HBP; + g_tx_ctrl_handle->dpi_hfp = __DPI_HFP; + g_tx_ctrl_handle->base_info.src_w = INPUT_WIDTH; + g_tx_ctrl_handle->base_info.src_h = INPUT_HEIGHT; + g_tx_ctrl_handle->base_info.dst_w = __DPI_HACT; + g_tx_ctrl_handle->base_info.dst_h = __DPI_VACT; + g_tx_ctrl_handle->base_info.src_frate = INPUT_SRC_FRATE; + g_tx_ctrl_handle->base_info.src_mode = DSI_INPUT_DATA_MODE; + g_tx_ctrl_handle->base_info.dst_mode = DSI_OUTPUT_DATA_MODE; + +#if LCD_PT628_CSOT //RGBG玻璃匹配RGB Driver IC + //remap规则参数， 此款玻璃remapl_rule/remapr_rule使用同一规则； 如果玻璃存在两个规则需要支持，请定义两个数组分别配置remapl_rule/remapr_rule + remap_rule_t remap_rule = + { + 9, 11, 12, 8, 7, 10, 4, 5, 6, 2, 1, 3, + 20, 19, 22, 21, 23, 24, 14, 13, 15, 16, 17, 18 + }; + g_tx_ctrl_handle->pentile_info.pentile_24b = true; // 是否RGB驱动IC搭配RGBG玻璃使用 + g_tx_ctrl_handle->pentile_info.pentile_reverse_en = true; // 是否需要使用芯片本身行反转功能 + g_tx_ctrl_handle->pentile_info.pentile_enable = true; // 是否RGBG格式的数据传输 + g_tx_ctrl_handle->pentile_info.remapl_rule = &remap_rule; // reamp规则1 + g_tx_ctrl_handle->pentile_info.remapr_rule = &remap_rule; // reamp规则2 + g_tx_ctrl_handle->pentile_info.rgb_hact = 900; // 如果是RGB驱动IC搭配RGBG玻璃使用，此处配置RGB驱动IC的分辨率；dst_w按玻璃分辨率进行配置 + /* RGBG 屏幕补黑配置，此款玻璃两块补黑区域均参与子像素重排*/ + g_tx_ctrl_handle->pentile_info.blank_info0.blank_en = 1; // 是否使用补黑区域0 + g_tx_ctrl_handle->pentile_info.blank_info0.remap_en = 1; // 补黑区域0是否参与remap重排 + g_tx_ctrl_handle->pentile_info.blank_info0.st_col = 0; // 补黑区域0起始位置，按有效子像素序号进行计算 + g_tx_ctrl_handle->pentile_info.blank_info0.width = 12; // 补黑区域0补黑宽度，按子像素级计算 + g_tx_ctrl_handle->pentile_info.blank_info1.blank_en = 1; // 是否使用补黑区域1 + g_tx_ctrl_handle->pentile_info.blank_info1.remap_en = 1; // 补黑区域1是否参与remap重排 + g_tx_ctrl_handle->pentile_info.blank_info1.st_col = 1248; // 补黑区域1起始位置，按有效子像素序号进行计算，必须大于补黑区域0的起始位置 + g_tx_ctrl_handle->pentile_info.blank_info1.width = 216; // 补黑区域1补黑宽度，按子像素级计算 +#endif + +#if DEMO_ENDIAN_EN + hal_dsi_tx_ctrl_set_endianness(DPI_ENDIAN_BGR);// 默认RGB输出，可以更改为BGR 需要在初始化之前调用 +#endif + + /*调用初始化接口进行TX初始化*/ + hal_dsi_tx_ctrl_init(g_tx_ctrl_handle); + + /*屏幕初始化，复位时序和发送initial code*/ + if (!panel_init) + { + demo_panel_init(); + panel_init = true; + } + +#if DEMO_TX_VPG_EN /*使用TX VPG测试TX是否正常工作*/ + hal_dsi_tx_ctrl_set_vpg(true, TX_VPG_V_COLOR, false); +#endif + + /*tx start开始传输高速数据*/ + hal_dsi_tx_ctrl_start(g_tx_ctrl_handle); + + /*可选功能配置，在任意时刻均可调用 start*/ +#if DEMO_CCM_EN + ccm_coef_t coef; + coef.coef_c00 = 0x1f3; + coef.coef_c01 = 0xf3a; + coef.coef_c02 = 0xfd3; + coef.coef_c10 = 0xf9c; + coef.coef_c11 = 0x19c; + coef.coef_c12 = 0xfca; + coef.coef_c20 = 0x27; + coef.coef_c21 = 0xf46; + coef.coef_c22 = 0x193; + hal_dsi_tx_ctrl_set_ccm(&coef); +#endif + +#if DEMO_OVERWRITE_EN + hal_dsi_tx_ctrl_set_overwrite_rgb(0x00, 0x00, 0xFF); //蓝色图形数据输出 参数为R/G/B灰度值 + hal_dsi_tx_ctrl_overwrite_enable(true); //开启overwrite功能 + /*........*/ + //hal_dsi_tx_ctrl_overwrite_enable(false); //需要关闭overwrite功能时调用 +#endif + +#if DEMO_EDGE_DECT_EN + dsi_tx_edge_dect_t edge_dect_para = {0x10, true}; + hal_dsi_tx_ctrl_set_edge_dect(&edge_dect_para, true); +#endif + +#if DEMO_EDGE_ENHANCE_EN + dsi_tx_edge_enh_t edge_enh_para = {true, 64, 4, 64, 0}; + hal_dsi_tx_ctrl_set_edge_enhance(&edge_enh_para, true); +#endif + +#if DEMO_FC_EN + dsi_tx_fc_t fc_para = {64, 64}; + hal_dsi_tx_ctrl_set_fc(&fc_para, true); +#endif + +#if DEMO_BCS_EN + dsi_tx_bcs_t bcs_cfg = {0x00, 0x10, 0x10}; // 参数含义：{明亮度，对比度，饱和度} + hal_dsi_tx_ctrl_set_bcs(&bcs_cfg, true); +#endif + /*可选功能配置，在任意时刻均可调用 end*/ + +} + +/** +* @brief demo测试接口函数 +* @param None +* @retval None +*/ +void demo_dsi_tx_case(void) +{ + TAU_LOGD("DSI TX DEMO.\n"); + demo_open_mipi_rx(); + demo_open_mipi_tx(); + + while (1) + { +#if DEMO_BTA_HS_EN + if (sg_bta_need_flag) //当需要进行BTA回读的时候置标志位，等待Vporch阶段进行BTA回读获取有效数据 + { + uint8_t bta_data = 0; + if (hal_dsi_tx_ctrl_vporch_bta_opera(0x06, 0xDA, 1, &bta_data)) + { + //Vporch阶段进行BTA回读获取到有效数据，关闭本次回读流程 + sg_bta_need_flag = false; + TAU_LOGD("hs bta[0x%x]\n", bta_data); + } + } +#endif + } + +} + diff --git a/src/app/module_demo/demo_hal_dsi_tx.h b/src/app/module_demo/demo_hal_dsi_tx.h new file mode 100644 index 0000000..3d93371 --- /dev/null +++ b/src/app/module_demo/demo_hal_dsi_tx.h @@ -0,0 +1,77 @@ +/******************************************************************************* +* +* +* File: demo_hal_dsi_tx.h +* Description: dsi-tx demo头文件 +* Version: V0.1 +* Date: 2023-07-27 +* Author: zzf + *******************************************************************************/ +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "hal_dsi_tx_ctrl.h" +#include "hal_dsi_rx_ctrl.h" +#include "tau_delay.h" +#include "tau_log.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifndef _DEMO_HAL_DSI_TX_H_ +#define _DEMO_HAL_DSI_TX_H_ + +#define LCD_PT628_CSOT (1) //4lane RGBG-1242x2699 RGB-900X2688 +#define AMOLED_NT37280 (0) //4lane 1080X2280 + +#if LCD_PT628_CSOT + +#define _LANE_NUMBER (4) //数据lane的个数 +#define _CMD_TYPE (DSI_CMD_TX_LP) //0-HS,1-LP; + +#define __DPI_VSA (16) //VSYNC宽度 +#define __DPI_VBP (16) //VSYNC后的无效像素 +#define __DPI_VACT (2688) //玻璃V分辨率定义 +#define __DPI_VFP (123 ) //VSYNC前的无效像素 + +#define __DPI_HSA (6) //HSYNC宽度 +#define __DPI_HBP (18) //HSYNC后的无效像素 +#define __DPI_HACT (1242) //玻璃H分辨率定义 +#define __DPI_HFP (32) //HSYNC前的无效像素 + +#elif AMOLED_NT37280 + +#define _LANE_NUMBER (4) //数据lane的个数 +#define _CMD_TYPE (DSI_CMD_TX_LP) //0-HS,1-LP; + +#define __DPI_VSA (4) //VSYNC宽度 +#define __DPI_VBP (28) //VSYNC后的无效像素 +#define __DPI_VACT (2280) //V分辨率定义 +#define __DPI_VFP (10) //VSYNC前的无效像素 + +#define __DPI_HSA (8) //HSYNC宽度 +#define __DPI_HBP (16) //HSYNC后的无效像素 +#define __DPI_HACT (1080) //H分辨率定义 +#define __DPI_HFP (36) //HSYNC前的无效像素 + +#endif + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief demo测试接口函数 +* @param None +* @retval None +*/ +void demo_dsi_tx_case(void); + +#endif diff --git a/src/app/module_demo/demo_hal_flash.c b/src/app/module_demo/demo_hal_flash.c new file mode 100644 index 0000000..4843e0e --- /dev/null +++ b/src/app/module_demo/demo_hal_flash.c @@ -0,0 +1,218 @@ +/******************************************************************************* +* Copyright (C) 2021-2022, All Rights Reserved. +* +* File: test_hal_flash.c +* Description： hal_flash 测试用例源文件 +* Version： V0.1 +* Date： 2022-04-21 +* Author： RANDY + *******************************************************************************/ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "demo_hal_flash.h" +#include "hal_flash.h" +#include "tau_delay.h" +#include "tau_log.h" +#include "tau_common.h" +#include "test_cfg_global.h" + +#if _MODULE_DEMO_FLASH_EN +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "demo_flash" + +#define TEST_DATA_SIZE 32 + +#define DATA_BLOCK_SIZE (64*1024) +#define DATA_PAGE_SIZE 1024 + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +static fls_ops_cfg_t *fls_ops_cfg; + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ + +/************************************************************************** +* @name : +* @brief +* @param +* @retval +**************************************************************************/ + +void test_hal_flash_get_public_region_test(void) +{ + uint8_t test_data[TEST_DATA_SIZE] = 0; + TAU_LOGD("test get data public\n"); + + fls_ops_cfg->flash_block = 7;//固定值 + fls_ops_cfg->flash_page = 0;//0-32 + fls_ops_cfg->page_offset_addr = 0; + fls_ops_cfg->data_size = TEST_DATA_SIZE; + fls_ops_cfg->user_data = test_data; + + hal_flash_init(); + + //1 读数据 + hal_flash_public_region_ops(FLASH_PUBLIC_READ, fls_ops_cfg); + + for (uint8_t i = 0; i < TEST_DATA_SIZE; i++) + { + TAU_LOGD("read data[%d]=0x%x ", i, test_data[i]); + } + + //2 写数据 + for (uint32_t i = 0; i < TEST_DATA_SIZE; i++) + { + test_data[i] = i; + } + + hal_flash_public_region_ops(FLASH_PUBLIC_WRITE, fls_ops_cfg); + + //3 回读 + for (uint32_t i = 0; i < TEST_DATA_SIZE; i++) + { + test_data[i] = 0; + } + + hal_flash_public_region_ops(FLASH_PUBLIC_READ, fls_ops_cfg); + + //4 对比 + for (uint8_t i = 0; i < TEST_DATA_SIZE; i++) + { + TAU_LOGD("read data[%d]=0x%x ", i, test_data[i]); + } + +} + + + +// 验证flash UID的读取，16byte的UID +void test_flash_uid_read(void) +{ + uint8_t get_id[16] = {0}; + + TAU_LOGD("test_flash_uid_read begin \n"); + + hal_flash_init(); + + hal_flash_read_uid(get_id, 16); + //不同的IC，ID不一样，存在0x00或者0xFF的情况 + for (uint8_t i = 0; i < 16; i++) + { + TAU_LOGD("read ID [%d]=0x%X \n", i, get_id[i]); + } +} + + +/** +* @brief 获取user_data的数据个数 +* @param 无 +* @retval bool 无 +*/ +void get_user_data_size(void) +{ + uint32_t user_data_size = 0; + + TAU_LOGD("test get data addr\n"); + + user_data_size = hal_flash_get_user_data_size(); + + TAU_LOGD("user_data size 0x%x \n", user_data_size); +} + + +void test_hal_flash_get_user_region_test(void) +{ + uint8_t user_data[32]; + uint32_t user_address = 0; //需要读取数据的位置 + uint32_t user_data_size = 0; + + TAU_LOGD("test get data addr\n"); + //读取user data 0地址 + user_address = 0; + + fls_ops_cfg->flash_block = user_address / DATA_BLOCK_SIZE; + fls_ops_cfg->flash_page = (user_address % DATA_BLOCK_SIZE) / DATA_PAGE_SIZE; + fls_ops_cfg->page_offset_addr = user_address % DATA_PAGE_SIZE; + fls_ops_cfg->data_size = 16; + fls_ops_cfg->user_data = user_data; + hal_flash_user_region_ops(FLASH_USERDATA_READ, fls_ops_cfg); + for (uint8_t i = 0; i < 2; i++) + { + TAU_LOGD("user_data[%d]=0x%x ", i, user_data[i]); + } + + //读取user data 0x6000地址 + user_address = 0x6000; + + fls_ops_cfg->flash_block = user_address / DATA_BLOCK_SIZE; + fls_ops_cfg->flash_page = (user_address % DATA_BLOCK_SIZE) / DATA_PAGE_SIZE; + fls_ops_cfg->page_offset_addr = user_address % DATA_PAGE_SIZE; + fls_ops_cfg->data_size = 16; + fls_ops_cfg->user_data = user_data; + hal_flash_user_region_ops(FLASH_USERDATA_READ, fls_ops_cfg); + for (uint8_t i = 0; i < 2; i++) + { + TAU_LOGD("user_data[%d]=0x%x ", i, user_data[i]); + } +} + + +/** +* @brief 获取user_data的绝对起始地址 的接口测试 +* @param 无 +* @retval bool 无 +*/ + +void demo_hal_flash(void) +{ + uint8_t case_sel = 2; + + switch (case_sel) + { + case 1: + test_hal_flash_get_public_region_test(); + break; + + case 2: + test_hal_flash_get_user_region_test(); + break; + + case 3: + test_flash_uid_read(); + break; + + case 4: + get_user_data_size(); + break; + + case 5: + //测试共享flash接口,需要外接SPI主机测试 + TAU_LOGI("test TMON \n"); + hal_flash_share_mode(true); + break; + + default: + break; + } + + +} + + + +#endif + diff --git a/src/app/module_demo/demo_hal_flash.h b/src/app/module_demo/demo_hal_flash.h new file mode 100644 index 0000000..849440b --- /dev/null +++ b/src/app/module_demo/demo_hal_flash.h @@ -0,0 +1,35 @@ +/******************************************************************************* +* Copyright (C) 2021-2022, All Rights Reserved. +* +* File: test_hal_flash.h +* Description: hal_flash测试用例头文件 +* Version: V0.1 +* Date: 2023-07-17 +* Author: Kevin + *******************************************************************************/ +#ifndef __DEMO_HAL_FLASH_H__ +#define __DEMO_HAL_FLASH_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +void demo_hal_flash(void); + +#endif /* __TEST_HAL_FLASH_H__ */ + diff --git a/src/app/module_demo/demo_hal_gpio.c b/src/app/module_demo/demo_hal_gpio.c new file mode 100644 index 0000000..208b4d2 --- /dev/null +++ b/src/app/module_demo/demo_hal_gpio.c @@ -0,0 +1,268 @@ +/******************************************************************************* +* +* +* File: demo_gpio.c +* Description： GPIO测试用例源文件 +* Version： V0.1 +* Date： 2023-07-27 +* Author： kevin + *******************************************************************************/ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "hal_gpio.h" +#include "tau_delay.h" +#include "tau_log.h" +#include "test_cfg_global.h" + +#if _DEMO_GPIO_EN +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "gpio-log" + +//output +#define GPIO_OUT_TEST 1 +#define GPIO_OUT_IN_CONNECT 0 + +//input +#define GPIO_IN_INT_SINGLE 0 +//IO mode init +#define GPIO_MODE_INIT 0 + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ +static bool s_gpio_callback_flag = false; +static sys_cfg_trigger_e s_gpio_trig = DETECT_HIGH_LVL; +static io_pad_e s_gpio_demo_pad1 = IO_PAD_AP_TPRSTN; +static io_pad_e s_gpio_demo_pad2 = IO_PAD_AP_PWMEN; + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ + +/************************************************************************** +* @name : demo_gpio_callback +* @brief : 测试回调函数 +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +static void demo_gpio_callback(void *data) +{ + gpio_int_e type = *(gpio_int_e *)data; + gpio_int_e int_type = hal_gpio_get_int_type(s_gpio_demo_pad1); + + TAU_LOGI("demo_gpio_callback type:%d, int_type:%d, s_gpio_trig:%d\r\n", type, int_type, s_gpio_trig); + + hal_gpio_ctrl_eint(s_gpio_demo_pad1, DISABLE); + + if (DETECT_HIGH_LVL == s_gpio_trig) + { + hal_gpio_set_output_data(s_gpio_demo_pad2, IO_LVL_LOW); + } + else if (DETECT_LOW_LVL == s_gpio_trig) + { + hal_gpio_set_output_data(s_gpio_demo_pad2, IO_LVL_HIGH); + } + + switch (s_gpio_trig) + { + case DETECT_HIGH_LVL: + s_gpio_trig = DETECT_LOW_LVL; + break; + + case DETECT_LOW_LVL: + s_gpio_trig = DETECT_RISING_EDGE; + break; + + case DETECT_RISING_EDGE: + s_gpio_trig = DETECT_FALLING_EDGE; + break; + + default: + return; + } + + s_gpio_callback_flag = true; +} + +/************************************************************************** +* @name : demo_gpio_int +* @brief : gpio测试中断通用配置 +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +static void demo_gpio_int(io_pad_e pad, sys_cfg_trigger_e trig) +{ + /*1.关闭中断*/ + hal_gpio_ctrl_eint(pad, DISABLE); + + /*2.中断初始化*/ + hal_gpio_init_eint(pad, trig); + + /*3.注册回调*/ + hal_gpio_reg_eint_cb(pad, demo_gpio_callback); + + /*4.使能中断*/ + hal_gpio_ctrl_eint(pad, ENABLE); +} + +/************************************************************************** +* @name : demo_gpio_out_case +* @brief : gpio output功能测试 +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +static void demo_gpio_out_case(void) +{ + gpio_level_e flag = IO_LVL_LOW; + + TAU_LOGI("demo_gpio_out_case\r\n"); + + hal_gpio_init_output(s_gpio_demo_pad1, flag); + while (1) + { + delayMs(10); + flag = (flag == IO_LVL_LOW) ? IO_LVL_HIGH : IO_LVL_LOW; + hal_gpio_set_output_data(s_gpio_demo_pad1, flag); + } +} + +/************************************************************************** +* @name : demo_gpio_in_case +* @brief : gpio input功能测试 +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +static void demo_gpio_in_case(void) +{ + gpio_level_e flag = IO_LVL_LOW; + + TAU_LOGI("demo_gpio_in_case\r\n"); + + hal_gpio_init_input(s_gpio_demo_pad1); + hal_gpio_init_output(s_gpio_demo_pad2, flag); + while (1) + { + delayMs(10); + flag = (flag == IO_LVL_LOW) ? IO_LVL_HIGH : IO_LVL_LOW; + hal_gpio_set_output_data(s_gpio_demo_pad2, flag); + } +} + +/************************************************************************** +* @name : demo_gpio_int_single +* @brief : gpio input配置单个中断 +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +static void demo_gpio_int_single(void) +{ + sys_cfg_trigger_e trig = s_gpio_trig; + + TAU_LOGI("demo_gpio_int_single trig:%d\r\n", trig); + + if (DETECT_HIGH_LVL == s_gpio_trig || DETECT_RISING_EDGE == s_gpio_trig) + { + hal_gpio_init_output(s_gpio_demo_pad2, IO_LVL_LOW); + } + else if (DETECT_LOW_LVL == s_gpio_trig || DETECT_FALLING_EDGE == s_gpio_trig) + { + hal_gpio_init_output(s_gpio_demo_pad2, IO_LVL_HIGH); + } + + demo_gpio_int(s_gpio_demo_pad1, trig); + + if (DETECT_HIGH_LVL == s_gpio_trig || DETECT_RISING_EDGE == s_gpio_trig) + { + delayMs(100); + hal_gpio_set_output_data(s_gpio_demo_pad2, IO_LVL_HIGH); + } + else if (DETECT_LOW_LVL == s_gpio_trig || DETECT_FALLING_EDGE == s_gpio_trig) + { + delayMs(100); + hal_gpio_set_output_data(s_gpio_demo_pad2, IO_LVL_LOW); + } +} + +/** +* @brief GPIO初始化配置,根据实际原理图提前配置IO功能以及状态,默认功能可不配置 +* TP相关I2C/SPI 在tp_transfer.c +* @param none +* @retval none +*/ +static void demo_gpio_init(void) +{ + io_pad_attr_t attrs[] = + { + //1.配置成GPIO 输出 + {IO_PIN_8, PIN8_MODE_GPIO7, IO_IOE_OUTPUT, IO_LVL_LOW}, /* PIN_8(TD_RSTN), GPIO,输出,低电平 */ + {IO_PIN_17, PIN17_MODE_GPIO8, IO_IOE_OUTPUT, IO_LVL_LOW}, /* PIN_17(PWMEN), GPIO,输出,低电平 */ + {IO_PIN_16, PIN16_MODE_GPIO2, IO_IOE_OUTPUT, IO_LVL_LOW}, /* PIN_16(AP_INT),GPIO,输出,低电平 */ + + //2.配置成GPIO 输入 + {IO_PIN_29, PIN29_MODE_GPIO3, IO_IOE_INPUT, IO_LVL_NONE}, /* PIN_29(AP_TE), GPIO,输入 */ + + //3.配置UART TX + {IO_PIN_2, PIN2_MODE_UART0_TX, IO_IOE_NONE, IO_LVL_NONE}, /* PIN_2(UART0_TX), UART,TX */ + + //4.配置I2C + {IO_PIN_5, PIN5_MODE_I2C1_SCL, IO_IOE_NONE, IO_LVL_NONE}, /* PIN_5(TD_SPIM_CLK), I2C,SCL */ + {IO_PIN_6, PIN6_MODE_I2C1_SDA, IO_IOE_NONE, IO_LVL_NONE}, /* PIN_6(TD_SPIM_CSN), I2C,SDA */ + + //5.配置SPIS + {IO_PIN_30, PIN30_MODE_SPIS_MISO, IO_IOE_NONE, IO_LVL_NONE}, /* PIN_30(AP_SPIS_MISO), SPIS,MISO */ + {IO_PIN_31, PIN31_MODE_SPIS_CSN, IO_IOE_NONE, IO_LVL_NONE}, /* PIN_31(AP_SPIS_CSN), SPIS,CSN */ + {IO_PIN_32, PIN32_MODE_SPIS_SCLK, IO_IOE_NONE, IO_LVL_NONE}, /* PIN_32(AP_SPIS_CLK), SPIS,CLK */ + {IO_PIN_33, PIN33_MODE_SPIS_MOSI, IO_IOE_NONE, IO_LVL_NONE} /* PIN_33(AP_SPIS_MOSI), SPIS,MOSI */ + }; + uint8_t size = sizeof(attrs) / sizeof(io_pad_attr_t); + hal_gpio_config_pad(attrs, size); +} + + +/************************************************************************** +* @name : demo_gpio_case +* @brief : 测试用例 +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +void demo_gpio_case(void) +{ + s_gpio_callback_flag = true; + +#if GPIO_IN_INT_SINGLE + while (1) + { + if (s_gpio_callback_flag) + { + s_gpio_callback_flag = false; + demo_gpio_int_single(); + } + } +#elif GPIO_OUT_TEST + demo_gpio_out_case(); +#elif GPIO_OUT_IN_CONNECT + demo_gpio_in_case(); +#elif GPIO_MODE_INIT + demo_gpio_init(); +#endif +} + +#endif + diff --git a/src/app/module_demo/demo_hal_gpio.h b/src/app/module_demo/demo_hal_gpio.h new file mode 100644 index 0000000..c961cd8 --- /dev/null +++ b/src/app/module_demo/demo_hal_gpio.h @@ -0,0 +1,35 @@ +/******************************************************************************* +* +* +* File: demo_gpio.h +* Description: GPIO测试用例头文件 +* Version: V0.1 +* Date: 2023-07-27 +* Author: kevin + *******************************************************************************/ +#ifndef __DEMO_GPIO_H__ +#define __DEMO_GPIO_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +void demo_gpio_case(void); + +#endif /* __DEMO_GPIO_H__ */ + diff --git a/src/app/module_demo/demo_hal_i2c.c b/src/app/module_demo/demo_hal_i2c.c new file mode 100644 index 0000000..356b484 --- /dev/null +++ b/src/app/module_demo/demo_hal_i2c.c @@ -0,0 +1,412 @@ +/******************************************************************************* +* Copyright (C) 2020-2023, tau Systems (R),All Rights Reserved. +* +* File: demo_hal_i2ci.c +* Description： i2c demo code +* Version： V0.1 +* Date： 2023-07-27 +* Author： swx + *******************************************************************************/ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "hal_i2c_master.h" +#include "hal_i2c_slave.h" +#include "demo_hal_i2c.h" +#include "hal_gpio.h" +#include "tau_log.h" +#include "tau_delay.h" + +#if _MODULE_DEMO_I2C_EN +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "demo_hal_i2c" +#define BUFFER_SIZE 10 // 以10个数据为例 + +#define CHECK_TRANS_RESULT(src, dst, size) \ + for(uint32_t check_num = 0; check_num < size; check_num ++) \ + {\ + if(src[check_num] != dst[check_num])\ + {\ + TAU_LOGD("src[%d] = %x, dst[%d] = %x , error!!\n",check_num,src[check_num],check_num,dst[check_num]);\ + return false;\ + }\ + }\ + +/******************************************************************************* +* 3.Global function and Global variable declarations +*******************************************************************************/ +static uint8_t i2cm_read_buffer[BUFFER_SIZE]; +static uint8_t i2cs_read_buffer[BUFFER_SIZE]; +static uint8_t i2cs_write_buffer[BUFFER_SIZE]; + + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief i2c master的IO初始化 +* @param none +* @retval none +*/ +static void i2cm_io_init(void) +{ + io_pad_attr_t attrs[] = + { + {IO_PAD_TD_SPIM_CLK, PIN5_MODE_I2C1_SCL, IO_IOE_NONE, IO_LVL_HIGH}, + {IO_PAD_TD_SPIM_CSN, PIN6_MODE_I2C1_SDA, IO_IOE_NONE, IO_LVL_HIGH} + }; + uint8_t size = sizeof(attrs) / sizeof(io_pad_attr_t); + hal_gpio_config_pad(attrs, size); +} + +/** +* @brief i2c slave的IO初始化 +* @param none +* @retval none +*/ +static void i2cs_io_init(void) +{ + io_pad_attr_t attrs[] = + { + {IO_PAD_AP_SPIS_CLK, PIN32_MODE_I2C02_SCL, IO_IOE_NONE, IO_LVL_HIGH}, + {IO_PAD_AP_SPIS_CSN, PIN31_MODE_I2C02_SDA, IO_IOE_NONE, IO_LVL_HIGH} + }; + uint8_t size = sizeof(attrs) / sizeof(io_pad_attr_t); + hal_gpio_config_pad(attrs, size); +} + +/** +* @brief i2c slave的中断回调服务函数 +* @param index: I2Cx index +* @param int_status: 中断事件 +* @param recieve_num： 接收到的packet数 +* @retval none +*/ +static void i2cs_callback(i2c_index_e index, hal_i2cs_event_e int_status, size_t recieve_num) +{ + /* 收到READ_REQ中断 */ + if (int_status == I2CS_EVENT_READ) + { + /* 更新I2CS的txbuffer，将i2cs_write_buffer的数据发送给主机 */ + hal_i2cs_update_tx_buffer(index, i2cs_write_buffer, BUFFER_SIZE, false); + } + /* 收到stop中断 */ + else if (int_status == I2CS_EVENT_STOP) + { + if (recieve_num > 0) + { + /* 将读到的值写到i2cs_write_buffer中 */ + for (int i = 0; i < recieve_num; i++) + i2cs_write_buffer[i] = i2cs_read_buffer[i]; + } + /* 更新I2CS的rxbuffer */ + hal_i2cs_update_rx_buffer(index, i2cs_read_buffer, BUFFER_SIZE); + } +} + +/** +* @brief i2c master初始化 +* @param index: I2Cx index +* @param addr: 从机地址 +* @param addr_bits: 从机地址位数 +* @param speed: 主机速率设置 +* @retval none +*/ +void i2cm_init(i2c_index_e index, uint16_t addr, uint8_t addr_bits, uint32_t speed) +{ + /* I2CS的IO初始化 */ + i2cm_io_init(); + + /* I2CM初始化 */ + hal_i2cm_init(index, addr, addr_bits, speed); +} + +/** +* @brief i2c slave初始化 +* @param index: I2Cx index +* @param addr: 从机自身地址 +* @param addr_bits: 从机地址位数 +* @retval none +*/ +void i2cs_init(i2c_index_e index, uint16_t addr, uint8_t addr_bits) +{ + /* I2CS的IO初始化 */ + i2cs_io_init(); + + /* I2CS的初始化 */ + hal_i2cs_init(index, addr, addr_bits); + + /* I2CS注册回调函函数 */ + hal_i2cs_register_callback(index, i2cs_callback); + + /* I2CS设置初始读写buffer */ + hal_i2cs_update_rx_buffer(index, i2cs_read_buffer, BUFFER_SIZE); + hal_i2cs_update_tx_buffer(index, i2cs_write_buffer, BUFFER_SIZE, false); + + /* I2CS启动 */ + hal_i2cs_start(index); +} + +/** +* @brief i2c master去初始化 +* @param index: I2Cx index +* @retval none +*/ +void i2cm_deinit(i2c_index_e index) +{ + hal_i2cm_deinit(index); +} + +/** +* @brief i2c slave去初始化 +* @param index: I2Cx index +* @retval none +*/ +void i2cs_deinit(i2c_index_e index) +{ + hal_i2cs_stop(index); + hal_i2cs_deinit(index); +} + +/** +* @brief i2c case buffer初始化 +* @param none +* @retval none +*/ +static void i2c_case_buffer_init(void) +{ + TAU_LOGD("i2c_case_buffer_init\n"); + /* init buffer */ + uint8_t i = 0 ; + for (i = 0; i < BUFFER_SIZE; i ++) + { + i2cm_read_buffer[i] = 0; + i2cs_read_buffer[i] = 0; + i2cs_write_buffer[i] = 0; + } +} + +/** +* @brief 芯片I2CM与I2CS对接,验证I2CM用CPU方式传输数据的正确性 +* @param +* @retval bool true/false +*/ +static bool hal_i2c_cpu_transfer_case(void) +{ + uint8_t write_buffer[10] = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19}; + uint8_t addr_bit = 7; + uint32_t speed = 400000; + uint16_t addr = 0x50; + + /* I2CM初始化，I2C1+目标地址0x50+7位地址+400k传输速率 */ + i2cm_init(I2C_INDEX_1, addr, addr_bit, speed); + + /* I2CS初始化，I2C0+本机地址0x50+7位地址 */ + i2cs_init(I2C_INDEX_0, addr, addr_bit); + + /* buffer初始化 */ + i2c_case_buffer_init(); + + /* I2CM写write_buffer数据到0x50地址的从机 */ + if (hal_i2cm_write(I2C_INDEX_1, write_buffer, BUFFER_SIZE) != true) + { + TAU_LOGD("I2CM CPU write data fail!\n"); + return false; + } + TAU_LOGD("tx: %x %x %x %x %x %x %x %x %x %x\n", write_buffer[0], write_buffer[1], write_buffer[2], \ + write_buffer[3], write_buffer[4], write_buffer[5], write_buffer[6], write_buffer[7], write_buffer[8], \ + write_buffer[9]); + + /* I2CM向地址为0x50的从机读取BUFFER_SIZE个数据，此case中，寄存器addr和size为0，可自行添加 */ + if (hal_i2cm_read(I2C_INDEX_1, 0, 0, i2cm_read_buffer, BUFFER_SIZE) != true) + { + TAU_LOGD("I2CM CPU read data fail!\n"); + return false; + } + TAU_LOGD("rx: %x %x %x %x %x %x %x %x %x %x\n", i2cm_read_buffer[0], i2cm_read_buffer[1], \ + i2cm_read_buffer[2], i2cm_read_buffer[3], i2cm_read_buffer[4], i2cm_read_buffer[5], \ + i2cm_read_buffer[6], i2cm_read_buffer[7], i2cm_read_buffer[8], i2cm_read_buffer[9]); + + /* 检查传输结果，I2CM发出去的数据是否与接收到的数据一致 */ + CHECK_TRANS_RESULT(write_buffer, i2cm_read_buffer, BUFFER_SIZE); + + /* I2CM && I2CS去初始化 */ + i2cs_deinit(I2C_INDEX_0); + i2cm_deinit(I2C_INDEX_1); + TAU_LOGD("hal_i2c_cpu_transfer_case done!\n"); + return true; +} + + +/** +* @brief 芯片I2CM与I2CS对接,验证I2CM用DMA方式传输数据的正确性 +* @param +* @retval bool true/false +*/ +static bool hal_i2c_dma_transfer_case(void) +{ + uint8_t write_buffer[10] = {0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29}; + uint8_t addr_bit = 7; + uint32_t speed = 400000; + uint16_t addr = 0x50; + + /* I2CM初始化，I2C1+目标地址0x50+7位地址+400k传输速率 */ + i2cm_init(I2C_INDEX_1, addr, addr_bit, speed); + + /* I2CS初始化，I2C0+本机地址0x50+7位地址 */ + i2cs_init(I2C_INDEX_0, addr, addr_bit); + + /* buffer初始化 */ + i2c_case_buffer_init(); + + /* I2CM写write_buffer数据到0x50地址的从机 */ + hal_i2cm_dma_write(I2C_INDEX_1, write_buffer, BUFFER_SIZE); + + /* 等待I2CM传输完成 */ + while (!hal_i2cm_get_transfer_complete(I2C_INDEX_1)); + TAU_LOGD("tx: %x %x %x %x %x %x %x %x %x %x\n", write_buffer[0], write_buffer[1], write_buffer[2], \ + write_buffer[3], write_buffer[4], write_buffer[5], write_buffer[6], write_buffer[7], write_buffer[8], \ + write_buffer[9]); + + /* I2CM向地址为0x50的从机读取BUFFER_SIZE个数据，此case中，寄存器addr和size为0，可自行添加 */ + hal_i2cm_dma_read(I2C_INDEX_1, 0, 0, i2cm_read_buffer, BUFFER_SIZE); + + /* 等待I2CM传输完成 */ + while (!hal_i2cm_get_transfer_complete(I2C_INDEX_1)); + TAU_LOGD("rx: %x %x %x %x %x %x %x %x %x %x\n", i2cm_read_buffer[0], i2cm_read_buffer[1], \ + i2cm_read_buffer[2], i2cm_read_buffer[3], i2cm_read_buffer[4], i2cm_read_buffer[5], \ + i2cm_read_buffer[6], i2cm_read_buffer[7], i2cm_read_buffer[8], i2cm_read_buffer[9]); + + /* 检查传输结果，I2CM发出去的数据是否与接收到的数据一致 */ + CHECK_TRANS_RESULT(write_buffer, i2cm_read_buffer, BUFFER_SIZE); + + /* I2CM && I2CS去初始化 */ + i2cs_deinit(I2C_INDEX_0); + i2cm_deinit(I2C_INDEX_1); + TAU_LOGD("hal_i2c_dma_transfer_case done!\n"); + return true; +} + +/** +* @brief 芯片I2CM与I2CS对接,验证双slave通信的正确性 +* @param +* @retval bool true/false +*/ +static bool hal_i2c_double_slave_case(void) +{ + uint16_t i2cs1_addr = 0x50; + uint8_t i2cs1_addrbit = 7; + uint16_t i2cs2_addr = 0x120; + uint8_t i2cs2_addrbit = 10; + uint32_t speed = 400000; + uint8_t write_buffer1[10] = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19}; + uint8_t write_buffer2[10] = {0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29}; + + /* I2CM初始化，I2C1+目标地址0x50+7位地址+400k传输速率 */ + i2cm_init(I2C_INDEX_1, i2cs1_addr, i2cs1_addrbit, speed); + + /* I2CS初始化，I2C0+本机地址0x50+7位地址 */ + i2cs_init(I2C_INDEX_0, i2cs1_addr, i2cs1_addrbit); + + /* I2CS初始化，I2C2+本机地址0x120+10位地址 */ + i2cs_init(I2C_INDEX_2, i2cs2_addr, i2cs2_addrbit); + + /* I2CM写write_buffer1数据到0x50地址的从机 */ + hal_i2cm_dma_write(I2C_INDEX_1, write_buffer1, BUFFER_SIZE); + + /* 等待I2CM传输完成 */ + while (!hal_i2cm_get_transfer_complete(I2C_INDEX_1)); + TAU_LOGD("tx: %x %x %x %x %x %x %x %x %x %x\n", write_buffer1[0], write_buffer1[1], write_buffer1[2], \ + write_buffer1[3], write_buffer1[4], write_buffer1[5], write_buffer1[6], write_buffer1[7], write_buffer1[8], \ + write_buffer1[9]); + + /* I2CM向地址为0x50的从机读取BUFFER_SIZE个数据，此case中，寄存器addr和size为0，可自行添加 */ + hal_i2cm_dma_read(I2C_INDEX_1, 0, 0, i2cm_read_buffer, BUFFER_SIZE); + + /* 等待I2CM传输完成 */ + while (!hal_i2cm_get_transfer_complete(I2C_INDEX_1)); + TAU_LOGD("rx: %x %x %x %x %x %x %x %x %x %x\n", i2cm_read_buffer[0], i2cm_read_buffer[1], \ + i2cm_read_buffer[2], i2cm_read_buffer[3], i2cm_read_buffer[4], i2cm_read_buffer[5], \ + i2cm_read_buffer[6], i2cm_read_buffer[7], i2cm_read_buffer[8], i2cm_read_buffer[9]); + + /* 检查传输结果，I2CM发出去的数据是否与接收到的数据一致 */ + CHECK_TRANS_RESULT(write_buffer1, i2cm_read_buffer, BUFFER_SIZE); + + /* 修改I2CM的目标从机地址为10位地址的0x120 */ + hal_i2cm_set_slave_addr(I2C_INDEX_1, i2cs2_addr, i2cs2_addrbit); + + /* I2CM写write_buffer2数据到0x120地址的从机 */ + hal_i2cm_dma_write(I2C_INDEX_1, write_buffer2, BUFFER_SIZE); + + /* 等待I2CM传输完成 */ + while (!hal_i2cm_get_transfer_complete(I2C_INDEX_1)); + TAU_LOGD("tx: %x %x %x %x %x %x %x %x %x %x\n", write_buffer2[0], write_buffer2[1], write_buffer2[2], \ + write_buffer2[3], write_buffer2[4], write_buffer2[5], write_buffer2[6], write_buffer2[7], write_buffer2[8], \ + write_buffer2[9]); + + /* I2CM向地址为0x120的从机读取BUFFER_SIZE个数据，此case中，寄存器addr和size为0，可自行添加 */ + hal_i2cm_dma_read(I2C_INDEX_1, 0, 0, i2cm_read_buffer, BUFFER_SIZE); + + /* 等待I2CM传输完成 */ + while (!hal_i2cm_get_transfer_complete(I2C_INDEX_1)); + TAU_LOGD("rx: %x %x %x %x %x %x %x %x %x %x\n", i2cm_read_buffer[0], i2cm_read_buffer[1], \ + i2cm_read_buffer[2], i2cm_read_buffer[3], i2cm_read_buffer[4], i2cm_read_buffer[5], \ + i2cm_read_buffer[6], i2cm_read_buffer[7], i2cm_read_buffer[8], i2cm_read_buffer[9]); + + /* 检查传输结果，I2CM发出去的数据是否与接收到的数据一致 */ + CHECK_TRANS_RESULT(write_buffer2, i2cm_read_buffer, BUFFER_SIZE); + + /* I2CM && I2CS去初始化 */ + i2cm_deinit(I2C_INDEX_1); + i2cs_deinit(I2C_INDEX_0); + i2cs_deinit(I2C_INDEX_2); + TAU_LOGD("hal_i2c_double_slave_case done!\n"); + return true; +} + +/** +* @brief i2c demo case +* @param none +* @retval none +*/ +void demo_hal_i2c(void) +{ + /* I2C DMA传输case */ + if (!hal_i2c_dma_transfer_case()) + { + i2cs_deinit(I2C_INDEX_0); + i2cm_deinit(I2C_INDEX_1); + TAU_LOGD("hal_i2c_dma_transfer_case fail!\n"); + } + + /* 双slave传输case */ + if (!hal_i2c_double_slave_case()) + { + i2cm_deinit(I2C_INDEX_1); + i2cs_deinit(I2C_INDEX_0); + i2cs_deinit(I2C_INDEX_2); + TAU_LOGD("hal_i2c_double_slave_case fail!\n"); + } + + /* I2C CPU传输case */ + if (!hal_i2c_cpu_transfer_case()) + { + i2cs_deinit(I2C_INDEX_0); + i2cm_deinit(I2C_INDEX_1); + TAU_LOGD("hal_i2c_cpu_transfer_case fail!\n"); + } + + TAU_LOGD("i2c case done\n"); +} +#endif + diff --git a/src/app/module_demo/demo_hal_i2c.h b/src/app/module_demo/demo_hal_i2c.h new file mode 100644 index 0000000..4ecb600 --- /dev/null +++ b/src/app/module_demo/demo_hal_i2c.h @@ -0,0 +1,35 @@ +/******************************************************************************* +* Copyright (C) 2020-2023, tau Systems (R),All Rights Reserved. +* +* File: demo_hal_i2c.h +* Description: demo i2c 头文件 +* Version: V0.1 +* Date： 2023-07-27 +* Author: swx +*******************************************************************************/ +#ifndef __DEMO_HAL_I2C_H__ +#define __DEMO_HAL_I2C_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "test_cfg_global.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +void demo_hal_i2c(void); + +#endif /* __DEMO_HAL_I2C_H__ */ diff --git a/src/app/module_demo/demo_hal_pwm.c b/src/app/module_demo/demo_hal_pwm.c new file mode 100644 index 0000000..617a92e --- /dev/null +++ b/src/app/module_demo/demo_hal_pwm.c @@ -0,0 +1,125 @@ +/******************************************************************************* +* +* +* File: demo_hal_pwm.c +* Description： pwm demo code +* Version： V0.1 +* Date： 2023-07-27 +* Author： jaya + *******************************************************************************/ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "stdarg.h" +#include "stdlib.h" +#include "stdio.h" +#include "test_cfg_global.h" +#include "hal_pwm.h" +#include "hal_gpio.h" +#include "tau_log.h" +#include "tau_delay.h" +#include "demo_hal_pwm.h" + +#if _MODULE_DEMO_PWM_EN +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "demo_hal_pwm" + +/******************************************************************************* +* 3.Global function and Global variable declarations +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief 数字PWM输出demo +* @param +* @retval bool true/false +*/ +bool demo_digital_pwm_output(void) +{ + /* GPIO 初始化,配置PIN15输出PWM, PWM可配置从PIN2/PIN13/PIN15/PIN17/PIN36输出 */ + hal_gpio_set_mode(IO_PIN_15, PIN15_MODE_PWMO); + //hal_gpio_set_mode(IO_PIN_17, PIN17_MODE_PWMO); + + /* PWM 初始化 ，配置为30K 255阶 */ + if (hal_pwm_init(30000, 255)) + { + /* PWM enable */ + hal_pwm_enable(true); + uint8_t i = 0; + while (i != 255) + { + /* PWM 配置占空比, 从1/255开始到100%*/ + hal_pwm_set_duty(i); + delayMs(20); + i++; + } + } + + /* PWM disable */ + hal_pwm_enable(false); + /* PWM deinit */ + hal_pwm_deinit(); + TAU_LOGD("demo_digital_pwm_output done\n"); + return true; +} + +/** +* @brief 模拟PWM输出demo +* @param +* @retval bool true/false +*/ +bool demo_analog_pwm_output_with_vcc(void) +{ + /* 模拟PWM,可选择不从数字IO输出PWM,也可以选择从数字IO输出 */ + hal_gpio_set_mode(IO_PIN_15, PIN15_MODE_PWMO); + //hal_gpio_set_mode(IO_PIN_17, PIN17_MODE_PWMO); + + /* PWM 初始化 ，配置为30K 255阶 */ + if (hal_pwm_init(30000, 255)) + { + /* PWM enable */ + hal_pwm_enable(true); + /* ELVCC 接入3-6V的电源,PWM 配置从ELVCC调试后的电源 */ + hal_pwm_set_elvcc_output(true); + + uint8_t i = 0; + while (i != 255) + { + hal_pwm_set_duty(i); + delayMs(20); + i++; + } + } + + /* PWM disable */ + hal_pwm_enable(false); + /* PWM deinit */ + hal_pwm_deinit(); + TAU_LOGD("demo_digital_pwm_output done\n"); + return true; +} + +/** +* @brief pwm demo case +* @param none +* @retval none +*/ +void demo_hal_pwm(void) +{ + TAU_LOGD("pwm dmeo \n"); + //demo_digital_pwm_output(); + demo_analog_pwm_output_with_vcc(); +} +#endif diff --git a/src/app/module_demo/demo_hal_pwm.h b/src/app/module_demo/demo_hal_pwm.h new file mode 100644 index 0000000..c9e9770 --- /dev/null +++ b/src/app/module_demo/demo_hal_pwm.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* Copyright (C) 2020-2023, tau Systems (R),All Rights Reserved. +* +* File: demo_hal_pwm.h +* Description: demo pwm 头文件 +* Version: V0.1 +* Date： 2023-07-27 +* Author: jaya + *******************************************************************************/ +#ifndef __DEMO_HAL_PWM_H__ +#define __DEMO_HAL_PWM_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "test_cfg_global.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +void demo_hal_pwm(void); + +#endif /* __DEMO_HAL_PWM_H__ */ + diff --git a/src/app/module_demo/demo_hal_pwr.c b/src/app/module_demo/demo_hal_pwr.c new file mode 100644 index 0000000..1042343 --- /dev/null +++ b/src/app/module_demo/demo_hal_pwr.c @@ -0,0 +1,218 @@ +/******************************************************************************* +* +* +* File: demo_hal_pwr.c +* Description： pwr demo code +* Version： V0.1 +* Date： 2023-07-27 +* Author： jaya + *******************************************************************************/ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "stdarg.h" +#include "stdlib.h" +#include "stdio.h" +#include "test_cfg_global.h" +#include "hal_pwr.h" +#include "hal_gpio.h" +#include "tau_log.h" +#include "tau_delay.h" +#include "demo_hal_pwr.h" + +#if _MODULE_DEMO_PWR_EN +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "demo_hal_pwr" + +#define MAIN_POWER_SELECT PWR_SEL_VCC /* 主供电电源选择 */ +#define SLEEP_MODE_POWER PWR_SLEEP_IN_TP18 /* 息屏电源选择 */ + +/******************************************************************************* +* 3.Global function and Global variable declarations +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +static bool sg_system_resume = false; + +static void ap_rstn_pull_high_cb(void *data) +{ + TAU_LOGD("AP RSTN !\n"); + /* system resume begin */ + sg_system_resume = true; + /* 关闭AP reset检查 */ + hal_gpio_set_ap_reset_int(DISABLE, NULL, DETECT_HIGH_LVL); +} + +/** +* @brief normal sleep mode demo +* @param +* @retval bool true/false +*/ +static bool demo_normal_sleep_mode() +{ + /* 主电源供电选择 */ + hal_pwr_set_main_power(MAIN_POWER_SELECT); + + if (MAIN_POWER_SELECT == PWR_SEL_VCC) + { + while (hal_pwr_get_vcc_power_ready() == false); + } + + /* system 正常启动 */ + + /* sustem suspend */ + /* 关闭外设/图像通路 */ + + /* 息屏电源供电选择 */ + hal_pwr_set_sleep_mode_power(SLEEP_MODE_POWER); + + /* enter deep sleep mode */ + TAU_LOGD("enter stop mode now\n"); + + /* normal sleep mode, MCU可以正常工作 */ + hal_gpio_set_ap_reset_int(ENABLE, ap_rstn_pull_high_cb, DETECT_RISING_EDGE); + + hal_pwr_enter_normal_sleep_mode(); + while (1) + { + /* normal sleep mode 下外设模块正常,打印正常,SWD通讯正常 */ + TAU_LOGD("wait ap rstn\n"); + if (sg_system_resume) + { + break; + } + delayMs(1000); + } + + /* 退出sleep mode */ + hal_pwr_exit_sleep_mode(); + /* system resume */ + TAU_LOGD("system resum\n"); + return true; +} + +/** +* @brief stop sleep mode demo +* @param +* @retval bool true/false +*/ +static bool demo_stop_sleep_mode() +{ + /* 主电源供电选择 */ + hal_pwr_set_main_power(MAIN_POWER_SELECT); + + if (MAIN_POWER_SELECT == PWR_SEL_VCC) + { + while (hal_pwr_get_vcc_power_ready() == false); + } + + /* system 正常启动 */ + + /* sustem suspend */ + /* 关闭外设/图像通路 */ + + /* 息屏电源供电选择 */ + hal_pwr_set_sleep_mode_power(SLEEP_MODE_POWER); + + /* enter deep sleep mode */ + while (1) + { + + TAU_LOGD("enter stop mode now\n"); + + /* 等待打印完成 */ + delayMs(200); /* 实际使用不需要延时 */ + + /* 配置唤醒AP RSTN 、SPIS CS、TD INT 唤醒*/ + hal_pwr_set_stop_sleep_wakeup_pin(IO_PAD_AP_RSTN, WUP_RISING_EDGE); + hal_pwr_set_stop_sleep_wakeup_pin(IO_PAD_AP_SPIS_CSN, WUP_FALLING_EDGE); + hal_pwr_set_stop_sleep_wakeup_pin(IO_PAD_TD_INT, WUP_FALLING_EDGE); + delayMs(1000); /* 实际使用不需要延时 */ + /* 进入stop sleep mode, MCU停止运行,SWD无法通讯 */ + io_pad_e wakeup_io = hal_pwr_enter_stop_sleep_mode(); + + TAU_LOGD("stop sleep mode wake up by io %d\n", wakeup_io); + + if (wakeup_io == IO_PAD_AP_RSTN) + { + TAU_LOGD("AP RSTN reset, system resume\n"); + break; + } + else + { + TAU_LOGD("Touch process\n"); + /* 处理touchu 事件 处理完成后继续进入sleep mode*/ + } + } + + /* 退出sleep mode */ + hal_pwr_exit_sleep_mode(); + /* system resume */ + TAU_LOGD("system resum\n"); + return true; +} + +/** +* @brief deep sleep mode demo +* @param +* @retval bool true/false +*/ +static bool demo_deep_sleep_mode() +{ + pwr_reset_flag_e reset_flag = hal_pwr_get_reset_flag(); + TAU_LOGD("wakeup flag %d\n", reset_flag); + if (reset_flag == RF_TDINT_WAKEUP) + { + /* TD_INT reset, 处理触摸事件, 唤醒AP 等待AP RSTN*/ + TAU_LOGD("TD_INT reset\n"); + } + /* 主电源供电选择 */ + hal_pwr_set_main_power(MAIN_POWER_SELECT); + + if (MAIN_POWER_SELECT == PWR_SEL_VCC) + { + while (hal_pwr_get_vcc_power_ready() == false); + } + + /* system 正常启动 */ + + /* enter deep sleep mode */ + TAU_LOGD("enter deep mode now\n"); + + /* 息屏电源供电选择 */ + hal_pwr_set_sleep_mode_power(SLEEP_MODE_POWER); + + /* deep sleep mode,配置AP RSTN 上升沿,TD INT 下降沿唤醒 */ + hal_pwr_enter_deep_sleep_mode(WUP_RISING_EDGE, WUP_FALLING_EDGE); + /* 数字完全掉电,SWD无法通讯,唤醒后芯片重启 */ + return true; +} + +/** +* @brief pwr demo case +* @param none +* @retval none +*/ +void demo_hal_pwr(void) +{ + TAU_LOGD("pwr dmeo \n"); + /* normal sleep mode demo */ + demo_normal_sleep_mode(); + /* stop sleep mode demo */ + demo_stop_sleep_mode(); + /* deep sleep mode demo */ + demo_deep_sleep_mode(); +} +#endif diff --git a/src/app/module_demo/demo_hal_pwr.h b/src/app/module_demo/demo_hal_pwr.h new file mode 100644 index 0000000..c1edefb --- /dev/null +++ b/src/app/module_demo/demo_hal_pwr.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* Copyright (C) 2020-2023, tau Systems (R),All Rights Reserved. +* +* File: demo_hal_pwr.h +* Description: demo pwr 头文件 +* Version: V0.1 +* Date： 2023-07-27 +* Author: jaya + *******************************************************************************/ +#ifndef __DEMO_HAL_PWR_H__ +#define __DEMO_HAL_PWR_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "test_cfg_global.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +void demo_hal_pwr(void); + +#endif /* __DEMO_HAL_PWR_H__ */ + diff --git a/src/app/module_demo/demo_hal_spi.c b/src/app/module_demo/demo_hal_spi.c new file mode 100644 index 0000000..ec5c2aa --- /dev/null +++ b/src/app/module_demo/demo_hal_spi.c @@ -0,0 +1,485 @@ +/******************************************************************************* +* Copyright (C) 2020-2023, tau Systems (R),All Rights Reserved. +* +* File: demo_hal_spi.c +* Description： spi demo code +* Version： V0.1 +* Date： 2023-07-27 +* Author： swx +*******************************************************************************/ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "hal_spi_master.h" +#include "hal_spi_slave.h" +#include "demo_hal_spi.h" +#include "hal_gpio.h" +#include "tau_log.h" +#include "tau_delay.h" + +#if _MODULE_DEMO_SPI_EN +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "demo_hal_spi" + +#define BUFFER_SIZE 255 + +#define CHECK_TRANS_RESULT(src, dst, size) \ + for(uint32_t check_num = 0; check_num < size; check_num ++) \ + {\ + if(src[check_num] != dst[check_num])\ + {\ + TAU_LOGD("src[%d] = %x, dst[%d] = %x , error!!\n",check_num,src[check_num],check_num,dst[check_num]);\ + return false;\ + }\ + }\ + +/******************************************************************************* +* 3.Global function and Global variable declarations +*******************************************************************************/ +bool spis_hw_miss_flag = false; + +/*SPIS硬件回复功能32组回复数据*/ +uint8_t spis_hw_header_data0[] = {0xf0, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d}; +uint8_t spis_hw_header_data1[] = {0xf1, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19}; +uint8_t spis_hw_header_data2[] = {0xf2, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29}; +uint8_t spis_hw_header_data3[] = {0xf3, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39}; +uint8_t spis_hw_header_data4[] = {0xf4, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49}; +uint8_t spis_hw_header_data5[] = {0xf5, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59}; +uint8_t spis_hw_header_data6[] = {0xf6, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69}; +uint8_t spis_hw_header_data7[] = {0xf7, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79}; +uint8_t spis_hw_header_data8[] = {0xf8, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89}; +uint8_t spis_hw_header_data9[] = {0xf9, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99}; +uint8_t spis_hw_header_data10[] = {0xfa, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9}; +uint8_t spis_hw_header_data11[] = {0xfb, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9}; +uint8_t spis_hw_header_data12[] = {0xfc, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9}; +uint8_t spis_hw_header_data13[] = {0xfd, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9}; +uint8_t spis_hw_header_data14[] = {0xfe, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9}; +uint8_t spis_hw_header_data15[] = {0xff, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9}; +uint8_t spis_hw_header_data16[] = {0xf0, 0x21, 0x31, 0x41, 0x51, 0x61, 0x71, 0x81, 0x91}; +uint8_t spis_hw_header_data17[] = {0xf1, 0x22, 0x31, 0x42, 0x52, 0x62, 0x72, 0x82, 0x92}; +uint8_t spis_hw_header_data18[] = {0xf2, 0x23, 0x33, 0x43, 0x53, 0x63, 0x73, 0x83, 0x93}; +uint8_t spis_hw_header_data19[] = {0xf3, 0x24, 0x34, 0x44, 0x54, 0x64, 0x74, 0x84, 0x94}; +uint8_t spis_hw_header_data20[] = {0xf4, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09}; +uint8_t spis_hw_header_data21[] = {0xf5, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19}; +uint8_t spis_hw_header_data22[] = {0xf6, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29}; +uint8_t spis_hw_header_data23[] = {0xf7, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39}; +uint8_t spis_hw_header_data24[] = {0xf8, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49}; +uint8_t spis_hw_header_data25[] = {0xf9, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59}; +uint8_t spis_hw_header_data26[] = {0xfa, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69}; +uint8_t spis_hw_header_data27[] = {0xfb, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79}; +uint8_t spis_hw_header_data28[] = {0xfc, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89}; +uint8_t spis_hw_header_data29[] = {0xfd, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99}; +uint8_t spis_hw_header_data30[] = {0xfe, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89}; +uint8_t spis_hw_header_data31[] = {0xff, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xf0, 0x13, 0xff}; + +static hal_spis_hw_ack_info_t spis_hw_test_header[32] = +{ + /*序号_匹配值_匹配长度_使能_回复延时_回复数据的地址_回复数据长度 */ + {0, {0x01, 0x02, 0x03, 0x04}, 0, 1, 0, spis_hw_header_data0, sizeof(spis_hw_header_data0) / sizeof(uint8_t) - 1}, + {1, {0x05, 0x06, 0x07, 0x08}, 1, 1, 1, spis_hw_header_data1, sizeof(spis_hw_header_data1) / sizeof(uint8_t) - 1}, + {2, {0x09, 0x0a, 0x0b, 0x0c}, 2, 1, 2, spis_hw_header_data2, sizeof(spis_hw_header_data2) / sizeof(uint8_t) - 1}, + {3, {0x0d, 0x0e, 0x0f, 0x10}, 3, 1, 3, spis_hw_header_data3, sizeof(spis_hw_header_data3) / sizeof(uint8_t) - 1}, + {4, {0x11, 0x12, 0x13, 0x14}, 0, 1, 4, spis_hw_header_data4, sizeof(spis_hw_header_data4) / sizeof(uint8_t) - 1}, + {5, {0x15, 0x16, 0x17, 0x18}, 1, 1, 5, spis_hw_header_data5, sizeof(spis_hw_header_data5) / sizeof(uint8_t) - 1}, + {6, {0x19, 0x1a, 0x1b, 0x1c}, 2, 1, 6, spis_hw_header_data6, sizeof(spis_hw_header_data6) / sizeof(uint8_t) - 1}, + {7, {0x1d, 0x1e, 0x1f, 0x20}, 3, 1, 7, spis_hw_header_data7, sizeof(spis_hw_header_data7) / sizeof(uint8_t) - 1}, + {8, {0x21, 0x22, 0x23, 0x24}, 0, 1, 8, spis_hw_header_data8, sizeof(spis_hw_header_data8) / sizeof(uint8_t) - 1}, + {9, {0x25, 0x26, 0x27, 0x28}, 1, 1, 9, spis_hw_header_data9, sizeof(spis_hw_header_data9) / sizeof(uint8_t) - 1}, + {10, {0x29, 0x2a, 0x2b, 0x2c}, 2, 1, 10, spis_hw_header_data10, sizeof(spis_hw_header_data10) / sizeof(uint8_t) - 1}, + {11, {0x2d, 0x2e, 0x2f, 0x30}, 3, 1, 0, spis_hw_header_data11, sizeof(spis_hw_header_data11) / sizeof(uint8_t) - 1}, + {12, {0x31, 0x32, 0x33, 0x34}, 0, 1, 1, spis_hw_header_data12, sizeof(spis_hw_header_data12) / sizeof(uint8_t) - 1}, + {13, {0x35, 0x36, 0x37, 0x38}, 1, 1, 2, spis_hw_header_data13, sizeof(spis_hw_header_data13) / sizeof(uint8_t) - 1}, + {14, {0x39, 0x3a, 0x3b, 0x3c}, 2, 1, 3, spis_hw_header_data14, sizeof(spis_hw_header_data14) / sizeof(uint8_t) - 1}, + {15, {0x3d, 0x3e, 0x3f, 0x40}, 3, 1, 4, spis_hw_header_data15, sizeof(spis_hw_header_data15) / sizeof(uint8_t) - 1}, + {16, {0x41, 0x42, 0x43, 0x44}, 0, 1, 5, spis_hw_header_data16, sizeof(spis_hw_header_data16) / sizeof(uint8_t) - 1}, + {17, {0x45, 0x46, 0x47, 0x48}, 1, 1, 6, spis_hw_header_data17, sizeof(spis_hw_header_data17) / sizeof(uint8_t) - 1}, + {18, {0x49, 0x4a, 0x4b, 0x4c}, 2, 1, 7, spis_hw_header_data18, sizeof(spis_hw_header_data18) / sizeof(uint8_t) - 1}, + {19, {0x4d, 0x4e, 0x4f, 0x50}, 3, 1, 8, spis_hw_header_data19, sizeof(spis_hw_header_data19) / sizeof(uint8_t) - 1}, + {20, {0x51, 0x52, 0x53, 0x54}, 0, 1, 9, spis_hw_header_data20, sizeof(spis_hw_header_data20) / sizeof(uint8_t) - 1}, + {21, {0x55, 0x56, 0x57, 0x58}, 1, 1, 10, spis_hw_header_data21, sizeof(spis_hw_header_data21) / sizeof(uint8_t) - 1}, + {22, {0x59, 0x5a, 0x5b, 0x5c}, 2, 1, 11, spis_hw_header_data22, sizeof(spis_hw_header_data22) / sizeof(uint8_t) - 1}, + {23, {0x5d, 0x5e, 0x5f, 0x60}, 3, 1, 12, spis_hw_header_data23, sizeof(spis_hw_header_data23) / sizeof(uint8_t) - 1}, + {24, {0x61, 0x62, 0x63, 0x64}, 0, 1, 13, spis_hw_header_data24, sizeof(spis_hw_header_data24) / sizeof(uint8_t) - 1}, + {25, {0x65, 0x66, 0x67, 0x68}, 1, 1, 14, spis_hw_header_data25, sizeof(spis_hw_header_data25) / sizeof(uint8_t) - 1}, + {26, {0x69, 0x6a, 0x6b, 0x6c}, 2, 1, 15, spis_hw_header_data26, sizeof(spis_hw_header_data26) / sizeof(uint8_t) - 1}, + {27, {0x6d, 0x6e, 0x6f, 0x70}, 3, 1, 11, spis_hw_header_data27, sizeof(spis_hw_header_data27) / sizeof(uint8_t) - 1}, + {28, {0x71, 0x72, 0x73, 0x74}, 0, 1, 12, spis_hw_header_data28, sizeof(spis_hw_header_data28) / sizeof(uint8_t) - 1}, + {29, {0x75, 0x76, 0x77, 0x78}, 1, 1, 13, spis_hw_header_data29, sizeof(spis_hw_header_data29) / sizeof(uint8_t) - 1}, + {30, {0x79, 0x7a, 0x7b, 0x7c}, 2, 1, 12, spis_hw_header_data30, sizeof(spis_hw_header_data30) / sizeof(uint8_t) - 1}, + {31, {0x7d, 0x7e, 0x7f, 0x80}, 3, 1, 14, spis_hw_header_data31, sizeof(spis_hw_header_data31) / sizeof(uint8_t) - 1}, +}; + +static uint8_t spim_write_buffer[BUFFER_SIZE] = {0}; +static uint8_t spim_read_buffer[BUFFER_SIZE] = {0}; +static uint8_t spis_read_buffer[BUFFER_SIZE] = {0}; +static uint8_t spis_write_buffer[BUFFER_SIZE] = {0}; + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ + +/** +* @brief spi master IO初始化 +* @param none +* @retval +*/ +static void spim_io_init(void) +{ + io_pad_attr_t attrs[] = + { + {IO_PAD_TD_SPIM_CLK, PIN5_MODE_SPIM_SCLK, IO_IOE_NONE, IO_LVL_HIGH}, + {IO_PAD_TD_SPIM_CSN, PIN6_MODE_SPIM_CSN, IO_IOE_NONE, IO_LVL_HIGH}, + {IO_PAD_TD_SPIM_MISO, PIN7_MODE_SPIM_MISO, IO_IOE_NONE, IO_LVL_HIGH}, + {IO_PAD_TD_SPIM_MOSI, PIN4_MODE_SPIM_MOSI, IO_IOE_NONE, IO_LVL_HIGH} + }; + uint8_t size = sizeof(attrs) / sizeof(io_pad_attr_t); + hal_gpio_config_pad(attrs, size); +} + +/** +* @brief spi slave IO初始化 +* @param none +* @retval +*/ +static void spis_io_init(void) +{ + io_pad_attr_t attrs[] = + { + {IO_PAD_AP_SPIS_CLK, PIN32_MODE_SPIS_SCLK, IO_IOE_NONE, IO_LVL_HIGH}, + {IO_PAD_AP_SPIS_CSN, PIN31_MODE_SPIS_CSN, IO_IOE_NONE, IO_LVL_HIGH}, + {IO_PAD_AP_SPIS_MISO, PIN30_MODE_SPIS_MISO, IO_IOE_NONE, IO_LVL_HIGH}, + {IO_PAD_AP_SPIS_MOSI, PIN33_MODE_SPIS_MOSI, IO_IOE_NONE, IO_LVL_HIGH} + }; + uint8_t size = sizeof(attrs) / sizeof(io_pad_attr_t); + hal_gpio_config_pad(attrs, size); +} + +/** +* @brief spi slave中断回调函数 +* @param event：SPIS收到的中断事件 +* @param packet_info： SPIS收到的数据packet +* @retval +*/ +void spis_callback(hal_spis_event_e event, hal_spis_packet_info_t *packet_info) +{ + /* 收到CS_RISE中断 */ + if (event == SPIS_EVENT_RCV_CS_RISE) + { + /* 更新SPIS的txbuffer和rxbuffer */ + hal_spis_update_rx_buffer(spis_read_buffer, BUFFER_SIZE); + hal_spis_update_tx_buffer(spis_write_buffer, BUFFER_SIZE, true); + } + /* 收到CS_FALL中断 */ + else if (event == SPIS_EVENT_RCV_CS_FALL) + { + //TAU_LOGD("spis_test SPIS_EVENT_RCV_CS_FALL\n"); + } + /* 收到数据接收指定阈值中断 */ + else if (event == SPIS_EVENT_RCV_CNT) + { + //TAU_LOGD("spis_test SPIS_EVENT_RCV_CNT\n"); + } + /* 收到数据接收完全中断 */ + else if (event == SPIS_EVENT_RCV_FULL) + { + //TAU_LOGD("spis_test SPIS_EVENT_RCV_CNT\n"); + } +} + +/** +* @brief spi slave硬件快速回复功能中断回调函数 +* @param event：SPIS收到的中断事件 +* @param packet_info： SPIS收到的数据packet +* @retval +*/ +void spis_hw_callback(hal_spis_event_e event, hal_spis_packet_info_t *packet_info) +{ + /* 收到CS_RISE中断 */ + if (event == SPIS_EVENT_RCV_CS_RISE) + { + /* 产生了ALL_MISS中断的标记 */ + if (spis_hw_miss_flag) + { + /* 使能SPIS硬件快速回复功能，默认回复值为0xE0 */ + hal_spis_set_hw_ack_enable(ENABLE, 0xE0); + spis_hw_miss_flag = false; + } + /* SPIS更新读写buffer */ + hal_spis_update_tx_buffer(spis_hw_header_data31, sizeof(spis_hw_header_data31) / sizeof(uint8_t), true); + hal_spis_update_rx_buffer(spis_read_buffer, BUFFER_SIZE); + } + + /* 收到ALL_MISS中断 */ + if (event == SPIS_EVENT_ALL_MISS) + { + /* 关闭SPIS硬件快速回复功能，默认回复值为0xF0 */ + hal_spis_set_hw_ack_enable(DISABLE, 0xf0); + spis_hw_miss_flag = true; + TAU_LOGE("All miss intr test\n"); + } +} + +/** +* @brief 获取随机值函数 +* @param range_begin: 随机值范围起始 +* @param renge_end: 随机值范围结束 +* @retval uint32_t : 范围内随机值 +*/ +uint32_t unit_case_get_rand(uint32_t range_begin, uint32_t renge_end) +{ + uint32_t range = 1; + if (renge_end > range_begin) + { + range = renge_end - range_begin + 1; + } + else + { + TAU_LOGE("rand range[%d ~ %d] error! default set to 1\n"); + } + return (uint32_t)((rand() % range) + range_begin); +} + +/** +* @brief spi master和slave的发送/接收buffer初始化 +* @param none +* @retval +*/ +static bool spi_case_rand_buffer(bool spim_en, bool spis_en) +{ + TAU_LOGD("spi_case_rand_buffer\n"); + /* read buffer默认初始化为0, tx buffer 初始为随机数 */ + uint8_t i = 0 ; + uint32_t count = BUFFER_SIZE; + for (i = 0; i < count; i ++) + { + spis_read_buffer[i] = 0; + spim_read_buffer[i] = 0; + if (spim_en) + { + spim_write_buffer[i] = unit_case_get_rand(0, 255); + } + if (spis_en) + { + spis_write_buffer[i] = unit_case_get_rand(0, 255); + } + } + return true; +} + + +/** +* @brief 芯片SPIM与SPIS对接,验证基础传输数据的正确性 +* @param +* @retval bool true/false +*/ +static bool hal_spi_base_case(void) +{ + uint32_t speed = 400000; + uint8_t cpha = 0; + uint8_t cpol = 0; + + /* 随机buffer值 */ + spi_case_rand_buffer(true, true); + + /* SPIS IO初始化 */ + spis_io_init(); + /* SPIS初始化，相位0+极性0 */ + hal_spis_init(cpha, cpol); + /* SPIS设置初始读写buffer */ + hal_spis_update_rx_buffer(spis_read_buffer, BUFFER_SIZE); + hal_spis_update_tx_buffer(spis_write_buffer, BUFFER_SIZE, true); + /* SPIS注册回调函函数，这里开启了CS_RISE、CS_FALL、RX_CNT、RX_FULL中断，RX_CNT阈值设置为100 */ + hal_spis_register_callback(spis_callback, SPIS_EVENT_RCV_CS_RISE | SPIS_EVENT_RCV_CS_FALL | SPIS_EVENT_RCV_CNT | SPIS_EVENT_RCV_FULL, 100); + /* SPIS启动 */ + hal_spis_start(); + + /* SPIM IOc初始化 */ + spim_io_init(); + /* SPIM初始化，400k传输速率+相位0+极性0 */ + hal_spim_init(speed, cpha, cpol); + + TAU_LOGD("base trans para cpha[%d] cpol[%d] speed[%d] \n", cpha, cpol, speed); + + /* 测试 SPIM CPU读写 */ + hal_spim_read(spim_write_buffer, BUFFER_SIZE, spim_read_buffer, BUFFER_SIZE); + /* SPIM 写完，检查 SPIS RX buffer 是否等于 SPIM TX buffer*/ + CHECK_TRANS_RESULT(spim_write_buffer, spis_read_buffer, BUFFER_SIZE); + /* SPIM 读完，检查 SPIS TX buffer 是否等于 SPIM RX buffer*/ + CHECK_TRANS_RESULT(spis_write_buffer, spim_read_buffer, BUFFER_SIZE); + + /* 随机buffer值 */ + spi_case_rand_buffer(true, false); + + /* 测试 SPIM CPU写 */ + hal_spim_write(spim_write_buffer, BUFFER_SIZE); + /* SPIM 写完，检查 SPIS RX buffer 是否等于 SPIM TX buffer*/ + CHECK_TRANS_RESULT(spim_write_buffer, spis_read_buffer, BUFFER_SIZE); + + /* 传输完成,关闭SPI */ + hal_spis_stop(); + hal_spis_deinit(); + hal_spim_deinit(); + + TAU_LOGD("hal_spi_base_case done!\n"); + return true; +} + + +/** +* @brief 芯片SPIM与SPIS对接, 验证SPIS 硬件快速回复传输功能 +* @param +* @retval bool true/false +*/ +static bool hal_spis_hw_case(void) +{ + uint32_t speed = 400000; + uint8_t cpha = 0; + uint8_t cpol = 0; + uint8_t write_buffer[30] = {0x9e, 0xa0, 0x00, 0x01, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, + 0x8a, 0x1b, 0x1c, 0x5d, 0x7e, 0x4f, 0x20, 0x21, 0x22, 0x23, + 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x30, 0x31, 0x32, 0x33 + }; + /* SPIS IO初始化 */ + spis_io_init(); + /* SPIS初始化，相位0+极性0 */ + hal_spis_init(cpha, cpol); + + /* SPIS设置初始读buffer */ + hal_spis_update_rx_buffer(spis_read_buffer, BUFFER_SIZE); + /* SPIS设置初始写buffer */ + hal_spis_update_tx_buffer(spis_hw_header_data31, sizeof(spis_hw_header_data31) / sizeof(uint8_t), true); + /* SPIS注册回调函函数，这里开启了CS_RISE和ALL_MISS中断 */ + hal_spis_register_callback(spis_hw_callback, SPIS_EVENT_RCV_CS_RISE | SPIS_EVENT_ALL_MISS, 0); + + /* 设置SPIS硬件快速回复参数 */ + hal_spis_set_hw_ack_info(spis_hw_test_header, (sizeof(spis_hw_test_header) / sizeof(hal_spis_hw_ack_info_t))); + /* 使能SPIS硬件快速回复功能，默认回复值为0xE0 */ + hal_spis_set_hw_ack_enable(ENABLE, 0xE0); + /* SPIS启动 */ + hal_spis_start(); + + /* SPIM IO初始化 */ + spim_io_init(); + /* SPIM初始化，400k传输速率+相位0+极性0 */ + hal_spim_init(speed, cpha, cpol); + + /* 32组硬件快速回复功能参数demo */ + for (int k = 0; k < 32; k++) + { + /* write_buffer前4个字节设置为每组参数的匹配值 */ + for (int j = 0; j < 4; j++) + { + write_buffer[j] = spis_hw_test_header[k].cmp_data[j]; + } + + /* 将第11组和第14组的write_buffer[0]自加，这样匹配不到后就会产生ALL_MISS中断 */ + if ((k == 10) || (k == 13)) + { + write_buffer[0]++; + } + + /* FLUSH SPIM FIFO */ + hal_spim_flush(); + /* SPIM发送30个write_buffer数据给SPIS，并读取SPIS的30个数据到spim_read_buffer */ + hal_spim_read(write_buffer, 30, spim_read_buffer, 30); + + /* 等待SPIM传输完成 */ + while (!hal_spim_get_transfer_complete()); + + printf("SPIM_TX:"); + for (int i = 0; i < 30; i++) + { + printf("%02x ", spis_read_buffer[i]); + } + printf("\n"); + printf("SPIM_RX:"); + for (int i = 0; i < 30; i++) + { + printf("%02x ", spim_read_buffer[i]); + } + printf("\n"); + + /* 以下是校验SPIS的硬件快速回复数据是否正确 */ + int index = spis_hw_test_header[k].delay_clk + 1 + spis_hw_test_header[k].cmp_len + 1; + printf("CMP_LEN:%d, DELAY_CLK:%d\n", spis_hw_test_header[k].cmp_len, spis_hw_test_header[k].delay_clk); + bool flag = true; + for (int i = 0; i < spis_hw_test_header[k].ack_length; i++) + { + if (spis_hw_test_header[k].ack_address[i] == spim_read_buffer[index + i]) + { + if (flag) + { + printf("Group[%d] OK\n", k); + flag = false; + } + + continue; + } + else + { + if ((k == 10) || (k == 13)) + { + if (flag) + { + printf("Group[%d] All_miss init test\n", k); + flag = false; + } + continue; + } + else + { + printf("Header_addr[%d]:%02x Header_addr[%d]:%02x ", i, spis_hw_test_header[k].ack_address[i], index + i, spim_read_buffer[index + i]); + printf("Group[%d] error\n", k); + return false; + } + } + } + printf("\n"); + } + + /* 传输完成,关闭SPI */ + hal_spis_stop(); + hal_spis_deinit(); + hal_spim_deinit(); + TAU_LOGD("hal_spis_hw_case done!\n"); + return true; +} + +/** +* @brief spi demo case +* @param none +* @retval none +*/ +void demo_hal_spi(void) +{ + /* 基础传输case */ + if (!hal_spi_base_case()) + { + hal_spis_stop(); + hal_spis_deinit(); + hal_spim_deinit(); + TAU_LOGD("hal_spi_base_case fail!\n"); + } + + /* SPIS硬件快速回复功能case */ + if (!hal_spis_hw_case()) + { + hal_spis_stop(); + hal_spis_deinit(); + hal_spim_deinit(); + TAU_LOGD("hal_spis_hw_case fail!\n"); + } + + TAU_LOGD("spi case done\n"); +} +#endif diff --git a/src/app/module_demo/demo_hal_spi.h b/src/app/module_demo/demo_hal_spi.h new file mode 100644 index 0000000..cd1db2b --- /dev/null +++ b/src/app/module_demo/demo_hal_spi.h @@ -0,0 +1,37 @@ +/******************************************************************************* +* Copyright (C) 2020-2023, tau Systems (R),All Rights Reserved. +* +* File: demo_hal_spi.h +* Description: demo spi 头文件 +* Version: V0.1 +* Date： 2023-07-27 +* Author: swx +*******************************************************************************/ +#ifndef __DEMO_HAL_SPI_H__ +#define __DEMO_HAL_SPI_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "test_cfg_global.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +void demo_hal_spi(void); + +#endif /* __DEMO_HAL_SPI_H__ */ + + diff --git a/src/app/module_demo/demo_hal_swire.c b/src/app/module_demo/demo_hal_swire.c new file mode 100644 index 0000000..b8c45be --- /dev/null +++ b/src/app/module_demo/demo_hal_swire.c @@ -0,0 +1,140 @@ +/******************************************************************************* +* +* +* File: demo_hal_swire.c +* Description： swire demo code +* Version： V0.1 +* Date： 2023-07-27 +* Author： jaya + *******************************************************************************/ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "stdarg.h" +#include "stdlib.h" +#include "stdio.h" +#include "test_cfg_global.h" +#include "hal_swire.h" +#include "hal_gpio.h" +#include "tau_log.h" +#include "tau_delay.h" +#include "demo_hal_swire.h" + +#if _MODULE_DEMO_SWIRE_EN +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "demo_hal_swire" + +/******************************************************************************* +* 3.Global function and Global variable declarations +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief swire 手动产生波形 demo +* @param +* @retval bool true/false +*/ +static bool demo_hal_swire_gen_swire_manual(void) +{ + /* 配置PIN15为SWIRE 输出*/ + hal_gpio_set_mode(IO_PAD_AP_SWIRE, PIN15_MODE_SWIRE); + /* swire 初始化 */ + hal_swire_init(); + /* 启动swire, Swire引脚信号拉高 */ + hal_swire_enable(true); + delayMs(100); + /* 配置pulse 为36,产生36个脉冲波形后保持拉高 */ + hal_swire_set_pulse(36); + delayMs(100); + /* 配置pulse 为25,产生25个脉冲波形后保持拉高 */ + hal_swire_set_pulse(25); + delayMs(100); + /* 关闭swire, Swire引脚信号拉低 */ + hal_swire_enable(false); + /* swire去初始化 */ + hal_swire_deinit(); + return true; +} + +/** +* @brief swire 自动产生波形 demo +* @param +* @retval bool true/false +*/ +static bool demo_hal_swire_gen_swire_auto(void) +{ + /* 配置PIN15为SWIRE 输出*/ + hal_gpio_set_mode(IO_PAD_AP_SWIRE, PIN15_MODE_SWIRE); + /* swire 初始化 */ + hal_swire_init(); + hal_swire_set_timer(TIMER_NUM0, 16, true); + + /* 启动swire, Swire引脚信号拉高,每个16ms发送一次swire信号 */ + hal_swire_enable(true); + + /*保持每16ms输出36个脉冲，持续100ms*/ + hal_swire_set_pulse(36); /* 使用timer情况下pulse配置为0时实际输出255个脉冲, 可以在enable之前或者enable前后配置发送正确波形,消除255脉冲问题 */ + delayMs(100); + + /* 配置pulse 为25,保持每16ms输出36个脉冲，持续100ms */ + hal_swire_set_pulse(25); + + /* 关闭swire, Swire引脚信号拉低 */ + hal_swire_enable(false); + /* swire去初始化 */ + hal_swire_deinit(); + return true; +} + +/** +* @brief swire 配置波形形状demo +* @param +* @retval bool true/false +*/ +static bool demo_hal_swire_set_swire_waveform(void) +{ + /* 配置PIN15为SWIRE 输出*/ + hal_gpio_set_mode(IO_PAD_AP_SWIRE, PIN15_MODE_SWIRE); + /* swire 初始化 */ + hal_swire_init(); + /* 配置波形,持续时间50us */ + hal_swire_set_waveform(50, 50, 50, 50); + /* 启动swire, Swire引脚信号拉高 */ + hal_swire_enable(true); + delayMs(100); + /* 配置pulse 为36,产生36个脉冲波形后保持拉高 */ + hal_swire_set_pulse(36); + delayMs(100); + /* 关闭swire, Swire引脚信号拉低 */ + hal_swire_enable(false); + /* swire去初始化 */ + hal_swire_deinit(); + return true; +} + + +/** +* @brief swire demo case +* @param none +* @retval none +*/ +void demo_hal_swire(void) +{ + TAU_LOGD("swire dmeo \n"); + demo_hal_swire_gen_swire_manual(); + //demo_hal_swire_gen_swire_auto(); + //demo_hal_swire_set_swire_waveform(); +} +#endif diff --git a/src/app/module_demo/demo_hal_swire.h b/src/app/module_demo/demo_hal_swire.h new file mode 100644 index 0000000..c39f949 --- /dev/null +++ b/src/app/module_demo/demo_hal_swire.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* Copyright (C) 2020-2023, tau Systems (R),All Rights Reserved. +* +* File: demo_hal_swire.h +* Description: demo swire 头文件 +* Version: V0.1 +* Date： 2023-07-27 +* Author: jaya + *******************************************************************************/ +#ifndef __DEMO_HAL_SWIRE_H__ +#define __DEMO_HAL_SWIRE_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "test_cfg_global.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +void demo_hal_swire(void); + +#endif /* __DEMO_HAL_SWIRE_H__ */ + diff --git a/src/app/module_demo/demo_hal_timer.c b/src/app/module_demo/demo_hal_timer.c new file mode 100644 index 0000000..7abe963 --- /dev/null +++ b/src/app/module_demo/demo_hal_timer.c @@ -0,0 +1,136 @@ +/******************************************************************************* +* +* +* File: demo_hal_timer.c +* Description： timer demo源文件 +* Version： V0.1 +* Date： 2023-07-27 +* Author： zzf + *******************************************************************************/ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "hal_timer.h" +#include "hal_gpio.h" +#include "tau_log.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "timer-log" + +#define TIMER_DEMO_NORMAL 0 //定时器常规使用，循环超时 +#define TIMER_DEMO_RESTART 1 //中断重启定时器 + +#define TIMER_SEL TIMER_NUM0 //timer0-3 都ok + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ +static io_pad_e sg_timer_io_pad = IO_PAD_GPIO1; +static gpio_level_e sg_timer_io_lvl = IO_LVL_LOW; +#if TIMER_DEMO_RESTART +static uint16_t sg_timer_count = 1; +#endif + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +#if TIMER_DEMO_RESTART +/** +* @brief 重新循环中断回调函数 +* @param None +* @retval None +*/ +static void demo_timer_restart_callback(void *data) +{ + /* 翻转GPIO */ + sg_timer_io_lvl = (sg_timer_io_lvl ? IO_LVL_LOW : IO_LVL_HIGH); + hal_gpio_set_output_data(sg_timer_io_pad, sg_timer_io_lvl); + + /* 重新启动定时器 */ + sg_timer_count = sg_timer_count * 10; + if (sg_timer_count > 100) + { + sg_timer_count = 1; + } + hal_timer_start(TIMER_SEL, sg_timer_count * 10, demo_timer_restart_callback, NULL); +} + +/** +* @brief 重新中断例程初始化 +* @param None +* @retval None +*/ +static void demo_timer_case_restart(void) +{ + /*重新初始化定时器*/ + hal_timer_init(TIMER_SEL); + hal_timer_set_repeat(TIMER_SEL, false); + + /*初始化GPIO低电平*/ + hal_gpio_init_output(sg_timer_io_pad, sg_timer_io_lvl); + + /*更新当前timer测试参数*/ + hal_timer_start(TIMER_SEL, sg_timer_count * 10, demo_timer_restart_callback, NULL); +} +#endif + +#if TIMER_DEMO_NORMAL +/** +* @brief 多次循环中断回调函数 +* @param None +* @retval None +*/ +static void demo_timer_normal_callback(void *data) +{ + /* 翻转GPIO */ + sg_timer_io_lvl = (sg_timer_io_lvl ? IO_LVL_LOW : IO_LVL_HIGH); + hal_gpio_set_output_data(sg_timer_io_pad, sg_timer_io_lvl); +} + +/** +* @brief 重新中断例程初始化 +* @param None +* @retval None +*/ +static void demo_timer_case_normal(void) +{ + /*重新初始化定时器*/ + hal_timer_init(TIMER_SEL); + hal_timer_set_repeat(TIMER_SEL, true); + + /*初始化GPIO低电平*/ + hal_gpio_init_output(sg_timer_io_pad, sg_timer_io_lvl); + + /*更新当前timer测试参数*/ + hal_timer_start(TIMER_SEL, 10, demo_timer_normal_callback, NULL); +} +#endif + +/** +* @brief demo测试接口函数 +* @param None +* @retval None +*/ +void demo_timer_case(void) +{ + TAU_LOGI("start test\r\n"); + +#if TIMER_DEMO_NORMAL + demo_timer_case_normal(); // 10ms定时进行IO电平翻转 +#elif TIMER_DEMO_RESTART + demo_timer_case_restart(); +#endif + + TAU_LOGI("end test\r\n"); +} + diff --git a/src/app/module_demo/demo_hal_timer.h b/src/app/module_demo/demo_hal_timer.h new file mode 100644 index 0000000..0de0f1d --- /dev/null +++ b/src/app/module_demo/demo_hal_timer.h @@ -0,0 +1,39 @@ +/******************************************************************************* +* +* +* File: demo_hal_timer.h +* Description: timer demo头文件 +* Version: V0.1 +* Date: 2023-07-27 +* Author: zzf + *******************************************************************************/ +#ifndef __DEMO_TIMER_H__ +#define __DEMO_TIMER_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief demo测试接口函数 +* @param None +* @retval None +*/ +void demo_timer_case(void); + +#endif /* __DEMO_TIMER_H__ */ diff --git a/src/app/module_demo/demo_hal_uart.c b/src/app/module_demo/demo_hal_uart.c new file mode 100644 index 0000000..c4cf64e --- /dev/null +++ b/src/app/module_demo/demo_hal_uart.c @@ -0,0 +1,648 @@ +/******************************************************************************* +* +* +* File: demo_hal_uart.c +* Description： 测试说明：将电脑端USB转串口分别连接UART0，1测试 +* Version： V0.1 +* Date： 2023-07-09 +* Author： kc + *******************************************************************************/ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "stdarg.h" +#include "stdlib.h" +#include "stdio.h" +#include "test_cfg_global.h" +#include "hal_uart.h" +#include "hal_gpio.h" +#include "tau_log.h" +#include "tau_delay.h" +#include "demo_hal_uart.h" + +#if _MODULE_DEMO_UART_EN +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "uart-log" + +#define UART_TEST_AUTO 1 + +#define TEST_UART_BAUDRATE 115200 + +/******************************************************************************* +* 3.Global function and Global variable declarations +*******************************************************************************/ + +/** + * @brief 测试case + */ +typedef enum +{ + UART_CASE_BLOCKING = 0, + UART_CASE_NONE_BLOCKING, + UART_CASE_DMA, + UART_CASE_MAX, + UART_CASE_LOOP_BACK, + UART_CASE_DEINIT, +} uart_case_e; + +typedef void (*unit_test_func)(); +typedef struct unit_test_entry_t +{ + char case_name[128]; /* Case名称 */ + unit_test_func case_func; /* Case处理函数 */ +} unit_test_entry_t; + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ +static char sg_uart_log[256] = {0}; +static char sg_uart_send_buff[1024] = {0}; +static char sg_uart_recv_buff[1024] = {0}; +static uart_case_e sg_uart_case = UART_CASE_BLOCKING; +static hal_uart_num_e sg_uart_cur_num = HAL_UART_0; +volatile static bool sg_uart_case_done = true; +static hal_uart_config_t s_huart; + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +void STRFMT(const char *fmt, ...) +{ + va_list ap;//初始化指向可变参数列表的指针 + //将第一个可变参数的地址付给ap，即ap指向可变参数列表的开始 + va_start(ap, fmt); + //将参数fmt、ap指向的可变参数一起转换成格式化字符串，放string数组中，其作用同sprintf（），只是参数类型不同 + vsprintf(sg_uart_log, fmt, ap); + va_end(ap); //ap付值为0，没什么实际用处，主要是为程序健壮性 +} + +#define TEST_LOG(num,format,...) \ + do { \ + STRFMT(format, ##__VA_ARGS__); \ + hal_uart_send_blocking(num, (uint8_t *)sg_uart_log, strlen(sg_uart_log)); \ + } while (0) +/************************************************************************** +* @name : TEST_UART_PinMux_Init +* @brief : UART 脚位功能初始化 +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +static void test_uart_mode_init(void) +{ + //UART 0 + hal_gpio_set_mode(IO_PAD_UART0_TX, PIN2_MODE_UART0_TX); + hal_gpio_set_mode(IO_PAD_UART0_RX, PIN36_MODE_UART0_RX); + //UART 1 只有唯一一组 + //hal_gpio_set_mode(IO_PAD_UART1_TX, PIN14_MODE_UART1_TX); + //hal_gpio_set_mode(IO_PAD_TD_TP_RESX, PIN13_MODE_UART1_RX); +} + +/************************************************************************** +* @name : test_uart_deinit +* @brief : uart注销 +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +static void test_uart_common_deinit(hal_uart_num_e num) +{ + delayMs(500); + hal_uart_deinit(num); +} + +/************************************************************************** +* @name : test_uart_normal_init +* @brief : uart 普通模式初始化 +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +static void test_uart_common_init(hal_uart_num_e num) +{ + hal_uart_config_t huart = {0}; + huart.baudrate = TEST_UART_BAUDRATE; + huart.data_width = HAL_UART_DATAWIDTH_8; + huart.parity = HAL_UART_PARITY_NO; + huart.stopbits = HAL_UART_STOPBIT_1; + hal_uart_init(num, &huart); +} + +/** +* @brief 获取端口号 +* @param 无 +* @retval 无 +*/ +static char test_uart_get_input_str(hal_uart_num_e num) +{ + char str = 0; + hal_uart_recv_blocking(num, (uint8_t *)&str, 1); + return str; +} + +/** +* @brief 获取输入字符串个数 +* @param 无 +* @retval 无 +*/ +static uint32_t test_uart_get_input_num(hal_uart_num_e num) +{ + uint32_t recv = 0; + char str[10] = {0}; + uint8_t i = 0; + + TEST_LOG(num, "input recv num and space to exit:"); + + while (1) + { + hal_uart_recv_blocking(num, (uint8_t *)&str[i], 1); + if (str[i] >= '0' && str[i] <= '9') + { + TEST_LOG(num, "%c", (char)str[i]); + i++; + } + else if (str[i] == 32) + { + str[i] = 0; + TEST_LOG(num, "\n"); + break; + } + } + + recv = atol(str); + return recv; +} + +/** +* @brief 复位uart所在PAD为GPIO mode +* @param 无 +* @retval 无 +*/ +static void test_uart_reset_uart_mode(void) +{ + hal_gpio_init_input(IO_PAD_AP_SPIS_MOSI); + hal_gpio_init_input(IO_PAD_UART0_TX); + hal_gpio_init_input(IO_PAD_AP_SPIS_MISO); + hal_gpio_init_input(IO_PAD_UART0_RX); + hal_gpio_init_input(IO_PAD_AP_TPRSTN); + hal_gpio_init_input(IO_PAD_AP_PWMEN); + hal_gpio_init_input(IO_PAD_TD_SPIM_MOSI); + hal_gpio_init_input(IO_PAD_UART1_TX); + hal_gpio_init_input(IO_PAD_TD_TP_RESX); +} + +/** +* @brief 在UART2上设置UART1的TX和RX PAD +* @param 无 +* @retval 无 +*/ +static void test_uart_set_uart_mode(void) +{ + char str = 0; + hal_uart_num_e uart_org_num = sg_uart_cur_num; + + TEST_LOG(uart_org_num, "select UART(0/1):\n"); + TEST_LOG(uart_org_num, "Enter:"); + str = test_uart_get_input_str(uart_org_num); + TEST_LOG(uart_org_num, "%c\n\n", str); + sg_uart_cur_num = (hal_uart_num_e)(str - '0'); + + if (HAL_UART_1 == sg_uart_cur_num) /* 测试UART1 */ + { + //sel tx + TEST_LOG(uart_org_num, "select UART1 TX:\n"); + TEST_LOG(uart_org_num, "0:IO_PAD_UART1_TX->PIN14_MODE_UART1_TX\n"); + //sel rx + TEST_LOG(uart_org_num, "select UART1 RX:\n"); + TEST_LOG(uart_org_num, "0:IO_PAD_TD_TP_RESX->PIN13_MODE_UART1_RX\n"); + TEST_LOG(uart_org_num, "change the connect pin and press space to continue \n"); + delayMs(200); + + test_uart_reset_uart_mode(); + hal_gpio_set_mode(IO_PAD_UART1_TX, PIN14_MODE_UART1_TX); + hal_gpio_set_mode(IO_PAD_TD_TP_RESX, PIN13_MODE_UART1_RX); + hal_uart_deinit(HAL_UART_0); + test_uart_common_init(HAL_UART_1); + } + else + { + uint8_t sel_tx, sel_rx; + //sel tx + TEST_LOG(uart_org_num, "select UART0 TX:\n"); + TEST_LOG(uart_org_num, "0:IO_PAD_UART0_TX->PIN2_MODE_UART0_TX\n"); + TEST_LOG(uart_org_num, "1:IO_PAD_AP_SPIS_MOSI->PIN33_MODE_UART0_TX \n"); + TEST_LOG(uart_org_num, "2:IO_PAD_TD_SPIM_MOSI->PIN4_MODE_UART0_TX\n"); + TEST_LOG(uart_org_num, "Enter:"); + str = test_uart_get_input_str(uart_org_num); + TEST_LOG(uart_org_num, "%c\n\n", str); + sel_tx = str - '0'; + + //sel rx + TEST_LOG(uart_org_num, "select UART0 RX:\n"); + TEST_LOG(uart_org_num, "0:IO_PAD_UART0_RX->PIN36_MODE_UART0_RX\n"); + TEST_LOG(uart_org_num, "1:IO_PAD_AP_SPIS_MISO->PIN30_MODE_UART0_RX\n"); + TEST_LOG(uart_org_num, "2:IO_PAD_AP_TPRSTN->PIN18_MODE_UART0_RX\n"); + TEST_LOG(uart_org_num, "3:IO_PAD_AP_PWMEN->PIN17_MODE_UART0_RX\n"); + TEST_LOG(uart_org_num, "4:IO_PAD_UART1_TX->PIN14_MODE_UART0_RX\n"); + TEST_LOG(uart_org_num, "Enter:"); + str = test_uart_get_input_str(uart_org_num); + TEST_LOG(uart_org_num, "%c\n\n", str); + sel_rx = str - '0'; + + TEST_LOG(uart_org_num, "change the connect pin and press space to continue \n"); + delayMs(500); + test_uart_reset_uart_mode(); + + switch (sel_tx) + { + case 0: + hal_gpio_set_mode(IO_PAD_UART0_TX, PIN2_MODE_UART0_TX); + break; + + case 1: + hal_gpio_set_mode(IO_PAD_AP_SPIS_MOSI, PIN33_MODE_UART0_TX); + break; + + case 2: + hal_gpio_set_mode(IO_PAD_TD_SPIM_MOSI, PIN4_MODE_UART0_TX); + break; + + default: + break; + } + + switch (sel_rx) + { + case 0: + hal_gpio_set_mode(IO_PAD_UART0_RX, PIN36_MODE_UART0_RX); + break; + + case 1: + hal_gpio_set_mode(IO_PAD_AP_SPIS_MISO, PIN30_MODE_UART0_RX); + break; + + case 2: + hal_gpio_set_mode(IO_PAD_AP_TPRSTN, PIN18_MODE_UART0_RX); + break; + + case 3: + hal_gpio_set_mode(IO_PAD_AP_PWMEN, PIN17_MODE_UART0_RX); + break; + + case 4: + hal_gpio_set_mode(IO_PAD_UART1_TX, PIN14_MODE_UART0_RX); + break; + + default: + break; + } + hal_uart_deinit(HAL_UART_1); + test_uart_common_init(HAL_UART_0); + } + while (1) + { + str = test_uart_get_input_str(sg_uart_cur_num); + if (str == 32) + { + break; + } + } +} + +/** +* @brief 是否重复 +* @param 无 +* @retval 无 +*/ +static bool test_uart_sel_continue() +{ + uint8_t str = 0; + delayMs(500); + test_uart_common_deinit(sg_uart_cur_num); + test_uart_common_init(sg_uart_cur_num); + TEST_LOG(sg_uart_cur_num, " y repeat \n"); + TEST_LOG(sg_uart_cur_num, " n exit \n"); + while (1) + { + str = test_uart_get_input_str(sg_uart_cur_num); + switch (str) + { + case 'y': + TEST_LOG(sg_uart_cur_num, "y\n"); + return true; + + case 'n': + TEST_LOG(sg_uart_cur_num, "n\n"); + return false; + + default: + continue; + } + } +} + +/************************************************************************** +* @name : test_uart_blocking +* @brief : UART TX，RX阻塞读写。 +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +static void test_uart_blocking(void) +{ + uint32_t recv = 0; + delayMs(500); + test_uart_common_deinit(sg_uart_cur_num); + test_uart_common_init(sg_uart_cur_num); + delayMs(500); + TEST_LOG(sg_uart_cur_num, "test uart%d start.\n", sg_uart_cur_num); + + //test recv + recv = test_uart_get_input_num(sg_uart_cur_num); + TEST_LOG(sg_uart_cur_num, "input %d char one time:\n", recv); + memset(sg_uart_recv_buff, 0, recv + 1); + if (!hal_uart_recv_blocking(sg_uart_cur_num, (uint8_t *)sg_uart_recv_buff, recv)) + { + TEST_LOG(sg_uart_cur_num, "an error has occurred!\n"); + } + TEST_LOG(sg_uart_cur_num, "%s\n", sg_uart_recv_buff); + + //test send + TEST_LOG(sg_uart_cur_num, "send:\n"); + strcpy(sg_uart_send_buff, sg_uart_recv_buff); + if (!hal_uart_send_blocking(sg_uart_cur_num, (uint8_t *)sg_uart_send_buff, strlen(sg_uart_send_buff))) + { + TEST_LOG(sg_uart_cur_num, "an error has occurred!\n"); + } + + TEST_LOG(sg_uart_cur_num, "\n"); + + sg_uart_case_done = true; +} + +/************************************************************************** +* @name : test_uart_trans_cb +* @brief : 用户回调函数 +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +static void test_uart_trans_cb(status_t status, void *user_data) +{ + switch (status) + { + case STATUS_UART_RX_IDLE: + case STATUS_UART_TX_IDLE: + *(bool *)user_data = true; + break; + + default: + break; + } +} + +/************************************************************************** +* @name : test_uart_none_blocking +* @brief : UART TX，RX非阻塞读写。 +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +static void test_uart_none_blocking(void) +{ + uint32_t recv = 0; + volatile bool int_done = false; + delayMs(500); + test_uart_common_deinit(sg_uart_cur_num); + s_huart.baudrate = TEST_UART_BAUDRATE; + s_huart.data_width = HAL_UART_DATAWIDTH_8; + s_huart.parity = HAL_UART_PARITY_NO; + s_huart.stopbits = HAL_UART_STOPBIT_1; + s_huart.callback = test_uart_trans_cb; + s_huart.user_data = &int_done; + hal_uart_init(sg_uart_cur_num, &s_huart); + delayMs(500); + TEST_LOG(sg_uart_cur_num, "test uart%d start...\n", sg_uart_cur_num); + TEST_LOG(sg_uart_cur_num, "input and output 10 char:\n"); + int_done = false; + memset(sg_uart_recv_buff, 0, recv + 1); + while (!hal_uart_recv_none_blocking(sg_uart_cur_num, (uint8_t *)sg_uart_recv_buff, 10)) + { + //TEST_LOG(sg_uart_cur_num, "device busy!\n"); + } + while (!int_done); + + //test send + int_done = false; + strcpy(sg_uart_send_buff, sg_uart_recv_buff); + while (!hal_uart_send_none_blocking(sg_uart_cur_num, (uint8_t *)sg_uart_send_buff, strlen(sg_uart_send_buff))) + { + //TEST_LOG(sg_uart_cur_num, "device busy!\n"); + } + while (!int_done); + + TEST_LOG(sg_uart_cur_num, "\n"); + + sg_uart_case_done = true; +} + + +/************************************************************************** +* @name : test_uart_dma_transmit +* @brief : UART DMA读写测试 +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +static void test_uart_dma_transmit(void) +{ + uint32_t recv = 0; + char str = 0; + bool int_done = false; + + while (1) + { + TEST_LOG(sg_uart_cur_num, "test uart%d start...\n", sg_uart_cur_num); + recv = test_uart_get_input_num(sg_uart_cur_num); + TEST_LOG(sg_uart_cur_num, "please input %d char once:\n", recv); + + test_uart_common_deinit(sg_uart_cur_num); + s_huart.baudrate = TEST_UART_BAUDRATE; + s_huart.data_width = HAL_UART_DATAWIDTH_8; + s_huart.parity = HAL_UART_PARITY_NO; + s_huart.stopbits = HAL_UART_STOPBIT_1; + s_huart.callback = test_uart_trans_cb; + s_huart.user_data = &int_done; + hal_uart_init(sg_uart_cur_num, &s_huart); + + int_done = false; + memset(sg_uart_recv_buff, 0, recv + 1); + while (!hal_uart_dma_recv(sg_uart_cur_num, (uint8_t *)sg_uart_recv_buff, recv)) + { + //TEST_LOG(sg_uart_cur_num, "device busy!\n"); + } + while (!int_done) + { + delayMs(500); + }; + + TEST_LOG(sg_uart_cur_num, "%s\n", sg_uart_recv_buff); + TEST_LOG(sg_uart_cur_num, "please input %d char twice:\n", recv); + + int_done = false; + memset(sg_uart_recv_buff, 0, recv + 1); + while (!hal_uart_dma_recv(sg_uart_cur_num, (uint8_t *)sg_uart_recv_buff, recv)) + { + //TEST_LOG(sg_uart_cur_num, "device busy!\n"); + } + while (!int_done) + { + delayMs(100); + //TEST_LOG("recv dma not done!!!\n"); + }; + TEST_LOG(sg_uart_cur_num, "%s\n", sg_uart_recv_buff); + + int_done = false; + strcpy(sg_uart_send_buff, "uart dma tx test comp once!\n"); + while (!hal_uart_dma_send(sg_uart_cur_num, (uint8_t *)sg_uart_send_buff, strlen(sg_uart_send_buff))) + { + //TEST_LOG(sg_uart_cur_num, "device busy!\n"); + } + while (!int_done); + + int_done = false; + strcpy(sg_uart_send_buff, "uart dma tx test comp twice!\n"); + while (!hal_uart_dma_send(sg_uart_cur_num, (uint8_t *)sg_uart_send_buff, strlen(sg_uart_send_buff))) + { + //TEST_LOG(sg_uart_cur_num, "device busy!\n"); + } + while (!int_done); + + if (sg_uart_cur_num == HAL_UART_0) + { + hal_uart_dma_path_close(HAL_UART0_DMA_PATH_TX); + hal_uart_dma_path_close(HAL_UART0_DMA_PATH_RX); + //TEST_LOG(sg_uart_cur_num, "close uart0 dma channel\n"); + } + else + { + hal_uart_dma_path_close(HAL_UART1_DMA_PATH_TX); + hal_uart_dma_path_close(HAL_UART1_DMA_PATH_RX); + //TEST_LOG(sg_uart_cur_num, "close uart1 dma channel\n"); + } + delayMs(500); + /* 用普通方式初始化uart */ + test_uart_common_deinit(sg_uart_cur_num); + test_uart_common_init(sg_uart_cur_num); + + TEST_LOG(sg_uart_cur_num, "0:continue\n"); + TEST_LOG(sg_uart_cur_num, "1:exit\n"); + TEST_LOG(sg_uart_cur_num, "Enter:"); + while (1) + { + str = test_uart_get_input_str(sg_uart_cur_num); + if ('0' == str) + { + TEST_LOG(sg_uart_cur_num, "%c\n", str); + break; + } + else if ('1' == str) + { + TEST_LOG(sg_uart_cur_num, "%c\n", str); + sg_uart_case_done = true; + return; + } + } + } +} + + +static const unit_test_entry_t sg_uart_unit_test_table[] = +{ + {"blocking case ...", test_uart_blocking}, + {"none blocking case ...", test_uart_none_blocking}, + {"dma trans case ...", test_uart_dma_transmit}, + {"end", NULL}, +}; + +#if UART_TEST_AUTO +/** +* @brief uart测试用例切换 +* @param 无 +* @retval 无 +*/ +static void test_uart_auto_case(void) +{ + for (sg_uart_case = UART_CASE_BLOCKING; sg_uart_case < UART_CASE_MAX; sg_uart_case++) + { + TEST_LOG(sg_uart_cur_num, "%s\n", sg_uart_unit_test_table[sg_uart_case].case_name); + + sg_uart_case_done = false; + + /*配置并启动定时器*/ + sg_uart_unit_test_table[sg_uart_case].case_func(); + + /*等待超时中断*/ + while (!sg_uart_case_done); + + TEST_LOG(sg_uart_cur_num, "test case pass \n"); + TEST_LOG(sg_uart_cur_num, "\n"); + } +} +#else +/** +* @brief uart测试用例切换 +* @param 无 +* @retval 无 +*/ +static void test_uart_unit_case(uint8_t case_num) +{ + TEST_LOG(sg_uart_cur_num, "%s\n", sg_uart_unit_test_table[case_num].case_name); + + sg_uart_case_done = false; + + /*配置并启动定时器*/ + sg_uart_unit_test_table[case_num].case_func(); + + /*等待超时中断*/ + while (!sg_uart_case_done); + + TEST_LOG(sg_uart_cur_num, "test case pass!!\n"); +} +#endif + +/************************************************************************** +* @name : demo_hal_uart_case +* @brief : +* @param[in] : +* @return : +* @retval : +**************************************************************************/ +void demo_hal_uart_case(void) +{ + test_uart_common_init(sg_uart_cur_num); + test_uart_mode_init(); + while (1) + { + test_uart_set_uart_mode(); + +#if UART_TEST_AUTO + test_uart_auto_case(); +#else + test_uart_unit_case(sg_uart_case); +#endif + + if (!test_uart_sel_continue()) + { + break; + } + } + TEST_LOG(sg_uart_cur_num, "uart test done!\n"); +} +#endif diff --git a/src/app/module_demo/demo_hal_uart.h b/src/app/module_demo/demo_hal_uart.h new file mode 100644 index 0000000..30dd036 --- /dev/null +++ b/src/app/module_demo/demo_hal_uart.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* Copyright (C) 2020-2023, tau Systems (R),All Rights Reserved. +* +* File: demo_hal_uart.h +* Description: hal uart测试用例头文件 +* Version: V0.1 +* Date： 2023-07-09 +* Author: kc + *******************************************************************************/ +#ifndef __DEMO_HAL_UART_H__ +#define __DEMO_HAL_UART_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "test_cfg_global.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +void demo_hal_uart_case(void); + +#endif /* __DEMO_HAL_UART_H__ */ + diff --git a/src/app/module_demo/demo_hal_wdg.c b/src/app/module_demo/demo_hal_wdg.c new file mode 100644 index 0000000..aeaa1c7 --- /dev/null +++ b/src/app/module_demo/demo_hal_wdg.c @@ -0,0 +1,135 @@ +/******************************************************************************* +* +* +* File: demo_hal_wdg.c +* Description： watch dog demo源文件 +* Version： V0.1 +* Date： 2023-07-27 +* Author： zzf + *******************************************************************************/ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "hal_wdg.h" +#include "hal_gpio.h" +#include "tau_delay.h" +#include "tau_log.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "wdg-log" + +#define WDG_CASE_RST 0 //复位模式 +#define WDG_CASE_INTR 1 //中断模式 + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ +#if WDG_CASE_INTR +static io_pad_e sg_wdg_io_pad = IO_PAD_GPIO1; +static gpio_level_e sg_wdg_io_lvl = IO_LVL_LOW; +/* 循环喂狗 */ +static uint8_t sg_feed_cnt = 0; +#endif + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +#if WDG_CASE_RST +/** +* @brief 复位模式测试 +* @param 无 +* @retval 无 +*/ +static void demo_wdg_case_rst_mode(void) +{ + TAU_LOGI("reset start...\n"); + + /* WDG初始化复位模式 */ + hal_wdg_init(); + + /* 启动 */ + hal_wdg_start(WDG_MODE_RESET, 5000); +} +#endif + +#if WDG_CASE_INTR +/** +* @brief 测试回调函数 +* @param 无 +* @retval 无 +*/ +static void demo_wdg_callback(void *data) +{ + /* 翻转GPIO */ + sg_wdg_io_lvl = (sg_wdg_io_lvl ? IO_LVL_LOW : IO_LVL_HIGH); + hal_gpio_set_output_data(sg_wdg_io_pad, sg_wdg_io_lvl); + sg_feed_cnt++; + + if (sg_feed_cnt > 10) + { + hal_wdg_stop(); + } +} + +/** +* @brief 中断模式测试 +* @param 无 +* @retval 无 +*/ +static void demo_wdg_case_int_mode(void) +{ + TAU_LOGI("int start...\n"); + + /* WDG初始化 */ + hal_wdg_init(); + + /* 设置循环超时 */ + hal_wdg_set_repeat(true); + + /* 设置回调函数 */ + hal_wdg_register_callback(demo_wdg_callback, NULL); + + /*初始化GPIO低状态*/ + hal_gpio_init_output(sg_wdg_io_pad, sg_wdg_io_lvl); + + /* 设置中断模式 */ + hal_wdg_start(WDG_MODE_INTERRUPT, 200); + + + while (sg_feed_cnt < 6) + { + sg_feed_cnt++; + hal_wdg_kick_dog(); + delayMs(150); + TAU_LOGI("feed [%d]th done\n", sg_feed_cnt); + } + +} +#endif + +/** +* @brief demo测试接口函数 +* @param None +* @retval None +*/ +void demo_wdg_case(void) +{ + TAU_LOGI("demo_wdg_case\r\n"); + +#if WDG_CASE_RST + demo_wdg_case_rst_mode(); +#elif WDG_CASE_INTR + demo_wdg_case_int_mode(); +#endif +} + diff --git a/src/app/module_demo/demo_hal_wdg.h b/src/app/module_demo/demo_hal_wdg.h new file mode 100644 index 0000000..64dd430 --- /dev/null +++ b/src/app/module_demo/demo_hal_wdg.h @@ -0,0 +1,40 @@ +/******************************************************************************* +* +* +* File: demo_hal_wdg.h +* Description: watch dog demo头文件 +* Version: V0.1 +* Date: 2023-07-27 +* Author: zzf + *******************************************************************************/ +#ifndef __DEMO_WDG_H__ +#define __DEMO_WDG_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief demo测试接口函数 +* @param None +* @retval None +*/ +void demo_wdg_case(void); + +#endif /* __DEMO_WDG_H__ */ + diff --git a/src/app/module_demo/module_demo_main.c b/src/app/module_demo/module_demo_main.c new file mode 100644 index 0000000..59b4f51 --- /dev/null +++ b/src/app/module_demo/module_demo_main.c @@ -0,0 +1,69 @@ +/******************************************************************************* +* +* File: ap_demo_main.c +* Description: ap demo main file +* Version: V0.1 +* Date: 2022-04-15 +* Author: Jaya + *******************************************************************************/ + +#include +#include +#include +#include "module_demo_main.h" + +void module_demo_main() +{ +#if _MODULE_DEMO_DSI_TX_EN + demo_dsi_tx_case(); +#endif + +#if _MODULE_DEMO_DSI_RX_EN + demo_hal_dsi_rx_case(); +#endif + +#if _MODULE_DEMO_TIMER_EN + demo_timer_case(); +#endif + +#if _MODULE_DEMO_WDG_EN + demo_wdg_case(); +#endif + +#if _MODULE_DEMO_GPIO_EN + demo_gpio_case(); +#endif + +#if _MODULE_DEMO_SWIRE_EN + demo_hal_swire(); +#endif + +#if _MODULE_DEMO_SPI_EN + demo_hal_spi(); +#endif + +#if _MODULE_DEMO_I2C_EN + demo_hal_i2c(); +#endif + +#if _MODULE_DEMO_FLASH_EN + demo_hal_flash(); +#endif + +#if _MODULE_DEMO_PWM_EN + demo_hal_pwm(); +#endif + +#if _MODULE_DEMO_PWR_EN + demo_hal_pwr(); +#endif + +#if _MODULE_DEMO_UART_EN + demo_hal_uart_case(); +#endif + +#if _MODULE_DEMO_CRC_EN + demo_hal_crc_case(); +#endif + +} diff --git a/src/app/module_demo/module_demo_main.h b/src/app/module_demo/module_demo_main.h new file mode 100644 index 0000000..a01138f --- /dev/null +++ b/src/app/module_demo/module_demo_main.h @@ -0,0 +1,68 @@ +/******************************************************************************* +* +* File: module_demo_main.h +* Description: module demo main file +* Version: V0.1 +* Date: 2023-07-27 +* Author: Jaya + *******************************************************************************/ + +#ifndef __MODULE_DEMO_MAIN_H__ +#define __MODULE_DEMO_MAIN_H__ +#include "test_cfg_global.h" + +#if _MODULE_DEMO_DSI_TX_EN +#include "demo_hal_dsi_tx.h" +#endif + +#if _MODULE_DEMO_DSI_RX_EN +#include "demo_hal_dsi_rx.h" +#endif + +#if _MODULE_DEMO_TIMER_EN +#include "demo_hal_timer.h" +#endif + +#if _MODULE_DEMO_WDG_EN +#include "demo_hal_wdg.h" +#endif + +#if _MODULE_DEMO_GPIO_EN +#include "demo_hal_gpio.h" +#endif + +#if _MODULE_DEMO_SWIRE_EN +#include "demo_hal_swire.h" +#endif + +#if _MODULE_DEMO_SPI_EN +#include "demo_hal_spi.h" +#endif + +#if _MODULE_DEMO_I2C_EN +#include "demo_hal_i2c.h" +#endif + +#if _MODULE_DEMO_FLASH_EN +#include "demo_hal_flash.h" +#endif + +#if _MODULE_DEMO_PWM_EN +#include "demo_hal_pwm.h" +#endif + +#if _MODULE_DEMO_PWR_EN +#include "demo_hal_pwr.h" +#endif + +#if _MODULE_DEMO_UART_EN +#include "demo_hal_uart.h" +#endif + +#if _MODULE_DEMO_CRC_EN +#include "demo_hal_crc.h" +#endif + +void module_demo_main(void); + +#endif /* __MODULE_DEMO_MAIN_H__ */ diff --git a/src/app/test_cfg_global.h b/src/app/test_cfg_global.h new file mode 100644 index 0000000..2d6e8f0 --- /dev/null +++ b/src/app/test_cfg_global.h @@ -0,0 +1,39 @@ +/******************************************************************************* +* +* File: test_cfg_global.h +* Description： 测试用例全局配置头文件 +* Version： V0.1 +* Date： 2021-05-01 +* Author： kevin + *******************************************************************************/ + +#ifndef __TEST_GLOBAL_CONFIG_H__ +#define __TEST_GLOBAL_CONFIG_H__ +/******************************************************************************* +* 1.Included files +*******************************************************************************/ + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +/* 模块demo 宏定义 */ +#define _MODULE_DEMO_ENABLE 0 +#define _MODULE_DEMO_TIMER_EN 0 +#define _MODULE_DEMO_DSI_TX_EN 0 +#define _MODULE_DEMO_DSI_RX_EN 0 +#define _MODULE_DEMO_PWM_EN 0 +#define _MODULE_DEMO_SWIRE_EN 0 +#define _MODULE_DEMO_WDG_EN 0 +#define _MODULE_DEMO_GPIO_EN 0 +#define _MODULE_DEMO_I2C_EN 0 +#define _MODULE_DEMO_SPI_EN 0 +#define _MODULE_DEMO_PWR_EN 0 +/* ap demo 宏定义 */ +#define _DEMO_GOOGLE_P8P_EN 1 + + +#if _DEMO_GOOGLE_P8P_EN + #include "p8p_demo.h" +#endif +#endif + diff --git a/src/board/board.c b/src/board/board.c new file mode 100644 index 0000000..ed06fd5 --- /dev/null +++ b/src/board/board.c @@ -0,0 +1,31 @@ +/******************************************************************************* +* +* +* File: board.c +* Description 板级文件 +* Version V0.1 +* Date 2023-07-23 +* Author lzy +*******************************************************************************/ +#include "board.h" +#include "hal_system.h" +#include "hal_gpio.h" +#include "ArmCM0.h" +#include "tau_log.h" + +/** +* @brief 系统板级初始化,配置系统时钟,调试log输出 +* @param none +* @retval none +*/ +void board_Init(void) +{ + /* system init ,配置MCU时钟 */ + hal_system_init(HAL_SYSCLK_80M); + + /* 使用SWD口作为Debug Log输出,可配置成Uart方式 */ + tau_log_init(115200, LOG_PORT_UART0); + + /* systick init,根据需要配置 */ + //hal_system_enable_systick(1); +} diff --git a/src/board/board.h b/src/board/board.h new file mode 100644 index 0000000..16c7b2a --- /dev/null +++ b/src/board/board.h @@ -0,0 +1,21 @@ +/******************************************************************************* +* +* +* File: board.h +* Description: baord 初始化头文件 +* Version: V0.1 +* Date: 2020-01-08 +* Author: lzy + *******************************************************************************/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +/** +* @brief 系统板级初始化,配置系统时钟,调试log输出 +* @param none +* @retval none +*/ +void board_Init(void); + +#endif diff --git a/src/board/startup/startup_ARMCM0.s b/src/board/startup/startup_ARMCM0.s new file mode 100644 index 0000000..947bb24 --- /dev/null +++ b/src/board/startup/startup_ARMCM0.s @@ -0,0 +1,226 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device +; * @version V5.4.0 +; * @date 12. December 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + + ; Interrupts + DCD VIDC_IRQn_Handler ; 0 Interrupt 0 + DCD LCDC_IRQn_Handler ; 1 Interrupt 1 + DCD MIPI_RX_IRQn_Handler ; 2 Interrupt 2 + DCD MIPI_TX_IRQn_Handler ; 3 Interrupt 3 + DCD MEMC_IRQn_Handler ; 4 Interrupt 4 + DCD VPRE_IRQn_Handler ; 5 Interrupt 5 + DCD FLSCTRL_IRQn_Handler ; 6 Interrupt 6 + DCD DMA_IRQn_Handler ; 7 Interrupt 7 + DCD TIMER0_IRQn_Handler ; 8 Interrupt 8 + DCD TIMER1_IRQn_Handler ; 9 Interrupt 9 + DCD TIMER2_IRQn_Handler ; 10 Interrupt 10 + DCD TIMER3_IRQn_Handler ; 11 Interrupt 11 + DCD WDG_IRQn_Handler ; 12 Interrupt 12 + DCD UART_IRQn_Handler ; 13 Interrupt 13 + DCD I2C0_IRQn_Handler ; 14 Interrupt 14 + DCD I2C1_IRQn_Handler ; 15 Interrupt 15 + DCD SPIS_IRQn_Handler ; 16 Interrupt 16 + DCD SPIM_IRQn_Handler ; 17 Interrupt 17 + DCD VPRE1_IRQn_Handler ; 18 Interrupt 18 + DCD I2C2_IRQn_Handler ; 19 Interrupt 19 + DCD OTP_IRQn_Handler ; 20 Interrupt 20 + DCD SWIRE_IRQn_Handler ; 21 Interrupt 21 + DCD PVD_IRQn_Handler ; 22 Interrupt 22 + DCD AP_NRESET_IRQn_Handler ; 23 Interrupt 23 + DCD EXTI_INT0_IRQn_Handler ; 24 Interrupt 24 + DCD EXTI_INT1_IRQn_Handler ; 25 Interrupt 25 + DCD EXTI_INT2_IRQn_Handler ; 26 Interrupt 26 + DCD EXTI_INT3_IRQn_Handler ; 27 Interrupt 27 + DCD EXTI_INT4_IRQn_Handler ; 28 Interrupt 28 + DCD EXTI_INT5_IRQn_Handler ; 29 Interrupt 29 + DCD EXTI_INT6_IRQn_Handler ; 30 Interrupt 30 + DCD EXTI_INT7_IRQn_Handler ; 31 Interrupt 31 + + SPACE ( 0 * 4) ; Interrupts 10 .. 31 are left out + +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors +_NVIC_ICER0 EQU 0xE000E180 ;清中断使能寄存器地址 +_NVIC_ICPR0 EQU 0xE000E280 ;清中断pending寄存器地址 + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + +;清中断使能和pending ——开始—— + CPSID I ; 屏蔽中断 + LDR R0, =_NVIC_ICER0 + LDR R1, =_NVIC_ICPR0 + LDR R2, =0xFFFFFFFF + MOVS R3, #1 ; 设置循环次数 M0只有1组(32个)中断，故只需要循环1次 +_irq_clear + ;CBZ R3, _irq_clear_end + CMP R3,#0 ; 循环次数等于0，跳转到_irq_clear_end + BNE _irq_clear_end + STR R2, [R0] ;,#4 ; NVIC_ICER0 - 清 enable IRQ 寄存器 + STR R2, [R1] ;,#4 ; NVIC_ICPR0 - 清 pending IRQ 寄存器 + SUBS R3, #1 ; 循环数自减1 + B _irq_clear +_irq_clear_end +;清中断使能和pending ——结束—— + CPSIE I ; 开启中断 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler VIDC_IRQn_Handler + Set_Default_Handler LCDC_IRQn_Handler + Set_Default_Handler MIPI_RX_IRQn_Handler + Set_Default_Handler MIPI_TX_IRQn_Handler + Set_Default_Handler MEMC_IRQn_Handler + Set_Default_Handler VPRE_IRQn_Handler + Set_Default_Handler FLSCTRL_IRQn_Handler + Set_Default_Handler DMA_IRQn_Handler + Set_Default_Handler TIMER0_IRQn_Handler + Set_Default_Handler TIMER1_IRQn_Handler + + Set_Default_Handler TIMER2_IRQn_Handler + Set_Default_Handler TIMER3_IRQn_Handler + Set_Default_Handler WDG_IRQn_Handler + Set_Default_Handler UART_IRQn_Handler + Set_Default_Handler I2C0_IRQn_Handler + Set_Default_Handler I2C1_IRQn_Handler + Set_Default_Handler SPIS_IRQn_Handler + Set_Default_Handler SPIM_IRQn_Handler + Set_Default_Handler VPRE1_IRQn_Handler + Set_Default_Handler I2C2_IRQn_Handler + + Set_Default_Handler OTP_IRQn_Handler + Set_Default_Handler SWIRE_IRQn_Handler + Set_Default_Handler PVD_IRQn_Handler + Set_Default_Handler AP_NRESET_IRQn_Handler + Set_Default_Handler EXTI_INT0_IRQn_Handler + Set_Default_Handler EXTI_INT1_IRQn_Handler + Set_Default_Handler EXTI_INT2_IRQn_Handler + Set_Default_Handler EXTI_INT3_IRQn_Handler + Set_Default_Handler EXTI_INT4_IRQn_Handler + Set_Default_Handler EXTI_INT5_IRQn_Handler + + Set_Default_Handler EXTI_INT6_IRQn_Handler + Set_Default_Handler EXTI_INT7_IRQn_Handler + ALIGN + + +; User setup Stack & Heap + + IF :LNOT::DEF:__MICROLIB + IMPORT __use_two_region_memory + ENDIF + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/src/common/tau_common.h b/src/common/tau_common.h new file mode 100644 index 0000000..48d8ac2 --- /dev/null +++ b/src/common/tau_common.h @@ -0,0 +1,222 @@ +/******************************************************************************* +* +* +* File: tau_common.h +* Description 通用数据类型相关定义头文件 +* Version V0.1 +* Date 2020-09-07 +* Author lzy + *******************************************************************************/ + +#ifndef __TAU_COMMON_H +#define __TAU_COMMON_H + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "stdint.h" +#include "math.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +/** + * \name 通用常量定义 + * @{ + */ +//#define ENABLE 1 +//#define DISABLE 0 + +#define ON 1 +#define OFF 0 + +#define NONE 0 +#define EOS '\0' + +/* +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif +*/ + +#ifndef __cplusplus +#define true 1 +#define false 0 +#define bool _Bool +#endif /* ifndef __cplusplus */ + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#define TAU_LITTLE_ENDIAN 1234 /**< \brief 小端模式 */ +#define TAU_BIG_ENDIAN 3412 /**< \brief 大端模式 */ + +/** @} */ + +/******************************************************************************/ + +/** + * \name 常用宏定义 + * @{ + */ + +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +#define TAU_INLINE inline +#define TAU_STATIC_INLINE static inline +#define TAU_STATIC static +#define TAU_CONST const +#define TAU_EXTERN extern + +#define MIN(x, y) (((x) < (y)) ? (x) : (y)) +#define MAX(x, y) (((x) > (y)) ? (x) : (y)) + +/** + * \brief 求结构体成员的偏移 + * \attention 不同平台上，由于成员大小和内存对齐等原因， + * 同一结构体成员的偏移可能是不一样的 + * + * \par 示例 + * \code + * struct my_struct { + * int m1; + * char m2; + * }; + * int offset_m2; + * + * offset_m2 = TAU_OFFSET(struct my_struct, m2); + * \endcode + */ +#define TAU_OFFSET(structure, member) ((uint32_t)(&(((structure *)0)->member))) + +/** @} */ + +/** + * \brief 通过结构体成员指针获取包含该结构体成员的结构体 + * + * \param ptr 指向结构体成员的指针 + * \param type 结构体类型 + * \param member 结构体中该成员的名称 + * + * \par 示例 + * \code + * struct my_struct = { + * int m1; + * char m2; + * }; + * struct my_struct my_st; + * char *p_m2 = &my_st.m2; + * struct my_struct *p_st = TAU_CONTAINER_OF(p_m2, struct my_struct, m2); + * \endcode + */ +#define TAU_CONTAINER_OF(ptr, type, member) \ + ((type *)((char *)(ptr)-TAU_OFFSET(type, member))) + +/** + * \brief 计算结构体成员的大小 + * + * \code + * struct a = { + * uint32_t m1; + * uint32_t m2; + * }; + * int size_m2; + * + * size_m2 = TAU_MEMBER_SIZE(a, m2); //size_m2 = 4 + * \endcode + */ +#define TAU_MEMBER_SIZE(structure, member) (sizeof(((structure *)0)->member)) + +/** + * \brief 计算数组元素个数 + * + * \code + * int a[] = {0, 1, 2, 3}; + * int element_a = TAU_NELEMENTS(a); // element_a = 4 + * \endcode + */ +#define TAU_NELEMENTS(array) (sizeof(array) / sizeof((array)[0])) + +/** + * \brief 向上舍入 + * + * \param x 被运算的数 + * \param align 对齐因素 + * + * \code + * int size = TAU_ROUND_UP(15, 4); // size = 16 + * \endcode + */ +#define TAU_ROUND_UP(x, align) (((int)(x)/(align))*(align) + (((int)(x)%(align)) ? (align) : 0)) + +/** + * \brief 向下舍入 + * + * \param x 被运算的数 + * \param align 对齐因素 + * + * \code + * int size = TAU_ROUND_DOWN(15, 4); // size = 12 + * \endcode + */ +#define TAU_ROUND_DOWN(x, align) (((int)(x)/(align))*(align)) + +/** \brief 倍数向上舍入 */ +#define TAU_DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d)) + +/** + * \brief 测试是否对齐 + * + * \param x 被运算的数 + * \param align 对齐因素，必须为2的乘方 + * + * \code + * if (TAU_ALIGNED(x, 4) { + * ; // x对齐 + * } else { + * ; // x不对齐 + * } + * \endcode + */ +#define TAU_ALIGNED(x, align) (((int)(x) & (align - 1)) == 0) + +/** \brief 将1字节BCD数据转换为16进制数据 */ +#define TAU_BCD_TO_HEX(val) (((val)&0x0f) + ((val) >> 4) * 10) + +/** \brief 将1字节16进制数据转换为BCD数据 */ +#define TAU_HEX_TO_BCD(val) ((((val) / 10) << 4) + (val) % 10) + +/** + * \brief 向上取整 + */ +#define TAU_CEIL(val) ceil(val) + + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +/*!< @brief 用于返回状态和错误 */ +typedef uint32_t status_t; + +/* \brief 通用回调函数指针定义 */ +typedef void (*fcb_type)(void *data); + +typedef void (*uart_trans_cb)(status_t status, void *user_data); + +typedef void (*flash_trans_cb)(status_t status, void *user_data); +#endif /* __TAU_COMMON_H */ diff --git a/src/common/tau_delay.h b/src/common/tau_delay.h new file mode 100644 index 0000000..b4a64ca --- /dev/null +++ b/src/common/tau_delay.h @@ -0,0 +1,34 @@ +/** + * File Name: tau_delay.h + * + * + * + * Author: Fortsense 3D Firmware Team + * + * Date: 2020/12/04 + * + * Project: Taurus + * + * Description: + * + * HISTORY: +**/ +#ifndef _DELAY_H_ +#define _DELAY_H_ +#include "stdint.h" + +/** +* @brief delay ms 函数,误差2%以内 +* @param ms:delay时长 +* @retval none +*/ +void delayMs(uint32_t ms); + +/** +* @brief delay us 函数,误差2%以内 +* @param us:delay时长 +* @retval none +*/ +void delayUs(uint32_t us); + +#endif diff --git a/src/common/tau_device_datatype.h b/src/common/tau_device_datatype.h new file mode 100644 index 0000000..bfce3bc --- /dev/null +++ b/src/common/tau_device_datatype.h @@ -0,0 +1,229 @@ +/******************************************************************************* + * + * + * File: tau_device_datatype.h + * Description device datatype + * Version V0.1 + * Date 2020-12-04 + * Author kevin + *******************************************************************************/ + +#ifndef _TAU_DEVICE_DATATYPE_H_ +#define _TAU_DEVICE_DATATYPE_H_ + + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ + +#include "stdint.h" +#include "tau_common.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +/*! @brief 计算组状态码 */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +/*! @brief 分组状态值 */ +enum _status_groups +{ + STATUS_GROUP_GENERIC = 0, + STATUS_GROUP_I2C = 1, + STATUS_GROUP_UART = 2, + STATUS_GROUP_SPI = 3, + STATUS_GROUP_TIMER = 4, +}; + +/*! @brief 常用状态码 */ +enum _generic_status +{ + STATUS_SUCCESS = MAKE_STATUS(STATUS_GROUP_GENERIC, 0), + STATUS_FAIL = MAKE_STATUS(STATUS_GROUP_GENERIC, 1), + STATUS_READ_ONLY = MAKE_STATUS(STATUS_GROUP_GENERIC, 2), + STATUS_OUT_OF_RANGE = MAKE_STATUS(STATUS_GROUP_GENERIC, 3), + STATUS_INVALID_ARGUMENT = MAKE_STATUS(STATUS_GROUP_GENERIC, 4), + STATUS_TIME_OUT = MAKE_STATUS(STATUS_GROUP_GENERIC, 5), + STATUS_NO_TRANSFER_IN_PROGRESS = MAKE_STATUS(STATUS_GROUP_GENERIC, 6), +}; + +/** +* @brief UART状态枚举定义 +* +*/ +typedef enum +{ + STATUS_UART_TX_BUSY = MAKE_STATUS(STATUS_GROUP_UART, 0), /*!< Transmitter is busy. */ + STATUS_UART_RX_BUSY = MAKE_STATUS(STATUS_GROUP_UART, 1), /*!< Receiver is busy. */ + STATUS_UART_TX_IDLE = MAKE_STATUS(STATUS_GROUP_UART, 2), /*!< USART transmitter is idle. */ + STATUS_UART_RX_IDLE = MAKE_STATUS(STATUS_GROUP_UART, 3), /*!< USART receiver is idle. */ + STATUS_UART_TX_ERR = MAKE_STATUS(STATUS_GROUP_UART, 7), /*!< Error happens on txFIFO. */ + STATUS_UART_RX_ERR = MAKE_STATUS(STATUS_GROUP_UART, 9), /*!< Error happens on rxFIFO. */ + STATUS_UART_RX_RING_BUFF_OVERRUN = MAKE_STATUS(STATUS_GROUP_UART, 8), /*!< Error happens on rx ring buffer */ + STATUS_UART_NOISE_ERR = MAKE_STATUS(STATUS_GROUP_UART, 10), /*!< USART noise error. */ + STATUS_UART_FRAMING_ERR = MAKE_STATUS(STATUS_GROUP_UART, 11), /*!< USART framing error. */ + STATUS_UART_PARITY_ERR = MAKE_STATUS(STATUS_GROUP_UART, 12), /*!< USART parity error. */ + STATUS_UART_BAUDRATE_NOT_SPT = MAKE_STATUS(STATUS_GROUP_UART, 13), /*!< Baudrate is not support in current clock source */ +} uart_status_e; + +/*! + * @brief timer状态 + */ +typedef enum +{ + STATUS_TIMER_IDLE = MAKE_STATUS(STATUS_GROUP_TIMER, 0), /*!< 空闲 */ + STATUS_TIMER_RUNNING = MAKE_STATUS(STATUS_GROUP_TIMER, 1), /*!< 运行中 */ + STATUS_TIMER_TIMEOUT = MAKE_STATUS(STATUS_GROUP_TIMER, 2), /*!< 超时 */ +} timer_status_e; + +/*! + * @brief system触发事件(中断/复位)模式 + */ +typedef enum +{ + DETECT_HIGH_LVL = 0, + DETECT_LOW_LVL, + DETECT_RISING_EDGE, + DETECT_FALLING_EDGE, + DETECT_DOUBLE_EDGE +} sys_cfg_trigger_e; + +/** +* @brief GPIO interrupt type +*/ +typedef enum +{ + TIMER_NUM0 = 0, + TIMER_NUM1, + TIMER_NUM2, + TIMER_NUM3, + TIMER_NUM_MAX +} timer_num_e; + +/** +* @brief GPIO interrupt type +*/ +typedef enum +{ + GPIO_INT_EXTI_INT0 = 0, + GPIO_INT_EXTI_INT1, + GPIO_INT_EXTI_INT2, + GPIO_INT_EXTI_INT3, + GPIO_INT_EXTI_INT4, + GPIO_INT_EXTI_INT5, + GPIO_INT_EXTI_INT6, + GPIO_INT_EXTI_INT7, + GPIO_INT_MAX +} gpio_int_e; + +/*! @brief PWMI中断类型 */ +typedef enum _pwm_int_type +{ + PWM_INT_HIGH_OVERFLOW = 0, + PWM_INT_LOW_OVERFLOW, + PWM_INT_TOTAL_OVERFLOW, + PWM_INT_HIGH_DONE, + PWM_INT_LOW_DONE, + PWM_INT_TOTAL_DONE, + PWM_INT_MAX +} pwm_int_type_e; + +/** +* @brief I2C chose +*/ +typedef enum +{ + I2C_SELECT_0 = 0, //常用slave + I2C_SELECT_1, //常用master +} i2c_select_e; + +/*! + * @brief 传输速度 + * @note + */ +typedef enum _i2c_rate +{ + I2C_RATE_STANDARD = 1, //100kHz + I2C_RATE_FAST, //400kHz + I2C_RATE_HIGH, //1MHz +} i2c_rate_e; + +/*! + * @brief I2C Index + * @note + */ +typedef enum +{ + I2C_INDEX_0, + I2C_INDEX_1, + I2C_INDEX_2, + I2C_INDEX_MAX +} i2c_index_e; + +/*! + * @brief DMA channel type + * @note + */ +typedef enum +{ + AHB_DMA_CH0, + AHB_DMA_CH1, + AHB_DMA_CH2, + AHB_DMA_CH3, + AHB_DMA_CH4, + AHB_DMA_CH5, + AHB_DMA_CH6, + AHB_DMA_CH7, + AHB_DMA_CH_NUM +} dma_channel_type_e; + +/*! @brief Type used for all status and error return values. */ + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} function_state_e; + +/** +* @brief The reversal types of the bit order of the input/output data +*/ +typedef enum +{ + CRC_REV_NO_TRANSPOSE = 0, /*!< No transposition */ + CRC_REV_ONLY_BITS_TRANSPOSE, /*!< Bits in bytes are transposed; bytes are not transposed */ + CRC_REV_BOTH_TRANSPOSE, /*!< Both bits in bytes and bytes are transposed */ + CRC_REV_ONLY_BYTES_TRANSPOSE, /*!< Only bytes are transposed; no bits in a byte are transposed */ +} crc_reversal_type_e; + +/** +* @brief Complement Read Of CRC Data Register +*/ +typedef enum +{ + CRC_FXOR_DISABLE = 0, /*!< No XOR on reading */ + CRC_FXOR_ENABLE, /*!< Invert or complement the read value of the CRC Data register */ +} crc_fxor_function_e; + +/** +* @brief width of CRC protocol (polynomial) +*/ +typedef enum +{ + CRC_16_BIT_PROTOCOL = 0, /*!< 0: 16-bit CRC protocol */ + CRC_32_BIT_PROTOCOL, /*!< 1: 32-bit CRC protocol */ +} crc_protocol_type_e; + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +#endif + diff --git a/src/common/tau_dsi_datatype.h b/src/common/tau_dsi_datatype.h new file mode 100644 index 0000000..fb301c9 --- /dev/null +++ b/src/common/tau_dsi_datatype.h @@ -0,0 +1,405 @@ +/******************************************************************************* +* +* +* File: tau_dsi_datatype.h +* Description: mipi dsi 通用头文件 +* Version: V0.1 +* Date: 2021-01-13 +* Author: lzy + *******************************************************************************/ + +#ifndef __MIPI_DSI_COMMON_H__ +#define __MIPI_DSI_COMMON_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_common.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#define DSC_PPS_SIZE 128 + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +/** +* @brief Data Types for Peripheral-sourced Packets,From Mipi DSI Spec +*/ +typedef enum +{ + DSI_ACK_DT_ERROR = 0x02, + DSI_ACK_DT_EOTP = 0x08, + DSI_ACK_DT_GEN_SHORT_RESPONSE_1B = 0x11, + DSI_ACK_DT_GEN_SHORT_RESPONSE_2B = 0x12, + DSI_ACK_DT_GEN_LONG_RESPONSE = 0x1A, + DSI_ACK_DT_DCS_LONG_RESPONSE = 0x1C, + DSI_ACK_DT_DCS_SHORT_RESPONSE_1B = 0x21, + DSI_ACK_DT_DCS_SHORT_RESPONSE_2B = 0x22, + DSI_ACK_DT_MAX +} dsi_ack_data_type_e; + +/** +* @brief Software handle data types +*/ +typedef enum +{ + DSI_RECV_DT_PPS = 0x0A, //Picture Parameter Set + DSI_RECV_DT_GEN_WRITE_1B = 0x13, //Generic Short WRITE, 1 parameter + DSI_RECV_DT_GEN_WRITE_2B = 0x23, //Generic Short WRITE, 2 parameters + DSI_RECV_DT_GEN_READ_0B = 0x04, //Generic READ, no parameters + DSI_RECV_DT_GEN_READ_1B = 0x14, //Generic READ, 1 parameter + DSI_RECV_DT_GEN_READ_2B = 0x24, //Generic READ, 2 parameters + DSI_RECV_DT_DCS_WRITE_0B = 0x05, //DCS Short WRITE, no parameters + DSI_RECV_DT_DCS_WRITE_1B = 0x15, //DCS Short WRITE, 1 parameter + DSI_RECV_DT_DCS_READ_0B = 0x06, //DCS READ, no parameters + DSI_RECV_DT_GEN_WRITE_LONG = 0x29, //Generic Long Write + DSI_RECV_DT_DCS_WRITE_LONG = 0x39, //DCS Long Write/write_LUT Command Packet + DSI_RECV_DT_MAX +} dsi_data_type_e; + +typedef enum +{ + DCS_ENTER_IDLE_MODE = 0x39, + DCS_ENTER_INVERT_MODE = 0x21, + DCS_ENTER_NORMAL_MODE = 0x13, + DCS_ENTER_PARTIAL_MODE = 0x12, + DCS_ENTER_SLEEP_MODE = 0x10, + DCS_EXIT_IDLE_MODE = 0x38, + DCS_EXIT_INVERT_MODE = 0x20, + DCS_EXIT_SLEEP_MODE = 0x11, + DCS_GET_3D_CONTROL = 0x3F, + DCS_GET_ADDRESS_MODE = 0x0B, + DCS_GET_BLUE_CHANNEL = 0x08, + DCS_GET_COMPRESSION_MODE = 0x03, + DCS_GET_DIAGNOSTIC_RESULT = 0x0F, + DCS_GET_DISPLAY_MODE = 0x0D, + DCS_GET_GREEN_CHANNEL = 0x07, + DCS_GET_PIXEL_FORMAT = 0x0C, + DCS_GET_POWER_MODE = 0x0A, + DCS_GET_RED_CHANNEL = 0x06, + DCS_GET_SCANLINE = 0x45, + DCS_GET_SIGNAL_MODE = 0x0E, + DCS_NOP = 0x00, + DCS_READ_DDB_CONTINUE = 0xA8, + DCS_READ_DDB_START = 0xA1, + DCS_READ_MEMORY_CONTINUE = 0x3E, + DCS_READ_MEMORY_START = 0x2E, + DCS_SET_3D_CONTROL = 0x3D, + DCS_SET_ADDRESS_MODE = 0x36, + DCS_SET_COLUMN_ADDRESS = 0x2A, + DCS_SET_DISPLAY_OFF = 0x28, + DCS_SET_DISPLAY_ON = 0x29, + DCS_SET_GAMMA_CURVE = 0x26, + DCS_SET_PAGE_ADDRESS = 0x2B, + DCS_SET_PARTIAL_COLUMNS = 0x31, + DCS_SET_PARTIAL_ROWS = 0x30, + DCS_SET_PIXEL_FORMAT = 0x3A, + DCS_SET_SCROLL_AREA = 0x33, + DCS_SET_SCROLL_START = 0x37, + DCS_SET_TEAR_OFF = 0x34, + DCS_SET_TEAR_ON = 0x35, + DCS_SET_TEAR_SCANLINE = 0x44, + DCS_SET_VSYNC_TIMING = 0x40, + DCS_SOFT_RESET = 0x01, + DCS_WRITE_LUT = 0x2D, + DCS_WRITE_MEMORY_CONTINUE = 0x3C, + DCS_WRITE_MEMORY_START = 0x2C +} dsi_dcs_cmd_type_e; + +/** +* @brief video data transfer mode +*/ +typedef enum +{ + DSI_DATA_VIDEO_MODE = 0, + DSI_DATA_CMD_MODE = 1, + DSI_DATA_MODE_MAX +} dsi_video_data_mode_e; + +/** +* @brief dsi virtual channel +*/ +typedef enum +{ + DSI_VC_0 = 0, + DSI_VC_1 = 1, + DSI_VC_2 = 2, + DSI_VC_3 = 3, + DSI_VC_MAX +} dsi_virtual_channel_e; + +/** +* @brief video data mode +*/ +typedef enum +{ + DSI_FRAME_RATE_60HZ = 0, + DSI_FRAME_RATE_90HZ = 1, + DSI_FRAME_RATE_120HZ = 2, + DSI_FRAME_RATE_144HZ = 3, + DSI_FRAME_RATE_160HZ = 4, + DSI_FRAME_RATE_MAX +} dsi_video_frame_rate_e; + +/** +* @brief dsi rx color coding +*/ +typedef enum +{ + DSI_RGB565 = 1, + DSI_RGB666 = 2, /*!< 18 bbp(18bits per pixel) */ + DSI_RGB666_LOOSELY = 3, /*!< 24 bbp(24bits per pixel) */ + DSI_RGB888 = 4, /*!< 24 bbp(24bits per pixel) */ + DSI_RGB10_10_10 = 5, + DSI_RGB12_12_12 = 6, + DSI_YCbCr422_16 = 7, + DSI_PENTILE_16 = DSI_YCbCr422_16, + DSI_YCbCr422_20_LOOSELY = 8, + DSI_YCbCr422_24 = 9, + DSI_YCbCr420_12 = 10, + DSI_DSC_STREAM = 11, + DSI_COLOR_CODE_MAX +} dsi_color_code_e; + +/** +* @brief dsi endianness type +*/ +typedef enum +{ + DPI_ENDIAN_RGB = 0, + DPI_ENDIAN_BGR +} dsi_endianness_e; + +/** +* @brief mipi lane number +*/ +typedef enum +{ + DSI_LANE_1 = 1, + DSI_LANE_2 = 2, + DSI_LANE_3 = 3, + DSI_LANE_4 = 4, + DSI_LANE_NUME_MAX +} dsi_lane_nume_e; + +/** +* @brief video mode +*/ +typedef enum +{ + DSI_NONBURST_PULSE = 0, + DSI_NONBURST_EVENT = 1, + DSI_BURST_MODE = 2, + DSI_VIDEO_MODE_MAX +} dsi_video_mode_type_e; + +/** +* @brief panel init cmd transfer type +*/ +typedef enum +{ + DSI_CMD_TX_HS = 0, + DSI_CMD_TX_LP = 1 +} dsi_tx_cmd_tx_type_e; + +/** +* @brief angle of rotation +*/ +typedef enum +{ + VIDOE_ROT_ANGLE_0 = 0, /* 不旋转 */ + VIDOE_ROT_ANGLE_90 = 1, /* 旋转90度 */ + VIDOE_ROT_ANGLE_180 = 2, /* 旋转180度 */ + VIDOE_ROT_ANGLE_270 = 3, /* 转转270度 */ + VIDOE_ROT_ANGLE_MAX +} video_rotate_angle_e; + +/** +* @brief mipi rx lane swap +软件配置 PIN28&PIN27 PIN26&PIN25 PIN24&PIN23 PIN22&PIN21 PIN20&PIN19 +RX_LANE_SWAP_0123 D0P&D0N D1P&D1N CLKP&CLKN D2P&D2N D3P&D3N +RX_LANE_SWAP_3210 D3P&D3N D2P&D2N CLKP&CLKN D1P&D1N D0P&D0N +RX_LANE_SWAP_2103(default) D2P&D2N D1P&D1N CLKP&CLKN D0P&D0N D3P&D3N +RX_LANE_SWAP_3012 D3P&D3N D0P&D0N CLKP&CLKN D1P&D1N D2P&D2N +*/ +typedef enum +{ + RX_LANE_SWAP_0123 = 0x0, + RX_LANE_SWAP_3210 = 0x1, + RX_LANE_SWAP_2103 = 0x2, + RX_LANE_SWAP_DEFAULT_ORDER = 0x2, /* 默认原理图为2103顺序 */ + RX_LANE_SWAP_3012 = 0x3, + RX_LANE_SWAP_MAX +} dsi_rx_lane_swap_e; + +/** +* @brief mipi P/N lane swap flag +* eg: pn_swap = RX_LANE_0_PN_SWAP | RX_LANE_CLK_PN_SWAP; +* 表示 lane0 与 CLK 的P跟N交换，其他lane不变。 +* 注意这里的lane表示的是进行完lane swap的lane,如lane swap配置RX_LANE_SWAP_3012,再配置RX_LANE_0_PN_SWAP则表示PIN26&PIN25进行PN交换,由D0P&D0N变成D0N&D0P +*/ +typedef enum +{ + RX_LANE_0_PN_SWAP = 0x1, + RX_LANE_1_PN_SWAP = 0x2, + RX_LANE_2_PN_SWAP = 0x4, + RX_LANE_3_PN_SWAP = 0x8, + RX_LANE_CLK_PN_SWAP = 0x10 +} dsi_rx_lane_pn_swap_e; + +/** +* @brief error processing level +*/ +typedef enum +{ + ERR_HANDLE_NONE = 0, + ERR_HANDLE_L1 = 1, + ERR_HANDLE_L2 = 2, + ERR_HANDLE_L3 = 3, + ERR_HANDLE_MAX +} hal_err_handle_level_e; + +/** +* @brief flow control mode +*/ +typedef enum +{ + FC_AUTO_MODE = 0, /* 自动匹配模式,根据base info配置匹配1-4 */ + FC_V2V_NORMAL_MODE = 1, /* Video to Video 模式转换 */ + FC_V2C_NORMAL_MODE = 2, /* Video to Command 模式转换 */ + FC_C2V_NORMAL_MODE = 3, /* Command to Video 模式转换 */ + FC_C2C_NORMAL_MODE = 4, /* Command to Command 模式转换 */ + FC_PRO_MOTION_MODE = 6, /* 自适应帧率转换(LTPO模式) */ + FC_PRO_MOTION_MODE_2 = 5, /* 自适应帧率转换(LTPO模式) */ + FC_PRO_MOTION_WITH_PU_MODE = 7, /* 自适应帧率带PU */ + FC_V2V_AUTO_SYCN_MODE = 8, /* Video to Video 软件同步 */ + FC_V2V_DIRECT_MODE = 9, /* Video to Video 直通模式 */ + FC_MODE_MAX +} flow_control_mode_e; + +/** +* @brief transform 基本信息 +*/ +typedef struct +{ + uint16_t top; + uint16_t bottom; + uint16_t left; + uint16_t right; + bool enable; +} pic_edge_info_t; + +/** +* @brief transform 基本信息 +*/ +typedef struct +{ + uint32_t src_w; /* mipi rx 接收的 width */ + uint32_t src_h; /* mipi rx 接收的 height */ + uint32_t dst_w; /* mipi tx 发送的 width */ + uint32_t dst_h; /* mipi tx 发送的 height */ + dsi_video_frame_rate_e src_frate; /* mipi rx 接收的frame rate */ + dsi_video_data_mode_e src_mode; /* mipi rx 接收video 数据传输模式(video/cmd mode) */ + dsi_video_data_mode_e dst_mode; /* mipi tx 输出video 数据传输模式(video/cmd mode) */ + uint16_t pn_swap; /* mipi P/N swap标志位, rx可配置/tx暂不支持 */ +} dsi_base_trans_info_t; + +/** +* @brief transform 基本信息 +*/ +typedef struct +{ + bool mirror_en; /* 对video 做水平镜像标志位 */ + bool pu_optimize; /* 用于优化PU显示效果，默认为false;true:优化PU显示显示效果,高功耗;false:普通PU模式,低功耗 */ + video_rotate_angle_e rot_angle; /* 对video 做旋转的角度 */ + flow_control_mode_e flow_control_mode; /* 图像数据流控制模式 */ + pic_edge_info_t crop_info; /* 图像边缘裁剪配置 not impletmented */ + pic_edge_info_t blank_info; /* 图像边缘补黑配置 not impletmented */ + bool bw_optimize; /* 带宽自动检查,默认打开 */ + uint8_t pq_type; /* picture quality,参数为 pq_type_e */ +} dsi_base_extra_info_t; + +/** +* @brief ccm系数 +*/ +typedef struct +{ + uint32_t coef_c00; + uint32_t coef_c01; + uint32_t coef_c02; + uint32_t coef_c10; + uint32_t coef_c11; + uint32_t coef_c12; + uint32_t coef_c20; + uint32_t coef_c21; + uint32_t coef_c22; +} ccm_coef_t; + +/** +* @brief hight performan mode level +*/ +typedef enum +{ + HIGHT_PERFORMAN_NONE = 0, + HIGHT_PERFORMAN_L1 = 1, + HIGHT_PERFORMAN_L2 = 2, + HIGHT_PERFORMAN_MAX +} hight_performan_mode_e; + +/** +* @brief TX False color去伪彩参数结构体 +*/ +typedef struct +{ + uint16_t edgemedslope; + uint16_t desatslope; +} dsi_tx_fc_t; + +/** +* @brief TX 边缘增强参数结构体 +*/ +typedef struct +{ + bool y_enh_method; + uint8_t enhance_str; + uint16_t enhance_slope; + uint16_t boundscale_low; + uint16_t boundscale_high; +} dsi_tx_edge_enh_t; + +/** +* @brief TX 边缘检测参数结构体 +*/ +typedef struct +{ + uint8_t edge_thr; + bool use_large_kernel; +} dsi_tx_edge_dect_t; + +/** +* @brief TX bcsa 参数结构体 +*/ +typedef struct +{ + int8_t brightness; /* 亮度调整, 范围-127 - 127 */ + uint16_t contrast; /* 对比度调整,范围0 - 4095 */ + uint16_t saturation; /* 饱和度调整,范围0 - 4095 */ +} dsi_tx_bcs_t; + +/** +* @brief partial display 参数结构体 +*/ +typedef struct +{ + uint32_t st_line; /*部分显示起始行位置*/ + uint32_t st_col; /*部分显示起始列位置*/ + uint32_t end_line; /*部分显示结束行位置*/ + uint32_t end_col; /*部分显示结束列位置*/ + uint8_t value_r; /*部分显示背景色R值*/ + uint8_t value_g; /*部分显示背景色G值*/ + uint8_t value_b; /*部分显示背景色B值*/ +} dsi_tx_par_dis_t; + +#endif //__MIPI_DSI_COMMON_H__ diff --git a/src/common/tau_log.h b/src/common/tau_log.h new file mode 100644 index 0000000..15e94a8 --- /dev/null +++ b/src/common/tau_log.h @@ -0,0 +1,100 @@ +/******************************************************************************* +* +* +* File: tau_log.h +* Description log file +* Version V0.1 +* Date 2020-12-08 +* Author linyw +*******************************************************************************/ +#ifndef _TAU_LOG_H_ +#define _TAU_LOG_H_ + + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include +#include +#include +#include "ArmCM0.h" +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +#ifdef LOG_TAG +#undef LOG_TAG +#endif +#define LOG_TAG "tau_log" +#define LOG_CURREN_LEVEL kLOG_LEVEL_DBG /* 配置打印等级 TODO:每个模块可配置打印等级 */ +#define LOG_BUF_SIZE (256) /* 配置打印缓存的大小 */ + +/* + * Using the following three macros for conveniently logging. + */ +#define TAU_LOGD(format,...) \ + do { \ + tau_log_printf(kLOG_LEVEL_DBG, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); \ + } while (0) + +#define TAU_LOGI(format,...) \ + do { \ + tau_log_printf(kLOG_LEVEL_INF, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); \ + } while (0) + +#define TAU_LOGE(format,...) \ + do { \ + tau_log_printf(kLOG_LEVEL_ERR, "[%s] (%04d) " format, LOG_TAG, __LINE__, ##__VA_ARGS__); \ + } while (0) + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +/** +* @brief log打印等级枚举 +* +*/ +typedef enum +{ + kLOG_LEVEL_DBG = 0, + kLOG_LEVEL_INF, + kLOG_LEVEL_ERR, + kLOG_LEVEL_NONE /* 不打印任何参数 */ +} log_level_e; + +/** +* @brief log打印端口枚举 +* +*/ +typedef enum +{ + LOG_PORT_UART0, /* 使用串口输出打印 */ + LOG_PORT_UART1, /* 使用串口输出打印 */ + LOG_PORT_SWD, /* 使用swd输出打印 */ + LOG_PORT_UNKNOWN +} log_port_e; + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief 初始化log系统 +* @param baud_rate 波特率 +* @param log_port 打印端口选择 +* @retval none +*/ +void tau_log_init(uint32_t baud_rate, log_port_e log_port); + +/** +* @brief 初始化log系统 +* @param baud_rate 波特率 +* @param log_port 打印端口选择 +* @retval none +*/ +void tau_log_printf(log_level_e log_lv, const char *fmt, ...); + +#endif diff --git a/src/common/tau_operations.h b/src/common/tau_operations.h new file mode 100644 index 0000000..c7b2ba3 --- /dev/null +++ b/src/common/tau_operations.h @@ -0,0 +1,229 @@ +/******************************************************************************* +* +* +* File: tau_operations.h +* Description 位操作与字节操作相关定义头文件 +* Version V0.1 +* Date 2020-09-07 +* Author lzy + *******************************************************************************/ +#ifndef __TAU_BYTEOPS_H +#define __TAU_BYTEOPS_H + +/** + * \name 通用位常数定义 + * @{ + */ + +/** \brief 长整数位数 */ +#ifndef TAU_BITS_PER_LONG +#define TAU_BITS_PER_LONG 32 +#endif + +/** \brief 字节位数 */ +#define TAU_BITS_PER_BYTE 8 + +/** @} */ + + +/******************************************************************************/ + +/** + * \name 通用位操作 + * @{ + */ + +/** \brief bit移位 + * TAU_BIT(2) is 0x4 + */ +#define TAU_BIT(bit) (1u << (bit)) + +/** \brief 值移位 + * TAU_SBF(0xFF, 8) is 0xff00 + */ +#define TAU_SBF(value, field) ((value) << (field)) + +/** \brief bit置位 + * TAU_BIT_SET(0, 8) is 0x100 + */ +#define TAU_BIT_SET(data, bit) ((data) |= TAU_BIT(bit)) + +/** \brief bit清零 + * TAU_BIT_CLR(0xFF, 2) is 0xfb + */ +#define TAU_BIT_CLR(data, bit) ((data) &= ~TAU_BIT(bit)) + +/** \brief bit置位, 根据 mask 指定的位 + * TAU_BIT_SET_MASK(0xF0F0, 0xF00) is 0xfff0 + */ +#define TAU_BIT_SET_MASK(data, mask) ((data) |= (mask)) + +/** \brief bit清零, 根据 mask 指定的位 + * TAU_BIT_CLR_MASK(0xFFFF, 0xFF00) is 0xff + */ +#define TAU_BIT_CLR_MASK(data, mask) ((data) &= ~(mask)) + +/** \brief bit翻转 + * TAU_BIT_TOGGLE(0xFFFF, 0) is 0xfffe + * TAU_BIT_TOGGLE(0x0000, 1) is 0x2 + */ +#define TAU_BIT_TOGGLE(data, bit) ((data) ^= TAU_BIT(bit)) + +/** \brief bit修改 + * TAU_BIT_MODIFY(0, 8, 1) is 0x100 + * TAU_BIT_MODIFY(0xFFFF, 1, 0) is 0xfffd + */ +#define TAU_BIT_MODIFY(data, bit, value) \ + ((value) ? TAU_BIT_SET(data, bit) : TAU_BIT_CLR(data, bit)) + +/** \brief 测试bit是否置位 + * TAU_BIT_ISSET(0xF0F1, 1) is 0 + * TAU_BIT_ISSET(0xF0F2, 1) is 2 + */ +#define TAU_BIT_ISSET(data, bit) ((data) & TAU_BIT(bit)) + +/** \brief 获取bit值 + * TAU_BIT_GET(0xF0F1, 1) is 0 + * TAU_BIT_GET(0xF0F2, 1) is 1 + */ +#define TAU_BIT_GET(data, bit) (TAU_BIT_ISSET(data, bit) ? 1 : 0) + +/** \brief 检测bit值 + * TAU_BIT_CHECK(0xF5FF, 4) is 1 + */ +#define TAU_BIT_CHECK(data, bit) \ + (((data) & TAU_BIT(bit)) ? 1 : 0) + +/** \brief 获取 n bits 掩码值 + * TAU_BITS_MASK(2) is 0x3 + */ +#define TAU_BITS_MASK(n) (~((~0u) << (n))) + +/** \brief 获取位段值 + * TAU_BITS_GET(0xF5FF, 0x0F00, 8) is 0x5 + */ +#define TAU_BITS_GET(data, mask, pos) \ + (((data) & (mask)) >> (pos)) + +/** \brief 获取位段值 + * TAU_BITS_CHECK(0xF5FF, 0x0F00) is 1 + */ +#define TAU_BITS_CHECK(data, mask) \ + (((data) & (mask)) ? 1 : 0) + +/** \brief 修改位段值 + * TAU_BITS_MODIFY(0xF5FF, 0x0FF0, 0x8A0) is 0xF8AF +*/ +#define TAU_BITS_MODIFY(data, clear_mask, set_mask) \ + (data) = (((data) & (~(clear_mask))) | (set_mask)) + +/** \brief 设置位段值 + * TAU_WRITE_REG32(0x05FF, 0xFFFA) is 0xFFFA +*/ +#define TAU_WRITE_REG32(data, value) ((data) = (value)) + +/** \brief 设置位段值 + * TAU_RAED_REG32(0x05FF) is 0x05FF +*/ +#define TAU_RAED_REG32(data) (data) + + +/** @} */ + +/******************************************************************************/ + +/** + * \brief 取2-byte整数的高位byte + * + * \par 示例 + * \code + * uint16_t a = 0x1234; + * uint16_t b; + * + * b = TAU_MSB(a); //b=0x12 + * \endcode + */ +#define TAU_MSB(x) (((x) >> 8) & 0xff) + +/** + * \brief 取2-byte整数的低位byte + * + * \par 示例 + * \code + * uint16_t a = 0x1234; + * uint16_t b; + * + * b = TAU_LSB(a); //b=0x34 + * \endcode + */ +#define TAU_LSB(x) ((x) & 0xff) + +/** + * \brief 取2-word整数的高位word + * + * \par 示例 + * \code + * uint32_t a = 0x12345678; + * uint32_t b; + * + * b = TAU_MSW(a); //b=0x1234 + * \endcode + */ +#define TAU_MSW(x) (((x) >> 16) & 0xffff) + +/** + * \brief 取2-word整数的低位word + * + * \par 示例 + * \code + * uint32_t a = 0x12345678; + * uint32_t b; + * + * b = TAU_LSW(a); //b=0x5678 + * \endcode + */ +#define TAU_LSW(x) ((x) & 0xffff) + +/** + * \brief 交换32-bit整数的高位word和低位word + * + * \par 示例 + * \code + * uint32_t a = 0x12345678; + * uint32_t b; + * + * b = TAU_WORDSWAP(a); //b=0x56781234 + * \endcode + */ +#define TAU_WORDSWAP(x) (TAU_MSW(x) | (TAU_LSW(x) << 16)) + +/** + * \brief 交换32-bit整数的字节顺序 + * + * \par 示例 + * \code + * uint32_t a = 0x12345678; + * uint32_t b; + * + * b = TAU_LONGSWAP(a); //b=0x78563412 + * \endcode + */ +#define TAU_LONGSWAP(x) ((TAU_LLSB(x) << 24) | \ + (TAU_LNLSB(x) << 16) | \ + (TAU_LNMSB(x) << 8) | \ + (TAU_LMSB(x))) + +#define TAU_LLSB(x) ((x) & 0xff) /**< \brief 取32bit整数第1个字节 */ +#define TAU_LNLSB(x) (((x) >> 8) & 0xff) /**< \brief 取32bit整数第2个字节 */ +#define TAU_LNMSB(x) (((x) >> 16) & 0xff) /**< \brief 取32bit整数第3个字节 */ +#define TAU_LMSB(x) (((x) >> 24) & 0xff) /**< \brief 取32bit整数第4个字节 */ +#define TAU_LNSB(x,n) (((x) >> ((n) * 8) ) & 0xff) /**< \brief 取32bit整数第n个字节 ,参数 0 - 3*/ + +/** + * @} + */ + +#endif /* __TAU_BYTEOPS_H */ + +/* end of file */ + diff --git a/src/sdk/CVWL468/lib/CVWL468.lib b/src/sdk/CVWL468/lib/CVWL468.lib new file mode 100644 index 0000000..db7f8bc Binary files /dev/null and b/src/sdk/CVWL468/lib/CVWL468.lib differ diff --git a/src/sdk/CVWL668/lib/CVWL668.lib b/src/sdk/CVWL668/lib/CVWL668.lib new file mode 100644 index 0000000..8224cc3 Binary files /dev/null and b/src/sdk/CVWL668/lib/CVWL668.lib differ diff --git a/src/sdk/CVWL668T/lib/CVWL668T.lib b/src/sdk/CVWL668T/lib/CVWL668T.lib new file mode 100644 index 0000000..e27af89 Binary files /dev/null and b/src/sdk/CVWL668T/lib/CVWL668T.lib differ diff --git a/src/sdk/include/M0/ArmCM0.h b/src/sdk/include/M0/ArmCM0.h new file mode 100644 index 0000000..5cf8fc1 --- /dev/null +++ b/src/sdk/include/M0/ArmCM0.h @@ -0,0 +1,184 @@ +/**************************************************************************//** + * @file ARMCM0.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARMCM0_H +#define ARMCM0_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ + /* ------------------- Processor Exceptions Numbers ----------------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + + /* ------------------- Processor Interrupt Numbers ------------------------------ */ + VIDC_IRQn = 0, + LCDC_IRQn = 1, + MIPI_RX_IRQn = 2, + MIPI_TX_IRQn = 3, + MEMC_IRQn = 4, + VPRE_IRQn = 5, + FLSCTRL_IRQn = 6, + DMA_IRQn = 7, + TIMER0_IRQn = 8, + TIMER1_IRQn = 9, + TIMER2_IRQn = 10, + TIMER3_IRQn = 11, + WDG_IRQn = 12, + UART_IRQn = 13, + I2C0_IRQn = 14, + I2C1_IRQn = 15, + SPIS_IRQn = 16, + SPIM_IRQn = 17, + VPRE1_IRQn = 18, + I2C2_IRQn = 19, + OTP_IRQn = 20, + SWIRE_IRQn = 21, + PVD_IRQn = 22, + AP_NRESET_IRQn = 23, + EXTI_INT0_IRQn = 24, + EXTI_INT1_IRQn = 25, + EXTI_INT2_IRQn = 26, + EXTI_INT3_IRQn = 27, + EXTI_INT4_IRQn = 28, + EXTI_INT5_IRQn = 29, + EXTI_INT6_IRQn = 30, + EXTI_INT7_IRQn = 31 + /* Interrupts 10 .. 31 are left out */ +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined (__ICCARM__) +#pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined (__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __CM0_REV 0x0000U /* Core revision r0p0 */ +#define __MPU_PRESENT 0U /* no MPU present */ +#define __VTOR_PRESENT 0U /* no VTOR present */ +#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ //20220228 +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ + +#define __FPU_PRESENT 0U /* Set to 1 if FPU is present */ +#define __FPU_DP 0U /* single precision FPU */ +#define __ICACHE_PRESENT 0U /* Set to 1 if I-CACHE is present */ +#define __DCACHE_PRESENT 0U /* Set to 1 if D-CACHE is present */ +#define __DSP_PRESENT 0U /* no DSP extension present */ + +#include "core_cm0.h" /* Processor and core peripherals */ +#include "system_ARMCM0.h" /* System Header */ + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) +#pragma pop +#elif defined (__ICCARM__) +/* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#pragma clang diagnostic pop +#elif defined (__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined (__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + +/* In HS mode and when the DMA is used, all variables and data structures dealing + with the DMA during the transaction process should be 4-bytes aligned */ +#define DMA_WORD_ALIGN_EN +#ifdef DMA_WORD_ALIGN_EN +#if defined (__GNUC__) /* GNU Compiler */ +#define __ALIGN_END __attribute__ ((aligned (4))) +#define __ALIGN_BEGIN +#else +#define __ALIGN_END +#if defined (__CC_ARM) /* ARM Compiler */ +#define __ALIGN_BEGIN __align(4) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __ALIGN_BEGIN +#elif defined (__TASKING__) /* TASKING Compiler */ +#define __ALIGN_BEGIN __align(4) +#endif /* __CC_ARM */ +#endif /* __GNUC__ */ +#else + +#define __ALIGN_BEGIN +#define __ALIGN_END + +#define __ALIGN_END_1 __attribute__ ((aligned (1))) +#endif /* DMA_WORD_ALIGN_EN */ + +/* __packed keyword used to decrease the data type alignment to 1-byte */ +#if defined (__CC_ARM) /* ARM Compiler */ +#define __packed __packed +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __packed __packed +#elif defined ( __GNUC__ ) /* GNU Compiler */ +#define __packed __attribute__ ((__packed__)) +#define __weak __attribute__((weak)) +#elif defined (__TASKING__) /* TASKING Compiler */ +#define __packed __unaligned +#endif /* __CC_ARM */ + +#ifdef __cplusplus +} +#endif + +#endif /* ARMCM0_H */ diff --git a/src/sdk/include/hal_crc.h b/src/sdk/include/hal_crc.h new file mode 100644 index 0000000..41865cc --- /dev/null +++ b/src/sdk/include/hal_crc.h @@ -0,0 +1,114 @@ +/******************************************************************************* +* +* +* File: hal_crc.h +* Description: hal crc ͷ�ļ� +* Version: V0.1 +* Date: 2023-07-27 +* Author: zzf + *******************************************************************************/ +#ifndef __HAL_CRC_H +#define __HAL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_device_datatype.h" +#include "tau_common.h" + +/******************************************************************************* +* 2.Exported constant and macro definitions +*******************************************************************************/ + +/******************************************************************************* +* 3.Exported structures, unions and enumerations +*******************************************************************************/ +/** +* @brief crc calculation unit structure +*/ +typedef struct +{ + uint32_t polynomial_value; + uint32_t initial_seed_value; + crc_protocol_type_e crc_protocol; + crc_fxor_function_e crc_foxr; + crc_reversal_type_e crc_reversal_in; + crc_reversal_type_e crc_reversal_out; +} crc_ctrl_handle_t; + +/** +* @brief crc dma callback function define +*/ +typedef void (*crc_dma_callback)(uint32_t crc_result); + +/******************************************************************************* +* 4.Exported variable declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Exported function declarations +*******************************************************************************/ +/** +* @brief The initialization for CRC calculation unit +* @param crc_ctrl_handle: configuration parameters in initialization +* @retval true or false +**/ +bool hal_crc_init(const crc_ctrl_handle_t *crc_ctrl_handle); + +/** +* @brief The initialization for CRC calculation unit +* @param None +* @retval true or false +**/ +bool hal_crc_deinit(void); + +/** +* @brief Reset CRC calculation unit and DR to CRCR_INIT value +* @param None +* @retval true or false +**/ +bool hal_crc_reset(void); + +/** +* @brief Get the result of CRC calculation uint +* @param buffer_address: 16-bit or 32-bit crc calculate buffer address +* @param buffer_length: the length of buffer +* @retval 32-bit crc calculate result +**/ +uint32_t hal_crc_cal(const void *buffer_address, uint32_t buffer_length); + +/** +* @brief initial DMA transfer +* @param crc_ctrl_handle: configuration parameters in initialization +* @param buffer_address: 16-bit or 32-bit crc calculate buffer address +* @param buffer_length: the length of buffer(0~65535) +* @param cb_func: dma interrupt callback function to get the result of crc calculation +* @retval true or false +**/ +bool hal_crc_dma_init(const crc_ctrl_handle_t *crc_ctrl_handle, crc_dma_callback cb_func, const void *buffer_address, uint16_t buffer_length); + +/** +* @brief deinitial DMA transfer +* @param None +* @retval true or false +**/ +bool hal_crc_dma_deinit(void); + +/** +* @brief start DMA transfer +* @param None +* @retval true or false +**/ +bool hal_crc_dma_start(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __HAL_CRC_H */ + +/***************** (C) COPYRIGHT ISP Systems (R) END OF FILE ******************/ diff --git a/src/sdk/include/hal_dsi_rx_ctrl.h b/src/sdk/include/hal_dsi_rx_ctrl.h new file mode 100644 index 0000000..6a5014a --- /dev/null +++ b/src/sdk/include/hal_dsi_rx_ctrl.h @@ -0,0 +1,523 @@ +/******************************************************************************* +* +* +* File: hal_dsi_rx_ctrl.h +* Description: hal mipi dsi rx path control 头文件 +* Version: V0.1 +* Date: 2021-04-06 +* Author: lzy + *******************************************************************************/ +#ifndef __HAL_DSI_RX_CTRL_H__ +#define __HAL_DSI_RX_CTRL_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_dsi_datatype.h" +#include "tau_common.h" +#include "tau_log.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +#define RX_DCS_QUEUE_MAX_SIZE 20 /* DCS存储队列长度 */ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +typedef struct hal_dcs_execute_entry_t hal_dcs_execute_entry_t; + +typedef struct hal_dcs_packet_t hal_dcs_packet_t; + +typedef struct hal_dsi_rx_ctrl_handle_t hal_dsi_rx_ctrl_handle_t; + +/* DCS CMD 回调函数, 注册进cus_dcs_entry_table里, 匹配对应的DCS 后回调*/ +typedef bool (*hal_dsi_rx_ctrl_dcs_execute)(hal_dsi_rx_ctrl_handle_t *rx_handle, hal_dcs_packet_t *dcs_packet); + +/* AP 读cmd 回调, 需要快速回CMD 时可注册, 为NULL 时DSC 读指令与写指令经过parse后由cus_dcs_entry_table回调 */ +typedef bool (*hal_dsi_rx_ctrl_read_entry)(uint8_t data_type, uint8_t dcs_cmd, uint8_t param); + +/* AP PPS 更新回调,参数为PPS 以及从PPS 里解析出来的picture width/height, 用于分辨率切换, 不注册该接口时内部处理PPS */ +typedef bool (*hal_dsi_rx_ctrl_pps_entry)(uint8_t *pps, uint8_t size, uint32_t pic_width, uint32_t pic_height); + +/** +* @brief hal_rx_event_e select +*/ +typedef enum hal_rx_event_e +{ + HAL_RX_FS_EVENT = 0x1, /* Frame start event */ + HAL_RX_LINE_EVENT = 0x2, /* Frame receive line event */ + HAL_RX_END_EVENT = 0x4, /* Frame end event */ +} hal_rx_event_e; + +/** +* @brief rx pq filter index +* 默认使用linear,特殊场景使用OPT filter +* RX_FLT_OPT_0最模糊,边缘最平滑,index越大越清晰,边缘锯齿会加重 +*/ +typedef enum +{ + RX_FLT_OPT_0 = 0, + RX_FLT_OPT_1 = 1, + RX_FLT_OPT_2 = 2, + RX_FLT_OPT_3 = 3, + RX_FLT_OPT_4 = 4, + RX_FLT_OPT_5 = 5, + RX_FLT_OPT_6 = 6, + RX_FLT_OPT_7 = 7, + RX_FLT_OPT_8 = 8, + RX_FLT_OPT_9 = 9, + RX_FLT_OPT_10 = 10, + RX_FLT_LINEAR = 11, + RX_FLT_MAX +} hal_dsi_rx_pq_filter_e; + +/* RX debug 回调函数,用于获取frame start 等功能debug */ +typedef void (*hal_dsi_rx_ctrl_event_entry)(hal_rx_event_e event, void *data); + +/** +* @brief dsi rx ctrl handle struct +*/ +typedef struct hal_dsi_rx_ctrl_handle_t +{ + dsi_base_trans_info_t base_info; /* mipi video 转换基本信息 */ + dsi_base_extra_info_t extra_info; /* 新增旋转、镜像配置 */ + dsi_color_code_e rx_color_mode; /* 输入color mode */ + dsi_lane_nume_e rx_lanes; /* mipi data lane */ + dsi_video_mode_type_e rx_nonburst_models; /* transmission packet sequences */ + bool compress_en; /* DSC 压缩标志 */ + uint32_t rx_hsclk_rate; /* mipi 高速信号lane rate */ + uint8_t rx_dsc_pps[DSC_PPS_SIZE]; /* DSC 压缩PPS参数 */ + const hal_dcs_execute_entry_t *cus_dcs_entry_table; /* DCS处理函数列表 */ + hal_dsi_rx_ctrl_read_entry rx_dcs_read_entry; /* Host读指令数据函数,为NULL时由rx_dcs_queue注册cmd处理 */ + hal_dsi_rx_ctrl_pps_entry pps_update_entry; /* PPS Update 时回调函数,用于分辨率切换更新PPS,为NULL时内部处理 */ + bool used; /* handle使用标志位 */ + hal_err_handle_level_e err_handler_level; /* RX接收错误的时候对模块做reset等级, 等级越高reset模块越多 */ + uint8_t rx_strength; /* 用于调节RX信号强度，仅适用于开启内阻校准模式，档位0~7，默认3 */ + hight_performan_mode_e hight_performan_mode; /* 高性能模式等级,参考hight_performan_mode_e */ + dsi_rx_lane_swap_e rx_lane_swap; /* lane swap default order is 2103*/ + hal_dsi_rx_pq_filter_e rx_pq_index; /* 画质调整滤波器,默认为linear最优效果,特殊场景使用OPT filter */ +} hal_dsi_rx_ctrl_handle_t; + +/** +* @brief DCS command execute entry +*/ +typedef struct hal_dcs_execute_entry_t +{ + uint32_t dcs_command; /* DCS command */ + hal_dsi_rx_ctrl_dcs_execute execute_func; /* command 对应处理函数 */ + bool immediately_func; /* 执行机制:true-在中断里立即执行,false-加入DCS队列异步执行 */ +} hal_dcs_execute_entry_t; + +/** +* @brief 存储 DCS packet 结构体 +*/ +typedef struct hal_dcs_packet_t +{ + uint32_t data_type; /* data type */ + uint32_t dcs_command; /* dcs command */ + uint32_t param_length; /* dcs param length */ + uint8_t *packet_param; /* dcs param */ + uint16_t crc_data; /* dcs crc */ + const hal_dcs_execute_entry_t *dcs_execute_entry; /* dcs packet 处理函数入口*/ +} hal_dcs_packet_t; + +/** +* @brief video mode 下 RX pattern参数结构体 +*/ +typedef struct +{ + uint32_t ipi_pg_hsa; + uint32_t ipi_pg_hbp; + uint32_t ipi_pg_hfp; + uint32_t ipi_pg_vsa; + uint32_t ipi_pg_vbp; + uint32_t ipi_pg_vfp; + uint32_t frame_rate; +} hal_dsi_rx_ipi_pg_t; + + +/** +* @brief dcs command filter select +*/ +typedef enum +{ + HAL_RX_DCS_FILTER_0 = 0x0, + HAL_RX_DCS_FILTER_1 = 0x1, + HAL_RX_DCS_FILTER_2 = 0x2, + HAL_RX_DCS_FILTER_3 = 0x3, + HAL_RX_DCS_FILTER_4 = 0x4, + HAL_RX_DCS_FILTER_5 = 0x5, + HAL_RX_DCS_FILTER_6 = 0x6, + HAL_RX_DCS_FILTER_7 = 0x7, + HAL_RX_DCS_FILTER_8 = 0x8, + HAL_RX_DCS_FILTER_9 = 0x9, + HAL_RX_DCS_FILTER_A = 0xA, + HAL_RX_DCS_FILTER_B = 0xB, + HAL_RX_DCS_FILTER_MAX +} hal_rx_dcs_filter_sel_e; + + +/** +* @brief dcs command filter select +*/ +typedef enum +{ + HAL_RX_QRESP_CODE0 = 0, + HAL_RX_QRESP_CODE1 = 1, + HAL_RX_QRESP_CODE2 = 2, + HAL_RX_QRESP_CODE3 = 3, + HAL_RX_QRESP_CODE4 = 4, + HAL_RX_QRESP_CODE5 = 5, + HAL_RX_QRESP_CODE6 = 6, + HAL_RX_QRESP_CODE7 = 7, + HAL_RX_QRESP_MAX +} hal_rx_dcs_qresp_e; + +/** +* @brief pentile source color format +*/ +typedef enum +{ + PENTILE_SRC_FORMAT_RGB = 0x0, + PENTILE_SRC_FORMAT_BGR = 0x1, + PENTILE_SRC_FORMAT_RGBG_BGRG = 0x8, + PENTILE_SRC_FORMAT_GBGR_GRGB = 0x9, + PENTILE_SRC_FORMAT_BGRG_RGBG = 0xA, + PENTILE_SRC_FORMAT_GRGB_GBGR = 0xB, + PENTILE_SRC_FORMAT_RGBG_RGBG = 0xC, + PENTILE_SRC_FORMAT_GBGR_GBGR = 0xD, + PENTILE_SRC_FORMAT_BGRG_BGRG = 0xE, + PENTILE_SRC_FORMAT_GRGB_GRGB = 0xF, + PENTILE_SRC_FORMAT_MAX +} pentile_src_format_e; + +/** +* @brief 设置RX CLK +*/ +typedef enum +{ + RX_CLK_100M = 0, + RX_CLK_150M = 1, + RX_CLK_200M = 2, + RX_CLK_300M = 3, + RX_CLK_40M = 4, + RX_CLK_80M = 5, + RX_CLK_MAX +} hal_rx_clk_e; + +/** +* @brief pq_type_e select +*/ +typedef enum +{ + PQ_TYPE_DEFAULT = 0x0, + PQ_TYPE_LIMIT = 0x1, + PQ_TYPE_MAX +} pq_type_e; + +/** +* @brief 线的粗细 +*/ +typedef enum +{ + LINE_WEIGHT_FINE = 0, + LINE_WEIGHT_MEDIUM = 1, + LINE_WEIGHT_BOLD = 2, + LINE_WEIGHT_MAX +} line_weight_e; + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ + +/** +* @brief 创建dsi rx ctrl handle (释放时需调用hal_dsi_rx_ctrl_release_handle) +* @param none +* @retval dsi rx handle +*/ +hal_dsi_rx_ctrl_handle_t *hal_dsi_rx_ctrl_create_handle(void); + +/** +* @brief 释放dsi rx ctrl handle +* @param rx_ctrl_handle: dsi rx handle +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_release_handle(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + +/** +* @brief 设置rx ctrl handle 里的 PPS 参数 +* @param rx_ctrl_handle: dsi rx handle +* @param pps: pps 参数 +* @param pps_size: pps 参数长度 +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_pre_init_pps(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint8_t pps[], uint32_t pps_size); + +/** +* @brief 初始化dsi rx 模块 +* @param rx_ctrl_handle: dsi rx handle +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_init(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + +/** +* @brief dsi rx 模块去初始化 +* @param rx_ctrl_handle: dsi rx handle +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_deinit(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + +/** +* @brief 启动dsi rx +* @param rx_ctrl_handle: dsi rx handle +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_start(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + +/** +* @brief 重新配置dsi rx参数并恢复状态 (debug使用, 重新配置rx_ctrl_handle参数后调用该接口重启) +* @param rx_ctrl_handle: dsi rx handle +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_restart(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + +/** +* @brief 停止dsi rx +* @param rx_ctrl_handle: dsi rx handle +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_stop(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + +/** +* @brief 手动设置RX clk,一般RX CLK 由底层自动计算,用于特殊video mode场景出现FIFO FULL情况调试使用 +* @param rxbr_clk: rx clk, 需要大于hs_lane_rate/8 +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_set_rx_clk(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_rx_clk_e rxbr_clk); + +/** +* @brief 发送 MIPI HOST的读响应 CMD +* @param rx_ctrl_handle: dsi rx handle +* @param data_type: data type +* @param vc: virtual channel +* @param cmd_count: ack command 的长度 +* @param ... : 需要发送的command(数量与cmd_count 配置一致) +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_send_ack_cmd(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, dsi_ack_data_type_e data_type, dsi_virtual_channel_e vc, uint8_t cmd_count, ...); + +/** +* @brief 使用数组方式回复短包,与hal_dsi_rx_ctrl_send_ack_cmd功能一致 +* @param rx_ctrl_handle: dsi rx handle +* @param data_size: 数组长度,固定为4 +* @param data: 回复cmd数据,数据排列有严格规定: +* data[0]:DI(data type) +* data[1]:data 0 +* data[2]:data 1 +* data[3]:内部pkt type,短包固定为0 +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_ack_short_cmd(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint8_t data_size, uint8_t data[]); + +/** +* @brief 使用数组方式回复长包,与hal_dsi_rx_ctrl_send_ack_cmd功能一致 +* @param rx_ctrl_handle: dsi rx handle +* @param data_size: 数组长度,为Word Count + header长度 (header固定为4) +* @param data: 回复cmd数据,数据排列有严格规定: +* data[0]:DI(data type) +* data[1]:wc 0 (Word Count 低八位) +* data[2]:wc 1 (Word Count 高八位) +* data[3]:内部pkt type,长包固定为1 +* data[N]:长包数据 +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_ack_long_cmd(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint32_t data_size, uint8_t data[]); + +/** +* @brief 异步处理DSC接口,执行cus_dcs_entry_table里对应DCS immediately_func为false的函数 +* @param rx_ctrl_handle: dsi rx handle +* @retval true - 正常处理1个DSC , false - 无DSC 处理 +*/ +bool hal_dsi_rx_ctrl_dcs_async_handler(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + +/** +* @brief 使用硬件filter丢弃不需要处理的CMD,避免MCU资源被无效CMD占用 +* @param rx_ctrl_handle: dsi rx handle +* @param filter_number: filter 编号(0-7) +* @param cmd_start: 需要丢弃command code起始位 +* @param cmd_end: 需要丢弃command code终止位 +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_set_hw_cmd_filter(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, + hal_rx_dcs_filter_sel_e filter_number, + uint32_t cmd_start, uint32_t cmd_end); + +/** +* @brief 使用内置pattern代替mipi输入(用于测试) +* @param rx_ctrl_handle: dsi rx handle +* @param pg_orient: pattern 方向(0:Vertical mode ; 1:Horizontal mode) +* @param enable: 开启/关闭pattern +* @param frame_rate: pattern 帧率 +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_enable_test_pattern(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint8_t pg_orient, bool enable, int frame_rate); + + +/** +* @brief 获取AP 配置 BTA回复数据最大size +* @param rx_ctrl_handle: dsi rx handle +* @retval 返回数据大小 +*/ +uint32_t hal_dsi_rx_ctrl_get_max_ret_size(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + +/** +* @brief 获取AP Compression Mode Command配置,默认为0,谨慎使用 +* @param rx_ctrl_handle: dsi rx handle +* @retval AP 配置compressen_en +*/ +bool hal_dsi_rx_ctrl_get_compressen_en(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + +/** +* @brief 输入分辨率切换接口 +* @param rx_ctrl_handle: dsi rx handle +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_toggle_resolution(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + +/** +* @brief 配置 RX escape clk +* @param rx_ctrl_handle: dsi rx handle +* @param esc_clk: escape clk 单位Hz,10000000时回CMD为10Mhz +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_set_cus_esc_clk(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint32_t esc_clk); + +/** +* @brief 自动计算并配置硬件filter +* @param rx_ctrl_handle: dsi rx handle +* @param enable: 启动/关闭 硬件filter +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_set_auto_hw_filter(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, bool enable); + +/* +* @brief 输入帧率修改(针对video mode) +* @param rx_ctrl_handle: dsi rx handle +* @param frame_rate：frame rate +*/ +bool hal_dsi_rx_ctrl_toggle_input_frame_rate(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, dsi_video_frame_rate_e frame_rate); + +/* +* @brief 注册写命令的回调函数,用于特殊命令序列时写命令的处理. + 可配合hal_dsi_rx_ctrl_set_auto_hw_filter关闭hw filter用于获取所有软件CMD +* @param rx_ctrl_handle: dsi rx handle +* @param 写命令处理函数 +* @retval none +*/ +void hal_dsi_rx_ctrl_register_write_cmd_entry(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_dsi_rx_ctrl_dcs_execute execute_func); + +/** +* @brief 配置硬件自动回复命令 +* 最大回复长度64,AP需要配置set_max_return_size后并且对比一直才会自动回复,不需要软件再参与 +* 应用于所有回复固定数据的场景 +* @param RXBR: registers struct +* @param qresp_number: qresp 编号(0-7) +* @param data_type: 需要回复的读命令的datatype +* @param cmd_code: 需要回复的读命令 +* @param cmd_count: 需要回复的命令的大小,长包最大size为64,与set_max_return_size一致才会回复 +* @param ...: 需要回复的参数 +* @retval true/false +*/ +bool hal_dsi_rx_ctrl_set_auto_ack(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_rx_dcs_qresp_e qresp_number, dsi_ack_data_type_e data_type, uint32_t cmd_code, uint8_t cmd_count, ...); + +/* +* @brief 初始化画点模式 +* @param rx_ctrl_handle: dsi rx handle +* @param draw_en: 画点模式使能 +* @param pxl_init_en: 是否对全屏数据赋值,true:使用init_value赋值,false:使用上一帧数据作为初始值 +* @param color_mode: 画点模式数据源格式见dsi_color_code_e +* @param init_value: 全屏初始化数据,bit[23:16]--R，bit[15:8]--G，bit[7:0]--B +* @retval none +*/ +void hal_dsi_rx_ctrl_draw_mode_init(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, bool draw_en, bool pxl_init_en, dsi_color_code_e color_mode, uint32_t init_value); + +/* +* @brief 配置像素颜色 +* @param rx_ctrl_handle: dsi rx handle +* @param x: 像素点的x 坐标 +* @param y: 像素点的y 坐标 +* @param red_data: 像素点R分量 +* @param green_data: 像素点G分量 +* @param blue_data: 像素点B分量 +* @retval none +*/ +void hal_dsi_rx_ctrl_set_pixel_data(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, int x, int y, uint8_t red_data, uint8_t green_data, uint8_t blue_data); + + +/** +* @brief video mode下强制将数据设置为特定的color mode,具体type见dsi_color_code_e +* @param rx_ctrl_handle: dsi rx handle +* @param enable: 使能强制数据模式 +* @param frc_vid_code: 强制的数据格式 +* @retval none +*/ +void hal_dsi_rx_ctrl_force_video_crtl(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, bool enable, dsi_color_code_e frc_vid_code); + +/** +* @brief 注册RX 事件回调函数 +* @param rx_ctrl_handle: dsi rx handle +* @param event_cb: 回调函数 +* @param event_mask: 接收事件掩码,见hal_rx_event_e(eg:HAL_RX_FS_EVENT|HAL_RX_LINE_EVENT) +* @param enable: 事件回调开关 +* @param user_data: 预留扩展参数,不同事件事件配置不同参数 +* @retval none +*/ +void hal_dsi_rx_ctrl_register_callback(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, hal_dsi_rx_ctrl_event_entry event_cb, uint32_t event_mask, bool enable, void *user_data); + +/** +* @brief 配置是否打开长包CRC检查 +* @param rx_ctrl_handle: dsi rx handle +* @param enable: 开启或者屏蔽CRC检测 +* @retval none +*/ +void hal_dsi_rx_ctrl_set_check_crc(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, bool enable); + +/** +* @brief 配置rx log 等级 +* @param rx_drv_level: rx log等级见枚举log_level_e +* @retval none +*/ +void hal_dsi_rx_ctrl_set_log_level(log_level_e rx_drv_level); + +/** + * @brief 带颜色画线函数(直线、斜线) + * @param x1,y1 起点坐标 + * @param x2,y2 终点坐标 + * @param red_data: 像素点R分量 + * @param green_data: 像素点G分量 + * @param blue_data: 像素点B分量 + * @param line_weight: 线粗 + * @return none + */ +void hal_dsi_rx_ctrl_draw_line(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint8_t red_data, uint8_t green_data, uint8_t blue_data, line_weight_e line_weight); + +/** + * @brief 设置需要获取pixel的坐标 + * @param cap_x: 抓取pixel的x坐标 + * @param cap_y: 抓取pixel的y坐标 + * @return none + */ +void hal_dsi_rx_ctrl_set_cap_pixel_pos(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle, uint16_t x0, uint16_t y0); + +/** + * @brief 获取指定坐标颜色,必须先设置获取颜色的坐标 + * @return 返回指定坐标颜色 + */ +uint32_t hal_dsi_rx_ctrl_get_cap_pixel_color(hal_dsi_rx_ctrl_handle_t *rx_ctrl_handle); + +#endif //__HAL_DSI_RX_CTRL_H__ diff --git a/src/sdk/include/hal_dsi_tx_ctrl.h b/src/sdk/include/hal_dsi_tx_ctrl.h new file mode 100644 index 0000000..1f4bdf3 --- /dev/null +++ b/src/sdk/include/hal_dsi_tx_ctrl.h @@ -0,0 +1,349 @@ +/******************************************************************************* +* +* +* File: hal_dsi_tx_ctrl.h +* Description: hal mipi dsi tx 头文件 +* Version: V0.1 +* Date: 2021-04-23 +* Author: jaya + *******************************************************************************/ +#ifndef __HAL_DSI_TX_CTRL_H__ +#define __HAL_DSI_TX_CTRL_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_dsi_datatype.h" +#include "tau_device_datatype.h" +#include "hal_gpio.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +/** +* @brief blank display configure type +*/ +typedef struct +{ + uint16_t st_col; /* 补黑区域起始坐标，RGBG格式以子像素计数*/ + uint16_t width; /* 补黑区域宽度，RGBG格式以子像素计数*/ + uint8_t remap_en; /* 补黑区域是否参与子像素重排*/ + uint8_t blank_en; /* 补黑区域开关*/ +} blank_disp_t; + +/** +* @brief pentile remap rule configuration type in rom code +*/ +typedef uint8_t (remap_rule_t)[24]; + +/** +* @brief 客制化MIPI TX参数结构体 +*/ +typedef struct +{ + bool pentile_enable; /* 是否pentile输出*/ + bool pentile_reverse_en; /* 是否打开芯片本身行翻转功能*/ + bool pentile_24b; /* 是否以RGB IC搭配RGBG玻璃*/ + uint32_t rgb_hact; /* RGB IC搭配RGBG玻璃使用时IC水平方向分辨率*/ + remap_rule_t *remapl_rule; /* RGB IC搭配RGBG玻璃使用时remap规则1*/ + remap_rule_t *remapr_rule; /* RGB IC搭配RGBG玻璃使用时remap规则2*/ + blank_disp_t blank_info0; /* 补黑参数配置信息*/ + blank_disp_t blank_info1; /* 补黑参数配置信息*/ +} dsi_tx_pent_info_t; + +/** +* @brief MIPI TX clk/data lane是否自动进LP控制枚举类型 +* 不同driver IC spec不同,对Lane rate范围要求也不同 +* 无法点亮时可尝试替换不同的模式 +*/ +typedef enum +{ + ALWAYS_HS = 0, // vid输出默认此模式，仅VSA自动进LP; cmd输出暂不支持此模式 + ONLY_DATA_LANE_AUTO_LP = 1, // cmd输出默认此模式，data lane行间自动进LP， clk保持HS + CLK_DATA_LANE_AUTO_LP = 2, // data/clk lane行间自动进LP +} dsi_tx_lane_lp_e; + +/** +* @brief tx pq filter index +* 默认使用OPT +*/ +typedef enum +{ + TX_FLT_OPT = 0, + TX_FLT_LINEAR = 1, + TX_FLT_MAX +} hal_dsi_tx_pq_filter_e; + +/** +* @brief 客制化MIPI TX参数结构体 +*/ +typedef struct +{ + dsi_base_trans_info_t base_info; /* mipi video 转换基本信息 */ + uint32_t dpi_vsa; /* DPI VSA*/ + uint32_t dpi_vbp; /* DPI VBP*/ + uint32_t dpi_vfp; /* DPI VFP*/ + uint32_t dpi_hsa; /* DPI HSA*/ + uint32_t dpi_hbp; /* DPI HBP*/ + uint32_t dpi_hfp; /* DPI HFP*/ + float tx_frame_rate; /* 默认60Hz输出,不建议配置为其他,仅作为debug使用 */ + uint8_t lane_num; /* TX 使用的 lane 数量*/ + bool used; /* handle使用标志位 内部自动更新状态，不需要操作*/ + bool lp_exit_lpdt; /* 每一条LP CMD都退出LPDT */ + dsi_tx_lane_lp_e tx_lane_lp; /* clk/data lane是否自动进LP模式配置 */ + dsi_virtual_channel_e channel_id; /* 虚拟通道ID，默认为0*/ + dsi_video_mode_type_e vid_mode; /* video输出时选择输出的vid模式种类 */ + dsi_tx_cmd_tx_type_e cmd_tx_type; /* 初始化模式传输命令方式，0:HS; 1:LP */ + dsi_tx_pent_info_t pentile_info; /* pentile屏基本信息 */ + hal_dsi_tx_pq_filter_e tx_pq_index; /* 画质调整滤波器,默认为OPT最优效果 */ +} hal_dsi_tx_ctrl_handle_t; + +/** +* @brief TE 信号产生模式 +*/ +typedef enum +{ + TE_60HZ_MODE = 0, + TE_USER_MODE = 1, /* 底层不产生TE, 由hal_dsi_tx_ctrl_gen_a_tear_signal 接口产生 */ + TE_STOP_MODE = 1, + TE_90HZ_MODE = 2, + TE_120HZ_MODE = 3, + TE_144HZ_MODE = 4, + TE_160HZ_MODE = 5, + TE_MODE_MAX +} te_mode_e; + +/** +* @brief dpi tx vpg style +*/ +typedef enum +{ + TX_VPG_V_COLOR = 0, + TX_VPG_H_COLOR = 1, + TX_VPG_V_BER = 2, + TX_VPG_FLICKER = 3, + TX_VPG_MAX +} dsi_tx_vpg_style_e; + +/** +* @brief MIPI TX初始化 +* @param tx_ctrl_handle: MIPI TX实例 +* @retval true/false +*/ +bool hal_dsi_tx_ctrl_init(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); + +/** +* @brief MIPI TX反初始化 +* @param tx_ctrl_handle: MIPI TX实例 +* @retval true/false +*/ +bool hal_dsi_tx_ctrl_deinit(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); + +/** +* @brief MIPI TX创建实例 +* @param None +* @retval tx_ctrl_handle: MIPI TX实例 +*/ +hal_dsi_tx_ctrl_handle_t *hal_dsi_tx_ctrl_create_handle(void); + +/** +* @brief MIPI TX释放实例 +* @param tx_ctrl_handle: MIPI TX实例 +* @retval true/false +*/ +bool hal_dsi_tx_ctrl_release_handle(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); + +/** +* @brief MIPI TX开始运行 +* @param tx_ctrl_handle: MIPI TX实例 +* @retval true/false +*/ +bool hal_dsi_tx_ctrl_start(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); + +/** +* @brief MIPI TX停止运行 +* @param tx_ctrl_handle: MIPI TX实例 +* @retval true/false +*/ +bool hal_dsi_tx_ctrl_stop(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); + +/** +* @brief MIPI TX接收命令 +* @param data_type: 数据类型，参考枚举类型dsi_data_type_e +* @param vc: 虚拟通道编号，参考枚举类型dsi_virtual_channel_e +* @param cmd: DCS指令 +* @param size: 读取数据长度 +* @param data: 数据存放地址 +* @retval None +*/ +void hal_dsi_tx_ctrl_read_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd, uint8_t size, uint8_t *data); + +/** +* @brief video高速数据传输时V porch阶段进行bta回读接口 +* @param data_type: 数据类型，参考枚举类型dsi_data_type_e +* @param cmd: DCS指令 +* @param size: 读取数据长度 +* @param data: 数据存放地址 +* @retval true-BTA回复获取有效，false-BTA回复未获得 +* @attention 需要考虑V porch时长是否足够size长度的寄存器回读，否则造成TX数据通路出错 +*/ +bool hal_dsi_tx_ctrl_vporch_bta_opera(uint8_t data_type, uint8_t cmd, uint8_t size, uint8_t *data); + +/** +* @brief MIPI TX发送命令 +* @param data_type: 数据类型，参考枚举类型dsi_data_type_e +* @param vc: 虚拟通道编号，参考枚举类型dsi_virtual_channel_e +* @param cmd_count: 可变参数个数 +* @param ...: 可变参数 +* @retval true-command发送正常；false-TX当前状态不能发送command +*/ +bool hal_dsi_tx_ctrl_write_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd_count, ...); + +/** +* @brief MIPI TX发送命令 +* @param data_type: 数据类型，参考枚举类型dsi_data_type_e +* @param vc: 虚拟通道编号，参考枚举类型dsi_virtual_channel_e +* @param size: data个数 +* @param data: data数组 +* @retval true-command发送正常；false-TX当前状态不能发送command +*/ +bool hal_dsi_tx_ctrl_write_array_cmd(uint8_t data_type, uint8_t vc, uint8_t size, const uint8_t *data); + +/** +* @brief 切换至 LP cmd发送模式 +* @param enable: true-进行cmd发送；false-结束LP cmd发送 +* @retval None +* @attention 应用场景：AP enter sleep后传输发送LP cmd +*/ +void hal_dsi_tx_ctrl_cmd_mode(bool enable); + +/** +* @brief 设置TX escape mode时钟 +* @param esc_clk: escape clk 单位Hz,10000000时CMD为10Mhz +* @retval None +*/ +void hal_dsi_tx_ctrl_set_escape_clock_div(uint32_t esc_clk); + +/** +* @brief 设置RGB或BGR +* @param endianness: 选择RGB或BGR显示，参考dsi_endianness_e +* @attention 接口需要在初始化接口hal_dsi_tx_ctrl_init调用前才能生效 +* @retval None +*/ +void hal_dsi_tx_ctrl_set_endianness(dsi_endianness_e endianness); + +/** +* @brief 设置CCM参数 +* @param coef: 客制化参数，参考结构体ccm_coef_t +* @retval None +*/ +void hal_dsi_tx_ctrl_set_ccm(ccm_coef_t *ccm); + +/** +* @brief 设置边缘检测算法参数 +* @param edge_dect_para: 边缘检测算法参数，参考 dsi_tx_edge_dect_t;关闭模块时可以传参NULL +* @param edge_dect_en: 是否开启边缘检测模块 +* @retval None +*/ +void hal_dsi_tx_ctrl_set_edge_dect(dsi_tx_edge_dect_t *edge_dect_para, bool edge_dect_en); + +/** +* @brief 设置边缘增强效果算法参数 +* @param edge_enh_para: 边缘增强算法参数，参考 dsi_tx_edge_enh_t;关闭模块时可以传参NULL +* @param edge_enh_en: 是否开启边缘增强模块 +* @retval None +*/ +void hal_dsi_tx_ctrl_set_edge_enhance(dsi_tx_edge_enh_t *edge_enh_para, bool edge_enh_en); + +/** +* @brief 设置False Color remove算法参数 +* @param fc_para: false color参数，参考 dsi_tx_fc_t;关闭模块时可以传参NULL +* @param fc_en: 是否开启false color配置模块 +* @retval None +*/ +void hal_dsi_tx_ctrl_set_fc(dsi_tx_fc_t *fc_para, bool fc_en); + +/** +* @brief 设置bcs参数 +* @param bcs_para: 明亮度/对比度/饱和度，参考 dsi_tx_bcs_t;关闭模块时可以传参NULL +* @param bcs_en: 是否开启bcs配置模块 +* @retval None +*/ +void hal_dsi_tx_ctrl_set_bcs(dsi_tx_bcs_t *bcs_para, bool bcs_en); + +/** +* @brief 设置复写颜色 +* @param R: RGB的R分量 +* @param G: RGB的G分量 +* @param B: RGB的B分量 +* @retval None +*/ +void hal_dsi_tx_ctrl_set_overwrite_rgb(uint8_t R, uint8_t G, uint8_t B); + +/** +* @brief 打开overwrite功能 +* @param enable: true-打开overwrite； false-关闭overwrite +* @retval None +*/ +void hal_dsi_tx_ctrl_overwrite_enable(bool enable); + +/** +* @brief 设置部分显示 +* @param enable: true-打开partial显示； false-关闭partial显示 +* @param par_disp_cfg display区域和背景色设置，参考 dsi_tx_par_dis_t; 关闭模块功能时可以传参NULL +* @retval None +*/ +void hal_dsi_tx_ctrl_partial_disp_enable(bool enable, dsi_tx_par_dis_t *par_disp_cfg); + +/** +* @brief 控制TX VPG的输出 +* @param vpg_en: 使能VPG +* @param style: VPG的样式 +* @param vpg_hline_adj: false-正常情况使用，true-VPG显示滚动情况下使用 +* @attention vpg_hline_adj此参数只能解决带宽余量相差不大的情况，如果带宽需求超出过多，依然无法解决带宽不足引起的VPG显示滚动问题 +* @retval None +*/ +void hal_dsi_tx_ctrl_set_vpg(bool vpg_en, dsi_tx_vpg_style_e style, bool vpg_hline_adj); + +/** +* @brief 配置TE模式 +* @param tx_ctrl_handle: dsi tx handle +* @param te: te mode +* @retval None +*/ +void hal_dsi_tx_ctrl_set_tear_mode(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle, te_mode_e te); + +/** +* @brief 生成一个TE信号 +* @param None +* @retval None +*/ +void hal_dsi_tx_ctrl_gen_a_tear_signal(void); + +/** +* @brief command mode输出模式下产生一帧数据 +* @param None +* @retval None +*/ +bool hal_dsi_tx_ctrl_gen_a_frame(void); + +/** +* @brief 配置输入输出同步行数,用于调整图像撕裂问题 +* @param tx_ctrl_handle: dsi tx handle +* @param line_num: 同步行号,范围1 ~ output height +* @retval true/false +*/ +bool hal_dsi_tx_ctrl_set_cus_sync_line(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle, uint32_t line_num); + +/** +* @brief 获取TX当前显示行号 +* @param tx_ctrl_handle: dsi tx handle +* @retval 当前显示行号,包括vsa + vbp + vactive + vfp +*/ +uint32_t hal_dsi_tx_ctrl_get_disp_line(hal_dsi_tx_ctrl_handle_t *tx_ctrl_handle); + +#endif //__HAL_DSI_TX_CTRL_H__ diff --git a/src/sdk/include/hal_flash.h b/src/sdk/include/hal_flash.h new file mode 100644 index 0000000..0375dcd --- /dev/null +++ b/src/sdk/include/hal_flash.h @@ -0,0 +1,139 @@ +/******************************************************************************* +* +* +* File: hal_system.h +* Description hal 通用系统接口头文件 +* Version V0.1 +* Date 2023-03-03 +* Author kevin + *******************************************************************************/ +#ifndef __HAL_FLASH_H__ +#define __HAL_FLASH_H__ +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_common.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +typedef struct +{ + uint8_t flash_block; + uint8_t flash_page; + uint16_t data_size; + uint16_t page_offset_addr; + uint8_t *user_data; +} fls_ops_cfg_t; + +/** +* @brief 用户空间的操作 +*/ +typedef enum +{ + FLASH_USERDATA_READ, +} fls_userdata_ops_e; + + +/** +* @brief 公共区域的操作 +*/ +typedef enum +{ + FLASH_PUBLIC_READ, + FLASH_PUBLIC_WRITE, + FLASH_PUBLIC_ERASE_4K, + FLASH_PUBLIC_ERASE_32K +} fls_public_ops_e; + + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ + +/** +* @brief 初始化flash 模块,使用完flash模块后需要deinit用于节省功耗 +* @param +* @retval bool 无 +*/ +void hal_flash_init(void); + +/** +* @brief 关闭flash 模块 +* @param +* @retval bool 无 +*/ +void hal_flash_deinit(void); + + +/** +* @brief flash ctl读取flash-uid操作 +* @param UID[16] 存放UID的数组,UID最大长度为16 +* @param UID 数组长度(最大16) +* @retval +*/ +void hal_flash_read_uid(uint8_t *UID, uint8_t size); + +/** +* @brief 发送0xAB指令控制flash退出deep sleep power mode +* @param none +* @retval null +*/ +void hal_flash_release_power_down(void); + +/** +* @brief 发送0xB9指令控制flash进入deep sleep power mode +* @param none +* @retval null +*/ +void hal_flash_power_down(void); + +/** +* @brief 配置共享flash开关(使用过后注意关闭,常开功耗会增加) +* @param enable:true:可通过F_SPI访问内部flash , false:不可通过F_SPI访问内部flash +* @retval true/false +*/ +bool hal_flash_share_mode(bool enable); + +/** +* @brief 获取user_data的个数 +* @param +* @retval 数据个数 +*/ +uint32_t hal_flash_get_user_data_size(void); + +/** +* @brief Flash user data区域,该区域由烧录器烧录,软件只读,不可写。 + Size从hal_flash_get_user_data_size接口获取 +* @param ops:选择操作的方式：读 + cfg: flash_block: flash block = userdata偏移地址/64K + flash_page: flash page = (userdata偏移地址%/64K)/1K + page_offset_addr: userdata偏移地址%block(1K)，flash page内偏移地址(0-1023) + data_size: 读取数据的总长度 (0-1023) + user_data: 读取的数据 +* @retval 无 +*/ +void hal_flash_user_region_ops(fls_userdata_ops_e ops, fls_ops_cfg_t *cfg); + + +/** +* @brief Flash公共区域，可读写、擦除，大小32KB +* @param ops:选择操作的方式：读/写/擦除 + cfg: flash_block:固定为0 + flash_page:0-31 (总共32KB) + page_offset_addr: flash page内偏移地址(0-1023) + data_size: 需要操作数据的总长度 (0-1023) + user_data: 需要操作的数据 +* @retval 无 +*/ +void hal_flash_public_region_ops(fls_public_ops_e ops, fls_ops_cfg_t *cfg); +#endif //__HAL_FLASH_H__ diff --git a/src/sdk/include/hal_gpio.h b/src/sdk/include/hal_gpio.h new file mode 100644 index 0000000..75607c8 --- /dev/null +++ b/src/sdk/include/hal_gpio.h @@ -0,0 +1,725 @@ +/******************************************************************************* +* +* +* File: hal_gpio.h +* Description： gpio HAL层头文件 +* Version： V0.1 +* Date： 2023-07-27 +* Author： kevin + *******************************************************************************/ +#ifndef __HAL_GPIO_H__ +#define __HAL_GPIO_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_device_datatype.h" +#include "tau_common.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ +/** +* @brief GPIO pin +*/ +typedef enum +{ + /*以GPIO命名PIN*/ + IO_PAD_GPIO0 = 0, + IO_PAD_GPIO1, + IO_PAD_GPIO2, + IO_PAD_GPIO3, + IO_PAD_GPIO4, + IO_PAD_GPIO5, + IO_PAD_GPIO6, + IO_PAD_GPIO7, + IO_PAD_GPIO8, + IO_PAD_GPIO9, + IO_PAD_GPIO10, + IO_PAD_GPIO11, + IO_PAD_GPIO12, + IO_PAD_GPIO13, + IO_PAD_GPIO14, + IO_PAD_GPIO15, + IO_PAD_GPIO16, + IO_PAD_GPIO17, + IO_PAD_GPIO18, + IO_PAD_GPIO19, + IO_PAD_GPIO20, + IO_PAD_GPIO21, + IO_PAD_GPIO22, + IO_PAD_GPIO23, + IO_PAD_GPIO24, + IO_PAD_GPIO25, + + /*以实际PAD NAME命名PIN*/ + IO_PAD_AP_SPIS_MISO = IO_PAD_GPIO0, + IO_PAD_AP_SPIS_MOSI = IO_PAD_GPIO1, + IO_PAD_AP_INT = IO_PAD_GPIO2, + IO_PAD_AP_TE = IO_PAD_GPIO3, + IO_PAD_AP_SWIRE = IO_PAD_GPIO4, + IO_PAD_TD_SPIM_MISO = IO_PAD_GPIO5, + IO_PAD_TD_SPIM_MOSI = IO_PAD_GPIO6, + IO_PAD_TD_RSTN = IO_PAD_GPIO7, + IO_PAD_AP_PWMEN = IO_PAD_GPIO8, + IO_PAD_AP_SPIS_CLK = IO_PAD_GPIO9, + IO_PAD_AP_SPIS_CSN = IO_PAD_GPIO10, + IO_PAD_TD_FC_CLK = IO_PAD_GPIO11, + IO_PAD_TD_FC_CSN = IO_PAD_GPIO12, + IO_PAD_TD_FC_IO0 = IO_PAD_GPIO13, + IO_PAD_TD_FC_IO1 = IO_PAD_GPIO14, + IO_PAD_SWD_CLK = IO_PAD_GPIO15, + IO_PAD_SWD_DIO = IO_PAD_GPIO16, + IO_PAD_AP_RSTN = IO_PAD_GPIO17, + IO_PAD_UART0_TX = IO_PAD_GPIO18, + IO_PAD_TD_SPIM_CLK = IO_PAD_GPIO19, + IO_PAD_TD_SPIM_CSN = IO_PAD_GPIO20, + IO_PAD_AP_TPRSTN = IO_PAD_GPIO21, + IO_PAD_TD_INT = IO_PAD_GPIO22, + IO_PAD_TD_TP_RESX = IO_PAD_GPIO23, + IO_PAD_UART1_TX = IO_PAD_GPIO24, + IO_PAD_UART0_RX = IO_PAD_GPIO25, + + IO_PAD_MAX, + + + /*以实际引脚序号命名PIN*/ + IO_PIN_1 = IO_PAD_SWD_CLK, + IO_PIN_2 = IO_PAD_UART0_TX, + IO_PIN_3 = IO_PAD_SWD_DIO, + IO_PIN_4 = IO_PAD_TD_SPIM_MOSI, + IO_PIN_5 = IO_PAD_TD_SPIM_CLK, + IO_PIN_6 = IO_PAD_TD_SPIM_CSN, + IO_PIN_7 = IO_PAD_TD_SPIM_MISO, + IO_PIN_8 = IO_PAD_TD_RSTN, + IO_PIN_9 = IO_PAD_TD_FC_CSN, + IO_PIN_10 = IO_PAD_TD_FC_CLK, + IO_PIN_11 = IO_PAD_TD_FC_IO0, + IO_PIN_12 = IO_PAD_TD_FC_IO1, + IO_PIN_13 = IO_PAD_TD_TP_RESX, + IO_PIN_14 = IO_PAD_UART1_TX, + IO_PIN_15 = IO_PAD_AP_SWIRE, + IO_PIN_16 = IO_PAD_AP_INT, + IO_PIN_17 = IO_PAD_AP_PWMEN, + IO_PIN_18 = IO_PAD_AP_TPRSTN, + + IO_PIN_29 = IO_PAD_AP_TE, + IO_PIN_30 = IO_PAD_AP_SPIS_MISO, + IO_PIN_31 = IO_PAD_AP_SPIS_CSN, + IO_PIN_32 = IO_PAD_AP_SPIS_CLK, + IO_PIN_33 = IO_PAD_AP_SPIS_MOSI, + IO_PIN_34 = IO_PAD_AP_RSTN, + IO_PIN_35 = IO_PAD_TD_INT, + IO_PIN_36 = IO_PAD_UART0_RX, + +} io_pad_e; + + +/* +芯片引脚 | 默认mode | 可选mode +---------------------------------------------------------------- +IO_PIN_1 | IO_PAD_SWCLK, | PIN1_MODE_SWDCLK + | | PIN1_MODE_GPIO15 +---------------------------------------------------------------- +IO_PIN_2 | IO_PAD_UART0_TX, | PIN2_MODE_UART0_TX + | | PIN2_MODE_PWMO + | | PIN2_MODE_GPIO18 + | | PIN2_MODE_PWMI + | | PIN2_MODE_TEAR1 +---------------------------------------------------------------- +IO_PIN_3 | IO_PAD_SWDIO, | PIN3_MODE_SWDIO + | | PIN3_MODE_GPIO16 +---------------------------------------------------------------- +IO_PIN_4 | IO_PAD_TD_SPIM_MOSI, | PIN4_MODE_SPIM_MOSI + | | PIN4_MODE_I2C02_SDA + | | PIN4_MODE_GPIO6 + | | PIN4_MODE_UART0_TX +---------------------------------------------------------------- +IO_PIN_5 | IO_PAD_TD_SPIM_CLK, | PIN5_MODE_SPIM_SCLK + | | PIN5_MODE_I2C1_SCL + | | PIN5_MODE_GPIO19 +---------------------------------------------------------------- +IO_PIN_6 | IO_PAD_TD_SPIM_CSN, | PIN6_MODE_SPIM_CSN + | | PIN6_MODE_I2C1_SDA + | | PIN6_MODE_GPIO20 +---------------------------------------------------------------- +IO_PIN_7 | IO_PAD_TD_SPIM_MISO, | PIN7_MODE_SPIM_MISO + | | PIN7_MODE_I2C02_SCL + | | PIN7_MODE_GPIO5 +---------------------------------------------------------------- +IO_PIN_8 | IO_PAD_TD_RSTN, | PIN8_MODE_GPIO7 + | | PIN8_MODE_I2C02_SDA +---------------------------------------------------------------- +IO_PIN_9 | IO_PAD_TD_FC_CSN, | PIN9_MODE_TSPIS_CSN + | | PIN9_MODE_GPIO12 +---------------------------------------------------------------- +IO_PIN_10 | IO_PAD_TD_FC_CLK, | PIN10_MODE_TSPIS_CLK + | | PIN10_MODE_GPIO11 +---------------------------------------------------------------- +IO_PIN_11 | IO_PAD_TD_FC_IO0, | PIN11_MODE_TSPIS_IO0 + | | PIN11_MODE_GPIO13 + | | PIN11_MODE_I2C02_SDA +---------------------------------------------------------------- +IO_PIN_12 | IO_PAD_TD_FC_IO1, | PIN12_MODE_TSPIS_IO1 + | | PIN12_MODE_GPIO14 + | | PIN12_MODE_I2C02_SCL +---------------------------------------------------------------- +IO_PIN_13 | IO_PAD_TD_TP_RESX, | PIN13_MODE_GPIO23 + | | PIN13_MODE_PWMO + | | PIN13_MODE_UART1_RX + | | PIN13_MODE_UART1_RX +---------------------------------------------------------------- +IO_PIN_14 | IO_PAD_UART1_TX, | PIN14_MODE_GPIO24 + | | PIN14_MODE_UART0_RX + | | PIN14_MODE_UART1_TX + | | +---------------------------------------------------------------- +IO_PIN_15 | IO_PAD_AP_SWIRE, | PIN15_MODE_SWIRE + | | PIN15_MODE_PWMO + | | PIN15_MODE_GPIO4 +---------------------------------------------------------------- +IO_PIN_16 | IO_PAD_AP_INT, | PIN16_MODE_GPIO2 +---------------------------------------------------------------- +IO_PIN_17 | IO_PAD_AP_PWMEN, | PIN17_MODE_UART0_RX + | | PIN17_MODE_GPIO8 + | | PIN17_MODE_PWMO +---------------------------------------------------------------- +IO_PIN_18 | IO_PAD_AP_TPRSTN, | PIN18_MODE_UART0_RX + | | PIN18_MODE_GPIO21 + | | PIN18_MODE_I2C02_SCL +---------------------------------------------------------------- +IO_PIN_29 | IO_PAD_AP_TE, | PIN29_MODE_JTAG_TRSTN + | | PIN29_MODE_TEAR + | | PIN29_MODE_GPIO3 +---------------------------------------------------------------- +IO_PIN_30 | IO_PAD_AP_SPIS_MISO, | PIN30_MODE_JTAG_TDO + | | PIN30_MODE_SPIS_MISO + | | PIN30_MODE_GPIO0 + | | PIN30_MODE_UART0_RX + | | PIN30_MODE_I2C1_SCL +---------------------------------------------------------------- +IO_PIN_31 | IO_PAD_AP_SPIS_CSN, | PIN31_MODE_JTAG_TMS + | | PIN31_MODE_SPIS_CSN + | | PIN31_MODE_GPIO10 + | | PIN31_MODE_I2C02_SDA +---------------------------------------------------------------- +IO_PIN_32 | IO_PAD_AP_SPIS_CLK, | PIN32_MODE_JTAG_TCK + | | PIN32_MODE_SPIS_SCLK + | | PIN32_MODE_GPIO9 + | | PIN32_MODE_I2C02_SCL +---------------------------------------------------------------- +IO_PIN_33 | IO_PAD_AP_SPIS_MOSI, | PIN33_MODE_JTAG_TDI + | | PIN33_MODE_SPIS_MOSI + | | PIN33_MODE_GPIO1 + | | PIN33_MODE_UART0_TX + | | PIN33_MODE_I2C1_SDA_0 +---------------------------------------------------------------- +IO_PIN_34 | IO_PAD_AP_RSTN, | PIN34_MODE_GPIO17 +---------------------------------------------------------------- +IO_PIN_35 | IO_PAD_TD_INT, | PIN35_MODE_GPIO22 +---------------------------------------------------------------- +IO_PIN_36 | IO_PAD_UART0_RX, | PIN36_MODE_UART0_RX + | | PIN36_MODE_PWMO + | | PIN36_MODE_GPIO25 +---------------------------------------------------------------- +*/ + + +/** +* @brief PIN1 IO_PAD_SWD_CLK 可选的mode +*/ +typedef enum +{ + PIN1_MODE_SWDCLK = 0, + PIN1_MODE_GPIO15 = 2, +} pin1_mode_e; + + +/** +* @brief PIN2 PAD_UART0_TX可选的mode +*/ +typedef enum +{ + PIN2_MODE_UART0_TX = 0, + PIN2_MODE_PWMO = 1, + PIN2_MODE_GPIO18 = 2, + PIN2_MODE_PWMI = 3, + PIN2_MODE_TEAR1 = 4, +} pin2_mode_e; + +/** +* @brief PIN3 IO_PAD_SWD_DIO 可选的mode +*/ +typedef enum +{ + PIN3_MODE_SWDIO = 0, + PIN3_MODE_GPIO16 = 2, +} pin3_mode_e; + + +/** +* @brief PIN4 PAD_TD_SPIM_MOSI可选的mode +*/ +typedef enum +{ + PIN4_MODE_SPIM_MOSI = 0, + PIN4_MODE_I2C02_SDA = 1, + PIN4_MODE_GPIO6 = 2, + PIN4_MODE_UART0_TX = 3, +} pin4_mode_e; + +/** +* @brief PIN5 PAD_TD_SPIM_CLK可选的mode +*/ +typedef enum +{ + PIN5_MODE_SPIM_SCLK = 0, + PIN5_MODE_I2C1_SCL = 1, + PIN5_MODE_GPIO19 = 2, +} pin5_mode_e; + +/** +* @brief PIN6 PAD_TD_SPIM_CSN可选的mode +*/ +typedef enum +{ + PIN6_MODE_SPIM_CSN = 0, + PIN6_MODE_I2C1_SDA = 1, + PIN6_MODE_GPIO20 = 2, +} pin6_mode_e; + +/** +* @brief PIN7 PAD_TD_SPIM_MISO可选的mode +*/ +typedef enum +{ + PIN7_MODE_SPIM_MISO = 0, + PIN7_MODE_I2C02_SCL = 1, + PIN7_MODE_GPIO5 = 2, +} pin7_mode_e; + +/** +* @brief PIN8 PAD_TD_RSTN可选的mode +*/ +typedef enum +{ + PIN8_MODE_GPIO7 = 2, + PIN8_MODE_I2C02_SDA = 3, +} pin8_mode_e; + +/** +* @brief PIN9 PAD_TD_FC_CSN可选的mode +*/ +typedef enum +{ + PIN9_MODE_TSPIS_CSN = 0, + PIN9_MODE_GPIO12 = 2, +} pin9_mode_e; + +/** +* @brief PIN10 PAD_TD_FC_CLK可选的mode +*/ +typedef enum +{ + PIN10_MODE_TSPIS_CLK = 0, + PIN10_MODE_GPIO11 = 2, +} pin10_mode_e; + + +/** +* @brief PIN11 PAD_TD_FC_IO0可选的mode +*/ +typedef enum +{ + PIN11_MODE_TSPIS_IO0 = 0, + PIN11_MODE_GPIO13 = 2, + PIN11_MODE_I2C02_SDA = 3, +} pin11_mode_e; + +/** +* @brief PIN12 PAD_TD_FC_IO1可选的mode +*/ +typedef enum +{ + PIN12_MODE_TSPIS_IO1 = 0, + PIN12_MODE_GPIO14 = 2, + PIN12_MODE_I2C02_SCL = 3, +} pin12_mode_e; + +/** +* @brief PIN13 PAD_TD_TP_RESX可选的mode +*/ +typedef enum +{ + PIN13_MODE_GPIO23 = 2, + PIN13_MODE_PWMO = 3, + PIN13_MODE_UART1_RX = 4, +} pin13_mode_e; + +/** +* @brief PIN14 PAD_UART1_TX可选的mode +*/ +typedef enum +{ + PIN14_MODE_GPIO24 = 2, + PIN14_MODE_UART0_RX = 3, + PIN14_MODE_UART1_TX = 4, +} pin14_mode_e; + + + +/** +* @brief PIN15 PAD_AP_SWIRE可选的mode +*/ +typedef enum +{ + PIN15_MODE_SWIRE = 0, + PIN15_MODE_PWMO = 1, + PIN15_MODE_GPIO4 = 2, +} pin15_mode_e; + +/** +* @brief PIN16 IO_PAD_AP_INT 可选的mode +*/ +typedef enum +{ + PIN16_MODE_GPIO2 = 2, +} pin16_mode_e; + +/** +* @brief PIN17 PAD_AP_PWMEN可选的mode +*/ +typedef enum +{ + PIN17_MODE_UART0_RX = 1, + PIN17_MODE_GPIO8 = 2, + PIN17_MODE_PWMO = 3, +} pin17_mode_e; + +/** +* @brief PIN18 IO_PAD_AP_TPRSTN 可选的mode +*/ +typedef enum +{ + PIN18_MODE_UART0_RX = 0, + PIN18_MODE_GPIO21 = 2, + PIN18_MODE_I2C02_SCL = 3, +} pin18_mode_e; + + +//---------- + +/** +* @brief PIN29 IO_PAD_AP_TE 可选的mode +*/ +typedef enum +{ + PIN29_MODE_JTAG_TRSTN = 0, + PIN29_MODE_TEAR = 1, + PIN29_MODE_GPIO3 = 2, +} pin29_mode_e; + + +/** +* @brief PIN30 IO_PAD_AP_SPIS_MISO 可选的mode +*/ +typedef enum +{ + PIN30_MODE_JTAG_TDO = 0, + PIN30_MODE_SPIS_MISO = 1, + PIN30_MODE_GPIO0 = 2, + PIN30_MODE_UART0_RX = 3, + PIN30_MODE_I2C1_SCL = 6, +} pin30_mode_e; + +/** +* @brief PIN31 IO_PAD_AP_SPIS_CSN 可选的mode +*/ +typedef enum +{ + PIN31_MODE_JTAG_TMS = 0, + PIN31_MODE_SPIS_CSN = 1, + PIN31_MODE_GPIO10 = 2, + PIN31_MODE_I2C02_SDA = 3, +} pin31_mode_e; + +/** +* @brief PIN32 IO_PAD_AP_SPIS_CLK 可选的mode +*/ +typedef enum +{ + PIN32_MODE_JTAG_TCK = 0, + PIN32_MODE_SPIS_SCLK = 1, + PIN32_MODE_GPIO9 = 2, + PIN32_MODE_I2C02_SCL = 3, +} pin32_mode_e; + +/** +* @brief PIN33 IO_PAD_AP_SPIS_MOSI 可选的mode +*/ +typedef enum +{ + PIN33_MODE_JTAG_TDI = 0, + PIN33_MODE_SPIS_MOSI = 1, + PIN33_MODE_GPIO1 = 2, + PIN33_MODE_UART0_TX = 3, + PIN33_MODE_I2C1_SDA_0 = 6, +} pin33_mode_e; + +/** +* @brief PIN34 PAD_AP_RST可选的mode +*/ +typedef enum +{ + PIN34_MODE_GPIO17 = 2, +} pin34_mode_e; + + +/** +* @brief PIN35 PAD_TD_INT可选的mode +*/ +typedef enum +{ + PIN35_MODE_GPIO22 = 2, +} pin35_mode_e; + + +/** +* @brief PIN36 PAD_UART_RX可选的mode +*/ +typedef enum +{ + PIN36_MODE_UART0_RX = 0, + PIN36_MODE_PWMO = 1, + PIN36_MODE_GPIO25 = 2, +} pin36_mode_e; + + + +//------------------------------------------------------------------------- +/** +* @brief PAD_SFC_CLK可选的mode 内部PAD +*/ +typedef enum +{ + IO_MODE_INTER_FC_CLK = 0, + IO_MODE_TSPIS_CLK_EN = 2, +} pad_sfc_clk_mode_e; + +/** +* @brief PAD_SFC_CSN可选的mode 内部PAD +*/ +typedef enum +{ + IO_MODE_INTER_FC_CSN = 0, + IO_MODE_TSPIS_CSN_EN = 2, +} pad_sfc_csn_mode_e; + +/** +* @brief PAD_SFC_IO0可选的mode 内部PAD +*/ +typedef enum +{ + IO_MODE_INTER_FC_IO0 = 0, + IO_MODE_TSPIS_IO0_EN = 2, +} pad_sfc_io0_mode_e; + +/** +* @brief PAD_SFC_IO1可选的mode 内部PAD +*/ +typedef enum +{ + IO_MODE_INTER_FC_IO1 = 0, + IO_MODE_TSPIS_IO1_EN = 2, +} pad_sfc_io1_mode_e; + +/** +* @brief PAD电压转换速率 +*/ +typedef enum +{ + IO_SLEW_RATE_SLOW = 0, + IO_SLEW_RATE_FAST = 1, +} pad_slew_rate_e; + +/******************************************************************************* +* IOE +*******************************************************************************/ +/** +* @brief GPIO io方向 +*/ +typedef enum +{ + IO_IOE_INPUT = 0, + IO_IOE_OUTPUT, + IO_IOE_NONE +} gpio_ioe_e; + +/** +* @brief GPIO level +*/ +typedef enum +{ + IO_LVL_LOW = 0, + IO_LVL_HIGH, + IO_LVL_NONE +} gpio_level_e; + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +/** +* @brief PAD与MODE的MAP结构体 +*/ +typedef struct +{ + io_pad_e pad; + uint8_t mode; + gpio_ioe_e ioe; + gpio_level_e lvl; +} io_pad_attr_t; + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief 配置指定PAD为GPIO mode，方向为input，指定中断触发方式 +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @param trig：4种中断触发方式，参考枚举类型sys_cfg_trigger_e +* @retval 无 +*/ +void hal_gpio_init_eint(io_pad_e pad, sys_cfg_trigger_e trig); + +/** +* @brief 注册GPIO中断回调函数 +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @param cb_func：回调函数地址 +* @param data：回调函数参数地址 +* @retval 无 +*/ +void hal_gpio_reg_eint_cb(io_pad_e pad, fcb_type cb_func); + +/** +* @brief 开关GPIO中断 +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @param state：开关控制 +* @retval 无 +*/ +void hal_gpio_ctrl_eint(io_pad_e pad, bool state); + +/** +* @brief 获取GPIO中断类型 +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @retval 无 +*/ +gpio_int_e hal_gpio_get_int_type(io_pad_e pad); + +/** +* @brief 配置指定PAD为GPIO mode，方向为output，指定初始电平 +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @param lvl：初始电平，参考枚举类型gpio_level_e +* @retval 无 +*/ +void hal_gpio_init_output(io_pad_e pad, gpio_level_e lvl); + +/** +* @brief 封装设置输出接口 +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @param lvl：初始电平，参考枚举类型gpio_level_e +* @retval 无 +*/ +void hal_gpio_set_output_data(io_pad_e pad, gpio_level_e lvl); + +/** +* @brief 配置指定PAD为GPIO mode，方向为input +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @retval 无 +*/ +void hal_gpio_init_input(io_pad_e pad); + +/** +* @brief 读取输入电平 +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @retval 无 +*/ +gpio_level_e hal_gpio_get_input_data(io_pad_e pad); + +/** +* @brief 设置io mode +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @param mode：工作模式，参考各PAD对应的mode枚举类型 +* @retval 无 +*/ +void hal_gpio_set_mode(io_pad_e pad, uint8_t mode); + +/** +* @brief 设置io 为高阻态 +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @retval 无 +*/ +void hal_gpio_set_high_impedance(io_pad_e pad); + +/** +* @brief 获取指定PAD的默认上拉、下拉状态 +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @param up_enable：默认上拉状态 +* @param down_enable：默认下拉状态 +* @retval 无 +*/ +void hal_gpio_get_pull_state(io_pad_e pad, bool *up_enable, bool *down_enable); + +/** +* @brief 配置指定PAD的默认上拉、下拉状态 +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @param up_enable：默认上拉状态 +* @param down_enable：默认下拉状态 +* @retval 无 +*/ +void hal_gpio_set_pull_state(io_pad_e pad, bool up_enable, bool down_enable); + +/** +* @brief 配置指定PAD是否为施密特触发 +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @param st_enable：1为施密特触发，0为正常触发 +* @retval 无 +*/ +void hal_gpio_set_schmitt_trigger(io_pad_e pad, bool st_enable); + +/** +* @brief 配置指定PAD的驱动能力 +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @param strength：驱动强度，取值为0~3 +* @retval 无 +*/ +void hal_gpio_set_driving_strength(io_pad_e pad, uint8_t strength); + +/** +* @brief 配置指定PAD的电压转换速率 +* @param pad：GPIO序号，参考枚举类型gpio_pad_e +* @param rate：驱动强度，取值为0~3 +* @retval 无 +*/ +void hal_gpio_set_slew_rate(io_pad_e pad, pad_slew_rate_e rate); + +/** +* @brief 配置AP_RSTN引脚中断 +* @param enable: 中断开关 +* @param cb_func：回调函数 +* @param trig：触发模式 +* @retval 无 +*/ +void hal_gpio_set_ap_reset_int(bool enable, fcb_type cb_func, sys_cfg_trigger_e trig); + +/** +* @brief 批量设置IO参数 +* @param attrs: PAD属性 +* @param size: 数组成员个数 +* @retval 无 +*/ +void hal_gpio_config_pad(io_pad_attr_t *attrs, uint8_t size); + +#endif /* __HAL_GPIO_H__ */ diff --git a/src/sdk/include/hal_i2c_master.h b/src/sdk/include/hal_i2c_master.h new file mode 100644 index 0000000..5e352da --- /dev/null +++ b/src/sdk/include/hal_i2c_master.h @@ -0,0 +1,134 @@ +/******************************************************************************* +* Copyright (C) 2021-2025, All Rights Reserved. +* +* File: hal_i2c_master.h +* Description hal i2c master模块接口头文件 +* Version V0.1 +* Date 2023-07-27 +* Author swx +*******************************************************************************/ +#ifndef __HAL_I2C_MASTER_H__ +#define __HAL_I2C_MASTER_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_device_datatype.h" +#include "tau_common.h" +#include "string.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief hal_i2cm_init +* @param index: I2Cx index +* @param slave_addr: 从机地址 +* @param addr_bits: 从机地址位数 +* @param i2c_m_speed_hz: 主机速率设置 +* @retval none +*/ +void hal_i2cm_init(i2c_index_e index, uint16_t slave_addr, uint8_t addr_bits, uint32_t i2cm_speed_hz); + +/** +* @brief hal_i2cm_deinit +* @param index: I2Cx index +* @retval none +*/ +void hal_i2cm_deinit(i2c_index_e index); + +/** +* @brief hal_i2cm_set_slave_addr +* @param index: I2Cx index +* @param slave_addr: 从机地址 +* @param addr_bits: 从机地址位数 +* @retval none +*/ +void hal_i2cm_set_slave_addr(i2c_index_e index, uint16_t slave_addr, uint8_t addr_bits); + +/** +* @brief i2c master 发送数据 +* @param index: I2Cx index +* @param tx_buffer: 发送数据buffer +* @param tx_size: 发送数据个数 +* @retval true/false: 成功/失败 +*/ +bool hal_i2cm_write(i2c_index_e index, const uint8_t *tx_buffer, uint32_t tx_size); + +/** +* @brief i2c master 接收数据 +* @param index: I2Cx index +* @param reg_address：寄存器地址 +* @param reg_size: 寄存器地址size +* @param rx_buffer: 接收数据buffer +* @param rx_size: 接收数据个数 +* @retval true/false: 成功/失败 +*/ +bool hal_i2cm_read(i2c_index_e index, uint32_t reg_address, size_t reg_size, uint8_t *rx_buffer, size_t rx_size); + +/** +* @brief i2c master 多地址参数接收数据 +* @param index: I2Cx index +* @param reg_address：寄存器地址 +* @param reg_size: 寄存器地址size +* @param rx_buffer: 接收数据buffer +* @param rx_size: 接收数据个数 +* @retval true/false: 成功/失败 +*/ +bool hal_i2cm_multi_params_read(i2c_index_e index, uint8_t *reg_address, size_t reg_size, uint8_t *rx_buffer, size_t rx_size); + +/** +* @brief i2c master dma 发送数据 +* @param index: I2Cx index +* @param tx_buffer: 发送数据buffer +* @param tx_size: 发送数据个数 +* @retval true: 数据已排入 DMA 通道，但不一定全部发送 +* false：发送出错，需要重新调用函数发送 +*/ +bool hal_i2cm_dma_write(i2c_index_e index, const uint8_t *tx_buffer, uint32_t tx_size); + +/** +* @brief i2c master dma 接收数据 +* @param index: I2Cx index +* @param reg_address：寄存器地址 +* @param reg_size: 寄存器地址size +* @param rx_buffer: 接收数据buffer +* @param rx_size: 接收数据个数 +* @retval true：寄存器地址发送成功，并已配置DMA接收通道，但不一定完成接收 +* false：接收出错，需要重新调用函数接收 +*/ +bool hal_i2cm_dma_read(i2c_index_e index, uint32_t reg_address, size_t reg_size, uint8_t *rx_buffer, size_t rx_size); + +/** +* @brief i2c master dma 多地址参数接收数据 +* @param index: I2Cx index +* @param reg_address：寄存器地址 +* @param reg_size: 寄存器地址size +* @param rx_buffer: 接收数据buffer +* @param rx_size: 接收数据个数 +* @retval true：寄存器地址发送成功，并已配置DMA接收通道，但不一定完成接收 +* false：接收出错，需要重新调用函数接收 +*/ +bool hal_i2cm_multi_params_dma_read(i2c_index_e index, uint8_t *reg_address, size_t reg_size, uint8_t *rx_buffer, size_t rx_size); + +/** +* @brief 获取 i2c master 发送状态 +* @param index: I2Cx index +* @retval true/false +*/ +bool hal_i2cm_get_transfer_complete(i2c_index_e index); + +#endif /* __HAL_I2C_MASTER_H__*/ + diff --git a/src/sdk/include/hal_i2c_slave.h b/src/sdk/include/hal_i2c_slave.h new file mode 100644 index 0000000..eaa69a9 --- /dev/null +++ b/src/sdk/include/hal_i2c_slave.h @@ -0,0 +1,156 @@ +/******************************************************************************* +* Copyright (C) 2021-2025, All Rights Reserved. +* +* File: hal_i2c_slave.h +* Description hal i2c slave模块接口头文件 +* Version V0.1 +* Date 2023-07-27 +* Author swx +*******************************************************************************/ +#ifndef __HAL_I2C_SLAVE_H__ +#define __HAL_I2C_SLAVE_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_device_datatype.h" +#include "tau_common.h" +#include "string.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +/** +* @brief i2cs event packet info +*/ +typedef struct hal_i2cs_packet_info_t +{ + uint8_t *rx_buffer; /* 接收buffer */ + uint32_t rx_buffer_size; /* 接收buffer size */ + const uint8_t *tx_buffer; /* 发送buffer */ + uint32_t tx_buffer_size; /* 发送buffer size */ + bool tx_circle; /* 发送circle mode */ + uint32_t packet_size; /* packet size : READ、RST、STOP中断事件时整个传输过程中I2CM发送packet的总量 */ +} hal_i2cs_packet_info_t; + +/** +* @brief i2cs event +*/ +typedef enum +{ + I2CS_EVENT_READ = 0, //发生 读请求 中断 + I2CS_EVENT_RST, //发生 restart 中断 + I2CS_EVENT_STOP //发生 stop 中断 +} hal_i2cs_event_e; + +typedef void (*hal_i2cs_cb)(i2c_index_e index, hal_i2cs_event_e event, size_t receive_num); + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief hal_i2cs_init +* @param index: I2Cx index +* @param slave_addr: 从机地址 +* @param addr_bits: 从机地址位数 +* @retval none +*/ +void hal_i2cs_init(i2c_index_e index, uint16_t slave_addr, uint8_t addr_bits); + +/** +* @brief hal_i2cs_deinit +* @param index: I2Cx index +* @retval none +*/ +void hal_i2cs_deinit(i2c_index_e index); + +/** +* @brief hal_i2cs_set_continue_transfer +* @param index: I2Cx index +* @param status: true/false +* @retval none +*/ +void hal_i2cs_set_continue_transfer(i2c_index_e index, bool status); + +/** +* @brief 获取i2c slave发送成功字节数 +* 注意这是通信过程i2c slave发送的数据量，如果更新了i2c slave的tx_buffer，则清零 +* @param index: I2Cx index +* @retval 发送总字节数 +*/ +uint32_t hal_i2cs_get_tx_cnt(i2c_index_e index); + +/** +* @brief 获取 i2c slave 接收数量 +* 注意这是通信过程i2c slave接收的数据量，如果更新了i2c slave的rx_buffer，则清零 +* @param index: I2Cx index +* @retval 数据接收数量 +*/ +uint32_t hal_i2cs_get_rx_cnt(i2c_index_e index); + +/** +* @brief 清零 i2c slave 接收数量 +* @param index: I2Cx index +* @retval none +*/ +void hal_i2cs_rx_cnt_clear(i2c_index_e index); + +/** +* @brief 获取 i2c slave 发送状态 +* @param index: I2Cx index +* @retval true：数据发送完成 +* false：数据还在发送 +*/ +bool hal_i2cs_get_write_complete(i2c_index_e index); + +/** +* @brief i2c slave 注册回调函数 +* @param index: I2Cx index +* @param cb：call back +* @retval +*/ +void hal_i2cs_register_callback(i2c_index_e index, hal_i2cs_cb cb); + +/** +* @brief i2c slave 配置接收buffer, 底层自动接收数据后调用callback +* @param index: I2Cx index +* @param rx_buffer：自动模式数据接收buffer +* @param rx_size: 自动模式数据接收buffer size +* @retval none +*/ +void hal_i2cs_update_rx_buffer(i2c_index_e index, uint8_t *rx_buffer, size_t rx_size); + +/** +* @brief i2c slave 配置自动发送buffer +* @param index: I2Cx index +* @param tx_buffer：自动模式数据发送buffer +* @param tx_size： 自动模式数据发收buffer size +* @param circle：circle mode，重复发送buffer的数据 +* @retval none +*/ +void hal_i2cs_update_tx_buffer(i2c_index_e index, const uint8_t *tx_buffer, uint32_t tx_size, bool circle); + +/** +* @brief i2c slave 启动 +* @param index: I2Cx index +* @retval none +*/ +void hal_i2cs_start(i2c_index_e index); + +/** +* @brief i2c slave 停止 +* @param index: I2Cx index +* @retval none +*/ +void hal_i2cs_stop(i2c_index_e index); + +#endif /* __HAL_I2C_SLAVE_H__*/ + diff --git a/src/sdk/include/hal_pwm.h b/src/sdk/include/hal_pwm.h new file mode 100644 index 0000000..cc8f876 --- /dev/null +++ b/src/sdk/include/hal_pwm.h @@ -0,0 +1,82 @@ +/******************************************************************************* +* +* +* File: hal_pwm.h +* Description： pwm HAL层头文件 +* Version： V0.1 +* Date： 2021-03-17 +* Author： jaya + *******************************************************************************/ +#ifndef __HAL_PWM_H__ +#define __HAL_PWM_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_device_datatype.h" +#include "tau_common.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief pwm 初始化 +* @param frequency: PWM 频率 < 30000 (30K) +* @param duty_step: 占空比调试阶数,与硬件相关,不能超过硬件限制（建议配置255） + 最大阶数 = (1000000000/130)/frequency，常见如下 + frequency, max step(最大step可配置) + { 30000, 255 } + { 4000, 1923} + { 3000, 2564} +* @retval true/false +*/ +bool hal_pwm_init(uint32_t frequency, uint32_t duty_step); + +/** +* @brief pwm 启动停止控制 +* @param enable: 启动/停止 +* @retval none +*/ +void hal_pwm_enable(bool enable); + +/** +* @brief pwm 设置占空比 +* @param duty_ratio: 占空比,范围为0 - duty_step(hal_pwm_init配置的参数) +* @retval none +*/ +void hal_pwm_set_duty(uint32_t duty_ratio); + +/** +* @brief pwm 配置从elvcc直接输出背光电源 +* @param enable: ELVCC输出启停 +* @retval none +*/ +bool hal_pwm_set_elvcc_output(bool enable); + +/** +* @brief 配置elvcc PWM 驱动背光能力,范围 0 - 15, capactiy为15时驱动能力最强,ELVCC输出电流最大 +* @param capacity: 0 - 15,hal_pwm_set_elvcc_output配置时会恢复默认值15 +* @retval none +*/ +void hal_pwm_set_elvcc_capacity(uint8_t capacity); + +/** +* @brief pwm 去初始化 +* @param none +* @retval true/false +*/ +bool hal_pwm_deinit(void); + +#endif /* __HAL_PWM_H__ */ diff --git a/src/sdk/include/hal_pwr.h b/src/sdk/include/hal_pwr.h new file mode 100644 index 0000000..3572bc8 --- /dev/null +++ b/src/sdk/include/hal_pwr.h @@ -0,0 +1,325 @@ +/******************************************************************************* +* +* +* File: hal_pwr.h +* Description： pwr hal层头文件 +* Version： V0.1 +* Date： 2023-07-21 +* Author： lyw + *******************************************************************************/ +#ifndef __HAL_PWR_H__ +#define __HAL_PWR_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_device_datatype.h" +#include "tau_common.h" +#include "hal_gpio.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +/** +* @brief IC主供电电源选择 +*/ +typedef enum +{ + PWR_SEL_IOV18 = 0, /* IC选择IOV18主供电(默认值) */ + PWR_SEL_TP18 = 1, /* IC选择TP18主供电 */ + PWR_SEL_VCC = 2, /* IC选择VCC主供电 */ + PWR_SEL_VDD13CP = 3, /* IC选择VDD13CP外接电源主供电*/ +} pwr_main_power_sel_e; + +/** +* @brief Sleep mode 供电模式 +*/ +typedef enum +{ + PWR_SLEEP_IN_NON = 0, /* Sleep Mode期间无外部供电(默认值) */ + PWR_SLEEP_IN_TP18 = 1, /* Sleep Mode期间TP18有电,其他电源掉电或不存在 */ + PWR_SLEEP_IN_VCC = 2, /* Sleep Mode期间VCC有电,其他电源掉电或不存在 */ + PWR_SLEEP_IN_VCC_TP18 = 3, /* Sleep Mode期间TP18与VCC有电,其他电源掉电或不存在 */ + PWR_SLEEP_IN_IOV18 = 4, /* Sleep Mode期间IOV18有电,其他电源掉电或不存在 */ + PWR_SLEEP_IN_IOV18_TP18 = 5, /* Sleep Mode期间IOV18与TP18有电,其他电源掉电或不存在 */ + PWR_SLEEP_IN_IOV18_VCC = 6, /* Sleep Mode期间IOV18与VCC有电,其他电源掉电或不存在 */ + PWR_SLEEP_IN_IOV18_VCC_TP18 = 7, /* Sleep Mode期间IOV18、TP18、VCC均有电,其他电源掉电或不存在 */ +} pwr_sleep_power_sel_e; + +/** +* @brief sleep mode 唤醒沿配置 +*/ +typedef enum +{ + WUP_RISING_EDGE = 2, /* 上升沿唤醒 */ + WUP_FALLING_EDGE = 3 /* 下降沿唤醒 */ +} pwr_wakeup_trigger_e; + +/** +* @brief 软件启动原因 +*/ +typedef enum +{ + RF_POWER_ON = 0, /* Power On,正常上电 */ + RF_CORE_RST = 1, /* 软件reset, 调用NVIC_SystemReset产生reset */ + RF_WDT_RST = 2, /* WDT reset */ + RF_CHIP_RST = 3, /* Chip reset,调用hal_system_reset_chip产生的reset */ + RF_APRSTN_WAKEUP = 4, /* deep sleep mode 下AP_RSTN reset */ + RF_TDINT_WAKEUP = 5 /* deep sleep mode 下TD_INT reset */ +} pwr_reset_flag_e; + +/** +* @brief pwr sleep mode type +* 不同sleep mode具体应用场景见《PWR说明文档》 +*/ +typedef enum +{ + PWR_NORMAL_SLEEP_MODE = 0, /* 待机下需要处理外设(I2C)等事件使用,调用hal_pwr_enter_normal_sleep_mode 进入,hal_pwr_exit_sleep_mode退出 */ + PWR_STOP_SLEEP_MODE = 1, /* 待机下需要通过任意GPIO唤醒时使用此模式,进入之前关闭所有模块以及MCU,通过hal_pwr_set_stop_sleep_wakeup_pin 注册GPIO中唤醒源,调用hal_pwr_enter_stop_sleep_mode 进入,hal_pwr_exit_sleep_mode退出 */ + PWR_DEEP_SLEEP_MODE = 2 /* 待机下只需要通过AP RSTN跟TD INT引脚唤醒使用时使用此模式,调用hal_pwr_enter_deep_sleep_mode 唤醒后重启,通过hal_pwr_get_reset_flag确定唤醒源 */ +} pwr_sleep_mode_e; + +/*! @brief HV LDO输出电压配置*/ +typedef enum _pwr_hv_ldo_e +{ + HV_LDO_0 = 0, /*1.20V*/ + HV_LDO_1 = 1, /*1.26V*/ + HV_LDO_2 = 2, /*1.32V*/ + HV_LDO_3 = 3, /*1.38V*/ + HV_LDO_4 = 4, /*1.44V*/ + HV_LDO_5 = 5, /*1.50V*/ + HV_LDO_6 = 6, /*1.56V*/ + HV_LDO_7 = 7, /*1.62V*/ + HV_LDO_8 = 8, /*1.68V*/ + HV_LDO_9 = 9, /*1.74V*/ + HV_LDO_10 = 10, /*1.80V*/ + HV_LDO_11 = 11, /*1.86V*/ + HV_LDO_12 = 12, /*2.04V*/ + HV_LDO_13 = 13, /*2.46V*/ + HV_LDO_14 = 14, /*3.00V*/ + HV_LDO_15 = 15, /*3.30V*/ +} pwr_hv_ldo_e; + +/*! @brief LDO 13S输出电压配置*/ +typedef enum _pwr_ldo_13s_e +{ + LDO_13S_0 = 0, /*1.22V*/ + LDO_13S_1 = 1, /*1.25V*/ + LDO_13S_2 = 2, /*1.27V*/ + LDO_13S_3 = 3, /*1.30V*/ + LDO_13S_4 = 4, /*1.33V*/ + LDO_13S_5 = 5, /*1.37V*/ + LDO_13S_6 = 6, /*1.40V*/ + LDO_13S_7 = 7, /*1.43V*/ +} pwr_ldo_13s_e; + +/*! @brief LDO 18S输出电压配置*/ +typedef enum _pwr_ldo_18s_e +{ + LDO_18S_0 = 0, /*1.61V*/ + LDO_18S_1 = 1, /*1.64V*/ + LDO_18S_2 = 2, /*1.67V*/ + LDO_18S_3 = 3, /*1.70V*/ + LDO_18S_4 = 4, /*1.74V*/ + LDO_18S_5 = 5, /*1.77V*/ + LDO_18S_6 = 6, /*1.80V*/ + LDO_18S_7 = 7, /*1.83V*/ +} pwr_ldo_18s_e; + +/*! @brief PWR PVD index */ +typedef enum +{ + PVD_IOVCC = 3, + PVD_VCI = 15, +} pwr_pvd_index_e; + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief IC主供电选择,如果是配置vcc主供电，可通过hal_pwr_get_vcc_power_ready获取电源状态 +* 注:上电只能配置一次,不可随意切换 +* @param power_sel 主供电选择,见枚举描述 +* @retval none +*/ +void hal_pwr_set_main_power(pwr_main_power_sel_e power_sel); + +/** +* @brief 获取VCC电源稳定状态,使用hal_pwr_set_main_power切换电源后,通过此接口获取电源稳定状态 +* eg: 使用hal_pwr_set_main_power切换至VCC主供电,在VCC电源接口上电之前,此接口返回值为false +* @param None +* @retval true-电源切换完成 false-电源未切换完成 +*/ +bool hal_pwr_get_vcc_power_ready(void); + +/** +* @brief 配置VCC开关,芯片启动默认打开VCC CP,不存在VCC的情况下可关闭 +* @param enable: true:打开CP, false:关闭CP +* @retval none +*/ +void hal_pwr_set_vcc_enable(bool enable); + +/** +* @brief sleep mode 期间电源情况配置 +* 调用sleep mode之前配置,根据配置情况在sleep mode自动切换电源 +* exit sleep mode后切换回hal_pwr_set_main_power的电源 +* @param powerin =000 息屏期间状态，IOV18掉电0，VCC掉电0，TP18也掉电0； +* @retval none +*/ +void hal_pwr_set_sleep_mode_power(pwr_sleep_power_sel_e power_sel); + +/** +* @brief 进入normal sleep mode 模式（详细使用方法见《PWR说明文档》） +* 待机下需要处理外设(I2C)等事件使用,图像通路关闭,MCU&外设正常运行 +* 调用hal_pwr_exit_sleep_mode退出 +* @param none +* @retval bool true/false +*/ +bool hal_pwr_enter_normal_sleep_mode(void); + +/** +* @brief 进入stop sleep mode 模式（详细使用方法见《PWR说明文档》） +* 待机下需要通过任意GPIO唤醒时使用此模式，进入之前关闭所有模块,通过hal_pwr_set_stop_sleep_wakeup_pin 注册GPIO中唤醒源。 +* 调用此接口后MCU会停止运行,等待中断唤醒后该函数才返回,调用hal_pwr_exit_sleep_mode真正退出stop sleep mode +* @param none +* @retval io_pad_e:唤醒接口 +*/ +io_pad_e hal_pwr_enter_stop_sleep_mode(void); + +/** +* @brief 注册 stop sleep mode 唤醒IO （详细使用方法见文档） +* @param pad ：Pin name +* @param trig：唤醒触发模式 +* @retval true/false +*/ +bool hal_pwr_set_stop_sleep_wakeup_pin(io_pad_e pad, pwr_wakeup_trigger_e trig); + +/** +* @brief 进入deep sleep mode 模式, 等待AP_RSTN 或者TD_INT 唤醒 +* 待机下只需要通过AP RSTN跟TD INT引脚唤醒使用时使用此模式，唤醒后重启,通过hal_pwr_get_reset_flag确定唤醒源 +* 注意, 如果需要使用deep sleep mode,TD INT引脚不能悬空,必须有上拉或者下拉保证确定电平,否则会导致误唤醒 +* @param polarity true:上升沿唤醒 false:下降沿唤醒 +* @retval none +*/ +void hal_pwr_enter_deep_sleep_mode(pwr_wakeup_trigger_e ap_rstn_trig, pwr_wakeup_trigger_e td_int_trig); + +/** +* @brief 退出sleep mode, normal/stop sleep mode都需要通过此接口退出 +* @param none +* @retval true/false +*/ +bool hal_pwr_exit_sleep_mode(void); + +/** +* @brief 获取系统复位原因 +* @param none +* @retval reset flag,见pwr_reset_flag_e +*/ +pwr_reset_flag_e hal_pwr_get_reset_flag(void); + +/** +* @brief 打开ELVCC作为供电电源 +* @param none +* @retval +*/ +void hal_pwr_elvcc_ldo_en(bool enable); + + +/** +* @brief +* @param HV LDO输出电压配置 + =0000：1.20V， + =0001：1.26V， + =0010：1.32V， + =0011：1.38V， + =0100：1.44V， + =0101：1.50V， + =0110：1.56V， + =0111：1.62V， + =1000：1.68V， + =1001：1.74V， + =1010：1.80V， + =1011：1.86V， + =1100：2.04V， + =1101：2.46V， + =1110：3.00V， + =1111：3.30V +* @retval none +*/ +void hal_pwr_elvcc_vol_set(pwr_hv_ldo_e voltage); + +/** +* @brief +* @param LDO18_S模块使能控制，=0关闭，默认关闭；=1开启 +* @retval none +*/ +void hal_pwr_ldo18s_en(bool enable); + + +/** +* @brief +* @param LDO18_S输出电压配置， + 000=1.61V + 001=1.64V + 010=1.67V + 011=1.70V + 100=1.74V + 101=1.77V + 110=1.80V + 111=1.83V +* @retval none +*/ +void hal_pwr_ldo18s_set(pwr_ldo_18s_e voltage); + +/** +* @brief +* @param LDO13_S模块使能控制，=0关闭，默认关闭；=1开启 +* @retval none +*/ +void hal_pwr_ldo13s_en(bool enable); + + +/** +* @brief +* @param LDO13_S输出电压配置， + 000=1.22V, + 001=1.25V, + 010=1.27V, + 011=1.30V, + 100=1.33V， + 101=1.37V， + 110=1.40V， + 111=1.43V +* @retval none +*/ +void hal_pwr_ldo13s_set(pwr_ldo_13s_e voltage); + +/** +* @brief PVD(电源检查)开关接口, +* PVD默认均为打开,注意!电源切换(如主供电切换,进出sleep mode)必须打开PVD! +* @param index: PVD选择 IOVCC/VCI +* @param enable: PVD开关 +* @retval none +*/ +void hal_pwr_set_pvd(pwr_pvd_index_e index, bool enable); + +/** +* @brief 使能TP18给VDD18供电 +* @warning info!!! 1:进入休眠的电源要选择TP18供电 eg： hal_pwr_set_sleep_mode_power(PWR_SLEEP_IN_TP18); +* @warning info!!! 2:唤醒之后，关闭改使能 eg： hal_pwr_sw_tp18_en(DISENABLE); +* @param enable: +* @retval none +*/ +void hal_pwr_sw_tp18_en(bool enable); + + + +#endif /* __HAL_PWR_H__ */ diff --git a/src/sdk/include/hal_spi_master.h b/src/sdk/include/hal_spi_master.h new file mode 100644 index 0000000..931ef5a --- /dev/null +++ b/src/sdk/include/hal_spi_master.h @@ -0,0 +1,93 @@ +/******************************************************************************* +* Copyright (C) 2021-2025, All Rights Reserved. +* +* File: hal_spi_master.h +* Description hal spi masrer模块头文件 +* Version V0.1 +* Date 2023-07-27 +* Author swx +*******************************************************************************/ +#ifndef __HAL_SPI_MASTER_H__ +#define __HAL_SPI_MASTER_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_device_datatype.h" +#include "tau_common.h" +#include "string.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ + +/** +* @brief 初始化spi master 模块 +* @param speed: 传输速度 +* @param cpha: 相位配置 +* @param cpol: 极性配置 +* @retval none +*/ +void hal_spim_init(uint32_t speed, uint8_t cpha, uint8_t cpol); + +/** +* @brief spi master 去初始化 +* @param none +* @retval none +*/ +void hal_spim_deinit(void); + +/** +* @brief spi master自定义CS脚 +* @param none +* @retval none +*/ +void hal_spim_set_csio_byself(bool enable); + +/** +* @brief 获取dma tx 传输状态 +* @param none +* @retval true:传输完成, false:传输数据中,不可操作spim接口 +*/ +bool hal_spim_get_transfer_complete(void); + +/** +* @brief spim flush fifo +* @param none +* @retval none +*/ +void hal_spim_flush(void); + +/** +* @brief spim 发送数据,函数返回即传输完成,阻塞函数 +* @param tx_buffer:tx buffer地址 +* @param tx_size: tx size +* @retval none +*/ +void hal_spim_write(const uint8_t *data_buffer, uint32_t data_size); + +/** +* @brief spi master读写数据,函数返回即传输完成,阻塞函数 +* @param cmd : 传输过程汇总需要发送command的地址 +* @param cmd_size: 传输过程汇总需要发送command的数据长度 +* @param rx_buffer:rx buffer地址 +* @param rx_size: rx buffer size +* @retval none +*/ +void hal_spim_read(const uint8_t *cmd, uint32_t cmd_size, uint8_t *data_buffer, uint32_t data_size); + + +#endif + diff --git a/src/sdk/include/hal_spi_slave.h b/src/sdk/include/hal_spi_slave.h new file mode 100644 index 0000000..97b90ba --- /dev/null +++ b/src/sdk/include/hal_spi_slave.h @@ -0,0 +1,217 @@ +/******************************************************************************* +* Copyright (C) 2021-2025, All Rights Reserved. +* +* File: hal_spi_slave.h +* Description hal spi slave 模块头文件 +* Version V0.1 +* Date 2023-07-27 +* Author swx +*******************************************************************************/ +#ifndef __HAL_SPI_SLAVE_H__ +#define __HAL_SPI_SLAVE_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_dsi_datatype.h" +#include "tau_common.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +/** +* @brief spi slave event type +*/ +typedef enum +{ + SPIS_EVENT_RCV_FULL = 0x2, /* 数据接收完全 */ + SPIS_EVENT_RCV_CNT = 0x4, /* 数据接收指定阈值 */ + SPIS_EVENT_RCV_CS_RISE = 0x40, /* CS上升沿 */ + SPIS_EVENT_RCV_CS_FALL = 0x80, /* CS下降沿 */ + SPIS_EVENT_ALL_MISS = 0X100, /* ALL MISS中断*/ +} hal_spis_event_e; + +/** +* @brief spi 硬件快速回复配置结构体 +*/ +typedef struct hal_spis_hw_ack_info_t +{ + uint8_t index; + uint8_t cmp_data[4]; /* 匹配最长4byte */ + uint8_t cmp_len; /* 0 - 3 */ + bool cmp_en; /* 匹配enable */ + uint8_t delay_clk; /* 匹配成功后延迟数据恢复的clk数量,最小设置0,延迟1 clk */ + uint8_t *ack_address; /* 匹配成功回复数据地址 */ + uint32_t ack_length; /* 匹配成功回复数据长度 */ +} hal_spis_hw_ack_info_t; + +/** +* @brief spi 事件 packet info +*/ +typedef struct hal_spis_packet_info_t +{ + uint8_t *rx_buffer; /* 接收buffer */ + uint32_t rx_buffer_size; /* 接收buffer size */ + const uint8_t *tx_buffer; /* 发送buffer */ + uint32_t tx_buffer_size; /* 发送buffer size */ + bool tx_circle; /* 发送circle mode */ + uint32_t packet_size; /* packet size : RCV FULL事件 = rx buffer size, CS_RISE事件时为整个传输过程中SPIM发送packet的总量 */ +} hal_spis_packet_info_t; + +typedef void (*hal_spis_cb)(hal_spis_event_e event, hal_spis_packet_info_t *packet_info); + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/* +SPIS启动流程: +1：hal_spis_init +2：hal_spis_update_rx_buffer & hal_spis_update_tx_buffer +3：hal_spis_register_callback +4：hal_spis_start +等待回调函数并从packet_info获取数据 + +Event: +SPI_EVENT_RCV_FULL,表示RX buffer接收满 , packet_info.packet_size = rx_buffer_size +SPI_EVENT_RCV_CS_HIGH,表示CS 拉高,一帧传输数据结束，此时packet_info.packet_size 为当前packet传输的所有byte数量 + +有可能存在只有SPI_EVENT_RCV_CS_HIGH而没有SPI_EVENT_RCV_FULL的情况,此时表示SPIM发送的数据不足于填满RX buffer +eg: rx_buffer_size = 10, SPIM实际只发送了2byte数据 + +接收到SPI_EVENT_RCV_CS_HIGH后可通过hal_spis_update_tx_buffer更新下一帧需要发送的数据 +也可以通过hal_spis_update_rx_buffer更新接收数据的buffer + +*/ + +/** +* @brief 初始化spi slave 模块 +* @param cpha: 相位配置 +* @param cpol: 极性配置 +* @param +* @retval none +*/ +void hal_spis_init(uint8_t cpha, uint8_t cpol); + +/** +* @brief spi slave 模块去初始化 +* @param none +* @retval none +*/ +void hal_spis_deinit(void); + +/** +* @brief spi slave 注册回调函数 +* @param cb：call back +* @param event_mask：接收事件掩码(eg:SPIS_EVENT_RCV_FULL|SPIS_EVENT_RCV_CS_RISE) +* @param data_intcnt：SPIS_EVENT_RCV_CNT事件触发参数,当rx buffer接收到data_intcnt数据时.产生RCV_CNT事件 +* @retval +*/ +void hal_spis_register_callback(hal_spis_cb cb, uint32_t event_mask, uint16_t data_intcnt); + +/** +* @brief spi slave 设置RX DMA传输数据中断阈值 +* @param data_intcnt：SPIS_EVENT_RCV_CNT事件触发参数,当rx buffer接收到data_intcnt数据时.产生RCV_CNT事件 +* @retval none +*/ +void hal_spis_set_rx_dma_intcnt(uint16_t data_intcnt); + +/** +* @brief spi slave 配置接收buffer, 底层自动接收数据后调用callback +* @param buffer：自动模式数据接收buffer +* @param size： 自动模式数据接收buffer size +* @retval +*/ +void hal_spis_update_rx_buffer(uint8_t *buffer, uint32_t size); + +/** +* @brief spi slave 配置自动发送buffer +* @param buffer：自动模式数据发送buffer +* @param size： 自动模式数据发收buffer size +* @param circle：circle mode，重复发送buffer的数据 +* @retval +*/ +void hal_spis_update_tx_buffer(const uint8_t *buffer, uint32_t size, bool circle); + +/** +* @brief spi slave 启动 +* @param none +* @retval +*/ +void hal_spis_start(void); + +/** +* @brief spi slave 停止 +* @param none +* @retval true/false +*/ +void hal_spis_stop(void); + +/** +* @brief spi slave flush fifo +* @param none +* @retval true/false +*/ +void hal_spis_flush(void); + +/** +* @brief 获取SPIS busy状态 +* @param none +* @retval true: CS拉低状态, false:CS拉高状态 +*/ +bool hal_spis_busy(void); + +/** +* @brief 读取rx fifo缓冲数据 +* @param buffer:读取数据的缓冲区 +* @param count:需要读取的字节数 +* @retval uint8_t:实际读取的字节数 +*/ +uint8_t hal_spis_read_data(uint8_t *buffer, uint8_t count); + +/** +* @brief spi slave cpu写一个数据 +* @param data:写的数据 +* @retval true/false +*/ +bool hal_spis_write_data(uint8_t data); + +/** +* @brief 获取rx fifo状态 +* @param none +* @retval true/false +*/ +bool hal_spis_get_rxfifo(void); + +/** +* @brief 设置SPIS硬件快速回复功能使能状态 +* @param en:硬件快速回复功能使能 +* @param header_default:硬件快速回复功能的默认回复值 +* @retval none +*/ +void hal_spis_set_hw_ack_enable(bool en, uint8_t header_default); + +/** +* @brief 获取SPIS硬件快速回复功能使能状态 +* @param void +* @retval bool +*/ +bool hal_spis_get_hw_ack_enable(void); + +/** +* @brief 设置SPIS硬件快速回复header参数 +* @param info:spi硬件快速回复配置结构体数组 +* @param size:设置size组参数 +* @retval none +*/ +void hal_spis_set_hw_ack_info(hal_spis_hw_ack_info_t *info, uint8_t size); + +#endif /* __HAL_SPI_SLAVE_H__*/ + diff --git a/src/sdk/include/hal_swire.h b/src/sdk/include/hal_swire.h new file mode 100644 index 0000000..2d5ff35 --- /dev/null +++ b/src/sdk/include/hal_swire.h @@ -0,0 +1,90 @@ +/******************************************************************************* +* +* +* File: hal_swire.h +* Description： swire HAL层头文件 +* Version： V0.1 +* Date： 2021-03-17 +* Author： jaya + *******************************************************************************/ +#ifndef __HAL_SWIRE_H__ +#define __HAL_SWIRE_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_device_datatype.h" +#include "tau_common.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief SWIRE初始化 +* @param 无 +* @retval 无 +*/ +void hal_swire_init(void); + +/** +* @brief SWIRE去初始化 +* @param 无 +* @retval 无 +*/ +void hal_swire_deinit(void); + +/** +* @brief 配置SWIRE波形 +* @param start_time：起始时长，单位us +* @param stop_time：结束时长，单位us，必须大于300us +* @param high_time：高电平时长，单位us +* @param low_time：低电平时长，单位us +* @retval 无 +*/ +void hal_swire_set_waveform(uint32_t start_time, uint32_t stop_time, + uint32_t high_time, uint32_t low_time); + + +/** +* @brief 配置SWIRE脉冲个数 +* @param pulse：脉冲数 +* @retval 无 +*/ +void hal_swire_set_pulse(uint32_t pulse); + +/** +* @brief 开关swire输出,不绑定timer的情况下,每次调用hal_swire_set_pulse产生一个swire波形 +* @param state：开关控制 +* @retval 无 +*/ +void hal_swire_enable(bool state); + +/** +* @brief 配置swire选择的timer +* @param timer_num_e index：定时器编号 +* @param uint32_t ms：超时时间 +* @param repeat :是否重复 +* @retval 无 +*/ +void hal_swire_set_timer(timer_num_e index, uint32_t ms, bool repeat); + +/** +* @brief 注册回调函数,每次swire 发送完成后会产生回调 +* @param cb_func：回调函数地址 +* @retval 无 +*/ +void hal_swire_register_callback(fcb_type cb_func); + +#endif /* __HAL_SWIRE_H__ */ diff --git a/src/sdk/include/hal_system.h b/src/sdk/include/hal_system.h new file mode 100644 index 0000000..26df5c5 --- /dev/null +++ b/src/sdk/include/hal_system.h @@ -0,0 +1,114 @@ +/******************************************************************************* +* +* +* File: hal_system.h +* Description hal 通用系统接口头文件 +* Version V0.1 +* Date 2021-05-21 +* Author lzy + *******************************************************************************/ +#ifndef __HAL_SYSTEM_H__ +#define __HAL_SYSTEM_H__ +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_common.h" +#include "hal_gpio.h" +#include "tau_log.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +/** +* @brief 系统时钟配置 +*/ +typedef enum +{ + HAL_SYSCLK_80M = 80000000, + HAL_SYSCLK_100M = 100000000, + HAL_SYSCLK_150M = 150000000 +} hal_system_clk_e; + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ + +/** +* @brief system 初始化 +* @param sysclk:系统时钟 +* @retval none +*/ +void hal_system_init(hal_system_clk_e sysclk); + +/** +* @brief mcu进入idle模式,等待中断唤醒 +* @param disable_systick: 进入idle时是否关闭systick(退出idle 恢复systick) +* @retval none +*/ +void hal_system_idle_mode(bool disable_systick); + +/** +* @brief 注册systick回调函数 +* @param cb_func：回调函数地址 +* @retval 无 +*/ +void hal_system_register_systick_cb(fcb_type cb_func); + +/** +* @brief 启动sys tickt +* @param ms: sys tickt 间隔, 范围1-10ms +* @retval true/false +*/ +bool hal_system_enable_systick(uint8_t ms); + +/** +* @brief 获取systickt +* @param none +* @retval 当前systickt值 +*/ +bool hal_system_disable_systick(void); + +/** +* @brief 获取systickt +* @param none +* @retval 当前systickt值 +*/ +uint32_t hal_system_get_tick(void); + +/** +* @brief reset chip +* @param none +* @retval none +*/ +void hal_system_reset_chip(void); + +/** +* @brief 获取上位机设置的debug state(debug only) +* @param none +* @retval debug state +*/ +uint32_t hal_system_get_debug_state(void); + +/** +* @brief clear debug state(debug only) +* @param none +* @retval none +*/ +void hal_system_clear_debug_state(void); + +/** +* @brief 更新MCU时钟 +* @param sysclk:系统时钟 +* @retval true/false +*/ +bool hal_system_updata_sysclk(hal_system_clk_e sysclk); + +#endif //__HAL_SYSTEM_H__ diff --git a/src/sdk/include/hal_timer.h b/src/sdk/include/hal_timer.h new file mode 100644 index 0000000..f73566b --- /dev/null +++ b/src/sdk/include/hal_timer.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* +* +* File: hal_timer.h +* Description： timer HAL层头文件 +* Version： V0.1 +* Date： 2021-03-16 +* Author： jaya + *******************************************************************************/ +#ifndef __HAL_TIMER_H__ +#define __HAL_TIMER_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_device_datatype.h" +#include "tau_common.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief 指定定时器初始化 +* @param index：实例序号(0~3)，参考枚举类型timer_num_e +* @retval None +*/ +void hal_timer_init(timer_num_e index); + +/** +* @brief 指定定时器反初始化 +* @param index：实例序号(0~3)，参考枚举类型timer_num_e +* @retval None +*/ +void hal_timer_deinit(timer_num_e index); + +/** +* @brief 启动指定定时器 +* @param index：实例序号(0~3)，参考枚举类型timer_num_e +* @param ms：超时时间，单位ms。由于应用场景一般是ms级别的，应用开发不需要计数具体时针数， + 故直接输入时间，在接口内部换算成时钟数进行寄存器设置。 +* @param cb_func：回调函数地址，不需要则填NULL +* @param data：回调函数的参数地址，不需要则填NULL +* @retval None +*/ +void hal_timer_start(timer_num_e index, uint32_t ms, fcb_type cb_func, void *data); + +/** +* @brief 启动指定定时器 +* @param index：实例序号(0~3)，参考枚举类型timer_num_e +* @param us：超时时间，单位us。由于应用场景一般是us级别的，应用开发不需要计数具体时针数， + 故直接输入时间，在接口内部换算成时钟数进行寄存器设置。 +* @param cb_func：回调函数地址，不需要则填NULL +* @param data：回调函数的参数地址，不需要则填NULL +* @retval None +*/ +void hal_timer_start_ex(timer_num_e index, uint32_t us, fcb_type cb_func, void *data); + +/** +* @brief 停止指定定时器 +* @param index：实例序号(0~3)，参考枚举类型timer_num_e +* @retval None +*/ +void hal_timer_stop(timer_num_e index); + +/** +* @brief 设置定时器是否循环超时 +* @param index：实例序号(0~3)，参考枚举类型timer_num_e +* @param bool enable：循环超时使能 +* @retval None +*/ +void hal_timer_set_repeat(timer_num_e index, bool repeat); + +/** +* @brief 获取指定指示器状态 +* @param index：实例序号(0~3)，参考枚举类型timer_num_e +* @retval 参考timer_status_e +*/ +timer_status_e hal_timer_get_status(timer_num_e index); + +#endif /* __HAL_TIMER_H__ */ diff --git a/src/sdk/include/hal_uart.h b/src/sdk/include/hal_uart.h new file mode 100644 index 0000000..4760521 --- /dev/null +++ b/src/sdk/include/hal_uart.h @@ -0,0 +1,164 @@ +/******************************************************************************* +* +* +* File: hal_uart.h +* Description +* Version V0.1 +* Date 2021-11-24 +* Author kc +*******************************************************************************/ + +#ifndef __HAL_UART_H__ +#define __HAL_UART_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_device_datatype.h" + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +/** +* @brief UART停止位 +*/ +typedef enum +{ + HAL_UART_STOPBIT_1 = 0, + HAL_UART_STOPBIT_1P5 = 1, + HAL_UART_STOPBIT_2 = 1 +} hal_uart_stopbit_e; + +/** +* @brief UART极性 +*/ +typedef enum +{ + HAL_UART_PARITY_NO = 0, + HAL_UART_PARITY_ODD = 0x01, + HAL_UART_PARITY_EVEN = 0x03, +} hal_uart_parity_e; + +/** +* @brief UART数据宽度 +*/ +typedef enum +{ + HAL_UART_DATAWIDTH_5 = 0, + HAL_UART_DATAWIDTH_6 = 1, + HAL_UART_DATAWIDTH_7 = 2, + HAL_UART_DATAWIDTH_8 = 3 +} hal_uart_datawidth_e; + +/** +* @brief UART编号 +*/ +typedef enum +{ + HAL_UART_0, + HAL_UART_1, + HAL_UART_MAX +} hal_uart_num_e; + +typedef struct +{ + uint32_t baudrate; + hal_uart_stopbit_e stopbits; + hal_uart_datawidth_e data_width; + hal_uart_parity_e parity; + uart_trans_cb callback; + void *user_data; +} hal_uart_config_t; + +/** +* @brief UART DMA 通道TX/RX方向选择 +*/ +typedef enum +{ + HAL_UART0_DMA_PATH_TX, + HAL_UART0_DMA_PATH_RX, + HAL_UART1_DMA_PATH_TX, + HAL_UART1_DMA_PATH_RX, + HAL_UART_DMA_PATH_MAX +} hal_uart_dma_path_e; +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief 初始化设置uart 传输的波特率、位宽等参数 +* @param hal_uart_config_t +* @retval hal_uart_status +*/ +void hal_uart_init(hal_uart_num_e num, hal_uart_config_t *huart); + +/** +* @brief 关闭uart口 +* @retval 无 +*/ +void hal_uart_deinit(hal_uart_num_e num); + +/** +* @brief 阻塞式发送数据 +* @param pdata:传输数据指针 +* @param size:传输数据大小 +* @retval hal_uart_status +*/ +bool hal_uart_send_blocking(hal_uart_num_e num, uint8_t *pdata, uint16_t size); + +/** +* @brief 阻塞式接收数据 +* @param pdata:传输数据指针 +* @param size:传输数据大小 +* @retval hal_uart_status +*/ +bool hal_uart_recv_blocking(hal_uart_num_e num, uint8_t *pdata, uint16_t size); + +/** +* @brief 中断非阻塞式发送数据 +* @param pdata:传输数据指针 +* @param size:传输数据大小 +* @retval 状态 +*/ +bool hal_uart_send_none_blocking(hal_uart_num_e num, uint8_t *pdata, uint16_t size); + +/** +* @brief 中断非阻塞式接收数据 +* @param pdata:传输数据指针 +* @param size:传输数据大小 +* @retval hal_uart_status +*/ +bool hal_uart_recv_none_blocking(hal_uart_num_e num, uint8_t *pdata, uint16_t size); + +/** +* @brief 使用DMA通道发送数据 +* @param num: 串口编号 串口0或串口1 +* @param pdata:传输数据指针 +* @param size:传输数据大小 +* @retval true or false +*/ +bool hal_uart_dma_send(hal_uart_num_e num, uint8_t *pdata, uint16_t size); + +/** +* @brief 使用DMA接收数据 +* @param num: 串口编号 串口0或串口1 +* @param pdata:传输数据指针 +* @param size:传输数据大小 +* @retval true or false +*/ +bool hal_uart_dma_recv(hal_uart_num_e num, uint8_t *pdata, uint16_t size); + +/** +* @brief UART DMA通道不再使用后关闭释放UART DMA资源 +* @param path:TX通道或RX通道 +* @retval void +*/ +void hal_uart_dma_path_close(hal_uart_dma_path_e path); +#endif /* __HAL_UART_H__ */ diff --git a/src/sdk/include/hal_wdg.h b/src/sdk/include/hal_wdg.h new file mode 100644 index 0000000..8e40ee3 --- /dev/null +++ b/src/sdk/include/hal_wdg.h @@ -0,0 +1,94 @@ +/******************************************************************************* +* +* +* File: hal_wdg.h +* Description： wdg HAL层头文件 +* Version： V0.1 +* Date： 2021-03-16 +* Author： jaya + *******************************************************************************/ +#ifndef __HAL_WDG_H__ +#define __HAL_WDG_H__ + +/******************************************************************************* +* 1.Included files +*******************************************************************************/ +#include "tau_device_datatype.h" +#include "tau_common.h" + + +/******************************************************************************* +* 2.Global constant and macro definitions using #define +*******************************************************************************/ + +/******************************************************************************* +* 3.Global structures, unions and enumerations using typedef +*******************************************************************************/ +/*! + * @brief watch dog模式 + */ +typedef enum +{ + WDG_MODE_RESET = 0, //复位模式，跑飞复位 + WDG_MODE_INTERRUPT = 1 //中断模式，跑飞进入中断 +} wdg_mode_e; + +/******************************************************************************* +* 4.Global variable extern declarations +*******************************************************************************/ + +/******************************************************************************* +* 5.Global function prototypes +*******************************************************************************/ +/** +* @brief 看门狗初始化 +* @param 无 +* @retval 无 +*/ +void hal_wdg_init(void); + +/** +* @brief 看门狗反初始化 +* @param 无 +* @retval 无 +*/ +void hal_wdg_deinit(void); + +/** +* @brief 启动看门狗 +* @param wdg_mode_e modeSel: 复位或中断模式 +* @param uint32_t load: 超时时间，单位ms +* @retval 无 +*/ +void hal_wdg_start(wdg_mode_e modeSel, uint32_t load); + +/** +* @brief 停止看门狗 +* @param 无 +* @retval 无 +*/ +void hal_wdg_stop(void); + +/** +* @brief 设置WDG是否循环超时 +* @param enable：循环超时使能 +* @retval 无 +*/ +void hal_wdg_set_repeat(bool repeat); + +/** +* @brief 注册中断回调函数 +* @param cb_func：回调函数地址 +* @param data：回调参数地址 +* @retval 无 +*/ +void hal_wdg_register_callback(fcb_type cb_func, void *data); + +/** +* @brief 喂狗 +* @param 无 +* @retval 无 +*/ +void hal_wdg_kick_dog(void); + +#endif /* __HAL_WDG_H__ */ diff --git a/src/sdk/sdk_version.h b/src/sdk/sdk_version.h new file mode 100644 index 0000000..398c0e5 --- /dev/null +++ b/src/sdk/sdk_version.h @@ -0,0 +1 @@ +#define SDK_REVISION 6000 \ No newline at end of file