;/**************************************************************************//**
; * @file startup_ARMCM0.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0 Device
; * @version V5.4.0
; * @date 12. December 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; Stack Configuration
; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
; Heap Configuration
; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;
Heap_Size EQU 0x00000C00
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD VIDC_IRQn_Handler ; 0 Interrupt 0
DCD LCDC_IRQn_Handler ; 1 Interrupt 1
DCD MIPI_RX_IRQn_Handler ; 2 Interrupt 2
DCD MIPI_TX_IRQn_Handler ; 3 Interrupt 3
DCD MEMC_IRQn_Handler ; 4 Interrupt 4
DCD VPRE_IRQn_Handler ; 5 Interrupt 5
DCD FLSCTRL_IRQn_Handler ; 6 Interrupt 6
DCD DMA_IRQn_Handler ; 7 Interrupt 7
DCD TIMER0_IRQn_Handler ; 8 Interrupt 8
DCD TIMER1_IRQn_Handler ; 9 Interrupt 9
DCD TIMER2_IRQn_Handler ; 10 Interrupt 10
DCD TIMER3_IRQn_Handler ; 11 Interrupt 11
DCD WDG_IRQn_Handler ; 12 Interrupt 12
DCD UART_IRQn_Handler ; 13 Interrupt 13
DCD I2C0_IRQn_Handler ; 14 Interrupt 14
DCD I2C1_IRQn_Handler ; 15 Interrupt 15
DCD SPIS_IRQn_Handler ; 16 Interrupt 16
DCD SPIM_IRQn_Handler ; 17 Interrupt 17
DCD ADC_IRQn_Handler ; 18 Interrupt 18
DCD PWMDET_IRQn_Handler ; 19 Interrupt 19
DCD OTP_IRQn_Handler ; 20 Interrupt 20
DCD SWIRE_IRQn_Handler ; 21 Interrupt 21
DCD PVD_IRQn_Handler ; 22 Interrupt 22
DCD AP_NRESET_IRQn_Handler ; 23 Interrupt 23
DCD EXTI_INT0_IRQn_Handler ; 24 Interrupt 24
DCD EXTI_INT1_IRQn_Handler ; 25 Interrupt 25
DCD EXTI_INT2_IRQn_Handler ; 26 Interrupt 26
DCD EXTI_INT3_IRQn_Handler ; 27 Interrupt 27
DCD EXTI_INT4_IRQn_Handler ; 28 Interrupt 28
DCD EXTI_INT5_IRQn_Handler ; 29 Interrupt 29
DCD EXTI_INT6_IRQn_Handler ; 30 Interrupt 30
DCD EXTI_INT7_IRQn_Handler ; 31 Interrupt 31
SPACE ( 0 * 4) ; Interrupts 10 .. 31 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
_NVIC_ICER0 EQU 0xE000E180 ;清中断使能寄存器地址
_NVIC_ICPR0 EQU 0xE000E280 ;清中断pending寄存器地址
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
;清中断使能和pending ——开始——
CPSID I ; 屏蔽中断
LDR R0, =_NVIC_ICER0
LDR R1, =_NVIC_ICPR0
LDR R2, =0xFFFFFFFF
MOVS R3, #1 ; 设置循环次数 M0只有1组(32个)中断，故只需要循环1次
_irq_clear
;CBZ R3, _irq_clear_end
CMP R3,#0 ; 循环次数等于0，跳转到_irq_clear_end
BEQ _irq_clear_end
STR R2, [R0] ;,#4 ; NVIC_ICER0 - 清 enable IRQ 寄存器
STR R2, [R1] ;,#4 ; NVIC_ICPR0 - 清 pending IRQ 寄存器
SUBS R3, #1 ; 循环数自减1
B _irq_clear
_irq_clear_end
;清中断使能和pending ——结束——
CPSIE I ; 开启中断
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler VIDC_IRQn_Handler
Set_Default_Handler LCDC_IRQn_Handler
Set_Default_Handler MIPI_RX_IRQn_Handler
Set_Default_Handler MIPI_TX_IRQn_Handler
Set_Default_Handler MEMC_IRQn_Handler
Set_Default_Handler VPRE_IRQn_Handler
Set_Default_Handler FLSCTRL_IRQn_Handler
Set_Default_Handler DMA_IRQn_Handler
Set_Default_Handler TIMER0_IRQn_Handler
Set_Default_Handler TIMER1_IRQn_Handler
Set_Default_Handler TIMER2_IRQn_Handler
Set_Default_Handler TIMER3_IRQn_Handler
Set_Default_Handler WDG_IRQn_Handler
Set_Default_Handler UART_IRQn_Handler
Set_Default_Handler I2C0_IRQn_Handler
Set_Default_Handler I2C1_IRQn_Handler
Set_Default_Handler SPIS_IRQn_Handler
Set_Default_Handler SPIM_IRQn_Handler
Set_Default_Handler ADC_IRQn_Handler
Set_Default_Handler PWMDET_IRQn_Handler
Set_Default_Handler OTP_IRQn_Handler
Set_Default_Handler SWIRE_IRQn_Handler
Set_Default_Handler PVD_IRQn_Handler
Set_Default_Handler AP_NRESET_IRQn_Handler
Set_Default_Handler EXTI_INT0_IRQn_Handler
Set_Default_Handler EXTI_INT1_IRQn_Handler
Set_Default_Handler EXTI_INT2_IRQn_Handler
Set_Default_Handler EXTI_INT3_IRQn_Handler
Set_Default_Handler EXTI_INT4_IRQn_Handler
Set_Default_Handler EXTI_INT5_IRQn_Handler
Set_Default_Handler EXTI_INT6_IRQn_Handler
Set_Default_Handler EXTI_INT7_IRQn_Handler
ALIGN
; User setup Stack & Heap
IF :LNOT::DEF:__MICROLIB
IMPORT __use_two_region_memory
ENDIF
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END