227 lines
9.8 KiB
ArmAsm
227 lines
9.8 KiB
ArmAsm
;/**************************************************************************//**
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; * @file startup_ARMCM0.s
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; * @brief CMSIS Core Device Startup File for
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; * ARMCM0 Device
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; * @version V5.4.0
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; * @date 12. December 2018
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; ******************************************************************************/
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;/*
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; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Licensed under the Apache License, Version 2.0 (the License); you may
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; * not use this file except in compliance with the License.
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; * You may obtain a copy of the License at
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; *
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; * www.apache.org/licenses/LICENSE-2.0
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; *
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; * Unless required by applicable law or agreed to in writing, software
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; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; * See the License for the specific language governing permissions and
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; * limitations under the License.
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; */
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;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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;<h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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;</h>
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Stack_Size EQU 0x00001000
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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__stack_limit
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Stack_Mem SPACE Stack_Size
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__initial_sp
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;<h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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;</h>
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Heap_Size EQU 0x00000C00
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IF Heap_Size != 0 ; Heap is provided
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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ENDIF
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; -14 NMI Handler
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DCD HardFault_Handler ; -13 Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; -5 SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; -2 PendSV Handler
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DCD SysTick_Handler ; -1 SysTick Handler
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; Interrupts
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DCD VIDC_IRQn_Handler ; 0 Interrupt 0
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DCD LCDC_IRQn_Handler ; 1 Interrupt 1
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DCD MIPI_RX_IRQn_Handler ; 2 Interrupt 2
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DCD MIPI_TX_IRQn_Handler ; 3 Interrupt 3
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DCD MEMC_IRQn_Handler ; 4 Interrupt 4
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DCD VPRE_IRQn_Handler ; 5 Interrupt 5
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DCD FLSCTRL_IRQn_Handler ; 6 Interrupt 6
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DCD DMA_IRQn_Handler ; 7 Interrupt 7
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DCD TIMER0_IRQn_Handler ; 8 Interrupt 8
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DCD TIMER1_IRQn_Handler ; 9 Interrupt 9
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DCD TIMER2_IRQn_Handler ; 10 Interrupt 10
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DCD TIMER3_IRQn_Handler ; 11 Interrupt 11
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DCD WDG_IRQn_Handler ; 12 Interrupt 12
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DCD UART_IRQn_Handler ; 13 Interrupt 13
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DCD I2C0_IRQn_Handler ; 14 Interrupt 14
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DCD I2C1_IRQn_Handler ; 15 Interrupt 15
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DCD SPIS_IRQn_Handler ; 16 Interrupt 16
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DCD SPIM_IRQn_Handler ; 17 Interrupt 17
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DCD ADC_IRQn_Handler ; 18 Interrupt 18
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DCD PWMDET_IRQn_Handler ; 19 Interrupt 19
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DCD OTP_IRQn_Handler ; 20 Interrupt 20
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DCD SWIRE_IRQn_Handler ; 21 Interrupt 21
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DCD PVD_IRQn_Handler ; 22 Interrupt 22
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DCD AP_NRESET_IRQn_Handler ; 23 Interrupt 23
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DCD EXTI_INT0_IRQn_Handler ; 24 Interrupt 24
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DCD EXTI_INT1_IRQn_Handler ; 25 Interrupt 25
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DCD EXTI_INT2_IRQn_Handler ; 26 Interrupt 26
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DCD EXTI_INT3_IRQn_Handler ; 27 Interrupt 27
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DCD EXTI_INT4_IRQn_Handler ; 28 Interrupt 28
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DCD EXTI_INT5_IRQn_Handler ; 29 Interrupt 29
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DCD EXTI_INT6_IRQn_Handler ; 30 Interrupt 30
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DCD EXTI_INT7_IRQn_Handler ; 31 Interrupt 31
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SPACE ( 0 * 4) ; Interrupts 10 .. 31 are left out
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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_NVIC_ICER0 EQU 0xE000E180 ;清中断使能寄存器地址
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_NVIC_ICPR0 EQU 0xE000E280 ;清中断pending寄存器地址
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT __main
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;清中断使能和pending ——开始——
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CPSID I ; 屏蔽中断
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LDR R0, =_NVIC_ICER0
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LDR R1, =_NVIC_ICPR0
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LDR R2, =0xFFFFFFFF
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MOVS R3, #1 ; 设置循环次数 M0只有1组(32个)中断，故只需要循环1次
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_irq_clear
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;CBZ R3, _irq_clear_end
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CMP R3,#0 ; 循环次数等于0，跳转到_irq_clear_end
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BEQ _irq_clear_end
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STR R2, [R0] ;,#4 ; NVIC_ICER0 - 清 enable IRQ 寄存器
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STR R2, [R1] ;,#4 ; NVIC_ICPR0 - 清 pending IRQ 寄存器
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SUBS R3, #1 ; 循环数自减1
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B _irq_clear
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_irq_clear_end
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;清中断使能和pending ——结束——
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CPSIE I ; 开启中断
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LDR R0, =__main
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BX R0
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ENDP
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; Macro to define default exception/interrupt handlers.
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; Default handler are weak symbols with an endless loop.
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; They can be overwritten by real handlers.
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MACRO
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Set_Default_Handler $Handler_Name
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$Handler_Name PROC
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EXPORT $Handler_Name [WEAK]
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B .
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ENDP
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MEND
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; Default exception/interrupt handler
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Set_Default_Handler NMI_Handler
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Set_Default_Handler HardFault_Handler
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Set_Default_Handler SVC_Handler
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Set_Default_Handler PendSV_Handler
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Set_Default_Handler SysTick_Handler
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Set_Default_Handler VIDC_IRQn_Handler
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Set_Default_Handler LCDC_IRQn_Handler
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Set_Default_Handler MIPI_RX_IRQn_Handler
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Set_Default_Handler MIPI_TX_IRQn_Handler
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Set_Default_Handler MEMC_IRQn_Handler
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Set_Default_Handler VPRE_IRQn_Handler
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Set_Default_Handler FLSCTRL_IRQn_Handler
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Set_Default_Handler DMA_IRQn_Handler
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Set_Default_Handler TIMER0_IRQn_Handler
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Set_Default_Handler TIMER1_IRQn_Handler
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Set_Default_Handler TIMER2_IRQn_Handler
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Set_Default_Handler TIMER3_IRQn_Handler
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Set_Default_Handler WDG_IRQn_Handler
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Set_Default_Handler UART_IRQn_Handler
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Set_Default_Handler I2C0_IRQn_Handler
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Set_Default_Handler I2C1_IRQn_Handler
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Set_Default_Handler SPIS_IRQn_Handler
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Set_Default_Handler SPIM_IRQn_Handler
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Set_Default_Handler ADC_IRQn_Handler
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Set_Default_Handler PWMDET_IRQn_Handler
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Set_Default_Handler OTP_IRQn_Handler
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Set_Default_Handler SWIRE_IRQn_Handler
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Set_Default_Handler PVD_IRQn_Handler
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Set_Default_Handler AP_NRESET_IRQn_Handler
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Set_Default_Handler EXTI_INT0_IRQn_Handler
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Set_Default_Handler EXTI_INT1_IRQn_Handler
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Set_Default_Handler EXTI_INT2_IRQn_Handler
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Set_Default_Handler EXTI_INT3_IRQn_Handler
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Set_Default_Handler EXTI_INT4_IRQn_Handler
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Set_Default_Handler EXTI_INT5_IRQn_Handler
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Set_Default_Handler EXTI_INT6_IRQn_Handler
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Set_Default_Handler EXTI_INT7_IRQn_Handler
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ALIGN
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; User setup Stack & Heap
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IF :LNOT::DEF:__MICROLIB
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IMPORT __use_two_region_memory
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ENDIF
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EXPORT __stack_limit
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EXPORT __initial_sp
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IF Heap_Size != 0 ; Heap is provided
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EXPORT __heap_base
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EXPORT __heap_limit
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ENDIF
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END
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