L 1 "..\src\board\board.c" N/******************************************************************************* N* Copyright (C) 2019-2022, ISP Systems (R),All Rights Reserved. N* N* File: board.c N* Description 板级文件 N* Version V0.1 N* Date 2020-12-07 N* Author linyw N*******************************************************************************/ N#include "board.h" L 1 "..\src\board\board.h" 1 N/******************************************************************************* N* Copyright (C) 2019-2022, 518/568 Systems (R),All Rights Reserved. N* N* File: board.h N* Description: baord 初始化头文件 N* Version: V0.1 N* Date: 2020-01-08 N* Author: lzy N *******************************************************************************/ N N#ifndef __BOARD_H__ N#define __BOARD_H__ N Nvoid board_Init(void); N N#endif L 11 "..\src\board\board.c" 2 N#include "hal_system.h" L 1 "..\src\sdk\include\hal_system.h" 1 N/******************************************************************************* N* N* N* File: hal_system.h N* Description hal 通用系统接口头文件 N* Version V0.1 N* Date 2021-05-21 N* Author lzy N *******************************************************************************/ N#ifndef __HAL_SYSTEM_H__ N#define __HAL_SYSTEM_H__ N/******************************************************************************* N* 1.Included files N*******************************************************************************/ N#include "tau_common.h" L 1 "..\src\common\tau_common.h" 1 N/******************************************************************************* N* N* N* File: tau_common.h N* Description ͨضͷļ N* Version V0.1 N* Date 2020-09-07 N* Author lzy N *******************************************************************************/ N N#ifndef __TAU_COMMON_H N#define __TAU_COMMON_H N N/******************************************************************************* N* 1.Included files N*******************************************************************************/ N#include "stdint.h" L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h" 1 N/* Copyright (C) ARM Ltd., 1999,2014 */ N/* All rights reserved */ N N/* N * RCS $Revision$ N * Checkin $Date$ N * Revising $Author: agrant $ N */ N N#ifndef __stdint_h N#define __stdint_h N#define __ARMCLIB_VERSION 5060037 N N #ifdef __INT64_TYPE__ S /* armclang predefines '__INT64_TYPE__' and '__INT64_C_SUFFIX__' */ S #define __INT64 __INT64_TYPE__ N #else N /* armcc has builtin '__int64' which can be used in --strict mode */ N #define __INT64 __int64 N #define __INT64_C_SUFFIX__ ll N #endif N #define __PASTE2(x, y) x ## y N #define __PASTE(x, y) __PASTE2(x, y) N #define __INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__)) N #define __UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__)) N #if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__)) X #if 0L || (1L && !0L) N /* armclang and non-strict armcc allow 'long long' in system headers */ N #define __LONGLONG long long N #else S /* strict armcc has '__int64' */ S #define __LONGLONG __int64 N #endif N N #ifndef __STDINT_DECLS N #define __STDINT_DECLS N N #undef __CLIBNS N N #ifdef __cplusplus S namespace std { S #define __CLIBNS std:: S extern "C" { N #else N #define __CLIBNS N #endif /* __cplusplus */ N N N/* N * 'signed' is redundant below, except for 'signed char' and if N * the typedef is used to declare a bitfield. N */ N N /* 7.18.1.1 */ N N /* exact-width signed integer types */ Ntypedef signed char int8_t; Ntypedef signed short int int16_t; Ntypedef signed int int32_t; Ntypedef signed __INT64 int64_t; Xtypedef signed __int64 int64_t; N N /* exact-width unsigned integer types */ Ntypedef unsigned char uint8_t; Ntypedef unsigned short int uint16_t; Ntypedef unsigned int uint32_t; Ntypedef unsigned __INT64 uint64_t; Xtypedef unsigned __int64 uint64_t; N N /* 7.18.1.2 */ N N /* smallest type of at least n bits */ N /* minimum-width signed integer types */ Ntypedef signed char int_least8_t; Ntypedef signed short int int_least16_t; Ntypedef signed int int_least32_t; Ntypedef signed __INT64 int_least64_t; Xtypedef signed __int64 int_least64_t; N N /* minimum-width unsigned integer types */ Ntypedef unsigned char uint_least8_t; Ntypedef unsigned short int uint_least16_t; Ntypedef unsigned int uint_least32_t; Ntypedef unsigned __INT64 uint_least64_t; Xtypedef unsigned __int64 uint_least64_t; N N /* 7.18.1.3 */ N N /* fastest minimum-width signed integer types */ Ntypedef signed int int_fast8_t; Ntypedef signed int int_fast16_t; Ntypedef signed int int_fast32_t; Ntypedef signed __INT64 int_fast64_t; Xtypedef signed __int64 int_fast64_t; N N /* fastest minimum-width unsigned integer types */ Ntypedef unsigned int uint_fast8_t; Ntypedef unsigned int uint_fast16_t; Ntypedef unsigned int uint_fast32_t; Ntypedef unsigned __INT64 uint_fast64_t; Xtypedef unsigned __int64 uint_fast64_t; N N /* 7.18.1.4 integer types capable of holding object pointers */ N#if __sizeof_ptr == 8 X#if 4 == 8 Stypedef signed __INT64 intptr_t; Stypedef unsigned __INT64 uintptr_t; N#else Ntypedef signed int intptr_t; Ntypedef unsigned int uintptr_t; N#endif N N /* 7.18.1.5 greatest-width integer types */ Ntypedef signed __LONGLONG intmax_t; Xtypedef signed long long intmax_t; Ntypedef unsigned __LONGLONG uintmax_t; Xtypedef unsigned long long uintmax_t; N N N#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) X#if !0L || 0L N N /* 7.18.2.1 */ N N /* minimum values of exact-width signed integer types */ N#define INT8_MIN -128 N#define INT16_MIN -32768 N#define INT32_MIN (~0x7fffffff) /* -2147483648 is unsigned */ N#define INT64_MIN __INT64_C(~0x7fffffffffffffff) /* -9223372036854775808 is unsigned */ N N /* maximum values of exact-width signed integer types */ N#define INT8_MAX 127 N#define INT16_MAX 32767 N#define INT32_MAX 2147483647 N#define INT64_MAX __INT64_C(9223372036854775807) N N /* maximum values of exact-width unsigned integer types */ N#define UINT8_MAX 255 N#define UINT16_MAX 65535 N#define UINT32_MAX 4294967295u N#define UINT64_MAX __UINT64_C(18446744073709551615) N N /* 7.18.2.2 */ N N /* minimum values of minimum-width signed integer types */ N#define INT_LEAST8_MIN -128 N#define INT_LEAST16_MIN -32768 N#define INT_LEAST32_MIN (~0x7fffffff) N#define INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff) N N /* maximum values of minimum-width signed integer types */ N#define INT_LEAST8_MAX 127 N#define INT_LEAST16_MAX 32767 N#define INT_LEAST32_MAX 2147483647 N#define INT_LEAST64_MAX __INT64_C(9223372036854775807) N N /* maximum values of minimum-width unsigned integer types */ N#define UINT_LEAST8_MAX 255 N#define UINT_LEAST16_MAX 65535 N#define UINT_LEAST32_MAX 4294967295u N#define UINT_LEAST64_MAX __UINT64_C(18446744073709551615) N N /* 7.18.2.3 */ N N /* minimum values of fastest minimum-width signed integer types */ N#define INT_FAST8_MIN (~0x7fffffff) N#define INT_FAST16_MIN (~0x7fffffff) N#define INT_FAST32_MIN (~0x7fffffff) N#define INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff) N N /* maximum values of fastest minimum-width signed integer types */ N#define INT_FAST8_MAX 2147483647 N#define INT_FAST16_MAX 2147483647 N#define INT_FAST32_MAX 2147483647 N#define INT_FAST64_MAX __INT64_C(9223372036854775807) N N /* maximum values of fastest minimum-width unsigned integer types */ N#define UINT_FAST8_MAX 4294967295u N#define UINT_FAST16_MAX 4294967295u N#define UINT_FAST32_MAX 4294967295u N#define UINT_FAST64_MAX __UINT64_C(18446744073709551615) N N /* 7.18.2.4 */ N N /* minimum value of pointer-holding signed integer type */ N#if __sizeof_ptr == 8 X#if 4 == 8 S#define INTPTR_MIN INT64_MIN N#else N#define INTPTR_MIN INT32_MIN N#endif N N /* maximum value of pointer-holding signed integer type */ N#if __sizeof_ptr == 8 X#if 4 == 8 S#define INTPTR_MAX INT64_MAX N#else N#define INTPTR_MAX INT32_MAX N#endif N N /* maximum value of pointer-holding unsigned integer type */ N#if __sizeof_ptr == 8 X#if 4 == 8 S#define UINTPTR_MAX UINT64_MAX N#else N#define UINTPTR_MAX UINT32_MAX N#endif N N /* 7.18.2.5 */ N N /* minimum value of greatest-width signed integer type */ N#define INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) N N /* maximum value of greatest-width signed integer type */ N#define INTMAX_MAX __ESCAPE__(9223372036854775807ll) N N /* maximum value of greatest-width unsigned integer type */ N#define UINTMAX_MAX __ESCAPE__(18446744073709551615ull) N N /* 7.18.3 */ N N /* limits of ptrdiff_t */ N#if __sizeof_ptr == 8 X#if 4 == 8 S#define PTRDIFF_MIN INT64_MIN S#define PTRDIFF_MAX INT64_MAX N#else N#define PTRDIFF_MIN INT32_MIN N#define PTRDIFF_MAX INT32_MAX N#endif N N /* limits of sig_atomic_t */ N#define SIG_ATOMIC_MIN (~0x7fffffff) N#define SIG_ATOMIC_MAX 2147483647 N N /* limit of size_t */ N#if __sizeof_ptr == 8 X#if 4 == 8 S#define SIZE_MAX UINT64_MAX N#else N#define SIZE_MAX UINT32_MAX N#endif N N /* limits of wchar_t */ N /* NB we have to undef and redef because they're defined in both N * stdint.h and wchar.h */ N#undef WCHAR_MIN N#undef WCHAR_MAX N N#if defined(__WCHAR32) || (defined(__ARM_SIZEOF_WCHAR_T) && __ARM_SIZEOF_WCHAR_T == 4) X#if 0L || (0L && __ARM_SIZEOF_WCHAR_T == 4) S #define WCHAR_MIN 0 S #define WCHAR_MAX 0xffffffffU N#else N #define WCHAR_MIN 0 N #define WCHAR_MAX 65535 N#endif N N /* limits of wint_t */ N#define WINT_MIN (~0x7fffffff) N#define WINT_MAX 2147483647 N N#endif /* __STDC_LIMIT_MACROS */ N N#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) X#if !0L || 0L N N /* 7.18.4.1 macros for minimum-width integer constants */ N#define INT8_C(x) (x) N#define INT16_C(x) (x) N#define INT32_C(x) (x) N#define INT64_C(x) __INT64_C(x) N N#define UINT8_C(x) (x ## u) N#define UINT16_C(x) (x ## u) N#define UINT32_C(x) (x ## u) N#define UINT64_C(x) __UINT64_C(x) N N /* 7.18.4.2 macros for greatest-width integer constants */ N#define INTMAX_C(x) __ESCAPE__(x ## ll) N#define UINTMAX_C(x) __ESCAPE__(x ## ull) N N#endif /* __STDC_CONSTANT_MACROS */ N N #ifdef __cplusplus S } /* extern "C" */ S } /* namespace std */ N #endif /* __cplusplus */ N #endif /* __STDINT_DECLS */ N N #ifdef __cplusplus S #ifndef __STDINT_NO_EXPORTS S using ::std::int8_t; S using ::std::int16_t; S using ::std::int32_t; S using ::std::int64_t; S using ::std::uint8_t; S using ::std::uint16_t; S using ::std::uint32_t; S using ::std::uint64_t; S using ::std::int_least8_t; S using ::std::int_least16_t; S using ::std::int_least32_t; S using ::std::int_least64_t; S using ::std::uint_least8_t; S using ::std::uint_least16_t; S using ::std::uint_least32_t; S using ::std::uint_least64_t; S using ::std::int_fast8_t; S using ::std::int_fast16_t; S using ::std::int_fast32_t; S using ::std::int_fast64_t; S using ::std::uint_fast8_t; S using ::std::uint_fast16_t; S using ::std::uint_fast32_t; S using ::std::uint_fast64_t; S using ::std::intptr_t; S using ::std::uintptr_t; S using ::std::intmax_t; S using ::std::uintmax_t; S #endif N #endif /* __cplusplus */ N N#undef __INT64 N#undef __LONGLONG N N#endif /* __stdint_h */ N N/* end of stdint.h */ L 18 "..\src\common\tau_common.h" 2 N#include "math.h" L 1 "C:\Keil_v5\ARM\ARMCC\Bin\..\include\math.h" 1 N/* N * math.h: ANSI 'C' (X3J11 Oct 88) library header, section 4.5 N * Copyright (C) Codemist Ltd., 1988 N * Copyright 1991-1998,2004-2006,2014 ARM Limited. All rights reserved N */ N N/* N * RCS $Revision$ Codemist 0.03 N * Checkin $Date$ N * Revising $Author: statham $ N */ N N/* N * Parts of this file are based upon fdlibm: N * N * ==================================================== N * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. N * N * Developed at SunSoft, a Sun Microsystems, Inc. business. N * Permission to use, copy, modify, and distribute this N * software is freely granted, provided that this notice N * is preserved. N * ==================================================== N */ N N#ifndef __math_h N#define __math_h N#define __ARMCLIB_VERSION 5060037 N N#if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__)) X#if 0L || (1L && !0L) N /* armclang and non-strict armcc allow 'long long' in system headers */ N #define __LONGLONG long long N#else S /* strict armcc has '__int64' */ S #define __LONGLONG __int64 N#endif N N/* N * Some of these declarations are new in C99. To access them in C++ N * you can use -D__USE_C99_MATH (or -D__USE_C99_ALL). N */ N#ifndef __USE_C99_MATH N #if defined(__USE_C99_ALL) || (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) || (defined(__cplusplus) && 201103L <= __cplusplus) X #if 0L || (1L && 199901L <= 199901L) || (0L && 201103L <= __cplusplus) N #define __USE_C99_MATH 1 N #endif N#endif N N#define _ARMABI __declspec(__nothrow) N#ifdef __TARGET_ARCH_AARCH64 S# define _ARMABI_SOFTFP __declspec(__nothrow) N#else N# define _ARMABI_SOFTFP __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) N# define __HAVE_LONGDOUBLE 1 N#endif N#define _ARMABI_PURE __declspec(__nothrow) __attribute__((const)) N#ifdef __FP_FENV_EXCEPTIONS S# define _ARMABI_FPEXCEPT _ARMABI N#else N# define _ARMABI_FPEXCEPT _ARMABI __attribute__((const)) N#endif N N#ifdef __cplusplus S#define _ARMABI_INLINE inline S#define _ARMABI_INLINE_DEF inline N#elif defined __GNUC__ || defined _USE_STATIC_INLINE X#elif 1L || 0L N#define _ARMABI_INLINE static __inline N#define _ARMABI_INLINE_DEF static __inline N#elif (defined(__STDC_VERSION__) && 199901L <= __STDC_VERSION__) X#elif (1L && 199901L <= 199901L) S#define _ARMABI_INLINE inline S#define _ARMABI_INLINE_DEF static inline S#else S#define _ARMABI_INLINE __inline S#define _ARMABI_INLINE_DEF __inline N#endif N N#ifdef __TARGET_ARCH_AARCH64 S# define _SOFTFP N#else N# define _SOFTFP __attribute__((__pcs__("aapcs"))) N#endif N N /* N * If the compiler supports signalling nans as per N965 then it N * will define __SUPPORT_SNAN__, in which case a user may define N * _WANT_SNAN in order to obtain the nans function, as well as the N * FP_NANS and FP_NANQ classification macros. N */ N#if defined(__SUPPORT_SNAN__) && defined(_WANT_SNAN) X#if 0L && 0L S#pragma import(__use_snan) N#endif N N/* N * Macros for our inline functions down below. N * unsigned& __FLT(float x) - returns the bit pattern of x N * unsigned& __HI(double x) - returns the bit pattern of the high part of x N * (high part has exponent & sign bit in it) N * unsigned& __LO(double x) - returns the bit pattern of the low part of x N * N * We can assign to __FLT, __HI, and __LO and the appropriate bits get set in N * the floating point variable used. N * N * __HI & __LO are affected by the endianness and the target FPU. N */ N#define __FLT(x) (*(unsigned *)&(x)) N#if defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN) X#if 0L || 0L S# define __LO(x) (*(1 + (unsigned *)&(x))) S# define __HI(x) (*(unsigned *)&(x)) N#else /* !defined(__ARM_BIG_ENDIAN) && !defined(__BIG_ENDIAN) */ N# define __HI(x) (*(1 + (unsigned *)&(x))) N# define __LO(x) (*(unsigned *)&(x)) N#endif /* !defined(__ARM_BIG_ENDIAN) && !defined(__BIG_ENDIAN) */ N N# ifndef __MATH_DECLS N# define __MATH_DECLS N N N/* N * A set of functions that we don't actually want to put in the standard N * namespace ever. These are all called by the C99 macros. As they're N * not specified by any standard they can't belong in ::std::. The N * macro #defines are below amongst the standard function declarations. N * We only include these if we actually need them later on N */ N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) X#if !0L || 1L N# ifdef __cplusplus S extern "C" { N# endif /* __cplusplus */ N Nextern _SOFTFP unsigned __ARM_dcmp4(double /*x*/, double /*y*/); Xextern __attribute__((__pcs__("aapcs"))) unsigned __ARM_dcmp4(double , double ); Nextern _SOFTFP unsigned __ARM_fcmp4(float /*x*/, float /*y*/); Xextern __attribute__((__pcs__("aapcs"))) unsigned __ARM_fcmp4(float , float ); N /* N * Compare x and y and return the CPSR in r0. These means we can test for N * result types with bit pattern matching. N * N * These are a copy of the declarations in rt_fp.h keep in sync. N */ N Nextern _ARMABI_SOFTFP int __ARM_fpclassifyf(float /*x*/); Xextern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassifyf(float ); Nextern _ARMABI_SOFTFP int __ARM_fpclassify(double /*x*/); Xextern __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_fpclassify(double ); N /* Classify x into NaN, infinite, normal, subnormal, zero */ N /* Used by fpclassify macro */ N N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isfinitef(float __x) Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinitef(float __x) N{ N return ((__FLT(__x) >> 23) & 0xff) != 0xff; X return (((*(unsigned *)&(__x)) >> 23) & 0xff) != 0xff; N} N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isfinite(double __x) Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isfinite(double __x) N{ N return ((__HI(__x) >> 20) & 0x7ff) != 0x7ff; X return (((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff) != 0x7ff; N} N /* Return 1 if __x is finite, 0 otherwise */ N /* Used by isfinite macro */ N N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isinff(float __x) Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinff(float __x) N{ N return (__FLT(__x) << 1) == 0xff000000; X return ((*(unsigned *)&(__x)) << 1) == 0xff000000; N} N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isinf(double __x) Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isinf(double __x) N{ N return ((__HI(__x) << 1) == 0xffe00000) && (__LO(__x) == 0); X return (((*(1 + (unsigned *)&(__x))) << 1) == 0xffe00000) && ((*(unsigned *)&(__x)) == 0); N} N /* Return 1 if __x is infinite, 0 otherwise */ N /* Used by isinf macro */ N N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_islessgreaterf(float __x, float __y) Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreaterf(float __x, float __y) N{ N unsigned __f = __ARM_fcmp4(__x, __y) >> 28; N return (__f == 8) || (__f == 2); /* Just N set or Just Z set */ N} N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_islessgreater(double __x, double __y) Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_islessgreater(double __x, double __y) N{ N unsigned __f = __ARM_dcmp4(__x, __y) >> 28; N return (__f == 8) || (__f == 2); /* Just N set or Just Z set */ N} N /* N * Compare __x and __y and return 1 if __x < __y or __x > __y, 0 otherwise N * Used by islessgreater macro N */ N N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnanf(float __x) Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnanf(float __x) N{ N return (0x7f800000 - (__FLT(__x) & 0x7fffffff)) >> 31; X return (0x7f800000 - ((*(unsigned *)&(__x)) & 0x7fffffff)) >> 31; N} N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnan(double __x) Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnan(double __x) N{ N unsigned __xf = __HI(__x) | ((__LO(__x) == 0) ? 0 : 1); X unsigned __xf = (*(1 + (unsigned *)&(__x))) | (((*(unsigned *)&(__x)) == 0) ? 0 : 1); N return (0x7ff00000 - (__xf & 0x7fffffff)) >> 31; N} N /* Return 1 if __x is a NaN, 0 otherwise */ N /* Used by isnan macro */ N N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnormalf(float __x) Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormalf(float __x) N{ N unsigned __xe = (__FLT(__x) >> 23) & 0xff; X unsigned __xe = ((*(unsigned *)&(__x)) >> 23) & 0xff; N return (__xe != 0xff) && (__xe != 0); N} N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_isnormal(double __x) Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_isnormal(double __x) N{ N unsigned __xe = (__HI(__x) >> 20) & 0x7ff; X unsigned __xe = ((*(1 + (unsigned *)&(__x))) >> 20) & 0x7ff; N return (__xe != 0x7ff) && (__xe != 0); N} N /* Return 1 if __x is a normalised number, 0 otherwise */ N /* used by isnormal macro */ N N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_signbitf(float __x) Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbitf(float __x) N{ N return __FLT(__x) >> 31; X return (*(unsigned *)&(__x)) >> 31; N} N_ARMABI_INLINE_DEF _ARMABI_SOFTFP int __ARM_signbit(double __x) Xstatic __inline __declspec(__nothrow) __attribute__((__pcs__("aapcs"))) int __ARM_signbit(double __x) N{ N return __HI(__x) >> 31; X return (*(1 + (unsigned *)&(__x))) >> 31; N} N /* Return signbit of __x */ N /* Used by signbit macro */ N N# ifdef __cplusplus S } /* extern "C" */ N# endif /* __cplusplus */ N#endif /* Strict ANSI */ N N# undef __CLIBNS N N# ifdef __cplusplus S namespace std { S# define __CLIBNS ::std:: S extern "C" { N# else N# define __CLIBNS N# endif /* __cplusplus */ N N N#ifndef __has_builtin N #define __has_builtin(x) 0 N#endif N N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) X#if !0L || 1L N /* C99 additions */ N typedef float float_t; N typedef double double_t; N#if __has_builtin(__builtin_inf) X#if 0 S# define HUGE_VALF __builtin_inff() S# define HUGE_VALL __builtin_infl() S# define INFINITY __builtin_inff() S# define NAN __builtin_nanf("") N# else N# define HUGE_VALF ((float)__INFINITY__) N# define HUGE_VALL ((long double)__INFINITY__) N# define INFINITY ((float)__INFINITY__) N# define NAN (__ESCAPE__(0f_7FC00000)) N#endif N N# define MATH_ERRNO 1 N# define MATH_ERREXCEPT 2 Nextern const int math_errhandling; N#endif N#if __has_builtin(__builtin_inf) X#if 0 S# define HUGE_VAL __builtin_inf() N#else N# define HUGE_VAL ((double)__INFINITY__) N#endif N Nextern _ARMABI double acos(double /*x*/); Xextern __declspec(__nothrow) double acos(double ); N /* computes the principal value of the arc cosine of x */ N /* a domain error occurs for arguments not in the range -1 to 1 */ N /* Returns: the arc cosine in the range 0 to Pi. */ Nextern _ARMABI double asin(double /*x*/); Xextern __declspec(__nothrow) double asin(double ); N /* computes the principal value of the arc sine of x */ N /* a domain error occurs for arguments not in the range -1 to 1 */ N /* and -HUGE_VAL is returned. */ N /* Returns: the arc sine in the range -Pi/2 to Pi/2. */ N Nextern _ARMABI_PURE double atan(double /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) double atan(double ); N /* computes the principal value of the arc tangent of x */ N /* Returns: the arc tangent in the range -Pi/2 to Pi/2. */ N Nextern _ARMABI double atan2(double /*y*/, double /*x*/); Xextern __declspec(__nothrow) double atan2(double , double ); N /* computes the principal value of the arc tangent of y/x, using the */ N /* signs of both arguments to determine the quadrant of the return value */ N /* a domain error occurs if both args are zero, and -HUGE_VAL returned. */ N /* Returns: the arc tangent of y/x, in the range -Pi to Pi. */ N Nextern _ARMABI double cos(double /*x*/); Xextern __declspec(__nothrow) double cos(double ); N /* computes the cosine of x (measured in radians). A large magnitude */ N /* argument may yield a result with little or no significance. */ N /* a domain error occurs for infinite input (C 7.12.1 footnote 196). */ N /* Returns: the cosine value. */ Nextern _ARMABI double sin(double /*x*/); Xextern __declspec(__nothrow) double sin(double ); N /* computes the sine of x (measured in radians). A large magnitude */ N /* argument may yield a result with little or no significance. */ N /* a domain error occurs for infinite input (C 7.12.1 footnote 196). */ N /* Returns: the sine value. */ N Nextern void __use_accurate_range_reduction(void); N /* reference this to select the larger, slower, but more accurate */ N /* range reduction in sin, cos and tan */ N Nextern _ARMABI double tan(double /*x*/); Xextern __declspec(__nothrow) double tan(double ); N /* computes the tangent of x (measured in radians). A large magnitude */ N /* argument may yield a result with little or no significance */ N /* Returns: the tangent value. */ N /* if range error; returns HUGE_VAL. */ N Nextern _ARMABI double cosh(double /*x*/); Xextern __declspec(__nothrow) double cosh(double ); N /* computes the hyperbolic cosine of x. A range error occurs if the */ N /* magnitude of x is too large. */ N /* Returns: the hyperbolic cosine value. */ N /* if range error; returns HUGE_VAL. */ Nextern _ARMABI double sinh(double /*x*/); Xextern __declspec(__nothrow) double sinh(double ); N /* computes the hyperbolic sine of x. A range error occurs if the */ N /* magnitude of x is too large. */ N /* Returns: the hyperbolic sine value. */ N /* if range error; returns -HUGE_VAL or HUGE_VAL depending */ N /* on the sign of the argument */ N Nextern _ARMABI_PURE double tanh(double /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) double tanh(double ); N /* computes the hyperbolic tangent of x. */ N /* Returns: the hyperbolic tangent value. */ N Nextern _ARMABI double exp(double /*x*/); Xextern __declspec(__nothrow) double exp(double ); N /* computes the exponential function of x. A range error occurs if the */ N /* magnitude of x is too large. */ N /* Returns: the exponential value. */ N /* if underflow range error; 0 is returned. */ N /* if overflow range error; HUGE_VAL is returned. */ N Nextern _ARMABI double frexp(double /*value*/, int * /*exp*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) double frexp(double , int * ) __attribute__((__nonnull__(2))); N /* breaks a floating-point number into a normalised fraction and an */ N /* integral power of 2. It stores the integer in the int object pointed */ N /* to by exp. */ N /* Returns: the value x, such that x is a double with magnitude in the */ N /* interval 0.5 to 1.0 or zero, and value equals x times 2 raised to the */ N /* power *exp. If value is zero, both parts of the result are zero. */ N Nextern _ARMABI double ldexp(double /*x*/, int /*exp*/); Xextern __declspec(__nothrow) double ldexp(double , int ); N /* multiplies a floating-point number by an integral power of 2. */ N /* A range error may occur. */ N /* Returns: the value of x times 2 raised to the power of exp. */ N /* if range error; HUGE_VAL is returned. */ Nextern _ARMABI double log(double /*x*/); Xextern __declspec(__nothrow) double log(double ); N /* computes the natural logarithm of x. A domain error occurs if the */ N /* argument is negative, and -HUGE_VAL is returned. A range error occurs */ N /* if the argument is zero. */ N /* Returns: the natural logarithm. */ N /* if range error; -HUGE_VAL is returned. */ Nextern _ARMABI double log10(double /*x*/); Xextern __declspec(__nothrow) double log10(double ); N /* computes the base-ten logarithm of x. A domain error occurs if the */ N /* argument is negative. A range error occurs if the argument is zero. */ N /* Returns: the base-ten logarithm. */ Nextern _ARMABI double modf(double /*value*/, double * /*iptr*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) double modf(double , double * ) __attribute__((__nonnull__(2))); N /* breaks the argument value into integral and fraction parts, each of */ N /* which has the same sign as the argument. It stores the integral part */ N /* as a double in the object pointed to by iptr. */ N /* Returns: the signed fractional part of value. */ N Nextern _ARMABI double pow(double /*x*/, double /*y*/); Xextern __declspec(__nothrow) double pow(double , double ); N /* computes x raised to the power of y. A domain error occurs if x is */ N /* zero and y is less than or equal to zero, or if x is negative and y */ N /* is not an integer, and -HUGE_VAL returned. A range error may occur. */ N /* Returns: the value of x raised to the power of y. */ N /* if underflow range error; 0 is returned. */ N /* if overflow range error; HUGE_VAL is returned. */ Nextern _ARMABI double sqrt(double /*x*/); Xextern __declspec(__nothrow) double sqrt(double ); N /* computes the non-negative square root of x. A domain error occurs */ N /* if the argument is negative, and -HUGE_VAL returned. */ N /* Returns: the value of the square root. */ N N#if defined(__TARGET_FPU_VFP_DOUBLE) && !defined(__TARGET_FPU_SOFTVFP) X#if 0L && !1L S _ARMABI_INLINE double _sqrt(double __x) { return __sqrt(__x); } N#else N _ARMABI_INLINE double _sqrt(double __x) { return sqrt(__x); } X static __inline double _sqrt(double __x) { return sqrt(__x); } N#endif N#if defined(__TARGET_FPU_VFP_SINGLE) && !defined(__TARGET_FPU_SOFTVFP) X#if 0L && !1L S _ARMABI_INLINE float _sqrtf(float __x) { return __sqrtf(__x); } N#else N _ARMABI_INLINE float _sqrtf(float __x) { return (float)sqrt(__x); } X static __inline float _sqrtf(float __x) { return (float)sqrt(__x); } N#endif N /* With VFP, _sqrt and _sqrtf should expand inline as the native VFP square root N * instructions. They will not behave like the C sqrt() function, because N * they will report unusual values as IEEE exceptions (in fpmodes which N * support IEEE exceptions) rather than in errno. These function names N * are not specified in any standard. */ N Nextern _ARMABI_PURE double ceil(double /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) double ceil(double ); N /* computes the smallest integer not less than x. */ N /* Returns: the smallest integer not less than x, expressed as a double. */ Nextern _ARMABI_PURE double fabs(double /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) double fabs(double ); N /* computes the absolute value of the floating-point number x. */ N /* Returns: the absolute value of x. */ N Nextern _ARMABI_PURE double floor(double /*d*/); Xextern __declspec(__nothrow) __attribute__((const)) double floor(double ); N /* computes the largest integer not greater than x. */ N /* Returns: the largest integer not greater than x, expressed as a double */ N Nextern _ARMABI double fmod(double /*x*/, double /*y*/); Xextern __declspec(__nothrow) double fmod(double , double ); N /* computes the floating-point remainder of x/y. */ N /* Returns: the value x - i * y, for some integer i such that, if y is */ N /* nonzero, the result has the same sign as x and magnitude */ N /* less than the magnitude of y. If y is zero, a domain error */ N /* occurs and -HUGE_VAL is returned. */ N N /* Additional Mathlib functions not defined by the ANSI standard. N * Not guaranteed, and not necessarily very well tested. N * C99 requires the user to include to use these functions N * declaring them "by hand" is not sufficient N * N * The above statement is not completely true now. Some of the above N * C99 functionality has been added as per the Standard, and (where N * necessary) old Mathlib functionality withdrawn/changed. Before N * including this header #define __ENABLE_MATHLIB_LEGACY if you want to N * re-enable the legacy functionality. N */ N N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) X#if !0L || 1L N Nextern _ARMABI double acosh(double /*x*/); Xextern __declspec(__nothrow) double acosh(double ); N /* N * Inverse cosh. EDOM if argument < 1.0 N */ Nextern _ARMABI double asinh(double /*x*/); Xextern __declspec(__nothrow) double asinh(double ); N /* N * Inverse sinh. N */ Nextern _ARMABI double atanh(double /*x*/); Xextern __declspec(__nothrow) double atanh(double ); N /* N * Inverse tanh. EDOM if |argument| > 1.0 N */ Nextern _ARMABI double cbrt(double /*x*/); Xextern __declspec(__nothrow) double cbrt(double ); N /* N * Cube root. N */ N_ARMABI_INLINE _ARMABI_PURE double copysign(double __x, double __y) Xstatic __inline __declspec(__nothrow) __attribute__((const)) double copysign(double __x, double __y) N /* N * Returns x with sign bit replaced by sign of y. N */ N{ N __HI(__x) = (__HI(__x) & 0x7fffffff) | (__HI(__y) & 0x80000000); X (*(1 + (unsigned *)&(__x))) = ((*(1 + (unsigned *)&(__x))) & 0x7fffffff) | ((*(1 + (unsigned *)&(__y))) & 0x80000000); N return __x; N} N_ARMABI_INLINE _ARMABI_PURE float copysignf(float __x, float __y) Xstatic __inline __declspec(__nothrow) __attribute__((const)) float copysignf(float __x, float __y) N /* N * Returns x with sign bit replaced by sign of y. N */ N{ N __FLT(__x) = (__FLT(__x) & 0x7fffffff) | (__FLT(__y) & 0x80000000); X (*(unsigned *)&(__x)) = ((*(unsigned *)&(__x)) & 0x7fffffff) | ((*(unsigned *)&(__y)) & 0x80000000); N return __x; N} Nextern _ARMABI double erf(double /*x*/); Xextern __declspec(__nothrow) double erf(double ); N /* N * Error function. (2/sqrt(pi)) * integral from 0 to x of exp(-t*t) dt. N */ Nextern _ARMABI double erfc(double /*x*/); Xextern __declspec(__nothrow) double erfc(double ); N /* N * 1-erf(x). (More accurate than just coding 1-erf(x), for large x.) N */ Nextern _ARMABI double expm1(double /*x*/); Xextern __declspec(__nothrow) double expm1(double ); N /* N * exp(x)-1. (More accurate than just coding exp(x)-1, for small x.) N */ N#define fpclassify(x) \ N ((sizeof(x) == sizeof(float)) ? \ N __ARM_fpclassifyf(x) : __ARM_fpclassify(x)) X#define fpclassify(x) ((sizeof(x) == sizeof(float)) ? __ARM_fpclassifyf(x) : __ARM_fpclassify(x)) N /* N * Classify a floating point number into one of the following values: N */ N#define FP_ZERO (0) N#define FP_SUBNORMAL (4) N#define FP_NORMAL (5) N#define FP_INFINITE (3) N#define FP_NAN (7) N N#if defined(_WANT_SNAN) && defined(__SUPPORT_SNAN__) X#if 0L && 0L S/* S * Note that we'll never classify a number as FP_NAN, as all NaNs will S * be either FP_NANQ or FP_NANS S */ S# define FP_NANQ (8) S# define FP_NANS (9) N#endif N N Nextern _ARMABI double hypot(double /*x*/, double /*y*/); Xextern __declspec(__nothrow) double hypot(double , double ); N /* N * sqrt(x*x+y*y), ie the length of the vector (x,y) or the N * hypotenuse of a right triangle whose other two sides are x N * and y. Won't overflow unless the _answer_ is too big, even N * if the intermediate x*x+y*y is too big. N */ Nextern _ARMABI int ilogb(double /*x*/); Xextern __declspec(__nothrow) int ilogb(double ); N /* N * Exponent of x (returns 0 for 1.0, 1 for 2.0, -1 for 0.5, etc.) N */ Nextern _ARMABI int ilogbf(float /*x*/); Xextern __declspec(__nothrow) int ilogbf(float ); N /* N * Like ilogb but takes a float N */ Nextern _ARMABI int ilogbl(long double /*x*/); Xextern __declspec(__nothrow) int ilogbl(long double ); N /* N * Exponent of x (returns 0 for 1.0, 1 for 2.0, -1 for 0.5, etc.) N */ N#define FP_ILOGB0 (-0x7fffffff) /* ilogb(0) == -INT_MAX */ N#define FP_ILOGBNAN ( 0x80000000) /* ilogb(NAN) == INT_MIN */ N N#define isfinite(x) \ N ((sizeof(x) == sizeof(float)) \ N ? __ARM_isfinitef(x) \ N : __ARM_isfinite(x)) X#define isfinite(x) ((sizeof(x) == sizeof(float)) ? __ARM_isfinitef(x) : __ARM_isfinite(x)) N /* N * Returns true if x is a finite number, size independent. N */ N N#define isgreater(x, y) \ N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ N ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000) \ N : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000)) X#define isgreater(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x20000000)) N /* N * Returns true if x > y, throws no exceptions except on Signaling NaNs N * N * We want the C not set but the Z bit clear, V must be clear N */ N N#define isgreaterequal(x, y) \ N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ N ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000) \ N : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000)) X#define isgreaterequal(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x30000000) == 0x20000000) : ((__ARM_dcmp4((x), (y)) & 0x30000000) == 0x20000000)) N /* N * Returns true if x >= y, throws no exceptions except on Signaling NaNs N * N * We just need to see if the C bit is set or not and ensure V clear N */ N N#define isinf(x) \ N ((sizeof(x) == sizeof(float)) \ N ? __ARM_isinff(x) \ N : __ARM_isinf(x)) X#define isinf(x) ((sizeof(x) == sizeof(float)) ? __ARM_isinff(x) : __ARM_isinf(x)) N /* N * Returns true if x is an infinity, size independent. N */ N N#define isless(x, y) \ N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ N ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000) \ N : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000)) X#define isless(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xf0000000) == 0x80000000) : ((__ARM_dcmp4((x), (y)) & 0xf0000000) == 0x80000000)) N /* N * Returns true if x < y, throws no exceptions except on Signaling NaNs N * N * We're less than if N is set, V clear N */ N N#define islessequal(x, y) \ N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ N ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0) \ N : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0)) X#define islessequal(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0xc0000000) != 0) : ((__ARM_dcmp4((x), (y)) & 0xc0000000) != 0)) N /* N * Returns true if x <= y, throws no exceptions except on Signaling NaNs N * N * We're less than or equal if one of N or Z is set, V clear N */ N N#define islessgreater(x, y) \ N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ N ? __ARM_islessgreaterf((x), (y)) \ N : __ARM_islessgreater((x), (y))) X#define islessgreater(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? __ARM_islessgreaterf((x), (y)) : __ARM_islessgreater((x), (y))) N /* N * Returns true if x <> y, throws no exceptions except on Signaling NaNs N * Unfortunately this test is too complicated to do in a macro without N * evaluating x & y twice. Shame really... N */ N N#define isnan(x) \ N ((sizeof(x) == sizeof(float)) \ N ? __ARM_isnanf(x) \ N : __ARM_isnan(x)) X#define isnan(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnanf(x) : __ARM_isnan(x)) N /* N * Returns TRUE if x is a NaN. N */ N N#define isnormal(x) \ N ((sizeof(x) == sizeof(float)) \ N ? __ARM_isnormalf(x) \ N : __ARM_isnormal(x)) X#define isnormal(x) ((sizeof(x) == sizeof(float)) ? __ARM_isnormalf(x) : __ARM_isnormal(x)) N /* N * Returns TRUE if x is a NaN. N */ N N#define isunordered(x, y) \ N (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) \ N ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000) \ N : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000)) X#define isunordered(x, y) (((sizeof(x) == sizeof(float)) && (sizeof(y) == sizeof(float))) ? ((__ARM_fcmp4((x), (y)) & 0x10000000) == 0x10000000) : ((__ARM_dcmp4((x), (y)) & 0x10000000) == 0x10000000)) N /* N * Returns true if x ? y, throws no exceptions except on Signaling NaNs N * Unordered occurs if and only if the V bit is set N */ N Nextern _ARMABI double lgamma (double /*x*/); Xextern __declspec(__nothrow) double lgamma (double ); N /* N * The log of the absolute value of the gamma function of x. The sign N * of the gamma function of x is returned in the global `signgam'. N */ Nextern _ARMABI double log1p(double /*x*/); Xextern __declspec(__nothrow) double log1p(double ); N /* N * log(1+x). (More accurate than just coding log(1+x), for small x.) N */ Nextern _ARMABI double logb(double /*x*/); Xextern __declspec(__nothrow) double logb(double ); N /* N * Like ilogb but returns a double. N */ Nextern _ARMABI float logbf(float /*x*/); Xextern __declspec(__nothrow) float logbf(float ); N /* N * Like logb but takes and returns float N */ Nextern _ARMABI long double logbl(long double /*x*/); Xextern __declspec(__nothrow) long double logbl(long double ); N /* N * Like logb but takes and returns long double N */ Nextern _ARMABI double nextafter(double /*x*/, double /*y*/); Xextern __declspec(__nothrow) double nextafter(double , double ); N /* N * Returns the next representable number after x, in the N * direction toward y. N */ Nextern _ARMABI float nextafterf(float /*x*/, float /*y*/); Xextern __declspec(__nothrow) float nextafterf(float , float ); N /* N * Returns the next representable number after x, in the N * direction toward y. N */ Nextern _ARMABI long double nextafterl(long double /*x*/, long double /*y*/); Xextern __declspec(__nothrow) long double nextafterl(long double , long double ); N /* N * Returns the next representable number after x, in the N * direction toward y. N */ Nextern _ARMABI double nexttoward(double /*x*/, long double /*y*/); Xextern __declspec(__nothrow) double nexttoward(double , long double ); N /* N * Returns the next representable number after x, in the N * direction toward y. N */ Nextern _ARMABI float nexttowardf(float /*x*/, long double /*y*/); Xextern __declspec(__nothrow) float nexttowardf(float , long double ); N /* N * Returns the next representable number after x, in the N * direction toward y. N */ Nextern _ARMABI long double nexttowardl(long double /*x*/, long double /*y*/); Xextern __declspec(__nothrow) long double nexttowardl(long double , long double ); N /* N * Returns the next representable number after x, in the N * direction toward y. N */ Nextern _ARMABI double remainder(double /*x*/, double /*y*/); Xextern __declspec(__nothrow) double remainder(double , double ); N /* N * Returns the remainder of x by y, in the IEEE 754 sense. N */ Nextern _ARMABI_FPEXCEPT double rint(double /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) double rint(double ); N /* N * Rounds x to an integer, in the IEEE 754 sense. N */ Nextern _ARMABI double scalbln(double /*x*/, long int /*n*/); Xextern __declspec(__nothrow) double scalbln(double , long int ); N /* N * Compute x times 2^n quickly. N */ Nextern _ARMABI float scalblnf(float /*x*/, long int /*n*/); Xextern __declspec(__nothrow) float scalblnf(float , long int ); N /* N * Compute x times 2^n quickly. N */ Nextern _ARMABI long double scalblnl(long double /*x*/, long int /*n*/); Xextern __declspec(__nothrow) long double scalblnl(long double , long int ); N /* N * Compute x times 2^n quickly. N */ Nextern _ARMABI double scalbn(double /*x*/, int /*n*/); Xextern __declspec(__nothrow) double scalbn(double , int ); N /* N * Compute x times 2^n quickly. N */ Nextern _ARMABI float scalbnf(float /*x*/, int /*n*/); Xextern __declspec(__nothrow) float scalbnf(float , int ); N /* N * Compute x times 2^n quickly. N */ Nextern _ARMABI long double scalbnl(long double /*x*/, int /*n*/); Xextern __declspec(__nothrow) long double scalbnl(long double , int ); N /* N * Compute x times 2^n quickly. N */ N#define signbit(x) \ N ((sizeof(x) == sizeof(float)) \ N ? __ARM_signbitf(x) \ N : __ARM_signbit(x)) X#define signbit(x) ((sizeof(x) == sizeof(float)) ? __ARM_signbitf(x) : __ARM_signbit(x)) N /* N * Returns the signbit of x, size independent macro N */ N#endif N N/* C99 float versions of functions. math.h has always reserved these N identifiers for this purpose (7.13.4). */ Nextern _ARMABI_PURE float _fabsf(float); /* old ARM name */ Xextern __declspec(__nothrow) __attribute__((const)) float _fabsf(float); N_ARMABI_INLINE _ARMABI_PURE float fabsf(float __f) { return _fabsf(__f); } Xstatic __inline __declspec(__nothrow) __attribute__((const)) float fabsf(float __f) { return _fabsf(__f); } Nextern _ARMABI float sinf(float /*x*/); Xextern __declspec(__nothrow) float sinf(float ); Nextern _ARMABI float cosf(float /*x*/); Xextern __declspec(__nothrow) float cosf(float ); Nextern _ARMABI float tanf(float /*x*/); Xextern __declspec(__nothrow) float tanf(float ); Nextern _ARMABI float acosf(float /*x*/); Xextern __declspec(__nothrow) float acosf(float ); Nextern _ARMABI float asinf(float /*x*/); Xextern __declspec(__nothrow) float asinf(float ); Nextern _ARMABI float atanf(float /*x*/); Xextern __declspec(__nothrow) float atanf(float ); Nextern _ARMABI float atan2f(float /*y*/, float /*x*/); Xextern __declspec(__nothrow) float atan2f(float , float ); Nextern _ARMABI float sinhf(float /*x*/); Xextern __declspec(__nothrow) float sinhf(float ); Nextern _ARMABI float coshf(float /*x*/); Xextern __declspec(__nothrow) float coshf(float ); Nextern _ARMABI float tanhf(float /*x*/); Xextern __declspec(__nothrow) float tanhf(float ); Nextern _ARMABI float expf(float /*x*/); Xextern __declspec(__nothrow) float expf(float ); Nextern _ARMABI float logf(float /*x*/); Xextern __declspec(__nothrow) float logf(float ); Nextern _ARMABI float log10f(float /*x*/); Xextern __declspec(__nothrow) float log10f(float ); Nextern _ARMABI float powf(float /*x*/, float /*y*/); Xextern __declspec(__nothrow) float powf(float , float ); Nextern _ARMABI float sqrtf(float /*x*/); Xextern __declspec(__nothrow) float sqrtf(float ); Nextern _ARMABI float ldexpf(float /*x*/, int /*exp*/); Xextern __declspec(__nothrow) float ldexpf(float , int ); Nextern _ARMABI float frexpf(float /*value*/, int * /*exp*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) float frexpf(float , int * ) __attribute__((__nonnull__(2))); Nextern _ARMABI_PURE float ceilf(float /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) float ceilf(float ); Nextern _ARMABI_PURE float floorf(float /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) float floorf(float ); Nextern _ARMABI float fmodf(float /*x*/, float /*y*/); Xextern __declspec(__nothrow) float fmodf(float , float ); Nextern _ARMABI float modff(float /*value*/, float * /*iptr*/) __attribute__((__nonnull__(2))); Xextern __declspec(__nothrow) float modff(float , float * ) __attribute__((__nonnull__(2))); N N/* C99 long double versions of functions. */ N/* (also need to have 'using' declarations below) */ N#define _ARMDEFLD1(f) \ N _ARMABI long double f##l(long double /*x*/) X#define _ARMDEFLD1(f) _ARMABI long double f##l(long double ) N N#define _ARMDEFLD1P(f, T) \ N _ARMABI long double f##l(long double /*x*/, T /*p*/) X#define _ARMDEFLD1P(f, T) _ARMABI long double f##l(long double , T ) N N#define _ARMDEFLD2(f) \ N _ARMABI long double f##l(long double /*x*/, long double /*y*/) X#define _ARMDEFLD2(f) _ARMABI long double f##l(long double , long double ) N N/* N * Long double versions of C89 functions can be defined N * unconditionally, because C89 reserved these names in "future N * library directions". N */ N_ARMDEFLD1(acos); X__declspec(__nothrow) long double acosl(long double ); N_ARMDEFLD1(asin); X__declspec(__nothrow) long double asinl(long double ); N_ARMDEFLD1(atan); X__declspec(__nothrow) long double atanl(long double ); N_ARMDEFLD2(atan2); X__declspec(__nothrow) long double atan2l(long double , long double ); N_ARMDEFLD1(ceil); X__declspec(__nothrow) long double ceill(long double ); N_ARMDEFLD1(cos); X__declspec(__nothrow) long double cosl(long double ); N_ARMDEFLD1(cosh); X__declspec(__nothrow) long double coshl(long double ); N_ARMDEFLD1(exp); X__declspec(__nothrow) long double expl(long double ); N_ARMDEFLD1(fabs); X__declspec(__nothrow) long double fabsl(long double ); N_ARMDEFLD1(floor); X__declspec(__nothrow) long double floorl(long double ); N_ARMDEFLD2(fmod); X__declspec(__nothrow) long double fmodl(long double , long double ); N_ARMDEFLD1P(frexp, int*) __attribute__((__nonnull__(2))); X__declspec(__nothrow) long double frexpl(long double , int* ) __attribute__((__nonnull__(2))); N_ARMDEFLD1P(ldexp, int); X__declspec(__nothrow) long double ldexpl(long double , int ); N_ARMDEFLD1(log); X__declspec(__nothrow) long double logl(long double ); N_ARMDEFLD1(log10); X__declspec(__nothrow) long double log10l(long double ); N_ARMABI long double modfl(long double /*x*/, long double * /*p*/) __attribute__((__nonnull__(2))); X__declspec(__nothrow) long double modfl(long double , long double * ) __attribute__((__nonnull__(2))); N_ARMDEFLD2(pow); X__declspec(__nothrow) long double powl(long double , long double ); N_ARMDEFLD1(sin); X__declspec(__nothrow) long double sinl(long double ); N_ARMDEFLD1(sinh); X__declspec(__nothrow) long double sinhl(long double ); N_ARMDEFLD1(sqrt); X__declspec(__nothrow) long double sqrtl(long double ); N_ARMDEFLD1(tan); X__declspec(__nothrow) long double tanl(long double ); N_ARMDEFLD1(tanh); X__declspec(__nothrow) long double tanhl(long double ); N N#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) X#if !0L || 1L N N/* N * C99 float and long double versions of extra-C89 functions. N */ Nextern _ARMABI float acoshf(float /*x*/); Xextern __declspec(__nothrow) float acoshf(float ); N_ARMDEFLD1(acosh); X__declspec(__nothrow) long double acoshl(long double ); Nextern _ARMABI float asinhf(float /*x*/); Xextern __declspec(__nothrow) float asinhf(float ); N_ARMDEFLD1(asinh); X__declspec(__nothrow) long double asinhl(long double ); Nextern _ARMABI float atanhf(float /*x*/); Xextern __declspec(__nothrow) float atanhf(float ); N_ARMDEFLD1(atanh); X__declspec(__nothrow) long double atanhl(long double ); N_ARMDEFLD2(copysign); X__declspec(__nothrow) long double copysignl(long double , long double ); Nextern _ARMABI float cbrtf(float /*x*/); Xextern __declspec(__nothrow) float cbrtf(float ); N_ARMDEFLD1(cbrt); X__declspec(__nothrow) long double cbrtl(long double ); Nextern _ARMABI float erff(float /*x*/); Xextern __declspec(__nothrow) float erff(float ); N_ARMDEFLD1(erf); X__declspec(__nothrow) long double erfl(long double ); Nextern _ARMABI float erfcf(float /*x*/); Xextern __declspec(__nothrow) float erfcf(float ); N_ARMDEFLD1(erfc); X__declspec(__nothrow) long double erfcl(long double ); Nextern _ARMABI float expm1f(float /*x*/); Xextern __declspec(__nothrow) float expm1f(float ); N_ARMDEFLD1(expm1); X__declspec(__nothrow) long double expm1l(long double ); Nextern _ARMABI float log1pf(float /*x*/); Xextern __declspec(__nothrow) float log1pf(float ); N_ARMDEFLD1(log1p); X__declspec(__nothrow) long double log1pl(long double ); Nextern _ARMABI float hypotf(float /*x*/, float /*y*/); Xextern __declspec(__nothrow) float hypotf(float , float ); N_ARMDEFLD2(hypot); X__declspec(__nothrow) long double hypotl(long double , long double ); Nextern _ARMABI float lgammaf(float /*x*/); Xextern __declspec(__nothrow) float lgammaf(float ); N_ARMDEFLD1(lgamma); X__declspec(__nothrow) long double lgammal(long double ); Nextern _ARMABI float remainderf(float /*x*/, float /*y*/); Xextern __declspec(__nothrow) float remainderf(float , float ); N_ARMDEFLD2(remainder); X__declspec(__nothrow) long double remainderl(long double , long double ); Nextern _ARMABI float rintf(float /*x*/); Xextern __declspec(__nothrow) float rintf(float ); N_ARMDEFLD1(rint); X__declspec(__nothrow) long double rintl(long double ); N N#endif N N#if (defined(__clang__) && !defined(__STRICT_ANSI)) || defined(__USE_C99_MATH) X#if (0L && !0L) || 1L N/* N * Functions new in C99. N */ Nextern _ARMABI double exp2(double /*x*/); /* * 2.^x. */ Xextern __declspec(__nothrow) double exp2(double ); Nextern _ARMABI float exp2f(float /*x*/); Xextern __declspec(__nothrow) float exp2f(float ); N_ARMDEFLD1(exp2); X__declspec(__nothrow) long double exp2l(long double ); Nextern _ARMABI double fdim(double /*x*/, double /*y*/); Xextern __declspec(__nothrow) double fdim(double , double ); Nextern _ARMABI float fdimf(float /*x*/, float /*y*/); Xextern __declspec(__nothrow) float fdimf(float , float ); N_ARMDEFLD2(fdim); X__declspec(__nothrow) long double fdiml(long double , long double ); N#ifdef __FP_FAST_FMA S#define FP_FAST_FMA N#endif N#ifdef __FP_FAST_FMAF S#define FP_FAST_FMAF N#endif N#ifdef __FP_FAST_FMAL S#define FP_FAST_FMAL N#endif Nextern _ARMABI double fma(double /*x*/, double /*y*/, double /*z*/); Xextern __declspec(__nothrow) double fma(double , double , double ); Nextern _ARMABI float fmaf(float /*x*/, float /*y*/, float /*z*/); Xextern __declspec(__nothrow) float fmaf(float , float , float ); N#ifdef __HAVE_LONGDOUBLE N_ARMABI_INLINE _ARMABI long double fmal(long double __x, long double __y, long double __z) \ N { return (long double)fma((double)__x, (double)__y, (double)__z); } Xstatic __inline __declspec(__nothrow) long double fmal(long double __x, long double __y, long double __z) { return (long double)fma((double)__x, (double)__y, (double)__z); } N#endif Nextern _ARMABI_FPEXCEPT double fmax(double /*x*/, double /*y*/); Xextern __declspec(__nothrow) __attribute__((const)) double fmax(double , double ); Nextern _ARMABI_FPEXCEPT float fmaxf(float /*x*/, float /*y*/); Xextern __declspec(__nothrow) __attribute__((const)) float fmaxf(float , float ); N_ARMDEFLD2(fmax); X__declspec(__nothrow) long double fmaxl(long double , long double ); Nextern _ARMABI_FPEXCEPT double fmin(double /*x*/, double /*y*/); Xextern __declspec(__nothrow) __attribute__((const)) double fmin(double , double ); Nextern _ARMABI_FPEXCEPT float fminf(float /*x*/, float /*y*/); Xextern __declspec(__nothrow) __attribute__((const)) float fminf(float , float ); N_ARMDEFLD2(fmin); X__declspec(__nothrow) long double fminl(long double , long double ); Nextern _ARMABI double log2(double /*x*/); /* * log base 2 of x. */ Xextern __declspec(__nothrow) double log2(double ); Nextern _ARMABI float log2f(float /*x*/); Xextern __declspec(__nothrow) float log2f(float ); N_ARMDEFLD1(log2); X__declspec(__nothrow) long double log2l(long double ); Nextern _ARMABI long lrint(double /*x*/); Xextern __declspec(__nothrow) long lrint(double ); Nextern _ARMABI long lrintf(float /*x*/); Xextern __declspec(__nothrow) long lrintf(float ); N#ifdef __HAVE_LONGDOUBLE N_ARMABI_INLINE _ARMABI long lrintl(long double __x) \ N { return lrint((double)__x); } Xstatic __inline __declspec(__nothrow) long lrintl(long double __x) { return lrint((double)__x); } N#endif Nextern _ARMABI __LONGLONG llrint(double /*x*/); Xextern __declspec(__nothrow) long long llrint(double ); Nextern _ARMABI __LONGLONG llrintf(float /*x*/); Xextern __declspec(__nothrow) long long llrintf(float ); N#ifdef __HAVE_LONGDOUBLE N_ARMABI_INLINE _ARMABI __LONGLONG llrintl(long double __x) \ N { return llrint((double)__x); } Xstatic __inline __declspec(__nothrow) long long llrintl(long double __x) { return llrint((double)__x); } N#endif Nextern _ARMABI long lround(double /*x*/); Xextern __declspec(__nothrow) long lround(double ); Nextern _ARMABI long lroundf(float /*x*/); Xextern __declspec(__nothrow) long lroundf(float ); N#ifdef __HAVE_LONGDOUBLE N_ARMABI_INLINE _ARMABI long lroundl(long double __x) \ N { return lround((double)__x); } Xstatic __inline __declspec(__nothrow) long lroundl(long double __x) { return lround((double)__x); } N#endif Nextern _ARMABI __LONGLONG llround(double /*x*/); Xextern __declspec(__nothrow) long long llround(double ); Nextern _ARMABI __LONGLONG llroundf(float /*x*/); Xextern __declspec(__nothrow) long long llroundf(float ); N#ifdef __HAVE_LONGDOUBLE N_ARMABI_INLINE _ARMABI __LONGLONG llroundl(long double __x) \ N { return llround((double)__x); } Xstatic __inline __declspec(__nothrow) long long llroundl(long double __x) { return llround((double)__x); } N#endif Nextern _ARMABI_PURE double nan(const char */*tagp*/); Xextern __declspec(__nothrow) __attribute__((const)) double nan(const char * ); Nextern _ARMABI_PURE float nanf(const char */*tagp*/); Xextern __declspec(__nothrow) __attribute__((const)) float nanf(const char * ); N#ifdef __HAVE_LONGDOUBLE N_ARMABI_INLINE _ARMABI_PURE long double nanl(const char *__t) \ N { return (long double)nan(__t); } Xstatic __inline __declspec(__nothrow) __attribute__((const)) long double nanl(const char *__t) { return (long double)nan(__t); } N#endif N#if defined(_WANT_SNAN) && defined(__SUPPORT_SNAN__) X#if 0L && 0L Sextern _ARMABI_PURE double nans(const char */*tagp*/); Sextern _ARMABI_PURE float nansf(const char */*tagp*/); S#ifdef __HAVE_LONGDOUBLE S_ARMABI_INLINE _ARMABI_FPEXCEPT long double nansl(const char *__t) \ S { return (long double)nans(__t); } X_ARMABI_INLINE _ARMABI_FPEXCEPT long double nansl(const char *__t) { return (long double)nans(__t); } S#endif N#endif Nextern _ARMABI_FPEXCEPT double nearbyint(double /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) double nearbyint(double ); Nextern _ARMABI_FPEXCEPT float nearbyintf(float /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) float nearbyintf(float ); N_ARMDEFLD1(nearbyint); X__declspec(__nothrow) long double nearbyintl(long double ); Nextern double remquo(double /*x*/, double /*y*/, int */*quo*/); Nextern float remquof(float /*x*/, float /*y*/, int */*quo*/); N#ifdef __HAVE_LONGDOUBLE N_ARMABI_INLINE long double remquol(long double __x, long double __y, int *__q) \ N { return (long double)remquo((double)__x, (double)__y, __q); } Xstatic __inline long double remquol(long double __x, long double __y, int *__q) { return (long double)remquo((double)__x, (double)__y, __q); } N#endif Nextern _ARMABI_FPEXCEPT double round(double /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) double round(double ); Nextern _ARMABI_FPEXCEPT float roundf(float /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) float roundf(float ); N_ARMDEFLD1(round); X__declspec(__nothrow) long double roundl(long double ); Nextern _ARMABI double tgamma(double /*x*/); /* * The gamma function of x. */ Xextern __declspec(__nothrow) double tgamma(double ); Nextern _ARMABI float tgammaf(float /*x*/); Xextern __declspec(__nothrow) float tgammaf(float ); N_ARMDEFLD1(tgamma); X__declspec(__nothrow) long double tgammal(long double ); Nextern _ARMABI_FPEXCEPT double trunc(double /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) double trunc(double ); Nextern _ARMABI_FPEXCEPT float truncf(float /*x*/); Xextern __declspec(__nothrow) __attribute__((const)) float truncf(float ); N_ARMDEFLD1(trunc); X__declspec(__nothrow) long double truncl(long double ); N#endif N N#undef _ARMDEFLD1 N#undef _ARMDEFLD1P N#undef _ARMDEFLD2 N N#if defined(__cplusplus) && ((!defined(__STRICT_ANSI__) || defined(__USE_C99_MATH)) || defined(__ARMCOMPILER_LIBCXX)) X#if 0L && ((!0L || 1L) || 0L) S extern "C++" { S inline int (fpclassify)(double __x) { return fpclassify(__x); } S inline bool (isfinite)(double __x) { return isfinite(__x); } S inline bool (isgreater)(double __x, double __y) { return isgreater(__x, __y); } S inline bool (isgreaterequal)(double __x, double __y) { return isgreaterequal(__x, __y); } S inline bool (isinf)(double __x) { return isinf(__x); } S inline bool (isless)(double __x, double __y) { return isless(__x, __y); } S inline bool (islessequal)(double __x, double __y) { return islessequal(__x, __y); } S inline bool (islessgreater)(double __x, double __y) { return islessgreater(__x, __y); } S inline bool (isnan)(double __x) { return isnan(__x); } S inline bool (isnormal)(double __x) { return isnormal(__x); } S inline bool (isunordered)(double __x, double __y) { return isunordered(__x, __y); } S S } N#endif N N#if defined(__cplusplus) && !defined(__ARMCOMPILER_LIBCXX) X#if 0L && !0L S extern "C++" { S inline float abs(float __x) { return fabsf(__x); } S inline float acos(float __x) { return acosf(__x); } S inline float asin(float __x) { return asinf(__x); } S inline float atan(float __x) { return atanf(__x); } S inline float atan2(float __y, float __x) { return atan2f(__y,__x); } S inline float ceil(float __x) { return ceilf(__x); } S inline float cos(float __x) { return cosf(__x); } S inline float cosh(float __x) { return coshf(__x); } S inline float exp(float __x) { return expf(__x); } S inline float fabs(float __x) { return fabsf(__x); } S inline float floor(float __x) { return floorf(__x); } S inline float fmod(float __x, float __y) { return fmodf(__x, __y); } S float frexp(float __x, int* __exp) __attribute__((__nonnull__(2))); S inline float frexp(float __x, int* __exp) { return frexpf(__x, __exp); } S inline float ldexp(float __x, int __exp) { return ldexpf(__x, __exp);} S inline float log(float __x) { return logf(__x); } S inline float log10(float __x) { return log10f(__x); } S float modf(float __x, float* __iptr) __attribute__((__nonnull__(2))); S inline float modf(float __x, float* __iptr) { return modff(__x, __iptr); } S inline float pow(float __x, float __y) { return powf(__x,__y); } S inline float pow(float __x, int __y) { return powf(__x, (float)__y); } S inline float sin(float __x) { return sinf(__x); } S inline float sinh(float __x) { return sinhf(__x); } S inline float sqrt(float __x) { return sqrtf(__x); } S inline float _sqrt(float __x) { return _sqrtf(__x); } S inline float tan(float __x) { return tanf(__x); } S inline float tanh(float __x) { return tanhf(__x); } S S inline double abs(double __x) { return fabs(__x); } S inline double pow(double __x, int __y) S { return pow(__x, (double) __y); } S S#ifdef __HAVE_LONGDOUBLE S inline long double abs(long double __x) S { return (long double)fabsl(__x); } S inline long double acos(long double __x) S { return (long double)acosl(__x); } S inline long double asin(long double __x) S { return (long double)asinl(__x); } S inline long double atan(long double __x) S { return (long double)atanl(__x); } S inline long double atan2(long double __y, long double __x) S { return (long double)atan2l(__y, __x); } S inline long double ceil(long double __x) S { return (long double)ceill( __x); } S inline long double cos(long double __x) S { return (long double)cosl(__x); } S inline long double cosh(long double __x) S { return (long double)coshl(__x); } S inline long double exp(long double __x) S { return (long double)expl(__x); } S inline long double fabs(long double __x) S { return (long double)fabsl(__x); } S inline long double floor(long double __x) S { return (long double)floorl(__x); } S inline long double fmod(long double __x, long double __y) S { return (long double)fmodl(__x, __y); } S long double frexp(long double __x, int* __p) __attribute__((__nonnull__(2))); S inline long double frexp(long double __x, int* __p) S { return (long double)frexpl(__x, __p); } S inline long double ldexp(long double __x, int __exp) S { return (long double)ldexpl(__x, __exp); } S inline long double log(long double __x) S { return (long double)logl(__x); } S inline long double log10(long double __x) S { return (long double)log10l(__x); } S long double modf(long double __x, long double* __p) __attribute__((__nonnull__(2))); S inline long double modf(long double __x, long double* __p) S { return (long double)modfl(__x, __p); } S inline long double pow(long double __x, long double __y) S { return (long double)powl(__x, __y); } S inline long double pow(long double __x, int __y) S { return (long double)powl(__x, __y); } S inline long double sin(long double __x) S { return (long double)sinl(__x); } S inline long double sinh(long double __x) S { return (long double)sinhl(__x); } S inline long double sqrt(long double __x) S { return (long double)sqrtl(__x); } S inline long double _sqrt(long double __x) S { return (long double)_sqrt((double) __x); } S inline long double tan(long double __x) S { return (long double)tanl(__x); } S inline long double tanh(long double __x) S { return (long double)tanhl(__x); } S#endif S S#if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) S inline float acosh(float __x) { return acoshf(__x); } S inline float asinh(float __x) { return asinhf(__x); } S inline float atanh(float __x) { return atanhf(__x); } S inline float cbrt(float __x) { return cbrtf(__x); } S inline float erf(float __x) { return erff(__x); } S inline float erfc(float __x) { return erfcf(__x); } S inline float expm1(float __x) { return expm1f(__x); } S inline float log1p(float __x) { return log1pf(__x); } S inline float hypot(float __x, float __y) { return hypotf(__x, __y); } S inline float lgamma(float __x) { return lgammaf(__x); } S inline float remainder(float __x, float __y) { return remainderf(__x, __y); } S inline float rint(float __x) { return rintf(__x); } S#endif S S#ifdef __USE_C99_MATH S inline float exp2(float __x) { return exp2f(__x); } S inline float fdim(float __x, float __y) { return fdimf(__x, __y); } S inline float fma(float __x, float __y, float __z) { return fmaf(__x, __y, __z); } S inline float fmax(float __x, float __y) { return fmaxf(__x, __y); } S inline float fmin(float __x, float __y) { return fminf(__x, __y); } S inline float log2(float __x) { return log2f(__x); } S inline _ARMABI long lrint(float __x) { return lrintf(__x); } S inline _ARMABI __LONGLONG llrint(float __x) { return llrintf(__x); } S inline _ARMABI long lround(float __x) { return lroundf(__x); } S inline _ARMABI __LONGLONG llround(float __x) { return llroundf(__x); } S inline _ARMABI_FPEXCEPT float nearbyint(float __x) { return nearbyintf(__x); } S inline float remquo(float __x, float __y, int *__q) { return remquof(__x, __y, __q); } S inline _ARMABI_FPEXCEPT float round(float __x) { return roundf(__x); } S inline float tgamma(float __x) { return tgammaf(__x); } S inline _ARMABI_FPEXCEPT float trunc(float __x) { return truncf(__x); } S S inline int (fpclassify)(float __x) { return fpclassify(__x); } S inline bool (isfinite)(float __x) { return isfinite(__x); } S inline bool (isgreater)(float __x, float __y) { return isgreater(__x, __y); } S inline bool (isgreaterequal)(float __x, float __y) { return isgreaterequal(__x, __y); } S inline bool (isinf)(float __x) { return isinf(__x); } S inline bool (isless)(float __x, float __y) { return isless(__x, __y); } S inline bool (islessequal)(float __x, float __y) { return islessequal(__x, __y); } S inline bool (islessgreater)(float __x, float __y) { return islessgreater(__x, __y); } S inline bool (isnan)(float __x) { return isnan(__x); } S inline bool (isnormal)(float __x) { return isnormal(__x); } S inline bool (isunordered)(float __x, float __y) { return isunordered(__x, __y); } S S#ifdef __HAVE_LONGDOUBLE S inline long double acosh(long double __x) { return acoshl(__x); } S inline long double asinh(long double __x) { return asinhl(__x); } S inline long double atanh(long double __x) { return atanhl(__x); } S inline long double cbrt(long double __x) { return cbrtl(__x); } S inline long double erf(long double __x) { return erfl(__x); } S inline long double erfc(long double __x) { return erfcl(__x); } S inline long double expm1(long double __x) { return expm1l(__x); } S inline long double log1p(long double __x) { return log1pl(__x); } S inline long double hypot(long double __x, long double __y) { return hypotl(__x, __y); } S inline long double lgamma(long double __x) { return lgammal(__x); } S inline long double remainder(long double __x, long double __y) { return remainderl(__x, __y); } S inline long double rint(long double __x) { return rintl(__x); } S inline long double exp2(long double __x) { return exp2l(__x); } S inline long double fdim(long double __x, long double __y) { return fdiml(__x, __y); } S inline long double fma(long double __x, long double __y, long double __z) { return fmal(__x, __y, __z); } S inline long double fmax(long double __x, long double __y) { return fmaxl(__x, __y); } S inline long double fmin(long double __x, long double __y) { return fminl(__x, __y); } S inline long double log2(long double __x) { return log2l(__x); } S inline _ARMABI long lrint(long double __x) { return lrintl(__x); } S inline _ARMABI __LONGLONG llrint(long double __x) { return llrintl(__x); } S inline _ARMABI long lround(long double __x) { return lroundl(__x); } S inline _ARMABI __LONGLONG llround(long double __x) { return llroundl(__x); } S inline _ARMABI_FPEXCEPT long double nearbyint(long double __x) { return nearbyintl(__x); } S inline long double remquo(long double __x, long double __y, int *__q) { return remquol(__x, __y, __q); } S inline _ARMABI_FPEXCEPT long double round(long double __x) { return roundl(__x); } S inline long double tgamma(long double __x) { return tgammal(__x); } S inline _ARMABI_FPEXCEPT long double trunc(long double __x) { return truncl(__x); } S inline int (fpclassify)(long double __x) { return fpclassify(__x); } S inline bool (isfinite)(long double __x) { return isfinite(__x); } S inline bool (isgreater)(long double __x, long double __y) { return isgreater(__x, __y); } S inline bool (isgreaterequal)(long double __x, long double __y) { return isgreaterequal(__x, __y); } S inline bool (isinf)(long double __x) { return isinf(__x); } S inline bool (isless)(long double __x, long double __y) { return isless(__x, __y); } S inline bool (islessequal)(long double __x, long double __y) { return islessequal(__x, __y); } S inline bool (islessgreater)(long double __x, long double __y) { return islessgreater(__x, __y); } S inline bool (isnan)(long double __x) { return isnan(__x); } S inline bool (isnormal)(long double __x) { return isnormal(__x); } S inline bool (isunordered)(long double __x, long double __y) { return isunordered(__x, __y); } S#endif S S#undef fpclassify S#undef isfinite S#undef isgreater S#undef isgreaterequal S#undef isinf S#undef isless S#undef islessequal S#undef islessgreater S#undef isnan S#undef isnormal S#undef isunordered S S#endif S S } N#endif N N #ifdef __cplusplus S } /* extern "C" */ S } /* namespace std */ N #endif N #endif /* __MATH_DECLS */ N N #if _AEABI_PORTABILITY_LEVEL != 0 && !defined _AEABI_PORTABLE X #if _AEABI_PORTABILITY_LEVEL != 0 && !0L S #define _AEABI_PORTABLE N #endif N N #if defined(__cplusplus) && !defined(__MATH_NO_EXPORTS) X #if 0L && !0L S using ::std::__use_accurate_range_reduction; S #ifndef __ARMCOMPILER_LIBCXX S using ::std::abs; S #endif S using ::std::acos; S using ::std::asin; S using ::std::atan2; S using ::std::atan; S using ::std::ceil; S using ::std::cos; S using ::std::cosh; S using ::std::exp; S using ::std::fabs; S using ::std::floor; S using ::std::fmod; S using ::std::frexp; S using ::std::ldexp; S using ::std::log10; S using ::std::log; S using ::std::modf; S using ::std::pow; S using ::std::sin; S using ::std::sinh; S using ::std::sqrt; S using ::std::_sqrt; S using ::std::_sqrtf; S using ::std::tan; S using ::std::tanh; S using ::std::_fabsf; S /* C99 float and long double versions in already-C89-reserved namespace */ S using ::std::acosf; S using ::std::acosl; S using ::std::asinf; S using ::std::asinl; S using ::std::atan2f; S using ::std::atan2l; S using ::std::atanf; S using ::std::atanl; S using ::std::ceilf; S using ::std::ceill; S using ::std::cosf; S using ::std::coshf; S using ::std::coshl; S using ::std::cosl; S using ::std::expf; S using ::std::expl; S using ::std::fabsf; S using ::std::fabsl; S using ::std::floorf; S using ::std::floorl; S using ::std::fmodf; S using ::std::fmodl; S using ::std::frexpf; S using ::std::frexpl; S using ::std::ldexpf; S using ::std::ldexpl; S using ::std::log10f; S using ::std::log10l; S using ::std::logf; S using ::std::logl; S using ::std::modff; S using ::std::modfl; S using ::std::powf; S using ::std::powl; S using ::std::sinf; S using ::std::sinhf; S using ::std::sinhl; S using ::std::sinl; S using ::std::sqrtf; S using ::std::sqrtl; S using ::std::tanf; S using ::std::tanhf; S using ::std::tanhl; S using ::std::tanl; S #if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) S /* C99 additions which for historical reasons appear in non-strict mode */ S using ::std::acosh; S using ::std::asinh; S using ::std::atanh; S using ::std::cbrt; S using ::std::copysign; S using ::std::copysignf; S using ::std::erf; S using ::std::erfc; S using ::std::expm1; S using ::std::hypot; S using ::std::ilogb; S using ::std::ilogbf; S using ::std::ilogbl; S using ::std::lgamma; S using ::std::log1p; S using ::std::logb; S using ::std::logbf; S using ::std::logbl; S using ::std::nextafter; S using ::std::nextafterf; S using ::std::nextafterl; S using ::std::nexttoward; S using ::std::nexttowardf; S using ::std::nexttowardl; S using ::std::remainder; S using ::std::rint; S using ::std::scalbln; S using ::std::scalblnf; S using ::std::scalblnl; S using ::std::scalbn; S using ::std::scalbnf; S using ::std::scalbnl; S using ::std::math_errhandling; S using ::std::acoshf; S using ::std::acoshl; S using ::std::asinhf; S using ::std::asinhl; S using ::std::atanhf; S using ::std::atanhl; S using ::std::copysignl; S using ::std::cbrtf; S using ::std::cbrtl; S using ::std::erff; S using ::std::erfl; S using ::std::erfcf; S using ::std::erfcl; S using ::std::expm1f; S using ::std::expm1l; S using ::std::log1pf; S using ::std::log1pl; S using ::std::hypotf; S using ::std::hypotl; S using ::std::lgammaf; S using ::std::lgammal; S using ::std::remainderf; S using ::std::remainderl; S using ::std::rintf; S using ::std::rintl; S /* New in C99. */ S using ::std::float_t; S using ::std::double_t; S #endif S #if (defined(__clang__) && !defined(__STRICT_ANSI)) || defined(__USE_C99_MATH) S /* Functions new in C99. */ S using ::std::exp2; S using ::std::exp2f; S using ::std::exp2l; S using ::std::fdim; S using ::std::fdimf; S using ::std::fdiml; S using ::std::fma; S using ::std::fmaf; S#ifdef __HAVE_LONGDOUBLE S using ::std::fmal; S#endif S using ::std::fmax; S using ::std::fmaxf; S using ::std::fmaxl; S using ::std::fmin; S using ::std::fminf; S using ::std::fminl; S using ::std::log2; S using ::std::log2f; S using ::std::log2l; S using ::std::lrint; S using ::std::lrintf; S#ifdef __HAVE_LONGDOUBLE S using ::std::lrintl; S#endif S using ::std::llrint; S using ::std::llrintf; S#ifdef __HAVE_LONGDOUBLE S using ::std::llrintl; S#endif S using ::std::lround; S using ::std::lroundf; S#ifdef __HAVE_LONGDOUBLE S using ::std::lroundl; S#endif S using ::std::llround; S using ::std::llroundf; S#ifdef __HAVE_LONGDOUBLE S using ::std::llroundl; S#endif S using ::std::nan; S using ::std::nanf; S#ifdef __HAVE_LONGDOUBLE S using ::std::nanl; S#endif S using ::std::nearbyint; S using ::std::nearbyintf; S using ::std::nearbyintl; S using ::std::remquo; S using ::std::remquof; S#ifdef __HAVE_LONGDOUBLE S using ::std::remquol; S#endif S using ::std::round; S using ::std::roundf; S using ::std::roundl; S using ::std::tgamma; S using ::std::tgammaf; S using ::std::tgammal; S using ::std::trunc; S using ::std::truncf; S using ::std::truncl; S #endif S S #if !defined(__STRICT_ANSI__) || defined(__USE_C99_MATH) S using ::std::fpclassify; S using ::std::isfinite; S using ::std::isgreater; S using ::std::isgreaterequal; S using ::std::isinf; S using ::std::isless; S using ::std::islessequal; S using ::std::islessgreater; S using ::std::isnan; S using ::std::isnormal; S using ::std::isunordered; S #endif N #endif N N#undef __LONGLONG N N#endif /* __math_h */ N N/* end of math.h */ L 19 "..\src\common\tau_common.h" 2 N N/******************************************************************************* N* 2.Global constant and macro definitions using #define N*******************************************************************************/ N/** N * \name ͨó N * @{ N */ N//#define ENABLE 1 N//#define DISABLE 0 N N#define ON 1 N#define OFF 0 N N#define NONE 0 N#define EOS '\0' N N/* N#ifndef TRUE N#define TRUE 1 N#endif N N#ifndef FALSE N#define FALSE 0 N#endif N*/ N N#ifndef __cplusplus N #define true 1 N #define false 0 N #define bool _Bool N#endif /* ifndef __cplusplus */ N N#ifndef NULL N #define NULL ((void *)0) N#endif N N#define TAU_LITTLE_ENDIAN 1234 /**< \brief Сģʽ */ N#define TAU_BIG_ENDIAN 3412 /**< \brief ģʽ */ N N/** @} */ N N/******************************************************************************/ N N/** N * \name ú궨 N * @{ N */ N N#ifdef __cplusplus S #define __I volatile /*!< Defines 'read only' permissions */ N#else N #define __I volatile const /*!< Defines 'read only' permissions */ N#endif N#define __O volatile /*!< Defines 'write only' permissions */ N#define __IO volatile /*!< Defines 'read / write' permissions */ N N#define TAU_INLINE inline N#define TAU_STATIC_INLINE static inline N#define TAU_STATIC static N#define TAU_CONST const N#define TAU_EXTERN extern N N#define MIN(x, y) (((x) < (y)) ? (x) : (y)) N#define MAX(x, y) (((x) > (y)) ? (x) : (y)) N N/** N * \brief ṹԱƫ N * \attention ͬƽ̨ϣڳԱСڴԭ N * ͬһṹԱƫƿDzһ N * N * \par ʾ N * \code N * struct my_struct { N * int m1; N * char m2; N * }; N * int offset_m2; N * N * offset_m2 = TAU_OFFSET(struct my_struct, m2); N * \endcode N */ N#define TAU_OFFSET(structure, member) ((uint32_t)(&(((structure *)0)->member))) N N/** @} */ N N/** N * \brief ͨṹԱָȡýṹԱĽṹ N * N * \param ptr ָṹԱָ N * \param type ṹ N * \param member ṹиóԱ N * N * \par ʾ N * \code N * struct my_struct = { N * int m1; N * char m2; N * }; N * struct my_struct my_st; N * char *p_m2 = &my_st.m2; N * struct my_struct *p_st = TAU_CONTAINER_OF(p_m2, struct my_struct, m2); N * \endcode N */ N#define TAU_CONTAINER_OF(ptr, type, member) \ N ((type *)((char *)(ptr)-TAU_OFFSET(type, member))) X#define TAU_CONTAINER_OF(ptr, type, member) ((type *)((char *)(ptr)-TAU_OFFSET(type, member))) N N/** N * \brief ṹԱĴС N * N * \code N * struct a = { N * uint32_t m1; N * uint32_t m2; N * }; N * int size_m2; N * N * size_m2 = TAU_MEMBER_SIZE(a, m2); //size_m2 = 4 N * \endcode N */ N#define TAU_MEMBER_SIZE(structure, member) (sizeof(((structure *)0)->member)) N N/** N * \brief Ԫظ N * N * \code N * int a[] = {0, 1, 2, 3}; N * int element_a = TAU_NELEMENTS(a); // element_a = 4 N * \endcode N */ N#define TAU_NELEMENTS(array) (sizeof(array) / sizeof((array)[0])) N N/** N * \brief N * N * \param x N * \param align N * N * \code N * int size = TAU_ROUND_UP(15, 4); // size = 16 N * \endcode N */ N#define TAU_ROUND_UP(x, align) (((int)(x)/(align))*(align) + (((int)(x)%(align)) ? (align) : 0)) N N/** N * \brief N * N * \param x N * \param align N * N * \code N * int size = TAU_ROUND_DOWN(15, 4); // size = 12 N * \endcode N */ N#define TAU_ROUND_DOWN(x, align) (((int)(x)/(align))*(align)) N N/** \brief */ N#define TAU_DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d)) N N/** N * \brief Ƿ N * N * \param x N * \param align أΪ2ij˷ N * N * \code N * if (TAU_ALIGNED(x, 4) { N * ; // x N * } else { N * ; // x N * } N * \endcode N */ N#define TAU_ALIGNED(x, align) (((int)(x) & (align - 1)) == 0) N N/** \brief 1ֽBCDתΪ16 */ N#define TAU_BCD_TO_HEX(val) (((val)&0x0f) + ((val) >> 4) * 10) N N/** \brief 1ֽ16תΪBCD */ N#define TAU_HEX_TO_BCD(val) ((((val) / 10) << 4) + (val) % 10) N N/** N * \brief ȡ N */ N#define TAU_CEIL(val) ceil(val) N N N/*! @brief Construct the version number for drivers. */ N#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) N N N/******************************************************************************* N* 3.Global structures, unions and enumerations using typedef N*******************************************************************************/ N/* \brief ͨûصָ붨 */ Ntypedef void (*fcb_type)(void *data); N N#endif /* __TAU_COMMON_H */ L 16 "..\src\sdk\include\hal_system.h" 2 N N/******************************************************************************* N* 2.Global constant and macro definitions using #define N*******************************************************************************/ N N/******************************************************************************* N* 3.Global structures, unions and enumerations using typedef N*******************************************************************************/ N N/******************************************************************************* N* 4.Global variable extern declarations N*******************************************************************************/ N N/******************************************************************************* N* 5.Global function prototypes N*******************************************************************************/ N N/** N* @brief system 初始化 N* @param none N* @retval none N*/ Nvoid hal_system_init(uint32_t sysclk); N N/** N* @brief system 初始化 console N* @param baud_rate 波特率 N* @retval none N*/ Nvoid hal_system_init_console(uint32_t baud_rate); N N/** N* @brief mcu进入idle模式,等待中断唤醒 N* @param disable_systick: 进入idle时是否关闭systick(退出idle 恢复systick) N* @retval none N*/ Nvoid hal_system_idle_mode(bool disable_systick); Xvoid hal_system_idle_mode(_Bool disable_systick); N N/** N* @brief 注册systick回调函数 N* @param cb_func：回调函数地址 N* @retval 无 N*/ Nvoid hal_system_register_systick_cb(fcb_type cb_func); N N/** N* @brief 启动sys tickt N* @param ms: sys tickt 间隔, 范围1-10ms N* @retval true/false N*/ Nbool hal_system_enable_systick(uint8_t ms); X_Bool hal_system_enable_systick(uint8_t ms); N N/** N* @brief 获取systickt N* @param none N* @retval 当前systickt值 N*/ Nbool hal_system_disable_systick(void); X_Bool hal_system_disable_systick(void); N N/** N* @brief 获取systickt N* @param none N* @retval 当前systickt值 N*/ Nuint32_t hal_system_get_tick(void); N N/** N* @brief 进入deep sleep mode 模式, 等待AP_RSTN 唤醒 N* @param polarity true:上升沿唤醒, false:下降沿唤醒 N* @retval none N*/ Nvoid hal_system_deep_sleep_mode(bool polarity); Xvoid hal_system_deep_sleep_mode(_Bool polarity); N N/** N* @brief 配置共享flash开关(使用过后注意关闭,常开功耗会增加) N* @param enable:true:可通过F_SPI访问内部flash , false:不可通过F_SPI访问内部flash N* @retval true/false N*/ Nbool hal_system_share_flash_mode(bool enable); X_Bool hal_system_share_flash_mode(_Bool enable); N N/** N* @brief sleep mode 配置 N* @param enable N* @retval none N*/ Nvoid hal_system_sleep_mode(bool enable); Xvoid hal_system_sleep_mode(_Bool enable); N N/** N* @brief reset chip N* @param none N* @retval none N*/ Nvoid hal_system_reset_chip(void); N N/** N* @brief 开关PVD检测 N* @param none N* @retval none N*/ Nvoid hal_system_set_pvd(bool enable); Xvoid hal_system_set_pvd(_Bool enable); N N/** N* @brief VCC电源开关， N* 使用场景: VCC掉电，13D与13M使用外灌电源时，关闭内部VCC供电,防止电源倒灌 N* @param enable: true:打开CP, false:关闭CP N* @retval none N*/ Nvoid hal_system_set_vcc(bool enable); Xvoid hal_system_set_vcc(_Bool enable); N N/** N* @brief 用户字节数组形式从flash读取数据,按页读取，每页1024字节 N* @param *usr_cfg_t_addr(数组首地址), N usr_cfg_t_size(数组大小可以超过1024，可以按页读也可连续跨页读) N flash_page （页0~63） N* @retval bool 无 N*/ Nbool hal_system_flash_read(uint8_t *usr_cfg_t_addr, uint16_t usr_cfg_t_size, uint8_t flash_page); X_Bool hal_system_flash_read(uint8_t *usr_cfg_t_addr, uint16_t usr_cfg_t_size, uint8_t flash_page); N N/** N* @brief 用户字节数组形式存入flash(次数有限，不可频繁写入),按页写入，每页1024字节 N* @param *usr_cfg_t_addr(数组首地址), N usr_cfg_t_size(数组大小可以超过1024，可以按页写也可连续跨页写入)， N 推荐按页顺序写入方式，第一次必须从0页开始写入，后续才可1~63任意页写入 N flash_page （写入页0~63） N* @retval bool 校验size是否超出 N*/ Nbool hal_system_flash_write(uint8_t *usr_cfg_t_addr, uint16_t usr_cfg_t_size, uint8_t flash_page); X_Bool hal_system_flash_write(uint8_t *usr_cfg_t_addr, uint16_t usr_cfg_t_size, uint8_t flash_page); N N#if defined(ISP_568) || defined(ISP_368) X#if 1L || 0L N /** N * @brief 控制DPHY内部校准开关 N * @param en: 使能开关 N * @retval none N */ N void hal_system_set_phy_calibration(bool en); X void hal_system_set_phy_calibration(_Bool en); N#endif N N#endif //__HAL_SYSTEM_H__ L 12 "..\src\board\board.c" 2 N#include "ArmCM0.h" L 1 "..\src\sdk\include\M0\ArmCM0.h" 1 N/**************************************************************************//** N * @file ARMCM0.h N * @brief CMSIS Core Peripheral Access Layer Header File for N * ARMCM0 Device N * @version V5.3.1 N * @date 09. July 2018 N ******************************************************************************/ N/* N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. N * N * SPDX-License-Identifier: Apache-2.0 N * N * Licensed under the Apache License, Version 2.0 (the License); you may N * not use this file except in compliance with the License. N * You may obtain a copy of the License at N * N * www.apache.org/licenses/LICENSE-2.0 N * N * Unless required by applicable law or agreed to in writing, software N * distributed under the License is distributed on an AS IS BASIS, WITHOUT N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. N * See the License for the specific language governing permissions and N * limitations under the License. N */ N N#ifndef ARMCM0_H N#define ARMCM0_H N N#ifdef __cplusplus Sextern "C" { N#endif N N N/* ------------------------- Interrupt Number Definition ------------------------ */ N Ntypedef enum IRQn N{ N /* ------------------- Processor Exceptions Numbers ----------------------------- */ N NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ N HardFault_IRQn = -13, /* 3 HardFault Interrupt */ N SVCall_IRQn = -5, /* 11 SV Call Interrupt */ N PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ N SysTick_IRQn = -1, /* 15 System Tick Interrupt */ N N /* ------------------- Processor Interrupt Numbers ------------------------------ */ N VIDC_IRQn = 0, N LCDC_IRQn = 1, N MIPI_RX_IRQn = 2, N MIPI_TX_IRQn = 3, N MEMC_IRQn = 4, N VPRE_IRQn = 5, N FLSCTRL_IRQn = 6, N DMA_IRQn = 7, N TIMER0_IRQn = 8, N TIMER1_IRQn = 9, N TIMER2_IRQn = 10, N TIMER3_IRQn = 11, N WDG_IRQn = 12, N UART_IRQn = 13, N I2C0_IRQn = 14, N I2C1_IRQn = 15, N SPIS_IRQn = 16, N SPIM_IRQn = 17, N ADC_IRQn = 18, N PWMDET_IRQn = 19, N OTP_IRQn = 20, N SWIRE_IRQn = 21, N PVD_IRQn = 22, N AP_NRESET_IRQn = 23, N EXTI_INT0_IRQn = 24, N EXTI_INT1_IRQn = 25, N EXTI_INT2_IRQn = 26, N EXTI_INT3_IRQn = 27, N EXTI_INT4_IRQn = 28, N EXTI_INT5_IRQn = 29, N EXTI_INT6_IRQn = 30, N EXTI_INT7_IRQn = 31 N /* Interrupts 10 .. 31 are left out */ N} IRQn_Type; N N N N N/* ================================================================================ */ N/* ================ Processor and Core Peripheral Section ================ */ N/* ================================================================================ */ N N/* ------- Start of section using anonymous unions and disabling warnings ------- */ N#if defined (__CC_ARM) X#if 1L N#pragma push N#pragma anon_unions N#elif defined (__ICCARM__) X#elif 0L S#pragma language=extended S#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) S#pragma clang diagnostic push S#pragma clang diagnostic ignored "-Wc11-extensions" S#pragma clang diagnostic ignored "-Wreserved-id-macro" S#elif defined (__GNUC__) S/* anonymous unions are enabled by default */ S#elif defined (__TMS470__) S/* anonymous unions are enabled by default */ S#elif defined (__TASKING__) S#pragma warning 586 S#elif defined (__CSMC__) S/* anonymous unions are enabled by default */ S#else S#warning Not supported compiler type N#endif N N/* -------- Configuration of Core Peripherals ----------------------------------- */ N#define __CM0_REV 0x0000U /* Core revision r0p0 */ N#define __MPU_PRESENT 0U /* no MPU present */ N#define __VTOR_PRESENT 0U /* no VTOR present */ N#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ //20220228 N#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ N N#define __FPU_PRESENT 0U /* Set to 1 if FPU is present */ N#define __FPU_DP 0U /* single precision FPU */ N#define __ICACHE_PRESENT 0U /* Set to 1 if I-CACHE is present */ N#define __DCACHE_PRESENT 0U /* Set to 1 if D-CACHE is present */ N#define __DSP_PRESENT 0U /* no DSP extension present */ N N#define FPGA_MODE 0 N#define EDA_MODE 0 N#define EXTERN_24M 0 N#define CPU_CLK_100M 0 N N#include "core_cm0.h" /* Processor and core peripherals */ L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h" 1 N/**************************************************************************//** N * @file core_cm0.h N * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File N * @version V5.0.6 N * @date 13. March 2019 N ******************************************************************************/ N/* N * Copyright (c) 2009-2019 Arm Limited. All rights reserved. N * N * SPDX-License-Identifier: Apache-2.0 N * N * Licensed under the Apache License, Version 2.0 (the License); you may N * not use this file except in compliance with the License. N * You may obtain a copy of the License at N * N * www.apache.org/licenses/LICENSE-2.0 N * N * Unless required by applicable law or agreed to in writing, software N * distributed under the License is distributed on an AS IS BASIS, WITHOUT N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. N * See the License for the specific language governing permissions and N * limitations under the License. N */ N N#if defined ( __ICCARM__ ) X#if 0L S #pragma system_include /* treat file as system include file for MISRA check */ S#elif defined (__clang__) X#elif 0L S #pragma clang system_header /* treat file as system include file */ N#endif N N#ifndef __CORE_CM0_H_GENERIC N#define __CORE_CM0_H_GENERIC N N#include N N#ifdef __cplusplus S extern "C" { N#endif N N/** N \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions N CMSIS violates the following MISRA-C:2004 rules: N N \li Required Rule 8.5, object/function definition in header file.
N Function definitions in header files are used to allow 'inlining'. N N \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
N Unions are used for effective representation of core registers. N N \li Advisory Rule 19.7, Function-like macro defined.
N Function-like macros are used to allow more efficient code. N */ N N N/******************************************************************************* N * CMSIS definitions N ******************************************************************************/ N/** N \ingroup Cortex_M0 N @{ N */ N N#include "cmsis_version.h" L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_version.h" 1 N/**************************************************************************//** N * @file cmsis_version.h N * @brief CMSIS Core(M) Version definitions N * @version V5.0.2 N * @date 19. April 2017 N ******************************************************************************/ N/* N * Copyright (c) 2009-2017 ARM Limited. All rights reserved. N * N * SPDX-License-Identifier: Apache-2.0 N * N * Licensed under the Apache License, Version 2.0 (the License); you may N * not use this file except in compliance with the License. N * You may obtain a copy of the License at N * N * www.apache.org/licenses/LICENSE-2.0 N * N * Unless required by applicable law or agreed to in writing, software N * distributed under the License is distributed on an AS IS BASIS, WITHOUT N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. N * See the License for the specific language governing permissions and N * limitations under the License. N */ N N#if defined ( __ICCARM__ ) X#if 0L S #pragma system_include /* treat file as system include file for MISRA check */ S#elif defined (__clang__) X#elif 0L S #pragma clang system_header /* treat file as system include file */ N#endif N N#ifndef __CMSIS_VERSION_H N#define __CMSIS_VERSION_H N N/* CMSIS Version definitions */ N#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ N#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ N#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ N __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ X#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | __CM_CMSIS_VERSION_SUB ) N#endif L 64 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h" 2 N N/* CMSIS CM0 definitions */ N#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ N#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ N#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ N __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ X#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB ) N N#define __CORTEX_M (0U) /*!< Cortex-M Core */ N N/** __FPU_USED indicates whether an FPU is used or not. N This core does not support an FPU at all N*/ N#define __FPU_USED 0U N N#if defined ( __CC_ARM ) X#if 1L N #if defined __TARGET_FPU_VFP X #if 0L S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" N #endif N N#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) X#elif 1L && (5060750 >= 6010050) S #if defined __ARM_FP S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" S #endif S S#elif defined ( __GNUC__ ) S #if defined (__VFP_FP__) && !defined(__SOFTFP__) S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" S #endif S S#elif defined ( __ICCARM__ ) S #if defined __ARMVFP__ S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" S #endif S S#elif defined ( __TI_ARM__ ) S #if defined __TI_VFP_SUPPORT__ S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" S #endif S S#elif defined ( __TASKING__ ) S #if defined __FPU_VFP__ S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" S #endif S S#elif defined ( __CSMC__ ) S #if ( __CSMC__ & 0x400U) S #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" S #endif S N#endif N N#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h" 1 N/**************************************************************************//** N * @file cmsis_compiler.h N * @brief CMSIS compiler generic header file N * @version V5.1.0 N * @date 09. October 2018 N ******************************************************************************/ N/* N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. N * N * SPDX-License-Identifier: Apache-2.0 N * N * Licensed under the Apache License, Version 2.0 (the License); you may N * not use this file except in compliance with the License. N * You may obtain a copy of the License at N * N * www.apache.org/licenses/LICENSE-2.0 N * N * Unless required by applicable law or agreed to in writing, software N * distributed under the License is distributed on an AS IS BASIS, WITHOUT N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. N * See the License for the specific language governing permissions and N * limitations under the License. N */ N N#ifndef __CMSIS_COMPILER_H N#define __CMSIS_COMPILER_H N N#include N N/* N * Arm Compiler 4/5 N */ N#if defined ( __CC_ARM ) X#if 1L N #include "cmsis_armcc.h" L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_armcc.h" 1 N/**************************************************************************//** N * @file cmsis_armcc.h N * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file N * @version V5.0.5 N * @date 14. December 2018 N ******************************************************************************/ N/* N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. N * N * SPDX-License-Identifier: Apache-2.0 N * N * Licensed under the Apache License, Version 2.0 (the License); you may N * not use this file except in compliance with the License. N * You may obtain a copy of the License at N * N * www.apache.org/licenses/LICENSE-2.0 N * N * Unless required by applicable law or agreed to in writing, software N * distributed under the License is distributed on an AS IS BASIS, WITHOUT N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. N * See the License for the specific language governing permissions and N * limitations under the License. N */ N N#ifndef __CMSIS_ARMCC_H N#define __CMSIS_ARMCC_H N N N#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) X#if 1L && (5060750 < 400677) S #error "Please use Arm Compiler Toolchain V4.0.677 or later!" N#endif N N/* CMSIS compiler control architecture macros */ N#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ N (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) X#if ((0L && (__TARGET_ARCH_6_M == 1)) || (1L && (1 == 1)) ) N #define __ARM_ARCH_6M__ 1 N#endif N N#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) X#if (0L && (__TARGET_ARCH_7_M == 1)) S #define __ARM_ARCH_7M__ 1 N#endif N N#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) X#if (0L && (__TARGET_ARCH_7E_M == 1)) S #define __ARM_ARCH_7EM__ 1 N#endif N N /* __ARM_ARCH_8M_BASE__ not applicable */ N /* __ARM_ARCH_8M_MAIN__ not applicable */ N N/* CMSIS compiler control DSP macros */ N#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) X#if ((0L && (__ARM_ARCH_7EM__ == 1)) ) S #define __ARM_FEATURE_DSP 1 N#endif N N/* CMSIS compiler specific defines */ N#ifndef __ASM N #define __ASM __asm N#endif N#ifndef __INLINE N #define __INLINE __inline N#endif N#ifndef __STATIC_INLINE N #define __STATIC_INLINE static __inline N#endif N#ifndef __STATIC_FORCEINLINE N #define __STATIC_FORCEINLINE static __forceinline N#endif N#ifndef __NO_RETURN N #define __NO_RETURN __declspec(noreturn) N#endif N#ifndef __USED N #define __USED __attribute__((used)) N#endif N#ifndef __WEAK N #define __WEAK __attribute__((weak)) N#endif N#ifndef __PACKED N #define __PACKED __attribute__((packed)) N#endif N#ifndef __PACKED_STRUCT N #define __PACKED_STRUCT __packed struct N#endif N#ifndef __PACKED_UNION N #define __PACKED_UNION __packed union N#endif N#ifndef __UNALIGNED_UINT32 /* deprecated */ N #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) N#endif N#ifndef __UNALIGNED_UINT16_WRITE N #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) N#endif N#ifndef __UNALIGNED_UINT16_READ N #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) N#endif N#ifndef __UNALIGNED_UINT32_WRITE N #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) N#endif N#ifndef __UNALIGNED_UINT32_READ N #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) N#endif N#ifndef __ALIGNED N #define __ALIGNED(x) __attribute__((aligned(x))) N#endif N#ifndef __RESTRICT N #define __RESTRICT __restrict N#endif N N/* ########################### Core Function Access ########################### */ N/** \ingroup CMSIS_Core_FunctionInterface N \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions N @{ N */ N N/** N \brief Enable IRQ Interrupts N \details Enables IRQ interrupts by clearing the I-bit in the CPSR. N Can only be executed in Privileged modes. N */ N/* intrinsic void __enable_irq(); */ N N N/** N \brief Disable IRQ Interrupts N \details Disables IRQ interrupts by setting the I-bit in the CPSR. N Can only be executed in Privileged modes. N */ N/* intrinsic void __disable_irq(); */ N N/** N \brief Get Control Register N \details Returns the content of the Control Register. N \return Control Register value N */ N__STATIC_INLINE uint32_t __get_CONTROL(void) Xstatic __inline uint32_t __get_CONTROL(void) N{ N register uint32_t __regControl __ASM("control"); X register uint32_t __regControl __asm("control"); N return(__regControl); N} N N N/** N \brief Set Control Register N \details Writes the given value to the Control Register. N \param [in] control Control Register value to set N */ N__STATIC_INLINE void __set_CONTROL(uint32_t control) Xstatic __inline void __set_CONTROL(uint32_t control) N{ N register uint32_t __regControl __ASM("control"); X register uint32_t __regControl __asm("control"); N __regControl = control; N} N N N/** N \brief Get IPSR Register N \details Returns the content of the IPSR Register. N \return IPSR Register value N */ N__STATIC_INLINE uint32_t __get_IPSR(void) Xstatic __inline uint32_t __get_IPSR(void) N{ N register uint32_t __regIPSR __ASM("ipsr"); X register uint32_t __regIPSR __asm("ipsr"); N return(__regIPSR); N} N N N/** N \brief Get APSR Register N \details Returns the content of the APSR Register. N \return APSR Register value N */ N__STATIC_INLINE uint32_t __get_APSR(void) Xstatic __inline uint32_t __get_APSR(void) N{ N register uint32_t __regAPSR __ASM("apsr"); X register uint32_t __regAPSR __asm("apsr"); N return(__regAPSR); N} N N N/** N \brief Get xPSR Register N \details Returns the content of the xPSR Register. N \return xPSR Register value N */ N__STATIC_INLINE uint32_t __get_xPSR(void) Xstatic __inline uint32_t __get_xPSR(void) N{ N register uint32_t __regXPSR __ASM("xpsr"); X register uint32_t __regXPSR __asm("xpsr"); N return(__regXPSR); N} N N N/** N \brief Get Process Stack Pointer N \details Returns the current value of the Process Stack Pointer (PSP). N \return PSP Register value N */ N__STATIC_INLINE uint32_t __get_PSP(void) Xstatic __inline uint32_t __get_PSP(void) N{ N register uint32_t __regProcessStackPointer __ASM("psp"); X register uint32_t __regProcessStackPointer __asm("psp"); N return(__regProcessStackPointer); N} N N N/** N \brief Set Process Stack Pointer N \details Assigns the given value to the Process Stack Pointer (PSP). N \param [in] topOfProcStack Process Stack Pointer value to set N */ N__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) Xstatic __inline void __set_PSP(uint32_t topOfProcStack) N{ N register uint32_t __regProcessStackPointer __ASM("psp"); X register uint32_t __regProcessStackPointer __asm("psp"); N __regProcessStackPointer = topOfProcStack; N} N N N/** N \brief Get Main Stack Pointer N \details Returns the current value of the Main Stack Pointer (MSP). N \return MSP Register value N */ N__STATIC_INLINE uint32_t __get_MSP(void) Xstatic __inline uint32_t __get_MSP(void) N{ N register uint32_t __regMainStackPointer __ASM("msp"); X register uint32_t __regMainStackPointer __asm("msp"); N return(__regMainStackPointer); N} N N N/** N \brief Set Main Stack Pointer N \details Assigns the given value to the Main Stack Pointer (MSP). N \param [in] topOfMainStack Main Stack Pointer value to set N */ N__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) Xstatic __inline void __set_MSP(uint32_t topOfMainStack) N{ N register uint32_t __regMainStackPointer __ASM("msp"); X register uint32_t __regMainStackPointer __asm("msp"); N __regMainStackPointer = topOfMainStack; N} N N N/** N \brief Get Priority Mask N \details Returns the current state of the priority mask bit from the Priority Mask Register. N \return Priority Mask value N */ N__STATIC_INLINE uint32_t __get_PRIMASK(void) Xstatic __inline uint32_t __get_PRIMASK(void) N{ N register uint32_t __regPriMask __ASM("primask"); X register uint32_t __regPriMask __asm("primask"); N return(__regPriMask); N} N N N/** N \brief Set Priority Mask N \details Assigns the given value to the Priority Mask Register. N \param [in] priMask Priority Mask N */ N__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) Xstatic __inline void __set_PRIMASK(uint32_t priMask) N{ N register uint32_t __regPriMask __ASM("primask"); X register uint32_t __regPriMask __asm("primask"); N __regPriMask = (priMask); N} N N N#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) X#if ((0L && (__ARM_ARCH_7M__ == 1)) || (0L && (__ARM_ARCH_7EM__ == 1)) ) S S/** S \brief Enable FIQ S \details Enables FIQ interrupts by clearing the F-bit in the CPSR. S Can only be executed in Privileged modes. S */ S#define __enable_fault_irq __enable_fiq S S S/** S \brief Disable FIQ S \details Disables FIQ interrupts by setting the F-bit in the CPSR. S Can only be executed in Privileged modes. S */ S#define __disable_fault_irq __disable_fiq S S S/** S \brief Get Base Priority S \details Returns the current value of the Base Priority register. S \return Base Priority register value S */ S__STATIC_INLINE uint32_t __get_BASEPRI(void) S{ S register uint32_t __regBasePri __ASM("basepri"); S return(__regBasePri); S} S S S/** S \brief Set Base Priority S \details Assigns the given value to the Base Priority register. S \param [in] basePri Base Priority value to set S */ S__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) S{ S register uint32_t __regBasePri __ASM("basepri"); S __regBasePri = (basePri & 0xFFU); S} S S S/** S \brief Set Base Priority with condition S \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, S or the new value increases the BASEPRI priority level. S \param [in] basePri Base Priority value to set S */ S__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) S{ S register uint32_t __regBasePriMax __ASM("basepri_max"); S __regBasePriMax = (basePri & 0xFFU); S} S S S/** S \brief Get Fault Mask S \details Returns the current value of the Fault Mask register. S \return Fault Mask register value S */ S__STATIC_INLINE uint32_t __get_FAULTMASK(void) S{ S register uint32_t __regFaultMask __ASM("faultmask"); S return(__regFaultMask); S} S S S/** S \brief Set Fault Mask S \details Assigns the given value to the Fault Mask register. S \param [in] faultMask Fault Mask value to set S */ S__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) S{ S register uint32_t __regFaultMask __ASM("faultmask"); S __regFaultMask = (faultMask & (uint32_t)1U); S} S N#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ X#endif N N N/** N \brief Get FPSCR N \details Returns the current value of the Floating Point Status/Control register. N \return Floating Point Status/Control register value N */ N__STATIC_INLINE uint32_t __get_FPSCR(void) Xstatic __inline uint32_t __get_FPSCR(void) N{ N#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ N (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) X#if ((1L && (0U == 1U)) && (1L && (0U == 1U)) ) S register uint32_t __regfpscr __ASM("fpscr"); S return(__regfpscr); N#else N return(0U); N#endif N} N N N/** N \brief Set FPSCR N \details Assigns the given value to the Floating Point Status/Control register. N \param [in] fpscr Floating Point Status/Control value to set N */ N__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) Xstatic __inline void __set_FPSCR(uint32_t fpscr) N{ N#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ N (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) X#if ((1L && (0U == 1U)) && (1L && (0U == 1U)) ) S register uint32_t __regfpscr __ASM("fpscr"); S __regfpscr = (fpscr); N#else N (void)fpscr; N#endif N} N N N/*@} end of CMSIS_Core_RegAccFunctions */ N N N/* ########################## Core Instruction Access ######################### */ N/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface N Access to dedicated instructions N @{ N*/ N N/** N \brief No Operation N \details No Operation does nothing. This instruction can be used for code alignment purposes. N */ N#define __NOP __nop N N N/** N \brief Wait For Interrupt N \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. N */ N#define __WFI __wfi N N N/** N \brief Wait For Event N \details Wait For Event is a hint instruction that permits the processor to enter N a low-power state until one of a number of events occurs. N */ N#define __WFE __wfe N N N/** N \brief Send Event N \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. N */ N#define __SEV __sev N N N/** N \brief Instruction Synchronization Barrier N \details Instruction Synchronization Barrier flushes the pipeline in the processor, N so that all instructions following the ISB are fetched from cache or memory, N after the instruction has been completed. N */ N#define __ISB() do {\ N __schedule_barrier();\ N __isb(0xF);\ N __schedule_barrier();\ N } while (0U) X#define __ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U) N N/** N \brief Data Synchronization Barrier N \details Acts as a special kind of Data Memory Barrier. N It completes when all explicit memory accesses before this instruction complete. N */ N#define __DSB() do {\ N __schedule_barrier();\ N __dsb(0xF);\ N __schedule_barrier();\ N } while (0U) X#define __DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U) N N/** N \brief Data Memory Barrier N \details Ensures the apparent order of the explicit memory operations before N and after the instruction, without ensuring their completion. N */ N#define __DMB() do {\ N __schedule_barrier();\ N __dmb(0xF);\ N __schedule_barrier();\ N } while (0U) X#define __DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U) N N N/** N \brief Reverse byte order (32 bit) N \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. N \param [in] value Value to reverse N \return Reversed value N */ N#define __REV __rev N N N/** N \brief Reverse byte order (16 bit) N \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. N \param [in] value Value to reverse N \return Reversed value N */ N#ifndef __NO_EMBEDDED_ASM N__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) X__attribute__((section(".rev16_text"))) static __inline __asm uint32_t __REV16(uint32_t value) N{ N rev16 r0, r0 N bx lr N} N#endif N N N/** N \brief Reverse byte order (16 bit) N \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. N \param [in] value Value to reverse N \return Reversed value N */ N#ifndef __NO_EMBEDDED_ASM N__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) X__attribute__((section(".revsh_text"))) static __inline __asm int16_t __REVSH(int16_t value) N{ N revsh r0, r0 N bx lr N} N#endif N N N/** N \brief Rotate Right in unsigned value (32 bit) N \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. N \param [in] op1 Value to rotate N \param [in] op2 Number of Bits to rotate N \return Rotated value N */ N#define __ROR __ror N N N/** N \brief Breakpoint N \details Causes the processor to enter Debug state. N Debug tools can use this to investigate system state when the instruction at a particular address is reached. N \param [in] value is ignored by the processor. N If required, a debugger can use it to store additional information about the breakpoint. N */ N#define __BKPT(value) __breakpoint(value) N N N/** N \brief Reverse bit order of value N \details Reverses the bit order of the given value. N \param [in] value Value to reverse N \return Reversed value N */ N#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) X#if ((0L && (__ARM_ARCH_7M__ == 1)) || (0L && (__ARM_ARCH_7EM__ == 1)) ) S #define __RBIT __rbit N#else N__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) X__attribute__((always_inline)) static __inline uint32_t __RBIT(uint32_t value) N{ N uint32_t result; N uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ N N result = value; /* r will be reversed bits of v; first get LSB of v */ N for (value >>= 1U; value != 0U; value >>= 1U) N { N result <<= 1U; N result |= value & 1U; N s--; N } N result <<= s; /* shift when v's highest bits are zero */ N return result; N} N#endif N N N/** N \brief Count leading zeros N \details Counts the number of leading zeros of a data value. N \param [in] value Value to count the leading zeros N \return number of leading zeros in value N */ N#define __CLZ __clz N N N#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) X#if ((0L && (__ARM_ARCH_7M__ == 1)) || (0L && (__ARM_ARCH_7EM__ == 1)) ) S S/** S \brief LDR Exclusive (8 bit) S \details Executes a exclusive LDR instruction for 8 bit value. S \param [in] ptr Pointer to data S \return value of type uint8_t at (*ptr) S */ S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) S #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) S#else S #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") S#endif S S S/** S \brief LDR Exclusive (16 bit) S \details Executes a exclusive LDR instruction for 16 bit values. S \param [in] ptr Pointer to data S \return value of type uint16_t at (*ptr) S */ S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) S #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) S#else S #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") S#endif S S S/** S \brief LDR Exclusive (32 bit) S \details Executes a exclusive LDR instruction for 32 bit values. S \param [in] ptr Pointer to data S \return value of type uint32_t at (*ptr) S */ S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) S #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) S#else S #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") S#endif S S S/** S \brief STR Exclusive (8 bit) S \details Executes a exclusive STR instruction for 8 bit values. S \param [in] value Value to store S \param [in] ptr Pointer to location S \return 0 Function succeeded S \return 1 Function failed S */ S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) S #define __STREXB(value, ptr) __strex(value, ptr) S#else S #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") S#endif S S S/** S \brief STR Exclusive (16 bit) S \details Executes a exclusive STR instruction for 16 bit values. S \param [in] value Value to store S \param [in] ptr Pointer to location S \return 0 Function succeeded S \return 1 Function failed S */ S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) S #define __STREXH(value, ptr) __strex(value, ptr) S#else S #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") S#endif S S S/** S \brief STR Exclusive (32 bit) S \details Executes a exclusive STR instruction for 32 bit values. S \param [in] value Value to store S \param [in] ptr Pointer to location S \return 0 Function succeeded S \return 1 Function failed S */ S#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) S #define __STREXW(value, ptr) __strex(value, ptr) S#else S #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") S#endif S S S/** S \brief Remove the exclusive lock S \details Removes the exclusive lock which is created by LDREX. S */ S#define __CLREX __clrex S S S/** S \brief Signed Saturate S \details Saturates a signed value. S \param [in] value Value to be saturated S \param [in] sat Bit position to saturate to (1..32) S \return Saturated value S */ S#define __SSAT __ssat S S S/** S \brief Unsigned Saturate S \details Saturates an unsigned value. S \param [in] value Value to be saturated S \param [in] sat Bit position to saturate to (0..31) S \return Saturated value S */ S#define __USAT __usat S S S/** S \brief Rotate Right with Extend (32 bit) S \details Moves each bit of a bitstring right by one bit. S The carry input is shifted in at the left end of the bitstring. S \param [in] value Value to rotate S \return Rotated value S */ S#ifndef __NO_EMBEDDED_ASM S__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) S{ S rrx r0, r0 S bx lr S} S#endif S S S/** S \brief LDRT Unprivileged (8 bit) S \details Executes a Unprivileged LDRT instruction for 8 bit value. S \param [in] ptr Pointer to data S \return value of type uint8_t at (*ptr) S */ S#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) S S S/** S \brief LDRT Unprivileged (16 bit) S \details Executes a Unprivileged LDRT instruction for 16 bit values. S \param [in] ptr Pointer to data S \return value of type uint16_t at (*ptr) S */ S#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) S S S/** S \brief LDRT Unprivileged (32 bit) S \details Executes a Unprivileged LDRT instruction for 32 bit values. S \param [in] ptr Pointer to data S \return value of type uint32_t at (*ptr) S */ S#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) S S S/** S \brief STRT Unprivileged (8 bit) S \details Executes a Unprivileged STRT instruction for 8 bit values. S \param [in] value Value to store S \param [in] ptr Pointer to location S */ S#define __STRBT(value, ptr) __strt(value, ptr) S S S/** S \brief STRT Unprivileged (16 bit) S \details Executes a Unprivileged STRT instruction for 16 bit values. S \param [in] value Value to store S \param [in] ptr Pointer to location S */ S#define __STRHT(value, ptr) __strt(value, ptr) S S S/** S \brief STRT Unprivileged (32 bit) S \details Executes a Unprivileged STRT instruction for 32 bit values. S \param [in] value Value to store S \param [in] ptr Pointer to location S */ S#define __STRT(value, ptr) __strt(value, ptr) S N#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ X#else N N/** N \brief Signed Saturate N \details Saturates a signed value. N \param [in] value Value to be saturated N \param [in] sat Bit position to saturate to (1..32) N \return Saturated value N */ N__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) X__attribute__((always_inline)) static __inline int32_t __SSAT(int32_t val, uint32_t sat) N{ N if ((sat >= 1U) && (sat <= 32U)) N { N const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); N const int32_t min = -1 - max ; N if (val > max) N { N return max; N } N else if (val < min) N { N return min; N } N } N return val; N} N N/** N \brief Unsigned Saturate N \details Saturates an unsigned value. N \param [in] value Value to be saturated N \param [in] sat Bit position to saturate to (0..31) N \return Saturated value N */ N__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) X__attribute__((always_inline)) static __inline uint32_t __USAT(int32_t val, uint32_t sat) N{ N if (sat <= 31U) N { N const uint32_t max = ((1U << sat) - 1U); N if (val > (int32_t)max) N { N return max; N } N else if (val < 0) N { N return 0U; N } N } N return (uint32_t)val; N} N N#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ N (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ X#endif N N/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ N N N/* ################### Compiler specific Intrinsics ########################### */ N/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics N Access to dedicated SIMD instructions N @{ N*/ N N#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) X#if ((0L && (__ARM_ARCH_7EM__ == 1)) ) S S#define __SADD8 __sadd8 S#define __QADD8 __qadd8 S#define __SHADD8 __shadd8 S#define __UADD8 __uadd8 S#define __UQADD8 __uqadd8 S#define __UHADD8 __uhadd8 S#define __SSUB8 __ssub8 S#define __QSUB8 __qsub8 S#define __SHSUB8 __shsub8 S#define __USUB8 __usub8 S#define __UQSUB8 __uqsub8 S#define __UHSUB8 __uhsub8 S#define __SADD16 __sadd16 S#define __QADD16 __qadd16 S#define __SHADD16 __shadd16 S#define __UADD16 __uadd16 S#define __UQADD16 __uqadd16 S#define __UHADD16 __uhadd16 S#define __SSUB16 __ssub16 S#define __QSUB16 __qsub16 S#define __SHSUB16 __shsub16 S#define __USUB16 __usub16 S#define __UQSUB16 __uqsub16 S#define __UHSUB16 __uhsub16 S#define __SASX __sasx S#define __QASX __qasx S#define __SHASX __shasx S#define __UASX __uasx S#define __UQASX __uqasx S#define __UHASX __uhasx S#define __SSAX __ssax S#define __QSAX __qsax S#define __SHSAX __shsax S#define __USAX __usax S#define __UQSAX __uqsax S#define __UHSAX __uhsax S#define __USAD8 __usad8 S#define __USADA8 __usada8 S#define __SSAT16 __ssat16 S#define __USAT16 __usat16 S#define __UXTB16 __uxtb16 S#define __UXTAB16 __uxtab16 S#define __SXTB16 __sxtb16 S#define __SXTAB16 __sxtab16 S#define __SMUAD __smuad S#define __SMUADX __smuadx S#define __SMLAD __smlad S#define __SMLADX __smladx S#define __SMLALD __smlald S#define __SMLALDX __smlaldx S#define __SMUSD __smusd S#define __SMUSDX __smusdx S#define __SMLSD __smlsd S#define __SMLSDX __smlsdx S#define __SMLSLD __smlsld S#define __SMLSLDX __smlsldx S#define __SEL __sel S#define __QADD __qadd S#define __QSUB __qsub S S#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ S ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) X#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) S S#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ S ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) X#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) S S#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ S ((int64_t)(ARG3) << 32U) ) >> 32U)) X#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32U) ) >> 32U)) S N#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ N/*@} end of group CMSIS_SIMD_intrinsics */ N N N#endif /* __CMSIS_ARMCC_H */ L 35 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\cmsis_compiler.h" 2 N N N/* N * Arm Compiler 6.6 LTM (armclang) N */ N#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) X#elif 1L && (5060750 >= 6010050) && (5060750 < 6100100) S #include "cmsis_armclang_ltm.h" S S /* S * Arm Compiler above 6.10.1 (armclang) S */ S#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) S #include "cmsis_armclang.h" S S S/* S * GNU Compiler S */ S#elif defined ( __GNUC__ ) S #include "cmsis_gcc.h" S S S/* S * IAR Compiler S */ S#elif defined ( __ICCARM__ ) S #include S S S/* S * TI Arm Compiler S */ S#elif defined ( __TI_ARM__ ) S #include S S #ifndef __ASM S #define __ASM __asm S #endif S #ifndef __INLINE S #define __INLINE inline S #endif S #ifndef __STATIC_INLINE S #define __STATIC_INLINE static inline S #endif S #ifndef __STATIC_FORCEINLINE S #define __STATIC_FORCEINLINE __STATIC_INLINE S #endif S #ifndef __NO_RETURN S #define __NO_RETURN __attribute__((noreturn)) S #endif S #ifndef __USED S #define __USED __attribute__((used)) S #endif S #ifndef __WEAK S #define __WEAK __attribute__((weak)) S #endif S #ifndef __PACKED S #define __PACKED __attribute__((packed)) S #endif S #ifndef __PACKED_STRUCT S #define __PACKED_STRUCT struct __attribute__((packed)) S #endif S #ifndef __PACKED_UNION S #define __PACKED_UNION union __attribute__((packed)) S #endif S #ifndef __UNALIGNED_UINT32 /* deprecated */ S struct __attribute__((packed)) T_UINT32 { uint32_t v; }; S #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) S #endif S #ifndef __UNALIGNED_UINT16_WRITE S __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; S #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) S #endif S #ifndef __UNALIGNED_UINT16_READ S __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; S #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) S #endif S #ifndef __UNALIGNED_UINT32_WRITE S __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; S #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) S #endif S #ifndef __UNALIGNED_UINT32_READ S __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; S #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) S #endif S #ifndef __ALIGNED S #define __ALIGNED(x) __attribute__((aligned(x))) S #endif S #ifndef __RESTRICT S #define __RESTRICT __restrict S #endif S S S/* S * TASKING Compiler S */ S#elif defined ( __TASKING__ ) S /* S * The CMSIS functions have been implemented as intrinsics in the compiler. S * Please use "carm -?i" to get an up to date list of all intrinsics, S * Including the CMSIS ones. S */ S S #ifndef __ASM S #define __ASM __asm S #endif S #ifndef __INLINE S #define __INLINE inline S #endif S #ifndef __STATIC_INLINE S #define __STATIC_INLINE static inline S #endif S #ifndef __STATIC_FORCEINLINE S #define __STATIC_FORCEINLINE __STATIC_INLINE S #endif S #ifndef __NO_RETURN S #define __NO_RETURN __attribute__((noreturn)) S #endif S #ifndef __USED S #define __USED __attribute__((used)) S #endif S #ifndef __WEAK S #define __WEAK __attribute__((weak)) S #endif S #ifndef __PACKED S #define __PACKED __packed__ S #endif S #ifndef __PACKED_STRUCT S #define __PACKED_STRUCT struct __packed__ S #endif S #ifndef __PACKED_UNION S #define __PACKED_UNION union __packed__ S #endif S #ifndef __UNALIGNED_UINT32 /* deprecated */ S struct __packed__ T_UINT32 { uint32_t v; }; S #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) S #endif S #ifndef __UNALIGNED_UINT16_WRITE S __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; S #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) S #endif S #ifndef __UNALIGNED_UINT16_READ S __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; S #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) S #endif S #ifndef __UNALIGNED_UINT32_WRITE S __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; S #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) S #endif S #ifndef __UNALIGNED_UINT32_READ S __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; S #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) S #endif S #ifndef __ALIGNED S #define __ALIGNED(x) __align(x) S #endif S #ifndef __RESTRICT S #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. S #define __RESTRICT S #endif S S S/* S * COSMIC Compiler S */ S#elif defined ( __CSMC__ ) S #include S S #ifndef __ASM S #define __ASM _asm S #endif S #ifndef __INLINE S #define __INLINE inline S #endif S #ifndef __STATIC_INLINE S #define __STATIC_INLINE static inline S #endif S #ifndef __STATIC_FORCEINLINE S #define __STATIC_FORCEINLINE __STATIC_INLINE S #endif S #ifndef __NO_RETURN S // NO RETURN is automatically detected hence no warning here S #define __NO_RETURN S #endif S #ifndef __USED S #warning No compiler specific solution for __USED. __USED is ignored. S #define __USED S #endif S #ifndef __WEAK S #define __WEAK __weak S #endif S #ifndef __PACKED S #define __PACKED @packed S #endif S #ifndef __PACKED_STRUCT S #define __PACKED_STRUCT @packed struct S #endif S #ifndef __PACKED_UNION S #define __PACKED_UNION @packed union S #endif S #ifndef __UNALIGNED_UINT32 /* deprecated */ S @packed struct T_UINT32 { uint32_t v; }; S #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) S #endif S #ifndef __UNALIGNED_UINT16_WRITE S __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; S #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) S #endif S #ifndef __UNALIGNED_UINT16_READ S __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; S #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) S #endif S #ifndef __UNALIGNED_UINT32_WRITE S __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; S #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) S #endif S #ifndef __UNALIGNED_UINT32_READ S __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; S #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) S #endif S #ifndef __ALIGNED S #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. S #define __ALIGNED(x) S #endif S #ifndef __RESTRICT S #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. S #define __RESTRICT S #endif S S S#else S #error Unknown compiler. N#endif N N N#endif /* __CMSIS_COMPILER_H */ N L 116 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\CMSIS\Core\Include\core_cm0.h" 2 N N N#ifdef __cplusplus S} N#endif N N#endif /* __CORE_CM0_H_GENERIC */ N N#ifndef __CMSIS_GENERIC N N#ifndef __CORE_CM0_H_DEPENDANT N#define __CORE_CM0_H_DEPENDANT N N#ifdef __cplusplus S extern "C" { N#endif N N/* check device defines and use defaults */ N#if defined __CHECK_DEVICE_DEFINES X#if 0L S #ifndef __CM0_REV S #define __CM0_REV 0x0000U S #warning "__CM0_REV not defined in device header file; using default!" S #endif S S #ifndef __NVIC_PRIO_BITS S #define __NVIC_PRIO_BITS 2U S #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" S #endif S S #ifndef __Vendor_SysTickConfig S #define __Vendor_SysTickConfig 0U S #warning "__Vendor_SysTickConfig not defined in device header file; using default!" S #endif N#endif N N/* IO definitions (access restrictions to peripheral registers) */ N/** N \defgroup CMSIS_glob_defs CMSIS Global Defines N N IO Type Qualifiers are used N \li to specify the access to peripheral variables. N \li for automatic generation of peripheral register debug information. N*/ N#ifdef __cplusplus S #define __I volatile /*!< Defines 'read only' permissions */ N#else N #define __I volatile const /*!< Defines 'read only' permissions */ N#endif N#define __O volatile /*!< Defines 'write only' permissions */ N#define __IO volatile /*!< Defines 'read / write' permissions */ N N/* following defines should be used for structure members */ N#define __IM volatile const /*! Defines 'read only' structure member permissions */ N#define __OM volatile /*! Defines 'write only' structure member permissions */ N#define __IOM volatile /*! Defines 'read / write' structure member permissions */ N N/*@} end of group Cortex_M0 */ N N N N/******************************************************************************* N * Register Abstraction N Core Register contain: N - Core Register N - Core NVIC Register N - Core SCB Register N - Core SysTick Register N ******************************************************************************/ N/** N \defgroup CMSIS_core_register Defines and Type Definitions N \brief Type definitions and defines for Cortex-M processor based devices. N*/ N N/** N \ingroup CMSIS_core_register N \defgroup CMSIS_CORE Status and Control Registers N \brief Core Register type definitions. N @{ N */ N N/** N \brief Union type to access the Application Program Status Register (APSR). N */ Ntypedef union N{ N struct N { N uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ N uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ N uint32_t C:1; /*!< bit: 29 Carry condition code flag */ N uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ N uint32_t N:1; /*!< bit: 31 Negative condition code flag */ N } b; /*!< Structure used for bit access */ N uint32_t w; /*!< Type used for word access */ N} APSR_Type; N N/* APSR Register Definitions */ N#define APSR_N_Pos 31U /*!< APSR: N Position */ N#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ N N#define APSR_Z_Pos 30U /*!< APSR: Z Position */ N#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ N N#define APSR_C_Pos 29U /*!< APSR: C Position */ N#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ N N#define APSR_V_Pos 28U /*!< APSR: V Position */ N#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ N N N/** N \brief Union type to access the Interrupt Program Status Register (IPSR). N */ Ntypedef union N{ N struct N { N uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ N uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ N } b; /*!< Structure used for bit access */ N uint32_t w; /*!< Type used for word access */ N} IPSR_Type; N N/* IPSR Register Definitions */ N#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ N#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ N N N/** N \brief Union type to access the Special-Purpose Program Status Registers (xPSR). N */ Ntypedef union N{ N struct N { N uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ N uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ N uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ N uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ N uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ N uint32_t C:1; /*!< bit: 29 Carry condition code flag */ N uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ N uint32_t N:1; /*!< bit: 31 Negative condition code flag */ N } b; /*!< Structure used for bit access */ N uint32_t w; /*!< Type used for word access */ N} xPSR_Type; N N/* xPSR Register Definitions */ N#define xPSR_N_Pos 31U /*!< xPSR: N Position */ N#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ N N#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ N#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ N N#define xPSR_C_Pos 29U /*!< xPSR: C Position */ N#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ N N#define xPSR_V_Pos 28U /*!< xPSR: V Position */ N#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ N N#define xPSR_T_Pos 24U /*!< xPSR: T Position */ N#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ N N#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ N#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ N N N/** N \brief Union type to access the Control Registers (CONTROL). N */ Ntypedef union N{ N struct N { N uint32_t _reserved0:1; /*!< bit: 0 Reserved */ N uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ N uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ N } b; /*!< Structure used for bit access */ N uint32_t w; /*!< Type used for word access */ N} CONTROL_Type; N N/* CONTROL Register Definitions */ N#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ N#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ N N/*@} end of group CMSIS_CORE */ N N N/** N \ingroup CMSIS_core_register N \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) N \brief Type definitions for the NVIC Registers N @{ N */ N N/** N \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). N */ Ntypedef struct N{ N __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ X volatile uint32_t ISER[1U]; N uint32_t RESERVED0[31U]; N __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ X volatile uint32_t ICER[1U]; N uint32_t RESERVED1[31U]; N __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ X volatile uint32_t ISPR[1U]; N uint32_t RESERVED2[31U]; N __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ X volatile uint32_t ICPR[1U]; N uint32_t RESERVED3[31U]; N uint32_t RESERVED4[64U]; N __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ X volatile uint32_t IP[8U]; N} NVIC_Type; N N/*@} end of group CMSIS_NVIC */ N N N/** N \ingroup CMSIS_core_register N \defgroup CMSIS_SCB System Control Block (SCB) N \brief Type definitions for the System Control Block Registers N @{ N */ N N/** N \brief Structure type to access the System Control Block (SCB). N */ Ntypedef struct N{ N __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ X volatile const uint32_t CPUID; N __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ X volatile uint32_t ICSR; N uint32_t RESERVED0; N __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ X volatile uint32_t AIRCR; N __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ X volatile uint32_t SCR; N __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ X volatile uint32_t CCR; N uint32_t RESERVED1; N __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ X volatile uint32_t SHP[2U]; N __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ X volatile uint32_t SHCSR; N} SCB_Type; N N/* SCB CPUID Register Definitions */ N#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ N#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ N N#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ N#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ N N#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ N#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ N N#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ N#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ N N#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ N#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ N N/* SCB Interrupt Control State Register Definitions */ N#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ N#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ N N#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ N#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ N N#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ N#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ N N#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ N#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ N N#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ N#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ N N#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ N#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ N N#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ N#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ N N#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ N#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ N N#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ N#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ N N/* SCB Application Interrupt and Reset Control Register Definitions */ N#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ N#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ N N#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ N#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ N N#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ N#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ N N#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ N#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ N N#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ N#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ N N/* SCB System Control Register Definitions */ N#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ N#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ N N#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ N#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ N N#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ N#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ N N/* SCB Configuration Control Register Definitions */ N#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ N#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ N N#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ N#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ N N/* SCB System Handler Control and State Register Definitions */ N#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ N#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ N N/*@} end of group CMSIS_SCB */ N N N/** N \ingroup CMSIS_core_register N \defgroup CMSIS_SysTick System Tick Timer (SysTick) N \brief Type definitions for the System Timer Registers. N @{ N */ N N/** N \brief Structure type to access the System Timer (SysTick). N */ Ntypedef struct N{ N __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ X volatile uint32_t CTRL; N __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ X volatile uint32_t LOAD; N __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ X volatile uint32_t VAL; N __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ X volatile const uint32_t CALIB; N} SysTick_Type; N N/* SysTick Control / Status Register Definitions */ N#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ N#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ N N#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ N#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ N N#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ N#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ N N#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ N#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ N N/* SysTick Reload Register Definitions */ N#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ N#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ N N/* SysTick Current Register Definitions */ N#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ N#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ N N/* SysTick Calibration Register Definitions */ N#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ N#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ N N#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ N#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ N N#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ N#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ N N/*@} end of group CMSIS_SysTick */ N N N/** N \ingroup CMSIS_core_register N \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) N \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. N Therefore they are not covered by the Cortex-M0 header file. N @{ N */ N/*@} end of group CMSIS_CoreDebug */ N N N/** N \ingroup CMSIS_core_register N \defgroup CMSIS_core_bitfield Core register bit field macros N \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). N @{ N */ N N/** N \brief Mask and shift a bit field value for use in a register bit range. N \param[in] field Name of the register bit field. N \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. N \return Masked and shifted value. N*/ N#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) N N/** N \brief Mask and shift a register value to extract a bit filed value. N \param[in] field Name of the register bit field. N \param[in] value Value of register. This parameter is interpreted as an uint32_t type. N \return Masked and shifted bit field value. N*/ N#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) N N/*@} end of group CMSIS_core_bitfield */ N N N/** N \ingroup CMSIS_core_register N \defgroup CMSIS_core_base Core Definitions N \brief Definitions for base addresses, unions, and structures. N @{ N */ N N/* Memory mapping of Core Hardware */ N#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ N#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ N#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ N#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ N N#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ N#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ N#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ N N N/*@} */ N N N N/******************************************************************************* N * Hardware Abstraction Layer N Core Function Interface contains: N - Core NVIC Functions N - Core SysTick Functions N - Core Register Access Functions N ******************************************************************************/ N/** N \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference N*/ N N N N/* ########################## NVIC functions #################################### */ N/** N \ingroup CMSIS_Core_FunctionInterface N \defgroup CMSIS_Core_NVICFunctions NVIC Functions N \brief Functions that manage interrupts and exceptions via the NVIC. N @{ N */ N N#ifdef CMSIS_NVIC_VIRTUAL S #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE S #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" S #endif S #include CMSIS_NVIC_VIRTUAL_HEADER_FILE N#else N #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping N #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping N #define NVIC_EnableIRQ __NVIC_EnableIRQ N #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ N #define NVIC_DisableIRQ __NVIC_DisableIRQ N #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ N #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ N #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ N/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ N #define NVIC_SetPriority __NVIC_SetPriority N #define NVIC_GetPriority __NVIC_GetPriority N #define NVIC_SystemReset __NVIC_SystemReset N#endif /* CMSIS_NVIC_VIRTUAL */ N N#ifdef CMSIS_VECTAB_VIRTUAL S #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE S #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" S #endif S #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE N#else N #define NVIC_SetVector __NVIC_SetVector N #define NVIC_GetVector __NVIC_GetVector N#endif /* (CMSIS_VECTAB_VIRTUAL) */ N N#define NVIC_USER_IRQ_OFFSET 16 N N N/* The following EXC_RETURN values are saved the LR on exception entry */ N#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ N#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ N#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ N N N/* Interrupt Priorities are WORD accessible only under Armv6-M */ N/* The following MACROS handle generation of the register offset and byte masks */ N#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) N#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) N#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) N N#define __NVIC_SetPriorityGrouping(X) (void)(X) N#define __NVIC_GetPriorityGrouping() (0U) N N/** N \brief Enable Interrupt N \details Enables a device specific interrupt in the NVIC interrupt controller. N \param [in] IRQn Device specific interrupt number. N \note IRQn must not be negative. N */ N__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) Xstatic __inline void __NVIC_EnableIRQ(IRQn_Type IRQn) N{ N if ((int32_t)(IRQn) >= 0) N { N NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); N } N} N N N/** N \brief Get Interrupt Enable status N \details Returns a device specific interrupt enable status from the NVIC interrupt controller. N \param [in] IRQn Device specific interrupt number. N \return 0 Interrupt is not enabled. N \return 1 Interrupt is enabled. N \note IRQn must not be negative. N */ N__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) Xstatic __inline uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) N{ N if ((int32_t)(IRQn) >= 0) N { N return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); X return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); N } N else N { N return(0U); N } N} N N N/** N \brief Disable Interrupt N \details Disables a device specific interrupt in the NVIC interrupt controller. N \param [in] IRQn Device specific interrupt number. N \note IRQn must not be negative. N */ N__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) Xstatic __inline void __NVIC_DisableIRQ(IRQn_Type IRQn) N{ N if ((int32_t)(IRQn) >= 0) N { N NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); N __DSB(); X do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); N __ISB(); X do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U); N } N} N N N/** N \brief Get Pending Interrupt N \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. N \param [in] IRQn Device specific interrupt number. N \return 0 Interrupt status is not pending. N \return 1 Interrupt status is pending. N \note IRQn must not be negative. N */ N__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) Xstatic __inline uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) N{ N if ((int32_t)(IRQn) >= 0) N { N return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); X return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); N } N else N { N return(0U); N } N} N N N/** N \brief Set Pending Interrupt N \details Sets the pending bit of a device specific interrupt in the NVIC pending register. N \param [in] IRQn Device specific interrupt number. N \note IRQn must not be negative. N */ N__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) Xstatic __inline void __NVIC_SetPendingIRQ(IRQn_Type IRQn) N{ N if ((int32_t)(IRQn) >= 0) N { N NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); N } N} N N N/** N \brief Clear Pending Interrupt N \details Clears the pending bit of a device specific interrupt in the NVIC pending register. N \param [in] IRQn Device specific interrupt number. N \note IRQn must not be negative. N */ N__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) Xstatic __inline void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) N{ N if ((int32_t)(IRQn) >= 0) N { N NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); N } N} N N N/** N \brief Set Interrupt Priority N \details Sets the priority of a device specific interrupt or a processor exception. N The interrupt number can be positive to specify a device specific interrupt, N or negative to specify a processor exception. N \param [in] IRQn Interrupt number. N \param [in] priority Priority to set. N \note The priority cannot be set for every processor exception. N */ N__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) Xstatic __inline void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) N{ N if ((int32_t)(IRQn) >= 0) N { N NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | X ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] = ((uint32_t)(((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | N (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); X (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); N } N else N { N SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | X ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] = ((uint32_t)(((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] & ~(0xFFUL << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))) | N (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); X (((priority << (8U - 2U)) & (uint32_t)0xFFUL) << ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL))); N } N} N N N/** N \brief Get Interrupt Priority N \details Reads the priority of a device specific interrupt or a processor exception. N The interrupt number can be positive to specify a device specific interrupt, N or negative to specify a processor exception. N \param [in] IRQn Interrupt number. N \return Interrupt Priority. N Value is aligned automatically to the implemented priority bits of the microcontroller. N */ N__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) Xstatic __inline uint32_t __NVIC_GetPriority(IRQn_Type IRQn) N{ N N if ((int32_t)(IRQn) >= 0) N { N return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); X return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[ ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); N } N else N { N return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); X return((uint32_t)(((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )] >> ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ) & (uint32_t)0xFFUL) >> (8U - 2U))); N } N} N N N/** N \brief Encode Priority N \details Encodes the priority for an interrupt with the given priority group, N preemptive priority value, and subpriority value. N In case of a conflict between priority grouping and available N priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. N \param [in] PriorityGroup Used priority group. N \param [in] PreemptPriority Preemptive priority value (starting from 0). N \param [in] SubPriority Subpriority value (starting from 0). N \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). N */ N__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) Xstatic __inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) N{ N uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ N uint32_t PreemptPriorityBits; N uint32_t SubPriorityBits; N N PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); X PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); N SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); X SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); N N return ( N ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | N ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) N ); N} N N N/** N \brief Decode Priority N \details Decodes an interrupt priority value with a given priority group to N preemptive priority value and subpriority value. N In case of a conflict between priority grouping and available N priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. N \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). N \param [in] PriorityGroup Used priority group. N \param [out] pPreemptPriority Preemptive priority value (starting from 0). N \param [out] pSubPriority Subpriority value (starting from 0). N */ N__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) Xstatic __inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) N{ N uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ N uint32_t PreemptPriorityBits; N uint32_t SubPriorityBits; N N PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); X PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(2U)) ? (uint32_t)(2U) : (uint32_t)(7UL - PriorityGroupTmp); N SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); X SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(2U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(2U)); N N *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); N *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); N} N N N N/** N \brief Set Interrupt Vector N \details Sets an interrupt vector in SRAM based interrupt vector table. N The interrupt number can be positive to specify a device specific interrupt, N or negative to specify a processor exception. N Address 0 must be mapped to SRAM. N \param [in] IRQn Interrupt number N \param [in] vector Address of interrupt handler function N */ N__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) Xstatic __inline void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) N{ N uint32_t vectors = 0x0U; N (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; X (* (int *) (vectors + ((int32_t)IRQn + 16) * 4)) = vector; N} N N N/** N \brief Get Interrupt Vector N \details Reads an interrupt vector from interrupt vector table. N The interrupt number can be positive to specify a device specific interrupt, N or negative to specify a processor exception. N \param [in] IRQn Interrupt number. N \return Address of interrupt handler function N */ N__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) Xstatic __inline uint32_t __NVIC_GetVector(IRQn_Type IRQn) N{ N uint32_t vectors = 0x0U; N return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); X return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + 16) * 4)); N} N N N/** N \brief System Reset N \details Initiates a system reset request to reset the MCU. N */ N__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) X__declspec(noreturn) static __inline void __NVIC_SystemReset(void) N{ N __DSB(); /* Ensure all outstanding memory accesses included X do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); N buffered write are completed before reset */ N SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | X ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR = ((0x5FAUL << 16U) | N SCB_AIRCR_SYSRESETREQ_Msk); X (1UL << 2U)); N __DSB(); /* Ensure completion of memory access */ X do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U); N N for(;;) /* wait until reset */ N { N __NOP(); X __nop(); N } N} N N/*@} end of CMSIS_Core_NVICFunctions */ N N N/* ########################## FPU functions #################################### */ N/** N \ingroup CMSIS_Core_FunctionInterface N \defgroup CMSIS_Core_FpuFunctions FPU Functions N \brief Function that provides FPU type. N @{ N */ N N/** N \brief get FPU type N \details returns the FPU type N \returns N - \b 0: No FPU N - \b 1: Single precision FPU N - \b 2: Double + Single precision FPU N */ N__STATIC_INLINE uint32_t SCB_GetFPUType(void) Xstatic __inline uint32_t SCB_GetFPUType(void) N{ N return 0U; /* No FPU */ N} N N N/*@} end of CMSIS_Core_FpuFunctions */ N N N N/* ################################## SysTick function ############################################ */ N/** N \ingroup CMSIS_Core_FunctionInterface N \defgroup CMSIS_Core_SysTickFunctions SysTick Functions N \brief Functions that configure the System. N @{ N */ N N#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) X#if 1L && (0U == 0U) N N/** N \brief System Tick Configuration N \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. N Counter is in free running mode to generate periodic interrupts. N \param [in] ticks Number of ticks between two interrupts. N \return 0 Function succeeded. N \return 1 Function failed. N \note When the variable __Vendor_SysTickConfig is set to 1, then the N function SysTick_Config is not included. In this case, the file device.h N must contain a vendor-specific implementation of this function. N */ N__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) Xstatic __inline uint32_t SysTick_Config(uint32_t ticks) N{ N if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) X if ((ticks - 1UL) > (0xFFFFFFUL )) N { N return (1UL); /* Reload value impossible */ N } N N SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ X ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->LOAD = (uint32_t)(ticks - 1UL); N NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ X __NVIC_SetPriority (SysTick_IRQn, (1UL << 2U) - 1UL); N SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ X ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->VAL = 0UL; N SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | X ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL = (1UL << 2U) | N SysTick_CTRL_TICKINT_Msk | X (1UL << 1U) | N SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ X (1UL ); N return (0UL); /* Function successful */ N} N N#endif N N/*@} end of CMSIS_Core_SysTickFunctions */ N N N N N#ifdef __cplusplus S} N#endif N N#endif /* __CORE_CM0_H_DEPENDANT */ N N#endif /* __CMSIS_GENERIC */ L 129 "..\src\sdk\include\M0\ArmCM0.h" 2 N#include "system_ARMCM0.h" /* System Header */ L 1 "C:\Users\Markin\AppData\Local\Arm\Packs\ARM\CMSIS\5.5.1\Device\ARM\ARMCM0\Include\system_ARMCM0.h" 1 N/**************************************************************************//** N * @file system_ARMCM0.h N * @brief CMSIS Device System Header File for N * ARMCM0 Device N * @version V5.3.1 N * @date 09. July 2018 N ******************************************************************************/ N/* N * Copyright (c) 2009-2018 Arm Limited. All rights reserved. N * N * SPDX-License-Identifier: Apache-2.0 N * N * Licensed under the Apache License, Version 2.0 (the License); you may N * not use this file except in compliance with the License. N * You may obtain a copy of the License at N * N * www.apache.org/licenses/LICENSE-2.0 N * N * Unless required by applicable law or agreed to in writing, software N * distributed under the License is distributed on an AS IS BASIS, WITHOUT N * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. N * See the License for the specific language governing permissions and N * limitations under the License. N */ N N#ifndef SYSTEM_ARMCM0_H N#define SYSTEM_ARMCM0_H N N#ifdef __cplusplus Sextern "C" { N#endif N Nextern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ N N N/** N \brief Setup the microcontroller system. N N Initialize the System and update the SystemCoreClock variable. N */ Nextern void SystemInit (void); N N N/** N \brief Update SystemCoreClock variable. N N Updates the SystemCoreClock with current core Clock retrieved from cpu registers. N */ Nextern void SystemCoreClockUpdate (void); N N#ifdef __cplusplus S} N#endif N N#endif /* SYSTEM_ARMCM0_H */ L 130 "..\src\sdk\include\M0\ArmCM0.h" 2 N N/*---------------------------------------------------------------------------- N Define clocks N *----------------------------------------------------------------------------*/ N#define XTAL (500000000UL) /* Oscillator frequency */ N N#if FPGA_MODE X#if 0 S#define SYSTEM_CLOCK (33300000U) N#else N/* 使用外部晶振时,系统时钟只能是100M,不使用外部晶振时,系统时钟可以是100M/80M*/ N#if EXTERN_24M X#if 0 S#define SYSTEM_CLOCK (100000000U) N#else N#if CPU_CLK_100M X#if 0 S#define SYSTEM_CLOCK (100000000U) N#else N#define SYSTEM_CLOCK (80000000U) N#endif N#endif N#endif N N/* -------- End of section using anonymous unions and disabling warnings -------- */ N#if defined (__CC_ARM) X#if 1L N#pragma pop N#elif defined (__ICCARM__) X#elif 0L S/* leave anonymous unions enabled */ S#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) S#pragma clang diagnostic pop S#elif defined (__GNUC__) S/* anonymous unions are enabled by default */ S#elif defined (__TMS470__) S/* anonymous unions are enabled by default */ S#elif defined (__TASKING__) S#pragma warning restore S#elif defined (__CSMC__) S/* anonymous unions are enabled by default */ S#else S#warning Not supported compiler type N#endif N N/* In HS mode and when the DMA is used, all variables and data structures dealing N with the DMA during the transaction process should be 4-bytes aligned */ N#define DMA_WORD_ALIGN_EN N#ifdef DMA_WORD_ALIGN_EN N#if defined (__GNUC__) /* GNU Compiler */ X#if 1L N#define __ALIGN_END __attribute__ ((aligned (4))) N#define __ALIGN_BEGIN N#else S#define __ALIGN_END S#if defined (__CC_ARM) /* ARM Compiler */ S#define __ALIGN_BEGIN __align(4) S#elif defined (__ICCARM__) /* IAR Compiler */ S#define __ALIGN_BEGIN S#elif defined (__TASKING__) /* TASKING Compiler */ S#define __ALIGN_BEGIN __align(4) S#endif /* __CC_ARM */ N#endif /* __GNUC__ */ N#else S S#define __ALIGN_BEGIN S#define __ALIGN_END S S#define __ALIGN_END_1 __attribute__ ((aligned (1))) N#endif /* DMA_WORD_ALIGN_EN */ N N/* __packed keyword used to decrease the data type alignment to 1-byte */ N#if defined (__CC_ARM) /* ARM Compiler */ X#if 1L N#define __packed __packed N#elif defined (__ICCARM__) /* IAR Compiler */ X#elif 0L S#define __packed __packed S#elif defined ( __GNUC__ ) /* GNU Compiler */ S#define __packed __attribute__ ((__packed__)) S#define __weak __attribute__((weak)) S#elif defined (__TASKING__) /* TASKING Compiler */ S#define __packed __unaligned N#endif /* __CC_ARM */ N N#ifdef __cplusplus S} N#endif N N#endif /* ARMCM0_H */ L 13 "..\src\board\board.c" 2 N Nvoid board_Init(void) N{ N hal_system_init(SYSTEM_CLOCK); X hal_system_init((80000000U)); N hal_system_enable_systick(1); N#if !EDA_MODE X#if !0 N hal_system_init_console(115200); N#endif N#if defined(ISP_568) || defined(ISP_368) X#if 1L || 0L N /* 从EFUSE读取DPHY校准值并设置 */ N hal_system_set_phy_calibration(true); X hal_system_set_phy_calibration(1); N#endif N} N