4487 lines
278 KiB
HTML
4487 lines
278 KiB
HTML
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
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<html><head>
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<title>Static Call Graph - [.\Objects\WL568_S21_NT37701.axf]</title></head>
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<body><HR>
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<H1>Static Call Graph for image .\Objects\WL568_S21_NT37701.axf</H1><HR>
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<BR><P>#<CALLGRAPH># ARM Linker, 5060750: Last Updated: Sat Mar 11 19:33:49 2023
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<BR><P>
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<H3>Maximum Stack Usage = 472 bytes + Unknown(Cycles, Untraceable Function Pointers)</H3><H3>
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Call chain for Maximum Stack Depth:</H3>
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pps_update_handle ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_tx_ctrl_init ⇒ hal_dsi_tx_init_data_mode ⇒ hal_dsi_tx_init_video_mode ⇒ hal_dsi_tx_calc_video_chunks ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
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<P>
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<H3>
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Mutually Recursive functions
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</H3> <LI><a href="#[1]">NMI_Handler</a> ⇒ <a href="#[1]">NMI_Handler</a><BR>
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<LI><a href="#[3]">SVC_Handler</a> ⇒ <a href="#[3]">SVC_Handler</a><BR>
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<LI><a href="#[4]">PendSV_Handler</a> ⇒ <a href="#[4]">PendSV_Handler</a><BR>
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<LI><a href="#[1a]">OTP_IRQn_Handler</a> ⇒ <a href="#[1a]">OTP_IRQn_Handler</a><BR>
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<LI><a href="#[1c]">PVD_IRQn_Handler</a> ⇒ <a href="#[1c]">PVD_IRQn_Handler</a><BR>
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</UL>
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<P>
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<H3>
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Function Pointers
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</H3><UL>
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<LI><a href="#[18]">ADC_IRQn_Handler</a> from irq_redirect .o(i.ADC_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[1d]">AP_NRESET_IRQn_Handler</a> from irq_redirect .o(i.AP_NRESET_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[d]">DMA_IRQn_Handler</a> from irq_redirect .o(i.DMA_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[1e]">EXTI_INT0_IRQn_Handler</a> from irq_redirect .o(i.EXTI_INT0_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[1f]">EXTI_INT1_IRQn_Handler</a> from irq_redirect .o(i.EXTI_INT1_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[20]">EXTI_INT2_IRQn_Handler</a> from irq_redirect .o(i.EXTI_INT2_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[21]">EXTI_INT3_IRQn_Handler</a> from irq_redirect .o(i.EXTI_INT3_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[22]">EXTI_INT4_IRQn_Handler</a> from irq_redirect .o(i.EXTI_INT4_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[23]">EXTI_INT5_IRQn_Handler</a> from irq_redirect .o(i.EXTI_INT5_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[24]">EXTI_INT6_IRQn_Handler</a> from irq_redirect .o(i.EXTI_INT6_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[25]">EXTI_INT7_IRQn_Handler</a> from irq_redirect .o(i.EXTI_INT7_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[c]">FLSCTRL_IRQn_Handler</a> from irq_redirect .o(i.FLSCTRL_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[2]">HardFault_Handler</a> from irq_redirect .o(i.HardFault_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[14]">I2C0_IRQn_Handler</a> from irq_redirect .o(i.I2C0_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[15]">I2C1_IRQn_Handler</a> from irq_redirect .o(i.I2C1_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[7]">LCDC_IRQn_Handler</a> from irq_redirect .o(i.LCDC_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[a]">MEMC_IRQn_Handler</a> from irq_redirect .o(i.MEMC_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[8]">MIPI_RX_IRQn_Handler</a> from irq_redirect .o(i.MIPI_RX_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[9]">MIPI_TX_IRQn_Handler</a> from irq_redirect .o(i.MIPI_TX_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[1]">NMI_Handler</a> from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[1a]">OTP_IRQn_Handler</a> from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[1c]">PVD_IRQn_Handler</a> from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[19]">PWMDET_IRQn_Handler</a> from irq_redirect .o(i.PWMDET_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[4]">PendSV_Handler</a> from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[0]">Reset_Handler</a> from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[17]">SPIM_IRQn_Handler</a> from irq_redirect .o(i.SPIM_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[16]">SPIS_IRQn_Handler</a> from irq_redirect .o(i.SPIS_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[3]">SVC_Handler</a> from startup_armcm0.o(.text) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[1b]">SWIRE_IRQn_Handler</a> from irq_redirect .o(i.SWIRE_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[5]">SysTick_Handler</a> from irq_redirect .o(i.SysTick_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[e]">TIMER0_IRQn_Handler</a> from irq_redirect .o(i.TIMER0_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[f]">TIMER1_IRQn_Handler</a> from irq_redirect .o(i.TIMER1_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[10]">TIMER2_IRQn_Handler</a> from irq_redirect .o(i.TIMER2_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[11]">TIMER3_IRQn_Handler</a> from irq_redirect .o(i.TIMER3_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[13]">UART_IRQn_Handler</a> from irq_redirect .o(i.UART_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[6]">VIDC_IRQn_Handler</a> from irq_redirect .o(i.VIDC_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[b]">VPRE_IRQn_Handler</a> from irq_redirect .o(i.VPRE_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[12]">WDG_IRQn_Handler</a> from irq_redirect .o(i.WDG_IRQn_Handler) referenced from startup_armcm0.o(RESET)
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<LI><a href="#[27]">__main</a> from entry.o(.ARM.Collect$$$$00000000) referenced from startup_armcm0.o(.text)
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<LI><a href="#[2a]">_sputc</a> from printfa.o(i._sputc) referenced from printfa.o(i.__0vsprintf)
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<LI><a href="#[55]">ap_dcs_read</a> from ap_demo.o(i.ap_dcs_read) referenced from ap_demo.o(i.open_mipi_rx)
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<LI><a href="#[59]">ap_get_reg_df</a> from ap_demo.o(i.ap_get_reg_df) referenced from ap_demo.o(.constdata)
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<LI><a href="#[2c]">ap_reset_cb</a> from ap_demo.o(i.ap_reset_cb) referenced from ap_demo.o(i.ap_demo)
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<LI><a href="#[5a]">ap_set_backlight_51</a> from ap_demo.o(i.ap_set_backlight_51) referenced from ap_demo.o(.constdata)
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<LI><a href="#[58]">ap_set_display_off</a> from ap_demo.o(i.ap_set_display_off) referenced from ap_demo.o(.constdata)
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<LI><a href="#[57]">ap_set_display_on</a> from ap_demo.o(i.ap_set_display_on) referenced from ap_demo.o(.constdata)
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<LI><a href="#[5c]">ap_set_enter_sleep_mode</a> from ap_demo.o(i.ap_set_enter_sleep_mode) referenced from ap_demo.o(.constdata)
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<LI><a href="#[5d]">ap_set_exit_sleep_mode</a> from ap_demo.o(i.ap_set_exit_sleep_mode) referenced from ap_demo.o(.constdata)
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<LI><a href="#[5e]">ap_set_tp_calibration_04</a> from ap_demo.o(i.ap_set_tp_calibration_04) referenced from ap_demo.o(.constdata)
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<LI><a href="#[5b]">ap_update_frame_rate</a> from ap_demo.o(i.ap_update_frame_rate) referenced from ap_demo.o(.constdata)
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<LI><a href="#[40]">app_ADC_IRQn_Handler</a> from drv_rxbr.o(i.app_ADC_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[4b]">app_AP_NRESET_IRQn_Handler</a> from drv_gpio.o(i.app_AP_NRESET_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[4c]">app_EXTI_INT0_IRQn_Handler</a> from drv_gpio.o(i.app_EXTI_INT0_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[4d]">app_EXTI_INT1_IRQn_Handler</a> from drv_gpio.o(i.app_EXTI_INT1_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[4e]">app_EXTI_INT2_IRQn_Handler</a> from drv_gpio.o(i.app_EXTI_INT2_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[4f]">app_EXTI_INT3_IRQn_Handler</a> from drv_gpio.o(i.app_EXTI_INT3_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[50]">app_EXTI_INT4_IRQn_Handler</a> from drv_gpio.o(i.app_EXTI_INT4_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[51]">app_EXTI_INT5_IRQn_Handler</a> from drv_gpio.o(i.app_EXTI_INT5_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[52]">app_EXTI_INT6_IRQn_Handler</a> from drv_gpio.o(i.app_EXTI_INT6_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[53]">app_EXTI_INT7_IRQn_Handler</a> from drv_gpio.o(i.app_EXTI_INT7_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[54]">app_HardFault_Handler</a> from drv_common.o(i.app_HardFault_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[3b]">app_I2C0_IRQn_Handler</a> from drv_i2c_slave.o(i.app_I2C0_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[3c]">app_I2C1_IRQn_Handler</a> from drv_i2c_master.o(i.app_I2C1_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[36]">app_LCDC_IRQn_Handler</a> from hal_internal_vsync.o(i.app_LCDC_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[42]">app_MEMC_IRQn_Handler</a> from drv_memc.o(i.app_MEMC_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[37]">app_MIPI_RX_IRQn_Handler</a> from drv_dsi_rx.o(i.app_MIPI_RX_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[38]">app_MIPI_TX_IRQn_Handler</a> from drv_dsi_tx.o(i.app_MIPI_TX_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[49]">app_PWMDET_IRQn_Handler</a> from drv_pwm.o(i.app_PWMDET_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[3e]">app_SPIM_IRQn_Handler</a> from drv_spi_master.o(i.app_SPIM_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[3d]">app_SPIS_IRQn_Handler</a> from hal_spi_slave.o(i.app_SPIS_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[4a]">app_SWIRE_IRQn_Handler</a> from drv_swire.o(i.app_SWIRE_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[35]">app_SysTick_Handler</a> from drv_common.o(i.app_SysTick_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[43]">app_TIMER0_IRQn_Handler</a> from drv_timer.o(i.app_TIMER0_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[44]">app_TIMER1_IRQn_Handler</a> from drv_timer.o(i.app_TIMER1_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[45]">app_TIMER2_IRQn_Handler</a> from drv_timer.o(i.app_TIMER2_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[46]">app_TIMER3_IRQn_Handler</a> from drv_timer.o(i.app_TIMER3_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[48]">app_UART_IRQn_Handler</a> from drv_uart.o(i.app_UART_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[41]">app_VIDC_IRQn_Handler</a> from drv_vidc.o(i.app_VIDC_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[3f]">app_VPRE_IRQn_Handler</a> from drv_rxbr.o(i.app_VPRE_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[47]">app_WDG_IRQn_Handler</a> from drv_wdg.o(i.app_WDG_IRQn_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[39]">app_dma_irq_handler</a> from drv_dma.o(i.app_dma_irq_handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[3a]">app_fls_ctrl_Handler</a> from norflash.o(i.app_fls_ctrl_Handler) referenced from irq_redirect .o(i.handle_init)
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<LI><a href="#[2d]">app_tp_i2cs_callback</a> from app_tp_transfer.o(i.app_tp_i2cs_callback) referenced from app_tp_transfer.o(i.app_tp_I2C_init)
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<LI><a href="#[28]">app_tp_screen_int_callback</a> from app_tp_transfer.o(i.app_tp_screen_int_callback) referenced from app_tp_transfer.o(i.S20_Start_init)
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<LI><a href="#[2e]">drv_i2c_dma_callback</a> from drv_i2c_dma.o(i.drv_i2c_dma_callback) referenced from drv_i2c_dma.o(i.drv_i2c_set_dma_irq_callback)
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<LI><a href="#[29]">fputc</a> from tau_log.o(i.fputc) referenced from printfa.o(i.__0printf)
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<LI><a href="#[2f]">hal_i2c_master_irq_callback</a> from hal_i2c_master.o(i.hal_i2c_master_irq_callback) referenced from hal_i2c_master.o(i.hal_i2c_m_dma_init)
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<LI><a href="#[31]">hal_i2c_s_dma_user_callback</a> from hal_i2c_slave.o(i.hal_i2c_s_dma_user_callback) referenced from hal_i2c_slave.o(i.hal_i2c_s_init)
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<LI><a href="#[30]">hal_i2c_slave_irq_callback</a> from hal_i2c_slave.o(i.hal_i2c_slave_irq_callback) referenced from hal_i2c_slave.o(i.hal_i2c_s_init)
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<LI><a href="#[26]">main</a> from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
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<LI><a href="#[56]">pps_update_handle</a> from ap_demo.o(i.pps_update_handle) referenced from ap_demo.o(i.open_mipi_rx)
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<LI><a href="#[32]">rxbr_irq0_callback</a> from hal_internal_vsync.o(i.rxbr_irq0_callback) referenced from hal_internal_vsync.o(i.hal_internal_vsync_init_rx)
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<LI><a href="#[33]">rxbr_irq1_callback</a> from hal_internal_vsync.o(i.rxbr_irq1_callback) referenced from hal_internal_vsync.o(i.hal_internal_vsync_init_rx)
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<LI><a href="#[2b]">soft_timer3_cb</a> from ap_demo.o(i.soft_timer3_cb) referenced from ap_demo.o(i.ap_demo)
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<LI><a href="#[2b]">soft_timer3_cb</a> from ap_demo.o(i.soft_timer3_cb) referenced from ap_demo.o(i.soft_timer3_cb)
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<LI><a href="#[34]">vidc_callback</a> from hal_internal_vsync.o(i.vidc_callback) referenced from hal_internal_vsync.o(i.hal_internal_vsync_init_rx)
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</UL>
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<P>
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<H3>
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Global Symbols
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</H3>
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<P><STRONG><a name="[27]"></a>__main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
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<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(.text)
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</UL>
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<P><STRONG><a name="[23a]"></a>_main_stk</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))
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<P><STRONG><a name="[5f]"></a>_main_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
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<BR><BR>[Calls]<UL><LI><a href="#[60]">>></a> __scatterload
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</UL>
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<P><STRONG><a name="[7f]"></a>__main_after_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
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<BR><BR>[Called By]<UL><LI><a href="#[60]">>></a> __scatterload
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</UL>
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<P><STRONG><a name="[23b]"></a>_main_clock</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))
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<P><STRONG><a name="[23c]"></a>_main_cpp_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))
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<P><STRONG><a name="[23d]"></a>_main_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))
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<P><STRONG><a name="[23e]"></a>__rt_final_cpp</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000D))
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<P><STRONG><a name="[23f]"></a>__rt_final_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$0000000F))
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<P><STRONG><a name="[0]"></a>Reset_Handler</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, startup_armcm0.o(.text))
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<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
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</UL>
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<P><STRONG><a name="[1]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text))
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<BR><BR>[Calls]<UL><LI><a href="#[1]">>></a> NMI_Handler
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</UL>
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<BR>[Called By]<UL><LI><a href="#[1]">>></a> NMI_Handler
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</UL>
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<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
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</UL>
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<P><STRONG><a name="[3]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text))
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<BR><BR>[Calls]<UL><LI><a href="#[3]">>></a> SVC_Handler
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</UL>
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<BR>[Called By]<UL><LI><a href="#[3]">>></a> SVC_Handler
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</UL>
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<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
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</UL>
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<P><STRONG><a name="[4]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text))
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<BR><BR>[Calls]<UL><LI><a href="#[4]">>></a> PendSV_Handler
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</UL>
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<BR>[Called By]<UL><LI><a href="#[4]">>></a> PendSV_Handler
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</UL>
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<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[1a]"></a>OTP_IRQn_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text))
|
|
<BR><BR>[Calls]<UL><LI><a href="#[1a]">>></a> OTP_IRQn_Handler
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1a]">>></a> OTP_IRQn_Handler
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[1c]"></a>PVD_IRQn_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, startup_armcm0.o(.text))
|
|
<BR><BR>[Calls]<UL><LI><a href="#[1c]">>></a> PVD_IRQn_Handler
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1c]">>></a> PVD_IRQn_Handler
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[240]"></a>__aeabi_uidiv</STRONG> (Thumb, 0 bytes, Stack size 12 bytes, uidiv.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[62]"></a>__aeabi_uidivmod</STRONG> (Thumb, 44 bytes, Stack size 12 bytes, uidiv.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[1a7]">>></a> hal_internal_vsync_set_tear_mode
|
|
<LI><a href="#[19f]">>></a> hal_internal_vsync_set_sync_line
|
|
<LI><a href="#[10a]">>></a> drv_dsi_rx_set_up_phy
|
|
<LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
<LI><a href="#[160]">>></a> hal_dsi_rx_ctrl_init_dsi_rx
|
|
<LI><a href="#[c2]">>></a> app_tp_screen_analysis_int
|
|
<LI><a href="#[ac]">>></a> hal_timer_start
|
|
<LI><a href="#[19b]">>></a> hal_dsi_rx_ctrl_set_cus_esc_clk
|
|
<LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
<LI><a href="#[f8]">>></a> drv_common_enable_systick
|
|
<LI><a href="#[124]">>></a> drv_i2c_master_init
|
|
<LI><a href="#[10b]">>></a> drv_phy_get_rate_para
|
|
<LI><a href="#[112]">>></a> drv_dsi_tx_phy_test_setup
|
|
<LI><a href="#[20f]">>></a> hal_lcdc_config_upscaler
|
|
<LI><a href="#[205]">>></a> vsync_set_te_mode
|
|
<LI><a href="#[231]">>></a> rx_receive_pps
|
|
<LI><a href="#[22c]">>></a> rx_partial_update
|
|
<LI><a href="#[96]">>></a> UART_SetBaudRate
|
|
<LI><a href="#[9d]">>></a> _printf_core
|
|
<LI><a href="#[61]">>></a> __aeabi_idivmod
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[241]"></a>__aeabi_idiv</STRONG> (Thumb, 0 bytes, Stack size 16 bytes, idiv.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[61]"></a>__aeabi_idivmod</STRONG> (Thumb, 40 bytes, Stack size 16 bytes, idiv.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = __aeabi_idivmod ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
<LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[242]"></a>__aeabi_memcpy</STRONG> (Thumb, 36 bytes, Stack size 0 bytes, memcpya.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[bb]"></a>__aeabi_memcpy4</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, memcpya.o(.text))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
<LI><a href="#[15f]">>></a> hal_internal_vsync_init_rx
|
|
<LI><a href="#[171]">>></a> hal_internal_sync_get_fb_setting
|
|
<LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
<LI><a href="#[a7]">>></a> open_mipi_rx
|
|
<LI><a href="#[59]">>></a> ap_get_reg_df
|
|
<LI><a href="#[1bd]">>></a> hal_internal_vsync_init_tx
|
|
<LI><a href="#[13a]">>></a> drv_param_init_set_ccm
|
|
<LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[243]"></a>__aeabi_memcpy8</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, memcpya.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[64]"></a>__aeabi_memset</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
|
|
<BR><BR>[Called By]<UL><LI><a href="#[65]">>></a> _memset$wrapper
|
|
<LI><a href="#[63]">>></a> __aeabi_memclr
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[244]"></a>__aeabi_memset4</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[245]"></a>__aeabi_memset8</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[63]"></a>__aeabi_memclr</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
|
|
<BR><BR>[Calls]<UL><LI><a href="#[64]">>></a> __aeabi_memset
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[151]"></a>__aeabi_memclr4</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
<LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
<LI><a href="#[1b5]">>></a> hal_dsi_tx_ctrl_create_handle
|
|
<LI><a href="#[150]">>></a> hal_dsi_rx_ctrl_create_handle
|
|
<LI><a href="#[224]">>></a> hal_uart_init
|
|
<LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
<LI><a href="#[1ff]">>></a> hal_internal_vsync_deinit
|
|
<LI><a href="#[231]">>></a> rx_receive_pps
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[246]"></a>__aeabi_memclr8</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, memseta.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[65]"></a>_memset$wrapper</STRONG> (Thumb, 18 bytes, Stack size 8 bytes, memseta.o(.text), UNUSED)
|
|
<BR><BR>[Calls]<UL><LI><a href="#[64]">>></a> __aeabi_memset
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[66]"></a>__aeabi_fadd</STRONG> (Thumb, 162 bytes, Stack size 24 bytes, fadd.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = __aeabi_fadd ⇒ _float_epilogue
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[68]">>></a> _float_round
|
|
<LI><a href="#[67]">>></a> _float_epilogue
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[1b2]">>></a> hal_dsi_tx_config_params_for_lane_rate
|
|
<LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
<LI><a href="#[101]">>></a> drv_dsi_rx_calc_ipi_tx_delay
|
|
<LI><a href="#[69]">>></a> __aeabi_fsub
|
|
<LI><a href="#[6a]">>></a> __aeabi_frsub
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[69]"></a>__aeabi_fsub</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, fadd.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = __aeabi_fsub ⇒ __aeabi_fadd ⇒ _float_epilogue
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[66]">>></a> __aeabi_fadd
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
<LI><a href="#[101]">>></a> drv_dsi_rx_calc_ipi_tx_delay
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[6a]"></a>__aeabi_frsub</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, fadd.o(.text), UNUSED)
|
|
<BR><BR>[Calls]<UL><LI><a href="#[66]">>></a> __aeabi_fadd
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[102]"></a>__aeabi_fmul</STRONG> (Thumb, 122 bytes, Stack size 16 bytes, fmul.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __aeabi_fmul
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
<LI><a href="#[101]">>></a> drv_dsi_rx_calc_ipi_tx_delay
|
|
<LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[6b]"></a>__aeabi_fdiv</STRONG> (Thumb, 124 bytes, Stack size 16 bytes, fdiv.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __aeabi_fdiv
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[68]">>></a> _float_round
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
<LI><a href="#[101]">>></a> drv_dsi_rx_calc_ipi_tx_delay
|
|
<LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1ae]"></a>__ARM_scalbnf</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, fscalb.o(.text))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[247]"></a>scalbnf</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, fscalb.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[6c]"></a>__aeabi_dadd</STRONG> (Thumb, 328 bytes, Stack size 48 bytes, dadd.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 104<LI>Call Chain = __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[6e]">>></a> __aeabi_lasr
|
|
<LI><a href="#[6d]">>></a> __aeabi_llsl
|
|
<LI><a href="#[70]">>></a> _double_round
|
|
<LI><a href="#[6f]">>></a> _double_epilogue
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[101]">>></a> drv_dsi_rx_calc_ipi_tx_delay
|
|
<LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
<LI><a href="#[20f]">>></a> hal_lcdc_config_upscaler
|
|
<LI><a href="#[71]">>></a> __aeabi_dsub
|
|
<LI><a href="#[9f]">>></a> _fp_digits
|
|
<LI><a href="#[72]">>></a> __aeabi_drsub
|
|
<LI><a href="#[ee]">>></a> ceil
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[71]"></a>__aeabi_dsub</STRONG> (Thumb, 12 bytes, Stack size 8 bytes, dadd.o(.text), UNUSED)
|
|
<BR><BR>[Calls]<UL><LI><a href="#[6c]">>></a> __aeabi_dadd
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[72]"></a>__aeabi_drsub</STRONG> (Thumb, 12 bytes, Stack size 8 bytes, dadd.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[6c]">>></a> __aeabi_dadd
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ee]">>></a> ceil
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[73]"></a>__aeabi_dmul</STRONG> (Thumb, 202 bytes, Stack size 72 bytes, dmul.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 128<LI>Call Chain = __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[6f]">>></a> _double_epilogue
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[eb]">>></a> calc_framebuffer_setting
|
|
<LI><a href="#[9f]">>></a> _fp_digits
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[74]"></a>__aeabi_ddiv</STRONG> (Thumb, 234 bytes, Stack size 40 bytes, ddiv.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = __aeabi_ddiv ⇒ _double_round
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[70]">>></a> _double_round
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[eb]">>></a> calc_framebuffer_setting
|
|
<LI><a href="#[9f]">>></a> _fp_digits
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[75]"></a>__aeabi_i2f</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, fflti.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = __aeabi_i2f ⇒ _float_epilogue
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[67]">>></a> _float_epilogue
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[76]"></a>__aeabi_ui2f</STRONG> (Thumb, 14 bytes, Stack size 8 bytes, ffltui.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = __aeabi_ui2f ⇒ _float_epilogue
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[67]">>></a> _float_epilogue
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
<LI><a href="#[101]">>></a> drv_dsi_rx_calc_ipi_tx_delay
|
|
<LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[77]"></a>__aeabi_ui2d</STRONG> (Thumb, 24 bytes, Stack size 16 bytes, dfltui.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = __aeabi_ui2d ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[6f]">>></a> _double_epilogue
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
<LI><a href="#[20f]">>></a> hal_lcdc_config_upscaler
|
|
<LI><a href="#[eb]">>></a> calc_framebuffer_setting
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1af]"></a>__aeabi_f2iz</STRONG> (Thumb, 50 bytes, Stack size 0 bytes, ffixi.o(.text))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
<LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1b4]"></a>__aeabi_f2uiz</STRONG> (Thumb, 40 bytes, Stack size 0 bytes, ffixui.o(.text))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[78]"></a>__aeabi_d2iz</STRONG> (Thumb, 62 bytes, Stack size 16 bytes, dfixi.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = __aeabi_d2iz ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[79]">>></a> __aeabi_llsr
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[7a]"></a>__aeabi_d2uiz</STRONG> (Thumb, 50 bytes, Stack size 8 bytes, dfixui.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __aeabi_d2uiz ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[79]">>></a> __aeabi_llsr
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[101]">>></a> drv_dsi_rx_calc_ipi_tx_delay
|
|
<LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
<LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
<LI><a href="#[20f]">>></a> hal_lcdc_config_upscaler
|
|
<LI><a href="#[eb]">>></a> calc_framebuffer_setting
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[106]"></a>__aeabi_f2d</STRONG> (Thumb, 40 bytes, Stack size 0 bytes, f2d.o(.text))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
<LI><a href="#[101]">>></a> drv_dsi_rx_calc_ipi_tx_delay
|
|
<LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[248]"></a>__aeabi_cdcmpeq</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, cdcmple.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[ed]"></a>__aeabi_cdcmple</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, cdcmple.o(.text))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[eb]">>></a> calc_framebuffer_setting
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[105]"></a>__aeabi_cfrcmple</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, cfrcmple.o(.text))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[101]">>></a> drv_dsi_rx_calc_ipi_tx_delay
|
|
<LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[7b]"></a>__aeabi_uldivmod</STRONG> (Thumb, 96 bytes, Stack size 48 bytes, uldiv.o(.text), UNUSED)
|
|
<BR><BR>[Calls]<UL><LI><a href="#[79]">>></a> __aeabi_llsr
|
|
<LI><a href="#[6d]">>></a> __aeabi_llsl
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[9d]">>></a> _printf_core
|
|
<LI><a href="#[9f]">>></a> _fp_digits
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[6d]"></a>__aeabi_llsl</STRONG> (Thumb, 32 bytes, Stack size 8 bytes, llshl.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_llsl
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[6c]">>></a> __aeabi_dadd
|
|
<LI><a href="#[7b]">>></a> __aeabi_uldivmod
|
|
<LI><a href="#[6f]">>></a> _double_epilogue
|
|
<LI><a href="#[7e]">>></a> __aeabi_d2ulz
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[249]"></a>_ll_shift_l</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, llshl.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[79]"></a>__aeabi_llsr</STRONG> (Thumb, 34 bytes, Stack size 8 bytes, llushr.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_llsr
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[7a]">>></a> __aeabi_d2uiz
|
|
<LI><a href="#[78]">>></a> __aeabi_d2iz
|
|
<LI><a href="#[7b]">>></a> __aeabi_uldivmod
|
|
<LI><a href="#[6f]">>></a> _double_epilogue
|
|
<LI><a href="#[7e]">>></a> __aeabi_d2ulz
|
|
<LI><a href="#[7d]">>></a> _dsqrt
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[24a]"></a>_ll_ushift_r</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, llushr.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[6e]"></a>__aeabi_lasr</STRONG> (Thumb, 38 bytes, Stack size 8 bytes, llsshr.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __aeabi_lasr
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[6c]">>></a> __aeabi_dadd
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[24b]"></a>_ll_sshift_r</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, llsshr.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[24c]"></a>__I$use$fp</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, iusefp.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[68]"></a>_float_round</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, fepilogue.o(.text))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[6b]">>></a> __aeabi_fdiv
|
|
<LI><a href="#[66]">>></a> __aeabi_fadd
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[67]"></a>_float_epilogue</STRONG> (Thumb, 114 bytes, Stack size 12 bytes, fepilogue.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = _float_epilogue
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[76]">>></a> __aeabi_ui2f
|
|
<LI><a href="#[75]">>></a> __aeabi_i2f
|
|
<LI><a href="#[66]">>></a> __aeabi_fadd
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[70]"></a>_double_round</STRONG> (Thumb, 26 bytes, Stack size 8 bytes, depilogue.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = _double_round
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[74]">>></a> __aeabi_ddiv
|
|
<LI><a href="#[6c]">>></a> __aeabi_dadd
|
|
<LI><a href="#[6f]">>></a> _double_epilogue
|
|
<LI><a href="#[7d]">>></a> _dsqrt
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[6f]"></a>_double_epilogue</STRONG> (Thumb, 164 bytes, Stack size 48 bytes, depilogue.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[7c]">>></a> __ARM_clz
|
|
<LI><a href="#[79]">>></a> __aeabi_llsr
|
|
<LI><a href="#[6d]">>></a> __aeabi_llsl
|
|
<LI><a href="#[70]">>></a> _double_round
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[77]">>></a> __aeabi_ui2d
|
|
<LI><a href="#[73]">>></a> __aeabi_dmul
|
|
<LI><a href="#[6c]">>></a> __aeabi_dadd
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[7d]"></a>_dsqrt</STRONG> (Thumb, 162 bytes, Stack size 32 bytes, dsqrt.o(.text))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = _dsqrt ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[79]">>></a> __aeabi_llsr
|
|
<LI><a href="#[70]">>></a> _double_round
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ec]">>></a> sqrt
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[7e]"></a>__aeabi_d2ulz</STRONG> (Thumb, 54 bytes, Stack size 8 bytes, dfixul.o(.text), UNUSED)
|
|
<BR><BR>[Calls]<UL><LI><a href="#[79]">>></a> __aeabi_llsr
|
|
<LI><a href="#[6d]">>></a> __aeabi_llsl
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[9f]">>></a> _fp_digits
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[a0]"></a>__aeabi_cdrcmple</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, cdrcmple.o(.text))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[9f]">>></a> _fp_digits
|
|
<LI><a href="#[ee]">>></a> ceil
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[60]"></a>__scatterload</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
|
|
<BR><BR>[Calls]<UL><LI><a href="#[7f]">>></a> __main_after_scatterload
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[5f]">>></a> _main_scatterload
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[24d]"></a>__scatterload_rt2</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[24e]"></a>__decompress</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __dczerorl2.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[24f]"></a>__decompress1</STRONG> (Thumb, 86 bytes, Stack size unknown bytes, __dczerorl2.o(.text), UNUSED)
|
|
|
|
<P><STRONG><a name="[18]"></a>ADC_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.ADC_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[1d]"></a>AP_NRESET_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.AP_NRESET_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[d]"></a>DMA_IRQn_Handler</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, irq_redirect .o(i.DMA_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[1e]"></a>EXTI_INT0_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, irq_redirect .o(i.EXTI_INT0_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[1f]"></a>EXTI_INT1_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, irq_redirect .o(i.EXTI_INT1_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[20]"></a>EXTI_INT2_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, irq_redirect .o(i.EXTI_INT2_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[21]"></a>EXTI_INT3_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, irq_redirect .o(i.EXTI_INT3_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[22]"></a>EXTI_INT4_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, irq_redirect .o(i.EXTI_INT4_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[23]"></a>EXTI_INT5_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, irq_redirect .o(i.EXTI_INT5_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[24]"></a>EXTI_INT6_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, irq_redirect .o(i.EXTI_INT6_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[25]"></a>EXTI_INT7_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, irq_redirect .o(i.EXTI_INT7_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[c]"></a>FLSCTRL_IRQn_Handler</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, irq_redirect .o(i.FLSCTRL_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[80]"></a>Gpio_swire_output</STRONG> (Thumb, 78 bytes, Stack size 16 bytes, ap_demo.o(i.Gpio_swire_output))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = Gpio_swire_output ⇒ hal_gpio_init_output ⇒ hal_gpio_set_mode
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[83]">>></a> hal_gpio_set_output_data
|
|
<LI><a href="#[81]">>></a> hal_gpio_init_output
|
|
<LI><a href="#[84]">>></a> delayUs
|
|
<LI><a href="#[82]">>></a> delayMs
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ad]">>></a> init_panel
|
|
<LI><a href="#[5c]">>></a> ap_set_enter_sleep_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[2]"></a>HardFault_Handler</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, irq_redirect .o(i.HardFault_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[14]"></a>I2C0_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.I2C0_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[15]"></a>I2C1_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.I2C1_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[7]"></a>LCDC_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.LCDC_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[85]"></a>LOG_printf</STRONG> (Thumb, 30 bytes, Stack size 24 bytes, tau_log.o(i.LOG_printf))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[86]">>></a> vsprintf
|
|
<LI><a href="#[87]">>></a> __2printf
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[184]">>></a> hal_internal_vsync_set_auto_hw_filter
|
|
<LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
<LI><a href="#[15e]">>></a> hal_dsi_rx_ctrl_init_clk
|
|
<LI><a href="#[a4]">>></a> hal_dsi_rx_ctrl_send_ack_cmd
|
|
<LI><a href="#[b4]">>></a> app_tp_transfer_screen_int
|
|
<LI><a href="#[b3]">>></a> app_tp_calibration_exec
|
|
<LI><a href="#[56]">>></a> pps_update_handle
|
|
<LI><a href="#[5b]">>></a> ap_update_frame_rate
|
|
<LI><a href="#[5d]">>></a> ap_set_exit_sleep_mode
|
|
<LI><a href="#[5c]">>></a> ap_set_enter_sleep_mode
|
|
<LI><a href="#[57]">>></a> ap_set_display_on
|
|
<LI><a href="#[58]">>></a> ap_set_display_off
|
|
<LI><a href="#[2c]">>></a> ap_reset_cb
|
|
<LI><a href="#[55]">>></a> ap_dcs_read
|
|
<LI><a href="#[a5]">>></a> ap_demo
|
|
<LI><a href="#[37]">>></a> app_MIPI_RX_IRQn_Handler
|
|
<LI><a href="#[36]">>></a> app_LCDC_IRQn_Handler
|
|
<LI><a href="#[f7]">>></a> drv_chip_rx_info_check
|
|
<LI><a href="#[1fd]">>></a> hal_internal_init_memc
|
|
<LI><a href="#[205]">>></a> vsync_set_te_mode
|
|
<LI><a href="#[34]">>></a> vidc_callback
|
|
<LI><a href="#[33]">>></a> rxbr_irq1_callback
|
|
<LI><a href="#[231]">>></a> rx_receive_pps
|
|
<LI><a href="#[229]">>></a> rx_get_dcs_packet_data
|
|
<LI><a href="#[ef]">>></a> check_pkt_buf_rev
|
|
<LI><a href="#[eb]">>></a> calc_framebuffer_setting
|
|
<LI><a href="#[54]">>></a> app_HardFault_Handler
|
|
<LI><a href="#[38]">>></a> app_MIPI_TX_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[a]"></a>MEMC_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.MEMC_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[8]"></a>MIPI_RX_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.MIPI_RX_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[9]"></a>MIPI_TX_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.MIPI_TX_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[19]"></a>PWMDET_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, irq_redirect .o(i.PWMDET_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[88]"></a>S20_Start_init</STRONG> (Thumb, 300 bytes, Stack size 16 bytes, app_tp_transfer.o(i.S20_Start_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 120<LI>Call Chain = S20_Start_init ⇒ app_tp_m_read ⇒ hal_i2c_m_dma_read ⇒ drv_i2c_master_read_dma ⇒ drv_dma_set_transfer ⇒ drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[8a]">>></a> hal_i2c_m_transfer_complate
|
|
<LI><a href="#[8d]">>></a> hal_gpio_set_pull_state
|
|
<LI><a href="#[90]">>></a> hal_gpio_reg_eint_cb
|
|
<LI><a href="#[8f]">>></a> hal_gpio_init_eint
|
|
<LI><a href="#[8b]">>></a> hal_gpio_get_input_data
|
|
<LI><a href="#[8e]">>></a> hal_gpio_ctrl_eint
|
|
<LI><a href="#[8c]">>></a> app_tp_m_write
|
|
<LI><a href="#[89]">>></a> app_tp_m_read
|
|
<LI><a href="#[82]">>></a> delayMs
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e4]">>></a> app_tp_transfer_screen_const
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[17]"></a>SPIM_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, irq_redirect .o(i.SPIM_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[16]"></a>SPIS_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, irq_redirect .o(i.SPIS_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[1b]"></a>SWIRE_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, irq_redirect .o(i.SWIRE_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[5]"></a>SysTick_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.SysTick_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[e]"></a>TIMER0_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.TIMER0_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[f]"></a>TIMER1_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.TIMER1_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[10]"></a>TIMER2_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.TIMER2_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[11]"></a>TIMER3_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.TIMER3_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[91]"></a>UART0_IRQ_Handle</STRONG> (Thumb, 20 bytes, Stack size 8 bytes, drv_uart.o(i.UART0_IRQ_Handle))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = UART0_IRQ_Handle ⇒ UART_TransferHandleIRQ ⇒ UART_ResetRxFIFO
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
<LI><a href="#[92]">>></a> UART_TransferHandleIRQ
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[48]">>></a> app_UART_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[9a]"></a>UART_DisableDma</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, drv_uart.o(i.UART_DisableDma))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[99]">>></a> UART_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[95]"></a>UART_GetInstance</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, drv_uart.o(i.UART_GetInstance))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[99]">>></a> UART_init
|
|
<LI><a href="#[94]">>></a> UART_ResetRxFIFO
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[13]"></a>UART_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.UART_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[94]"></a>UART_ResetRxFIFO</STRONG> (Thumb, 32 bytes, Stack size 8 bytes, drv_uart.o(i.UART_ResetRxFIFO))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = UART_ResetRxFIFO
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[95]">>></a> UART_GetInstance
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[92]">>></a> UART_TransferHandleIRQ
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[96]"></a>UART_SetBaudRate</STRONG> (Thumb, 72 bytes, Stack size 24 bytes, drv_uart.o(i.UART_SetBaudRate))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = UART_SetBaudRate ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[99]">>></a> UART_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[97]"></a>UART_SwitchSCLK</STRONG> (Thumb, 26 bytes, Stack size 8 bytes, drv_uart.o(i.UART_SwitchSCLK))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = UART_SwitchSCLK
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[98]">>></a> drv_crgu_set_clock
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[99]">>></a> UART_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[92]"></a>UART_TransferHandleIRQ</STRONG> (Thumb, 308 bytes, Stack size 32 bytes, drv_uart.o(i.UART_TransferHandleIRQ))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = UART_TransferHandleIRQ ⇒ UART_ResetRxFIFO
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[94]">>></a> UART_ResetRxFIFO
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[91]">>></a> UART0_IRQ_Handle
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[228]"></a>UART_WriteBlocking</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, drv_uart.o(i.UART_WriteBlocking))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[14f]">>></a> hal_uart_transmit_blocking
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[99]"></a>UART_init</STRONG> (Thumb, 182 bytes, Stack size 24 bytes, drv_uart.o(i.UART_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 60<LI>Call Chain = UART_init ⇒ UART_SetBaudRate ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[9b]">>></a> drv_sys_cfg_set_int
|
|
<LI><a href="#[97]">>></a> UART_SwitchSCLK
|
|
<LI><a href="#[96]">>></a> UART_SetBaudRate
|
|
<LI><a href="#[95]">>></a> UART_GetInstance
|
|
<LI><a href="#[9a]">>></a> UART_DisableDma
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[224]">>></a> hal_uart_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[6]"></a>VIDC_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.VIDC_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[b]"></a>VPRE_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.VPRE_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[12]"></a>WDG_IRQn_Handler</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, irq_redirect .o(i.WDG_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> startup_armcm0.o(RESET)
|
|
</UL>
|
|
<P><STRONG><a name="[9c]"></a>__0printf</STRONG> (Thumb, 24 bytes, Stack size 24 bytes, printfa.o(i.__0printf), UNUSED)
|
|
<BR><BR>[Calls]<UL><LI><a href="#[9d]">>></a> _printf_core
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[250]"></a>__1printf</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0printf), UNUSED)
|
|
|
|
<P><STRONG><a name="[87]"></a>__2printf</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0printf))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = __2printf
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[100]">>></a> drv_dsc_dec_enable
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[f7]">>></a> drv_chip_rx_info_check
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[251]"></a>__c89printf</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0printf), UNUSED)
|
|
|
|
<P><STRONG><a name="[252]"></a>printf</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0printf), UNUSED)
|
|
|
|
<P><STRONG><a name="[9e]"></a>__0vsprintf</STRONG> (Thumb, 30 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf), UNUSED)
|
|
<BR><BR>[Calls]<UL><LI><a href="#[2a]">>></a> _sputc
|
|
<LI><a href="#[9d]">>></a> _printf_core
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[253]"></a>__1vsprintf</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf), UNUSED)
|
|
|
|
<P><STRONG><a name="[254]"></a>__2vsprintf</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf), UNUSED)
|
|
|
|
<P><STRONG><a name="[255]"></a>__c89vsprintf</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf), UNUSED)
|
|
|
|
<P><STRONG><a name="[86]"></a>vsprintf</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, printfa.o(i.__0vsprintf))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = vsprintf
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[7c]"></a>__ARM_clz</STRONG> (Thumb, 46 bytes, Stack size 0 bytes, depilogue.o(i.__ARM_clz))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[6f]">>></a> _double_epilogue
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[cc]"></a>__ARM_common_switch8</STRONG> (Thumb, 26 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.__ARM_common_switch8))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[144]">>></a> drv_rxbr_set_cmd_filter
|
|
<LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
<LI><a href="#[12d]">>></a> drv_i2c_s_clear_it_pending_bit
|
|
<LI><a href="#[121]">>></a> drv_i2c_m_clear_it_pending_bit
|
|
<LI><a href="#[120]">>></a> drv_gpio_set_pull_state
|
|
<LI><a href="#[111]">>></a> drv_dsi_tx_phy_status_stopstate
|
|
<LI><a href="#[103]">>></a> drv_dsi_rx_get_color_bpp
|
|
<LI><a href="#[3d]">>></a> app_SPIS_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[256]"></a>__scatterload_copy</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)
|
|
|
|
<P><STRONG><a name="[257]"></a>__scatterload_null</STRONG> (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)
|
|
|
|
<P><STRONG><a name="[258]"></a>__scatterload_zeroinit</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)
|
|
|
|
<P><STRONG><a name="[236]"></a>__set_errno</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, errno.o(i.__set_errno))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[ec]">>></a> sqrt
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[a5]"></a>ap_demo</STRONG> (Thumb, 292 bytes, Stack size 0 bytes, ap_demo.o(i.ap_demo))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 432<LI>Call Chain = ap_demo ⇒ open_mipi_rx ⇒ hal_dsi_rx_ctrl_init ⇒ hal_internal_vsync_init_rx ⇒ calc_framebuffer_setting ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[ac]">>></a> hal_timer_start
|
|
<LI><a href="#[ab]">>></a> hal_timer_init
|
|
<LI><a href="#[ba]">>></a> hal_system_set_vcc
|
|
<LI><a href="#[83]">>></a> hal_gpio_set_output_data
|
|
<LI><a href="#[b2]">>></a> hal_gpio_set_ap_reset_int
|
|
<LI><a href="#[81]">>></a> hal_gpio_init_output
|
|
<LI><a href="#[af]">>></a> hal_dsi_tx_ctrl_write_cmd
|
|
<LI><a href="#[b6]">>></a> hal_dsi_tx_ctrl_stop
|
|
<LI><a href="#[ae]">>></a> hal_dsi_tx_ctrl_start
|
|
<LI><a href="#[b7]">>></a> hal_dsi_tx_ctrl_deinit
|
|
<LI><a href="#[b8]">>></a> hal_dsi_rx_ctrl_stop
|
|
<LI><a href="#[b5]">>></a> hal_dsi_rx_ctrl_dsc_async_handler
|
|
<LI><a href="#[b9]">>></a> hal_dsi_rx_ctrl_deinit
|
|
<LI><a href="#[82]">>></a> delayMs
|
|
<LI><a href="#[b1]">>></a> app_tp_transfer_screen_start
|
|
<LI><a href="#[b4]">>></a> app_tp_transfer_screen_int
|
|
<LI><a href="#[b0]">>></a> app_tp_phone_clear_reset_on
|
|
<LI><a href="#[aa]">>></a> app_tp_init
|
|
<LI><a href="#[a6]">>></a> app_tp_I2C_init
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[b3]">>></a> app_tp_calibration_exec
|
|
<LI><a href="#[a7]">>></a> open_mipi_rx
|
|
<LI><a href="#[ad]">>></a> init_panel
|
|
<LI><a href="#[a8]">>></a> init_mipi_tx
|
|
<LI><a href="#[a9]">>></a> __NVIC_SetPriority
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[26]">>></a> main
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[c0]"></a>ap_tp_calibration</STRONG> (Thumb, 170 bytes, Stack size 8 bytes, app_tp_transfer.o(i.ap_tp_calibration))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = ap_tp_calibration ⇒ app_tp_m_write ⇒ hal_i2c_m_dma_write ⇒ drv_i2c_master_write_dma ⇒ drv_dma_set_transfer ⇒ drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[8a]">>></a> hal_i2c_m_transfer_complate
|
|
<LI><a href="#[8c]">>></a> app_tp_m_write
|
|
<LI><a href="#[82]">>></a> delayMs
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[b3]">>></a> app_tp_calibration_exec
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[e3]"></a>ap_tp_scan_point_init</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, app_tp_transfer.o(i.ap_tp_scan_point_init))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[e2]">>></a> app_tp_screen_reset
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[c1]"></a>ap_tp_simulate_finger_release_event</STRONG> (Thumb, 44 bytes, Stack size 16 bytes, app_tp_transfer.o(i.ap_tp_simulate_finger_release_event))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 84<LI>Call Chain = ap_tp_simulate_finger_release_event ⇒ app_tp_screen_analysis_int ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[c2]">>></a> app_tp_screen_analysis_int
|
|
<LI><a href="#[82]">>></a> delayMs
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e2]">>></a> app_tp_screen_reset
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[40]"></a>app_ADC_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, drv_rxbr.o(i.app_ADC_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_ADC_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[4b]"></a>app_AP_NRESET_IRQn_Handler</STRONG> (Thumb, 32 bytes, Stack size 8 bytes, drv_gpio.o(i.app_AP_NRESET_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = app_AP_NRESET_IRQn_Handler ⇒ drv_ap_rst_trig_edge_detect
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
<LI><a href="#[c4]">>></a> drv_ap_rst_trig_edge_detect
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[4c]"></a>app_EXTI_INT0_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, drv_gpio.o(i.app_EXTI_INT0_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_EXTI_INT0_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[4d]"></a>app_EXTI_INT1_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, drv_gpio.o(i.app_EXTI_INT1_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_EXTI_INT1_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[4e]"></a>app_EXTI_INT2_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, drv_gpio.o(i.app_EXTI_INT2_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_EXTI_INT2_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[4f]"></a>app_EXTI_INT3_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, drv_gpio.o(i.app_EXTI_INT3_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_EXTI_INT3_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[50]"></a>app_EXTI_INT4_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, drv_gpio.o(i.app_EXTI_INT4_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_EXTI_INT4_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[51]"></a>app_EXTI_INT5_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, drv_gpio.o(i.app_EXTI_INT5_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_EXTI_INT5_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[52]"></a>app_EXTI_INT6_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, drv_gpio.o(i.app_EXTI_INT6_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_EXTI_INT6_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[53]"></a>app_EXTI_INT7_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, drv_gpio.o(i.app_EXTI_INT7_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_EXTI_INT7_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[54]"></a>app_HardFault_Handler</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_common.o(i.app_HardFault_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = app_HardFault_Handler ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[3b]"></a>app_I2C0_IRQn_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_i2c_slave.o(i.app_I2C0_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[3c]"></a>app_I2C1_IRQn_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_i2c_master.o(i.app_I2C1_IRQn_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[36]"></a>app_LCDC_IRQn_Handler</STRONG> (Thumb, 98 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.app_LCDC_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = app_LCDC_IRQn_Handler ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
<LI><a href="#[c6]">>></a> drv_param_init_get_ccm
|
|
<LI><a href="#[c8]">>></a> drv_lcdc_config_int_single
|
|
<LI><a href="#[c7]">>></a> drv_lcdc_config_ccm
|
|
<LI><a href="#[c5]">>></a> soft_gen_te
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[42]"></a>app_MEMC_IRQn_Handler</STRONG> (Thumb, 132 bytes, Stack size 8 bytes, drv_memc.o(i.app_MEMC_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_MEMC_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
<LI><a href="#[c9]">>></a> drv_memc_get_status
|
|
<LI><a href="#[ca]">>></a> drv_memc_clear_status
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[37]"></a>app_MIPI_RX_IRQn_Handler</STRONG> (Thumb, 232 bytes, Stack size 24 bytes, drv_dsi_rx.o(i.app_MIPI_RX_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = app_MIPI_RX_IRQn_Handler ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[38]"></a>app_MIPI_TX_IRQn_Handler</STRONG> (Thumb, 56 bytes, Stack size 16 bytes, drv_dsi_tx.o(i.app_MIPI_TX_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = app_MIPI_TX_IRQn_Handler ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[49]"></a>app_PWMDET_IRQn_Handler</STRONG> (Thumb, 62 bytes, Stack size 24 bytes, drv_pwm.o(i.app_PWMDET_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = app_PWMDET_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[3e]"></a>app_SPIM_IRQn_Handler</STRONG> (Thumb, 34 bytes, Stack size 8 bytes, drv_spi_master.o(i.app_SPIM_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = app_SPIM_IRQn_Handler
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[cb]">>></a> __NVIC_ClearPendingIRQ
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[3d]"></a>app_SPIS_IRQn_Handler</STRONG> (Thumb, 500 bytes, Stack size 24 bytes, hal_spi_slave.o(i.app_SPIS_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = app_SPIS_IRQn_Handler ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[cc]">>></a> __ARM_common_switch8
|
|
<LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
<LI><a href="#[cd]">>></a> __NVIC_SetPriority
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[4a]"></a>app_SWIRE_IRQn_Handler</STRONG> (Thumb, 28 bytes, Stack size 8 bytes, drv_swire.o(i.app_SWIRE_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = app_SWIRE_IRQn_Handler ⇒ drv_swire_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
<LI><a href="#[ce]">>></a> drv_swire_set_int
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[35]"></a>app_SysTick_Handler</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, drv_common.o(i.app_SysTick_Handler))
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[43]"></a>app_TIMER0_IRQn_Handler</STRONG> (Thumb, 10 bytes, Stack size 8 bytes, drv_timer.o(i.app_TIMER0_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = app_TIMER0_IRQn_Handler ⇒ drv_timer_handle_interrupt ⇒ drv_timer_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[cf]">>></a> drv_timer_handle_interrupt
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[44]"></a>app_TIMER1_IRQn_Handler</STRONG> (Thumb, 10 bytes, Stack size 8 bytes, drv_timer.o(i.app_TIMER1_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = app_TIMER1_IRQn_Handler ⇒ drv_timer_handle_interrupt ⇒ drv_timer_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[cf]">>></a> drv_timer_handle_interrupt
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[45]"></a>app_TIMER2_IRQn_Handler</STRONG> (Thumb, 10 bytes, Stack size 8 bytes, drv_timer.o(i.app_TIMER2_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = app_TIMER2_IRQn_Handler ⇒ drv_timer_handle_interrupt ⇒ drv_timer_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[cf]">>></a> drv_timer_handle_interrupt
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[46]"></a>app_TIMER3_IRQn_Handler</STRONG> (Thumb, 10 bytes, Stack size 8 bytes, drv_timer.o(i.app_TIMER3_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = app_TIMER3_IRQn_Handler ⇒ drv_timer_handle_interrupt ⇒ drv_timer_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[cf]">>></a> drv_timer_handle_interrupt
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[48]"></a>app_UART_IRQn_Handler</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, drv_uart.o(i.app_UART_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = app_UART_IRQn_Handler ⇒ UART0_IRQ_Handle ⇒ UART_TransferHandleIRQ ⇒ UART_ResetRxFIFO
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[91]">>></a> UART0_IRQ_Handle
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[41]"></a>app_VIDC_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, drv_vidc.o(i.app_VIDC_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_VIDC_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[3f]"></a>app_VPRE_IRQn_Handler</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, drv_rxbr.o(i.app_VPRE_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_VPRE_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[47]"></a>app_WDG_IRQn_Handler</STRONG> (Thumb, 52 bytes, Stack size 8 bytes, drv_wdg.o(i.app_WDG_IRQn_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_WDG_IRQn_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
<LI><a href="#[d0]">>></a> drv_wdg_set_int
|
|
<LI><a href="#[d1]">>></a> drv_wdg_clear_counter
|
|
<LI><a href="#[d2]">>></a> drv_wdg_read_edge_flag
|
|
<LI><a href="#[d3]">>></a> drv_wdg_clear_edge_flag
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[39]"></a>app_dma_irq_handler</STRONG> (Thumb, 10 bytes, Stack size 8 bytes, drv_dma.o(i.app_dma_irq_handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = app_dma_irq_handler ⇒ drv_dma_irq_handler ⇒ drv_dma_clear_flag ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[d4]">>></a> drv_dma_irq_handler
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[3a]"></a>app_fls_ctrl_Handler</STRONG> (Thumb, 38 bytes, Stack size 8 bytes, norflash.o(i.app_fls_ctrl_Handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = app_fls_ctrl_Handler ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[d5]">>></a> fls_clr_interrupt_flag
|
|
<LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> irq_redirect .o(i.handle_init)
|
|
</UL>
|
|
<P><STRONG><a name="[a6]"></a>app_tp_I2C_init</STRONG> (Thumb, 26 bytes, Stack size 8 bytes, app_tp_transfer.o(i.app_tp_I2C_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 44<LI>Call Chain = app_tp_I2C_init ⇒ hal_i2c_s_init ⇒ drv_i2c_dma_init
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[d7]">>></a> hal_i2c_s_set_transfer
|
|
<LI><a href="#[d8]">>></a> hal_i2c_s_nonblocking_read
|
|
<LI><a href="#[d6]">>></a> hal_i2c_s_init
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[b3]"></a>app_tp_calibration_exec</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, ap_demo.o(i.app_tp_calibration_exec))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 80<LI>Call Chain = app_tp_calibration_exec ⇒ ap_tp_calibration ⇒ app_tp_m_write ⇒ hal_i2c_m_dma_write ⇒ drv_i2c_master_write_dma ⇒ drv_dma_set_transfer ⇒ drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[c0]">>></a> ap_tp_calibration
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[aa]"></a>app_tp_init</STRONG> (Thumb, 56 bytes, Stack size 8 bytes, app_tp_transfer.o(i.app_tp_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 60<LI>Call Chain = app_tp_init ⇒ hal_i2c_m_dma_init ⇒ drv_i2c_master_init ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[de]">>></a> hal_i2c_m_dma_init
|
|
<LI><a href="#[8d]">>></a> hal_gpio_set_pull_state
|
|
<LI><a href="#[dd]">>></a> hal_gpio_init_input
|
|
<LI><a href="#[dc]">>></a> app_tp_screen_init
|
|
<LI><a href="#[81]">>></a> hal_gpio_init_output
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[d9]"></a>app_tp_phone_analysis_data</STRONG> (Thumb, 806 bytes, Stack size 24 bytes, app_tp_for_custom_s8.o(i.app_tp_phone_analysis_data))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = app_tp_phone_analysis_data ⇒ hal_gpio_set_output_data
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[83]">>></a> hal_gpio_set_output_data
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[2d]">>></a> app_tp_i2cs_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[b0]"></a>app_tp_phone_clear_reset_on</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, app_tp_transfer.o(i.app_tp_phone_clear_reset_on))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[da]"></a>app_tp_s_read</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, app_tp_transfer.o(i.app_tp_s_read))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = app_tp_s_read
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[d8]">>></a> hal_i2c_s_nonblocking_read
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[2d]">>></a> app_tp_i2cs_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[db]"></a>app_tp_s_write</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, app_tp_transfer.o(i.app_tp_s_write))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 44<LI>Call Chain = app_tp_s_write ⇒ hal_i2c_s_dma_write ⇒ drv_i2c_slave_write_dma ⇒ drv_dma_prepar_transfer
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[e1]">>></a> hal_i2c_s_dma_write
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[2d]">>></a> app_tp_i2cs_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[c2]"></a>app_tp_screen_analysis_int</STRONG> (Thumb, 670 bytes, Stack size 56 bytes, app_tp_for_custom_s8.o(i.app_tp_screen_analysis_int))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 68<LI>Call Chain = app_tp_screen_analysis_int ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[83]">>></a> hal_gpio_set_output_data
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[c1]">>></a> ap_tp_simulate_finger_release_event
|
|
<LI><a href="#[b4]">>></a> app_tp_transfer_screen_int
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[dc]"></a>app_tp_screen_init</STRONG> (Thumb, 42 bytes, Stack size 8 bytes, app_tp_transfer.o(i.app_tp_screen_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = app_tp_screen_init ⇒ hal_gpio_init_output ⇒ hal_gpio_set_mode
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[83]">>></a> hal_gpio_set_output_data
|
|
<LI><a href="#[81]">>></a> hal_gpio_init_output
|
|
<LI><a href="#[84]">>></a> delayUs
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[aa]">>></a> app_tp_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[e2]"></a>app_tp_screen_reset</STRONG> (Thumb, 150 bytes, Stack size 8 bytes, app_tp_transfer.o(i.app_tp_screen_reset))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 92<LI>Call Chain = app_tp_screen_reset ⇒ ap_tp_simulate_finger_release_event ⇒ app_tp_screen_analysis_int ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[8a]">>></a> hal_i2c_m_transfer_complate
|
|
<LI><a href="#[c1]">>></a> ap_tp_simulate_finger_release_event
|
|
<LI><a href="#[e3]">>></a> ap_tp_scan_point_init
|
|
<LI><a href="#[8c]">>></a> app_tp_m_write
|
|
<LI><a href="#[83]">>></a> hal_gpio_set_output_data
|
|
<LI><a href="#[82]">>></a> delayMs
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[b4]">>></a> app_tp_transfer_screen_int
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[b4]"></a>app_tp_transfer_screen_int</STRONG> (Thumb, 306 bytes, Stack size 24 bytes, app_tp_transfer.o(i.app_tp_transfer_screen_int))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 152<LI>Call Chain = app_tp_transfer_screen_int ⇒ app_tp_transfer_screen_const ⇒ S20_Start_init ⇒ app_tp_m_read ⇒ hal_i2c_m_dma_read ⇒ drv_i2c_master_read_dma ⇒ drv_dma_set_transfer ⇒ drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[8a]">>></a> hal_i2c_m_transfer_complate
|
|
<LI><a href="#[8b]">>></a> hal_gpio_get_input_data
|
|
<LI><a href="#[c2]">>></a> app_tp_screen_analysis_int
|
|
<LI><a href="#[e2]">>></a> app_tp_screen_reset
|
|
<LI><a href="#[e4]">>></a> app_tp_transfer_screen_const
|
|
<LI><a href="#[89]">>></a> app_tp_m_read
|
|
<LI><a href="#[84]">>></a> delayUs
|
|
<LI><a href="#[82]">>></a> delayMs
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[b1]"></a>app_tp_transfer_screen_start</STRONG> (Thumb, 18 bytes, Stack size 16 bytes, app_tp_transfer.o(i.app_tp_transfer_screen_start))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 144<LI>Call Chain = app_tp_transfer_screen_start ⇒ app_tp_transfer_screen_const ⇒ S20_Start_init ⇒ app_tp_m_read ⇒ hal_i2c_m_dma_read ⇒ drv_i2c_master_read_dma ⇒ drv_dma_set_transfer ⇒ drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[e4]">>></a> app_tp_transfer_screen_const
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[e6]"></a>board_Init</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, board.o(i.board_Init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 132<LI>Call Chain = board_Init ⇒ hal_system_init_console ⇒ hal_uart_init ⇒ UART_init ⇒ UART_SetBaudRate ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[ea]">>></a> hal_system_set_phy_calibration
|
|
<LI><a href="#[e9]">>></a> hal_system_init_console
|
|
<LI><a href="#[e7]">>></a> hal_system_init
|
|
<LI><a href="#[e8]">>></a> hal_system_enable_systick
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[26]">>></a> main
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[ee]"></a>ceil</STRONG> (Thumb, 180 bytes, Stack size 24 bytes, ceil.o(i.ceil))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 136<LI>Call Chain = ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[6c]">>></a> __aeabi_dadd
|
|
<LI><a href="#[72]">>></a> __aeabi_drsub
|
|
<LI><a href="#[a0]">>></a> __aeabi_cdrcmple
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
<LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[22b]"></a>dcs_packet_fifo_alloc</STRONG> (Thumb, 80 bytes, Stack size 12 bytes, dcs_packet_fifo.o(i.dcs_packet_fifo_alloc))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = dcs_packet_fifo_alloc
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[229]">>></a> rx_get_dcs_packet_data
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[204]"></a>dcs_packet_fifo_init</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, dcs_packet_fifo.o(i.dcs_packet_fifo_init))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[15f]">>></a> hal_internal_vsync_init_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[158]"></a>dcs_packet_free_fifo_header</STRONG> (Thumb, 60 bytes, Stack size 0 bytes, dcs_packet_fifo.o(i.dcs_packet_free_fifo_header))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[b5]">>></a> hal_dsi_rx_ctrl_dsc_async_handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[157]"></a>dcs_packet_get_fifo_header</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, dcs_packet_fifo.o(i.dcs_packet_get_fifo_header))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[b5]">>></a> hal_dsi_rx_ctrl_dsc_async_handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[82]"></a>delayMs</STRONG> (Thumb, 24 bytes, Stack size 8 bytes, tau_delay.o(i.delayMs))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = delayMs
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[84]">>></a> delayUs
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e2]">>></a> app_tp_screen_reset
|
|
<LI><a href="#[c1]">>></a> ap_tp_simulate_finger_release_event
|
|
<LI><a href="#[88]">>></a> S20_Start_init
|
|
<LI><a href="#[b4]">>></a> app_tp_transfer_screen_int
|
|
<LI><a href="#[c0]">>></a> ap_tp_calibration
|
|
<LI><a href="#[80]">>></a> Gpio_swire_output
|
|
<LI><a href="#[ad]">>></a> init_panel
|
|
<LI><a href="#[5d]">>></a> ap_set_exit_sleep_mode
|
|
<LI><a href="#[5c]">>></a> ap_set_enter_sleep_mode
|
|
<LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[84]"></a>delayUs</STRONG> (Thumb, 34 bytes, Stack size 0 bytes, tau_delay.o(i.delayUs))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
<LI><a href="#[dc]">>></a> app_tp_screen_init
|
|
<LI><a href="#[82]">>></a> delayMs
|
|
<LI><a href="#[b4]">>></a> app_tp_transfer_screen_int
|
|
<LI><a href="#[80]">>></a> Gpio_swire_output
|
|
<LI><a href="#[ad]">>></a> init_panel
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[c4]"></a>drv_ap_rst_trig_edge_detect</STRONG> (Thumb, 46 bytes, Stack size 12 bytes, drv_sys_cfg.o(i.drv_ap_rst_trig_edge_detect))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = drv_ap_rst_trig_edge_detect
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[f3]">>></a> drv_sys_cfg_sel_ap_rst_lvl_trig
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[4b]">>></a> app_AP_NRESET_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[109]"></a>drv_chip_info_get_info</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, drv_chip_info.o(i.drv_chip_info_get_info))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[10a]">>></a> drv_dsi_rx_set_up_phy
|
|
<LI><a href="#[108]">>></a> drv_dsi_rx_set_lane_swap
|
|
<LI><a href="#[10c]">>></a> drv_phy_get_calibration
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[f4]"></a>drv_chip_info_init</STRONG> (Thumb, 56 bytes, Stack size 8 bytes, drv_chip_info.o(i.drv_chip_info_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_chip_info_init ⇒ drv_efuse_read
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[f5]">>></a> drv_efuse_enter_inactive
|
|
<LI><a href="#[f6]">>></a> drv_efuse_read
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[f9]">>></a> drv_common_system_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[f7]"></a>drv_chip_rx_info_check</STRONG> (Thumb, 122 bytes, Stack size 8 bytes, drv_chip_info.o(i.drv_chip_rx_info_check))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = drv_chip_rx_info_check ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[87]">>></a> __2printf
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[15f]">>></a> hal_internal_vsync_init_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[165]"></a>drv_chip_rx_init_done</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_chip_info.o(i.drv_chip_rx_init_done))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[f8]"></a>drv_common_enable_systick</STRONG> (Thumb, 70 bytes, Stack size 16 bytes, drv_common.o(i.drv_common_enable_systick))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = drv_common_enable_systick ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e8]">>></a> hal_system_enable_systick
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[f9]"></a>drv_common_system_init</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, drv_common.o(i.drv_common_system_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = drv_common_system_init ⇒ drv_chip_info_init ⇒ drv_efuse_read
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[f4]">>></a> drv_chip_info_init
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e7]">>></a> hal_system_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[155]"></a>drv_crgu_config_reset_modules</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_config_reset_modules))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
<LI><a href="#[b7]">>></a> hal_dsi_tx_ctrl_deinit
|
|
<LI><a href="#[b9]">>></a> hal_dsi_rx_ctrl_deinit
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[220]"></a>drv_crgu_set_ahb_pre_div</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_ahb_pre_div))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[e7]">>></a> hal_system_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[21f]"></a>drv_crgu_set_ahb_src</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_ahb_src))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[e7]">>></a> hal_system_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[98]"></a>drv_crgu_set_clock</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_clock))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1bc]">>></a> hal_dsi_tx_ctrl_init_clk
|
|
<LI><a href="#[169]">>></a> hal_dsi_rx_ctrl_set_rxbr_clk
|
|
<LI><a href="#[15e]">>></a> hal_dsi_rx_ctrl_init_clk
|
|
<LI><a href="#[e7]">>></a> hal_system_init
|
|
<LI><a href="#[ab]">>></a> hal_timer_init
|
|
<LI><a href="#[b7]">>></a> hal_dsi_tx_ctrl_deinit
|
|
<LI><a href="#[b9]">>></a> hal_dsi_rx_ctrl_deinit
|
|
<LI><a href="#[97]">>></a> UART_SwitchSCLK
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[216]"></a>drv_crgu_set_dpi_mux_src</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_dpi_mux_src))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[214]"></a>drv_crgu_set_dpi_pre_div</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_dpi_pre_div))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[215]"></a>drv_crgu_set_dpi_pre_src</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_dpi_pre_src))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1a6]"></a>drv_crgu_set_dsc_core_div</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_dsc_core_div))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[169]">>></a> hal_dsi_rx_ctrl_set_rxbr_clk
|
|
<LI><a href="#[22c]">>></a> rx_partial_update
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1a4]"></a>drv_crgu_set_dsco_src</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_dsco_src))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[169]">>></a> hal_dsi_rx_ctrl_set_rxbr_clk
|
|
<LI><a href="#[22c]">>></a> rx_partial_update
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1a5]"></a>drv_crgu_set_dsco_src_div</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_dsco_src_div))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[169]">>></a> hal_dsi_rx_ctrl_set_rxbr_clk
|
|
<LI><a href="#[22c]">>></a> rx_partial_update
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[168]"></a>drv_crgu_set_fb_div</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_fb_div))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[15e]">>></a> hal_dsi_rx_ctrl_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[167]"></a>drv_crgu_set_fb_src</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_fb_src))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[15e]">>></a> hal_dsi_rx_ctrl_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[218]"></a>drv_crgu_set_lcdc_div</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_lcdc_div))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[219]"></a>drv_crgu_set_lcdc_src</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_lcdc_src))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[116]"></a>drv_crgu_set_mipi_cfg_src</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_mipi_cfg_src))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[112]">>></a> drv_dsi_tx_phy_test_setup
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[115]"></a>drv_crgu_set_mipi_ref_src</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_mipi_ref_src))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[112]">>></a> drv_dsi_tx_phy_test_setup
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[239]"></a>drv_crgu_set_reset</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_reset))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[234]">>></a> vpre_err_reset
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1a3]"></a>drv_crgu_set_rxbr_div</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_rxbr_div))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[169]">>></a> hal_dsi_rx_ctrl_set_rxbr_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1a2]"></a>drv_crgu_set_rxbr_src</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_rxbr_src))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[169]">>></a> hal_dsi_rx_ctrl_set_rxbr_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[166]"></a>drv_crgu_set_vidc_src</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_crgu.o(i.drv_crgu_set_vidc_src))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[15e]">>></a> hal_dsi_rx_ctrl_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[fa]"></a>drv_dma_clear_flag</STRONG> (Thumb, 24 bytes, Stack size 8 bytes, drv_dma.o(i.drv_dma_clear_flag))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_dma_clear_flag ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[d4]">>></a> drv_dma_irq_handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[133]"></a>drv_dma_create_handle</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, drv_dma.o(i.drv_dma_create_handle))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[132]">>></a> drv_i2c_set_dma_irq_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[fe]"></a>drv_dma_disenable_channel</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_dma.o(i.drv_dma_disenable_channel))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[e1]">>></a> hal_i2c_s_dma_write
|
|
<LI><a href="#[30]">>></a> hal_i2c_slave_irq_callback
|
|
<LI><a href="#[fd]">>></a> drv_dma_set_burst
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[129]"></a>drv_dma_enable_channel</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_dma.o(i.drv_dma_enable_channel))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[30]">>></a> hal_i2c_slave_irq_callback
|
|
<LI><a href="#[12b]">>></a> drv_i2c_master_write_dma
|
|
<LI><a href="#[125]">>></a> drv_i2c_master_read_dma
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[fb]"></a>drv_dma_enable_channel_interrupts</STRONG> (Thumb, 32 bytes, Stack size 8 bytes, drv_dma.o(i.drv_dma_enable_channel_interrupts))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_dma_enable_channel_interrupts
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[9b]">>></a> drv_sys_cfg_set_int
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[d6]">>></a> hal_i2c_s_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[fc]"></a>drv_dma_get_channel_flag</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_dma.o(i.drv_dma_get_channel_flag))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[d4]">>></a> drv_dma_irq_handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[d4]"></a>drv_dma_irq_handler</STRONG> (Thumb, 138 bytes, Stack size 32 bytes, drv_dma.o(i.drv_dma_irq_handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = drv_dma_irq_handler ⇒ drv_dma_clear_flag ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[fc]">>></a> drv_dma_get_channel_flag
|
|
<LI><a href="#[fa]">>></a> drv_dma_clear_flag
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[39]">>></a> app_dma_irq_handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[128]"></a>drv_dma_prepar_transfer</STRONG> (Thumb, 18 bytes, Stack size 12 bytes, drv_dma.o(i.drv_dma_prepar_transfer))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = drv_dma_prepar_transfer
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[135]">>></a> drv_i2c_slave_write_dma
|
|
<LI><a href="#[12b]">>></a> drv_i2c_master_write_dma
|
|
<LI><a href="#[125]">>></a> drv_i2c_master_read_dma
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[fd]"></a>drv_dma_set_burst</STRONG> (Thumb, 26 bytes, Stack size 12 bytes, drv_dma.o(i.drv_dma_set_burst))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[fe]">>></a> drv_dma_disenable_channel
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ff]">>></a> drv_dma_set_transfer
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[134]"></a>drv_dma_set_callback</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, drv_dma.o(i.drv_dma_set_callback))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[132]">>></a> drv_i2c_set_dma_irq_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[ff]"></a>drv_dma_set_transfer</STRONG> (Thumb, 62 bytes, Stack size 12 bytes, drv_dma.o(i.drv_dma_set_transfer))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = drv_dma_set_transfer ⇒ drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[fd]">>></a> drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[12b]">>></a> drv_i2c_master_write_dma
|
|
<LI><a href="#[125]">>></a> drv_i2c_master_read_dma
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[199]"></a>drv_dsc_dec_convert_pps_rc_parameter</STRONG> (Thumb, 54 bytes, Stack size 20 bytes, drv_dsc_dec.o(i.drv_dsc_dec_convert_pps_rc_parameter))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = drv_dsc_dec_convert_pps_rc_parameter
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[198]">>></a> hal_dsi_rx_ctrl_pre_init_pps
|
|
<LI><a href="#[231]">>></a> rx_receive_pps
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[153]"></a>drv_dsc_dec_disable</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_dsc_dec.o(i.drv_dsc_dec_disable))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
<LI><a href="#[b9]">>></a> hal_dsi_rx_ctrl_deinit
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[100]"></a>drv_dsc_dec_enable</STRONG> (Thumb, 88 bytes, Stack size 40 bytes, drv_dsc_dec.o(i.drv_dsc_dec_enable))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = drv_dsc_dec_enable ⇒ __2printf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[f5]">>></a> drv_efuse_enter_inactive
|
|
<LI><a href="#[f6]">>></a> drv_efuse_read
|
|
<LI><a href="#[87]">>></a> __2printf
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
<LI><a href="#[231]">>></a> rx_receive_pps
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[22f]"></a>drv_dsc_dec_get_nslc</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_dsc_dec.o(i.drv_dsc_dec_get_nslc))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[22c]">>></a> rx_partial_update
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[162]"></a>drv_dsc_dec_set_u8_pps</STRONG> (Thumb, 40 bytes, Stack size 8 bytes, drv_dsc_dec.o(i.drv_dsc_dec_set_u8_pps))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_dsc_dec_set_u8_pps
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
<LI><a href="#[234]">>></a> vpre_err_reset
|
|
<LI><a href="#[231]">>></a> rx_receive_pps
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[101]"></a>drv_dsi_rx_calc_ipi_tx_delay</STRONG> (Thumb, 244 bytes, Stack size 56 bytes, drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 160<LI>Call Chain = drv_dsi_rx_calc_ipi_tx_delay ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[6c]">>></a> __aeabi_dadd
|
|
<LI><a href="#[7a]">>></a> __aeabi_d2uiz
|
|
<LI><a href="#[76]">>></a> __aeabi_ui2f
|
|
<LI><a href="#[69]">>></a> __aeabi_fsub
|
|
<LI><a href="#[102]">>></a> __aeabi_fmul
|
|
<LI><a href="#[6b]">>></a> __aeabi_fdiv
|
|
<LI><a href="#[66]">>></a> __aeabi_fadd
|
|
<LI><a href="#[106]">>></a> __aeabi_f2d
|
|
<LI><a href="#[105]">>></a> __aeabi_cfrcmple
|
|
<LI><a href="#[104]">>></a> drv_dsi_rx_get_color_pcc
|
|
<LI><a href="#[103]">>></a> drv_dsi_rx_get_color_bpp
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[16d]">>></a> hal_dsi_rx_ctrl_set_ipi_cfg
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[107]"></a>drv_dsi_rx_enable_irq</STRONG> (Thumb, 58 bytes, Stack size 8 bytes, drv_dsi_rx.o(i.drv_dsi_rx_enable_irq))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_dsi_rx_enable_irq ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[9b]">>></a> drv_sys_cfg_set_int
|
|
<LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[160]">>></a> hal_dsi_rx_ctrl_init_dsi_rx
|
|
<LI><a href="#[b9]">>></a> hal_dsi_rx_ctrl_deinit
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[232]"></a>drv_dsi_rx_get_compression_en</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[231]">>></a> rx_receive_pps
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[15c]"></a>drv_dsi_rx_get_max_ret_size</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_max_ret_size))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[a3]">>></a> hal_dsi_rx_ctrl_get_max_ret_size
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1aa]"></a>drv_dsi_rx_power_up</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_power_up))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1a8]">>></a> hal_dsi_rx_ctrl_start
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[16b]"></a>drv_dsi_rx_set_ctrl_cfg</STRONG> (Thumb, 32 bytes, Stack size 12 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_ctrl_cfg))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = drv_dsi_rx_set_ctrl_cfg
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[160]">>></a> hal_dsi_rx_ctrl_init_dsi_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[16c]"></a>drv_dsi_rx_set_ddi_cfg</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[160]">>></a> hal_dsi_rx_ctrl_init_dsi_rx
|
|
<LI><a href="#[19b]">>></a> hal_dsi_rx_ctrl_set_cus_esc_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[16e]"></a>drv_dsi_rx_set_inten</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_inten))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[160]">>></a> hal_dsi_rx_ctrl_init_dsi_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1a1]"></a>drv_dsi_rx_set_ipi_cfg</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_cfg))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_dsi_rx_set_ipi_cfg
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[16d]">>></a> hal_dsi_rx_ctrl_set_ipi_cfg
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[108]"></a>drv_dsi_rx_set_lane_swap</STRONG> (Thumb, 70 bytes, Stack size 16 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_lane_swap))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_dsi_rx_set_lane_swap
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[109]">>></a> drv_chip_info_get_info
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[160]">>></a> hal_dsi_rx_ctrl_init_dsi_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[16f]"></a>drv_dsi_rx_set_resp_cnt</STRONG> (Thumb, 38 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_resp_cnt))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[160]">>></a> hal_dsi_rx_ctrl_init_dsi_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[10a]"></a>drv_dsi_rx_set_up_phy</STRONG> (Thumb, 236 bytes, Stack size 32 bytes, drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = drv_dsi_rx_set_up_phy ⇒ drv_rx_phy_test_write_2_byte ⇒ drv_phy_test_write_2_byte ⇒ drv_phy_test_write_data
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[10b]">>></a> drv_phy_get_rate_para
|
|
<LI><a href="#[10c]">>></a> drv_phy_get_calibration
|
|
<LI><a href="#[109]">>></a> drv_chip_info_get_info
|
|
<LI><a href="#[10f]">>></a> drv_rx_phy_test_write_2_byte
|
|
<LI><a href="#[10e]">>></a> drv_rx_phy_test_write_1_byte
|
|
<LI><a href="#[110]">>></a> drv_rx_phy_test_lock
|
|
<LI><a href="#[10d]">>></a> drv_rx_phy_test_clear
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[160]">>></a> hal_dsi_rx_ctrl_init_dsi_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1ab]"></a>drv_dsi_rx_shut_down</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_shut_down))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[b8]">>></a> hal_dsi_rx_ctrl_stop
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1ea]"></a>drv_dsi_tx_command_header</STRONG> (Thumb, 20 bytes, Stack size 8 bytes, drv_dsi_tx.o(i.drv_dsi_tx_command_header))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_dsi_tx_command_header
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1d7]">>></a> hal_dsi_tx_send_cmd
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1b8]"></a>drv_dsi_tx_command_mode_cfg</STRONG> (Thumb, 108 bytes, Stack size 16 bytes, drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_dsi_tx_command_mode_cfg
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1ba]">>></a> hal_dsi_tx_ctrl_exit_init_panel_mode
|
|
<LI><a href="#[1b7]">>></a> hal_dsi_tx_ctrl_enter_init_panel_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1d8]"></a>drv_dsi_tx_command_put_payload</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[af]">>></a> hal_dsi_tx_ctrl_write_cmd
|
|
<LI><a href="#[1d5]">>></a> hal_dsi_tx_ctrl_write_array_cmd
|
|
<LI><a href="#[229]">>></a> rx_get_dcs_packet_data
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1ce]"></a>drv_dsi_tx_config_eotp</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_config_eotp))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[ae]">>></a> hal_dsi_tx_ctrl_start
|
|
<LI><a href="#[1c3]">>></a> hal_dsi_tx_init_remains
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1de]"></a>drv_dsi_tx_config_int</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_config_int))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1c4]">>></a> hal_dsi_tx_init_interrupt
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1dd]"></a>drv_dsi_tx_dpi_lpcmd_time</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_dpi_lpcmd_time))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1c1]">>></a> hal_dsi_tx_init_dpi_cfg
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1db]"></a>drv_dsi_tx_dpi_mode</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_dpi_mode))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1c1]">>></a> hal_dsi_tx_init_dpi_cfg
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1dc]"></a>drv_dsi_tx_dpi_polarity</STRONG> (Thumb, 36 bytes, Stack size 16 bytes, drv_dsi_tx.o(i.drv_dsi_tx_dpi_polarity))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_dsi_tx_dpi_polarity
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1c1]">>></a> hal_dsi_tx_init_dpi_cfg
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1d9]"></a>drv_dsi_tx_edpi_cmd_size</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_edpi_cmd_size))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1c2]">>></a> hal_dsi_tx_init_data_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1d6]"></a>drv_dsi_tx_get_cmd_status</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[af]">>></a> hal_dsi_tx_ctrl_write_cmd
|
|
<LI><a href="#[1d5]">>></a> hal_dsi_tx_ctrl_write_array_cmd
|
|
<LI><a href="#[1d7]">>></a> hal_dsi_tx_send_cmd
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1b9]"></a>drv_dsi_tx_mode</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_mode))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ba]">>></a> hal_dsi_tx_ctrl_exit_init_panel_mode
|
|
<LI><a href="#[1b7]">>></a> hal_dsi_tx_ctrl_enter_init_panel_mode
|
|
<LI><a href="#[1c2]">>></a> hal_dsi_tx_init_data_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1e5]"></a>drv_dsi_tx_phy_clock_lane_auto_lp</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1c3]">>></a> hal_dsi_tx_init_remains
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1cf]"></a>drv_dsi_tx_phy_clock_lane_req_hs</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[ae]">>></a> hal_dsi_tx_ctrl_start
|
|
<LI><a href="#[1c3]">>></a> hal_dsi_tx_init_remains
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1df]"></a>drv_dsi_tx_phy_lane_mode</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_lane_mode))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1be]">>></a> hal_dsi_tx_init_phy_cfg
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1c5]"></a>drv_dsi_tx_phy_status_ready</STRONG> (Thumb, 100 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[111]"></a>drv_dsi_tx_phy_status_stopstate</STRONG> (Thumb, 62 bytes, Stack size 4 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[cc]">>></a> __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1d7]">>></a> hal_dsi_tx_send_cmd
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[112]"></a>drv_dsi_tx_phy_test_setup</STRONG> (Thumb, 268 bytes, Stack size 40 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 80<LI>Call Chain = drv_dsi_tx_phy_test_setup ⇒ drv_tx_phy_test_write_2_byte ⇒ drv_phy_test_write_2_byte ⇒ drv_phy_test_write_data
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[10b]">>></a> drv_phy_get_rate_para
|
|
<LI><a href="#[10c]">>></a> drv_phy_get_calibration
|
|
<LI><a href="#[115]">>></a> drv_crgu_set_mipi_ref_src
|
|
<LI><a href="#[116]">>></a> drv_crgu_set_mipi_cfg_src
|
|
<LI><a href="#[113]">>></a> drv_phy_get_pll_para
|
|
<LI><a href="#[11b]">>></a> drv_tx_phy_test_exit
|
|
<LI><a href="#[114]">>></a> drv_tx_phy_test_enter
|
|
<LI><a href="#[11a]">>></a> drv_tx_phy_test_write_code
|
|
<LI><a href="#[119]">>></a> drv_tx_phy_test_write_2_byte
|
|
<LI><a href="#[118]">>></a> drv_tx_phy_test_write_1_byte
|
|
<LI><a href="#[117]">>></a> drv_tx_phy_test_clear
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1e0]"></a>drv_dsi_tx_phy_time_cfg</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_dsi_tx_phy_time_cfg
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1be]">>></a> hal_dsi_tx_init_phy_cfg
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1c6]"></a>drv_dsi_tx_powerup</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_powerup))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1e1]"></a>drv_dsi_tx_response_mode</STRONG> (Thumb, 28 bytes, Stack size 16 bytes, drv_dsi_tx.o(i.drv_dsi_tx_response_mode))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_dsi_tx_response_mode
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1c3]">>></a> hal_dsi_tx_init_remains
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1e7]"></a>drv_dsi_tx_set_bta_ack</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_bta_ack))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1da]">>></a> hal_dsi_tx_init_video_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1e2]"></a>drv_dsi_tx_set_esc_div</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1c3]">>></a> hal_dsi_tx_init_remains
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[11c]"></a>drv_dsi_tx_set_int</STRONG> (Thumb, 46 bytes, Stack size 8 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_int))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_dsi_tx_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[9b]">>></a> drv_sys_cfg_set_int
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[b6]">>></a> hal_dsi_tx_ctrl_stop
|
|
<LI><a href="#[1c4]">>></a> hal_dsi_tx_init_interrupt
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1e3]"></a>drv_dsi_tx_set_time_out_div</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_time_out_div))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1c3]">>></a> hal_dsi_tx_init_remains
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1b0]"></a>drv_dsi_tx_set_video_chunk</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_video_chunk))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1b1]"></a>drv_dsi_tx_set_video_timing</STRONG> (Thumb, 34 bytes, Stack size 16 bytes, drv_dsi_tx.o(i.drv_dsi_tx_set_video_timing))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_dsi_tx_set_video_timing
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1d4]"></a>drv_dsi_tx_shutdown</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_shutdown))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
<LI><a href="#[b6]">>></a> hal_dsi_tx_ctrl_stop
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1e4]"></a>drv_dsi_tx_timeout_cfg</STRONG> (Thumb, 38 bytes, Stack size 16 bytes, drv_dsi_tx.o(i.drv_dsi_tx_timeout_cfg))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_dsi_tx_timeout_cfg
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1c3]">>></a> hal_dsi_tx_init_remains
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1e6]"></a>drv_dsi_tx_video_mode_cfg</STRONG> (Thumb, 170 bytes, Stack size 20 bytes, drv_dsi_tx.o(i.drv_dsi_tx_video_mode_cfg))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = drv_dsi_tx_video_mode_cfg
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1da]">>></a> hal_dsi_tx_init_video_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1e9]"></a>drv_dsi_tx_video_mode_disable_hact_cmd</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_video_mode_disable_hact_cmd))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1da]">>></a> hal_dsi_tx_init_video_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1e8]"></a>drv_dsi_tx_video_mode_set_lp_cmd</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_dsi_tx_video_mode_set_lp_cmd))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1da]">>></a> hal_dsi_tx_init_video_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[f5]"></a>drv_efuse_enter_inactive</STRONG> (Thumb, 32 bytes, Stack size 4 bytes, drv_efuse.o(i.drv_efuse_enter_inactive))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = drv_efuse_enter_inactive
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[11d]">>></a> drv_efuse_int_enable
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[100]">>></a> drv_dsc_dec_enable
|
|
<LI><a href="#[f4]">>></a> drv_chip_info_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[11d]"></a>drv_efuse_int_enable</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_efuse.o(i.drv_efuse_int_enable))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[f5]">>></a> drv_efuse_enter_inactive
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[f6]"></a>drv_efuse_read</STRONG> (Thumb, 50 bytes, Stack size 8 bytes, drv_efuse.o(i.drv_efuse_read))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_efuse_read
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[11e]">>></a> drv_efuse_read_req
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[100]">>></a> drv_dsc_dec_enable
|
|
<LI><a href="#[10c]">>></a> drv_phy_get_calibration
|
|
<LI><a href="#[f4]">>></a> drv_chip_info_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[11e]"></a>drv_efuse_read_req</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, drv_efuse.o(i.drv_efuse_read_req))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[f6]">>></a> drv_efuse_read
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1eb]"></a>drv_gpio_get_input_data</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_get_input_data))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[8b]">>></a> hal_gpio_get_input_data
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1f2]"></a>drv_gpio_register_ap_reset_callback</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_register_ap_reset_callback))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[b2]">>></a> hal_gpio_set_ap_reset_int
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1f1]"></a>drv_gpio_register_callback</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_register_callback))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[90]">>></a> hal_gpio_reg_eint_cb
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[11f]"></a>drv_gpio_set_int</STRONG> (Thumb, 62 bytes, Stack size 16 bytes, drv_gpio.o(i.drv_gpio_set_int))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_gpio_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[9b]">>></a> drv_sys_cfg_set_int
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[8e]">>></a> hal_gpio_ctrl_eint
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1ec]"></a>drv_gpio_set_ioe</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_set_ioe))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[dd]">>></a> hal_gpio_init_input
|
|
<LI><a href="#[8f]">>></a> hal_gpio_init_eint
|
|
<LI><a href="#[81]">>></a> hal_gpio_init_output
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1f6]"></a>drv_gpio_set_mode0</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_set_mode0))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ed]">>></a> hal_gpio_set_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1f5]"></a>drv_gpio_set_mode1</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_set_mode1))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ed]">>></a> hal_gpio_set_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1f4]"></a>drv_gpio_set_mode2</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_set_mode2))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ed]">>></a> hal_gpio_set_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1f3]"></a>drv_gpio_set_mode3</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_gpio.o(i.drv_gpio_set_mode3))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ed]">>></a> hal_gpio_set_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[120]"></a>drv_gpio_set_pull_state</STRONG> (Thumb, 298 bytes, Stack size 16 bytes, drv_gpio.o(i.drv_gpio_set_pull_state))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = drv_gpio_set_pull_state ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[cc]">>></a> __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[8d]">>></a> hal_gpio_set_pull_state
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1f8]"></a>drv_i2c_dma_init</STRONG> (Thumb, 146 bytes, Stack size 20 bytes, drv_i2c_dma.o(i.drv_i2c_dma_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = drv_i2c_dma_init
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[d6]">>></a> hal_i2c_s_init
|
|
<LI><a href="#[de]">>></a> hal_i2c_m_dma_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1f9]"></a>drv_i2c_enable_rx_dma</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, drv_i2c_dma.o(i.drv_i2c_enable_rx_dma))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[de]">>></a> hal_i2c_m_dma_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1fa]"></a>drv_i2c_enable_tx_dma</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, drv_i2c_dma.o(i.drv_i2c_enable_tx_dma))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[d6]">>></a> hal_i2c_s_init
|
|
<LI><a href="#[de]">>></a> hal_i2c_m_dma_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[121]"></a>drv_i2c_m_clear_it_pending_bit</STRONG> (Thumb, 86 bytes, Stack size 8 bytes, drv_i2c_master.o(i.drv_i2c_m_clear_it_pending_bit))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_i2c_m_clear_it_pending_bit ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[cc]">>></a> __ARM_common_switch8
|
|
<LI><a href="#[122]">>></a> __NVIC_ClearPendingIRQ
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[2f]">>></a> hal_i2c_master_irq_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[126]"></a>drv_i2c_m_enable</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_i2c_master.o(i.drv_i2c_m_enable))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[125]">>></a> drv_i2c_master_read_dma
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[123]"></a>drv_i2c_m_enable_intr</STRONG> (Thumb, 42 bytes, Stack size 16 bytes, drv_i2c_master.o(i.drv_i2c_m_enable_intr))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_i2c_m_enable_intr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[122]">>></a> __NVIC_ClearPendingIRQ
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[de]">>></a> hal_i2c_m_dma_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1f7]"></a>drv_i2c_m_set_callback</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, drv_i2c_master.o(i.drv_i2c_m_set_callback))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[de]">>></a> hal_i2c_m_dma_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[124]"></a>drv_i2c_master_init</STRONG> (Thumb, 118 bytes, Stack size 24 bytes, drv_i2c_master.o(i.drv_i2c_master_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = drv_i2c_master_init ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[de]">>></a> hal_i2c_m_dma_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[125]"></a>drv_i2c_master_read_dma</STRONG> (Thumb, 82 bytes, Stack size 40 bytes, drv_i2c_dma.o(i.drv_i2c_master_read_dma))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = drv_i2c_master_read_dma ⇒ drv_dma_set_transfer ⇒ drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[127]">>></a> drv_sys_cfg_set_dma_rx_req
|
|
<LI><a href="#[129]">>></a> drv_dma_enable_channel
|
|
<LI><a href="#[126]">>></a> drv_i2c_m_enable
|
|
<LI><a href="#[12a]">>></a> drv_i2c_master_write_read_cmd
|
|
<LI><a href="#[ff]">>></a> drv_dma_set_transfer
|
|
<LI><a href="#[128]">>></a> drv_dma_prepar_transfer
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[df]">>></a> hal_i2c_m_dma_read
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[12b]"></a>drv_i2c_master_write_dma</STRONG> (Thumb, 50 bytes, Stack size 24 bytes, drv_i2c_dma.o(i.drv_i2c_master_write_dma))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = drv_i2c_master_write_dma ⇒ drv_dma_set_transfer ⇒ drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[12c]">>></a> drv_sys_cfg_set_dma_tx_req
|
|
<LI><a href="#[129]">>></a> drv_dma_enable_channel
|
|
<LI><a href="#[ff]">>></a> drv_dma_set_transfer
|
|
<LI><a href="#[128]">>></a> drv_dma_prepar_transfer
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e0]">>></a> hal_i2c_m_dma_write
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[12d]"></a>drv_i2c_s_clear_it_pending_bit</STRONG> (Thumb, 84 bytes, Stack size 8 bytes, drv_i2c_slave.o(i.drv_i2c_s_clear_it_pending_bit))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_i2c_s_clear_it_pending_bit ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[cc]">>></a> __ARM_common_switch8
|
|
<LI><a href="#[12e]">>></a> __NVIC_ClearPendingIRQ
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[30]">>></a> hal_i2c_slave_irq_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[12f]"></a>drv_i2c_s_enable_intr</STRONG> (Thumb, 40 bytes, Stack size 16 bytes, drv_i2c_slave.o(i.drv_i2c_s_enable_intr))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_i2c_s_enable_intr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[12e]">>></a> __NVIC_ClearPendingIRQ
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[d6]">>></a> hal_i2c_s_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[131]"></a>drv_i2c_s_get_fifo_status</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, drv_i2c_slave.o(i.drv_i2c_s_get_fifo_status))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[130]">>></a> drv_i2c_s_write_data
|
|
<LI><a href="#[30]">>></a> hal_i2c_slave_irq_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1fc]"></a>drv_i2c_s_set_callback</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, drv_i2c_slave.o(i.drv_i2c_s_set_callback))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[d6]">>></a> hal_i2c_s_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[130]"></a>drv_i2c_s_write_data</STRONG> (Thumb, 26 bytes, Stack size 4 bytes, drv_i2c_slave.o(i.drv_i2c_s_write_data))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = drv_i2c_s_write_data
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[131]">>></a> drv_i2c_s_get_fifo_status
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[30]">>></a> hal_i2c_slave_irq_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[132]"></a>drv_i2c_set_dma_irq_callback</STRONG> (Thumb, 68 bytes, Stack size 8 bytes, drv_i2c_dma.o(i.drv_i2c_set_dma_irq_callback))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_i2c_set_dma_irq_callback
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[133]">>></a> drv_dma_create_handle
|
|
<LI><a href="#[134]">>></a> drv_dma_set_callback
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[d6]">>></a> hal_i2c_s_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1fb]"></a>drv_i2c_slave_init</STRONG> (Thumb, 60 bytes, Stack size 8 bytes, drv_i2c_slave.o(i.drv_i2c_slave_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_i2c_slave_init
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[d6]">>></a> hal_i2c_s_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[135]"></a>drv_i2c_slave_write_dma</STRONG> (Thumb, 18 bytes, Stack size 8 bytes, drv_i2c_dma.o(i.drv_i2c_slave_write_dma))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = drv_i2c_slave_write_dma ⇒ drv_dma_prepar_transfer
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[128]">>></a> drv_dma_prepar_transfer
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e1]">>></a> hal_i2c_s_dma_write
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[207]"></a>drv_lcdc_config_bypass</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_bypass))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1c0]">>></a> hal_lcdc_init_cfg
|
|
<LI><a href="#[20f]">>></a> hal_lcdc_config_upscaler
|
|
<LI><a href="#[20e]">>></a> hal_lcdc_config_rgb_to_pentile
|
|
<LI><a href="#[206]">>></a> hal_lcdc_config_ccm
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[c7]"></a>drv_lcdc_config_ccm</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_ccm))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[206]">>></a> hal_lcdc_config_ccm
|
|
<LI><a href="#[36]">>></a> app_LCDC_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[209]"></a>drv_lcdc_config_disp_mode</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_disp_mode))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[208]">>></a> hal_lcdc_config_remains
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[20d]"></a>drv_lcdc_config_dpi_polarity</STRONG> (Thumb, 36 bytes, Stack size 16 bytes, drv_lcdc.o(i.drv_lcdc_config_dpi_polarity))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_lcdc_config_dpi_polarity
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[208]">>></a> hal_lcdc_config_remains
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[217]"></a>drv_lcdc_config_dpi_timing</STRONG> (Thumb, 38 bytes, Stack size 16 bytes, drv_lcdc.o(i.drv_lcdc_config_dpi_timing))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_lcdc_config_dpi_timing
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[20a]"></a>drv_lcdc_config_edpi_mode</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_edpi_mode))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[208]">>></a> hal_lcdc_config_remains
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[20b]"></a>drv_lcdc_config_endianness</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_endianness))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[208]">>></a> hal_lcdc_config_remains
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[137]"></a>drv_lcdc_config_input_size</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_input_size))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[136]">>></a> drv_lcdc_config_src_parameter
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[21c]"></a>drv_lcdc_config_int</STRONG> (Thumb, 30 bytes, Stack size 12 bytes, drv_lcdc.o(i.drv_lcdc_config_int))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = drv_lcdc_config_int
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[213]">>></a> hal_lcdc_init_interrupt
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[c8]"></a>drv_lcdc_config_int_single</STRONG> (Thumb, 34 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_config_int_single))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_lcdc_config_int_single
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[bc]">>></a> hal_dsi_tx_ctrl_set_ccm
|
|
<LI><a href="#[36]">>></a> app_LCDC_IRQn_Handler
|
|
<LI><a href="#[205]">>></a> vsync_set_te_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1d2]"></a>drv_lcdc_config_overwrite</STRONG> (Thumb, 34 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_overwrite))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[ae]">>></a> hal_dsi_tx_ctrl_start
|
|
<LI><a href="#[1b6]">>></a> hal_internal_vsync_set_tx_state
|
|
<LI><a href="#[34]">>></a> vidc_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1c9]"></a>drv_lcdc_config_overwrite_rgb</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_overwrite_rgb))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1c8]">>></a> hal_dsi_tx_ctrl_set_overwrite_rgb
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1cd]"></a>drv_lcdc_config_partial_display_area</STRONG> (Thumb, 26 bytes, Stack size 16 bytes, drv_lcdc.o(i.drv_lcdc_config_partial_display_area))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_lcdc_config_partial_display_area
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1cc]">>></a> hal_dsi_tx_ctrl_set_partial_disp_area
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1cb]"></a>drv_lcdc_config_partial_display_enable</STRONG> (Thumb, 34 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_partial_display_enable))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ca]">>></a> hal_dsi_tx_ctrl_set_partial_disp
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[212]"></a>drv_lcdc_config_scale_up_coef</STRONG> (Thumb, 26 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_config_scale_up_coef))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_lcdc_config_scale_up_coef
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[20f]">>></a> hal_lcdc_config_upscaler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[210]"></a>drv_lcdc_config_scale_up_step</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_scale_up_step))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[20f]">>></a> hal_lcdc_config_upscaler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[136]"></a>drv_lcdc_config_src_parameter</STRONG> (Thumb, 76 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_config_src_parameter))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_lcdc_config_src_parameter
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[137]">>></a> drv_lcdc_config_input_size
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[208]">>></a> hal_lcdc_config_remains
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[20c]"></a>drv_lcdc_config_thresh</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_config_thresh))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[208]">>></a> hal_lcdc_config_remains
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[21b]"></a>drv_lcdc_ctrl_flow</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_ctrl_flow))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[213]">>></a> hal_lcdc_init_interrupt
|
|
<LI><a href="#[205]">>></a> vsync_set_te_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1d0]"></a>drv_lcdc_enable_shadow_reg</STRONG> (Thumb, 32 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_enable_shadow_reg))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[ae]">>></a> hal_dsi_tx_ctrl_start
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[138]"></a>drv_lcdc_set_int</STRONG> (Thumb, 46 bytes, Stack size 8 bytes, drv_lcdc.o(i.drv_lcdc_set_int))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_lcdc_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[9b]">>></a> drv_sys_cfg_set_int
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[b6]">>></a> hal_dsi_tx_ctrl_stop
|
|
<LI><a href="#[213]">>></a> hal_lcdc_init_interrupt
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1d1]"></a>drv_lcdc_set_video_hw_mode</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_set_video_hw_mode))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[ae]">>></a> hal_dsi_tx_ctrl_start
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1d3]"></a>drv_lcdc_start</STRONG> (Thumb, 32 bytes, Stack size 0 bytes, drv_lcdc.o(i.drv_lcdc_start))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[b6]">>></a> hal_dsi_tx_ctrl_stop
|
|
<LI><a href="#[ae]">>></a> hal_dsi_tx_ctrl_start
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[ca]"></a>drv_memc_clear_status</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_clear_status))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[42]">>></a> app_MEMC_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[139]"></a>drv_memc_enable_irq</STRONG> (Thumb, 58 bytes, Stack size 8 bytes, drv_memc.o(i.drv_memc_enable_irq))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_memc_enable_irq ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[9b]">>></a> drv_sys_cfg_set_int
|
|
<LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
<LI><a href="#[b9]">>></a> hal_dsi_rx_ctrl_deinit
|
|
<LI><a href="#[1fd]">>></a> hal_internal_init_memc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[15b]"></a>drv_memc_gen_a_tear_signal</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_gen_a_tear_signal))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[15a]">>></a> hal_dsi_rx_ctrl_gen_a_tear_signal
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[c9]"></a>drv_memc_get_status</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_get_status))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[42]">>></a> app_MEMC_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[173]"></a>drv_memc_rate_transfer_sel</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_rate_transfer_sel))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[176]"></a>drv_memc_sel_vsync</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_sel_vsync))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[17b]"></a>drv_memc_set_active_height</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_active_height))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
<LI><a href="#[1fd]">>></a> hal_internal_init_memc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[170]"></a>drv_memc_set_data_mode</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_data_mode))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
<LI><a href="#[1fd]">>></a> hal_internal_init_memc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[17a]"></a>drv_memc_set_double_buffer</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_double_buffer))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
<LI><a href="#[1fd]">>></a> hal_internal_init_memc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[235]"></a>drv_memc_set_double_buffer_reverse</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_double_buffer_reverse))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[33]">>></a> rxbr_irq1_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[174]"></a>drv_memc_set_fs_en_conditions</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_fs_en_conditions))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[17c]"></a>drv_memc_set_inten</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_inten))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
<LI><a href="#[1fd]">>></a> hal_internal_init_memc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[175]"></a>drv_memc_set_lcdc_st_conditions</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_lcdc_st_conditions))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[172]"></a>drv_memc_set_ltpo_mode</STRONG> (Thumb, 26 bytes, Stack size 8 bytes, drv_memc.o(i.drv_memc_set_ltpo_mode))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_memc_set_ltpo_mode
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
<LI><a href="#[1fd]">>></a> hal_internal_init_memc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[179]"></a>drv_memc_set_tear_mode</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_tear_mode))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
<LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
<LI><a href="#[be]">>></a> hal_dsi_rx_ctrl_set_sw_tear_mode
|
|
<LI><a href="#[1fd]">>></a> hal_internal_init_memc
|
|
<LI><a href="#[205]">>></a> vsync_set_te_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[178]"></a>drv_memc_set_tear_waveform</STRONG> (Thumb, 34 bytes, Stack size 8 bytes, drv_memc.o(i.drv_memc_set_tear_waveform))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_memc_set_tear_waveform
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
<LI><a href="#[1fd]">>></a> hal_internal_init_memc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[177]"></a>drv_memc_set_vidc_sync_cnt</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, drv_memc.o(i.drv_memc_set_vidc_sync_cnt))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[c6]"></a>drv_param_init_get_ccm</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, drv_param_init.o(i.drv_param_init_get_ccm))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[206]">>></a> hal_lcdc_config_ccm
|
|
<LI><a href="#[36]">>></a> app_LCDC_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[18b]"></a>drv_param_init_get_scld_filter_h</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_param_init.o(i.drv_param_init_get_scld_filter_h))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[18c]"></a>drv_param_init_get_scld_filter_v</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_param_init.o(i.drv_param_init_get_scld_filter_v))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[211]"></a>drv_param_init_get_sclu_filter</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, drv_param_init.o(i.drv_param_init_get_sclu_filter))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[20f]">>></a> hal_lcdc_config_upscaler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[13a]"></a>drv_param_init_set_ccm</STRONG> (Thumb, 14 bytes, Stack size 8 bytes, drv_param_init.o(i.drv_param_init_set_ccm))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_param_init_set_ccm
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[bb]">>></a> __aeabi_memcpy4
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[bc]">>></a> hal_dsi_tx_ctrl_set_ccm
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[19d]"></a>drv_param_init_set_scld_filter</STRONG> (Thumb, 92 bytes, Stack size 20 bytes, drv_param_init.o(i.drv_param_init_set_scld_filter))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = drv_param_init_set_scld_filter
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[19c]">>></a> hal_dsi_rx_ctrl_set_cus_scld_filter
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[193]"></a>drv_param_p2r_filter_init</STRONG> (Thumb, 30 bytes, Stack size 16 bytes, drv_param_init.o(i.drv_param_p2r_filter_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_param_p2r_filter_init
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[225]"></a>drv_phy_enable_calibration</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_phy_common.o(i.drv_phy_enable_calibration))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[ea]">>></a> hal_system_set_phy_calibration
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[10c]"></a>drv_phy_get_calibration</STRONG> (Thumb, 50 bytes, Stack size 16 bytes, drv_phy_common.o(i.drv_phy_get_calibration))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = drv_phy_get_calibration ⇒ drv_efuse_read
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[109]">>></a> drv_chip_info_get_info
|
|
<LI><a href="#[f6]">>></a> drv_efuse_read
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[10a]">>></a> drv_dsi_rx_set_up_phy
|
|
<LI><a href="#[112]">>></a> drv_dsi_tx_phy_test_setup
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[113]"></a>drv_phy_get_pll_para</STRONG> (Thumb, 88 bytes, Stack size 0 bytes, drv_phy_common.o(i.drv_phy_get_pll_para))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[112]">>></a> drv_dsi_tx_phy_test_setup
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[10b]"></a>drv_phy_get_rate_para</STRONG> (Thumb, 76 bytes, Stack size 8 bytes, drv_phy_common.o(i.drv_phy_get_rate_para))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = drv_phy_get_rate_para ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[10a]">>></a> drv_dsi_rx_set_up_phy
|
|
<LI><a href="#[112]">>></a> drv_dsi_tx_phy_test_setup
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[13f]"></a>drv_phy_test_clear</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_phy_common.o(i.drv_phy_test_clear))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[10d]">>></a> drv_rx_phy_test_clear
|
|
<LI><a href="#[117]">>></a> drv_tx_phy_test_clear
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[140]"></a>drv_phy_test_lock</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, drv_phy_common.o(i.drv_phy_test_lock))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[110]">>></a> drv_rx_phy_test_lock
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[13b]"></a>drv_phy_test_write_1_byte</STRONG> (Thumb, 32 bytes, Stack size 16 bytes, drv_phy_common.o(i.drv_phy_test_write_1_byte))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = drv_phy_test_write_1_byte ⇒ drv_phy_test_write_data
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[13d]">>></a> drv_phy_test_write_data
|
|
<LI><a href="#[13c]">>></a> drv_phy_test_write_code
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[10e]">>></a> drv_rx_phy_test_write_1_byte
|
|
<LI><a href="#[118]">>></a> drv_tx_phy_test_write_1_byte
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[13e]"></a>drv_phy_test_write_2_byte</STRONG> (Thumb, 38 bytes, Stack size 16 bytes, drv_phy_common.o(i.drv_phy_test_write_2_byte))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = drv_phy_test_write_2_byte ⇒ drv_phy_test_write_data
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[13d]">>></a> drv_phy_test_write_data
|
|
<LI><a href="#[13c]">>></a> drv_phy_test_write_code
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[10f]">>></a> drv_rx_phy_test_write_2_byte
|
|
<LI><a href="#[119]">>></a> drv_tx_phy_test_write_2_byte
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[13c]"></a>drv_phy_test_write_code</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, drv_phy_common.o(i.drv_phy_test_write_code))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_phy_test_write_code
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[13e]">>></a> drv_phy_test_write_2_byte
|
|
<LI><a href="#[13b]">>></a> drv_phy_test_write_1_byte
|
|
<LI><a href="#[11a]">>></a> drv_tx_phy_test_write_code
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[226]"></a>drv_pwr_set_cp_mode</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, drv_pwr.o(i.drv_pwr_set_cp_mode))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[ba]">>></a> hal_system_set_vcc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[223]"></a>drv_pwr_set_pvd_mode</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_pwr.o(i.drv_pwr_set_pvd_mode))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[e7]">>></a> hal_system_init
|
|
<LI><a href="#[bd]">>></a> hal_system_set_pvd
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[21e]"></a>drv_pwr_set_system_clk_src</STRONG> (Thumb, 36 bytes, Stack size 0 bytes, drv_pwr.o(i.drv_pwr_set_system_clk_src))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[e7]">>></a> hal_system_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[f1]"></a>drv_rxbr_clear_pkt_buffer</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[33]">>></a> rxbr_irq1_callback
|
|
<LI><a href="#[231]">>></a> rx_receive_pps
|
|
<LI><a href="#[230]">>></a> rx_receive_packet
|
|
<LI><a href="#[ef]">>></a> check_pkt_buf_rev
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[f2]"></a>drv_rxbr_clear_status0</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_clear_status0))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
<LI><a href="#[33]">>></a> rxbr_irq1_callback
|
|
<LI><a href="#[32]">>></a> rxbr_irq0_callback
|
|
<LI><a href="#[230]">>></a> rx_receive_packet
|
|
<LI><a href="#[ef]">>></a> check_pkt_buf_rev
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[141]"></a>drv_rxbr_enable_irq</STRONG> (Thumb, 90 bytes, Stack size 8 bytes, drv_rxbr.o(i.drv_rxbr_enable_irq))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_rxbr_enable_irq ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[9b]">>></a> drv_sys_cfg_set_int
|
|
<LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
<LI><a href="#[142]">>></a> __NVIC_EnableIRQ
|
|
<LI><a href="#[143]">>></a> __NVIC_DisableIRQ
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[161]">>></a> hal_dsi_rx_ctrl_init_rxbr
|
|
<LI><a href="#[b9]">>></a> hal_dsi_rx_ctrl_deinit
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[17e]"></a>drv_rxbr_frame_drop_cfg</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_frame_drop_cfg))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[161]">>></a> hal_dsi_rx_ctrl_init_rxbr
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[16a]"></a>drv_rxbr_get_clk</STRONG> (Thumb, 44 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_get_clk))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[160]">>></a> hal_dsi_rx_ctrl_init_dsi_rx
|
|
<LI><a href="#[19b]">>></a> hal_dsi_rx_ctrl_set_cus_esc_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[22d]"></a>drv_rxbr_get_col_addr</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_get_col_addr))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[22c]">>></a> rx_partial_update
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[22e]"></a>drv_rxbr_get_page_addr</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_get_page_addr))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[22c]">>></a> rx_partial_update
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1a0]"></a>drv_rxbr_hline_rcv0_cfg</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_hline_rcv0_cfg))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[19e]">>></a> hal_dsi_rx_ctrl_set_cus_sync_line
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[183]"></a>drv_rxbr_hline_rcv_cfg</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_hline_rcv_cfg))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[161]">>></a> hal_dsi_rx_ctrl_init_rxbr
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[201]"></a>drv_rxbr_register_irq0_callback</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_register_irq0_callback))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[15f]">>></a> hal_internal_vsync_init_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[202]"></a>drv_rxbr_register_irq1_callback</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_register_irq1_callback))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[15f]">>></a> hal_internal_vsync_init_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[19a]"></a>drv_rxbr_set_ack_pkt_header</STRONG> (Thumb, 20 bytes, Stack size 8 bytes, drv_rxbr.o(i.drv_rxbr_set_ack_pkt_header))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_rxbr_set_ack_pkt_header
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a4]">>></a> hal_dsi_rx_ctrl_send_ack_cmd
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[144]"></a>drv_rxbr_set_cmd_filter</STRONG> (Thumb, 204 bytes, Stack size 20 bytes, drv_rxbr.o(i.drv_rxbr_set_cmd_filter))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = drv_rxbr_set_cmd_filter ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[cc]">>></a> __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[184]">>></a> hal_internal_vsync_set_auto_hw_filter
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[17d]"></a>drv_rxbr_set_color_format</STRONG> (Thumb, 20 bytes, Stack size 8 bytes, drv_rxbr.o(i.drv_rxbr_set_color_format))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_rxbr_set_color_format
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[161]">>></a> hal_dsi_rx_ctrl_init_rxbr
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[159]"></a>drv_rxbr_set_inten</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_inten))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[161]">>></a> hal_dsi_rx_ctrl_init_rxbr
|
|
<LI><a href="#[b5]">>></a> hal_dsi_rx_ctrl_dsc_async_handler
|
|
<LI><a href="#[32]">>></a> rxbr_irq0_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[17f]"></a>drv_rxbr_set_ltpo_drop_th</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_ltpo_drop_th))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[161]">>></a> hal_dsi_rx_ctrl_init_rxbr
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[180]"></a>drv_rxbr_set_usr_cfg</STRONG> (Thumb, 38 bytes, Stack size 16 bytes, drv_rxbr.o(i.drv_rxbr_set_usr_cfg))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_rxbr_set_usr_cfg
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[161]">>></a> hal_dsi_rx_ctrl_init_rxbr
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[181]"></a>drv_rxbr_set_usr_col</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_usr_col))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[161]">>></a> hal_dsi_rx_ctrl_init_rxbr
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[182]"></a>drv_rxbr_set_usr_row</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_rxbr.o(i.drv_rxbr_set_usr_row))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[161]">>></a> hal_dsi_rx_ctrl_init_rxbr
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[21d]"></a>drv_spi_m_read_data</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, drv_spi_master.o(i.drv_spi_m_read_data))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[e5]">>></a> hal_spi_m_clear_rxfifo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[ce]"></a>drv_swire_set_int</STRONG> (Thumb, 64 bytes, Stack size 16 bytes, drv_swire.o(i.drv_swire_set_int))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_swire_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[9b]">>></a> drv_sys_cfg_set_int
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[4a]">>></a> app_SWIRE_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[222]"></a>drv_sys_cfg_clear_all_int</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_clear_all_int))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[e7]">>></a> hal_system_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[93]"></a>drv_sys_cfg_clear_pending</STRONG> (Thumb, 32 bytes, Stack size 8 bytes, drv_sys_cfg.o(i.drv_sys_cfg_clear_pending))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[14e]">>></a> drv_vidc_enable_irq
|
|
<LI><a href="#[141]">>></a> drv_rxbr_enable_irq
|
|
<LI><a href="#[139]">>></a> drv_memc_enable_irq
|
|
<LI><a href="#[107]">>></a> drv_dsi_rx_enable_irq
|
|
<LI><a href="#[8f]">>></a> hal_gpio_init_eint
|
|
<LI><a href="#[b2]">>></a> hal_gpio_set_ap_reset_int
|
|
<LI><a href="#[3a]">>></a> app_fls_ctrl_Handler
|
|
<LI><a href="#[37]">>></a> app_MIPI_RX_IRQn_Handler
|
|
<LI><a href="#[36]">>></a> app_LCDC_IRQn_Handler
|
|
<LI><a href="#[146]">>></a> drv_timer_clear_status_flags
|
|
<LI><a href="#[53]">>></a> app_EXTI_INT7_IRQn_Handler
|
|
<LI><a href="#[52]">>></a> app_EXTI_INT6_IRQn_Handler
|
|
<LI><a href="#[51]">>></a> app_EXTI_INT5_IRQn_Handler
|
|
<LI><a href="#[50]">>></a> app_EXTI_INT4_IRQn_Handler
|
|
<LI><a href="#[4f]">>></a> app_EXTI_INT3_IRQn_Handler
|
|
<LI><a href="#[4e]">>></a> app_EXTI_INT2_IRQn_Handler
|
|
<LI><a href="#[4d]">>></a> app_EXTI_INT1_IRQn_Handler
|
|
<LI><a href="#[4c]">>></a> app_EXTI_INT0_IRQn_Handler
|
|
<LI><a href="#[4b]">>></a> app_AP_NRESET_IRQn_Handler
|
|
<LI><a href="#[fa]">>></a> drv_dma_clear_flag
|
|
<LI><a href="#[91]">>></a> UART0_IRQ_Handle
|
|
<LI><a href="#[47]">>></a> app_WDG_IRQn_Handler
|
|
<LI><a href="#[4a]">>></a> app_SWIRE_IRQn_Handler
|
|
<LI><a href="#[3d]">>></a> app_SPIS_IRQn_Handler
|
|
<LI><a href="#[49]">>></a> app_PWMDET_IRQn_Handler
|
|
<LI><a href="#[41]">>></a> app_VIDC_IRQn_Handler
|
|
<LI><a href="#[3f]">>></a> app_VPRE_IRQn_Handler
|
|
<LI><a href="#[40]">>></a> app_ADC_IRQn_Handler
|
|
<LI><a href="#[42]">>></a> app_MEMC_IRQn_Handler
|
|
<LI><a href="#[38]">>></a> app_MIPI_TX_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[f3]"></a>drv_sys_cfg_sel_ap_rst_lvl_trig</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_lvl_trig))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[145]">>></a> drv_sys_cfg_sel_ap_rst_trig
|
|
<LI><a href="#[c4]">>></a> drv_ap_rst_trig_edge_detect
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[145]"></a>drv_sys_cfg_sel_ap_rst_trig</STRONG> (Thumb, 22 bytes, Stack size 4 bytes, drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_trig))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = drv_sys_cfg_sel_ap_rst_trig
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[f3]">>></a> drv_sys_cfg_sel_ap_rst_lvl_trig
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[b2]">>></a> hal_gpio_set_ap_reset_int
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1ee]"></a>drv_sys_cfg_sel_gpio_group</STRONG> (Thumb, 30 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_sel_gpio_group))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[8f]">>></a> hal_gpio_init_eint
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1ef]"></a>drv_sys_cfg_sel_int_trig</STRONG> (Thumb, 30 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_sel_int_trig))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[8f]">>></a> hal_gpio_init_eint
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[127]"></a>drv_sys_cfg_set_dma_rx_req</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_set_dma_rx_req))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[125]">>></a> drv_i2c_master_read_dma
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[12c]"></a>drv_sys_cfg_set_dma_tx_req</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_set_dma_tx_req))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[d6]">>></a> hal_i2c_s_init
|
|
<LI><a href="#[12b]">>></a> drv_i2c_master_write_dma
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[9b]"></a>drv_sys_cfg_set_int</STRONG> (Thumb, 30 bytes, Stack size 0 bytes, drv_sys_cfg.o(i.drv_sys_cfg_set_int))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[14e]">>></a> drv_vidc_enable_irq
|
|
<LI><a href="#[141]">>></a> drv_rxbr_enable_irq
|
|
<LI><a href="#[139]">>></a> drv_memc_enable_irq
|
|
<LI><a href="#[107]">>></a> drv_dsi_rx_enable_irq
|
|
<LI><a href="#[b2]">>></a> hal_gpio_set_ap_reset_int
|
|
<LI><a href="#[99]">>></a> UART_init
|
|
<LI><a href="#[14a]">>></a> drv_timer_set_int
|
|
<LI><a href="#[fb]">>></a> drv_dma_enable_channel_interrupts
|
|
<LI><a href="#[11f]">>></a> drv_gpio_set_int
|
|
<LI><a href="#[138]">>></a> drv_lcdc_set_int
|
|
<LI><a href="#[11c]">>></a> drv_dsi_tx_set_int
|
|
<LI><a href="#[ce]">>></a> drv_swire_set_int
|
|
<LI><a href="#[d0]">>></a> drv_wdg_set_int
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[146]"></a>drv_timer_clear_status_flags</STRONG> (Thumb, 26 bytes, Stack size 8 bytes, drv_timer.o(i.drv_timer_clear_status_flags))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_timer_clear_status_flags ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
<LI><a href="#[147]">>></a> drv_timer_get_instance
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[cf]">>></a> drv_timer_handle_interrupt
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[148]"></a>drv_timer_enable</STRONG> (Thumb, 32 bytes, Stack size 4 bytes, drv_timer.o(i.drv_timer_enable))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = drv_timer_enable
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[147]">>></a> drv_timer_get_instance
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ac]">>></a> hal_timer_start
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[147]"></a>drv_timer_get_instance</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_timer.o(i.drv_timer_get_instance))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[14d]">>></a> drv_timer_set_prescaler
|
|
<LI><a href="#[14b]">>></a> drv_timer_set_match
|
|
<LI><a href="#[14c]">>></a> drv_timer_set_current_count
|
|
<LI><a href="#[149]">>></a> drv_timer_get_prescaler
|
|
<LI><a href="#[148]">>></a> drv_timer_enable
|
|
<LI><a href="#[146]">>></a> drv_timer_clear_status_flags
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[149]"></a>drv_timer_get_prescaler</STRONG> (Thumb, 14 bytes, Stack size 4 bytes, drv_timer.o(i.drv_timer_get_prescaler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = drv_timer_get_prescaler
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[147]">>></a> drv_timer_get_instance
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ac]">>></a> hal_timer_start
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[227]"></a>drv_timer_register_callback</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, drv_timer.o(i.drv_timer_register_callback))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[ac]">>></a> hal_timer_start
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[14c]"></a>drv_timer_set_current_count</STRONG> (Thumb, 12 bytes, Stack size 4 bytes, drv_timer.o(i.drv_timer_set_current_count))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = drv_timer_set_current_count
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[147]">>></a> drv_timer_get_instance
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ac]">>></a> hal_timer_start
|
|
<LI><a href="#[cf]">>></a> drv_timer_handle_interrupt
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[14a]"></a>drv_timer_set_int</STRONG> (Thumb, 68 bytes, Stack size 16 bytes, drv_timer.o(i.drv_timer_set_int))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_timer_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[9b]">>></a> drv_sys_cfg_set_int
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ac]">>></a> hal_timer_start
|
|
<LI><a href="#[cf]">>></a> drv_timer_handle_interrupt
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[14b]"></a>drv_timer_set_match</STRONG> (Thumb, 12 bytes, Stack size 4 bytes, drv_timer.o(i.drv_timer_set_match))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = drv_timer_set_match
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[147]">>></a> drv_timer_get_instance
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ac]">>></a> hal_timer_start
|
|
<LI><a href="#[cf]">>></a> drv_timer_handle_interrupt
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[14d]"></a>drv_timer_set_prescaler</STRONG> (Thumb, 22 bytes, Stack size 4 bytes, drv_timer.o(i.drv_timer_set_prescaler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = drv_timer_set_prescaler
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[147]">>></a> drv_timer_get_instance
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ab]">>></a> hal_timer_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[114]"></a>drv_tx_phy_test_enter</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_tx_phy_test_enter))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[112]">>></a> drv_dsi_tx_phy_test_setup
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[11b]"></a>drv_tx_phy_test_exit</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, drv_dsi_tx.o(i.drv_tx_phy_test_exit))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[112]">>></a> drv_dsi_tx_phy_test_setup
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[238]"></a>drv_vidc_clear_irq</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_clear_irq))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[34]">>></a> vidc_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1a9]"></a>drv_vidc_enable</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_enable))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1a7]">>></a> hal_internal_vsync_set_tear_mode
|
|
<LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
<LI><a href="#[b8]">>></a> hal_dsi_rx_ctrl_stop
|
|
<LI><a href="#[1a8]">>></a> hal_dsi_rx_ctrl_start
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[14e]"></a>drv_vidc_enable_irq</STRONG> (Thumb, 58 bytes, Stack size 8 bytes, drv_vidc.o(i.drv_vidc_enable_irq))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_vidc_enable_irq ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[9b]">>></a> drv_sys_cfg_set_int
|
|
<LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
<LI><a href="#[b9]">>></a> hal_dsi_rx_ctrl_deinit
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[237]"></a>drv_vidc_get_irq_status</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_get_irq_status))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[34]">>></a> vidc_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[188]"></a>drv_vidc_init_module_enable</STRONG> (Thumb, 36 bytes, Stack size 16 bytes, drv_vidc.o(i.drv_vidc_init_module_enable))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_vidc_init_module_enable
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[203]"></a>drv_vidc_register_callback</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_register_callback))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[15f]">>></a> hal_internal_vsync_init_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1fe]"></a>drv_vidc_reset</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_reset))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
<LI><a href="#[234]">>></a> vpre_err_reset
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[187]"></a>drv_vidc_set_dst_parameter</STRONG> (Thumb, 60 bytes, Stack size 16 bytes, drv_vidc.o(i.drv_vidc_set_dst_parameter))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_vidc_set_dst_parameter
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[197]"></a>drv_vidc_set_irqen</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_irqen))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
<LI><a href="#[34]">>></a> vidc_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[195]"></a>drv_vidc_set_mirror</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_mirror))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[194]"></a>drv_vidc_set_p2r_hcoef0</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_p2r_hcoef0))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[192]"></a>drv_vidc_set_p2r_hinitb</STRONG> (Thumb, 38 bytes, Stack size 12 bytes, drv_vidc.o(i.drv_vidc_set_p2r_hinitb))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = drv_vidc_set_p2r_hinitb
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[191]"></a>drv_vidc_set_p2r_hinitr</STRONG> (Thumb, 38 bytes, Stack size 12 bytes, drv_vidc.o(i.drv_vidc_set_p2r_hinitr))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = drv_vidc_set_p2r_hinitr
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[186]"></a>drv_vidc_set_pentile_swap</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_pentile_swap))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[196]"></a>drv_vidc_set_pu_ctrl</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_pu_ctrl))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[189]"></a>drv_vidc_set_rotation</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_rotation))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[18d]"></a>drv_vidc_set_scld_hcoef0</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_hcoef0))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
<LI><a href="#[19c]">>></a> hal_dsi_rx_ctrl_set_cus_scld_filter
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[18e]"></a>drv_vidc_set_scld_hcoef1</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_hcoef1))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
<LI><a href="#[19c]">>></a> hal_dsi_rx_ctrl_set_cus_scld_filter
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[18a]"></a>drv_vidc_set_scld_step</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_step))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[18f]"></a>drv_vidc_set_scld_vcoef0</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_vcoef0))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
<LI><a href="#[19c]">>></a> hal_dsi_rx_ctrl_set_cus_scld_filter
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[190]"></a>drv_vidc_set_scld_vcoef1</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_vidc.o(i.drv_vidc_set_scld_vcoef1))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
<LI><a href="#[19c]">>></a> hal_dsi_rx_ctrl_set_cus_scld_filter
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[185]"></a>drv_vidc_set_src_parameter</STRONG> (Thumb, 22 bytes, Stack size 12 bytes, drv_vidc.o(i.drv_vidc_set_src_parameter))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = drv_vidc_set_src_parameter
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[d1]"></a>drv_wdg_clear_counter</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_wdg.o(i.drv_wdg_clear_counter))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[47]">>></a> app_WDG_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[d0]"></a>drv_wdg_set_int</STRONG> (Thumb, 48 bytes, Stack size 8 bytes, drv_wdg.o(i.drv_wdg_set_int))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_wdg_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[9b]">>></a> drv_sys_cfg_set_int
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[47]">>></a> app_WDG_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[d5]"></a>fls_clr_interrupt_flag</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_fls.o(i.fls_clr_interrupt_flag))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[3a]">>></a> app_fls_ctrl_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[29]"></a>fputc</STRONG> (Thumb, 20 bytes, Stack size 32 bytes, tau_log.o(i.fputc))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = fputc ⇒ hal_uart_transmit_blocking
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[14f]">>></a> hal_uart_transmit_blocking
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> printfa.o(i.__0printf)
|
|
</UL>
|
|
<P><STRONG><a name="[150]"></a>hal_dsi_rx_ctrl_create_handle</STRONG> (Thumb, 42 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_dsi_rx_ctrl_create_handle
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[151]">>></a> __aeabi_memclr4
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a7]">>></a> open_mipi_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[b9]"></a>hal_dsi_rx_ctrl_deinit</STRONG> (Thumb, 148 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_deinit))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = hal_dsi_rx_ctrl_deinit ⇒ hal_internal_vsync_set_rx_state ⇒ hal_internal_vsync_deinit
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[156]">>></a> hal_internal_vsync_set_rx_state
|
|
<LI><a href="#[154]">>></a> hal_internal_vsync_get_tx_state
|
|
<LI><a href="#[152]">>></a> hal_internal_vsync_get_rx_state
|
|
<LI><a href="#[14e]">>></a> drv_vidc_enable_irq
|
|
<LI><a href="#[141]">>></a> drv_rxbr_enable_irq
|
|
<LI><a href="#[139]">>></a> drv_memc_enable_irq
|
|
<LI><a href="#[107]">>></a> drv_dsi_rx_enable_irq
|
|
<LI><a href="#[153]">>></a> drv_dsc_dec_disable
|
|
<LI><a href="#[98]">>></a> drv_crgu_set_clock
|
|
<LI><a href="#[155]">>></a> drv_crgu_config_reset_modules
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[b5]"></a>hal_dsi_rx_ctrl_dsc_async_handler</STRONG> (Thumb, 120 bytes, Stack size 16 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dsc_async_handler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = hal_dsi_rx_ctrl_dsc_async_handler
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[159]">>></a> drv_rxbr_set_inten
|
|
<LI><a href="#[157]">>></a> dcs_packet_get_fifo_header
|
|
<LI><a href="#[158]">>></a> dcs_packet_free_fifo_header
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
<LI><a href="#[229]">>></a> rx_get_dcs_packet_data
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[15a]"></a>hal_dsi_rx_ctrl_gen_a_tear_signal</STRONG> (Thumb, 32 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_gen_a_tear_signal))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_dsi_rx_ctrl_gen_a_tear_signal
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[15b]">>></a> drv_memc_gen_a_tear_signal
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[a3]"></a>hal_dsi_rx_ctrl_get_max_ret_size</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_dsi_rx_ctrl_get_max_ret_size
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[15c]">>></a> drv_dsi_rx_get_max_ret_size
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[55]">>></a> ap_dcs_read
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[15d]"></a>hal_dsi_rx_ctrl_init</STRONG> (Thumb, 144 bytes, Stack size 16 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 288<LI>Call Chain = hal_dsi_rx_ctrl_init ⇒ hal_internal_vsync_init_rx ⇒ calc_framebuffer_setting ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[156]">>></a> hal_internal_vsync_set_rx_state
|
|
<LI><a href="#[15f]">>></a> hal_internal_vsync_init_rx
|
|
<LI><a href="#[162]">>></a> drv_dsc_dec_set_u8_pps
|
|
<LI><a href="#[100]">>></a> drv_dsc_dec_enable
|
|
<LI><a href="#[153]">>></a> drv_dsc_dec_disable
|
|
<LI><a href="#[165]">>></a> drv_chip_rx_init_done
|
|
<LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
<LI><a href="#[161]">>></a> hal_dsi_rx_ctrl_init_rxbr
|
|
<LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
<LI><a href="#[160]">>></a> hal_dsi_rx_ctrl_init_dsi_rx
|
|
<LI><a href="#[15e]">>></a> hal_dsi_rx_ctrl_init_clk
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
<LI><a href="#[a7]">>></a> open_mipi_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[198]"></a>hal_dsi_rx_ctrl_pre_init_pps</STRONG> (Thumb, 56 bytes, Stack size 16 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = hal_dsi_rx_ctrl_pre_init_pps ⇒ drv_dsc_dec_convert_pps_rc_parameter
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[199]">>></a> drv_dsc_dec_convert_pps_rc_parameter
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a7]">>></a> open_mipi_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[a4]"></a>hal_dsi_rx_ctrl_send_ack_cmd</STRONG> (Thumb, 212 bytes, Stack size 48 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 96<LI>Call Chain = hal_dsi_rx_ctrl_send_ack_cmd ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[19a]">>></a> drv_rxbr_set_ack_pkt_header
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[55]">>></a> ap_dcs_read
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[19b]"></a>hal_dsi_rx_ctrl_set_cus_esc_clk</STRONG> (Thumb, 34 bytes, Stack size 16 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = hal_dsi_rx_ctrl_set_cus_esc_clk ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[16a]">>></a> drv_rxbr_get_clk
|
|
<LI><a href="#[16c]">>></a> drv_dsi_rx_set_ddi_cfg
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a7]">>></a> open_mipi_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[19c]"></a>hal_dsi_rx_ctrl_set_cus_scld_filter</STRONG> (Thumb, 98 bytes, Stack size 56 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_scld_filter))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 76<LI>Call Chain = hal_dsi_rx_ctrl_set_cus_scld_filter ⇒ drv_param_init_set_scld_filter
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[171]">>></a> hal_internal_sync_get_fb_setting
|
|
<LI><a href="#[190]">>></a> drv_vidc_set_scld_vcoef1
|
|
<LI><a href="#[18f]">>></a> drv_vidc_set_scld_vcoef0
|
|
<LI><a href="#[18e]">>></a> drv_vidc_set_scld_hcoef1
|
|
<LI><a href="#[18d]">>></a> drv_vidc_set_scld_hcoef0
|
|
<LI><a href="#[19d]">>></a> drv_param_init_set_scld_filter
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a7]">>></a> open_mipi_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[19e]"></a>hal_dsi_rx_ctrl_set_cus_sync_line</STRONG> (Thumb, 44 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_sync_line))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = hal_dsi_rx_ctrl_set_cus_sync_line ⇒ hal_internal_vsync_set_sync_line ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[19f]">>></a> hal_internal_vsync_set_sync_line
|
|
<LI><a href="#[1a0]">>></a> drv_rxbr_hline_rcv0_cfg
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a7]">>></a> open_mipi_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[be]"></a>hal_dsi_rx_ctrl_set_sw_tear_mode</STRONG> (Thumb, 42 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_sw_tear_mode))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 104<LI>Call Chain = hal_dsi_rx_ctrl_set_sw_tear_mode ⇒ hal_internal_vsync_set_tear_mode ⇒ vsync_set_te_mode ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1a7]">>></a> hal_internal_vsync_set_tear_mode
|
|
<LI><a href="#[179]">>></a> drv_memc_set_tear_mode
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[5c]">>></a> ap_set_enter_sleep_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[c3]"></a>hal_dsi_rx_ctrl_set_tear_mode_ex</STRONG> (Thumb, 14 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_tear_mode_ex))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 104<LI>Call Chain = hal_dsi_rx_ctrl_set_tear_mode_ex ⇒ hal_internal_vsync_set_tear_mode ⇒ vsync_set_te_mode ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1a7]">>></a> hal_internal_vsync_set_tear_mode
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[5b]">>></a> ap_update_frame_rate
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1a8]"></a>hal_dsi_rx_ctrl_start</STRONG> (Thumb, 46 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = hal_dsi_rx_ctrl_start ⇒ hal_internal_vsync_set_rx_state ⇒ hal_internal_vsync_deinit
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[156]">>></a> hal_internal_vsync_set_rx_state
|
|
<LI><a href="#[1a9]">>></a> drv_vidc_enable
|
|
<LI><a href="#[1aa]">>></a> drv_dsi_rx_power_up
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
<LI><a href="#[a7]">>></a> open_mipi_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[b8]"></a>hal_dsi_rx_ctrl_stop</STRONG> (Thumb, 46 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_stop))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = hal_dsi_rx_ctrl_stop ⇒ hal_internal_vsync_set_rx_state ⇒ hal_internal_vsync_deinit
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[156]">>></a> hal_internal_vsync_set_rx_state
|
|
<LI><a href="#[1a9]">>></a> drv_vidc_enable
|
|
<LI><a href="#[1ab]">>></a> drv_dsi_rx_shut_down
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[bf]"></a>hal_dsi_rx_ctrl_toggle_resolution</STRONG> (Thumb, 28 bytes, Stack size 8 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 448<LI>Call Chain = hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_tx_ctrl_init ⇒ hal_dsi_tx_init_data_mode ⇒ hal_dsi_tx_init_video_mode ⇒ hal_dsi_tx_calc_video_chunks ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[56]">>></a> pps_update_handle
|
|
<LI><a href="#[5d]">>></a> ap_set_exit_sleep_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1b5]"></a>hal_dsi_tx_ctrl_create_handle</STRONG> (Thumb, 34 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_dsi_tx_ctrl_create_handle
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[151]">>></a> __aeabi_memclr4
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a8]">>></a> init_mipi_tx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[b7]"></a>hal_dsi_tx_ctrl_deinit</STRONG> (Thumb, 68 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_deinit))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 104<LI>Call Chain = hal_dsi_tx_ctrl_deinit ⇒ hal_internal_vsync_set_tx_state ⇒ vsync_set_te_mode ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[98]">>></a> drv_crgu_set_clock
|
|
<LI><a href="#[155]">>></a> drv_crgu_config_reset_modules
|
|
<LI><a href="#[1b6]">>></a> hal_internal_vsync_set_tx_state
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1b7]"></a>hal_dsi_tx_ctrl_enter_init_panel_mode</STRONG> (Thumb, 68 bytes, Stack size 32 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_enter_init_panel_mode))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = hal_dsi_tx_ctrl_enter_init_panel_mode ⇒ drv_dsi_tx_command_mode_cfg
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1b9]">>></a> drv_dsi_tx_mode
|
|
<LI><a href="#[1b8]">>></a> drv_dsi_tx_command_mode_cfg
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ad]">>></a> init_panel
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1ba]"></a>hal_dsi_tx_ctrl_exit_init_panel_mode</STRONG> (Thumb, 32 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_exit_init_panel_mode))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = hal_dsi_tx_ctrl_exit_init_panel_mode ⇒ drv_dsi_tx_command_mode_cfg
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1b9]">>></a> drv_dsi_tx_mode
|
|
<LI><a href="#[1b8]">>></a> drv_dsi_tx_command_mode_cfg
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ad]">>></a> init_panel
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1bb]"></a>hal_dsi_tx_ctrl_init</STRONG> (Thumb, 188 bytes, Stack size 72 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 392<LI>Call Chain = hal_dsi_tx_ctrl_init ⇒ hal_dsi_tx_init_data_mode ⇒ hal_dsi_tx_init_video_mode ⇒ hal_dsi_tx_calc_video_chunks ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1bc]">>></a> hal_dsi_tx_ctrl_init_clk
|
|
<LI><a href="#[1b3]">>></a> hal_dsi_tx_count_lane_rate
|
|
<LI><a href="#[1b2]">>></a> hal_dsi_tx_config_params_for_lane_rate
|
|
<LI><a href="#[1b6]">>></a> hal_internal_vsync_set_tx_state
|
|
<LI><a href="#[1bd]">>></a> hal_internal_vsync_init_tx
|
|
<LI><a href="#[1c6]">>></a> drv_dsi_tx_powerup
|
|
<LI><a href="#[112]">>></a> drv_dsi_tx_phy_test_setup
|
|
<LI><a href="#[1c5]">>></a> drv_dsi_tx_phy_status_ready
|
|
<LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
<LI><a href="#[1c0]">>></a> hal_lcdc_init_cfg
|
|
<LI><a href="#[1c3]">>></a> hal_dsi_tx_init_remains
|
|
<LI><a href="#[1be]">>></a> hal_dsi_tx_init_phy_cfg
|
|
<LI><a href="#[1c4]">>></a> hal_dsi_tx_init_interrupt
|
|
<LI><a href="#[1c1]">>></a> hal_dsi_tx_init_dpi_cfg
|
|
<LI><a href="#[1c2]">>></a> hal_dsi_tx_init_data_mode
|
|
<LI><a href="#[151]">>></a> __aeabi_memclr4
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
<LI><a href="#[a8]">>></a> init_mipi_tx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1c7]"></a>hal_dsi_tx_ctrl_panel_reset_pin</STRONG> (Thumb, 12 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_panel_reset_pin))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = hal_dsi_tx_ctrl_panel_reset_pin ⇒ hal_gpio_set_output_data
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[83]">>></a> hal_gpio_set_output_data
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ad]">>></a> init_panel
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[bc]"></a>hal_dsi_tx_ctrl_set_ccm</STRONG> (Thumb, 28 bytes, Stack size 24 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_ccm))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = hal_dsi_tx_ctrl_set_ccm ⇒ drv_param_init_set_ccm
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[13a]">>></a> drv_param_init_set_ccm
|
|
<LI><a href="#[c8]">>></a> drv_lcdc_config_int_single
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[59]">>></a> ap_get_reg_df
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1c8]"></a>hal_dsi_tx_ctrl_set_overwrite_rgb</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_dsi_tx_ctrl_set_overwrite_rgb
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1c9]">>></a> drv_lcdc_config_overwrite_rgb
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a8]">>></a> init_mipi_tx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1ca]"></a>hal_dsi_tx_ctrl_set_partial_disp</STRONG> (Thumb, 12 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_partial_disp))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_dsi_tx_ctrl_set_partial_disp
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1cb]">>></a> drv_lcdc_config_partial_display_enable
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[20f]">>></a> hal_lcdc_config_upscaler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1cc]"></a>hal_dsi_tx_ctrl_set_partial_disp_area</STRONG> (Thumb, 30 bytes, Stack size 24 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_partial_disp_area))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = hal_dsi_tx_ctrl_set_partial_disp_area ⇒ drv_lcdc_config_partial_display_area
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1cd]">>></a> drv_lcdc_config_partial_display_area
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[20f]">>></a> hal_lcdc_config_upscaler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[ae]"></a>hal_dsi_tx_ctrl_start</STRONG> (Thumb, 94 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = hal_dsi_tx_ctrl_start ⇒ hal_internal_vsync_set_tx_state ⇒ vsync_set_te_mode ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1b6]">>></a> hal_internal_vsync_set_tx_state
|
|
<LI><a href="#[1d3]">>></a> drv_lcdc_start
|
|
<LI><a href="#[1d1]">>></a> drv_lcdc_set_video_hw_mode
|
|
<LI><a href="#[1d0]">>></a> drv_lcdc_enable_shadow_reg
|
|
<LI><a href="#[1d2]">>></a> drv_lcdc_config_overwrite
|
|
<LI><a href="#[1cf]">>></a> drv_dsi_tx_phy_clock_lane_req_hs
|
|
<LI><a href="#[1ce]">>></a> drv_dsi_tx_config_eotp
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
<LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[b6]"></a>hal_dsi_tx_ctrl_stop</STRONG> (Thumb, 54 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_stop))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 104<LI>Call Chain = hal_dsi_tx_ctrl_stop ⇒ hal_internal_vsync_set_tx_state ⇒ vsync_set_te_mode ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1b6]">>></a> hal_internal_vsync_set_tx_state
|
|
<LI><a href="#[1d3]">>></a> drv_lcdc_start
|
|
<LI><a href="#[138]">>></a> drv_lcdc_set_int
|
|
<LI><a href="#[1d4]">>></a> drv_dsi_tx_shutdown
|
|
<LI><a href="#[11c]">>></a> drv_dsi_tx_set_int
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1d5]"></a>hal_dsi_tx_ctrl_write_array_cmd</STRONG> (Thumb, 210 bytes, Stack size 48 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 100<LI>Call Chain = hal_dsi_tx_ctrl_write_array_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1d6]">>></a> drv_dsi_tx_get_cmd_status
|
|
<LI><a href="#[1d8]">>></a> drv_dsi_tx_command_put_payload
|
|
<LI><a href="#[1d7]">>></a> hal_dsi_tx_send_cmd
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ad]">>></a> init_panel
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[af]"></a>hal_dsi_tx_ctrl_write_cmd</STRONG> (Thumb, 172 bytes, Stack size 48 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 100<LI>Call Chain = hal_dsi_tx_ctrl_write_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1d6]">>></a> drv_dsi_tx_get_cmd_status
|
|
<LI><a href="#[1d8]">>></a> drv_dsi_tx_command_put_payload
|
|
<LI><a href="#[1d7]">>></a> hal_dsi_tx_send_cmd
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[ad]">>></a> init_panel
|
|
<LI><a href="#[5d]">>></a> ap_set_exit_sleep_mode
|
|
<LI><a href="#[5c]">>></a> ap_set_enter_sleep_mode
|
|
<LI><a href="#[58]">>></a> ap_set_display_off
|
|
<LI><a href="#[5a]">>></a> ap_set_backlight_51
|
|
<LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[8e]"></a>hal_gpio_ctrl_eint</STRONG> (Thumb, 18 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_ctrl_eint))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = hal_gpio_ctrl_eint ⇒ drv_gpio_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[11f]">>></a> drv_gpio_set_int
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[88]">>></a> S20_Start_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[8b]"></a>hal_gpio_get_input_data</STRONG> (Thumb, 18 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_get_input_data))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_gpio_get_input_data
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1eb]">>></a> drv_gpio_get_input_data
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[88]">>></a> S20_Start_init
|
|
<LI><a href="#[b4]">>></a> app_tp_transfer_screen_int
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[8f]"></a>hal_gpio_init_eint</STRONG> (Thumb, 58 bytes, Stack size 24 bytes, hal_gpio.o(i.hal_gpio_init_eint))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = hal_gpio_init_eint ⇒ hal_gpio_set_mode
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1ed]">>></a> hal_gpio_set_mode
|
|
<LI><a href="#[1ef]">>></a> drv_sys_cfg_sel_int_trig
|
|
<LI><a href="#[1ee]">>></a> drv_sys_cfg_sel_gpio_group
|
|
<LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
<LI><a href="#[1ec]">>></a> drv_gpio_set_ioe
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[88]">>></a> S20_Start_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[dd]"></a>hal_gpio_init_input</STRONG> (Thumb, 28 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_init_input))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = hal_gpio_init_input ⇒ hal_gpio_set_mode
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1ed]">>></a> hal_gpio_set_mode
|
|
<LI><a href="#[1ec]">>></a> drv_gpio_set_ioe
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[aa]">>></a> app_tp_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[81]"></a>hal_gpio_init_output</STRONG> (Thumb, 34 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_init_output))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = hal_gpio_init_output ⇒ hal_gpio_set_mode
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1ed]">>></a> hal_gpio_set_mode
|
|
<LI><a href="#[1ec]">>></a> drv_gpio_set_ioe
|
|
<LI><a href="#[1f0]">>></a> drv_gpio_set_output_data
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[dc]">>></a> app_tp_screen_init
|
|
<LI><a href="#[aa]">>></a> app_tp_init
|
|
<LI><a href="#[80]">>></a> Gpio_swire_output
|
|
<LI><a href="#[ad]">>></a> init_panel
|
|
<LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[90]"></a>hal_gpio_reg_eint_cb</STRONG> (Thumb, 20 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_reg_eint_cb))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_gpio_reg_eint_cb
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1f1]">>></a> drv_gpio_register_callback
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[88]">>></a> S20_Start_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[b2]"></a>hal_gpio_set_ap_reset_int</STRONG> (Thumb, 76 bytes, Stack size 16 bytes, hal_gpio.o(i.hal_gpio_set_ap_reset_int))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = hal_gpio_set_ap_reset_int ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[9b]">>></a> drv_sys_cfg_set_int
|
|
<LI><a href="#[145]">>></a> drv_sys_cfg_sel_ap_rst_trig
|
|
<LI><a href="#[93]">>></a> drv_sys_cfg_clear_pending
|
|
<LI><a href="#[1f2]">>></a> drv_gpio_register_ap_reset_callback
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1ed]"></a>hal_gpio_set_mode</STRONG> (Thumb, 90 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_set_mode))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_gpio_set_mode
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1f3]">>></a> drv_gpio_set_mode3
|
|
<LI><a href="#[1f4]">>></a> drv_gpio_set_mode2
|
|
<LI><a href="#[1f5]">>></a> drv_gpio_set_mode1
|
|
<LI><a href="#[1f6]">>></a> drv_gpio_set_mode0
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[d6]">>></a> hal_i2c_s_init
|
|
<LI><a href="#[de]">>></a> hal_i2c_m_dma_init
|
|
<LI><a href="#[dd]">>></a> hal_gpio_init_input
|
|
<LI><a href="#[8f]">>></a> hal_gpio_init_eint
|
|
<LI><a href="#[81]">>></a> hal_gpio_init_output
|
|
<LI><a href="#[a7]">>></a> open_mipi_rx
|
|
<LI><a href="#[224]">>></a> hal_uart_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[83]"></a>hal_gpio_set_output_data</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_set_output_data))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_gpio_set_output_data
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1f0]">>></a> drv_gpio_set_output_data
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[c2]">>></a> app_tp_screen_analysis_int
|
|
<LI><a href="#[d9]">>></a> app_tp_phone_analysis_data
|
|
<LI><a href="#[e2]">>></a> app_tp_screen_reset
|
|
<LI><a href="#[dc]">>></a> app_tp_screen_init
|
|
<LI><a href="#[1c7]">>></a> hal_dsi_tx_ctrl_panel_reset_pin
|
|
<LI><a href="#[80]">>></a> Gpio_swire_output
|
|
<LI><a href="#[5c]">>></a> ap_set_enter_sleep_mode
|
|
<LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[8d]"></a>hal_gpio_set_pull_state</STRONG> (Thumb, 26 bytes, Stack size 8 bytes, hal_gpio.o(i.hal_gpio_set_pull_state))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = hal_gpio_set_pull_state ⇒ drv_gpio_set_pull_state ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[120]">>></a> drv_gpio_set_pull_state
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[88]">>></a> S20_Start_init
|
|
<LI><a href="#[aa]">>></a> app_tp_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[de]"></a>hal_i2c_m_dma_init</STRONG> (Thumb, 92 bytes, Stack size 16 bytes, hal_i2c_master.o(i.hal_i2c_m_dma_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 52<LI>Call Chain = hal_i2c_m_dma_init ⇒ drv_i2c_master_init ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1ed]">>></a> hal_gpio_set_mode
|
|
<LI><a href="#[124]">>></a> drv_i2c_master_init
|
|
<LI><a href="#[1f7]">>></a> drv_i2c_m_set_callback
|
|
<LI><a href="#[123]">>></a> drv_i2c_m_enable_intr
|
|
<LI><a href="#[1fa]">>></a> drv_i2c_enable_tx_dma
|
|
<LI><a href="#[1f9]">>></a> drv_i2c_enable_rx_dma
|
|
<LI><a href="#[1f8]">>></a> drv_i2c_dma_init
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[aa]">>></a> app_tp_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[df]"></a>hal_i2c_m_dma_read</STRONG> (Thumb, 26 bytes, Stack size 16 bytes, hal_i2c_master.o(i.hal_i2c_m_dma_read))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 80<LI>Call Chain = hal_i2c_m_dma_read ⇒ drv_i2c_master_read_dma ⇒ drv_dma_set_transfer ⇒ drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[125]">>></a> drv_i2c_master_read_dma
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[89]">>></a> app_tp_m_read
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[e0]"></a>hal_i2c_m_dma_write</STRONG> (Thumb, 24 bytes, Stack size 8 bytes, hal_i2c_master.o(i.hal_i2c_m_dma_write))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = hal_i2c_m_dma_write ⇒ drv_i2c_master_write_dma ⇒ drv_dma_set_transfer ⇒ drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[12b]">>></a> drv_i2c_master_write_dma
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[8c]">>></a> app_tp_m_write
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[8a]"></a>hal_i2c_m_transfer_complate</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, hal_i2c_master.o(i.hal_i2c_m_transfer_complate))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[e2]">>></a> app_tp_screen_reset
|
|
<LI><a href="#[88]">>></a> S20_Start_init
|
|
<LI><a href="#[e4]">>></a> app_tp_transfer_screen_const
|
|
<LI><a href="#[b4]">>></a> app_tp_transfer_screen_int
|
|
<LI><a href="#[c0]">>></a> ap_tp_calibration
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[e1]"></a>hal_i2c_s_dma_write</STRONG> (Thumb, 46 bytes, Stack size 16 bytes, hal_i2c_slave.o(i.hal_i2c_s_dma_write))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = hal_i2c_s_dma_write ⇒ drv_i2c_slave_write_dma ⇒ drv_dma_prepar_transfer
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[135]">>></a> drv_i2c_slave_write_dma
|
|
<LI><a href="#[fe]">>></a> drv_dma_disenable_channel
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[db]">>></a> app_tp_s_write
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[d6]"></a>hal_i2c_s_init</STRONG> (Thumb, 86 bytes, Stack size 16 bytes, hal_i2c_slave.o(i.hal_i2c_s_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = hal_i2c_s_init ⇒ drv_i2c_dma_init
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1ed]">>></a> hal_gpio_set_mode
|
|
<LI><a href="#[12c]">>></a> drv_sys_cfg_set_dma_tx_req
|
|
<LI><a href="#[1fb]">>></a> drv_i2c_slave_init
|
|
<LI><a href="#[132]">>></a> drv_i2c_set_dma_irq_callback
|
|
<LI><a href="#[1fc]">>></a> drv_i2c_s_set_callback
|
|
<LI><a href="#[12f]">>></a> drv_i2c_s_enable_intr
|
|
<LI><a href="#[fb]">>></a> drv_dma_enable_channel_interrupts
|
|
<LI><a href="#[1fa]">>></a> drv_i2c_enable_tx_dma
|
|
<LI><a href="#[1f8]">>></a> drv_i2c_dma_init
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a6]">>></a> app_tp_I2C_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[d8]"></a>hal_i2c_s_nonblocking_read</STRONG> (Thumb, 14 bytes, Stack size 0 bytes, hal_i2c_slave.o(i.hal_i2c_s_nonblocking_read))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[da]">>></a> app_tp_s_read
|
|
<LI><a href="#[a6]">>></a> app_tp_I2C_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[d7]"></a>hal_i2c_s_set_transfer</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, hal_i2c_slave.o(i.hal_i2c_s_set_transfer))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[a6]">>></a> app_tp_I2C_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1fd]"></a>hal_internal_init_memc</STRONG> (Thumb, 146 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.hal_internal_init_memc))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = hal_internal_init_memc ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[178]">>></a> drv_memc_set_tear_waveform
|
|
<LI><a href="#[179]">>></a> drv_memc_set_tear_mode
|
|
<LI><a href="#[172]">>></a> drv_memc_set_ltpo_mode
|
|
<LI><a href="#[17c]">>></a> drv_memc_set_inten
|
|
<LI><a href="#[17a]">>></a> drv_memc_set_double_buffer
|
|
<LI><a href="#[170]">>></a> drv_memc_set_data_mode
|
|
<LI><a href="#[17b]">>></a> drv_memc_set_active_height
|
|
<LI><a href="#[139]">>></a> drv_memc_enable_irq
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[171]"></a>hal_internal_sync_get_fb_setting</STRONG> (Thumb, 12 bytes, Stack size 8 bytes, hal_internal_vsync.o(i.hal_internal_sync_get_fb_setting))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_internal_sync_get_fb_setting
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[bb]">>></a> __aeabi_memcpy4
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[163]">>></a> hal_dsi_rx_ctrl_init_vidc
|
|
<LI><a href="#[164]">>></a> hal_dsi_rx_ctrl_init_memc
|
|
<LI><a href="#[19c]">>></a> hal_dsi_rx_ctrl_set_cus_scld_filter
|
|
<LI><a href="#[1bf]">>></a> hal_lcdc_init_clk
|
|
<LI><a href="#[1c0]">>></a> hal_lcdc_init_cfg
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1ac]"></a>hal_internal_sync_input_resolution_change</STRONG> (Thumb, 418 bytes, Stack size 48 bytes, hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 440<LI>Call Chain = hal_internal_sync_input_resolution_change ⇒ hal_dsi_tx_ctrl_init ⇒ hal_dsi_tx_init_data_mode ⇒ hal_dsi_tx_init_video_mode ⇒ hal_dsi_tx_calc_video_chunks ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1a9]">>></a> drv_vidc_enable
|
|
<LI><a href="#[179]">>></a> drv_memc_set_tear_mode
|
|
<LI><a href="#[155]">>></a> drv_crgu_config_reset_modules
|
|
<LI><a href="#[15a]">>></a> hal_dsi_rx_ctrl_gen_a_tear_signal
|
|
<LI><a href="#[ae]">>></a> hal_dsi_tx_ctrl_start
|
|
<LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
<LI><a href="#[1a8]">>></a> hal_dsi_rx_ctrl_start
|
|
<LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
<LI><a href="#[84]">>></a> delayUs
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[1d4]">>></a> drv_dsi_tx_shutdown
|
|
<LI><a href="#[1fe]">>></a> drv_vidc_reset
|
|
<LI><a href="#[f2]">>></a> drv_rxbr_clear_status0
|
|
<LI><a href="#[1fd]">>></a> hal_internal_init_memc
|
|
<LI><a href="#[eb]">>></a> calc_framebuffer_setting
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[bf]">>></a> hal_dsi_rx_ctrl_toggle_resolution
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1ff]"></a>hal_internal_vsync_deinit</STRONG> (Thumb, 24 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.hal_internal_vsync_deinit))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = hal_internal_vsync_deinit
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[151]">>></a> __aeabi_memclr4
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[156]">>></a> hal_internal_vsync_set_rx_state
|
|
<LI><a href="#[1b6]">>></a> hal_internal_vsync_set_tx_state
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[152]"></a>hal_internal_vsync_get_rx_state</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.hal_internal_vsync_get_rx_state))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[b9]">>></a> hal_dsi_rx_ctrl_deinit
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[21a]"></a>hal_internal_vsync_get_sync_line</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[213]">>></a> hal_lcdc_init_interrupt
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[154]"></a>hal_internal_vsync_get_tx_state</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[b9]">>></a> hal_dsi_rx_ctrl_deinit
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[15f]"></a>hal_internal_vsync_init_rx</STRONG> (Thumb, 220 bytes, Stack size 72 bytes, hal_internal_vsync.o(i.hal_internal_vsync_init_rx))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 272<LI>Call Chain = hal_internal_vsync_init_rx ⇒ calc_framebuffer_setting ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[203]">>></a> drv_vidc_register_callback
|
|
<LI><a href="#[202]">>></a> drv_rxbr_register_irq1_callback
|
|
<LI><a href="#[201]">>></a> drv_rxbr_register_irq0_callback
|
|
<LI><a href="#[f7]">>></a> drv_chip_rx_info_check
|
|
<LI><a href="#[204]">>></a> dcs_packet_fifo_init
|
|
<LI><a href="#[200]">>></a> check_mipi_rx_tx_video_info
|
|
<LI><a href="#[eb]">>></a> calc_framebuffer_setting
|
|
<LI><a href="#[bb]">>></a> __aeabi_memcpy4
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1bd]"></a>hal_internal_vsync_init_tx</STRONG> (Thumb, 172 bytes, Stack size 56 bytes, hal_internal_vsync.o(i.hal_internal_vsync_init_tx))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 256<LI>Call Chain = hal_internal_vsync_init_tx ⇒ calc_framebuffer_setting ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[200]">>></a> check_mipi_rx_tx_video_info
|
|
<LI><a href="#[eb]">>></a> calc_framebuffer_setting
|
|
<LI><a href="#[bb]">>></a> __aeabi_memcpy4
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[184]"></a>hal_internal_vsync_set_auto_hw_filter</STRONG> (Thumb, 222 bytes, Stack size 32 bytes, hal_internal_vsync.o(i.hal_internal_vsync_set_auto_hw_filter))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 80<LI>Call Chain = hal_internal_vsync_set_auto_hw_filter ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[144]">>></a> drv_rxbr_set_cmd_filter
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[161]">>></a> hal_dsi_rx_ctrl_init_rxbr
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[156]"></a>hal_internal_vsync_set_rx_state</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = hal_internal_vsync_set_rx_state ⇒ hal_internal_vsync_deinit
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1ff]">>></a> hal_internal_vsync_deinit
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[b8]">>></a> hal_dsi_rx_ctrl_stop
|
|
<LI><a href="#[1a8]">>></a> hal_dsi_rx_ctrl_start
|
|
<LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
<LI><a href="#[b9]">>></a> hal_dsi_rx_ctrl_deinit
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[19f]"></a>hal_internal_vsync_set_sync_line</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = hal_internal_vsync_set_sync_line ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[19e]">>></a> hal_dsi_rx_ctrl_set_cus_sync_line
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1a7]"></a>hal_internal_vsync_set_tear_mode</STRONG> (Thumb, 64 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 96<LI>Call Chain = hal_internal_vsync_set_tear_mode ⇒ vsync_set_te_mode ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1a9]">>></a> drv_vidc_enable
|
|
<LI><a href="#[205]">>></a> vsync_set_te_mode
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[c3]">>></a> hal_dsi_rx_ctrl_set_tear_mode_ex
|
|
<LI><a href="#[be]">>></a> hal_dsi_rx_ctrl_set_sw_tear_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1b6]"></a>hal_internal_vsync_set_tx_state</STRONG> (Thumb, 54 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 96<LI>Call Chain = hal_internal_vsync_set_tx_state ⇒ vsync_set_te_mode ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1d2]">>></a> drv_lcdc_config_overwrite
|
|
<LI><a href="#[1ff]">>></a> hal_internal_vsync_deinit
|
|
<LI><a href="#[205]">>></a> vsync_set_te_mode
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[b6]">>></a> hal_dsi_tx_ctrl_stop
|
|
<LI><a href="#[ae]">>></a> hal_dsi_tx_ctrl_start
|
|
<LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
<LI><a href="#[b7]">>></a> hal_dsi_tx_ctrl_deinit
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[e5]"></a>hal_spi_m_clear_rxfifo</STRONG> (Thumb, 14 bytes, Stack size 8 bytes, hal_spi_master.o(i.hal_spi_m_clear_rxfifo))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_spi_m_clear_rxfifo
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[21d]">>></a> drv_spi_m_read_data
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e4]">>></a> app_tp_transfer_screen_const
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[e8]"></a>hal_system_enable_systick</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, hal_system.o(i.hal_system_enable_systick))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = hal_system_enable_systick ⇒ drv_common_enable_systick ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[f8]">>></a> drv_common_enable_systick
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e6]">>></a> board_Init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[e7]"></a>hal_system_init</STRONG> (Thumb, 104 bytes, Stack size 8 bytes, hal_system.o(i.hal_system_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = hal_system_init ⇒ drv_common_system_init ⇒ drv_chip_info_init ⇒ drv_efuse_read
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[98]">>></a> drv_crgu_set_clock
|
|
<LI><a href="#[221]">>></a> handle_init
|
|
<LI><a href="#[222]">>></a> drv_sys_cfg_clear_all_int
|
|
<LI><a href="#[21e]">>></a> drv_pwr_set_system_clk_src
|
|
<LI><a href="#[223]">>></a> drv_pwr_set_pvd_mode
|
|
<LI><a href="#[21f]">>></a> drv_crgu_set_ahb_src
|
|
<LI><a href="#[220]">>></a> drv_crgu_set_ahb_pre_div
|
|
<LI><a href="#[f9]">>></a> drv_common_system_init
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e6]">>></a> board_Init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[e9]"></a>hal_system_init_console</STRONG> (Thumb, 28 bytes, Stack size 24 bytes, hal_system.o(i.hal_system_init_console))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 124<LI>Call Chain = hal_system_init_console ⇒ hal_uart_init ⇒ UART_init ⇒ UART_SetBaudRate ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[224]">>></a> hal_uart_init
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e6]">>></a> board_Init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[ea]"></a>hal_system_set_phy_calibration</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, hal_system.o(i.hal_system_set_phy_calibration))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_system_set_phy_calibration
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[225]">>></a> drv_phy_enable_calibration
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e6]">>></a> board_Init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[bd]"></a>hal_system_set_pvd</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, hal_system.o(i.hal_system_set_pvd))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_system_set_pvd
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[223]">>></a> drv_pwr_set_pvd_mode
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[2c]">>></a> ap_reset_cb
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[ba]"></a>hal_system_set_vcc</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, hal_system.o(i.hal_system_set_vcc))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_system_set_vcc
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[226]">>></a> drv_pwr_set_cp_mode
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[2c]">>></a> ap_reset_cb
|
|
<LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[ab]"></a>hal_timer_init</STRONG> (Thumb, 26 bytes, Stack size 8 bytes, hal_timer.o(i.hal_timer_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = hal_timer_init ⇒ drv_timer_set_prescaler
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[98]">>></a> drv_crgu_set_clock
|
|
<LI><a href="#[14d]">>></a> drv_timer_set_prescaler
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[ac]"></a>hal_timer_start</STRONG> (Thumb, 74 bytes, Stack size 16 bytes, hal_timer.o(i.hal_timer_start))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = hal_timer_start ⇒ drv_timer_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[14b]">>></a> drv_timer_set_match
|
|
<LI><a href="#[14a]">>></a> drv_timer_set_int
|
|
<LI><a href="#[14c]">>></a> drv_timer_set_current_count
|
|
<LI><a href="#[227]">>></a> drv_timer_register_callback
|
|
<LI><a href="#[149]">>></a> drv_timer_get_prescaler
|
|
<LI><a href="#[148]">>></a> drv_timer_enable
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[2b]">>></a> soft_timer3_cb
|
|
<LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[224]"></a>hal_uart_init</STRONG> (Thumb, 126 bytes, Stack size 40 bytes, hal_uart.o(i.hal_uart_init))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 100<LI>Call Chain = hal_uart_init ⇒ UART_init ⇒ UART_SetBaudRate ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1ed]">>></a> hal_gpio_set_mode
|
|
<LI><a href="#[99]">>></a> UART_init
|
|
<LI><a href="#[151]">>></a> __aeabi_memclr4
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e9]">>></a> hal_system_init_console
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[14f]"></a>hal_uart_transmit_blocking</STRONG> (Thumb, 12 bytes, Stack size 8 bytes, hal_uart.o(i.hal_uart_transmit_blocking))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_uart_transmit_blocking
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[228]">>></a> UART_WriteBlocking
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[29]">>></a> fputc
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[221]"></a>handle_init</STRONG> (Thumb, 140 bytes, Stack size 0 bytes, irq_redirect .o(i.handle_init))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[e7]">>></a> hal_system_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[26]"></a>main</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, main.o(i.main))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 432<LI>Call Chain = main ⇒ ap_demo ⇒ open_mipi_rx ⇒ hal_dsi_rx_ctrl_init ⇒ hal_internal_vsync_init_rx ⇒ calc_framebuffer_setting ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[e6]">>></a> board_Init
|
|
<LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> entry9a.o(.ARM.Collect$$$$0000000B)
|
|
</UL>
|
|
<P><STRONG><a name="[ec]"></a>sqrt</STRONG> (Thumb, 66 bytes, Stack size 24 bytes, sqrt.o(i.sqrt))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = sqrt ⇒ _dsqrt ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[236]">>></a> __set_errno
|
|
<LI><a href="#[7d]">>></a> _dsqrt
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[eb]">>></a> calc_framebuffer_setting
|
|
</UL>
|
|
<P>
|
|
<H3>
|
|
Local Symbols
|
|
</H3>
|
|
<P><STRONG><a name="[a9]"></a>__NVIC_SetPriority</STRONG> (Thumb, 60 bytes, Stack size 0 bytes, ap_demo.o(i.__NVIC_SetPriority))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[55]"></a>ap_dcs_read</STRONG> (Thumb, 3950 bytes, Stack size 192 bytes, ap_demo.o(i.ap_dcs_read))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 288<LI>Call Chain = ap_dcs_read ⇒ hal_dsi_rx_ctrl_send_ack_cmd ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[a4]">>></a> hal_dsi_rx_ctrl_send_ack_cmd
|
|
<LI><a href="#[a3]">>></a> hal_dsi_rx_ctrl_get_max_ret_size
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> ap_demo.o(i.open_mipi_rx)
|
|
</UL>
|
|
<P><STRONG><a name="[59]"></a>ap_get_reg_df</STRONG> (Thumb, 136 bytes, Stack size 72 bytes, ap_demo.o(i.ap_get_reg_df))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 104<LI>Call Chain = ap_get_reg_df ⇒ hal_dsi_tx_ctrl_set_ccm ⇒ drv_param_init_set_ccm
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[bc]">>></a> hal_dsi_tx_ctrl_set_ccm
|
|
<LI><a href="#[bb]">>></a> __aeabi_memcpy4
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> ap_demo.o(.constdata)
|
|
</UL>
|
|
<P><STRONG><a name="[2c]"></a>ap_reset_cb</STRONG> (Thumb, 42 bytes, Stack size 0 bytes, ap_demo.o(i.ap_reset_cb))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = ap_reset_cb ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[ba]">>></a> hal_system_set_vcc
|
|
<LI><a href="#[bd]">>></a> hal_system_set_pvd
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> ap_demo.o(i.ap_demo)
|
|
</UL>
|
|
<P><STRONG><a name="[5a]"></a>ap_set_backlight_51</STRONG> (Thumb, 28 bytes, Stack size 16 bytes, ap_demo.o(i.ap_set_backlight_51))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 116<LI>Call Chain = ap_set_backlight_51 ⇒ hal_dsi_tx_ctrl_write_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[af]">>></a> hal_dsi_tx_ctrl_write_cmd
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> ap_demo.o(.constdata)
|
|
</UL>
|
|
<P><STRONG><a name="[58]"></a>ap_set_display_off</STRONG> (Thumb, 30 bytes, Stack size 8 bytes, ap_demo.o(i.ap_set_display_off))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 108<LI>Call Chain = ap_set_display_off ⇒ hal_dsi_tx_ctrl_write_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[af]">>></a> hal_dsi_tx_ctrl_write_cmd
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> ap_demo.o(.constdata)
|
|
</UL>
|
|
<P><STRONG><a name="[57]"></a>ap_set_display_on</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, ap_demo.o(i.ap_set_display_on))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = ap_set_display_on ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> ap_demo.o(.constdata)
|
|
</UL>
|
|
<P><STRONG><a name="[5c]"></a>ap_set_enter_sleep_mode</STRONG> (Thumb, 72 bytes, Stack size 8 bytes, ap_demo.o(i.ap_set_enter_sleep_mode))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = ap_set_enter_sleep_mode ⇒ hal_dsi_rx_ctrl_set_sw_tear_mode ⇒ hal_internal_vsync_set_tear_mode ⇒ vsync_set_te_mode ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[83]">>></a> hal_gpio_set_output_data
|
|
<LI><a href="#[af]">>></a> hal_dsi_tx_ctrl_write_cmd
|
|
<LI><a href="#[be]">>></a> hal_dsi_rx_ctrl_set_sw_tear_mode
|
|
<LI><a href="#[82]">>></a> delayMs
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[80]">>></a> Gpio_swire_output
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> ap_demo.o(.constdata)
|
|
</UL>
|
|
<P><STRONG><a name="[5d]"></a>ap_set_exit_sleep_mode</STRONG> (Thumb, 58 bytes, Stack size 8 bytes, ap_demo.o(i.ap_set_exit_sleep_mode))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 456<LI>Call Chain = ap_set_exit_sleep_mode ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_tx_ctrl_init ⇒ hal_dsi_tx_init_data_mode ⇒ hal_dsi_tx_init_video_mode ⇒ hal_dsi_tx_calc_video_chunks ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[af]">>></a> hal_dsi_tx_ctrl_write_cmd
|
|
<LI><a href="#[bf]">>></a> hal_dsi_rx_ctrl_toggle_resolution
|
|
<LI><a href="#[82]">>></a> delayMs
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> ap_demo.o(.constdata)
|
|
</UL>
|
|
<P><STRONG><a name="[5e]"></a>ap_set_tp_calibration_04</STRONG> (Thumb, 22 bytes, Stack size 0 bytes, ap_demo.o(i.ap_set_tp_calibration_04))
|
|
<BR>[Address Reference Count : 1]<UL><LI> ap_demo.o(.constdata)
|
|
</UL>
|
|
<P><STRONG><a name="[5b]"></a>ap_update_frame_rate</STRONG> (Thumb, 58 bytes, Stack size 8 bytes, ap_demo.o(i.ap_update_frame_rate))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = ap_update_frame_rate ⇒ hal_dsi_rx_ctrl_set_tear_mode_ex ⇒ hal_internal_vsync_set_tear_mode ⇒ vsync_set_te_mode ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[c3]">>></a> hal_dsi_rx_ctrl_set_tear_mode_ex
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> ap_demo.o(.constdata)
|
|
</UL>
|
|
<P><STRONG><a name="[a8]"></a>init_mipi_tx</STRONG> (Thumb, 104 bytes, Stack size 16 bytes, ap_demo.o(i.init_mipi_tx))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 408<LI>Call Chain = init_mipi_tx ⇒ hal_dsi_tx_ctrl_init ⇒ hal_dsi_tx_init_data_mode ⇒ hal_dsi_tx_init_video_mode ⇒ hal_dsi_tx_calc_video_chunks ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1c8]">>></a> hal_dsi_tx_ctrl_set_overwrite_rgb
|
|
<LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
<LI><a href="#[1b5]">>></a> hal_dsi_tx_ctrl_create_handle
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[ad]"></a>init_panel</STRONG> (Thumb, 142 bytes, Stack size 32 bytes, ap_demo.o(i.init_panel))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 132<LI>Call Chain = init_panel ⇒ hal_dsi_tx_ctrl_write_cmd ⇒ hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[81]">>></a> hal_gpio_init_output
|
|
<LI><a href="#[af]">>></a> hal_dsi_tx_ctrl_write_cmd
|
|
<LI><a href="#[1d5]">>></a> hal_dsi_tx_ctrl_write_array_cmd
|
|
<LI><a href="#[1c7]">>></a> hal_dsi_tx_ctrl_panel_reset_pin
|
|
<LI><a href="#[1ba]">>></a> hal_dsi_tx_ctrl_exit_init_panel_mode
|
|
<LI><a href="#[1b7]">>></a> hal_dsi_tx_ctrl_enter_init_panel_mode
|
|
<LI><a href="#[84]">>></a> delayUs
|
|
<LI><a href="#[82]">>></a> delayMs
|
|
<LI><a href="#[80]">>></a> Gpio_swire_output
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[a7]"></a>open_mipi_rx</STRONG> (Thumb, 162 bytes, Stack size 144 bytes, ap_demo.o(i.open_mipi_rx))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 432<LI>Call Chain = open_mipi_rx ⇒ hal_dsi_rx_ctrl_init ⇒ hal_internal_vsync_init_rx ⇒ calc_framebuffer_setting ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1ed]">>></a> hal_gpio_set_mode
|
|
<LI><a href="#[1a8]">>></a> hal_dsi_rx_ctrl_start
|
|
<LI><a href="#[19e]">>></a> hal_dsi_rx_ctrl_set_cus_sync_line
|
|
<LI><a href="#[19c]">>></a> hal_dsi_rx_ctrl_set_cus_scld_filter
|
|
<LI><a href="#[19b]">>></a> hal_dsi_rx_ctrl_set_cus_esc_clk
|
|
<LI><a href="#[198]">>></a> hal_dsi_rx_ctrl_pre_init_pps
|
|
<LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
<LI><a href="#[150]">>></a> hal_dsi_rx_ctrl_create_handle
|
|
<LI><a href="#[bb]">>></a> __aeabi_memcpy4
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[a5]">>></a> ap_demo
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[56]"></a>pps_update_handle</STRONG> (Thumb, 90 bytes, Stack size 24 bytes, ap_demo.o(i.pps_update_handle))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 472<LI>Call Chain = pps_update_handle ⇒ hal_dsi_rx_ctrl_toggle_resolution ⇒ hal_internal_sync_input_resolution_change ⇒ hal_dsi_tx_ctrl_init ⇒ hal_dsi_tx_init_data_mode ⇒ hal_dsi_tx_init_video_mode ⇒ hal_dsi_tx_calc_video_chunks ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[bf]">>></a> hal_dsi_rx_ctrl_toggle_resolution
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> ap_demo.o(i.open_mipi_rx)
|
|
</UL>
|
|
<P><STRONG><a name="[2b]"></a>soft_timer3_cb</STRONG> (Thumb, 36 bytes, Stack size 8 bytes, ap_demo.o(i.soft_timer3_cb))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = soft_timer3_cb ⇒ hal_timer_start ⇒ drv_timer_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[ac]">>></a> hal_timer_start
|
|
</UL>
|
|
<BR>[Address Reference Count : 2]<UL><LI> ap_demo.o(i.soft_timer3_cb)
|
|
<LI> ap_demo.o(i.ap_demo)
|
|
</UL>
|
|
<P><STRONG><a name="[2d]"></a>app_tp_i2cs_callback</STRONG> (Thumb, 42 bytes, Stack size 16 bytes, app_tp_transfer.o(i.app_tp_i2cs_callback))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 60<LI>Call Chain = app_tp_i2cs_callback ⇒ app_tp_s_write ⇒ hal_i2c_s_dma_write ⇒ drv_i2c_slave_write_dma ⇒ drv_dma_prepar_transfer
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[d9]">>></a> app_tp_phone_analysis_data
|
|
<LI><a href="#[db]">>></a> app_tp_s_write
|
|
<LI><a href="#[da]">>></a> app_tp_s_read
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> app_tp_transfer.o(i.app_tp_I2C_init)
|
|
</UL>
|
|
<P><STRONG><a name="[89]"></a>app_tp_m_read</STRONG> (Thumb, 32 bytes, Stack size 24 bytes, app_tp_transfer.o(i.app_tp_m_read))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 104<LI>Call Chain = app_tp_m_read ⇒ hal_i2c_m_dma_read ⇒ drv_i2c_master_read_dma ⇒ drv_dma_set_transfer ⇒ drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[df]">>></a> hal_i2c_m_dma_read
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[88]">>></a> S20_Start_init
|
|
<LI><a href="#[b4]">>></a> app_tp_transfer_screen_int
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[8c]"></a>app_tp_m_write</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, app_tp_transfer.o(i.app_tp_m_write))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = app_tp_m_write ⇒ hal_i2c_m_dma_write ⇒ drv_i2c_master_write_dma ⇒ drv_dma_set_transfer ⇒ drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[e0]">>></a> hal_i2c_m_dma_write
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[e2]">>></a> app_tp_screen_reset
|
|
<LI><a href="#[88]">>></a> S20_Start_init
|
|
<LI><a href="#[c0]">>></a> ap_tp_calibration
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[28]"></a>app_tp_screen_int_callback</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, app_tp_transfer.o(i.app_tp_screen_int_callback))
|
|
<BR>[Address Reference Count : 1]<UL><LI> app_tp_transfer.o(i.S20_Start_init)
|
|
</UL>
|
|
<P><STRONG><a name="[e4]"></a>app_tp_transfer_screen_const</STRONG> (Thumb, 50 bytes, Stack size 8 bytes, app_tp_transfer.o(i.app_tp_transfer_screen_const))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 128<LI>Call Chain = app_tp_transfer_screen_const ⇒ S20_Start_init ⇒ app_tp_m_read ⇒ hal_i2c_m_dma_read ⇒ drv_i2c_master_read_dma ⇒ drv_dma_set_transfer ⇒ drv_dma_set_burst
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[e5]">>></a> hal_spi_m_clear_rxfifo
|
|
<LI><a href="#[8a]">>></a> hal_i2c_m_transfer_complate
|
|
<LI><a href="#[88]">>></a> S20_Start_init
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[b1]">>></a> app_tp_transfer_screen_start
|
|
<LI><a href="#[b4]">>></a> app_tp_transfer_screen_int
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[15e]"></a>hal_dsi_rx_ctrl_init_clk</STRONG> (Thumb, 232 bytes, Stack size 24 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = hal_dsi_rx_ctrl_init_clk ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[166]">>></a> drv_crgu_set_vidc_src
|
|
<LI><a href="#[167]">>></a> drv_crgu_set_fb_src
|
|
<LI><a href="#[168]">>></a> drv_crgu_set_fb_div
|
|
<LI><a href="#[98]">>></a> drv_crgu_set_clock
|
|
<LI><a href="#[169]">>></a> hal_dsi_rx_ctrl_set_rxbr_clk
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[160]"></a>hal_dsi_rx_ctrl_init_dsi_rx</STRONG> (Thumb, 180 bytes, Stack size 24 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 200<LI>Call Chain = hal_dsi_rx_ctrl_init_dsi_rx ⇒ hal_dsi_rx_ctrl_set_ipi_cfg ⇒ drv_dsi_rx_calc_ipi_tx_delay ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[16a]">>></a> drv_rxbr_get_clk
|
|
<LI><a href="#[10a]">>></a> drv_dsi_rx_set_up_phy
|
|
<LI><a href="#[16f]">>></a> drv_dsi_rx_set_resp_cnt
|
|
<LI><a href="#[108]">>></a> drv_dsi_rx_set_lane_swap
|
|
<LI><a href="#[16e]">>></a> drv_dsi_rx_set_inten
|
|
<LI><a href="#[16c]">>></a> drv_dsi_rx_set_ddi_cfg
|
|
<LI><a href="#[16b]">>></a> drv_dsi_rx_set_ctrl_cfg
|
|
<LI><a href="#[107]">>></a> drv_dsi_rx_enable_irq
|
|
<LI><a href="#[16d]">>></a> hal_dsi_rx_ctrl_set_ipi_cfg
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[164]"></a>hal_dsi_rx_ctrl_init_memc</STRONG> (Thumb, 308 bytes, Stack size 48 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = hal_dsi_rx_ctrl_init_memc ⇒ drv_memc_enable_irq ⇒ drv_sys_cfg_clear_pending
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[171]">>></a> hal_internal_sync_get_fb_setting
|
|
<LI><a href="#[177]">>></a> drv_memc_set_vidc_sync_cnt
|
|
<LI><a href="#[178]">>></a> drv_memc_set_tear_waveform
|
|
<LI><a href="#[179]">>></a> drv_memc_set_tear_mode
|
|
<LI><a href="#[172]">>></a> drv_memc_set_ltpo_mode
|
|
<LI><a href="#[175]">>></a> drv_memc_set_lcdc_st_conditions
|
|
<LI><a href="#[17c]">>></a> drv_memc_set_inten
|
|
<LI><a href="#[174]">>></a> drv_memc_set_fs_en_conditions
|
|
<LI><a href="#[17a]">>></a> drv_memc_set_double_buffer
|
|
<LI><a href="#[170]">>></a> drv_memc_set_data_mode
|
|
<LI><a href="#[17b]">>></a> drv_memc_set_active_height
|
|
<LI><a href="#[176]">>></a> drv_memc_sel_vsync
|
|
<LI><a href="#[173]">>></a> drv_memc_rate_transfer_sel
|
|
<LI><a href="#[139]">>></a> drv_memc_enable_irq
|
|
<LI><a href="#[cc]">>></a> __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[161]"></a>hal_dsi_rx_ctrl_init_rxbr</STRONG> (Thumb, 288 bytes, Stack size 48 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 128<LI>Call Chain = hal_dsi_rx_ctrl_init_rxbr ⇒ hal_internal_vsync_set_auto_hw_filter ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[184]">>></a> hal_internal_vsync_set_auto_hw_filter
|
|
<LI><a href="#[182]">>></a> drv_rxbr_set_usr_row
|
|
<LI><a href="#[181]">>></a> drv_rxbr_set_usr_col
|
|
<LI><a href="#[180]">>></a> drv_rxbr_set_usr_cfg
|
|
<LI><a href="#[17f]">>></a> drv_rxbr_set_ltpo_drop_th
|
|
<LI><a href="#[159]">>></a> drv_rxbr_set_inten
|
|
<LI><a href="#[17d]">>></a> drv_rxbr_set_color_format
|
|
<LI><a href="#[183]">>></a> drv_rxbr_hline_rcv_cfg
|
|
<LI><a href="#[17e]">>></a> drv_rxbr_frame_drop_cfg
|
|
<LI><a href="#[141]">>></a> drv_rxbr_enable_irq
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[163]"></a>hal_dsi_rx_ctrl_init_vidc</STRONG> (Thumb, 544 bytes, Stack size 80 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 184<LI>Call Chain = hal_dsi_rx_ctrl_init_vidc ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[171]">>></a> hal_internal_sync_get_fb_setting
|
|
<LI><a href="#[185]">>></a> drv_vidc_set_src_parameter
|
|
<LI><a href="#[190]">>></a> drv_vidc_set_scld_vcoef1
|
|
<LI><a href="#[18f]">>></a> drv_vidc_set_scld_vcoef0
|
|
<LI><a href="#[18a]">>></a> drv_vidc_set_scld_step
|
|
<LI><a href="#[18e]">>></a> drv_vidc_set_scld_hcoef1
|
|
<LI><a href="#[18d]">>></a> drv_vidc_set_scld_hcoef0
|
|
<LI><a href="#[189]">>></a> drv_vidc_set_rotation
|
|
<LI><a href="#[196]">>></a> drv_vidc_set_pu_ctrl
|
|
<LI><a href="#[186]">>></a> drv_vidc_set_pentile_swap
|
|
<LI><a href="#[191]">>></a> drv_vidc_set_p2r_hinitr
|
|
<LI><a href="#[192]">>></a> drv_vidc_set_p2r_hinitb
|
|
<LI><a href="#[194]">>></a> drv_vidc_set_p2r_hcoef0
|
|
<LI><a href="#[195]">>></a> drv_vidc_set_mirror
|
|
<LI><a href="#[197]">>></a> drv_vidc_set_irqen
|
|
<LI><a href="#[187]">>></a> drv_vidc_set_dst_parameter
|
|
<LI><a href="#[188]">>></a> drv_vidc_init_module_enable
|
|
<LI><a href="#[14e]">>></a> drv_vidc_enable_irq
|
|
<LI><a href="#[193]">>></a> drv_param_p2r_filter_init
|
|
<LI><a href="#[18c]">>></a> drv_param_init_get_scld_filter_v
|
|
<LI><a href="#[18b]">>></a> drv_param_init_get_scld_filter_h
|
|
<LI><a href="#[77]">>></a> __aeabi_ui2d
|
|
<LI><a href="#[6c]">>></a> __aeabi_dadd
|
|
<LI><a href="#[7a]">>></a> __aeabi_d2uiz
|
|
<LI><a href="#[bb]">>></a> __aeabi_memcpy4
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[15d]">>></a> hal_dsi_rx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[16d]"></a>hal_dsi_rx_ctrl_set_ipi_cfg</STRONG> (Thumb, 50 bytes, Stack size 16 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 176<LI>Call Chain = hal_dsi_rx_ctrl_set_ipi_cfg ⇒ drv_dsi_rx_calc_ipi_tx_delay ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1a1]">>></a> drv_dsi_rx_set_ipi_cfg
|
|
<LI><a href="#[101]">>></a> drv_dsi_rx_calc_ipi_tx_delay
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[160]">>></a> hal_dsi_rx_ctrl_init_dsi_rx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[169]"></a>hal_dsi_rx_ctrl_set_rxbr_clk</STRONG> (Thumb, 114 bytes, Stack size 16 bytes, hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rxbr_clk))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = hal_dsi_rx_ctrl_set_rxbr_clk
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1a2]">>></a> drv_crgu_set_rxbr_src
|
|
<LI><a href="#[1a3]">>></a> drv_crgu_set_rxbr_div
|
|
<LI><a href="#[1a5]">>></a> drv_crgu_set_dsco_src_div
|
|
<LI><a href="#[1a4]">>></a> drv_crgu_set_dsco_src
|
|
<LI><a href="#[1a6]">>></a> drv_crgu_set_dsc_core_div
|
|
<LI><a href="#[98]">>></a> drv_crgu_set_clock
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[15e]">>></a> hal_dsi_rx_ctrl_init_clk
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1ad]"></a>hal_dsi_tx_calc_video_chunks</STRONG> (Thumb, 384 bytes, Stack size 136 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_calc_video_chunks))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 272<LI>Call Chain = hal_dsi_tx_calc_video_chunks ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[78]">>></a> __aeabi_d2iz
|
|
<LI><a href="#[1b1]">>></a> drv_dsi_tx_set_video_timing
|
|
<LI><a href="#[1b0]">>></a> drv_dsi_tx_set_video_chunk
|
|
<LI><a href="#[76]">>></a> __aeabi_ui2f
|
|
<LI><a href="#[75]">>></a> __aeabi_i2f
|
|
<LI><a href="#[69]">>></a> __aeabi_fsub
|
|
<LI><a href="#[102]">>></a> __aeabi_fmul
|
|
<LI><a href="#[6b]">>></a> __aeabi_fdiv
|
|
<LI><a href="#[66]">>></a> __aeabi_fadd
|
|
<LI><a href="#[1af]">>></a> __aeabi_f2iz
|
|
<LI><a href="#[106]">>></a> __aeabi_f2d
|
|
<LI><a href="#[1ae]">>></a> __ARM_scalbnf
|
|
<LI><a href="#[151]">>></a> __aeabi_memclr4
|
|
<LI><a href="#[bb]">>></a> __aeabi_memcpy4
|
|
<LI><a href="#[61]">>></a> __aeabi_idivmod
|
|
<LI><a href="#[ee]">>></a> ceil
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1da]">>></a> hal_dsi_tx_init_video_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1b2]"></a>hal_dsi_tx_config_params_for_lane_rate</STRONG> (Thumb, 42 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_config_params_for_lane_rate))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 44<LI>Call Chain = hal_dsi_tx_config_params_for_lane_rate ⇒ __aeabi_fadd ⇒ _float_epilogue
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[66]">>></a> __aeabi_fadd
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1b3]"></a>hal_dsi_tx_count_lane_rate</STRONG> (Thumb, 1160 bytes, Stack size 120 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_count_lane_rate))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 256<LI>Call Chain = hal_dsi_tx_count_lane_rate ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[77]">>></a> __aeabi_ui2d
|
|
<LI><a href="#[7a]">>></a> __aeabi_d2uiz
|
|
<LI><a href="#[78]">>></a> __aeabi_d2iz
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[10b]">>></a> drv_phy_get_rate_para
|
|
<LI><a href="#[76]">>></a> __aeabi_ui2f
|
|
<LI><a href="#[69]">>></a> __aeabi_fsub
|
|
<LI><a href="#[102]">>></a> __aeabi_fmul
|
|
<LI><a href="#[6b]">>></a> __aeabi_fdiv
|
|
<LI><a href="#[66]">>></a> __aeabi_fadd
|
|
<LI><a href="#[1b4]">>></a> __aeabi_f2uiz
|
|
<LI><a href="#[106]">>></a> __aeabi_f2d
|
|
<LI><a href="#[61]">>></a> __aeabi_idivmod
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
<LI><a href="#[ee]">>></a> ceil
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1bc]"></a>hal_dsi_tx_ctrl_init_clk</STRONG> (Thumb, 36 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_dsi_tx_ctrl_init_clk
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[98]">>></a> drv_crgu_set_clock
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1c2]"></a>hal_dsi_tx_init_data_mode</STRONG> (Thumb, 58 bytes, Stack size 24 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_data_mode))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 320<LI>Call Chain = hal_dsi_tx_init_data_mode ⇒ hal_dsi_tx_init_video_mode ⇒ hal_dsi_tx_calc_video_chunks ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1b9]">>></a> drv_dsi_tx_mode
|
|
<LI><a href="#[1d9]">>></a> drv_dsi_tx_edpi_cmd_size
|
|
<LI><a href="#[1da]">>></a> hal_dsi_tx_init_video_mode
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1c1]"></a>hal_dsi_tx_init_dpi_cfg</STRONG> (Thumb, 42 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_cfg))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = hal_dsi_tx_init_dpi_cfg ⇒ drv_dsi_tx_dpi_polarity
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1dc]">>></a> drv_dsi_tx_dpi_polarity
|
|
<LI><a href="#[1db]">>></a> drv_dsi_tx_dpi_mode
|
|
<LI><a href="#[1dd]">>></a> drv_dsi_tx_dpi_lpcmd_time
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1c4]"></a>hal_dsi_tx_init_interrupt</STRONG> (Thumb, 28 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_interrupt))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = hal_dsi_tx_init_interrupt ⇒ drv_dsi_tx_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[11c]">>></a> drv_dsi_tx_set_int
|
|
<LI><a href="#[1de]">>></a> drv_dsi_tx_config_int
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1be]"></a>hal_dsi_tx_init_phy_cfg</STRONG> (Thumb, 28 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = hal_dsi_tx_init_phy_cfg ⇒ drv_dsi_tx_phy_time_cfg
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1e0]">>></a> drv_dsi_tx_phy_time_cfg
|
|
<LI><a href="#[1df]">>></a> drv_dsi_tx_phy_lane_mode
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1c3]"></a>hal_dsi_tx_init_remains</STRONG> (Thumb, 142 bytes, Stack size 56 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_remains))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = hal_dsi_tx_init_remains ⇒ drv_dsi_tx_timeout_cfg
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1e4]">>></a> drv_dsi_tx_timeout_cfg
|
|
<LI><a href="#[1e3]">>></a> drv_dsi_tx_set_time_out_div
|
|
<LI><a href="#[1e2]">>></a> drv_dsi_tx_set_esc_div
|
|
<LI><a href="#[1e1]">>></a> drv_dsi_tx_response_mode
|
|
<LI><a href="#[1cf]">>></a> drv_dsi_tx_phy_clock_lane_req_hs
|
|
<LI><a href="#[1e5]">>></a> drv_dsi_tx_phy_clock_lane_auto_lp
|
|
<LI><a href="#[1ce]">>></a> drv_dsi_tx_config_eotp
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1da]"></a>hal_dsi_tx_init_video_mode</STRONG> (Thumb, 82 bytes, Stack size 24 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_video_mode))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 296<LI>Call Chain = hal_dsi_tx_init_video_mode ⇒ hal_dsi_tx_calc_video_chunks ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1ad]">>></a> hal_dsi_tx_calc_video_chunks
|
|
<LI><a href="#[1e8]">>></a> drv_dsi_tx_video_mode_set_lp_cmd
|
|
<LI><a href="#[1e9]">>></a> drv_dsi_tx_video_mode_disable_hact_cmd
|
|
<LI><a href="#[1e6]">>></a> drv_dsi_tx_video_mode_cfg
|
|
<LI><a href="#[1e7]">>></a> drv_dsi_tx_set_bta_ack
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1c2]">>></a> hal_dsi_tx_init_data_mode
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1d7]"></a>hal_dsi_tx_send_cmd</STRONG> (Thumb, 60 bytes, Stack size 40 bytes, hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 52<LI>Call Chain = hal_dsi_tx_send_cmd ⇒ drv_dsi_tx_phy_status_stopstate ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[111]">>></a> drv_dsi_tx_phy_status_stopstate
|
|
<LI><a href="#[1d6]">>></a> drv_dsi_tx_get_cmd_status
|
|
<LI><a href="#[1ea]">>></a> drv_dsi_tx_command_header
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[af]">>></a> hal_dsi_tx_ctrl_write_cmd
|
|
<LI><a href="#[1d5]">>></a> hal_dsi_tx_ctrl_write_array_cmd
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[206]"></a>hal_lcdc_config_ccm</STRONG> (Thumb, 30 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_config_ccm))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = hal_lcdc_config_ccm
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[c6]">>></a> drv_param_init_get_ccm
|
|
<LI><a href="#[c7]">>></a> drv_lcdc_config_ccm
|
|
<LI><a href="#[207]">>></a> drv_lcdc_config_bypass
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1c0]">>></a> hal_lcdc_init_cfg
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[208]"></a>hal_lcdc_config_remains</STRONG> (Thumb, 68 bytes, Stack size 24 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_config_remains))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = hal_lcdc_config_remains ⇒ drv_lcdc_config_dpi_polarity
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[20c]">>></a> drv_lcdc_config_thresh
|
|
<LI><a href="#[136]">>></a> drv_lcdc_config_src_parameter
|
|
<LI><a href="#[20b]">>></a> drv_lcdc_config_endianness
|
|
<LI><a href="#[20a]">>></a> drv_lcdc_config_edpi_mode
|
|
<LI><a href="#[20d]">>></a> drv_lcdc_config_dpi_polarity
|
|
<LI><a href="#[209]">>></a> drv_lcdc_config_disp_mode
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1c0]">>></a> hal_lcdc_init_cfg
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[20e]"></a>hal_lcdc_config_rgb_to_pentile</STRONG> (Thumb, 14 bytes, Stack size 8 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_config_rgb_to_pentile))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = hal_lcdc_config_rgb_to_pentile
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[207]">>></a> drv_lcdc_config_bypass
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1c0]">>></a> hal_lcdc_init_cfg
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[20f]"></a>hal_lcdc_config_upscaler</STRONG> (Thumb, 348 bytes, Stack size 40 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_config_upscaler))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 144<LI>Call Chain = hal_lcdc_config_upscaler ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[77]">>></a> __aeabi_ui2d
|
|
<LI><a href="#[6c]">>></a> __aeabi_dadd
|
|
<LI><a href="#[7a]">>></a> __aeabi_d2uiz
|
|
<LI><a href="#[211]">>></a> drv_param_init_get_sclu_filter
|
|
<LI><a href="#[210]">>></a> drv_lcdc_config_scale_up_step
|
|
<LI><a href="#[212]">>></a> drv_lcdc_config_scale_up_coef
|
|
<LI><a href="#[207]">>></a> drv_lcdc_config_bypass
|
|
<LI><a href="#[1cc]">>></a> hal_dsi_tx_ctrl_set_partial_disp_area
|
|
<LI><a href="#[1ca]">>></a> hal_dsi_tx_ctrl_set_partial_disp
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1c0]">>></a> hal_lcdc_init_cfg
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1c0]"></a>hal_lcdc_init_cfg</STRONG> (Thumb, 60 bytes, Stack size 40 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 184<LI>Call Chain = hal_lcdc_init_cfg ⇒ hal_lcdc_config_upscaler ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[171]">>></a> hal_internal_sync_get_fb_setting
|
|
<LI><a href="#[207]">>></a> drv_lcdc_config_bypass
|
|
<LI><a href="#[213]">>></a> hal_lcdc_init_interrupt
|
|
<LI><a href="#[20f]">>></a> hal_lcdc_config_upscaler
|
|
<LI><a href="#[20e]">>></a> hal_lcdc_config_rgb_to_pentile
|
|
<LI><a href="#[208]">>></a> hal_lcdc_config_remains
|
|
<LI><a href="#[206]">>></a> hal_lcdc_config_ccm
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1bf]"></a>hal_lcdc_init_clk</STRONG> (Thumb, 376 bytes, Stack size 120 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 256<LI>Call Chain = hal_lcdc_init_clk ⇒ ceil ⇒ __aeabi_drsub ⇒ __aeabi_dadd ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[171]">>></a> hal_internal_sync_get_fb_setting
|
|
<LI><a href="#[7a]">>></a> __aeabi_d2uiz
|
|
<LI><a href="#[217]">>></a> drv_lcdc_config_dpi_timing
|
|
<LI><a href="#[219]">>></a> drv_crgu_set_lcdc_src
|
|
<LI><a href="#[218]">>></a> drv_crgu_set_lcdc_div
|
|
<LI><a href="#[215]">>></a> drv_crgu_set_dpi_pre_src
|
|
<LI><a href="#[214]">>></a> drv_crgu_set_dpi_pre_div
|
|
<LI><a href="#[216]">>></a> drv_crgu_set_dpi_mux_src
|
|
<LI><a href="#[76]">>></a> __aeabi_ui2f
|
|
<LI><a href="#[102]">>></a> __aeabi_fmul
|
|
<LI><a href="#[6b]">>></a> __aeabi_fdiv
|
|
<LI><a href="#[1af]">>></a> __aeabi_f2iz
|
|
<LI><a href="#[106]">>></a> __aeabi_f2d
|
|
<LI><a href="#[105]">>></a> __aeabi_cfrcmple
|
|
<LI><a href="#[151]">>></a> __aeabi_memclr4
|
|
<LI><a href="#[bb]">>></a> __aeabi_memcpy4
|
|
<LI><a href="#[61]">>></a> __aeabi_idivmod
|
|
<LI><a href="#[ee]">>></a> ceil
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1bb]">>></a> hal_dsi_tx_ctrl_init
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[213]"></a>hal_lcdc_init_interrupt</STRONG> (Thumb, 58 bytes, Stack size 16 bytes, hal_dsi_tx_ctrl.o(i.hal_lcdc_init_interrupt))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = hal_lcdc_init_interrupt ⇒ drv_lcdc_config_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[21a]">>></a> hal_internal_vsync_get_sync_line
|
|
<LI><a href="#[138]">>></a> drv_lcdc_set_int
|
|
<LI><a href="#[21b]">>></a> drv_lcdc_ctrl_flow
|
|
<LI><a href="#[21c]">>></a> drv_lcdc_config_int
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1c0]">>></a> hal_lcdc_init_cfg
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[1f0]"></a>drv_gpio_set_output_data</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, hal_gpio.o(i.drv_gpio_set_output_data))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[83]">>></a> hal_gpio_set_output_data
|
|
<LI><a href="#[81]">>></a> hal_gpio_init_output
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[2f]"></a>hal_i2c_master_irq_callback</STRONG> (Thumb, 24 bytes, Stack size 8 bytes, hal_i2c_master.o(i.hal_i2c_master_irq_callback))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = hal_i2c_master_irq_callback ⇒ drv_i2c_m_clear_it_pending_bit ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[121]">>></a> drv_i2c_m_clear_it_pending_bit
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> hal_i2c_master.o(i.hal_i2c_m_dma_init)
|
|
</UL>
|
|
<P><STRONG><a name="[31]"></a>hal_i2c_s_dma_user_callback</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, hal_i2c_slave.o(i.hal_i2c_s_dma_user_callback))
|
|
<BR>[Address Reference Count : 1]<UL><LI> hal_i2c_slave.o(i.hal_i2c_s_init)
|
|
</UL>
|
|
<P><STRONG><a name="[30]"></a>hal_i2c_slave_irq_callback</STRONG> (Thumb, 304 bytes, Stack size 24 bytes, hal_i2c_slave.o(i.hal_i2c_slave_irq_callback))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = hal_i2c_slave_irq_callback ⇒ drv_i2c_s_clear_it_pending_bit ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[130]">>></a> drv_i2c_s_write_data
|
|
<LI><a href="#[131]">>></a> drv_i2c_s_get_fifo_status
|
|
<LI><a href="#[12d]">>></a> drv_i2c_s_clear_it_pending_bit
|
|
<LI><a href="#[129]">>></a> drv_dma_enable_channel
|
|
<LI><a href="#[fe]">>></a> drv_dma_disenable_channel
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> hal_i2c_slave.o(i.hal_i2c_s_init)
|
|
</UL>
|
|
<P><STRONG><a name="[2e]"></a>drv_i2c_dma_callback</STRONG> (Thumb, 40 bytes, Stack size 0 bytes, drv_i2c_dma.o(i.drv_i2c_dma_callback))
|
|
<BR>[Address Reference Count : 1]<UL><LI> drv_i2c_dma.o(i.drv_i2c_set_dma_irq_callback)
|
|
</UL>
|
|
<P><STRONG><a name="[12a]"></a>drv_i2c_master_write_read_cmd</STRONG> (Thumb, 46 bytes, Stack size 20 bytes, drv_i2c_dma.o(i.drv_i2c_master_write_read_cmd))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = drv_i2c_master_write_read_cmd
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[125]">>></a> drv_i2c_master_read_dma
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[122]"></a>__NVIC_ClearPendingIRQ</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_i2c_master.o(i.__NVIC_ClearPendingIRQ))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[123]">>></a> drv_i2c_m_enable_intr
|
|
<LI><a href="#[121]">>></a> drv_i2c_m_clear_it_pending_bit
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[12e]"></a>__NVIC_ClearPendingIRQ</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_i2c_slave.o(i.__NVIC_ClearPendingIRQ))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[12f]">>></a> drv_i2c_s_enable_intr
|
|
<LI><a href="#[12d]">>></a> drv_i2c_s_clear_it_pending_bit
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[cb]"></a>__NVIC_ClearPendingIRQ</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_spi_master.o(i.__NVIC_ClearPendingIRQ))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[3e]">>></a> app_SPIM_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[cf]"></a>drv_timer_handle_interrupt</STRONG> (Thumb, 62 bytes, Stack size 16 bytes, drv_timer.o(i.drv_timer_handle_interrupt))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = drv_timer_handle_interrupt ⇒ drv_timer_set_int
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[14b]">>></a> drv_timer_set_match
|
|
<LI><a href="#[14a]">>></a> drv_timer_set_int
|
|
<LI><a href="#[14c]">>></a> drv_timer_set_current_count
|
|
<LI><a href="#[146]">>></a> drv_timer_clear_status_flags
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[46]">>></a> app_TIMER3_IRQn_Handler
|
|
<LI><a href="#[45]">>></a> app_TIMER2_IRQn_Handler
|
|
<LI><a href="#[44]">>></a> app_TIMER1_IRQn_Handler
|
|
<LI><a href="#[43]">>></a> app_TIMER0_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[eb]"></a>calc_framebuffer_setting</STRONG> (Thumb, 902 bytes, Stack size 72 bytes, hal_internal_vsync.o(i.calc_framebuffer_setting))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 200<LI>Call Chain = calc_framebuffer_setting ⇒ __aeabi_dmul ⇒ _double_epilogue ⇒ __aeabi_llsr
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[77]">>></a> __aeabi_ui2d
|
|
<LI><a href="#[73]">>></a> __aeabi_dmul
|
|
<LI><a href="#[74]">>></a> __aeabi_ddiv
|
|
<LI><a href="#[7a]">>></a> __aeabi_d2uiz
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[ed]">>></a> __aeabi_cdcmple
|
|
<LI><a href="#[ec]">>></a> sqrt
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[15f]">>></a> hal_internal_vsync_init_rx
|
|
<LI><a href="#[1ac]">>></a> hal_internal_sync_input_resolution_change
|
|
<LI><a href="#[1bd]">>></a> hal_internal_vsync_init_tx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[200]"></a>check_mipi_rx_tx_video_info</STRONG> (Thumb, 44 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.check_mipi_rx_tx_video_info))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = check_mipi_rx_tx_video_info
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[15f]">>></a> hal_internal_vsync_init_rx
|
|
<LI><a href="#[1bd]">>></a> hal_internal_vsync_init_tx
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[ef]"></a>check_pkt_buf_rev</STRONG> (Thumb, 90 bytes, Stack size 16 bytes, hal_internal_vsync.o(i.check_pkt_buf_rev))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = check_pkt_buf_rev ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[f2]">>></a> drv_rxbr_clear_status0
|
|
<LI><a href="#[f1]">>></a> drv_rxbr_clear_pkt_buffer
|
|
<LI><a href="#[f0]">>></a> drv_rxbr_get_status0
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[231]">>></a> rx_receive_pps
|
|
<LI><a href="#[229]">>></a> rx_get_dcs_packet_data
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[22a]"></a>dcs_sw_filter</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.dcs_sw_filter))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[229]">>></a> rx_get_dcs_packet_data
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[233]"></a>drv_rxbr_get_int_source</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.drv_rxbr_get_int_source))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[33]">>></a> rxbr_irq1_callback
|
|
<LI><a href="#[32]">>></a> rxbr_irq0_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[f0]"></a>drv_rxbr_get_status0</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, hal_internal_vsync.o(i.drv_rxbr_get_status0))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[32]">>></a> rxbr_irq0_callback
|
|
<LI><a href="#[ef]">>></a> check_pkt_buf_rev
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[229]"></a>rx_get_dcs_packet_data</STRONG> (Thumb, 654 bytes, Stack size 56 bytes, hal_internal_vsync.o(i.rx_get_dcs_packet_data))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 120<LI>Call Chain = rx_get_dcs_packet_data ⇒ check_pkt_buf_rev ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[b5]">>></a> hal_dsi_rx_ctrl_dsc_async_handler
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[1d8]">>></a> drv_dsi_tx_command_put_payload
|
|
<LI><a href="#[22b]">>></a> dcs_packet_fifo_alloc
|
|
<LI><a href="#[22a]">>></a> dcs_sw_filter
|
|
<LI><a href="#[ef]">>></a> check_pkt_buf_rev
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[230]">>></a> rx_receive_packet
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[22c]"></a>rx_partial_update</STRONG> (Thumb, 304 bytes, Stack size 24 bytes, hal_internal_vsync.o(i.rx_partial_update))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = rx_partial_update ⇒ __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[1a5]">>></a> drv_crgu_set_dsco_src_div
|
|
<LI><a href="#[1a4]">>></a> drv_crgu_set_dsco_src
|
|
<LI><a href="#[1a6]">>></a> drv_crgu_set_dsc_core_div
|
|
<LI><a href="#[22e]">>></a> drv_rxbr_get_page_addr
|
|
<LI><a href="#[22d]">>></a> drv_rxbr_get_col_addr
|
|
<LI><a href="#[22f]">>></a> drv_dsc_dec_get_nslc
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[32]">>></a> rxbr_irq0_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[230]"></a>rx_receive_packet</STRONG> (Thumb, 128 bytes, Stack size 8 bytes, hal_internal_vsync.o(i.rx_receive_packet))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 224<LI>Call Chain = rx_receive_packet ⇒ rx_receive_pps ⇒ drv_dsc_dec_enable ⇒ __2printf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[f2]">>></a> drv_rxbr_clear_status0
|
|
<LI><a href="#[f1]">>></a> drv_rxbr_clear_pkt_buffer
|
|
<LI><a href="#[231]">>></a> rx_receive_pps
|
|
<LI><a href="#[229]">>></a> rx_get_dcs_packet_data
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[32]">>></a> rxbr_irq0_callback
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[231]"></a>rx_receive_pps</STRONG> (Thumb, 268 bytes, Stack size 152 bytes, hal_internal_vsync.o(i.rx_receive_pps))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 216<LI>Call Chain = rx_receive_pps ⇒ drv_dsc_dec_enable ⇒ __2printf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[232]">>></a> drv_dsi_rx_get_compression_en
|
|
<LI><a href="#[162]">>></a> drv_dsc_dec_set_u8_pps
|
|
<LI><a href="#[100]">>></a> drv_dsc_dec_enable
|
|
<LI><a href="#[199]">>></a> drv_dsc_dec_convert_pps_rc_parameter
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[f1]">>></a> drv_rxbr_clear_pkt_buffer
|
|
<LI><a href="#[ef]">>></a> check_pkt_buf_rev
|
|
<LI><a href="#[151]">>></a> __aeabi_memclr4
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[230]">>></a> rx_receive_packet
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[32]"></a>rxbr_irq0_callback</STRONG> (Thumb, 158 bytes, Stack size 24 bytes, hal_internal_vsync.o(i.rxbr_irq0_callback))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 248<LI>Call Chain = rxbr_irq0_callback ⇒ rx_receive_packet ⇒ rx_receive_pps ⇒ drv_dsc_dec_enable ⇒ __2printf
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|
</UL>
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|
<BR>[Calls]<UL><LI><a href="#[159]">>></a> drv_rxbr_set_inten
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|
<LI><a href="#[f2]">>></a> drv_rxbr_clear_status0
|
|
<LI><a href="#[230]">>></a> rx_receive_packet
|
|
<LI><a href="#[22c]">>></a> rx_partial_update
|
|
<LI><a href="#[f0]">>></a> drv_rxbr_get_status0
|
|
<LI><a href="#[233]">>></a> drv_rxbr_get_int_source
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|
</UL>
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|
<BR>[Address Reference Count : 1]<UL><LI> hal_internal_vsync.o(i.hal_internal_vsync_init_rx)
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|
</UL>
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|
<P><STRONG><a name="[33]"></a>rxbr_irq1_callback</STRONG> (Thumb, 222 bytes, Stack size 32 bytes, hal_internal_vsync.o(i.rxbr_irq1_callback))
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|
<BR><BR>[Stack]<UL><LI>Max Depth = 104<LI>Call Chain = rxbr_irq1_callback ⇒ vpre_err_reset ⇒ drv_dsc_dec_set_u8_pps
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|
</UL>
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|
<BR>[Calls]<UL><LI><a href="#[85]">>></a> LOG_printf
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|
<LI><a href="#[f2]">>></a> drv_rxbr_clear_status0
|
|
<LI><a href="#[f1]">>></a> drv_rxbr_clear_pkt_buffer
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|
<LI><a href="#[235]">>></a> drv_memc_set_double_buffer_reverse
|
|
<LI><a href="#[234]">>></a> vpre_err_reset
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|
<LI><a href="#[233]">>></a> drv_rxbr_get_int_source
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</UL>
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<BR>[Address Reference Count : 1]<UL><LI> hal_internal_vsync.o(i.hal_internal_vsync_init_rx)
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|
</UL>
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|
<P><STRONG><a name="[c5]"></a>soft_gen_te</STRONG> (Thumb, 116 bytes, Stack size 20 bytes, hal_internal_vsync.o(i.soft_gen_te))
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|
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = soft_gen_te
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|
</UL>
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|
<BR>[Called By]<UL><LI><a href="#[36]">>></a> app_LCDC_IRQn_Handler
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|
</UL>
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|
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|
<P><STRONG><a name="[34]"></a>vidc_callback</STRONG> (Thumb, 194 bytes, Stack size 24 bytes, hal_internal_vsync.o(i.vidc_callback))
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|
<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = vidc_callback ⇒ LOG_printf ⇒ vsprintf
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</UL>
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|
<BR>[Calls]<UL><LI><a href="#[197]">>></a> drv_vidc_set_irqen
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<LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[1d2]">>></a> drv_lcdc_config_overwrite
|
|
<LI><a href="#[237]">>></a> drv_vidc_get_irq_status
|
|
<LI><a href="#[238]">>></a> drv_vidc_clear_irq
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> hal_internal_vsync.o(i.hal_internal_vsync_init_rx)
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|
</UL>
|
|
<P><STRONG><a name="[234]"></a>vpre_err_reset</STRONG> (Thumb, 184 bytes, Stack size 64 bytes, hal_internal_vsync.o(i.vpre_err_reset))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = vpre_err_reset ⇒ drv_dsc_dec_set_u8_pps
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[162]">>></a> drv_dsc_dec_set_u8_pps
|
|
<LI><a href="#[239]">>></a> drv_crgu_set_reset
|
|
<LI><a href="#[1fe]">>></a> drv_vidc_reset
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[33]">>></a> rxbr_irq1_callback
|
|
</UL>
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|
|
|
<P><STRONG><a name="[205]"></a>vsync_set_te_mode</STRONG> (Thumb, 254 bytes, Stack size 32 bytes, hal_internal_vsync.o(i.vsync_set_te_mode))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 80<LI>Call Chain = vsync_set_te_mode ⇒ LOG_printf ⇒ vsprintf
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[179]">>></a> drv_memc_set_tear_mode
|
|
<LI><a href="#[85]">>></a> LOG_printf
|
|
<LI><a href="#[21b]">>></a> drv_lcdc_ctrl_flow
|
|
<LI><a href="#[c8]">>></a> drv_lcdc_config_int_single
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[1a7]">>></a> hal_internal_vsync_set_tear_mode
|
|
<LI><a href="#[1b6]">>></a> hal_internal_vsync_set_tx_state
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[103]"></a>drv_dsi_rx_get_color_bpp</STRONG> (Thumb, 62 bytes, Stack size 4 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = drv_dsi_rx_get_color_bpp ⇒ __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[cc]">>></a> __ARM_common_switch8
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[101]">>></a> drv_dsi_rx_calc_ipi_tx_delay
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[104]"></a>drv_dsi_rx_get_color_pcc</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, drv_dsi_rx.o(i.drv_dsi_rx_get_color_pcc))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[101]">>></a> drv_dsi_rx_calc_ipi_tx_delay
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[10d]"></a>drv_rx_phy_test_clear</STRONG> (Thumb, 12 bytes, Stack size 8 bytes, drv_dsi_rx.o(i.drv_rx_phy_test_clear))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_rx_phy_test_clear
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[13f]">>></a> drv_phy_test_clear
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[10a]">>></a> drv_dsi_rx_set_up_phy
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[110]"></a>drv_rx_phy_test_lock</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, drv_dsi_rx.o(i.drv_rx_phy_test_lock))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_rx_phy_test_lock
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[140]">>></a> drv_phy_test_lock
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[10a]">>></a> drv_dsi_rx_set_up_phy
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[10e]"></a>drv_rx_phy_test_write_1_byte</STRONG> (Thumb, 20 bytes, Stack size 8 bytes, drv_dsi_rx.o(i.drv_rx_phy_test_write_1_byte))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = drv_rx_phy_test_write_1_byte ⇒ drv_phy_test_write_1_byte ⇒ drv_phy_test_write_data
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[13b]">>></a> drv_phy_test_write_1_byte
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[10a]">>></a> drv_dsi_rx_set_up_phy
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[10f]"></a>drv_rx_phy_test_write_2_byte</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, drv_dsi_rx.o(i.drv_rx_phy_test_write_2_byte))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = drv_rx_phy_test_write_2_byte ⇒ drv_phy_test_write_2_byte ⇒ drv_phy_test_write_data
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[13e]">>></a> drv_phy_test_write_2_byte
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[10a]">>></a> drv_dsi_rx_set_up_phy
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[117]"></a>drv_tx_phy_test_clear</STRONG> (Thumb, 10 bytes, Stack size 8 bytes, drv_dsi_tx.o(i.drv_tx_phy_test_clear))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = drv_tx_phy_test_clear
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[13f]">>></a> drv_phy_test_clear
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[112]">>></a> drv_dsi_tx_phy_test_setup
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[118]"></a>drv_tx_phy_test_write_1_byte</STRONG> (Thumb, 18 bytes, Stack size 8 bytes, drv_dsi_tx.o(i.drv_tx_phy_test_write_1_byte))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = drv_tx_phy_test_write_1_byte ⇒ drv_phy_test_write_1_byte ⇒ drv_phy_test_write_data
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[13b]">>></a> drv_phy_test_write_1_byte
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[112]">>></a> drv_dsi_tx_phy_test_setup
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[119]"></a>drv_tx_phy_test_write_2_byte</STRONG> (Thumb, 20 bytes, Stack size 8 bytes, drv_dsi_tx.o(i.drv_tx_phy_test_write_2_byte))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = drv_tx_phy_test_write_2_byte ⇒ drv_phy_test_write_2_byte ⇒ drv_phy_test_write_data
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[13e]">>></a> drv_phy_test_write_2_byte
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[112]">>></a> drv_dsi_tx_phy_test_setup
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[11a]"></a>drv_tx_phy_test_write_code</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, drv_dsi_tx.o(i.drv_tx_phy_test_write_code))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_tx_phy_test_write_code ⇒ drv_phy_test_write_code
|
|
</UL>
|
|
<BR>[Calls]<UL><LI><a href="#[13c]">>></a> drv_phy_test_write_code
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[112]">>></a> drv_dsi_tx_phy_test_setup
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[143]"></a>__NVIC_DisableIRQ</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, drv_rxbr.o(i.__NVIC_DisableIRQ))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[141]">>></a> drv_rxbr_enable_irq
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[142]"></a>__NVIC_EnableIRQ</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, drv_rxbr.o(i.__NVIC_EnableIRQ))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[141]">>></a> drv_rxbr_enable_irq
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[13d]"></a>drv_phy_test_write_data</STRONG> (Thumb, 32 bytes, Stack size 16 bytes, drv_phy_common.o(i.drv_phy_test_write_data))
|
|
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = drv_phy_test_write_data
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[13e]">>></a> drv_phy_test_write_2_byte
|
|
<LI><a href="#[13b]">>></a> drv_phy_test_write_1_byte
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[cd]"></a>__NVIC_SetPriority</STRONG> (Thumb, 60 bytes, Stack size 0 bytes, hal_spi_slave.o(i.__NVIC_SetPriority))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[3d]">>></a> app_SPIS_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[d3]"></a>drv_wdg_clear_edge_flag</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, drv_wdg.o(i.drv_wdg_clear_edge_flag))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[47]">>></a> app_WDG_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[d2]"></a>drv_wdg_read_edge_flag</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, drv_wdg.o(i.drv_wdg_read_edge_flag))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[47]">>></a> app_WDG_IRQn_Handler
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[9f]"></a>_fp_digits</STRONG> (Thumb, 344 bytes, Stack size 64 bytes, printfa.o(i._fp_digits), UNUSED)
|
|
<BR><BR>[Calls]<UL><LI><a href="#[73]">>></a> __aeabi_dmul
|
|
<LI><a href="#[74]">>></a> __aeabi_ddiv
|
|
<LI><a href="#[6c]">>></a> __aeabi_dadd
|
|
<LI><a href="#[7b]">>></a> __aeabi_uldivmod
|
|
<LI><a href="#[7e]">>></a> __aeabi_d2ulz
|
|
<LI><a href="#[a0]">>></a> __aeabi_cdrcmple
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[9d]">>></a> _printf_core
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[9d]"></a>_printf_core</STRONG> (Thumb, 1754 bytes, Stack size 128 bytes, printfa.o(i._printf_core), UNUSED)
|
|
<BR><BR>[Calls]<UL><LI><a href="#[7b]">>></a> __aeabi_uldivmod
|
|
<LI><a href="#[a1]">>></a> _printf_pre_padding
|
|
<LI><a href="#[a2]">>></a> _printf_post_padding
|
|
<LI><a href="#[9f]">>></a> _fp_digits
|
|
<LI><a href="#[62]">>></a> __aeabi_uidivmod
|
|
</UL>
|
|
<BR>[Called By]<UL><LI><a href="#[9e]">>></a> __0vsprintf
|
|
<LI><a href="#[9c]">>></a> __0printf
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[a2]"></a>_printf_post_padding</STRONG> (Thumb, 32 bytes, Stack size 24 bytes, printfa.o(i._printf_post_padding), UNUSED)
|
|
<BR><BR>[Called By]<UL><LI><a href="#[9d]">>></a> _printf_core
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[a1]"></a>_printf_pre_padding</STRONG> (Thumb, 44 bytes, Stack size 40 bytes, printfa.o(i._printf_pre_padding), UNUSED)
|
|
<BR><BR>[Called By]<UL><LI><a href="#[9d]">>></a> _printf_core
|
|
</UL>
|
|
|
|
<P><STRONG><a name="[2a]"></a>_sputc</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, printfa.o(i._sputc))
|
|
<BR><BR>[Called By]<UL><LI><a href="#[9e]">>></a> __0vsprintf
|
|
</UL>
|
|
<BR>[Address Reference Count : 1]<UL><LI> printfa.o(i.__0vsprintf)
|
|
</UL><P>
|
|
<H3>
|
|
Undefined Global Symbols
|
|
</H3><HR></body></html>
|