/**************************************************************************//**
 * @file     ARMCM0.h
 * @brief    CMSIS Core Peripheral Access Layer Header File for
 *           ARMCM0 Device
 * @version  V5.3.1
 * @date     09. July 2018
 ******************************************************************************/
/*
 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#ifndef ARMCM0_H
#define ARMCM0_H

#ifdef __cplusplus
extern "C" {
#endif


/* -------------------------  Interrupt Number Definition  ------------------------ */

typedef enum IRQn
{
    /* -------------------  Processor Exceptions Numbers  ----------------------------- */
    NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */
    HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */
    SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */
    PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */
    SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */

    /* -------------------  Processor Interrupt Numbers  ------------------------------ */
    VIDC_IRQn                     =   0,
    LCDC_IRQn                     =   1,
    MIPI_RX_IRQn                  =   2,
    MIPI_TX_IRQn                  =   3,
    MEMC_IRQn                     =   4,
    VPRE_IRQn                     =   5,
    FLSCTRL_IRQn                  =   6,
    DMA_IRQn                      =   7,
    TIMER0_IRQn                   =   8,
    TIMER1_IRQn                   =   9,
    TIMER2_IRQn                   =   10,
    TIMER3_IRQn                   =   11,
    WDG_IRQn                      =   12,
    UART_IRQn                     =   13,
    I2C0_IRQn                     =   14,
    I2C1_IRQn                     =   15,
    SPIS_IRQn                     =   16,
    SPIM_IRQn                     =   17,
    ADC_IRQn                      =   18,
    PWMDET_IRQn                   =   19,
    OTP_IRQn                      =   20,
    SWIRE_IRQn                    =   21,
    PVD_IRQn                      =   22,
    AP_NRESET_IRQn                =   23,
    EXTI_INT0_IRQn                =   24,
    EXTI_INT1_IRQn                =   25,
    EXTI_INT2_IRQn                =   26,
    EXTI_INT3_IRQn                =   27,
    EXTI_INT4_IRQn                =   28,
    EXTI_INT5_IRQn                =   29,
    EXTI_INT6_IRQn                =   30,
    EXTI_INT7_IRQn                =   31
                                      /* Interrupts 10 .. 31 are left out */
} IRQn_Type;




/* ================================================================================ */
/* ================      Processor and Core Peripheral Section     ================ */
/* ================================================================================ */

/* -------  Start of section using anonymous unions and disabling warnings  ------- */
#if   defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif

/* --------  Configuration of Core Peripherals  ----------------------------------- */
#define __CM0_REV                 0x0000U   /* Core revision r0p0 */
#define __MPU_PRESENT             0U        /* no MPU present */
#define __VTOR_PRESENT            0U        /* no VTOR present */
#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */ //20220228
#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */

#define __FPU_PRESENT             0U        /* Set to 1 if FPU is present */
#define __FPU_DP                  0U        /* single precision FPU */
#define __ICACHE_PRESENT          0U        /* Set to 1 if I-CACHE is present  */
#define __DCACHE_PRESENT          0U        /* Set to 1 if D-CACHE is present  */
#define __DSP_PRESENT             0U        /* no DSP extension present */

#define FPGA_MODE                 0
#define EDA_MODE                  0
#define EXTERN_24M                0
#define CPU_CLK_100M              0

#define LOG_MODE_RTT              0         /* 0:UART MODE  1: rtt MODE  */

#include "core_cm0.h"                       /* Processor and core peripherals */
#include "system_ARMCM0.h"                  /* System Header */

/*----------------------------------------------------------------------------
  Define clocks
 *----------------------------------------------------------------------------*/
#define  XTAL            (500000000UL)     /* Oscillator frequency */

#if FPGA_MODE
#define  SYSTEM_CLOCK    (33300000U)
#else
/* 使用外部晶振时,系统时钟只能是100M,不使用外部晶振时,系统时钟可以是100M/80M*/
#if  EXTERN_24M
#define  SYSTEM_CLOCK    (100000000U)
#else
#if CPU_CLK_100M
#define  SYSTEM_CLOCK    (100000000U)
#else
#define  SYSTEM_CLOCK    (80000000U)
#endif
#endif
#endif

/* --------  End of section using anonymous unions and disabling warnings  -------- */
#if   defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif

/* In HS mode and when the DMA is used, all variables and data structures dealing
   with the DMA during the transaction process should be 4-bytes aligned */
#define DMA_WORD_ALIGN_EN
#ifdef DMA_WORD_ALIGN_EN
#if defined   (__GNUC__)        /* GNU Compiler */
#define __ALIGN_END    __attribute__ ((aligned (4)))
#define __ALIGN_BEGIN
#else
#define __ALIGN_END
#if defined   (__CC_ARM)      /* ARM Compiler */
#define __ALIGN_BEGIN    __align(4)
#elif defined (__ICCARM__)    /* IAR Compiler */
#define __ALIGN_BEGIN
#elif defined  (__TASKING__)  /* TASKING Compiler */
#define __ALIGN_BEGIN    __align(4)
#endif /* __CC_ARM */
#endif /* __GNUC__ */
#else

#define __ALIGN_BEGIN
#define __ALIGN_END

#define __ALIGN_END_1    __attribute__ ((aligned (1)))
#endif /* DMA_WORD_ALIGN_EN */

/* __packed keyword used to decrease the data type alignment to 1-byte */
#if defined (__CC_ARM)         /* ARM Compiler */
#define __packed    __packed
#elif defined (__ICCARM__)     /* IAR Compiler */
#define __packed    __packed
#elif defined   ( __GNUC__ )   /* GNU Compiler */
#define __packed    __attribute__ ((__packed__))
#define __weak   __attribute__((weak))
#elif defined   (__TASKING__)  /* TASKING Compiler */
#define __packed    __unaligned
#endif /* __CC_ARM */

#ifdef __cplusplus
}
#endif

#endif  /* ARMCM0_H */
