diff --git a/project/Listings/WL568_S21_NT37701_V100_20230907.map b/project/Listings/WL568_S21_NT37701_V100_20230907.map index 8c73538..035beb2 100644 --- a/project/Listings/WL568_S21_NT37701_V100_20230907.map +++ b/project/Listings/WL568_S21_NT37701_V100_20230907.map @@ -31,7 +31,9 @@ Section Cross References ap_demo.o(i.ap_demo) refers to ap_demo.o(.data) for .data ap_demo.o(i.ap_get_reg_df) refers to ap_demo.o(.data) for .data ap_demo.o(i.ap_get_reg_df) refers to ap_demo.o(.bss) for .bss + ap_demo.o(i.ap_set_backlight_51) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd ap_demo.o(i.ap_set_backlight_51) refers to tau_log.o(i.LOG_printf) for LOG_printf + ap_demo.o(i.ap_set_backlight_51) refers to ap_demo.o(.data) for .data ap_demo.o(i.ap_set_display_off) refers to hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) for hal_dsi_tx_ctrl_write_cmd ap_demo.o(i.ap_set_display_off) refers to tau_log.o(i.LOG_printf) for LOG_printf ap_demo.o(i.ap_set_display_on) refers to tau_log.o(i.LOG_printf) for LOG_printf @@ -3244,480 +3246,480 @@ Image Symbol Table ap_get_reg_df 0x00012dfd Thumb Code 68 ap_demo.o(i.ap_get_reg_df) i.ap_get_tp_calibration_status_01 0x00012e48 Section 0 app_tp_st_touch.o(i.ap_get_tp_calibration_status_01) i.ap_set_backlight_51 0x00012e68 Section 0 ap_demo.o(i.ap_set_backlight_51) - ap_set_backlight_51 0x00012e69 Thumb Code 32 ap_demo.o(i.ap_set_backlight_51) - i.ap_set_display_off 0x00012eac Section 0 ap_demo.o(i.ap_set_display_off) - ap_set_display_off 0x00012ead Thumb Code 28 ap_demo.o(i.ap_set_display_off) - i.ap_set_display_on 0x00012ef0 Section 0 ap_demo.o(i.ap_set_display_on) - ap_set_display_on 0x00012ef1 Thumb Code 16 ap_demo.o(i.ap_set_display_on) - i.ap_set_enter_sleep_mode 0x00012f28 Section 0 ap_demo.o(i.ap_set_enter_sleep_mode) - ap_set_enter_sleep_mode 0x00012f29 Thumb Code 74 ap_demo.o(i.ap_set_enter_sleep_mode) - i.ap_set_exit_sleep_mode 0x00012fa8 Section 0 ap_demo.o(i.ap_set_exit_sleep_mode) - ap_set_exit_sleep_mode 0x00012fa9 Thumb Code 58 ap_demo.o(i.ap_set_exit_sleep_mode) - i.ap_set_hbm_53 0x00013018 Section 0 ap_demo.o(i.ap_set_hbm_53) - ap_set_hbm_53 0x00013019 Thumb Code 44 ap_demo.o(i.ap_set_hbm_53) - i.ap_update_frame_rate 0x00013048 Section 0 ap_demo.o(i.ap_update_frame_rate) - ap_update_frame_rate 0x00013049 Thumb Code 36 ap_demo.o(i.ap_update_frame_rate) - i.app_ADC_IRQn_Handler 0x00013070 Section 0 drv_rxbr.o(i.app_ADC_IRQn_Handler) - i.app_AP_NRESET_IRQn_Handler 0x0001308c Section 0 drv_gpio.o(i.app_AP_NRESET_IRQn_Handler) - i.app_EXTI_INT0_IRQn_Handler 0x000130b0 Section 0 drv_gpio.o(i.app_EXTI_INT0_IRQn_Handler) - i.app_EXTI_INT1_IRQn_Handler 0x000130cc Section 0 drv_gpio.o(i.app_EXTI_INT1_IRQn_Handler) - i.app_EXTI_INT2_IRQn_Handler 0x000130e8 Section 0 drv_gpio.o(i.app_EXTI_INT2_IRQn_Handler) - i.app_EXTI_INT3_IRQn_Handler 0x00013104 Section 0 drv_gpio.o(i.app_EXTI_INT3_IRQn_Handler) - i.app_EXTI_INT4_IRQn_Handler 0x00013120 Section 0 drv_gpio.o(i.app_EXTI_INT4_IRQn_Handler) - i.app_EXTI_INT5_IRQn_Handler 0x0001313c Section 0 drv_gpio.o(i.app_EXTI_INT5_IRQn_Handler) - i.app_EXTI_INT6_IRQn_Handler 0x00013158 Section 0 drv_gpio.o(i.app_EXTI_INT6_IRQn_Handler) - i.app_EXTI_INT7_IRQn_Handler 0x00013174 Section 0 drv_gpio.o(i.app_EXTI_INT7_IRQn_Handler) - i.app_HardFault_Handler 0x00013190 Section 0 drv_common.o(i.app_HardFault_Handler) - i.app_I2C0_IRQn_Handler 0x000131d8 Section 0 drv_i2c_slave.o(i.app_I2C0_IRQn_Handler) - i.app_I2C1_IRQn_Handler 0x000131f0 Section 0 drv_i2c_master.o(i.app_I2C1_IRQn_Handler) - i.app_LCDC_IRQn_Handler 0x00013200 Section 0 hal_internal_vsync.o(i.app_LCDC_IRQn_Handler) - i.app_MEMC_IRQn_Handler 0x00013330 Section 0 drv_memc.o(i.app_MEMC_IRQn_Handler) - i.app_MIPI_RX_IRQn_Handler 0x000133b8 Section 0 drv_dsi_rx.o(i.app_MIPI_RX_IRQn_Handler) - i.app_MIPI_TX_IRQn_Handler 0x00013650 Section 0 drv_dsi_tx.o(i.app_MIPI_TX_IRQn_Handler) - i.app_PWMDET_IRQn_Handler 0x000136f0 Section 0 drv_pwm.o(i.app_PWMDET_IRQn_Handler) - i.app_SPIM_IRQn_Handler 0x00013738 Section 0 drv_spi_master.o(i.app_SPIM_IRQn_Handler) - i.app_SPIS_IRQn_Handler 0x00013768 Section 0 hal_spi_slave.o(i.app_SPIS_IRQn_Handler) - i.app_SWIRE_IRQn_Handler 0x00013968 Section 0 drv_swire.o(i.app_SWIRE_IRQn_Handler) - i.app_SysTick_Handler 0x00013988 Section 0 drv_common.o(i.app_SysTick_Handler) - i.app_TIMER0_IRQn_Handler 0x000139a0 Section 0 drv_timer.o(i.app_TIMER0_IRQn_Handler) - i.app_TIMER1_IRQn_Handler 0x000139aa Section 0 drv_timer.o(i.app_TIMER1_IRQn_Handler) - i.app_TIMER2_IRQn_Handler 0x000139b4 Section 0 drv_timer.o(i.app_TIMER2_IRQn_Handler) - i.app_TIMER3_IRQn_Handler 0x000139be Section 0 drv_timer.o(i.app_TIMER3_IRQn_Handler) - i.app_UART_IRQn_Handler 0x000139c8 Section 0 drv_uart.o(i.app_UART_IRQn_Handler) - i.app_VIDC_IRQn_Handler 0x000139d0 Section 0 drv_vidc.o(i.app_VIDC_IRQn_Handler) - i.app_VPRE_IRQn_Handler 0x000139ec Section 0 drv_rxbr.o(i.app_VPRE_IRQn_Handler) - i.app_WDG_IRQn_Handler 0x00013a08 Section 0 drv_wdg.o(i.app_WDG_IRQn_Handler) - i.app_dma_irq_handler 0x00013a40 Section 0 drv_dma.o(i.app_dma_irq_handler) - i.app_fls_ctrl_Handler 0x00013a50 Section 0 norflash.o(i.app_fls_ctrl_Handler) - i.board_Init 0x00013a80 Section 0 board.o(i.board_Init) - i.calc_framebuffer_setting 0x00013aa4 Section 0 hal_internal_vsync.o(i.calc_framebuffer_setting) - i.ceil 0x00014030 Section 0 ceil.o(i.ceil) - i.check_mipi_rx_tx_video_info 0x000140f8 Section 0 hal_internal_vsync.o(i.check_mipi_rx_tx_video_info) - check_mipi_rx_tx_video_info 0x000140f9 Thumb Code 44 hal_internal_vsync.o(i.check_mipi_rx_tx_video_info) - i.check_pkt_buf_rev 0x00014124 Section 0 hal_internal_vsync.o(i.check_pkt_buf_rev) - check_pkt_buf_rev 0x00014125 Thumb Code 74 hal_internal_vsync.o(i.check_pkt_buf_rev) - i.dcs_packet_fifo_alloc 0x000141a8 Section 0 dcs_packet_fifo.o(i.dcs_packet_fifo_alloc) - i.dcs_packet_fifo_init 0x00014200 Section 0 dcs_packet_fifo.o(i.dcs_packet_fifo_init) - i.dcs_packet_free_fifo_header 0x00014218 Section 0 dcs_packet_fifo.o(i.dcs_packet_free_fifo_header) - i.dcs_packet_get_fifo_header 0x0001425c Section 0 dcs_packet_fifo.o(i.dcs_packet_get_fifo_header) - i.dcs_sw_filter 0x00014280 Section 0 hal_internal_vsync.o(i.dcs_sw_filter) - dcs_sw_filter 0x00014281 Thumb Code 36 hal_internal_vsync.o(i.dcs_sw_filter) - i.delayMs 0x000142ac Section 0 tau_delay.o(i.delayMs) - i.delayUs 0x000142c4 Section 0 tau_delay.o(i.delayUs) - i.drv_ap_rst_trig_edge_detect 0x000142e8 Section 0 drv_sys_cfg.o(i.drv_ap_rst_trig_edge_detect) - i.drv_chip_info_get_info 0x00014320 Section 0 drv_chip_info.o(i.drv_chip_info_get_info) - i.drv_chip_info_init 0x0001432c Section 0 drv_chip_info.o(i.drv_chip_info_init) - i.drv_chip_rx_info_check 0x0001436c Section 0 drv_chip_info.o(i.drv_chip_rx_info_check) - i.drv_chip_rx_init_done 0x0001441c Section 0 drv_chip_info.o(i.drv_chip_rx_init_done) - i.drv_common_enable_systick 0x00014430 Section 0 drv_common.o(i.drv_common_enable_systick) - i.drv_common_system_init 0x00014488 Section 0 drv_common.o(i.drv_common_system_init) - i.drv_crgu_config_reset_modules 0x00014490 Section 0 drv_crgu.o(i.drv_crgu_config_reset_modules) - i.drv_crgu_set_ahb_pre_div 0x000144a0 Section 0 drv_crgu.o(i.drv_crgu_set_ahb_pre_div) - i.drv_crgu_set_ahb_src 0x000144b4 Section 0 drv_crgu.o(i.drv_crgu_set_ahb_src) - i.drv_crgu_set_clock 0x000144c8 Section 0 drv_crgu.o(i.drv_crgu_set_clock) - i.drv_crgu_set_dpi_mux_src 0x000144e8 Section 0 drv_crgu.o(i.drv_crgu_set_dpi_mux_src) - i.drv_crgu_set_dpi_pre_div 0x000144fc Section 0 drv_crgu.o(i.drv_crgu_set_dpi_pre_div) - i.drv_crgu_set_dpi_pre_src 0x00014514 Section 0 drv_crgu.o(i.drv_crgu_set_dpi_pre_src) - i.drv_crgu_set_dsc_core_div 0x00014528 Section 0 drv_crgu.o(i.drv_crgu_set_dsc_core_div) - i.drv_crgu_set_dsco_src 0x0001453c Section 0 drv_crgu.o(i.drv_crgu_set_dsco_src) - i.drv_crgu_set_dsco_src_div 0x00014550 Section 0 drv_crgu.o(i.drv_crgu_set_dsco_src_div) - i.drv_crgu_set_fb_div 0x00014564 Section 0 drv_crgu.o(i.drv_crgu_set_fb_div) - i.drv_crgu_set_fb_src 0x00014578 Section 0 drv_crgu.o(i.drv_crgu_set_fb_src) - i.drv_crgu_set_lcdc_div 0x0001458c Section 0 drv_crgu.o(i.drv_crgu_set_lcdc_div) - i.drv_crgu_set_lcdc_src 0x000145a0 Section 0 drv_crgu.o(i.drv_crgu_set_lcdc_src) - i.drv_crgu_set_mipi_cfg_src 0x000145b4 Section 0 drv_crgu.o(i.drv_crgu_set_mipi_cfg_src) - i.drv_crgu_set_mipi_ref_src 0x000145c8 Section 0 drv_crgu.o(i.drv_crgu_set_mipi_ref_src) - i.drv_crgu_set_reset 0x000145e0 Section 0 drv_crgu.o(i.drv_crgu_set_reset) - i.drv_crgu_set_rxbr_div 0x000145f8 Section 0 drv_crgu.o(i.drv_crgu_set_rxbr_div) - i.drv_crgu_set_rxbr_src 0x0001460c Section 0 drv_crgu.o(i.drv_crgu_set_rxbr_src) - i.drv_crgu_set_vidc_src 0x00014620 Section 0 drv_crgu.o(i.drv_crgu_set_vidc_src) - i.drv_dma_clear_flag 0x00014634 Section 0 drv_dma.o(i.drv_dma_clear_flag) - i.drv_dma_get_channel_flag 0x0001464c Section 0 drv_dma.o(i.drv_dma_get_channel_flag) - i.drv_dma_irq_handler 0x00014658 Section 0 drv_dma.o(i.drv_dma_irq_handler) - i.drv_dsc_dec_convert_pps_rc_parameter 0x000146e8 Section 0 drv_dsc_dec.o(i.drv_dsc_dec_convert_pps_rc_parameter) - i.drv_dsc_dec_disable 0x0001471e Section 0 drv_dsc_dec.o(i.drv_dsc_dec_disable) - i.drv_dsc_dec_enable 0x0001472c Section 0 drv_dsc_dec.o(i.drv_dsc_dec_enable) - i.drv_dsc_dec_get_nslc 0x000147a0 Section 0 drv_dsc_dec.o(i.drv_dsc_dec_get_nslc) - i.drv_dsc_dec_set_u8_pps 0x000147aa Section 0 drv_dsc_dec.o(i.drv_dsc_dec_set_u8_pps) - i.drv_dsi_rx_calc_ipi_tx_delay 0x000147d4 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) - i.drv_dsi_rx_enable_irq 0x000148d8 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) - i.drv_dsi_rx_get_bta_status 0x00014918 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_bta_status) - i.drv_dsi_rx_get_color_bpp 0x00014928 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp) - drv_dsi_rx_get_color_bpp 0x00014929 Thumb Code 62 drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp) - i.drv_dsi_rx_get_color_pcc 0x00014978 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_color_pcc) - drv_dsi_rx_get_color_pcc 0x00014979 Thumb Code 24 drv_dsi_rx.o(i.drv_dsi_rx_get_color_pcc) - i.drv_dsi_rx_get_compression_en 0x00014994 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en) - i.drv_dsi_rx_get_max_ret_size 0x0001499c Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_max_ret_size) - i.drv_dsi_rx_power_up 0x000149a2 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_power_up) - i.drv_dsi_rx_set_ctrl_cfg 0x000149b0 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ctrl_cfg) - i.drv_dsi_rx_set_ddi_cfg 0x000149d0 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) - i.drv_dsi_rx_set_inten 0x000149e0 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_inten) - i.drv_dsi_rx_set_ipi_cfg 0x000149e4 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_cfg) - i.drv_dsi_rx_set_lane_swap 0x000149f4 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_lane_swap) - i.drv_dsi_rx_set_resp_cnt 0x00014a3a Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_resp_cnt) - i.drv_dsi_rx_set_up_phy 0x00014a60 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) - i.drv_dsi_rx_shut_down 0x00014b64 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_shut_down) - i.drv_dsi_tx_command_header 0x00014b72 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_command_header) - i.drv_dsi_tx_command_mode_cfg 0x00014b86 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg) - i.drv_dsi_tx_command_put_payload 0x00014bf2 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) - i.drv_dsi_tx_config_eotp 0x00014bf6 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_config_eotp) - i.drv_dsi_tx_config_int 0x00014c0e Section 0 drv_dsi_tx.o(i.drv_dsi_tx_config_int) - i.drv_dsi_tx_dpi_lpcmd_time 0x00014c16 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_dpi_lpcmd_time) - i.drv_dsi_tx_dpi_mode 0x00014c1e Section 0 drv_dsi_tx.o(i.drv_dsi_tx_dpi_mode) - i.drv_dsi_tx_dpi_polarity 0x00014c28 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_dpi_polarity) - i.drv_dsi_tx_edpi_cmd_size 0x00014c4c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_edpi_cmd_size) - i.drv_dsi_tx_get_cmd_status 0x00014c50 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) - i.drv_dsi_tx_mode 0x00014c54 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_mode) - i.drv_dsi_tx_phy_clock_lane_auto_lp 0x00014c58 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp) - i.drv_dsi_tx_phy_clock_lane_req_hs 0x00014c70 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs) - i.drv_dsi_tx_phy_lane_mode 0x00014c8a Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_lane_mode) - i.drv_dsi_tx_phy_status_ready 0x00014c96 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready) - i.drv_dsi_tx_phy_status_stopstate 0x00014cfa Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) - i.drv_dsi_tx_phy_test_setup 0x00014d38 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) - i.drv_dsi_tx_phy_time_cfg 0x00014e6c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg) - i.drv_dsi_tx_powerup 0x00014e8a Section 0 drv_dsi_tx.o(i.drv_dsi_tx_powerup) - i.drv_dsi_tx_response_mode 0x00014e92 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_response_mode) - i.drv_dsi_tx_set_bta_ack 0x00014eae Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_bta_ack) - i.drv_dsi_tx_set_esc_div 0x00014ec6 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) - i.drv_dsi_tx_set_int 0x00014ed4 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_int) - i.drv_dsi_tx_set_time_out_div 0x00014f14 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_time_out_div) - i.drv_dsi_tx_set_video_chunk 0x00014f24 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_video_chunk) - i.drv_dsi_tx_set_video_timing 0x00014f2c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_video_timing) - i.drv_dsi_tx_shutdown 0x00014f4e Section 0 drv_dsi_tx.o(i.drv_dsi_tx_shutdown) - i.drv_dsi_tx_timeout_cfg 0x00014f56 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_timeout_cfg) - i.drv_dsi_tx_video_mode_cfg 0x00014f7c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_cfg) - i.drv_dsi_tx_video_mode_disable_hact_cmd 0x00015026 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_disable_hact_cmd) - i.drv_dsi_tx_video_mode_set_lp_cmd 0x0001503c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_set_lp_cmd) - i.drv_efuse_enter_inactive 0x00015054 Section 0 drv_efuse.o(i.drv_efuse_enter_inactive) - i.drv_efuse_int_enable 0x00015082 Section 0 drv_efuse.o(i.drv_efuse_int_enable) - i.drv_efuse_read 0x0001508e Section 0 drv_efuse.o(i.drv_efuse_read) - i.drv_efuse_read_req 0x000150c0 Section 0 drv_efuse.o(i.drv_efuse_read_req) - i.drv_gpio_set_ioe 0x000150d8 Section 0 drv_gpio.o(i.drv_gpio_set_ioe) - i.drv_gpio_set_mode0 0x000150f8 Section 0 drv_gpio.o(i.drv_gpio_set_mode0) - i.drv_gpio_set_mode1 0x00015108 Section 0 drv_gpio.o(i.drv_gpio_set_mode1) - i.drv_gpio_set_mode2 0x00015118 Section 0 drv_gpio.o(i.drv_gpio_set_mode2) - i.drv_gpio_set_mode3 0x00015128 Section 0 drv_gpio.o(i.drv_gpio_set_mode3) - i.drv_gpio_set_output_data 0x00015138 Section 0 hal_gpio.o(i.drv_gpio_set_output_data) - drv_gpio_set_output_data 0x00015139 Thumb Code 26 hal_gpio.o(i.drv_gpio_set_output_data) - i.drv_lcdc_config_bypass 0x00015158 Section 0 drv_lcdc.o(i.drv_lcdc_config_bypass) - i.drv_lcdc_config_ccm 0x00015170 Section 0 drv_lcdc.o(i.drv_lcdc_config_ccm) - i.drv_lcdc_config_disp_mode 0x000151a0 Section 0 drv_lcdc.o(i.drv_lcdc_config_disp_mode) - i.drv_lcdc_config_dpi_polarity 0x000151b6 Section 0 drv_lcdc.o(i.drv_lcdc_config_dpi_polarity) - i.drv_lcdc_config_dpi_timing 0x000151da Section 0 drv_lcdc.o(i.drv_lcdc_config_dpi_timing) - i.drv_lcdc_config_edpi_mode 0x00015200 Section 0 drv_lcdc.o(i.drv_lcdc_config_edpi_mode) - i.drv_lcdc_config_endianness 0x00015216 Section 0 drv_lcdc.o(i.drv_lcdc_config_endianness) - i.drv_lcdc_config_input_size 0x0001522c Section 0 drv_lcdc.o(i.drv_lcdc_config_input_size) - i.drv_lcdc_config_int 0x00015238 Section 0 drv_lcdc.o(i.drv_lcdc_config_int) - i.drv_lcdc_config_int_single 0x00015256 Section 0 drv_lcdc.o(i.drv_lcdc_config_int_single) - i.drv_lcdc_config_overwrite 0x00015278 Section 0 drv_lcdc.o(i.drv_lcdc_config_overwrite) - i.drv_lcdc_config_overwrite_rgb 0x0001529a Section 0 drv_lcdc.o(i.drv_lcdc_config_overwrite_rgb) - i.drv_lcdc_config_partial_display_area 0x000152a6 Section 0 drv_lcdc.o(i.drv_lcdc_config_partial_display_area) - i.drv_lcdc_config_partial_display_enable 0x000152c0 Section 0 drv_lcdc.o(i.drv_lcdc_config_partial_display_enable) - i.drv_lcdc_config_scale_up_coef 0x000152e2 Section 0 drv_lcdc.o(i.drv_lcdc_config_scale_up_coef) - i.drv_lcdc_config_scale_up_step 0x000152fc Section 0 drv_lcdc.o(i.drv_lcdc_config_scale_up_step) - i.drv_lcdc_config_src_parameter 0x00015308 Section 0 drv_lcdc.o(i.drv_lcdc_config_src_parameter) - i.drv_lcdc_config_thresh 0x00015354 Section 0 drv_lcdc.o(i.drv_lcdc_config_thresh) - i.drv_lcdc_ctrl_flow 0x0001535a Section 0 drv_lcdc.o(i.drv_lcdc_ctrl_flow) - i.drv_lcdc_enable_shadow_reg 0x0001536c Section 0 drv_lcdc.o(i.drv_lcdc_enable_shadow_reg) - i.drv_lcdc_set_int 0x0001538c Section 0 drv_lcdc.o(i.drv_lcdc_set_int) - i.drv_lcdc_set_prefetch 0x000153cc Section 0 drv_lcdc.o(i.drv_lcdc_set_prefetch) - i.drv_lcdc_set_video_hw_mode 0x000153e4 Section 0 drv_lcdc.o(i.drv_lcdc_set_video_hw_mode) - i.drv_lcdc_start 0x000153f8 Section 0 drv_lcdc.o(i.drv_lcdc_start) - i.drv_memc_clear_status 0x00015418 Section 0 drv_memc.o(i.drv_memc_clear_status) - i.drv_memc_enable_irq 0x00015424 Section 0 drv_memc.o(i.drv_memc_enable_irq) - i.drv_memc_gen_a_tear_signal 0x00015464 Section 0 drv_memc.o(i.drv_memc_gen_a_tear_signal) - i.drv_memc_get_status 0x00015470 Section 0 drv_memc.o(i.drv_memc_get_status) - i.drv_memc_rate_transfer_sel 0x00015482 Section 0 drv_memc.o(i.drv_memc_rate_transfer_sel) - i.drv_memc_sel_vsync 0x00015492 Section 0 drv_memc.o(i.drv_memc_sel_vsync) - i.drv_memc_set_active_height 0x000154a0 Section 0 drv_memc.o(i.drv_memc_set_active_height) - i.drv_memc_set_data_mode 0x000154b4 Section 0 drv_memc.o(i.drv_memc_set_data_mode) - i.drv_memc_set_double_buffer 0x000154c0 Section 0 drv_memc.o(i.drv_memc_set_double_buffer) - i.drv_memc_set_double_buffer_reverse 0x000154d0 Section 0 drv_memc.o(i.drv_memc_set_double_buffer_reverse) - i.drv_memc_set_fs_en_conditions 0x000154e2 Section 0 drv_memc.o(i.drv_memc_set_fs_en_conditions) - i.drv_memc_set_inten 0x000154f2 Section 0 drv_memc.o(i.drv_memc_set_inten) - i.drv_memc_set_lcdc_st_conditions 0x00015508 Section 0 drv_memc.o(i.drv_memc_set_lcdc_st_conditions) - i.drv_memc_set_ltpo_mode 0x00015520 Section 0 drv_memc.o(i.drv_memc_set_ltpo_mode) - i.drv_memc_set_tear_mode 0x0001553a Section 0 drv_memc.o(i.drv_memc_set_tear_mode) - i.drv_memc_set_tear_waveform 0x00015548 Section 0 drv_memc.o(i.drv_memc_set_tear_waveform) - i.drv_memc_set_vidc_sync_cnt 0x00015570 Section 0 drv_memc.o(i.drv_memc_set_vidc_sync_cnt) - i.drv_param_init_get_ccm 0x00015580 Section 0 drv_param_init.o(i.drv_param_init_get_ccm) - i.drv_param_init_get_scld_filter_h 0x00015588 Section 0 drv_param_init.o(i.drv_param_init_get_scld_filter_h) - i.drv_param_init_get_scld_filter_v 0x0001559c Section 0 drv_param_init.o(i.drv_param_init_get_scld_filter_v) - i.drv_param_init_get_sclu_filter 0x000155b0 Section 0 drv_param_init.o(i.drv_param_init_get_sclu_filter) - i.drv_param_init_set_ccm 0x000155b8 Section 0 drv_param_init.o(i.drv_param_init_set_ccm) - i.drv_param_init_set_scld_filter 0x000155cc Section 0 drv_param_init.o(i.drv_param_init_set_scld_filter) - i.drv_param_p2r_filter_init 0x00015630 Section 0 drv_param_init.o(i.drv_param_p2r_filter_init) - i.drv_phy_enable_calibration 0x00015654 Section 0 drv_phy_common.o(i.drv_phy_enable_calibration) - i.drv_phy_get_calibration 0x00015664 Section 0 drv_phy_common.o(i.drv_phy_get_calibration) - i.drv_phy_get_pll_para 0x000156a0 Section 0 drv_phy_common.o(i.drv_phy_get_pll_para) - i.drv_phy_get_rate_para 0x00015700 Section 0 drv_phy_common.o(i.drv_phy_get_rate_para) - i.drv_phy_test_clear 0x00015754 Section 0 drv_phy_common.o(i.drv_phy_test_clear) - i.drv_phy_test_lock 0x00015764 Section 0 drv_phy_common.o(i.drv_phy_test_lock) - i.drv_phy_test_write_1_byte 0x0001577c Section 0 drv_phy_common.o(i.drv_phy_test_write_1_byte) - i.drv_phy_test_write_2_byte 0x0001579c Section 0 drv_phy_common.o(i.drv_phy_test_write_2_byte) - i.drv_phy_test_write_code 0x000157c2 Section 0 drv_phy_common.o(i.drv_phy_test_write_code) - i.drv_phy_test_write_data 0x000157e0 Section 0 drv_phy_common.o(i.drv_phy_test_write_data) - drv_phy_test_write_data 0x000157e1 Thumb Code 32 drv_phy_common.o(i.drv_phy_test_write_data) - i.drv_pwr_set_pvd_mode 0x00015800 Section 0 drv_pwr.o(i.drv_pwr_set_pvd_mode) - i.drv_pwr_set_system_clk_src 0x00015818 Section 0 drv_pwr.o(i.drv_pwr_set_system_clk_src) - i.drv_rx_phy_test_clear 0x00015850 Section 0 drv_dsi_rx.o(i.drv_rx_phy_test_clear) - drv_rx_phy_test_clear 0x00015851 Thumb Code 12 drv_dsi_rx.o(i.drv_rx_phy_test_clear) - i.drv_rx_phy_test_lock 0x0001585c Section 0 drv_dsi_rx.o(i.drv_rx_phy_test_lock) - drv_rx_phy_test_lock 0x0001585d Thumb Code 16 drv_dsi_rx.o(i.drv_rx_phy_test_lock) - i.drv_rx_phy_test_write_1_byte 0x0001586c Section 0 drv_dsi_rx.o(i.drv_rx_phy_test_write_1_byte) - drv_rx_phy_test_write_1_byte 0x0001586d Thumb Code 20 drv_dsi_rx.o(i.drv_rx_phy_test_write_1_byte) - i.drv_rx_phy_test_write_2_byte 0x00015880 Section 0 drv_dsi_rx.o(i.drv_rx_phy_test_write_2_byte) - drv_rx_phy_test_write_2_byte 0x00015881 Thumb Code 22 drv_dsi_rx.o(i.drv_rx_phy_test_write_2_byte) - i.drv_rxbr_clear_pkt_buffer 0x00015896 Section 0 drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) - i.drv_rxbr_clear_status0 0x000158a0 Section 0 drv_rxbr.o(i.drv_rxbr_clear_status0) - i.drv_rxbr_enable_irq 0x000158a4 Section 0 drv_rxbr.o(i.drv_rxbr_enable_irq) - i.drv_rxbr_frame_drop_cfg 0x00015900 Section 0 drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) - i.drv_rxbr_get_clk 0x00015914 Section 0 drv_rxbr.o(i.drv_rxbr_get_clk) - i.drv_rxbr_get_col_addr 0x00015978 Section 0 drv_rxbr.o(i.drv_rxbr_get_col_addr) - i.drv_rxbr_get_int_source 0x0001597c Section 0 hal_internal_vsync.o(i.drv_rxbr_get_int_source) - drv_rxbr_get_int_source 0x0001597d Thumb Code 18 hal_internal_vsync.o(i.drv_rxbr_get_int_source) - i.drv_rxbr_get_page_addr 0x0001598e Section 0 drv_rxbr.o(i.drv_rxbr_get_page_addr) - i.drv_rxbr_get_pkt_buf_error_status 0x00015992 Section 0 drv_rxbr.o(i.drv_rxbr_get_pkt_buf_error_status) - i.drv_rxbr_get_status0 0x0001599e Section 0 hal_internal_vsync.o(i.drv_rxbr_get_status0) - drv_rxbr_get_status0 0x0001599f Thumb Code 18 hal_internal_vsync.o(i.drv_rxbr_get_status0) - i.drv_rxbr_get_status1 0x000159b0 Section 0 hal_internal_vsync.o(i.drv_rxbr_get_status1) - drv_rxbr_get_status1 0x000159b1 Thumb Code 22 hal_internal_vsync.o(i.drv_rxbr_get_status1) - i.drv_rxbr_hline_rcv0_cfg 0x000159c6 Section 0 drv_rxbr.o(i.drv_rxbr_hline_rcv0_cfg) - i.drv_rxbr_hline_rcv1_cfg 0x000159d2 Section 0 drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg) - i.drv_rxbr_hline_rcv_cfg 0x000159de Section 0 drv_rxbr.o(i.drv_rxbr_hline_rcv_cfg) - i.drv_rxbr_register_irq0_callback 0x000159e8 Section 0 drv_rxbr.o(i.drv_rxbr_register_irq0_callback) - i.drv_rxbr_register_irq1_callback 0x000159f4 Section 0 drv_rxbr.o(i.drv_rxbr_register_irq1_callback) - i.drv_rxbr_set_ack_pkt_header 0x00015a00 Section 0 drv_rxbr.o(i.drv_rxbr_set_ack_pkt_header) - i.drv_rxbr_set_color_format 0x00015a14 Section 0 drv_rxbr.o(i.drv_rxbr_set_color_format) - i.drv_rxbr_set_filter_regs 0x00015a28 Section 0 drv_rxbr.o(i.drv_rxbr_set_filter_regs) - i.drv_rxbr_set_inten 0x00015a3a Section 0 drv_rxbr.o(i.drv_rxbr_set_inten) - i.drv_rxbr_set_ltpo_drop_th 0x00015a4e Section 0 drv_rxbr.o(i.drv_rxbr_set_ltpo_drop_th) - i.drv_rxbr_set_usr_cfg 0x00015a5e Section 0 drv_rxbr.o(i.drv_rxbr_set_usr_cfg) - i.drv_rxbr_set_usr_col 0x00015a84 Section 0 drv_rxbr.o(i.drv_rxbr_set_usr_col) - i.drv_rxbr_set_usr_row 0x00015a8c Section 0 drv_rxbr.o(i.drv_rxbr_set_usr_row) - i.drv_swire_set_int 0x00015a94 Section 0 drv_swire.o(i.drv_swire_set_int) - i.drv_sys_cfg_clear_all_int 0x00015ae8 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_clear_all_int) - i.drv_sys_cfg_clear_pending 0x00015af4 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) - i.drv_sys_cfg_sel_ap_rst_lvl_trig 0x00015b1c Section 0 drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_lvl_trig) - i.drv_sys_cfg_set_int 0x00015b34 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_set_int) - i.drv_timer_clear_status_flags 0x00015b58 Section 0 drv_timer.o(i.drv_timer_clear_status_flags) - drv_timer_clear_status_flags 0x00015b59 Thumb Code 26 drv_timer.o(i.drv_timer_clear_status_flags) - i.drv_timer_enable 0x00015b72 Section 0 drv_timer.o(i.drv_timer_enable) - i.drv_timer_get_instance 0x00015b94 Section 0 drv_timer.o(i.drv_timer_get_instance) - i.drv_timer_handle_interrupt 0x00015ba4 Section 0 drv_timer.o(i.drv_timer_handle_interrupt) - drv_timer_handle_interrupt 0x00015ba5 Thumb Code 62 drv_timer.o(i.drv_timer_handle_interrupt) - i.drv_timer_set_compare_val 0x00015be8 Section 0 drv_timer.o(i.drv_timer_set_compare_val) - i.drv_timer_set_int 0x00015bf8 Section 0 drv_timer.o(i.drv_timer_set_int) - i.drv_tx_phy_test_clear 0x00015c4c Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_clear) - drv_tx_phy_test_clear 0x00015c4d Thumb Code 10 drv_dsi_tx.o(i.drv_tx_phy_test_clear) - i.drv_tx_phy_test_enter 0x00015c56 Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_enter) - i.drv_tx_phy_test_exit 0x00015c72 Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_exit) - i.drv_tx_phy_test_write_1_byte 0x00015c8e Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_write_1_byte) - drv_tx_phy_test_write_1_byte 0x00015c8f Thumb Code 18 drv_dsi_tx.o(i.drv_tx_phy_test_write_1_byte) - i.drv_tx_phy_test_write_2_byte 0x00015ca0 Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_write_2_byte) - drv_tx_phy_test_write_2_byte 0x00015ca1 Thumb Code 20 drv_dsi_tx.o(i.drv_tx_phy_test_write_2_byte) - i.drv_tx_phy_test_write_code 0x00015cb4 Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_write_code) - drv_tx_phy_test_write_code 0x00015cb5 Thumb Code 16 drv_dsi_tx.o(i.drv_tx_phy_test_write_code) - i.drv_vidc_clear_irq 0x00015cc4 Section 0 drv_vidc.o(i.drv_vidc_clear_irq) - i.drv_vidc_enable 0x00015ccc Section 0 drv_vidc.o(i.drv_vidc_enable) - i.drv_vidc_enable_irq 0x00015ce4 Section 0 drv_vidc.o(i.drv_vidc_enable_irq) - i.drv_vidc_get_irq_status 0x00015d24 Section 0 drv_vidc.o(i.drv_vidc_get_irq_status) - i.drv_vidc_init_module_enable 0x00015d38 Section 0 drv_vidc.o(i.drv_vidc_init_module_enable) - i.drv_vidc_register_callback 0x00015d60 Section 0 drv_vidc.o(i.drv_vidc_register_callback) - i.drv_vidc_reset 0x00015d6c Section 0 drv_vidc.o(i.drv_vidc_reset) - i.drv_vidc_set_dst_parameter 0x00015d72 Section 0 drv_vidc.o(i.drv_vidc_set_dst_parameter) - i.drv_vidc_set_irqen 0x00015dae Section 0 drv_vidc.o(i.drv_vidc_set_irqen) - i.drv_vidc_set_mirror 0x00015dc2 Section 0 drv_vidc.o(i.drv_vidc_set_mirror) - i.drv_vidc_set_p2r_hcoef0 0x00015dd2 Section 0 drv_vidc.o(i.drv_vidc_set_p2r_hcoef0) - i.drv_vidc_set_p2r_hinitb 0x00015dda Section 0 drv_vidc.o(i.drv_vidc_set_p2r_hinitb) - i.drv_vidc_set_p2r_hinitr 0x00015e00 Section 0 drv_vidc.o(i.drv_vidc_set_p2r_hinitr) - i.drv_vidc_set_pentile_swap 0x00015e28 Section 0 drv_vidc.o(i.drv_vidc_set_pentile_swap) - i.drv_vidc_set_pu_ctrl 0x00015e40 Section 0 drv_vidc.o(i.drv_vidc_set_pu_ctrl) - i.drv_vidc_set_rotation 0x00015e4a Section 0 drv_vidc.o(i.drv_vidc_set_rotation) - i.drv_vidc_set_scld_hcoef0 0x00015e5a Section 0 drv_vidc.o(i.drv_vidc_set_scld_hcoef0) - i.drv_vidc_set_scld_hcoef1 0x00015e64 Section 0 drv_vidc.o(i.drv_vidc_set_scld_hcoef1) - i.drv_vidc_set_scld_step 0x00015e6e Section 0 drv_vidc.o(i.drv_vidc_set_scld_step) - i.drv_vidc_set_scld_vcoef0 0x00015e80 Section 0 drv_vidc.o(i.drv_vidc_set_scld_vcoef0) - i.drv_vidc_set_scld_vcoef1 0x00015e8a Section 0 drv_vidc.o(i.drv_vidc_set_scld_vcoef1) - i.drv_vidc_set_src_parameter 0x00015e94 Section 0 drv_vidc.o(i.drv_vidc_set_src_parameter) - i.drv_wdg_clear_counter 0x00015eac Section 0 drv_wdg.o(i.drv_wdg_clear_counter) - i.drv_wdg_clear_edge_flag 0x00015ebc Section 0 drv_wdg.o(i.drv_wdg_clear_edge_flag) - drv_wdg_clear_edge_flag 0x00015ebd Thumb Code 12 drv_wdg.o(i.drv_wdg_clear_edge_flag) - i.drv_wdg_read_edge_flag 0x00015ecc Section 0 drv_wdg.o(i.drv_wdg_read_edge_flag) - drv_wdg_read_edge_flag 0x00015ecd Thumb Code 10 drv_wdg.o(i.drv_wdg_read_edge_flag) - i.drv_wdg_set_int 0x00015edc Section 0 drv_wdg.o(i.drv_wdg_set_int) - i.fls_clr_interrupt_flag 0x00015f1c Section 0 drv_fls.o(i.fls_clr_interrupt_flag) - i.fputc 0x00015f26 Section 0 tau_log.o(i.fputc) - i.frame_start_cb 0x00015f3c Section 0 ap_demo.o(i.frame_start_cb) - frame_start_cb 0x00015f3d Thumb Code 38 ap_demo.o(i.frame_start_cb) - i.hal_dsi_rx_ctrl_create_handle 0x00015f8c Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) - i.hal_dsi_rx_ctrl_dsc_async_handler 0x00015fc0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dsc_async_handler) - i.hal_dsi_rx_ctrl_gen_a_tear_signal 0x00015fe8 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_gen_a_tear_signal) - i.hal_dsi_rx_ctrl_get_max_ret_size 0x00016010 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) - i.hal_dsi_rx_ctrl_init 0x00016038 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) - i.hal_dsi_rx_ctrl_init_clk 0x000160d0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) - hal_dsi_rx_ctrl_init_clk 0x000160d1 Thumb Code 332 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) - i.hal_dsi_rx_ctrl_init_dsi_rx 0x00016274 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) - hal_dsi_rx_ctrl_init_dsi_rx 0x00016275 Thumb Code 184 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) - i.hal_dsi_rx_ctrl_init_memc 0x0001634c Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) - hal_dsi_rx_ctrl_init_memc 0x0001634d Thumb Code 342 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) - i.hal_dsi_rx_ctrl_init_rxbr 0x000164ac Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) - hal_dsi_rx_ctrl_init_rxbr 0x000164ad Thumb Code 320 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) - i.hal_dsi_rx_ctrl_init_vidc 0x000165fc Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) - hal_dsi_rx_ctrl_init_vidc 0x000165fd Thumb Code 544 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) - i.hal_dsi_rx_ctrl_pre_init_pps 0x00016828 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) - i.hal_dsi_rx_ctrl_restart 0x00016864 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) - i.hal_dsi_rx_ctrl_send_ack_cmd 0x000168b4 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) - i.hal_dsi_rx_ctrl_set_cus_esc_clk 0x000169a4 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk) - i.hal_dsi_rx_ctrl_set_cus_scld_filter 0x000169d0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_scld_filter) - i.hal_dsi_rx_ctrl_set_cus_sync_line 0x00016a3c Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_sync_line) - i.hal_dsi_rx_ctrl_set_ipi_cfg 0x00016a70 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) - hal_dsi_rx_ctrl_set_ipi_cfg 0x00016a71 Thumb Code 50 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) - i.hal_dsi_rx_ctrl_set_rxbr_clk 0x00016aa8 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rxbr_clk) - hal_dsi_rx_ctrl_set_rxbr_clk 0x00016aa9 Thumb Code 114 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rxbr_clk) - i.hal_dsi_rx_ctrl_set_tear_mode_ex 0x00016b1a Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_tear_mode_ex) - i.hal_dsi_rx_ctrl_start 0x00016b28 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) - i.hal_dsi_rx_ctrl_toggle_resolution 0x00016b64 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) - i.hal_dsi_tx_calc_video_chunks 0x00016b84 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_calc_video_chunks) - hal_dsi_tx_calc_video_chunks 0x00016b85 Thumb Code 384 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_calc_video_chunks) - i.hal_dsi_tx_config_params_for_lane_rate 0x00016d14 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_config_params_for_lane_rate) - hal_dsi_tx_config_params_for_lane_rate 0x00016d15 Thumb Code 42 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_config_params_for_lane_rate) - i.hal_dsi_tx_count_lane_rate 0x00016d48 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_count_lane_rate) - hal_dsi_tx_count_lane_rate 0x00016d49 Thumb Code 982 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_count_lane_rate) - i.hal_dsi_tx_ctrl_create_handle 0x00017170 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) - i.hal_dsi_tx_ctrl_enter_init_panel_mode 0x0001719c Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_enter_init_panel_mode) - i.hal_dsi_tx_ctrl_exit_init_panel_mode 0x000171e8 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_exit_init_panel_mode) - i.hal_dsi_tx_ctrl_init 0x00017210 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) - i.hal_dsi_tx_ctrl_init_clk 0x000172b4 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) - hal_dsi_tx_ctrl_init_clk 0x000172b5 Thumb Code 36 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) - i.hal_dsi_tx_ctrl_panel_reset_pin 0x000172d8 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_panel_reset_pin) - i.hal_dsi_tx_ctrl_set_ccm 0x000172e4 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_ccm) - i.hal_dsi_tx_ctrl_set_overwrite_rgb 0x00017304 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb) - i.hal_dsi_tx_ctrl_set_partial_disp 0x00017318 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_partial_disp) - i.hal_dsi_tx_ctrl_set_partial_disp_area 0x00017328 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_partial_disp_area) - i.hal_dsi_tx_ctrl_start 0x0001734c Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) - i.hal_dsi_tx_ctrl_write_array_cmd 0x000173f4 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) - i.hal_dsi_tx_ctrl_write_cmd 0x000174e4 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) - i.hal_dsi_tx_init_data_mode 0x000175b0 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_data_mode) - hal_dsi_tx_init_data_mode 0x000175b1 Thumb Code 58 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_data_mode) - i.hal_dsi_tx_init_dpi_cfg 0x000175f4 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_cfg) - hal_dsi_tx_init_dpi_cfg 0x000175f5 Thumb Code 42 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_cfg) - i.hal_dsi_tx_init_interrupt 0x00017624 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_interrupt) - hal_dsi_tx_init_interrupt 0x00017625 Thumb Code 28 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_interrupt) - i.hal_dsi_tx_init_phy_cfg 0x00017644 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) - hal_dsi_tx_init_phy_cfg 0x00017645 Thumb Code 28 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) - i.hal_dsi_tx_init_remains 0x00017664 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_remains) - hal_dsi_tx_init_remains 0x00017665 Thumb Code 142 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_remains) - i.hal_dsi_tx_init_video_mode 0x000176f8 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_video_mode) - hal_dsi_tx_init_video_mode 0x000176f9 Thumb Code 82 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_video_mode) - i.hal_dsi_tx_send_cmd 0x00017750 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) - hal_dsi_tx_send_cmd 0x00017751 Thumb Code 60 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) - i.hal_gpio_init_output 0x00017794 Section 0 hal_gpio.o(i.hal_gpio_init_output) - i.hal_gpio_set_mode 0x000177bc Section 0 hal_gpio.o(i.hal_gpio_set_mode) - i.hal_gpio_set_output_data 0x0001781c Section 0 hal_gpio.o(i.hal_gpio_set_output_data) - i.hal_internal_check_video_auto_sync 0x00017824 Section 0 hal_internal_vsync.o(i.hal_internal_check_video_auto_sync) - i.hal_internal_init_memc 0x0001783c Section 0 hal_internal_vsync.o(i.hal_internal_init_memc) - i.hal_internal_rx_dcs_async_handler 0x00017938 Section 0 hal_internal_vsync.o(i.hal_internal_rx_dcs_async_handler) - i.hal_internal_rx_dcs_polling 0x00017964 Section 0 hal_internal_vsync.o(i.hal_internal_rx_dcs_polling) - i.hal_internal_sync_get_fb_setting 0x000179bc Section 0 hal_internal_vsync.o(i.hal_internal_sync_get_fb_setting) - i.hal_internal_sync_get_hight_performan_mode 0x000179cc Section 0 hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) - i.hal_internal_sync_input_resolution_change 0x000179dc Section 0 hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) - i.hal_internal_vsync_deinit 0x00017c08 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_deinit) - i.hal_internal_vsync_get_sync_line 0x00017c30 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) - i.hal_internal_vsync_get_tear_mode 0x00017c48 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_get_tear_mode) - i.hal_internal_vsync_get_tx_state 0x00017c54 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) - i.hal_internal_vsync_init_rx 0x00017c60 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_init_rx) - i.hal_internal_vsync_init_tx 0x00017da0 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_init_tx) - i.hal_internal_vsync_set_auto_hw_filter 0x00017e50 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_auto_hw_filter) - i.hal_internal_vsync_set_rx_state 0x00017ee0 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) - i.hal_internal_vsync_set_sync_line 0x00017f04 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) - i.hal_internal_vsync_set_tear_mode 0x00017f48 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) - i.hal_internal_vsync_set_tx_state 0x00017f98 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) - i.hal_intl_svs_deinit_tx 0x0001801c Section 0 hal_internal_soft_sync.o(i.hal_intl_svs_deinit_tx) - i.hal_intl_svs_handle 0x0001802c Section 0 hal_internal_soft_sync.o(i.hal_intl_svs_handle) - i.hal_intl_svs_init_rx 0x00018050 Section 0 hal_internal_soft_sync.o(i.hal_intl_svs_init_rx) - i.hal_intl_svs_init_tx 0x000180c8 Section 0 hal_internal_soft_sync.o(i.hal_intl_svs_init_tx) - i.hal_intl_svs_set_sync_coef 0x000180dc Section 0 hal_internal_soft_sync.o(i.hal_intl_svs_set_sync_coef) - i.hal_intl_svs_update_rxbr_clk 0x000180e8 Section 0 hal_internal_soft_sync.o(i.hal_intl_svs_update_rxbr_clk) - i.hal_lcdc_config_ccm 0x00018130 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_ccm) - hal_lcdc_config_ccm 0x00018131 Thumb Code 30 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_ccm) - i.hal_lcdc_config_remains 0x00018154 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_remains) - hal_lcdc_config_remains 0x00018155 Thumb Code 94 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_remains) - i.hal_lcdc_config_rgb_to_pentile 0x000181b8 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_rgb_to_pentile) - hal_lcdc_config_rgb_to_pentile 0x000181b9 Thumb Code 14 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_rgb_to_pentile) - i.hal_lcdc_config_upscaler 0x000181cc Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_upscaler) - hal_lcdc_config_upscaler 0x000181cd Thumb Code 348 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_upscaler) - i.hal_lcdc_init_cfg 0x00018330 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) - hal_lcdc_init_cfg 0x00018331 Thumb Code 78 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) - i.hal_lcdc_init_clk 0x00018384 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) - hal_lcdc_init_clk 0x00018385 Thumb Code 446 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) - i.hal_lcdc_init_interrupt 0x00018550 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_interrupt) - hal_lcdc_init_interrupt 0x00018551 Thumb Code 58 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_interrupt) - i.hal_system_enable_systick 0x00018590 Section 0 hal_system.o(i.hal_system_enable_systick) - i.hal_system_init 0x00018598 Section 0 hal_system.o(i.hal_system_init) - i.hal_system_init_console 0x00018620 Section 0 hal_system.o(i.hal_system_init_console) - i.hal_system_set_phy_calibration 0x0001863c Section 0 hal_system.o(i.hal_system_set_phy_calibration) - i.hal_tx_frame_rate_adjust 0x00018644 Section 0 hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) - hal_tx_frame_rate_adjust 0x00018645 Thumb Code 44 hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) - i.hal_uart_init 0x00018674 Section 0 hal_uart.o(i.hal_uart_init) - i.hal_uart_transmit_blocking 0x00018700 Section 0 hal_uart.o(i.hal_uart_transmit_blocking) - i.handle_init 0x00018710 Section 0 irq_redirect .o(i.handle_init) - i.init_mipi_tx 0x00018820 Section 0 ap_demo.o(i.init_mipi_tx) - init_mipi_tx 0x00018821 Thumb Code 100 ap_demo.o(i.init_mipi_tx) - i.init_panel 0x0001888c Section 0 ap_demo.o(i.init_panel) - init_panel 0x0001888d Thumb Code 150 ap_demo.o(i.init_panel) - i.main 0x0001892c Section 0 main.o(i.main) - i.open_mipi_rx 0x00018938 Section 0 ap_demo.o(i.open_mipi_rx) - open_mipi_rx 0x00018939 Thumb Code 170 ap_demo.o(i.open_mipi_rx) - i.pps_update_handle 0x00018a0c Section 0 ap_demo.o(i.pps_update_handle) - pps_update_handle 0x00018a0d Thumb Code 78 ap_demo.o(i.pps_update_handle) - i.rx_get_dcs_packet_data 0x00018aa8 Section 0 hal_internal_vsync.o(i.rx_get_dcs_packet_data) - rx_get_dcs_packet_data 0x00018aa9 Thumb Code 654 hal_internal_vsync.o(i.rx_get_dcs_packet_data) - i.rx_partial_update 0x00018e9c Section 0 hal_internal_vsync.o(i.rx_partial_update) - rx_partial_update 0x00018e9d Thumb Code 348 hal_internal_vsync.o(i.rx_partial_update) - i.rx_receive_packet 0x00019008 Section 0 hal_internal_vsync.o(i.rx_receive_packet) - rx_receive_packet 0x00019009 Thumb Code 126 hal_internal_vsync.o(i.rx_receive_packet) - i.rx_receive_pps 0x00019094 Section 0 hal_internal_vsync.o(i.rx_receive_pps) - rx_receive_pps 0x00019095 Thumb Code 268 hal_internal_vsync.o(i.rx_receive_pps) - i.rxbr_irq0_callback 0x00019214 Section 0 hal_internal_vsync.o(i.rxbr_irq0_callback) - rxbr_irq0_callback 0x00019215 Thumb Code 192 hal_internal_vsync.o(i.rxbr_irq0_callback) - i.rxbr_irq1_callback 0x000192e0 Section 0 hal_internal_vsync.o(i.rxbr_irq1_callback) - rxbr_irq1_callback 0x000192e1 Thumb Code 392 hal_internal_vsync.o(i.rxbr_irq1_callback) - i.soft_gen_te 0x00019524 Section 0 hal_internal_vsync.o(i.soft_gen_te) - soft_gen_te 0x00019525 Thumb Code 166 hal_internal_vsync.o(i.soft_gen_te) - i.soft_gen_te_double_buffer 0x000195e8 Section 0 hal_internal_vsync.o(i.soft_gen_te_double_buffer) - soft_gen_te_double_buffer 0x000195e9 Thumb Code 166 hal_internal_vsync.o(i.soft_gen_te_double_buffer) - i.sqrt 0x000196a8 Section 0 sqrt.o(i.sqrt) - i.svs_direct_mode_setting 0x000196f0 Section 0 hal_internal_soft_sync.o(i.svs_direct_mode_setting) - svs_direct_mode_setting 0x000196f1 Thumb Code 156 hal_internal_soft_sync.o(i.svs_direct_mode_setting) - i.svs_get_rel_intv 0x0001979c Section 0 hal_internal_soft_sync.o(i.svs_get_rel_intv) - svs_get_rel_intv 0x0001979d Thumb Code 20 hal_internal_soft_sync.o(i.svs_get_rel_intv) - i.svs_sync_handle 0x000197b8 Section 0 hal_internal_soft_sync.o(i.svs_sync_handle) - svs_sync_handle 0x000197b9 Thumb Code 158 hal_internal_soft_sync.o(i.svs_sync_handle) - i.svs_wait_start 0x00019868 Section 0 hal_internal_soft_sync.o(i.svs_wait_start) - svs_wait_start 0x00019869 Thumb Code 224 hal_internal_soft_sync.o(i.svs_wait_start) - i.svs_waite_fr_stab 0x0001995c Section 0 hal_internal_soft_sync.o(i.svs_waite_fr_stab) - svs_waite_fr_stab 0x0001995d Thumb Code 148 hal_internal_soft_sync.o(i.svs_waite_fr_stab) - i.vidc_callback 0x00019a34 Section 0 hal_internal_vsync.o(i.vidc_callback) - vidc_callback 0x00019a35 Thumb Code 234 hal_internal_vsync.o(i.vidc_callback) - i.vpre_err_reset 0x00019b3c Section 0 hal_internal_vsync.o(i.vpre_err_reset) - vpre_err_reset 0x00019b3d Thumb Code 192 hal_internal_vsync.o(i.vpre_err_reset) - i.vsync_set_te_mode 0x00019c14 Section 0 hal_internal_vsync.o(i.vsync_set_te_mode) - vsync_set_te_mode 0x00019c15 Thumb Code 300 hal_internal_vsync.o(i.vsync_set_te_mode) - .constdata 0x00019de0 Section 8052 ap_demo.o(.constdata) - g_cus_rx_dcs_execute_table 0x00019de0 Data 108 ap_demo.o(.constdata) - .constdata 0x0001bd54 Section 210 hal_gpio.o(.constdata) - s_gpio_map 0x0001bd54 Data 120 hal_gpio.o(.constdata) - s_gpio_perf 0x0001bdcc Data 90 hal_gpio.o(.constdata) - .constdata 0x0001be28 Section 8 drv_param_init.o(.constdata) - .constdata 0x0001be30 Section 390 drv_phy_common.o(.constdata) - phy_para_mapping_h 0x0001be30 Data 184 drv_phy_common.o(.constdata) - phy_para_mapping_l 0x0001bee8 Data 128 drv_phy_common.o(.constdata) - phy_data_high_map 0x0001bf68 Data 48 drv_phy_common.o(.constdata) - phy_data_lp_map 0x0001bf98 Data 30 drv_phy_common.o(.constdata) - .conststring 0x0001bfb8 Section 72 hal_dsi_rx_ctrl.o(.conststring) - .conststring 0x0001c000 Section 67 hal_dsi_tx_ctrl.o(.conststring) - .conststring 0x0001c044 Section 376 hal_internal_vsync.o(.conststring) + ap_set_backlight_51 0x00012e69 Thumb Code 76 ap_demo.o(i.ap_set_backlight_51) + i.ap_set_display_off 0x00012edc Section 0 ap_demo.o(i.ap_set_display_off) + ap_set_display_off 0x00012edd Thumb Code 28 ap_demo.o(i.ap_set_display_off) + i.ap_set_display_on 0x00012f20 Section 0 ap_demo.o(i.ap_set_display_on) + ap_set_display_on 0x00012f21 Thumb Code 16 ap_demo.o(i.ap_set_display_on) + i.ap_set_enter_sleep_mode 0x00012f58 Section 0 ap_demo.o(i.ap_set_enter_sleep_mode) + ap_set_enter_sleep_mode 0x00012f59 Thumb Code 74 ap_demo.o(i.ap_set_enter_sleep_mode) + i.ap_set_exit_sleep_mode 0x00012fd8 Section 0 ap_demo.o(i.ap_set_exit_sleep_mode) + ap_set_exit_sleep_mode 0x00012fd9 Thumb Code 58 ap_demo.o(i.ap_set_exit_sleep_mode) + i.ap_set_hbm_53 0x00013048 Section 0 ap_demo.o(i.ap_set_hbm_53) + ap_set_hbm_53 0x00013049 Thumb Code 44 ap_demo.o(i.ap_set_hbm_53) + i.ap_update_frame_rate 0x00013078 Section 0 ap_demo.o(i.ap_update_frame_rate) + ap_update_frame_rate 0x00013079 Thumb Code 36 ap_demo.o(i.ap_update_frame_rate) + i.app_ADC_IRQn_Handler 0x000130a0 Section 0 drv_rxbr.o(i.app_ADC_IRQn_Handler) + i.app_AP_NRESET_IRQn_Handler 0x000130bc Section 0 drv_gpio.o(i.app_AP_NRESET_IRQn_Handler) + i.app_EXTI_INT0_IRQn_Handler 0x000130e0 Section 0 drv_gpio.o(i.app_EXTI_INT0_IRQn_Handler) + i.app_EXTI_INT1_IRQn_Handler 0x000130fc Section 0 drv_gpio.o(i.app_EXTI_INT1_IRQn_Handler) + i.app_EXTI_INT2_IRQn_Handler 0x00013118 Section 0 drv_gpio.o(i.app_EXTI_INT2_IRQn_Handler) + i.app_EXTI_INT3_IRQn_Handler 0x00013134 Section 0 drv_gpio.o(i.app_EXTI_INT3_IRQn_Handler) + i.app_EXTI_INT4_IRQn_Handler 0x00013150 Section 0 drv_gpio.o(i.app_EXTI_INT4_IRQn_Handler) + i.app_EXTI_INT5_IRQn_Handler 0x0001316c Section 0 drv_gpio.o(i.app_EXTI_INT5_IRQn_Handler) + i.app_EXTI_INT6_IRQn_Handler 0x00013188 Section 0 drv_gpio.o(i.app_EXTI_INT6_IRQn_Handler) + i.app_EXTI_INT7_IRQn_Handler 0x000131a4 Section 0 drv_gpio.o(i.app_EXTI_INT7_IRQn_Handler) + i.app_HardFault_Handler 0x000131c0 Section 0 drv_common.o(i.app_HardFault_Handler) + i.app_I2C0_IRQn_Handler 0x00013208 Section 0 drv_i2c_slave.o(i.app_I2C0_IRQn_Handler) + i.app_I2C1_IRQn_Handler 0x00013220 Section 0 drv_i2c_master.o(i.app_I2C1_IRQn_Handler) + i.app_LCDC_IRQn_Handler 0x00013230 Section 0 hal_internal_vsync.o(i.app_LCDC_IRQn_Handler) + i.app_MEMC_IRQn_Handler 0x00013360 Section 0 drv_memc.o(i.app_MEMC_IRQn_Handler) + i.app_MIPI_RX_IRQn_Handler 0x000133e8 Section 0 drv_dsi_rx.o(i.app_MIPI_RX_IRQn_Handler) + i.app_MIPI_TX_IRQn_Handler 0x00013680 Section 0 drv_dsi_tx.o(i.app_MIPI_TX_IRQn_Handler) + i.app_PWMDET_IRQn_Handler 0x00013720 Section 0 drv_pwm.o(i.app_PWMDET_IRQn_Handler) + i.app_SPIM_IRQn_Handler 0x00013768 Section 0 drv_spi_master.o(i.app_SPIM_IRQn_Handler) + i.app_SPIS_IRQn_Handler 0x00013798 Section 0 hal_spi_slave.o(i.app_SPIS_IRQn_Handler) + i.app_SWIRE_IRQn_Handler 0x00013998 Section 0 drv_swire.o(i.app_SWIRE_IRQn_Handler) + i.app_SysTick_Handler 0x000139b8 Section 0 drv_common.o(i.app_SysTick_Handler) + i.app_TIMER0_IRQn_Handler 0x000139d0 Section 0 drv_timer.o(i.app_TIMER0_IRQn_Handler) + i.app_TIMER1_IRQn_Handler 0x000139da Section 0 drv_timer.o(i.app_TIMER1_IRQn_Handler) + i.app_TIMER2_IRQn_Handler 0x000139e4 Section 0 drv_timer.o(i.app_TIMER2_IRQn_Handler) + i.app_TIMER3_IRQn_Handler 0x000139ee Section 0 drv_timer.o(i.app_TIMER3_IRQn_Handler) + i.app_UART_IRQn_Handler 0x000139f8 Section 0 drv_uart.o(i.app_UART_IRQn_Handler) + i.app_VIDC_IRQn_Handler 0x00013a00 Section 0 drv_vidc.o(i.app_VIDC_IRQn_Handler) + i.app_VPRE_IRQn_Handler 0x00013a1c Section 0 drv_rxbr.o(i.app_VPRE_IRQn_Handler) + i.app_WDG_IRQn_Handler 0x00013a38 Section 0 drv_wdg.o(i.app_WDG_IRQn_Handler) + i.app_dma_irq_handler 0x00013a70 Section 0 drv_dma.o(i.app_dma_irq_handler) + i.app_fls_ctrl_Handler 0x00013a80 Section 0 norflash.o(i.app_fls_ctrl_Handler) + i.board_Init 0x00013ab0 Section 0 board.o(i.board_Init) + i.calc_framebuffer_setting 0x00013ad4 Section 0 hal_internal_vsync.o(i.calc_framebuffer_setting) + i.ceil 0x00014060 Section 0 ceil.o(i.ceil) + i.check_mipi_rx_tx_video_info 0x00014128 Section 0 hal_internal_vsync.o(i.check_mipi_rx_tx_video_info) + check_mipi_rx_tx_video_info 0x00014129 Thumb Code 44 hal_internal_vsync.o(i.check_mipi_rx_tx_video_info) + i.check_pkt_buf_rev 0x00014154 Section 0 hal_internal_vsync.o(i.check_pkt_buf_rev) + check_pkt_buf_rev 0x00014155 Thumb Code 74 hal_internal_vsync.o(i.check_pkt_buf_rev) + i.dcs_packet_fifo_alloc 0x000141d8 Section 0 dcs_packet_fifo.o(i.dcs_packet_fifo_alloc) + i.dcs_packet_fifo_init 0x00014230 Section 0 dcs_packet_fifo.o(i.dcs_packet_fifo_init) + i.dcs_packet_free_fifo_header 0x00014248 Section 0 dcs_packet_fifo.o(i.dcs_packet_free_fifo_header) + i.dcs_packet_get_fifo_header 0x0001428c Section 0 dcs_packet_fifo.o(i.dcs_packet_get_fifo_header) + i.dcs_sw_filter 0x000142b0 Section 0 hal_internal_vsync.o(i.dcs_sw_filter) + dcs_sw_filter 0x000142b1 Thumb Code 36 hal_internal_vsync.o(i.dcs_sw_filter) + i.delayMs 0x000142dc Section 0 tau_delay.o(i.delayMs) + i.delayUs 0x000142f4 Section 0 tau_delay.o(i.delayUs) + i.drv_ap_rst_trig_edge_detect 0x00014318 Section 0 drv_sys_cfg.o(i.drv_ap_rst_trig_edge_detect) + i.drv_chip_info_get_info 0x00014350 Section 0 drv_chip_info.o(i.drv_chip_info_get_info) + i.drv_chip_info_init 0x0001435c Section 0 drv_chip_info.o(i.drv_chip_info_init) + i.drv_chip_rx_info_check 0x0001439c Section 0 drv_chip_info.o(i.drv_chip_rx_info_check) + i.drv_chip_rx_init_done 0x0001444c Section 0 drv_chip_info.o(i.drv_chip_rx_init_done) + i.drv_common_enable_systick 0x00014460 Section 0 drv_common.o(i.drv_common_enable_systick) + i.drv_common_system_init 0x000144b8 Section 0 drv_common.o(i.drv_common_system_init) + i.drv_crgu_config_reset_modules 0x000144c0 Section 0 drv_crgu.o(i.drv_crgu_config_reset_modules) + i.drv_crgu_set_ahb_pre_div 0x000144d0 Section 0 drv_crgu.o(i.drv_crgu_set_ahb_pre_div) + i.drv_crgu_set_ahb_src 0x000144e4 Section 0 drv_crgu.o(i.drv_crgu_set_ahb_src) + i.drv_crgu_set_clock 0x000144f8 Section 0 drv_crgu.o(i.drv_crgu_set_clock) + i.drv_crgu_set_dpi_mux_src 0x00014518 Section 0 drv_crgu.o(i.drv_crgu_set_dpi_mux_src) + i.drv_crgu_set_dpi_pre_div 0x0001452c Section 0 drv_crgu.o(i.drv_crgu_set_dpi_pre_div) + i.drv_crgu_set_dpi_pre_src 0x00014544 Section 0 drv_crgu.o(i.drv_crgu_set_dpi_pre_src) + i.drv_crgu_set_dsc_core_div 0x00014558 Section 0 drv_crgu.o(i.drv_crgu_set_dsc_core_div) + i.drv_crgu_set_dsco_src 0x0001456c Section 0 drv_crgu.o(i.drv_crgu_set_dsco_src) + i.drv_crgu_set_dsco_src_div 0x00014580 Section 0 drv_crgu.o(i.drv_crgu_set_dsco_src_div) + i.drv_crgu_set_fb_div 0x00014594 Section 0 drv_crgu.o(i.drv_crgu_set_fb_div) + i.drv_crgu_set_fb_src 0x000145a8 Section 0 drv_crgu.o(i.drv_crgu_set_fb_src) + i.drv_crgu_set_lcdc_div 0x000145bc Section 0 drv_crgu.o(i.drv_crgu_set_lcdc_div) + i.drv_crgu_set_lcdc_src 0x000145d0 Section 0 drv_crgu.o(i.drv_crgu_set_lcdc_src) + i.drv_crgu_set_mipi_cfg_src 0x000145e4 Section 0 drv_crgu.o(i.drv_crgu_set_mipi_cfg_src) + i.drv_crgu_set_mipi_ref_src 0x000145f8 Section 0 drv_crgu.o(i.drv_crgu_set_mipi_ref_src) + i.drv_crgu_set_reset 0x00014610 Section 0 drv_crgu.o(i.drv_crgu_set_reset) + i.drv_crgu_set_rxbr_div 0x00014628 Section 0 drv_crgu.o(i.drv_crgu_set_rxbr_div) + i.drv_crgu_set_rxbr_src 0x0001463c Section 0 drv_crgu.o(i.drv_crgu_set_rxbr_src) + i.drv_crgu_set_vidc_src 0x00014650 Section 0 drv_crgu.o(i.drv_crgu_set_vidc_src) + i.drv_dma_clear_flag 0x00014664 Section 0 drv_dma.o(i.drv_dma_clear_flag) + i.drv_dma_get_channel_flag 0x0001467c Section 0 drv_dma.o(i.drv_dma_get_channel_flag) + i.drv_dma_irq_handler 0x00014688 Section 0 drv_dma.o(i.drv_dma_irq_handler) + i.drv_dsc_dec_convert_pps_rc_parameter 0x00014718 Section 0 drv_dsc_dec.o(i.drv_dsc_dec_convert_pps_rc_parameter) + i.drv_dsc_dec_disable 0x0001474e Section 0 drv_dsc_dec.o(i.drv_dsc_dec_disable) + i.drv_dsc_dec_enable 0x0001475c Section 0 drv_dsc_dec.o(i.drv_dsc_dec_enable) + i.drv_dsc_dec_get_nslc 0x000147d0 Section 0 drv_dsc_dec.o(i.drv_dsc_dec_get_nslc) + i.drv_dsc_dec_set_u8_pps 0x000147da Section 0 drv_dsc_dec.o(i.drv_dsc_dec_set_u8_pps) + i.drv_dsi_rx_calc_ipi_tx_delay 0x00014804 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) + i.drv_dsi_rx_enable_irq 0x00014908 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) + i.drv_dsi_rx_get_bta_status 0x00014948 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_bta_status) + i.drv_dsi_rx_get_color_bpp 0x00014958 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp) + drv_dsi_rx_get_color_bpp 0x00014959 Thumb Code 62 drv_dsi_rx.o(i.drv_dsi_rx_get_color_bpp) + i.drv_dsi_rx_get_color_pcc 0x000149a8 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_color_pcc) + drv_dsi_rx_get_color_pcc 0x000149a9 Thumb Code 24 drv_dsi_rx.o(i.drv_dsi_rx_get_color_pcc) + i.drv_dsi_rx_get_compression_en 0x000149c4 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en) + i.drv_dsi_rx_get_max_ret_size 0x000149cc Section 0 drv_dsi_rx.o(i.drv_dsi_rx_get_max_ret_size) + i.drv_dsi_rx_power_up 0x000149d2 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_power_up) + i.drv_dsi_rx_set_ctrl_cfg 0x000149e0 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ctrl_cfg) + i.drv_dsi_rx_set_ddi_cfg 0x00014a00 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) + i.drv_dsi_rx_set_inten 0x00014a10 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_inten) + i.drv_dsi_rx_set_ipi_cfg 0x00014a14 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_cfg) + i.drv_dsi_rx_set_lane_swap 0x00014a24 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_lane_swap) + i.drv_dsi_rx_set_resp_cnt 0x00014a6a Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_resp_cnt) + i.drv_dsi_rx_set_up_phy 0x00014a90 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) + i.drv_dsi_rx_shut_down 0x00014b94 Section 0 drv_dsi_rx.o(i.drv_dsi_rx_shut_down) + i.drv_dsi_tx_command_header 0x00014ba2 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_command_header) + i.drv_dsi_tx_command_mode_cfg 0x00014bb6 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg) + i.drv_dsi_tx_command_put_payload 0x00014c22 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) + i.drv_dsi_tx_config_eotp 0x00014c26 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_config_eotp) + i.drv_dsi_tx_config_int 0x00014c3e Section 0 drv_dsi_tx.o(i.drv_dsi_tx_config_int) + i.drv_dsi_tx_dpi_lpcmd_time 0x00014c46 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_dpi_lpcmd_time) + i.drv_dsi_tx_dpi_mode 0x00014c4e Section 0 drv_dsi_tx.o(i.drv_dsi_tx_dpi_mode) + i.drv_dsi_tx_dpi_polarity 0x00014c58 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_dpi_polarity) + i.drv_dsi_tx_edpi_cmd_size 0x00014c7c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_edpi_cmd_size) + i.drv_dsi_tx_get_cmd_status 0x00014c80 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) + i.drv_dsi_tx_mode 0x00014c84 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_mode) + i.drv_dsi_tx_phy_clock_lane_auto_lp 0x00014c88 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp) + i.drv_dsi_tx_phy_clock_lane_req_hs 0x00014ca0 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs) + i.drv_dsi_tx_phy_lane_mode 0x00014cba Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_lane_mode) + i.drv_dsi_tx_phy_status_ready 0x00014cc6 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready) + i.drv_dsi_tx_phy_status_stopstate 0x00014d2a Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) + i.drv_dsi_tx_phy_test_setup 0x00014d68 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) + i.drv_dsi_tx_phy_time_cfg 0x00014e9c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg) + i.drv_dsi_tx_powerup 0x00014eba Section 0 drv_dsi_tx.o(i.drv_dsi_tx_powerup) + i.drv_dsi_tx_response_mode 0x00014ec2 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_response_mode) + i.drv_dsi_tx_set_bta_ack 0x00014ede Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_bta_ack) + i.drv_dsi_tx_set_esc_div 0x00014ef6 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) + i.drv_dsi_tx_set_int 0x00014f04 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_int) + i.drv_dsi_tx_set_time_out_div 0x00014f44 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_time_out_div) + i.drv_dsi_tx_set_video_chunk 0x00014f54 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_video_chunk) + i.drv_dsi_tx_set_video_timing 0x00014f5c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_set_video_timing) + i.drv_dsi_tx_shutdown 0x00014f7e Section 0 drv_dsi_tx.o(i.drv_dsi_tx_shutdown) + i.drv_dsi_tx_timeout_cfg 0x00014f86 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_timeout_cfg) + i.drv_dsi_tx_video_mode_cfg 0x00014fac Section 0 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_cfg) + i.drv_dsi_tx_video_mode_disable_hact_cmd 0x00015056 Section 0 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_disable_hact_cmd) + i.drv_dsi_tx_video_mode_set_lp_cmd 0x0001506c Section 0 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_set_lp_cmd) + i.drv_efuse_enter_inactive 0x00015084 Section 0 drv_efuse.o(i.drv_efuse_enter_inactive) + i.drv_efuse_int_enable 0x000150b2 Section 0 drv_efuse.o(i.drv_efuse_int_enable) + i.drv_efuse_read 0x000150be Section 0 drv_efuse.o(i.drv_efuse_read) + i.drv_efuse_read_req 0x000150f0 Section 0 drv_efuse.o(i.drv_efuse_read_req) + i.drv_gpio_set_ioe 0x00015108 Section 0 drv_gpio.o(i.drv_gpio_set_ioe) + i.drv_gpio_set_mode0 0x00015128 Section 0 drv_gpio.o(i.drv_gpio_set_mode0) + i.drv_gpio_set_mode1 0x00015138 Section 0 drv_gpio.o(i.drv_gpio_set_mode1) + i.drv_gpio_set_mode2 0x00015148 Section 0 drv_gpio.o(i.drv_gpio_set_mode2) + i.drv_gpio_set_mode3 0x00015158 Section 0 drv_gpio.o(i.drv_gpio_set_mode3) + i.drv_gpio_set_output_data 0x00015168 Section 0 hal_gpio.o(i.drv_gpio_set_output_data) + drv_gpio_set_output_data 0x00015169 Thumb Code 26 hal_gpio.o(i.drv_gpio_set_output_data) + i.drv_lcdc_config_bypass 0x00015188 Section 0 drv_lcdc.o(i.drv_lcdc_config_bypass) + i.drv_lcdc_config_ccm 0x000151a0 Section 0 drv_lcdc.o(i.drv_lcdc_config_ccm) + i.drv_lcdc_config_disp_mode 0x000151d0 Section 0 drv_lcdc.o(i.drv_lcdc_config_disp_mode) + i.drv_lcdc_config_dpi_polarity 0x000151e6 Section 0 drv_lcdc.o(i.drv_lcdc_config_dpi_polarity) + i.drv_lcdc_config_dpi_timing 0x0001520a Section 0 drv_lcdc.o(i.drv_lcdc_config_dpi_timing) + i.drv_lcdc_config_edpi_mode 0x00015230 Section 0 drv_lcdc.o(i.drv_lcdc_config_edpi_mode) + i.drv_lcdc_config_endianness 0x00015246 Section 0 drv_lcdc.o(i.drv_lcdc_config_endianness) + i.drv_lcdc_config_input_size 0x0001525c Section 0 drv_lcdc.o(i.drv_lcdc_config_input_size) + i.drv_lcdc_config_int 0x00015268 Section 0 drv_lcdc.o(i.drv_lcdc_config_int) + i.drv_lcdc_config_int_single 0x00015286 Section 0 drv_lcdc.o(i.drv_lcdc_config_int_single) + i.drv_lcdc_config_overwrite 0x000152a8 Section 0 drv_lcdc.o(i.drv_lcdc_config_overwrite) + i.drv_lcdc_config_overwrite_rgb 0x000152ca Section 0 drv_lcdc.o(i.drv_lcdc_config_overwrite_rgb) + i.drv_lcdc_config_partial_display_area 0x000152d6 Section 0 drv_lcdc.o(i.drv_lcdc_config_partial_display_area) + i.drv_lcdc_config_partial_display_enable 0x000152f0 Section 0 drv_lcdc.o(i.drv_lcdc_config_partial_display_enable) + i.drv_lcdc_config_scale_up_coef 0x00015312 Section 0 drv_lcdc.o(i.drv_lcdc_config_scale_up_coef) + i.drv_lcdc_config_scale_up_step 0x0001532c Section 0 drv_lcdc.o(i.drv_lcdc_config_scale_up_step) + i.drv_lcdc_config_src_parameter 0x00015338 Section 0 drv_lcdc.o(i.drv_lcdc_config_src_parameter) + i.drv_lcdc_config_thresh 0x00015384 Section 0 drv_lcdc.o(i.drv_lcdc_config_thresh) + i.drv_lcdc_ctrl_flow 0x0001538a Section 0 drv_lcdc.o(i.drv_lcdc_ctrl_flow) + i.drv_lcdc_enable_shadow_reg 0x0001539c Section 0 drv_lcdc.o(i.drv_lcdc_enable_shadow_reg) + i.drv_lcdc_set_int 0x000153bc Section 0 drv_lcdc.o(i.drv_lcdc_set_int) + i.drv_lcdc_set_prefetch 0x000153fc Section 0 drv_lcdc.o(i.drv_lcdc_set_prefetch) + i.drv_lcdc_set_video_hw_mode 0x00015414 Section 0 drv_lcdc.o(i.drv_lcdc_set_video_hw_mode) + i.drv_lcdc_start 0x00015428 Section 0 drv_lcdc.o(i.drv_lcdc_start) + i.drv_memc_clear_status 0x00015448 Section 0 drv_memc.o(i.drv_memc_clear_status) + i.drv_memc_enable_irq 0x00015454 Section 0 drv_memc.o(i.drv_memc_enable_irq) + i.drv_memc_gen_a_tear_signal 0x00015494 Section 0 drv_memc.o(i.drv_memc_gen_a_tear_signal) + i.drv_memc_get_status 0x000154a0 Section 0 drv_memc.o(i.drv_memc_get_status) + i.drv_memc_rate_transfer_sel 0x000154b2 Section 0 drv_memc.o(i.drv_memc_rate_transfer_sel) + i.drv_memc_sel_vsync 0x000154c2 Section 0 drv_memc.o(i.drv_memc_sel_vsync) + i.drv_memc_set_active_height 0x000154d0 Section 0 drv_memc.o(i.drv_memc_set_active_height) + i.drv_memc_set_data_mode 0x000154e4 Section 0 drv_memc.o(i.drv_memc_set_data_mode) + i.drv_memc_set_double_buffer 0x000154f0 Section 0 drv_memc.o(i.drv_memc_set_double_buffer) + i.drv_memc_set_double_buffer_reverse 0x00015500 Section 0 drv_memc.o(i.drv_memc_set_double_buffer_reverse) + i.drv_memc_set_fs_en_conditions 0x00015512 Section 0 drv_memc.o(i.drv_memc_set_fs_en_conditions) + i.drv_memc_set_inten 0x00015522 Section 0 drv_memc.o(i.drv_memc_set_inten) + i.drv_memc_set_lcdc_st_conditions 0x00015538 Section 0 drv_memc.o(i.drv_memc_set_lcdc_st_conditions) + i.drv_memc_set_ltpo_mode 0x00015550 Section 0 drv_memc.o(i.drv_memc_set_ltpo_mode) + i.drv_memc_set_tear_mode 0x0001556a Section 0 drv_memc.o(i.drv_memc_set_tear_mode) + i.drv_memc_set_tear_waveform 0x00015578 Section 0 drv_memc.o(i.drv_memc_set_tear_waveform) + i.drv_memc_set_vidc_sync_cnt 0x000155a0 Section 0 drv_memc.o(i.drv_memc_set_vidc_sync_cnt) + i.drv_param_init_get_ccm 0x000155b0 Section 0 drv_param_init.o(i.drv_param_init_get_ccm) + i.drv_param_init_get_scld_filter_h 0x000155b8 Section 0 drv_param_init.o(i.drv_param_init_get_scld_filter_h) + i.drv_param_init_get_scld_filter_v 0x000155cc Section 0 drv_param_init.o(i.drv_param_init_get_scld_filter_v) + i.drv_param_init_get_sclu_filter 0x000155e0 Section 0 drv_param_init.o(i.drv_param_init_get_sclu_filter) + i.drv_param_init_set_ccm 0x000155e8 Section 0 drv_param_init.o(i.drv_param_init_set_ccm) + i.drv_param_init_set_scld_filter 0x000155fc Section 0 drv_param_init.o(i.drv_param_init_set_scld_filter) + i.drv_param_p2r_filter_init 0x00015660 Section 0 drv_param_init.o(i.drv_param_p2r_filter_init) + i.drv_phy_enable_calibration 0x00015684 Section 0 drv_phy_common.o(i.drv_phy_enable_calibration) + i.drv_phy_get_calibration 0x00015694 Section 0 drv_phy_common.o(i.drv_phy_get_calibration) + i.drv_phy_get_pll_para 0x000156d0 Section 0 drv_phy_common.o(i.drv_phy_get_pll_para) + i.drv_phy_get_rate_para 0x00015730 Section 0 drv_phy_common.o(i.drv_phy_get_rate_para) + i.drv_phy_test_clear 0x00015784 Section 0 drv_phy_common.o(i.drv_phy_test_clear) + i.drv_phy_test_lock 0x00015794 Section 0 drv_phy_common.o(i.drv_phy_test_lock) + i.drv_phy_test_write_1_byte 0x000157ac Section 0 drv_phy_common.o(i.drv_phy_test_write_1_byte) + i.drv_phy_test_write_2_byte 0x000157cc Section 0 drv_phy_common.o(i.drv_phy_test_write_2_byte) + i.drv_phy_test_write_code 0x000157f2 Section 0 drv_phy_common.o(i.drv_phy_test_write_code) + i.drv_phy_test_write_data 0x00015810 Section 0 drv_phy_common.o(i.drv_phy_test_write_data) + drv_phy_test_write_data 0x00015811 Thumb Code 32 drv_phy_common.o(i.drv_phy_test_write_data) + i.drv_pwr_set_pvd_mode 0x00015830 Section 0 drv_pwr.o(i.drv_pwr_set_pvd_mode) + i.drv_pwr_set_system_clk_src 0x00015848 Section 0 drv_pwr.o(i.drv_pwr_set_system_clk_src) + i.drv_rx_phy_test_clear 0x00015880 Section 0 drv_dsi_rx.o(i.drv_rx_phy_test_clear) + drv_rx_phy_test_clear 0x00015881 Thumb Code 12 drv_dsi_rx.o(i.drv_rx_phy_test_clear) + i.drv_rx_phy_test_lock 0x0001588c Section 0 drv_dsi_rx.o(i.drv_rx_phy_test_lock) + drv_rx_phy_test_lock 0x0001588d Thumb Code 16 drv_dsi_rx.o(i.drv_rx_phy_test_lock) + i.drv_rx_phy_test_write_1_byte 0x0001589c Section 0 drv_dsi_rx.o(i.drv_rx_phy_test_write_1_byte) + drv_rx_phy_test_write_1_byte 0x0001589d Thumb Code 20 drv_dsi_rx.o(i.drv_rx_phy_test_write_1_byte) + i.drv_rx_phy_test_write_2_byte 0x000158b0 Section 0 drv_dsi_rx.o(i.drv_rx_phy_test_write_2_byte) + drv_rx_phy_test_write_2_byte 0x000158b1 Thumb Code 22 drv_dsi_rx.o(i.drv_rx_phy_test_write_2_byte) + i.drv_rxbr_clear_pkt_buffer 0x000158c6 Section 0 drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) + i.drv_rxbr_clear_status0 0x000158d0 Section 0 drv_rxbr.o(i.drv_rxbr_clear_status0) + i.drv_rxbr_enable_irq 0x000158d4 Section 0 drv_rxbr.o(i.drv_rxbr_enable_irq) + i.drv_rxbr_frame_drop_cfg 0x00015930 Section 0 drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) + i.drv_rxbr_get_clk 0x00015944 Section 0 drv_rxbr.o(i.drv_rxbr_get_clk) + i.drv_rxbr_get_col_addr 0x000159a8 Section 0 drv_rxbr.o(i.drv_rxbr_get_col_addr) + i.drv_rxbr_get_int_source 0x000159ac Section 0 hal_internal_vsync.o(i.drv_rxbr_get_int_source) + drv_rxbr_get_int_source 0x000159ad Thumb Code 18 hal_internal_vsync.o(i.drv_rxbr_get_int_source) + i.drv_rxbr_get_page_addr 0x000159be Section 0 drv_rxbr.o(i.drv_rxbr_get_page_addr) + i.drv_rxbr_get_pkt_buf_error_status 0x000159c2 Section 0 drv_rxbr.o(i.drv_rxbr_get_pkt_buf_error_status) + i.drv_rxbr_get_status0 0x000159ce Section 0 hal_internal_vsync.o(i.drv_rxbr_get_status0) + drv_rxbr_get_status0 0x000159cf Thumb Code 18 hal_internal_vsync.o(i.drv_rxbr_get_status0) + i.drv_rxbr_get_status1 0x000159e0 Section 0 hal_internal_vsync.o(i.drv_rxbr_get_status1) + drv_rxbr_get_status1 0x000159e1 Thumb Code 22 hal_internal_vsync.o(i.drv_rxbr_get_status1) + i.drv_rxbr_hline_rcv0_cfg 0x000159f6 Section 0 drv_rxbr.o(i.drv_rxbr_hline_rcv0_cfg) + i.drv_rxbr_hline_rcv1_cfg 0x00015a02 Section 0 drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg) + i.drv_rxbr_hline_rcv_cfg 0x00015a0e Section 0 drv_rxbr.o(i.drv_rxbr_hline_rcv_cfg) + i.drv_rxbr_register_irq0_callback 0x00015a18 Section 0 drv_rxbr.o(i.drv_rxbr_register_irq0_callback) + i.drv_rxbr_register_irq1_callback 0x00015a24 Section 0 drv_rxbr.o(i.drv_rxbr_register_irq1_callback) + i.drv_rxbr_set_ack_pkt_header 0x00015a30 Section 0 drv_rxbr.o(i.drv_rxbr_set_ack_pkt_header) + i.drv_rxbr_set_color_format 0x00015a44 Section 0 drv_rxbr.o(i.drv_rxbr_set_color_format) + i.drv_rxbr_set_filter_regs 0x00015a58 Section 0 drv_rxbr.o(i.drv_rxbr_set_filter_regs) + i.drv_rxbr_set_inten 0x00015a6a Section 0 drv_rxbr.o(i.drv_rxbr_set_inten) + i.drv_rxbr_set_ltpo_drop_th 0x00015a7e Section 0 drv_rxbr.o(i.drv_rxbr_set_ltpo_drop_th) + i.drv_rxbr_set_usr_cfg 0x00015a8e Section 0 drv_rxbr.o(i.drv_rxbr_set_usr_cfg) + i.drv_rxbr_set_usr_col 0x00015ab4 Section 0 drv_rxbr.o(i.drv_rxbr_set_usr_col) + i.drv_rxbr_set_usr_row 0x00015abc Section 0 drv_rxbr.o(i.drv_rxbr_set_usr_row) + i.drv_swire_set_int 0x00015ac4 Section 0 drv_swire.o(i.drv_swire_set_int) + i.drv_sys_cfg_clear_all_int 0x00015b18 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_clear_all_int) + i.drv_sys_cfg_clear_pending 0x00015b24 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) + i.drv_sys_cfg_sel_ap_rst_lvl_trig 0x00015b4c Section 0 drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_lvl_trig) + i.drv_sys_cfg_set_int 0x00015b64 Section 0 drv_sys_cfg.o(i.drv_sys_cfg_set_int) + i.drv_timer_clear_status_flags 0x00015b88 Section 0 drv_timer.o(i.drv_timer_clear_status_flags) + drv_timer_clear_status_flags 0x00015b89 Thumb Code 26 drv_timer.o(i.drv_timer_clear_status_flags) + i.drv_timer_enable 0x00015ba2 Section 0 drv_timer.o(i.drv_timer_enable) + i.drv_timer_get_instance 0x00015bc4 Section 0 drv_timer.o(i.drv_timer_get_instance) + i.drv_timer_handle_interrupt 0x00015bd4 Section 0 drv_timer.o(i.drv_timer_handle_interrupt) + drv_timer_handle_interrupt 0x00015bd5 Thumb Code 62 drv_timer.o(i.drv_timer_handle_interrupt) + i.drv_timer_set_compare_val 0x00015c18 Section 0 drv_timer.o(i.drv_timer_set_compare_val) + i.drv_timer_set_int 0x00015c28 Section 0 drv_timer.o(i.drv_timer_set_int) + i.drv_tx_phy_test_clear 0x00015c7c Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_clear) + drv_tx_phy_test_clear 0x00015c7d Thumb Code 10 drv_dsi_tx.o(i.drv_tx_phy_test_clear) + i.drv_tx_phy_test_enter 0x00015c86 Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_enter) + i.drv_tx_phy_test_exit 0x00015ca2 Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_exit) + i.drv_tx_phy_test_write_1_byte 0x00015cbe Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_write_1_byte) + drv_tx_phy_test_write_1_byte 0x00015cbf Thumb Code 18 drv_dsi_tx.o(i.drv_tx_phy_test_write_1_byte) + i.drv_tx_phy_test_write_2_byte 0x00015cd0 Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_write_2_byte) + drv_tx_phy_test_write_2_byte 0x00015cd1 Thumb Code 20 drv_dsi_tx.o(i.drv_tx_phy_test_write_2_byte) + i.drv_tx_phy_test_write_code 0x00015ce4 Section 0 drv_dsi_tx.o(i.drv_tx_phy_test_write_code) + drv_tx_phy_test_write_code 0x00015ce5 Thumb Code 16 drv_dsi_tx.o(i.drv_tx_phy_test_write_code) + i.drv_vidc_clear_irq 0x00015cf4 Section 0 drv_vidc.o(i.drv_vidc_clear_irq) + i.drv_vidc_enable 0x00015cfc Section 0 drv_vidc.o(i.drv_vidc_enable) + i.drv_vidc_enable_irq 0x00015d14 Section 0 drv_vidc.o(i.drv_vidc_enable_irq) + i.drv_vidc_get_irq_status 0x00015d54 Section 0 drv_vidc.o(i.drv_vidc_get_irq_status) + i.drv_vidc_init_module_enable 0x00015d68 Section 0 drv_vidc.o(i.drv_vidc_init_module_enable) + i.drv_vidc_register_callback 0x00015d90 Section 0 drv_vidc.o(i.drv_vidc_register_callback) + i.drv_vidc_reset 0x00015d9c Section 0 drv_vidc.o(i.drv_vidc_reset) + i.drv_vidc_set_dst_parameter 0x00015da2 Section 0 drv_vidc.o(i.drv_vidc_set_dst_parameter) + i.drv_vidc_set_irqen 0x00015dde Section 0 drv_vidc.o(i.drv_vidc_set_irqen) + i.drv_vidc_set_mirror 0x00015df2 Section 0 drv_vidc.o(i.drv_vidc_set_mirror) + i.drv_vidc_set_p2r_hcoef0 0x00015e02 Section 0 drv_vidc.o(i.drv_vidc_set_p2r_hcoef0) + i.drv_vidc_set_p2r_hinitb 0x00015e0a Section 0 drv_vidc.o(i.drv_vidc_set_p2r_hinitb) + i.drv_vidc_set_p2r_hinitr 0x00015e30 Section 0 drv_vidc.o(i.drv_vidc_set_p2r_hinitr) + i.drv_vidc_set_pentile_swap 0x00015e58 Section 0 drv_vidc.o(i.drv_vidc_set_pentile_swap) + i.drv_vidc_set_pu_ctrl 0x00015e70 Section 0 drv_vidc.o(i.drv_vidc_set_pu_ctrl) + i.drv_vidc_set_rotation 0x00015e7a Section 0 drv_vidc.o(i.drv_vidc_set_rotation) + i.drv_vidc_set_scld_hcoef0 0x00015e8a Section 0 drv_vidc.o(i.drv_vidc_set_scld_hcoef0) + i.drv_vidc_set_scld_hcoef1 0x00015e94 Section 0 drv_vidc.o(i.drv_vidc_set_scld_hcoef1) + i.drv_vidc_set_scld_step 0x00015e9e Section 0 drv_vidc.o(i.drv_vidc_set_scld_step) + i.drv_vidc_set_scld_vcoef0 0x00015eb0 Section 0 drv_vidc.o(i.drv_vidc_set_scld_vcoef0) + i.drv_vidc_set_scld_vcoef1 0x00015eba Section 0 drv_vidc.o(i.drv_vidc_set_scld_vcoef1) + i.drv_vidc_set_src_parameter 0x00015ec4 Section 0 drv_vidc.o(i.drv_vidc_set_src_parameter) + i.drv_wdg_clear_counter 0x00015edc Section 0 drv_wdg.o(i.drv_wdg_clear_counter) + i.drv_wdg_clear_edge_flag 0x00015eec Section 0 drv_wdg.o(i.drv_wdg_clear_edge_flag) + drv_wdg_clear_edge_flag 0x00015eed Thumb Code 12 drv_wdg.o(i.drv_wdg_clear_edge_flag) + i.drv_wdg_read_edge_flag 0x00015efc Section 0 drv_wdg.o(i.drv_wdg_read_edge_flag) + drv_wdg_read_edge_flag 0x00015efd Thumb Code 10 drv_wdg.o(i.drv_wdg_read_edge_flag) + i.drv_wdg_set_int 0x00015f0c Section 0 drv_wdg.o(i.drv_wdg_set_int) + i.fls_clr_interrupt_flag 0x00015f4c Section 0 drv_fls.o(i.fls_clr_interrupt_flag) + i.fputc 0x00015f56 Section 0 tau_log.o(i.fputc) + i.frame_start_cb 0x00015f6c Section 0 ap_demo.o(i.frame_start_cb) + frame_start_cb 0x00015f6d Thumb Code 38 ap_demo.o(i.frame_start_cb) + i.hal_dsi_rx_ctrl_create_handle 0x00015fbc Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) + i.hal_dsi_rx_ctrl_dsc_async_handler 0x00015ff0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dsc_async_handler) + i.hal_dsi_rx_ctrl_gen_a_tear_signal 0x00016018 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_gen_a_tear_signal) + i.hal_dsi_rx_ctrl_get_max_ret_size 0x00016040 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) + i.hal_dsi_rx_ctrl_init 0x00016068 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) + i.hal_dsi_rx_ctrl_init_clk 0x00016100 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) + hal_dsi_rx_ctrl_init_clk 0x00016101 Thumb Code 332 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_clk) + i.hal_dsi_rx_ctrl_init_dsi_rx 0x000162a4 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) + hal_dsi_rx_ctrl_init_dsi_rx 0x000162a5 Thumb Code 184 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_dsi_rx) + i.hal_dsi_rx_ctrl_init_memc 0x0001637c Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) + hal_dsi_rx_ctrl_init_memc 0x0001637d Thumb Code 342 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_memc) + i.hal_dsi_rx_ctrl_init_rxbr 0x000164dc Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) + hal_dsi_rx_ctrl_init_rxbr 0x000164dd Thumb Code 320 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_rxbr) + i.hal_dsi_rx_ctrl_init_vidc 0x0001662c Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) + hal_dsi_rx_ctrl_init_vidc 0x0001662d Thumb Code 544 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init_vidc) + i.hal_dsi_rx_ctrl_pre_init_pps 0x00016858 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) + i.hal_dsi_rx_ctrl_restart 0x00016894 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) + i.hal_dsi_rx_ctrl_send_ack_cmd 0x000168e4 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) + i.hal_dsi_rx_ctrl_set_cus_esc_clk 0x000169d4 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk) + i.hal_dsi_rx_ctrl_set_cus_scld_filter 0x00016a00 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_scld_filter) + i.hal_dsi_rx_ctrl_set_cus_sync_line 0x00016a6c Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_sync_line) + i.hal_dsi_rx_ctrl_set_ipi_cfg 0x00016aa0 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) + hal_dsi_rx_ctrl_set_ipi_cfg 0x00016aa1 Thumb Code 50 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_ipi_cfg) + i.hal_dsi_rx_ctrl_set_rxbr_clk 0x00016ad8 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rxbr_clk) + hal_dsi_rx_ctrl_set_rxbr_clk 0x00016ad9 Thumb Code 114 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_rxbr_clk) + i.hal_dsi_rx_ctrl_set_tear_mode_ex 0x00016b4a Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_tear_mode_ex) + i.hal_dsi_rx_ctrl_start 0x00016b58 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) + i.hal_dsi_rx_ctrl_toggle_resolution 0x00016b94 Section 0 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) + i.hal_dsi_tx_calc_video_chunks 0x00016bb4 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_calc_video_chunks) + hal_dsi_tx_calc_video_chunks 0x00016bb5 Thumb Code 384 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_calc_video_chunks) + i.hal_dsi_tx_config_params_for_lane_rate 0x00016d44 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_config_params_for_lane_rate) + hal_dsi_tx_config_params_for_lane_rate 0x00016d45 Thumb Code 42 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_config_params_for_lane_rate) + i.hal_dsi_tx_count_lane_rate 0x00016d78 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_count_lane_rate) + hal_dsi_tx_count_lane_rate 0x00016d79 Thumb Code 982 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_count_lane_rate) + i.hal_dsi_tx_ctrl_create_handle 0x000171a0 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) + i.hal_dsi_tx_ctrl_enter_init_panel_mode 0x000171cc Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_enter_init_panel_mode) + i.hal_dsi_tx_ctrl_exit_init_panel_mode 0x00017218 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_exit_init_panel_mode) + i.hal_dsi_tx_ctrl_init 0x00017240 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) + i.hal_dsi_tx_ctrl_init_clk 0x000172e4 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) + hal_dsi_tx_ctrl_init_clk 0x000172e5 Thumb Code 36 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init_clk) + i.hal_dsi_tx_ctrl_panel_reset_pin 0x00017308 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_panel_reset_pin) + i.hal_dsi_tx_ctrl_set_ccm 0x00017314 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_ccm) + i.hal_dsi_tx_ctrl_set_overwrite_rgb 0x00017334 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb) + i.hal_dsi_tx_ctrl_set_partial_disp 0x00017348 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_partial_disp) + i.hal_dsi_tx_ctrl_set_partial_disp_area 0x00017358 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_partial_disp_area) + i.hal_dsi_tx_ctrl_start 0x0001737c Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) + i.hal_dsi_tx_ctrl_write_array_cmd 0x00017424 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) + i.hal_dsi_tx_ctrl_write_cmd 0x00017514 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) + i.hal_dsi_tx_init_data_mode 0x000175e0 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_data_mode) + hal_dsi_tx_init_data_mode 0x000175e1 Thumb Code 58 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_data_mode) + i.hal_dsi_tx_init_dpi_cfg 0x00017624 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_cfg) + hal_dsi_tx_init_dpi_cfg 0x00017625 Thumb Code 42 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_dpi_cfg) + i.hal_dsi_tx_init_interrupt 0x00017654 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_interrupt) + hal_dsi_tx_init_interrupt 0x00017655 Thumb Code 28 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_interrupt) + i.hal_dsi_tx_init_phy_cfg 0x00017674 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) + hal_dsi_tx_init_phy_cfg 0x00017675 Thumb Code 28 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_phy_cfg) + i.hal_dsi_tx_init_remains 0x00017694 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_remains) + hal_dsi_tx_init_remains 0x00017695 Thumb Code 142 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_remains) + i.hal_dsi_tx_init_video_mode 0x00017728 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_video_mode) + hal_dsi_tx_init_video_mode 0x00017729 Thumb Code 82 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_init_video_mode) + i.hal_dsi_tx_send_cmd 0x00017780 Section 0 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) + hal_dsi_tx_send_cmd 0x00017781 Thumb Code 60 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_send_cmd) + i.hal_gpio_init_output 0x000177c4 Section 0 hal_gpio.o(i.hal_gpio_init_output) + i.hal_gpio_set_mode 0x000177ec Section 0 hal_gpio.o(i.hal_gpio_set_mode) + i.hal_gpio_set_output_data 0x0001784c Section 0 hal_gpio.o(i.hal_gpio_set_output_data) + i.hal_internal_check_video_auto_sync 0x00017854 Section 0 hal_internal_vsync.o(i.hal_internal_check_video_auto_sync) + i.hal_internal_init_memc 0x0001786c Section 0 hal_internal_vsync.o(i.hal_internal_init_memc) + i.hal_internal_rx_dcs_async_handler 0x00017968 Section 0 hal_internal_vsync.o(i.hal_internal_rx_dcs_async_handler) + i.hal_internal_rx_dcs_polling 0x00017994 Section 0 hal_internal_vsync.o(i.hal_internal_rx_dcs_polling) + i.hal_internal_sync_get_fb_setting 0x000179ec Section 0 hal_internal_vsync.o(i.hal_internal_sync_get_fb_setting) + i.hal_internal_sync_get_hight_performan_mode 0x000179fc Section 0 hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) + i.hal_internal_sync_input_resolution_change 0x00017a0c Section 0 hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) + i.hal_internal_vsync_deinit 0x00017c38 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_deinit) + i.hal_internal_vsync_get_sync_line 0x00017c60 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) + i.hal_internal_vsync_get_tear_mode 0x00017c78 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_get_tear_mode) + i.hal_internal_vsync_get_tx_state 0x00017c84 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) + i.hal_internal_vsync_init_rx 0x00017c90 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_init_rx) + i.hal_internal_vsync_init_tx 0x00017dd0 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_init_tx) + i.hal_internal_vsync_set_auto_hw_filter 0x00017e80 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_auto_hw_filter) + i.hal_internal_vsync_set_rx_state 0x00017f10 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) + i.hal_internal_vsync_set_sync_line 0x00017f34 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) + i.hal_internal_vsync_set_tear_mode 0x00017f78 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) + i.hal_internal_vsync_set_tx_state 0x00017fc8 Section 0 hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) + i.hal_intl_svs_deinit_tx 0x0001804c Section 0 hal_internal_soft_sync.o(i.hal_intl_svs_deinit_tx) + i.hal_intl_svs_handle 0x0001805c Section 0 hal_internal_soft_sync.o(i.hal_intl_svs_handle) + i.hal_intl_svs_init_rx 0x00018080 Section 0 hal_internal_soft_sync.o(i.hal_intl_svs_init_rx) + i.hal_intl_svs_init_tx 0x000180f8 Section 0 hal_internal_soft_sync.o(i.hal_intl_svs_init_tx) + i.hal_intl_svs_set_sync_coef 0x0001810c Section 0 hal_internal_soft_sync.o(i.hal_intl_svs_set_sync_coef) + i.hal_intl_svs_update_rxbr_clk 0x00018118 Section 0 hal_internal_soft_sync.o(i.hal_intl_svs_update_rxbr_clk) + i.hal_lcdc_config_ccm 0x00018160 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_ccm) + hal_lcdc_config_ccm 0x00018161 Thumb Code 30 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_ccm) + i.hal_lcdc_config_remains 0x00018184 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_remains) + hal_lcdc_config_remains 0x00018185 Thumb Code 94 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_remains) + i.hal_lcdc_config_rgb_to_pentile 0x000181e8 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_rgb_to_pentile) + hal_lcdc_config_rgb_to_pentile 0x000181e9 Thumb Code 14 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_rgb_to_pentile) + i.hal_lcdc_config_upscaler 0x000181fc Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_upscaler) + hal_lcdc_config_upscaler 0x000181fd Thumb Code 348 hal_dsi_tx_ctrl.o(i.hal_lcdc_config_upscaler) + i.hal_lcdc_init_cfg 0x00018360 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) + hal_lcdc_init_cfg 0x00018361 Thumb Code 78 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_cfg) + i.hal_lcdc_init_clk 0x000183b4 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) + hal_lcdc_init_clk 0x000183b5 Thumb Code 446 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_clk) + i.hal_lcdc_init_interrupt 0x00018580 Section 0 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_interrupt) + hal_lcdc_init_interrupt 0x00018581 Thumb Code 58 hal_dsi_tx_ctrl.o(i.hal_lcdc_init_interrupt) + i.hal_system_enable_systick 0x000185c0 Section 0 hal_system.o(i.hal_system_enable_systick) + i.hal_system_init 0x000185c8 Section 0 hal_system.o(i.hal_system_init) + i.hal_system_init_console 0x00018650 Section 0 hal_system.o(i.hal_system_init_console) + i.hal_system_set_phy_calibration 0x0001866c Section 0 hal_system.o(i.hal_system_set_phy_calibration) + i.hal_tx_frame_rate_adjust 0x00018674 Section 0 hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) + hal_tx_frame_rate_adjust 0x00018675 Thumb Code 44 hal_dsi_tx_ctrl.o(i.hal_tx_frame_rate_adjust) + i.hal_uart_init 0x000186a4 Section 0 hal_uart.o(i.hal_uart_init) + i.hal_uart_transmit_blocking 0x00018730 Section 0 hal_uart.o(i.hal_uart_transmit_blocking) + i.handle_init 0x00018740 Section 0 irq_redirect .o(i.handle_init) + i.init_mipi_tx 0x00018850 Section 0 ap_demo.o(i.init_mipi_tx) + init_mipi_tx 0x00018851 Thumb Code 100 ap_demo.o(i.init_mipi_tx) + i.init_panel 0x000188bc Section 0 ap_demo.o(i.init_panel) + init_panel 0x000188bd Thumb Code 150 ap_demo.o(i.init_panel) + i.main 0x0001895c Section 0 main.o(i.main) + i.open_mipi_rx 0x00018968 Section 0 ap_demo.o(i.open_mipi_rx) + open_mipi_rx 0x00018969 Thumb Code 170 ap_demo.o(i.open_mipi_rx) + i.pps_update_handle 0x00018a3c Section 0 ap_demo.o(i.pps_update_handle) + pps_update_handle 0x00018a3d Thumb Code 78 ap_demo.o(i.pps_update_handle) + i.rx_get_dcs_packet_data 0x00018ad8 Section 0 hal_internal_vsync.o(i.rx_get_dcs_packet_data) + rx_get_dcs_packet_data 0x00018ad9 Thumb Code 654 hal_internal_vsync.o(i.rx_get_dcs_packet_data) + i.rx_partial_update 0x00018ecc Section 0 hal_internal_vsync.o(i.rx_partial_update) + rx_partial_update 0x00018ecd Thumb Code 348 hal_internal_vsync.o(i.rx_partial_update) + i.rx_receive_packet 0x00019038 Section 0 hal_internal_vsync.o(i.rx_receive_packet) + rx_receive_packet 0x00019039 Thumb Code 126 hal_internal_vsync.o(i.rx_receive_packet) + i.rx_receive_pps 0x000190c4 Section 0 hal_internal_vsync.o(i.rx_receive_pps) + rx_receive_pps 0x000190c5 Thumb Code 268 hal_internal_vsync.o(i.rx_receive_pps) + i.rxbr_irq0_callback 0x00019244 Section 0 hal_internal_vsync.o(i.rxbr_irq0_callback) + rxbr_irq0_callback 0x00019245 Thumb Code 192 hal_internal_vsync.o(i.rxbr_irq0_callback) + i.rxbr_irq1_callback 0x00019310 Section 0 hal_internal_vsync.o(i.rxbr_irq1_callback) + rxbr_irq1_callback 0x00019311 Thumb Code 392 hal_internal_vsync.o(i.rxbr_irq1_callback) + i.soft_gen_te 0x00019554 Section 0 hal_internal_vsync.o(i.soft_gen_te) + soft_gen_te 0x00019555 Thumb Code 166 hal_internal_vsync.o(i.soft_gen_te) + i.soft_gen_te_double_buffer 0x00019618 Section 0 hal_internal_vsync.o(i.soft_gen_te_double_buffer) + soft_gen_te_double_buffer 0x00019619 Thumb Code 166 hal_internal_vsync.o(i.soft_gen_te_double_buffer) + i.sqrt 0x000196d8 Section 0 sqrt.o(i.sqrt) + i.svs_direct_mode_setting 0x00019720 Section 0 hal_internal_soft_sync.o(i.svs_direct_mode_setting) + svs_direct_mode_setting 0x00019721 Thumb Code 156 hal_internal_soft_sync.o(i.svs_direct_mode_setting) + i.svs_get_rel_intv 0x000197cc Section 0 hal_internal_soft_sync.o(i.svs_get_rel_intv) + svs_get_rel_intv 0x000197cd Thumb Code 20 hal_internal_soft_sync.o(i.svs_get_rel_intv) + i.svs_sync_handle 0x000197e8 Section 0 hal_internal_soft_sync.o(i.svs_sync_handle) + svs_sync_handle 0x000197e9 Thumb Code 158 hal_internal_soft_sync.o(i.svs_sync_handle) + i.svs_wait_start 0x00019898 Section 0 hal_internal_soft_sync.o(i.svs_wait_start) + svs_wait_start 0x00019899 Thumb Code 224 hal_internal_soft_sync.o(i.svs_wait_start) + i.svs_waite_fr_stab 0x0001998c Section 0 hal_internal_soft_sync.o(i.svs_waite_fr_stab) + svs_waite_fr_stab 0x0001998d Thumb Code 148 hal_internal_soft_sync.o(i.svs_waite_fr_stab) + i.vidc_callback 0x00019a64 Section 0 hal_internal_vsync.o(i.vidc_callback) + vidc_callback 0x00019a65 Thumb Code 234 hal_internal_vsync.o(i.vidc_callback) + i.vpre_err_reset 0x00019b6c Section 0 hal_internal_vsync.o(i.vpre_err_reset) + vpre_err_reset 0x00019b6d Thumb Code 192 hal_internal_vsync.o(i.vpre_err_reset) + i.vsync_set_te_mode 0x00019c44 Section 0 hal_internal_vsync.o(i.vsync_set_te_mode) + vsync_set_te_mode 0x00019c45 Thumb Code 300 hal_internal_vsync.o(i.vsync_set_te_mode) + .constdata 0x00019e10 Section 8052 ap_demo.o(.constdata) + g_cus_rx_dcs_execute_table 0x00019e10 Data 108 ap_demo.o(.constdata) + .constdata 0x0001bd84 Section 210 hal_gpio.o(.constdata) + s_gpio_map 0x0001bd84 Data 120 hal_gpio.o(.constdata) + s_gpio_perf 0x0001bdfc Data 90 hal_gpio.o(.constdata) + .constdata 0x0001be58 Section 8 drv_param_init.o(.constdata) + .constdata 0x0001be60 Section 390 drv_phy_common.o(.constdata) + phy_para_mapping_h 0x0001be60 Data 184 drv_phy_common.o(.constdata) + phy_para_mapping_l 0x0001bf18 Data 128 drv_phy_common.o(.constdata) + phy_data_high_map 0x0001bf98 Data 48 drv_phy_common.o(.constdata) + phy_data_lp_map 0x0001bfc8 Data 30 drv_phy_common.o(.constdata) + .conststring 0x0001bfe8 Section 72 hal_dsi_rx_ctrl.o(.conststring) + .conststring 0x0001c030 Section 67 hal_dsi_tx_ctrl.o(.conststring) + .conststring 0x0001c074 Section 376 hal_internal_vsync.o(.conststring) .ARM.__AT_0x00070100 0x00070100 Section 192 irq_redirect .o(.ARM.__AT_0x00070100) .data 0x000701d0 Section 560 ap_demo.o(.data) start_display_on 0x000701d0 Data 1 ap_demo.o(.data) @@ -4020,318 +4022,318 @@ Image Symbol Table __set_errno 0x000113a1 Thumb Code 6 errno.o(i.__set_errno) ap_demo 0x00012cdd Thumb Code 230 ap_demo.o(i.ap_demo) ap_get_tp_calibration_status_01 0x00012e49 Thumb Code 28 app_tp_st_touch.o(i.ap_get_tp_calibration_status_01) - app_ADC_IRQn_Handler 0x00013071 Thumb Code 22 drv_rxbr.o(i.app_ADC_IRQn_Handler) - app_AP_NRESET_IRQn_Handler 0x0001308d Thumb Code 32 drv_gpio.o(i.app_AP_NRESET_IRQn_Handler) - app_EXTI_INT0_IRQn_Handler 0x000130b1 Thumb Code 22 drv_gpio.o(i.app_EXTI_INT0_IRQn_Handler) - app_EXTI_INT1_IRQn_Handler 0x000130cd Thumb Code 22 drv_gpio.o(i.app_EXTI_INT1_IRQn_Handler) - app_EXTI_INT2_IRQn_Handler 0x000130e9 Thumb Code 22 drv_gpio.o(i.app_EXTI_INT2_IRQn_Handler) - app_EXTI_INT3_IRQn_Handler 0x00013105 Thumb Code 22 drv_gpio.o(i.app_EXTI_INT3_IRQn_Handler) - app_EXTI_INT4_IRQn_Handler 0x00013121 Thumb Code 22 drv_gpio.o(i.app_EXTI_INT4_IRQn_Handler) - app_EXTI_INT5_IRQn_Handler 0x0001313d Thumb Code 22 drv_gpio.o(i.app_EXTI_INT5_IRQn_Handler) - app_EXTI_INT6_IRQn_Handler 0x00013159 Thumb Code 22 drv_gpio.o(i.app_EXTI_INT6_IRQn_Handler) - app_EXTI_INT7_IRQn_Handler 0x00013175 Thumb Code 22 drv_gpio.o(i.app_EXTI_INT7_IRQn_Handler) - app_HardFault_Handler 0x00013191 Thumb Code 12 drv_common.o(i.app_HardFault_Handler) - app_I2C0_IRQn_Handler 0x000131d9 Thumb Code 14 drv_i2c_slave.o(i.app_I2C0_IRQn_Handler) - app_I2C1_IRQn_Handler 0x000131f1 Thumb Code 8 drv_i2c_master.o(i.app_I2C1_IRQn_Handler) - app_LCDC_IRQn_Handler 0x00013201 Thumb Code 146 hal_internal_vsync.o(i.app_LCDC_IRQn_Handler) - app_MEMC_IRQn_Handler 0x00013331 Thumb Code 132 drv_memc.o(i.app_MEMC_IRQn_Handler) - app_MIPI_RX_IRQn_Handler 0x000133b9 Thumb Code 232 drv_dsi_rx.o(i.app_MIPI_RX_IRQn_Handler) - app_MIPI_TX_IRQn_Handler 0x00013651 Thumb Code 56 drv_dsi_tx.o(i.app_MIPI_TX_IRQn_Handler) - app_PWMDET_IRQn_Handler 0x000136f1 Thumb Code 62 drv_pwm.o(i.app_PWMDET_IRQn_Handler) - app_SPIM_IRQn_Handler 0x00013739 Thumb Code 34 drv_spi_master.o(i.app_SPIM_IRQn_Handler) - app_SPIS_IRQn_Handler 0x00013769 Thumb Code 500 hal_spi_slave.o(i.app_SPIS_IRQn_Handler) - app_SWIRE_IRQn_Handler 0x00013969 Thumb Code 28 drv_swire.o(i.app_SWIRE_IRQn_Handler) - app_SysTick_Handler 0x00013989 Thumb Code 20 drv_common.o(i.app_SysTick_Handler) - app_TIMER0_IRQn_Handler 0x000139a1 Thumb Code 10 drv_timer.o(i.app_TIMER0_IRQn_Handler) - app_TIMER1_IRQn_Handler 0x000139ab Thumb Code 10 drv_timer.o(i.app_TIMER1_IRQn_Handler) - app_TIMER2_IRQn_Handler 0x000139b5 Thumb Code 10 drv_timer.o(i.app_TIMER2_IRQn_Handler) - app_TIMER3_IRQn_Handler 0x000139bf Thumb Code 10 drv_timer.o(i.app_TIMER3_IRQn_Handler) - app_UART_IRQn_Handler 0x000139c9 Thumb Code 8 drv_uart.o(i.app_UART_IRQn_Handler) - app_VIDC_IRQn_Handler 0x000139d1 Thumb Code 22 drv_vidc.o(i.app_VIDC_IRQn_Handler) - app_VPRE_IRQn_Handler 0x000139ed Thumb Code 22 drv_rxbr.o(i.app_VPRE_IRQn_Handler) - app_WDG_IRQn_Handler 0x00013a09 Thumb Code 52 drv_wdg.o(i.app_WDG_IRQn_Handler) - app_dma_irq_handler 0x00013a41 Thumb Code 10 drv_dma.o(i.app_dma_irq_handler) - app_fls_ctrl_Handler 0x00013a51 Thumb Code 38 norflash.o(i.app_fls_ctrl_Handler) - board_Init 0x00013a81 Thumb Code 30 board.o(i.board_Init) - calc_framebuffer_setting 0x00013aa5 Thumb Code 1416 hal_internal_vsync.o(i.calc_framebuffer_setting) - ceil 0x00014031 Thumb Code 180 ceil.o(i.ceil) - dcs_packet_fifo_alloc 0x000141a9 Thumb Code 80 dcs_packet_fifo.o(i.dcs_packet_fifo_alloc) - dcs_packet_fifo_init 0x00014201 Thumb Code 18 dcs_packet_fifo.o(i.dcs_packet_fifo_init) - dcs_packet_free_fifo_header 0x00014219 Thumb Code 60 dcs_packet_fifo.o(i.dcs_packet_free_fifo_header) - dcs_packet_get_fifo_header 0x0001425d Thumb Code 26 dcs_packet_fifo.o(i.dcs_packet_get_fifo_header) - delayMs 0x000142ad Thumb Code 24 tau_delay.o(i.delayMs) - delayUs 0x000142c5 Thumb Code 34 tau_delay.o(i.delayUs) - drv_ap_rst_trig_edge_detect 0x000142e9 Thumb Code 46 drv_sys_cfg.o(i.drv_ap_rst_trig_edge_detect) - drv_chip_info_get_info 0x00014321 Thumb Code 6 drv_chip_info.o(i.drv_chip_info_get_info) - drv_chip_info_init 0x0001432d Thumb Code 56 drv_chip_info.o(i.drv_chip_info_init) - drv_chip_rx_info_check 0x0001436d Thumb Code 98 drv_chip_info.o(i.drv_chip_rx_info_check) - drv_chip_rx_init_done 0x0001441d Thumb Code 16 drv_chip_info.o(i.drv_chip_rx_init_done) - drv_common_enable_systick 0x00014431 Thumb Code 70 drv_common.o(i.drv_common_enable_systick) - drv_common_system_init 0x00014489 Thumb Code 8 drv_common.o(i.drv_common_system_init) - drv_crgu_config_reset_modules 0x00014491 Thumb Code 10 drv_crgu.o(i.drv_crgu_config_reset_modules) - drv_crgu_set_ahb_pre_div 0x000144a1 Thumb Code 14 drv_crgu.o(i.drv_crgu_set_ahb_pre_div) - drv_crgu_set_ahb_src 0x000144b5 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_ahb_src) - drv_crgu_set_clock 0x000144c9 Thumb Code 26 drv_crgu.o(i.drv_crgu_set_clock) - drv_crgu_set_dpi_mux_src 0x000144e9 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_dpi_mux_src) - drv_crgu_set_dpi_pre_div 0x000144fd Thumb Code 18 drv_crgu.o(i.drv_crgu_set_dpi_pre_div) - drv_crgu_set_dpi_pre_src 0x00014515 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_dpi_pre_src) - drv_crgu_set_dsc_core_div 0x00014529 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_dsc_core_div) - drv_crgu_set_dsco_src 0x0001453d Thumb Code 16 drv_crgu.o(i.drv_crgu_set_dsco_src) - drv_crgu_set_dsco_src_div 0x00014551 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_dsco_src_div) - drv_crgu_set_fb_div 0x00014565 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_fb_div) - drv_crgu_set_fb_src 0x00014579 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_fb_src) - drv_crgu_set_lcdc_div 0x0001458d Thumb Code 16 drv_crgu.o(i.drv_crgu_set_lcdc_div) - drv_crgu_set_lcdc_src 0x000145a1 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_lcdc_src) - drv_crgu_set_mipi_cfg_src 0x000145b5 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_mipi_cfg_src) - drv_crgu_set_mipi_ref_src 0x000145c9 Thumb Code 18 drv_crgu.o(i.drv_crgu_set_mipi_ref_src) - drv_crgu_set_reset 0x000145e1 Thumb Code 20 drv_crgu.o(i.drv_crgu_set_reset) - drv_crgu_set_rxbr_div 0x000145f9 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_rxbr_div) - drv_crgu_set_rxbr_src 0x0001460d Thumb Code 16 drv_crgu.o(i.drv_crgu_set_rxbr_src) - drv_crgu_set_vidc_src 0x00014621 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_vidc_src) - drv_dma_clear_flag 0x00014635 Thumb Code 24 drv_dma.o(i.drv_dma_clear_flag) - drv_dma_get_channel_flag 0x0001464d Thumb Code 12 drv_dma.o(i.drv_dma_get_channel_flag) - drv_dma_irq_handler 0x00014659 Thumb Code 138 drv_dma.o(i.drv_dma_irq_handler) - drv_dsc_dec_convert_pps_rc_parameter 0x000146e9 Thumb Code 54 drv_dsc_dec.o(i.drv_dsc_dec_convert_pps_rc_parameter) - drv_dsc_dec_disable 0x0001471f Thumb Code 12 drv_dsc_dec.o(i.drv_dsc_dec_disable) - drv_dsc_dec_enable 0x0001472d Thumb Code 88 drv_dsc_dec.o(i.drv_dsc_dec_enable) - drv_dsc_dec_get_nslc 0x000147a1 Thumb Code 10 drv_dsc_dec.o(i.drv_dsc_dec_get_nslc) - drv_dsc_dec_set_u8_pps 0x000147ab Thumb Code 40 drv_dsc_dec.o(i.drv_dsc_dec_set_u8_pps) - drv_dsi_rx_calc_ipi_tx_delay 0x000147d5 Thumb Code 244 drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) - drv_dsi_rx_enable_irq 0x000148d9 Thumb Code 58 drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) - drv_dsi_rx_get_bta_status 0x00014919 Thumb Code 14 drv_dsi_rx.o(i.drv_dsi_rx_get_bta_status) - drv_dsi_rx_get_compression_en 0x00014995 Thumb Code 8 drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en) - drv_dsi_rx_get_max_ret_size 0x0001499d Thumb Code 6 drv_dsi_rx.o(i.drv_dsi_rx_get_max_ret_size) - drv_dsi_rx_power_up 0x000149a3 Thumb Code 14 drv_dsi_rx.o(i.drv_dsi_rx_power_up) - drv_dsi_rx_set_ctrl_cfg 0x000149b1 Thumb Code 32 drv_dsi_rx.o(i.drv_dsi_rx_set_ctrl_cfg) - drv_dsi_rx_set_ddi_cfg 0x000149d1 Thumb Code 16 drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) - drv_dsi_rx_set_inten 0x000149e1 Thumb Code 4 drv_dsi_rx.o(i.drv_dsi_rx_set_inten) - drv_dsi_rx_set_ipi_cfg 0x000149e5 Thumb Code 16 drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_cfg) - drv_dsi_rx_set_lane_swap 0x000149f5 Thumb Code 70 drv_dsi_rx.o(i.drv_dsi_rx_set_lane_swap) - drv_dsi_rx_set_resp_cnt 0x00014a3b Thumb Code 38 drv_dsi_rx.o(i.drv_dsi_rx_set_resp_cnt) - drv_dsi_rx_set_up_phy 0x00014a61 Thumb Code 256 drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) - drv_dsi_rx_shut_down 0x00014b65 Thumb Code 14 drv_dsi_rx.o(i.drv_dsi_rx_shut_down) - drv_dsi_tx_command_header 0x00014b73 Thumb Code 20 drv_dsi_tx.o(i.drv_dsi_tx_command_header) - drv_dsi_tx_command_mode_cfg 0x00014b87 Thumb Code 108 drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg) - drv_dsi_tx_command_put_payload 0x00014bf3 Thumb Code 4 drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) - drv_dsi_tx_config_eotp 0x00014bf7 Thumb Code 24 drv_dsi_tx.o(i.drv_dsi_tx_config_eotp) - drv_dsi_tx_config_int 0x00014c0f Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_config_int) - drv_dsi_tx_dpi_lpcmd_time 0x00014c17 Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_dpi_lpcmd_time) - drv_dsi_tx_dpi_mode 0x00014c1f Thumb Code 10 drv_dsi_tx.o(i.drv_dsi_tx_dpi_mode) - drv_dsi_tx_dpi_polarity 0x00014c29 Thumb Code 36 drv_dsi_tx.o(i.drv_dsi_tx_dpi_polarity) - drv_dsi_tx_edpi_cmd_size 0x00014c4d Thumb Code 4 drv_dsi_tx.o(i.drv_dsi_tx_edpi_cmd_size) - drv_dsi_tx_get_cmd_status 0x00014c51 Thumb Code 4 drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) - drv_dsi_tx_mode 0x00014c55 Thumb Code 4 drv_dsi_tx.o(i.drv_dsi_tx_mode) - drv_dsi_tx_phy_clock_lane_auto_lp 0x00014c59 Thumb Code 24 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp) - drv_dsi_tx_phy_clock_lane_req_hs 0x00014c71 Thumb Code 26 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs) - drv_dsi_tx_phy_lane_mode 0x00014c8b Thumb Code 12 drv_dsi_tx.o(i.drv_dsi_tx_phy_lane_mode) - drv_dsi_tx_phy_status_ready 0x00014c97 Thumb Code 100 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready) - drv_dsi_tx_phy_status_stopstate 0x00014cfb Thumb Code 62 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) - drv_dsi_tx_phy_test_setup 0x00014d39 Thumb Code 308 drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) - drv_dsi_tx_phy_time_cfg 0x00014e6d Thumb Code 30 drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg) - drv_dsi_tx_powerup 0x00014e8b Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_powerup) - drv_dsi_tx_response_mode 0x00014e93 Thumb Code 28 drv_dsi_tx.o(i.drv_dsi_tx_response_mode) - drv_dsi_tx_set_bta_ack 0x00014eaf Thumb Code 24 drv_dsi_tx.o(i.drv_dsi_tx_set_bta_ack) - drv_dsi_tx_set_esc_div 0x00014ec7 Thumb Code 12 drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) - drv_dsi_tx_set_int 0x00014ed5 Thumb Code 58 drv_dsi_tx.o(i.drv_dsi_tx_set_int) - drv_dsi_tx_set_time_out_div 0x00014f15 Thumb Code 16 drv_dsi_tx.o(i.drv_dsi_tx_set_time_out_div) - drv_dsi_tx_set_video_chunk 0x00014f25 Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_set_video_chunk) - drv_dsi_tx_set_video_timing 0x00014f2d Thumb Code 34 drv_dsi_tx.o(i.drv_dsi_tx_set_video_timing) - drv_dsi_tx_shutdown 0x00014f4f Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_shutdown) - drv_dsi_tx_timeout_cfg 0x00014f57 Thumb Code 38 drv_dsi_tx.o(i.drv_dsi_tx_timeout_cfg) - drv_dsi_tx_video_mode_cfg 0x00014f7d Thumb Code 170 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_cfg) - drv_dsi_tx_video_mode_disable_hact_cmd 0x00015027 Thumb Code 22 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_disable_hact_cmd) - drv_dsi_tx_video_mode_set_lp_cmd 0x0001503d Thumb Code 24 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_set_lp_cmd) - drv_efuse_enter_inactive 0x00015055 Thumb Code 46 drv_efuse.o(i.drv_efuse_enter_inactive) - drv_efuse_int_enable 0x00015083 Thumb Code 12 drv_efuse.o(i.drv_efuse_int_enable) - drv_efuse_read 0x0001508f Thumb Code 50 drv_efuse.o(i.drv_efuse_read) - drv_efuse_read_req 0x000150c1 Thumb Code 24 drv_efuse.o(i.drv_efuse_read_req) - drv_gpio_set_ioe 0x000150d9 Thumb Code 26 drv_gpio.o(i.drv_gpio_set_ioe) - drv_gpio_set_mode0 0x000150f9 Thumb Code 12 drv_gpio.o(i.drv_gpio_set_mode0) - drv_gpio_set_mode1 0x00015109 Thumb Code 12 drv_gpio.o(i.drv_gpio_set_mode1) - drv_gpio_set_mode2 0x00015119 Thumb Code 12 drv_gpio.o(i.drv_gpio_set_mode2) - drv_gpio_set_mode3 0x00015129 Thumb Code 12 drv_gpio.o(i.drv_gpio_set_mode3) - drv_lcdc_config_bypass 0x00015159 Thumb Code 24 drv_lcdc.o(i.drv_lcdc_config_bypass) - drv_lcdc_config_ccm 0x00015171 Thumb Code 48 drv_lcdc.o(i.drv_lcdc_config_ccm) - drv_lcdc_config_disp_mode 0x000151a1 Thumb Code 22 drv_lcdc.o(i.drv_lcdc_config_disp_mode) - drv_lcdc_config_dpi_polarity 0x000151b7 Thumb Code 36 drv_lcdc.o(i.drv_lcdc_config_dpi_polarity) - drv_lcdc_config_dpi_timing 0x000151db Thumb Code 38 drv_lcdc.o(i.drv_lcdc_config_dpi_timing) - drv_lcdc_config_edpi_mode 0x00015201 Thumb Code 22 drv_lcdc.o(i.drv_lcdc_config_edpi_mode) - drv_lcdc_config_endianness 0x00015217 Thumb Code 22 drv_lcdc.o(i.drv_lcdc_config_endianness) - drv_lcdc_config_input_size 0x0001522d Thumb Code 12 drv_lcdc.o(i.drv_lcdc_config_input_size) - drv_lcdc_config_int 0x00015239 Thumb Code 30 drv_lcdc.o(i.drv_lcdc_config_int) - drv_lcdc_config_int_single 0x00015257 Thumb Code 34 drv_lcdc.o(i.drv_lcdc_config_int_single) - drv_lcdc_config_overwrite 0x00015279 Thumb Code 34 drv_lcdc.o(i.drv_lcdc_config_overwrite) - drv_lcdc_config_overwrite_rgb 0x0001529b Thumb Code 12 drv_lcdc.o(i.drv_lcdc_config_overwrite_rgb) - drv_lcdc_config_partial_display_area 0x000152a7 Thumb Code 26 drv_lcdc.o(i.drv_lcdc_config_partial_display_area) - drv_lcdc_config_partial_display_enable 0x000152c1 Thumb Code 34 drv_lcdc.o(i.drv_lcdc_config_partial_display_enable) - drv_lcdc_config_scale_up_coef 0x000152e3 Thumb Code 26 drv_lcdc.o(i.drv_lcdc_config_scale_up_coef) - drv_lcdc_config_scale_up_step 0x000152fd Thumb Code 12 drv_lcdc.o(i.drv_lcdc_config_scale_up_step) - drv_lcdc_config_src_parameter 0x00015309 Thumb Code 76 drv_lcdc.o(i.drv_lcdc_config_src_parameter) - drv_lcdc_config_thresh 0x00015355 Thumb Code 6 drv_lcdc.o(i.drv_lcdc_config_thresh) - drv_lcdc_ctrl_flow 0x0001535b Thumb Code 18 drv_lcdc.o(i.drv_lcdc_ctrl_flow) - drv_lcdc_enable_shadow_reg 0x0001536d Thumb Code 32 drv_lcdc.o(i.drv_lcdc_enable_shadow_reg) - drv_lcdc_set_int 0x0001538d Thumb Code 58 drv_lcdc.o(i.drv_lcdc_set_int) - drv_lcdc_set_prefetch 0x000153cd Thumb Code 24 drv_lcdc.o(i.drv_lcdc_set_prefetch) - drv_lcdc_set_video_hw_mode 0x000153e5 Thumb Code 20 drv_lcdc.o(i.drv_lcdc_set_video_hw_mode) - drv_lcdc_start 0x000153f9 Thumb Code 32 drv_lcdc.o(i.drv_lcdc_start) - drv_memc_clear_status 0x00015419 Thumb Code 12 drv_memc.o(i.drv_memc_clear_status) - drv_memc_enable_irq 0x00015425 Thumb Code 58 drv_memc.o(i.drv_memc_enable_irq) - drv_memc_gen_a_tear_signal 0x00015465 Thumb Code 12 drv_memc.o(i.drv_memc_gen_a_tear_signal) - drv_memc_get_status 0x00015471 Thumb Code 18 drv_memc.o(i.drv_memc_get_status) - drv_memc_rate_transfer_sel 0x00015483 Thumb Code 16 drv_memc.o(i.drv_memc_rate_transfer_sel) - drv_memc_sel_vsync 0x00015493 Thumb Code 14 drv_memc.o(i.drv_memc_sel_vsync) - drv_memc_set_active_height 0x000154a1 Thumb Code 14 drv_memc.o(i.drv_memc_set_active_height) - drv_memc_set_data_mode 0x000154b5 Thumb Code 12 drv_memc.o(i.drv_memc_set_data_mode) - drv_memc_set_double_buffer 0x000154c1 Thumb Code 16 drv_memc.o(i.drv_memc_set_double_buffer) - drv_memc_set_double_buffer_reverse 0x000154d1 Thumb Code 18 drv_memc.o(i.drv_memc_set_double_buffer_reverse) - drv_memc_set_fs_en_conditions 0x000154e3 Thumb Code 16 drv_memc.o(i.drv_memc_set_fs_en_conditions) - drv_memc_set_inten 0x000154f3 Thumb Code 20 drv_memc.o(i.drv_memc_set_inten) - drv_memc_set_lcdc_st_conditions 0x00015509 Thumb Code 18 drv_memc.o(i.drv_memc_set_lcdc_st_conditions) - drv_memc_set_ltpo_mode 0x00015521 Thumb Code 26 drv_memc.o(i.drv_memc_set_ltpo_mode) - drv_memc_set_tear_mode 0x0001553b Thumb Code 14 drv_memc.o(i.drv_memc_set_tear_mode) - drv_memc_set_tear_waveform 0x00015549 Thumb Code 34 drv_memc.o(i.drv_memc_set_tear_waveform) - drv_memc_set_vidc_sync_cnt 0x00015571 Thumb Code 14 drv_memc.o(i.drv_memc_set_vidc_sync_cnt) - drv_param_init_get_ccm 0x00015581 Thumb Code 4 drv_param_init.o(i.drv_param_init_get_ccm) - drv_param_init_get_scld_filter_h 0x00015589 Thumb Code 12 drv_param_init.o(i.drv_param_init_get_scld_filter_h) - drv_param_init_get_scld_filter_v 0x0001559d Thumb Code 12 drv_param_init.o(i.drv_param_init_get_scld_filter_v) - drv_param_init_get_sclu_filter 0x000155b1 Thumb Code 4 drv_param_init.o(i.drv_param_init_get_sclu_filter) - drv_param_init_set_ccm 0x000155b9 Thumb Code 14 drv_param_init.o(i.drv_param_init_set_ccm) - drv_param_init_set_scld_filter 0x000155cd Thumb Code 92 drv_param_init.o(i.drv_param_init_set_scld_filter) - drv_param_p2r_filter_init 0x00015631 Thumb Code 30 drv_param_init.o(i.drv_param_p2r_filter_init) - drv_phy_enable_calibration 0x00015655 Thumb Code 12 drv_phy_common.o(i.drv_phy_enable_calibration) - drv_phy_get_calibration 0x00015665 Thumb Code 50 drv_phy_common.o(i.drv_phy_get_calibration) - drv_phy_get_pll_para 0x000156a1 Thumb Code 88 drv_phy_common.o(i.drv_phy_get_pll_para) - drv_phy_get_rate_para 0x00015701 Thumb Code 76 drv_phy_common.o(i.drv_phy_get_rate_para) - drv_phy_test_clear 0x00015755 Thumb Code 16 drv_phy_common.o(i.drv_phy_test_clear) - drv_phy_test_lock 0x00015765 Thumb Code 24 drv_phy_common.o(i.drv_phy_test_lock) - drv_phy_test_write_1_byte 0x0001577d Thumb Code 32 drv_phy_common.o(i.drv_phy_test_write_1_byte) - drv_phy_test_write_2_byte 0x0001579d Thumb Code 38 drv_phy_common.o(i.drv_phy_test_write_2_byte) - drv_phy_test_write_code 0x000157c3 Thumb Code 30 drv_phy_common.o(i.drv_phy_test_write_code) - drv_pwr_set_pvd_mode 0x00015801 Thumb Code 18 drv_pwr.o(i.drv_pwr_set_pvd_mode) - drv_pwr_set_system_clk_src 0x00015819 Thumb Code 44 drv_pwr.o(i.drv_pwr_set_system_clk_src) - drv_rxbr_clear_pkt_buffer 0x00015897 Thumb Code 10 drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) - drv_rxbr_clear_status0 0x000158a1 Thumb Code 4 drv_rxbr.o(i.drv_rxbr_clear_status0) - drv_rxbr_enable_irq 0x000158a5 Thumb Code 90 drv_rxbr.o(i.drv_rxbr_enable_irq) - drv_rxbr_frame_drop_cfg 0x00015901 Thumb Code 16 drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) - drv_rxbr_get_clk 0x00015915 Thumb Code 66 drv_rxbr.o(i.drv_rxbr_get_clk) - drv_rxbr_get_col_addr 0x00015979 Thumb Code 4 drv_rxbr.o(i.drv_rxbr_get_col_addr) - drv_rxbr_get_page_addr 0x0001598f Thumb Code 4 drv_rxbr.o(i.drv_rxbr_get_page_addr) - drv_rxbr_get_pkt_buf_error_status 0x00015993 Thumb Code 12 drv_rxbr.o(i.drv_rxbr_get_pkt_buf_error_status) - drv_rxbr_hline_rcv0_cfg 0x000159c7 Thumb Code 12 drv_rxbr.o(i.drv_rxbr_hline_rcv0_cfg) - drv_rxbr_hline_rcv1_cfg 0x000159d3 Thumb Code 12 drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg) - drv_rxbr_hline_rcv_cfg 0x000159df Thumb Code 8 drv_rxbr.o(i.drv_rxbr_hline_rcv_cfg) - drv_rxbr_register_irq0_callback 0x000159e9 Thumb Code 6 drv_rxbr.o(i.drv_rxbr_register_irq0_callback) - drv_rxbr_register_irq1_callback 0x000159f5 Thumb Code 6 drv_rxbr.o(i.drv_rxbr_register_irq1_callback) - drv_rxbr_set_ack_pkt_header 0x00015a01 Thumb Code 20 drv_rxbr.o(i.drv_rxbr_set_ack_pkt_header) - drv_rxbr_set_color_format 0x00015a15 Thumb Code 20 drv_rxbr.o(i.drv_rxbr_set_color_format) - drv_rxbr_set_filter_regs 0x00015a29 Thumb Code 18 drv_rxbr.o(i.drv_rxbr_set_filter_regs) - drv_rxbr_set_inten 0x00015a3b Thumb Code 20 drv_rxbr.o(i.drv_rxbr_set_inten) - drv_rxbr_set_ltpo_drop_th 0x00015a4f Thumb Code 16 drv_rxbr.o(i.drv_rxbr_set_ltpo_drop_th) - drv_rxbr_set_usr_cfg 0x00015a5f Thumb Code 38 drv_rxbr.o(i.drv_rxbr_set_usr_cfg) - drv_rxbr_set_usr_col 0x00015a85 Thumb Code 8 drv_rxbr.o(i.drv_rxbr_set_usr_col) - drv_rxbr_set_usr_row 0x00015a8d Thumb Code 8 drv_rxbr.o(i.drv_rxbr_set_usr_row) - drv_swire_set_int 0x00015a95 Thumb Code 76 drv_swire.o(i.drv_swire_set_int) - drv_sys_cfg_clear_all_int 0x00015ae9 Thumb Code 8 drv_sys_cfg.o(i.drv_sys_cfg_clear_all_int) - drv_sys_cfg_clear_pending 0x00015af5 Thumb Code 32 drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) - drv_sys_cfg_sel_ap_rst_lvl_trig 0x00015b1d Thumb Code 18 drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_lvl_trig) - drv_sys_cfg_set_int 0x00015b35 Thumb Code 30 drv_sys_cfg.o(i.drv_sys_cfg_set_int) - drv_timer_enable 0x00015b73 Thumb Code 32 drv_timer.o(i.drv_timer_enable) - drv_timer_get_instance 0x00015b95 Thumb Code 10 drv_timer.o(i.drv_timer_get_instance) - drv_timer_set_compare_val 0x00015be9 Thumb Code 16 drv_timer.o(i.drv_timer_set_compare_val) - drv_timer_set_int 0x00015bf9 Thumb Code 80 drv_timer.o(i.drv_timer_set_int) - drv_tx_phy_test_enter 0x00015c57 Thumb Code 28 drv_dsi_tx.o(i.drv_tx_phy_test_enter) - drv_tx_phy_test_exit 0x00015c73 Thumb Code 28 drv_dsi_tx.o(i.drv_tx_phy_test_exit) - drv_vidc_clear_irq 0x00015cc5 Thumb Code 8 drv_vidc.o(i.drv_vidc_clear_irq) - drv_vidc_enable 0x00015ccd Thumb Code 24 drv_vidc.o(i.drv_vidc_enable) - drv_vidc_enable_irq 0x00015ce5 Thumb Code 58 drv_vidc.o(i.drv_vidc_enable_irq) - drv_vidc_get_irq_status 0x00015d25 Thumb Code 18 drv_vidc.o(i.drv_vidc_get_irq_status) - drv_vidc_init_module_enable 0x00015d39 Thumb Code 36 drv_vidc.o(i.drv_vidc_init_module_enable) - drv_vidc_register_callback 0x00015d61 Thumb Code 6 drv_vidc.o(i.drv_vidc_register_callback) - drv_vidc_reset 0x00015d6d Thumb Code 6 drv_vidc.o(i.drv_vidc_reset) - drv_vidc_set_dst_parameter 0x00015d73 Thumb Code 60 drv_vidc.o(i.drv_vidc_set_dst_parameter) - drv_vidc_set_irqen 0x00015daf Thumb Code 20 drv_vidc.o(i.drv_vidc_set_irqen) - drv_vidc_set_mirror 0x00015dc3 Thumb Code 16 drv_vidc.o(i.drv_vidc_set_mirror) - drv_vidc_set_p2r_hcoef0 0x00015dd3 Thumb Code 8 drv_vidc.o(i.drv_vidc_set_p2r_hcoef0) - drv_vidc_set_p2r_hinitb 0x00015ddb Thumb Code 38 drv_vidc.o(i.drv_vidc_set_p2r_hinitb) - drv_vidc_set_p2r_hinitr 0x00015e01 Thumb Code 38 drv_vidc.o(i.drv_vidc_set_p2r_hinitr) - drv_vidc_set_pentile_swap 0x00015e29 Thumb Code 18 drv_vidc.o(i.drv_vidc_set_pentile_swap) - drv_vidc_set_pu_ctrl 0x00015e41 Thumb Code 10 drv_vidc.o(i.drv_vidc_set_pu_ctrl) - drv_vidc_set_rotation 0x00015e4b Thumb Code 16 drv_vidc.o(i.drv_vidc_set_rotation) - drv_vidc_set_scld_hcoef0 0x00015e5b Thumb Code 10 drv_vidc.o(i.drv_vidc_set_scld_hcoef0) - drv_vidc_set_scld_hcoef1 0x00015e65 Thumb Code 10 drv_vidc.o(i.drv_vidc_set_scld_hcoef1) - drv_vidc_set_scld_step 0x00015e6f Thumb Code 18 drv_vidc.o(i.drv_vidc_set_scld_step) - drv_vidc_set_scld_vcoef0 0x00015e81 Thumb Code 10 drv_vidc.o(i.drv_vidc_set_scld_vcoef0) - drv_vidc_set_scld_vcoef1 0x00015e8b Thumb Code 10 drv_vidc.o(i.drv_vidc_set_scld_vcoef1) - drv_vidc_set_src_parameter 0x00015e95 Thumb Code 22 drv_vidc.o(i.drv_vidc_set_src_parameter) - drv_wdg_clear_counter 0x00015ead Thumb Code 12 drv_wdg.o(i.drv_wdg_clear_counter) - drv_wdg_set_int 0x00015edd Thumb Code 60 drv_wdg.o(i.drv_wdg_set_int) - fls_clr_interrupt_flag 0x00015f1d Thumb Code 10 drv_fls.o(i.fls_clr_interrupt_flag) - fputc 0x00015f27 Thumb Code 20 tau_log.o(i.fputc) - hal_dsi_rx_ctrl_create_handle 0x00015f8d Thumb Code 48 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) - hal_dsi_rx_ctrl_dsc_async_handler 0x00015fc1 Thumb Code 34 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dsc_async_handler) - hal_dsi_rx_ctrl_gen_a_tear_signal 0x00015fe9 Thumb Code 32 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_gen_a_tear_signal) - hal_dsi_rx_ctrl_get_max_ret_size 0x00016011 Thumb Code 30 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) - hal_dsi_rx_ctrl_init 0x00016039 Thumb Code 144 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) - hal_dsi_rx_ctrl_pre_init_pps 0x00016829 Thumb Code 56 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) - hal_dsi_rx_ctrl_restart 0x00016865 Thumb Code 72 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) - hal_dsi_rx_ctrl_send_ack_cmd 0x000168b5 Thumb Code 212 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) - hal_dsi_rx_ctrl_set_cus_esc_clk 0x000169a5 Thumb Code 34 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk) - hal_dsi_rx_ctrl_set_cus_scld_filter 0x000169d1 Thumb Code 98 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_scld_filter) - hal_dsi_rx_ctrl_set_cus_sync_line 0x00016a3d Thumb Code 44 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_sync_line) - hal_dsi_rx_ctrl_set_tear_mode_ex 0x00016b1b Thumb Code 14 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_tear_mode_ex) - hal_dsi_rx_ctrl_start 0x00016b29 Thumb Code 46 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) - hal_dsi_rx_ctrl_toggle_resolution 0x00016b65 Thumb Code 28 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) - hal_dsi_tx_ctrl_create_handle 0x00017171 Thumb Code 34 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) - hal_dsi_tx_ctrl_enter_init_panel_mode 0x0001719d Thumb Code 68 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_enter_init_panel_mode) - hal_dsi_tx_ctrl_exit_init_panel_mode 0x000171e9 Thumb Code 32 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_exit_init_panel_mode) - hal_dsi_tx_ctrl_init 0x00017211 Thumb Code 154 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) - hal_dsi_tx_ctrl_panel_reset_pin 0x000172d9 Thumb Code 12 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_panel_reset_pin) - hal_dsi_tx_ctrl_set_ccm 0x000172e5 Thumb Code 28 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_ccm) - hal_dsi_tx_ctrl_set_overwrite_rgb 0x00017305 Thumb Code 16 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb) - hal_dsi_tx_ctrl_set_partial_disp 0x00017319 Thumb Code 12 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_partial_disp) - hal_dsi_tx_ctrl_set_partial_disp_area 0x00017329 Thumb Code 30 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_partial_disp_area) - hal_dsi_tx_ctrl_start 0x0001734d Thumb Code 150 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) - hal_dsi_tx_ctrl_write_array_cmd 0x000173f5 Thumb Code 236 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) - hal_dsi_tx_ctrl_write_cmd 0x000174e5 Thumb Code 200 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) - hal_gpio_init_output 0x00017795 Thumb Code 34 hal_gpio.o(i.hal_gpio_init_output) - hal_gpio_set_mode 0x000177bd Thumb Code 90 hal_gpio.o(i.hal_gpio_set_mode) - hal_gpio_set_output_data 0x0001781d Thumb Code 8 hal_gpio.o(i.hal_gpio_set_output_data) - hal_internal_check_video_auto_sync 0x00017825 Thumb Code 18 hal_internal_vsync.o(i.hal_internal_check_video_auto_sync) - hal_internal_init_memc 0x0001783d Thumb Code 170 hal_internal_vsync.o(i.hal_internal_init_memc) - hal_internal_rx_dcs_async_handler 0x00017939 Thumb Code 42 hal_internal_vsync.o(i.hal_internal_rx_dcs_async_handler) - hal_internal_rx_dcs_polling 0x00017965 Thumb Code 78 hal_internal_vsync.o(i.hal_internal_rx_dcs_polling) - hal_internal_sync_get_fb_setting 0x000179bd Thumb Code 12 hal_internal_vsync.o(i.hal_internal_sync_get_fb_setting) - hal_internal_sync_get_hight_performan_mode 0x000179cd Thumb Code 10 hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) - hal_internal_sync_input_resolution_change 0x000179dd Thumb Code 438 hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) - hal_internal_vsync_deinit 0x00017c09 Thumb Code 30 hal_internal_vsync.o(i.hal_internal_vsync_deinit) - hal_internal_vsync_get_sync_line 0x00017c31 Thumb Code 18 hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) - hal_internal_vsync_get_tear_mode 0x00017c49 Thumb Code 6 hal_internal_vsync.o(i.hal_internal_vsync_get_tear_mode) - hal_internal_vsync_get_tx_state 0x00017c55 Thumb Code 6 hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) - hal_internal_vsync_init_rx 0x00017c61 Thumb Code 274 hal_internal_vsync.o(i.hal_internal_vsync_init_rx) - hal_internal_vsync_init_tx 0x00017da1 Thumb Code 172 hal_internal_vsync.o(i.hal_internal_vsync_init_tx) - hal_internal_vsync_set_auto_hw_filter 0x00017e51 Thumb Code 132 hal_internal_vsync.o(i.hal_internal_vsync_set_auto_hw_filter) - hal_internal_vsync_set_rx_state 0x00017ee1 Thumb Code 30 hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) - hal_internal_vsync_set_sync_line 0x00017f05 Thumb Code 64 hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) - hal_internal_vsync_set_tear_mode 0x00017f49 Thumb Code 72 hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) - hal_internal_vsync_set_tx_state 0x00017f99 Thumb Code 122 hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) - hal_intl_svs_deinit_tx 0x0001801d Thumb Code 10 hal_internal_soft_sync.o(i.hal_intl_svs_deinit_tx) - hal_intl_svs_handle 0x0001802d Thumb Code 24 hal_internal_soft_sync.o(i.hal_intl_svs_handle) - hal_intl_svs_init_rx 0x00018051 Thumb Code 108 hal_internal_soft_sync.o(i.hal_intl_svs_init_rx) - hal_intl_svs_init_tx 0x000180c9 Thumb Code 16 hal_internal_soft_sync.o(i.hal_intl_svs_init_tx) - hal_intl_svs_set_sync_coef 0x000180dd Thumb Code 8 hal_internal_soft_sync.o(i.hal_intl_svs_set_sync_coef) - hal_intl_svs_update_rxbr_clk 0x000180e9 Thumb Code 52 hal_internal_soft_sync.o(i.hal_intl_svs_update_rxbr_clk) - hal_system_enable_systick 0x00018591 Thumb Code 8 hal_system.o(i.hal_system_enable_systick) - hal_system_init 0x00018599 Thumb Code 104 hal_system.o(i.hal_system_init) - hal_system_init_console 0x00018621 Thumb Code 28 hal_system.o(i.hal_system_init_console) - hal_system_set_phy_calibration 0x0001863d Thumb Code 8 hal_system.o(i.hal_system_set_phy_calibration) - hal_uart_init 0x00018675 Thumb Code 126 hal_uart.o(i.hal_uart_init) - hal_uart_transmit_blocking 0x00018701 Thumb Code 12 hal_uart.o(i.hal_uart_transmit_blocking) - handle_init 0x00018711 Thumb Code 140 irq_redirect .o(i.handle_init) - main 0x0001892d Thumb Code 10 main.o(i.main) - sqrt 0x000196a9 Thumb Code 66 sqrt.o(i.sqrt) - panel_init_code 0x00019e4c Data 7814 ap_demo.o(.constdata) - Region$$Table$$Base 0x0001c1bc Number 0 anon$$obj.o(Region$$Table) - Region$$Table$$Limit 0x0001c1ec Number 0 anon$$obj.o(Region$$Table) + app_ADC_IRQn_Handler 0x000130a1 Thumb Code 22 drv_rxbr.o(i.app_ADC_IRQn_Handler) + app_AP_NRESET_IRQn_Handler 0x000130bd Thumb Code 32 drv_gpio.o(i.app_AP_NRESET_IRQn_Handler) + app_EXTI_INT0_IRQn_Handler 0x000130e1 Thumb Code 22 drv_gpio.o(i.app_EXTI_INT0_IRQn_Handler) + app_EXTI_INT1_IRQn_Handler 0x000130fd Thumb Code 22 drv_gpio.o(i.app_EXTI_INT1_IRQn_Handler) + app_EXTI_INT2_IRQn_Handler 0x00013119 Thumb Code 22 drv_gpio.o(i.app_EXTI_INT2_IRQn_Handler) + app_EXTI_INT3_IRQn_Handler 0x00013135 Thumb Code 22 drv_gpio.o(i.app_EXTI_INT3_IRQn_Handler) + app_EXTI_INT4_IRQn_Handler 0x00013151 Thumb Code 22 drv_gpio.o(i.app_EXTI_INT4_IRQn_Handler) + app_EXTI_INT5_IRQn_Handler 0x0001316d Thumb Code 22 drv_gpio.o(i.app_EXTI_INT5_IRQn_Handler) + app_EXTI_INT6_IRQn_Handler 0x00013189 Thumb Code 22 drv_gpio.o(i.app_EXTI_INT6_IRQn_Handler) + app_EXTI_INT7_IRQn_Handler 0x000131a5 Thumb Code 22 drv_gpio.o(i.app_EXTI_INT7_IRQn_Handler) + app_HardFault_Handler 0x000131c1 Thumb Code 12 drv_common.o(i.app_HardFault_Handler) + app_I2C0_IRQn_Handler 0x00013209 Thumb Code 14 drv_i2c_slave.o(i.app_I2C0_IRQn_Handler) + app_I2C1_IRQn_Handler 0x00013221 Thumb Code 8 drv_i2c_master.o(i.app_I2C1_IRQn_Handler) + app_LCDC_IRQn_Handler 0x00013231 Thumb Code 146 hal_internal_vsync.o(i.app_LCDC_IRQn_Handler) + app_MEMC_IRQn_Handler 0x00013361 Thumb Code 132 drv_memc.o(i.app_MEMC_IRQn_Handler) + app_MIPI_RX_IRQn_Handler 0x000133e9 Thumb Code 232 drv_dsi_rx.o(i.app_MIPI_RX_IRQn_Handler) + app_MIPI_TX_IRQn_Handler 0x00013681 Thumb Code 56 drv_dsi_tx.o(i.app_MIPI_TX_IRQn_Handler) + app_PWMDET_IRQn_Handler 0x00013721 Thumb Code 62 drv_pwm.o(i.app_PWMDET_IRQn_Handler) + app_SPIM_IRQn_Handler 0x00013769 Thumb Code 34 drv_spi_master.o(i.app_SPIM_IRQn_Handler) + app_SPIS_IRQn_Handler 0x00013799 Thumb Code 500 hal_spi_slave.o(i.app_SPIS_IRQn_Handler) + app_SWIRE_IRQn_Handler 0x00013999 Thumb Code 28 drv_swire.o(i.app_SWIRE_IRQn_Handler) + app_SysTick_Handler 0x000139b9 Thumb Code 20 drv_common.o(i.app_SysTick_Handler) + app_TIMER0_IRQn_Handler 0x000139d1 Thumb Code 10 drv_timer.o(i.app_TIMER0_IRQn_Handler) + app_TIMER1_IRQn_Handler 0x000139db Thumb Code 10 drv_timer.o(i.app_TIMER1_IRQn_Handler) + app_TIMER2_IRQn_Handler 0x000139e5 Thumb Code 10 drv_timer.o(i.app_TIMER2_IRQn_Handler) + app_TIMER3_IRQn_Handler 0x000139ef Thumb Code 10 drv_timer.o(i.app_TIMER3_IRQn_Handler) + app_UART_IRQn_Handler 0x000139f9 Thumb Code 8 drv_uart.o(i.app_UART_IRQn_Handler) + app_VIDC_IRQn_Handler 0x00013a01 Thumb Code 22 drv_vidc.o(i.app_VIDC_IRQn_Handler) + app_VPRE_IRQn_Handler 0x00013a1d Thumb Code 22 drv_rxbr.o(i.app_VPRE_IRQn_Handler) + app_WDG_IRQn_Handler 0x00013a39 Thumb Code 52 drv_wdg.o(i.app_WDG_IRQn_Handler) + app_dma_irq_handler 0x00013a71 Thumb Code 10 drv_dma.o(i.app_dma_irq_handler) + app_fls_ctrl_Handler 0x00013a81 Thumb Code 38 norflash.o(i.app_fls_ctrl_Handler) + board_Init 0x00013ab1 Thumb Code 30 board.o(i.board_Init) + calc_framebuffer_setting 0x00013ad5 Thumb Code 1416 hal_internal_vsync.o(i.calc_framebuffer_setting) + ceil 0x00014061 Thumb Code 180 ceil.o(i.ceil) + dcs_packet_fifo_alloc 0x000141d9 Thumb Code 80 dcs_packet_fifo.o(i.dcs_packet_fifo_alloc) + dcs_packet_fifo_init 0x00014231 Thumb Code 18 dcs_packet_fifo.o(i.dcs_packet_fifo_init) + dcs_packet_free_fifo_header 0x00014249 Thumb Code 60 dcs_packet_fifo.o(i.dcs_packet_free_fifo_header) + dcs_packet_get_fifo_header 0x0001428d Thumb Code 26 dcs_packet_fifo.o(i.dcs_packet_get_fifo_header) + delayMs 0x000142dd Thumb Code 24 tau_delay.o(i.delayMs) + delayUs 0x000142f5 Thumb Code 34 tau_delay.o(i.delayUs) + drv_ap_rst_trig_edge_detect 0x00014319 Thumb Code 46 drv_sys_cfg.o(i.drv_ap_rst_trig_edge_detect) + drv_chip_info_get_info 0x00014351 Thumb Code 6 drv_chip_info.o(i.drv_chip_info_get_info) + drv_chip_info_init 0x0001435d Thumb Code 56 drv_chip_info.o(i.drv_chip_info_init) + drv_chip_rx_info_check 0x0001439d Thumb Code 98 drv_chip_info.o(i.drv_chip_rx_info_check) + drv_chip_rx_init_done 0x0001444d Thumb Code 16 drv_chip_info.o(i.drv_chip_rx_init_done) + drv_common_enable_systick 0x00014461 Thumb Code 70 drv_common.o(i.drv_common_enable_systick) + drv_common_system_init 0x000144b9 Thumb Code 8 drv_common.o(i.drv_common_system_init) + drv_crgu_config_reset_modules 0x000144c1 Thumb Code 10 drv_crgu.o(i.drv_crgu_config_reset_modules) + drv_crgu_set_ahb_pre_div 0x000144d1 Thumb Code 14 drv_crgu.o(i.drv_crgu_set_ahb_pre_div) + drv_crgu_set_ahb_src 0x000144e5 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_ahb_src) + drv_crgu_set_clock 0x000144f9 Thumb Code 26 drv_crgu.o(i.drv_crgu_set_clock) + drv_crgu_set_dpi_mux_src 0x00014519 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_dpi_mux_src) + drv_crgu_set_dpi_pre_div 0x0001452d Thumb Code 18 drv_crgu.o(i.drv_crgu_set_dpi_pre_div) + drv_crgu_set_dpi_pre_src 0x00014545 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_dpi_pre_src) + drv_crgu_set_dsc_core_div 0x00014559 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_dsc_core_div) + drv_crgu_set_dsco_src 0x0001456d Thumb Code 16 drv_crgu.o(i.drv_crgu_set_dsco_src) + drv_crgu_set_dsco_src_div 0x00014581 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_dsco_src_div) + drv_crgu_set_fb_div 0x00014595 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_fb_div) + drv_crgu_set_fb_src 0x000145a9 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_fb_src) + drv_crgu_set_lcdc_div 0x000145bd Thumb Code 16 drv_crgu.o(i.drv_crgu_set_lcdc_div) + drv_crgu_set_lcdc_src 0x000145d1 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_lcdc_src) + drv_crgu_set_mipi_cfg_src 0x000145e5 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_mipi_cfg_src) + drv_crgu_set_mipi_ref_src 0x000145f9 Thumb Code 18 drv_crgu.o(i.drv_crgu_set_mipi_ref_src) + drv_crgu_set_reset 0x00014611 Thumb Code 20 drv_crgu.o(i.drv_crgu_set_reset) + drv_crgu_set_rxbr_div 0x00014629 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_rxbr_div) + drv_crgu_set_rxbr_src 0x0001463d Thumb Code 16 drv_crgu.o(i.drv_crgu_set_rxbr_src) + drv_crgu_set_vidc_src 0x00014651 Thumb Code 16 drv_crgu.o(i.drv_crgu_set_vidc_src) + drv_dma_clear_flag 0x00014665 Thumb Code 24 drv_dma.o(i.drv_dma_clear_flag) + drv_dma_get_channel_flag 0x0001467d Thumb Code 12 drv_dma.o(i.drv_dma_get_channel_flag) + drv_dma_irq_handler 0x00014689 Thumb Code 138 drv_dma.o(i.drv_dma_irq_handler) + drv_dsc_dec_convert_pps_rc_parameter 0x00014719 Thumb Code 54 drv_dsc_dec.o(i.drv_dsc_dec_convert_pps_rc_parameter) + drv_dsc_dec_disable 0x0001474f Thumb Code 12 drv_dsc_dec.o(i.drv_dsc_dec_disable) + drv_dsc_dec_enable 0x0001475d Thumb Code 88 drv_dsc_dec.o(i.drv_dsc_dec_enable) + drv_dsc_dec_get_nslc 0x000147d1 Thumb Code 10 drv_dsc_dec.o(i.drv_dsc_dec_get_nslc) + drv_dsc_dec_set_u8_pps 0x000147db Thumb Code 40 drv_dsc_dec.o(i.drv_dsc_dec_set_u8_pps) + drv_dsi_rx_calc_ipi_tx_delay 0x00014805 Thumb Code 244 drv_dsi_rx.o(i.drv_dsi_rx_calc_ipi_tx_delay) + drv_dsi_rx_enable_irq 0x00014909 Thumb Code 58 drv_dsi_rx.o(i.drv_dsi_rx_enable_irq) + drv_dsi_rx_get_bta_status 0x00014949 Thumb Code 14 drv_dsi_rx.o(i.drv_dsi_rx_get_bta_status) + drv_dsi_rx_get_compression_en 0x000149c5 Thumb Code 8 drv_dsi_rx.o(i.drv_dsi_rx_get_compression_en) + drv_dsi_rx_get_max_ret_size 0x000149cd Thumb Code 6 drv_dsi_rx.o(i.drv_dsi_rx_get_max_ret_size) + drv_dsi_rx_power_up 0x000149d3 Thumb Code 14 drv_dsi_rx.o(i.drv_dsi_rx_power_up) + drv_dsi_rx_set_ctrl_cfg 0x000149e1 Thumb Code 32 drv_dsi_rx.o(i.drv_dsi_rx_set_ctrl_cfg) + drv_dsi_rx_set_ddi_cfg 0x00014a01 Thumb Code 16 drv_dsi_rx.o(i.drv_dsi_rx_set_ddi_cfg) + drv_dsi_rx_set_inten 0x00014a11 Thumb Code 4 drv_dsi_rx.o(i.drv_dsi_rx_set_inten) + drv_dsi_rx_set_ipi_cfg 0x00014a15 Thumb Code 16 drv_dsi_rx.o(i.drv_dsi_rx_set_ipi_cfg) + drv_dsi_rx_set_lane_swap 0x00014a25 Thumb Code 70 drv_dsi_rx.o(i.drv_dsi_rx_set_lane_swap) + drv_dsi_rx_set_resp_cnt 0x00014a6b Thumb Code 38 drv_dsi_rx.o(i.drv_dsi_rx_set_resp_cnt) + drv_dsi_rx_set_up_phy 0x00014a91 Thumb Code 256 drv_dsi_rx.o(i.drv_dsi_rx_set_up_phy) + drv_dsi_rx_shut_down 0x00014b95 Thumb Code 14 drv_dsi_rx.o(i.drv_dsi_rx_shut_down) + drv_dsi_tx_command_header 0x00014ba3 Thumb Code 20 drv_dsi_tx.o(i.drv_dsi_tx_command_header) + drv_dsi_tx_command_mode_cfg 0x00014bb7 Thumb Code 108 drv_dsi_tx.o(i.drv_dsi_tx_command_mode_cfg) + drv_dsi_tx_command_put_payload 0x00014c23 Thumb Code 4 drv_dsi_tx.o(i.drv_dsi_tx_command_put_payload) + drv_dsi_tx_config_eotp 0x00014c27 Thumb Code 24 drv_dsi_tx.o(i.drv_dsi_tx_config_eotp) + drv_dsi_tx_config_int 0x00014c3f Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_config_int) + drv_dsi_tx_dpi_lpcmd_time 0x00014c47 Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_dpi_lpcmd_time) + drv_dsi_tx_dpi_mode 0x00014c4f Thumb Code 10 drv_dsi_tx.o(i.drv_dsi_tx_dpi_mode) + drv_dsi_tx_dpi_polarity 0x00014c59 Thumb Code 36 drv_dsi_tx.o(i.drv_dsi_tx_dpi_polarity) + drv_dsi_tx_edpi_cmd_size 0x00014c7d Thumb Code 4 drv_dsi_tx.o(i.drv_dsi_tx_edpi_cmd_size) + drv_dsi_tx_get_cmd_status 0x00014c81 Thumb Code 4 drv_dsi_tx.o(i.drv_dsi_tx_get_cmd_status) + drv_dsi_tx_mode 0x00014c85 Thumb Code 4 drv_dsi_tx.o(i.drv_dsi_tx_mode) + drv_dsi_tx_phy_clock_lane_auto_lp 0x00014c89 Thumb Code 24 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_auto_lp) + drv_dsi_tx_phy_clock_lane_req_hs 0x00014ca1 Thumb Code 26 drv_dsi_tx.o(i.drv_dsi_tx_phy_clock_lane_req_hs) + drv_dsi_tx_phy_lane_mode 0x00014cbb Thumb Code 12 drv_dsi_tx.o(i.drv_dsi_tx_phy_lane_mode) + drv_dsi_tx_phy_status_ready 0x00014cc7 Thumb Code 100 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_ready) + drv_dsi_tx_phy_status_stopstate 0x00014d2b Thumb Code 62 drv_dsi_tx.o(i.drv_dsi_tx_phy_status_stopstate) + drv_dsi_tx_phy_test_setup 0x00014d69 Thumb Code 308 drv_dsi_tx.o(i.drv_dsi_tx_phy_test_setup) + drv_dsi_tx_phy_time_cfg 0x00014e9d Thumb Code 30 drv_dsi_tx.o(i.drv_dsi_tx_phy_time_cfg) + drv_dsi_tx_powerup 0x00014ebb Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_powerup) + drv_dsi_tx_response_mode 0x00014ec3 Thumb Code 28 drv_dsi_tx.o(i.drv_dsi_tx_response_mode) + drv_dsi_tx_set_bta_ack 0x00014edf Thumb Code 24 drv_dsi_tx.o(i.drv_dsi_tx_set_bta_ack) + drv_dsi_tx_set_esc_div 0x00014ef7 Thumb Code 12 drv_dsi_tx.o(i.drv_dsi_tx_set_esc_div) + drv_dsi_tx_set_int 0x00014f05 Thumb Code 58 drv_dsi_tx.o(i.drv_dsi_tx_set_int) + drv_dsi_tx_set_time_out_div 0x00014f45 Thumb Code 16 drv_dsi_tx.o(i.drv_dsi_tx_set_time_out_div) + drv_dsi_tx_set_video_chunk 0x00014f55 Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_set_video_chunk) + drv_dsi_tx_set_video_timing 0x00014f5d Thumb Code 34 drv_dsi_tx.o(i.drv_dsi_tx_set_video_timing) + drv_dsi_tx_shutdown 0x00014f7f Thumb Code 8 drv_dsi_tx.o(i.drv_dsi_tx_shutdown) + drv_dsi_tx_timeout_cfg 0x00014f87 Thumb Code 38 drv_dsi_tx.o(i.drv_dsi_tx_timeout_cfg) + drv_dsi_tx_video_mode_cfg 0x00014fad Thumb Code 170 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_cfg) + drv_dsi_tx_video_mode_disable_hact_cmd 0x00015057 Thumb Code 22 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_disable_hact_cmd) + drv_dsi_tx_video_mode_set_lp_cmd 0x0001506d Thumb Code 24 drv_dsi_tx.o(i.drv_dsi_tx_video_mode_set_lp_cmd) + drv_efuse_enter_inactive 0x00015085 Thumb Code 46 drv_efuse.o(i.drv_efuse_enter_inactive) + drv_efuse_int_enable 0x000150b3 Thumb Code 12 drv_efuse.o(i.drv_efuse_int_enable) + drv_efuse_read 0x000150bf Thumb Code 50 drv_efuse.o(i.drv_efuse_read) + drv_efuse_read_req 0x000150f1 Thumb Code 24 drv_efuse.o(i.drv_efuse_read_req) + drv_gpio_set_ioe 0x00015109 Thumb Code 26 drv_gpio.o(i.drv_gpio_set_ioe) + drv_gpio_set_mode0 0x00015129 Thumb Code 12 drv_gpio.o(i.drv_gpio_set_mode0) + drv_gpio_set_mode1 0x00015139 Thumb Code 12 drv_gpio.o(i.drv_gpio_set_mode1) + drv_gpio_set_mode2 0x00015149 Thumb Code 12 drv_gpio.o(i.drv_gpio_set_mode2) + drv_gpio_set_mode3 0x00015159 Thumb Code 12 drv_gpio.o(i.drv_gpio_set_mode3) + drv_lcdc_config_bypass 0x00015189 Thumb Code 24 drv_lcdc.o(i.drv_lcdc_config_bypass) + drv_lcdc_config_ccm 0x000151a1 Thumb Code 48 drv_lcdc.o(i.drv_lcdc_config_ccm) + drv_lcdc_config_disp_mode 0x000151d1 Thumb Code 22 drv_lcdc.o(i.drv_lcdc_config_disp_mode) + drv_lcdc_config_dpi_polarity 0x000151e7 Thumb Code 36 drv_lcdc.o(i.drv_lcdc_config_dpi_polarity) + drv_lcdc_config_dpi_timing 0x0001520b Thumb Code 38 drv_lcdc.o(i.drv_lcdc_config_dpi_timing) + drv_lcdc_config_edpi_mode 0x00015231 Thumb Code 22 drv_lcdc.o(i.drv_lcdc_config_edpi_mode) + drv_lcdc_config_endianness 0x00015247 Thumb Code 22 drv_lcdc.o(i.drv_lcdc_config_endianness) + drv_lcdc_config_input_size 0x0001525d Thumb Code 12 drv_lcdc.o(i.drv_lcdc_config_input_size) + drv_lcdc_config_int 0x00015269 Thumb Code 30 drv_lcdc.o(i.drv_lcdc_config_int) + drv_lcdc_config_int_single 0x00015287 Thumb Code 34 drv_lcdc.o(i.drv_lcdc_config_int_single) + drv_lcdc_config_overwrite 0x000152a9 Thumb Code 34 drv_lcdc.o(i.drv_lcdc_config_overwrite) + drv_lcdc_config_overwrite_rgb 0x000152cb Thumb Code 12 drv_lcdc.o(i.drv_lcdc_config_overwrite_rgb) + drv_lcdc_config_partial_display_area 0x000152d7 Thumb Code 26 drv_lcdc.o(i.drv_lcdc_config_partial_display_area) + drv_lcdc_config_partial_display_enable 0x000152f1 Thumb Code 34 drv_lcdc.o(i.drv_lcdc_config_partial_display_enable) + drv_lcdc_config_scale_up_coef 0x00015313 Thumb Code 26 drv_lcdc.o(i.drv_lcdc_config_scale_up_coef) + drv_lcdc_config_scale_up_step 0x0001532d Thumb Code 12 drv_lcdc.o(i.drv_lcdc_config_scale_up_step) + drv_lcdc_config_src_parameter 0x00015339 Thumb Code 76 drv_lcdc.o(i.drv_lcdc_config_src_parameter) + drv_lcdc_config_thresh 0x00015385 Thumb Code 6 drv_lcdc.o(i.drv_lcdc_config_thresh) + drv_lcdc_ctrl_flow 0x0001538b Thumb Code 18 drv_lcdc.o(i.drv_lcdc_ctrl_flow) + drv_lcdc_enable_shadow_reg 0x0001539d Thumb Code 32 drv_lcdc.o(i.drv_lcdc_enable_shadow_reg) + drv_lcdc_set_int 0x000153bd Thumb Code 58 drv_lcdc.o(i.drv_lcdc_set_int) + drv_lcdc_set_prefetch 0x000153fd Thumb Code 24 drv_lcdc.o(i.drv_lcdc_set_prefetch) + drv_lcdc_set_video_hw_mode 0x00015415 Thumb Code 20 drv_lcdc.o(i.drv_lcdc_set_video_hw_mode) + drv_lcdc_start 0x00015429 Thumb Code 32 drv_lcdc.o(i.drv_lcdc_start) + drv_memc_clear_status 0x00015449 Thumb Code 12 drv_memc.o(i.drv_memc_clear_status) + drv_memc_enable_irq 0x00015455 Thumb Code 58 drv_memc.o(i.drv_memc_enable_irq) + drv_memc_gen_a_tear_signal 0x00015495 Thumb Code 12 drv_memc.o(i.drv_memc_gen_a_tear_signal) + drv_memc_get_status 0x000154a1 Thumb Code 18 drv_memc.o(i.drv_memc_get_status) + drv_memc_rate_transfer_sel 0x000154b3 Thumb Code 16 drv_memc.o(i.drv_memc_rate_transfer_sel) + drv_memc_sel_vsync 0x000154c3 Thumb Code 14 drv_memc.o(i.drv_memc_sel_vsync) + drv_memc_set_active_height 0x000154d1 Thumb Code 14 drv_memc.o(i.drv_memc_set_active_height) + drv_memc_set_data_mode 0x000154e5 Thumb Code 12 drv_memc.o(i.drv_memc_set_data_mode) + drv_memc_set_double_buffer 0x000154f1 Thumb Code 16 drv_memc.o(i.drv_memc_set_double_buffer) + drv_memc_set_double_buffer_reverse 0x00015501 Thumb Code 18 drv_memc.o(i.drv_memc_set_double_buffer_reverse) + drv_memc_set_fs_en_conditions 0x00015513 Thumb Code 16 drv_memc.o(i.drv_memc_set_fs_en_conditions) + drv_memc_set_inten 0x00015523 Thumb Code 20 drv_memc.o(i.drv_memc_set_inten) + drv_memc_set_lcdc_st_conditions 0x00015539 Thumb Code 18 drv_memc.o(i.drv_memc_set_lcdc_st_conditions) + drv_memc_set_ltpo_mode 0x00015551 Thumb Code 26 drv_memc.o(i.drv_memc_set_ltpo_mode) + drv_memc_set_tear_mode 0x0001556b Thumb Code 14 drv_memc.o(i.drv_memc_set_tear_mode) + drv_memc_set_tear_waveform 0x00015579 Thumb Code 34 drv_memc.o(i.drv_memc_set_tear_waveform) + drv_memc_set_vidc_sync_cnt 0x000155a1 Thumb Code 14 drv_memc.o(i.drv_memc_set_vidc_sync_cnt) + drv_param_init_get_ccm 0x000155b1 Thumb Code 4 drv_param_init.o(i.drv_param_init_get_ccm) + drv_param_init_get_scld_filter_h 0x000155b9 Thumb Code 12 drv_param_init.o(i.drv_param_init_get_scld_filter_h) + drv_param_init_get_scld_filter_v 0x000155cd Thumb Code 12 drv_param_init.o(i.drv_param_init_get_scld_filter_v) + drv_param_init_get_sclu_filter 0x000155e1 Thumb Code 4 drv_param_init.o(i.drv_param_init_get_sclu_filter) + drv_param_init_set_ccm 0x000155e9 Thumb Code 14 drv_param_init.o(i.drv_param_init_set_ccm) + drv_param_init_set_scld_filter 0x000155fd Thumb Code 92 drv_param_init.o(i.drv_param_init_set_scld_filter) + drv_param_p2r_filter_init 0x00015661 Thumb Code 30 drv_param_init.o(i.drv_param_p2r_filter_init) + drv_phy_enable_calibration 0x00015685 Thumb Code 12 drv_phy_common.o(i.drv_phy_enable_calibration) + drv_phy_get_calibration 0x00015695 Thumb Code 50 drv_phy_common.o(i.drv_phy_get_calibration) + drv_phy_get_pll_para 0x000156d1 Thumb Code 88 drv_phy_common.o(i.drv_phy_get_pll_para) + drv_phy_get_rate_para 0x00015731 Thumb Code 76 drv_phy_common.o(i.drv_phy_get_rate_para) + drv_phy_test_clear 0x00015785 Thumb Code 16 drv_phy_common.o(i.drv_phy_test_clear) + drv_phy_test_lock 0x00015795 Thumb Code 24 drv_phy_common.o(i.drv_phy_test_lock) + drv_phy_test_write_1_byte 0x000157ad Thumb Code 32 drv_phy_common.o(i.drv_phy_test_write_1_byte) + drv_phy_test_write_2_byte 0x000157cd Thumb Code 38 drv_phy_common.o(i.drv_phy_test_write_2_byte) + drv_phy_test_write_code 0x000157f3 Thumb Code 30 drv_phy_common.o(i.drv_phy_test_write_code) + drv_pwr_set_pvd_mode 0x00015831 Thumb Code 18 drv_pwr.o(i.drv_pwr_set_pvd_mode) + drv_pwr_set_system_clk_src 0x00015849 Thumb Code 44 drv_pwr.o(i.drv_pwr_set_system_clk_src) + drv_rxbr_clear_pkt_buffer 0x000158c7 Thumb Code 10 drv_rxbr.o(i.drv_rxbr_clear_pkt_buffer) + drv_rxbr_clear_status0 0x000158d1 Thumb Code 4 drv_rxbr.o(i.drv_rxbr_clear_status0) + drv_rxbr_enable_irq 0x000158d5 Thumb Code 90 drv_rxbr.o(i.drv_rxbr_enable_irq) + drv_rxbr_frame_drop_cfg 0x00015931 Thumb Code 16 drv_rxbr.o(i.drv_rxbr_frame_drop_cfg) + drv_rxbr_get_clk 0x00015945 Thumb Code 66 drv_rxbr.o(i.drv_rxbr_get_clk) + drv_rxbr_get_col_addr 0x000159a9 Thumb Code 4 drv_rxbr.o(i.drv_rxbr_get_col_addr) + drv_rxbr_get_page_addr 0x000159bf Thumb Code 4 drv_rxbr.o(i.drv_rxbr_get_page_addr) + drv_rxbr_get_pkt_buf_error_status 0x000159c3 Thumb Code 12 drv_rxbr.o(i.drv_rxbr_get_pkt_buf_error_status) + drv_rxbr_hline_rcv0_cfg 0x000159f7 Thumb Code 12 drv_rxbr.o(i.drv_rxbr_hline_rcv0_cfg) + drv_rxbr_hline_rcv1_cfg 0x00015a03 Thumb Code 12 drv_rxbr.o(i.drv_rxbr_hline_rcv1_cfg) + drv_rxbr_hline_rcv_cfg 0x00015a0f Thumb Code 8 drv_rxbr.o(i.drv_rxbr_hline_rcv_cfg) + drv_rxbr_register_irq0_callback 0x00015a19 Thumb Code 6 drv_rxbr.o(i.drv_rxbr_register_irq0_callback) + drv_rxbr_register_irq1_callback 0x00015a25 Thumb Code 6 drv_rxbr.o(i.drv_rxbr_register_irq1_callback) + drv_rxbr_set_ack_pkt_header 0x00015a31 Thumb Code 20 drv_rxbr.o(i.drv_rxbr_set_ack_pkt_header) + drv_rxbr_set_color_format 0x00015a45 Thumb Code 20 drv_rxbr.o(i.drv_rxbr_set_color_format) + drv_rxbr_set_filter_regs 0x00015a59 Thumb Code 18 drv_rxbr.o(i.drv_rxbr_set_filter_regs) + drv_rxbr_set_inten 0x00015a6b Thumb Code 20 drv_rxbr.o(i.drv_rxbr_set_inten) + drv_rxbr_set_ltpo_drop_th 0x00015a7f Thumb Code 16 drv_rxbr.o(i.drv_rxbr_set_ltpo_drop_th) + drv_rxbr_set_usr_cfg 0x00015a8f Thumb Code 38 drv_rxbr.o(i.drv_rxbr_set_usr_cfg) + drv_rxbr_set_usr_col 0x00015ab5 Thumb Code 8 drv_rxbr.o(i.drv_rxbr_set_usr_col) + drv_rxbr_set_usr_row 0x00015abd Thumb Code 8 drv_rxbr.o(i.drv_rxbr_set_usr_row) + drv_swire_set_int 0x00015ac5 Thumb Code 76 drv_swire.o(i.drv_swire_set_int) + drv_sys_cfg_clear_all_int 0x00015b19 Thumb Code 8 drv_sys_cfg.o(i.drv_sys_cfg_clear_all_int) + drv_sys_cfg_clear_pending 0x00015b25 Thumb Code 32 drv_sys_cfg.o(i.drv_sys_cfg_clear_pending) + drv_sys_cfg_sel_ap_rst_lvl_trig 0x00015b4d Thumb Code 18 drv_sys_cfg.o(i.drv_sys_cfg_sel_ap_rst_lvl_trig) + drv_sys_cfg_set_int 0x00015b65 Thumb Code 30 drv_sys_cfg.o(i.drv_sys_cfg_set_int) + drv_timer_enable 0x00015ba3 Thumb Code 32 drv_timer.o(i.drv_timer_enable) + drv_timer_get_instance 0x00015bc5 Thumb Code 10 drv_timer.o(i.drv_timer_get_instance) + drv_timer_set_compare_val 0x00015c19 Thumb Code 16 drv_timer.o(i.drv_timer_set_compare_val) + drv_timer_set_int 0x00015c29 Thumb Code 80 drv_timer.o(i.drv_timer_set_int) + drv_tx_phy_test_enter 0x00015c87 Thumb Code 28 drv_dsi_tx.o(i.drv_tx_phy_test_enter) + drv_tx_phy_test_exit 0x00015ca3 Thumb Code 28 drv_dsi_tx.o(i.drv_tx_phy_test_exit) + drv_vidc_clear_irq 0x00015cf5 Thumb Code 8 drv_vidc.o(i.drv_vidc_clear_irq) + drv_vidc_enable 0x00015cfd Thumb Code 24 drv_vidc.o(i.drv_vidc_enable) + drv_vidc_enable_irq 0x00015d15 Thumb Code 58 drv_vidc.o(i.drv_vidc_enable_irq) + drv_vidc_get_irq_status 0x00015d55 Thumb Code 18 drv_vidc.o(i.drv_vidc_get_irq_status) + drv_vidc_init_module_enable 0x00015d69 Thumb Code 36 drv_vidc.o(i.drv_vidc_init_module_enable) + drv_vidc_register_callback 0x00015d91 Thumb Code 6 drv_vidc.o(i.drv_vidc_register_callback) + drv_vidc_reset 0x00015d9d Thumb Code 6 drv_vidc.o(i.drv_vidc_reset) + drv_vidc_set_dst_parameter 0x00015da3 Thumb Code 60 drv_vidc.o(i.drv_vidc_set_dst_parameter) + drv_vidc_set_irqen 0x00015ddf Thumb Code 20 drv_vidc.o(i.drv_vidc_set_irqen) + drv_vidc_set_mirror 0x00015df3 Thumb Code 16 drv_vidc.o(i.drv_vidc_set_mirror) + drv_vidc_set_p2r_hcoef0 0x00015e03 Thumb Code 8 drv_vidc.o(i.drv_vidc_set_p2r_hcoef0) + drv_vidc_set_p2r_hinitb 0x00015e0b Thumb Code 38 drv_vidc.o(i.drv_vidc_set_p2r_hinitb) + drv_vidc_set_p2r_hinitr 0x00015e31 Thumb Code 38 drv_vidc.o(i.drv_vidc_set_p2r_hinitr) + drv_vidc_set_pentile_swap 0x00015e59 Thumb Code 18 drv_vidc.o(i.drv_vidc_set_pentile_swap) + drv_vidc_set_pu_ctrl 0x00015e71 Thumb Code 10 drv_vidc.o(i.drv_vidc_set_pu_ctrl) + drv_vidc_set_rotation 0x00015e7b Thumb Code 16 drv_vidc.o(i.drv_vidc_set_rotation) + drv_vidc_set_scld_hcoef0 0x00015e8b Thumb Code 10 drv_vidc.o(i.drv_vidc_set_scld_hcoef0) + drv_vidc_set_scld_hcoef1 0x00015e95 Thumb Code 10 drv_vidc.o(i.drv_vidc_set_scld_hcoef1) + drv_vidc_set_scld_step 0x00015e9f Thumb Code 18 drv_vidc.o(i.drv_vidc_set_scld_step) + drv_vidc_set_scld_vcoef0 0x00015eb1 Thumb Code 10 drv_vidc.o(i.drv_vidc_set_scld_vcoef0) + drv_vidc_set_scld_vcoef1 0x00015ebb Thumb Code 10 drv_vidc.o(i.drv_vidc_set_scld_vcoef1) + drv_vidc_set_src_parameter 0x00015ec5 Thumb Code 22 drv_vidc.o(i.drv_vidc_set_src_parameter) + drv_wdg_clear_counter 0x00015edd Thumb Code 12 drv_wdg.o(i.drv_wdg_clear_counter) + drv_wdg_set_int 0x00015f0d Thumb Code 60 drv_wdg.o(i.drv_wdg_set_int) + fls_clr_interrupt_flag 0x00015f4d Thumb Code 10 drv_fls.o(i.fls_clr_interrupt_flag) + fputc 0x00015f57 Thumb Code 20 tau_log.o(i.fputc) + hal_dsi_rx_ctrl_create_handle 0x00015fbd Thumb Code 48 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_create_handle) + hal_dsi_rx_ctrl_dsc_async_handler 0x00015ff1 Thumb Code 34 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_dsc_async_handler) + hal_dsi_rx_ctrl_gen_a_tear_signal 0x00016019 Thumb Code 32 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_gen_a_tear_signal) + hal_dsi_rx_ctrl_get_max_ret_size 0x00016041 Thumb Code 30 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_get_max_ret_size) + hal_dsi_rx_ctrl_init 0x00016069 Thumb Code 144 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_init) + hal_dsi_rx_ctrl_pre_init_pps 0x00016859 Thumb Code 56 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_pre_init_pps) + hal_dsi_rx_ctrl_restart 0x00016895 Thumb Code 72 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_restart) + hal_dsi_rx_ctrl_send_ack_cmd 0x000168e5 Thumb Code 212 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_send_ack_cmd) + hal_dsi_rx_ctrl_set_cus_esc_clk 0x000169d5 Thumb Code 34 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_esc_clk) + hal_dsi_rx_ctrl_set_cus_scld_filter 0x00016a01 Thumb Code 98 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_scld_filter) + hal_dsi_rx_ctrl_set_cus_sync_line 0x00016a6d Thumb Code 44 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_cus_sync_line) + hal_dsi_rx_ctrl_set_tear_mode_ex 0x00016b4b Thumb Code 14 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_set_tear_mode_ex) + hal_dsi_rx_ctrl_start 0x00016b59 Thumb Code 46 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_start) + hal_dsi_rx_ctrl_toggle_resolution 0x00016b95 Thumb Code 28 hal_dsi_rx_ctrl.o(i.hal_dsi_rx_ctrl_toggle_resolution) + hal_dsi_tx_ctrl_create_handle 0x000171a1 Thumb Code 34 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_create_handle) + hal_dsi_tx_ctrl_enter_init_panel_mode 0x000171cd Thumb Code 68 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_enter_init_panel_mode) + hal_dsi_tx_ctrl_exit_init_panel_mode 0x00017219 Thumb Code 32 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_exit_init_panel_mode) + hal_dsi_tx_ctrl_init 0x00017241 Thumb Code 154 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_init) + hal_dsi_tx_ctrl_panel_reset_pin 0x00017309 Thumb Code 12 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_panel_reset_pin) + hal_dsi_tx_ctrl_set_ccm 0x00017315 Thumb Code 28 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_ccm) + hal_dsi_tx_ctrl_set_overwrite_rgb 0x00017335 Thumb Code 16 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_overwrite_rgb) + hal_dsi_tx_ctrl_set_partial_disp 0x00017349 Thumb Code 12 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_partial_disp) + hal_dsi_tx_ctrl_set_partial_disp_area 0x00017359 Thumb Code 30 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_set_partial_disp_area) + hal_dsi_tx_ctrl_start 0x0001737d Thumb Code 150 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_start) + hal_dsi_tx_ctrl_write_array_cmd 0x00017425 Thumb Code 236 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_array_cmd) + hal_dsi_tx_ctrl_write_cmd 0x00017515 Thumb Code 200 hal_dsi_tx_ctrl.o(i.hal_dsi_tx_ctrl_write_cmd) + hal_gpio_init_output 0x000177c5 Thumb Code 34 hal_gpio.o(i.hal_gpio_init_output) + hal_gpio_set_mode 0x000177ed Thumb Code 90 hal_gpio.o(i.hal_gpio_set_mode) + hal_gpio_set_output_data 0x0001784d Thumb Code 8 hal_gpio.o(i.hal_gpio_set_output_data) + hal_internal_check_video_auto_sync 0x00017855 Thumb Code 18 hal_internal_vsync.o(i.hal_internal_check_video_auto_sync) + hal_internal_init_memc 0x0001786d Thumb Code 170 hal_internal_vsync.o(i.hal_internal_init_memc) + hal_internal_rx_dcs_async_handler 0x00017969 Thumb Code 42 hal_internal_vsync.o(i.hal_internal_rx_dcs_async_handler) + hal_internal_rx_dcs_polling 0x00017995 Thumb Code 78 hal_internal_vsync.o(i.hal_internal_rx_dcs_polling) + hal_internal_sync_get_fb_setting 0x000179ed Thumb Code 12 hal_internal_vsync.o(i.hal_internal_sync_get_fb_setting) + hal_internal_sync_get_hight_performan_mode 0x000179fd Thumb Code 10 hal_internal_vsync.o(i.hal_internal_sync_get_hight_performan_mode) + hal_internal_sync_input_resolution_change 0x00017a0d Thumb Code 438 hal_internal_vsync.o(i.hal_internal_sync_input_resolution_change) + hal_internal_vsync_deinit 0x00017c39 Thumb Code 30 hal_internal_vsync.o(i.hal_internal_vsync_deinit) + hal_internal_vsync_get_sync_line 0x00017c61 Thumb Code 18 hal_internal_vsync.o(i.hal_internal_vsync_get_sync_line) + hal_internal_vsync_get_tear_mode 0x00017c79 Thumb Code 6 hal_internal_vsync.o(i.hal_internal_vsync_get_tear_mode) + hal_internal_vsync_get_tx_state 0x00017c85 Thumb Code 6 hal_internal_vsync.o(i.hal_internal_vsync_get_tx_state) + hal_internal_vsync_init_rx 0x00017c91 Thumb Code 274 hal_internal_vsync.o(i.hal_internal_vsync_init_rx) + hal_internal_vsync_init_tx 0x00017dd1 Thumb Code 172 hal_internal_vsync.o(i.hal_internal_vsync_init_tx) + hal_internal_vsync_set_auto_hw_filter 0x00017e81 Thumb Code 132 hal_internal_vsync.o(i.hal_internal_vsync_set_auto_hw_filter) + hal_internal_vsync_set_rx_state 0x00017f11 Thumb Code 30 hal_internal_vsync.o(i.hal_internal_vsync_set_rx_state) + hal_internal_vsync_set_sync_line 0x00017f35 Thumb Code 64 hal_internal_vsync.o(i.hal_internal_vsync_set_sync_line) + hal_internal_vsync_set_tear_mode 0x00017f79 Thumb Code 72 hal_internal_vsync.o(i.hal_internal_vsync_set_tear_mode) + hal_internal_vsync_set_tx_state 0x00017fc9 Thumb Code 122 hal_internal_vsync.o(i.hal_internal_vsync_set_tx_state) + hal_intl_svs_deinit_tx 0x0001804d Thumb Code 10 hal_internal_soft_sync.o(i.hal_intl_svs_deinit_tx) + hal_intl_svs_handle 0x0001805d Thumb Code 24 hal_internal_soft_sync.o(i.hal_intl_svs_handle) + hal_intl_svs_init_rx 0x00018081 Thumb Code 108 hal_internal_soft_sync.o(i.hal_intl_svs_init_rx) + hal_intl_svs_init_tx 0x000180f9 Thumb Code 16 hal_internal_soft_sync.o(i.hal_intl_svs_init_tx) + hal_intl_svs_set_sync_coef 0x0001810d Thumb Code 8 hal_internal_soft_sync.o(i.hal_intl_svs_set_sync_coef) + hal_intl_svs_update_rxbr_clk 0x00018119 Thumb Code 52 hal_internal_soft_sync.o(i.hal_intl_svs_update_rxbr_clk) + hal_system_enable_systick 0x000185c1 Thumb Code 8 hal_system.o(i.hal_system_enable_systick) + hal_system_init 0x000185c9 Thumb Code 104 hal_system.o(i.hal_system_init) + hal_system_init_console 0x00018651 Thumb Code 28 hal_system.o(i.hal_system_init_console) + hal_system_set_phy_calibration 0x0001866d Thumb Code 8 hal_system.o(i.hal_system_set_phy_calibration) + hal_uart_init 0x000186a5 Thumb Code 126 hal_uart.o(i.hal_uart_init) + hal_uart_transmit_blocking 0x00018731 Thumb Code 12 hal_uart.o(i.hal_uart_transmit_blocking) + handle_init 0x00018741 Thumb Code 140 irq_redirect .o(i.handle_init) + main 0x0001895d Thumb Code 10 main.o(i.main) + sqrt 0x000196d9 Thumb Code 66 sqrt.o(i.sqrt) + panel_init_code 0x00019e7c Data 7814 ap_demo.o(.constdata) + Region$$Table$$Base 0x0001c1ec Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x0001c21c Number 0 anon$$obj.o(Region$$Table) g_fun_handle 0x00070100 Data 192 irq_redirect .o(.ARM.__AT_0x00070100) s_power_up_flag 0x000701d7 Data 1 ap_demo.o(.data) panel_mode 0x000701d8 Data 1 ap_demo.o(.data) @@ -4410,9 +4412,9 @@ Memory Map of the image Image Entry point : 0x000100c1 - Load Region LR_IROM2 (Base: 0x00010000, Size: 0x0000cad4, Max: 0x00010000, ABSOLUTE, COMPRESSED[0x0000c718]) + Load Region LR_IROM2 (Base: 0x00010000, Size: 0x0000cb04, Max: 0x00010000, ABSOLUTE, COMPRESSED[0x0000c748]) - Execution Region ER_IROM2 (Exec base: 0x00010000, Load base: 0x00010000, Size: 0x0000c1ec, Max: 0x00010000, ABSOLUTE) + Execution Region ER_IROM2 (Exec base: 0x00010000, Load base: 0x00010000, Size: 0x0000c21c, Max: 0x00010000, ABSOLUTE) Exec Addr Load Addr Size Type Attr Idx E Section Name Object @@ -4536,433 +4538,433 @@ Memory Map of the image 0x00012cdc 0x00012cdc 0x00000120 Code RO 105 i.ap_demo ap_demo.o 0x00012dfc 0x00012dfc 0x0000004c Code RO 106 i.ap_get_reg_df ap_demo.o 0x00012e48 0x00012e48 0x00000020 Code RO 418 i.ap_get_tp_calibration_status_01 app_tp_st_touch.o - 0x00012e68 0x00012e68 0x00000044 Code RO 107 i.ap_set_backlight_51 ap_demo.o - 0x00012eac 0x00012eac 0x00000044 Code RO 108 i.ap_set_display_off ap_demo.o - 0x00012ef0 0x00012ef0 0x00000038 Code RO 109 i.ap_set_display_on ap_demo.o - 0x00012f28 0x00012f28 0x00000080 Code RO 110 i.ap_set_enter_sleep_mode ap_demo.o - 0x00012fa8 0x00012fa8 0x00000070 Code RO 111 i.ap_set_exit_sleep_mode ap_demo.o - 0x00013018 0x00013018 0x00000030 Code RO 112 i.ap_set_hbm_53 ap_demo.o - 0x00013048 0x00013048 0x00000028 Code RO 113 i.ap_update_frame_rate ap_demo.o - 0x00013070 0x00013070 0x0000001c Code RO 2034 i.app_ADC_IRQn_Handler CVWL568.lib(drv_rxbr.o) - 0x0001308c 0x0001308c 0x00000024 Code RO 1451 i.app_AP_NRESET_IRQn_Handler CVWL568.lib(drv_gpio.o) - 0x000130b0 0x000130b0 0x0000001c Code RO 1452 i.app_EXTI_INT0_IRQn_Handler CVWL568.lib(drv_gpio.o) - 0x000130cc 0x000130cc 0x0000001c Code RO 1453 i.app_EXTI_INT1_IRQn_Handler CVWL568.lib(drv_gpio.o) - 0x000130e8 0x000130e8 0x0000001c Code RO 1454 i.app_EXTI_INT2_IRQn_Handler CVWL568.lib(drv_gpio.o) - 0x00013104 0x00013104 0x0000001c Code RO 1455 i.app_EXTI_INT3_IRQn_Handler CVWL568.lib(drv_gpio.o) - 0x00013120 0x00013120 0x0000001c Code RO 1456 i.app_EXTI_INT4_IRQn_Handler CVWL568.lib(drv_gpio.o) - 0x0001313c 0x0001313c 0x0000001c Code RO 1457 i.app_EXTI_INT5_IRQn_Handler CVWL568.lib(drv_gpio.o) - 0x00013158 0x00013158 0x0000001c Code RO 1458 i.app_EXTI_INT6_IRQn_Handler CVWL568.lib(drv_gpio.o) - 0x00013174 0x00013174 0x0000001c Code RO 1459 i.app_EXTI_INT7_IRQn_Handler CVWL568.lib(drv_gpio.o) - 0x00013190 0x00013190 0x00000048 Code RO 1198 i.app_HardFault_Handler CVWL568.lib(drv_common.o) - 0x000131d8 0x000131d8 0x00000018 Code RO 1562 i.app_I2C0_IRQn_Handler CVWL568.lib(drv_i2c_slave.o) - 0x000131f0 0x000131f0 0x00000010 Code RO 1528 i.app_I2C1_IRQn_Handler CVWL568.lib(drv_i2c_master.o) - 0x00013200 0x00013200 0x00000130 Code RO 1099 i.app_LCDC_IRQn_Handler CVWL568.lib(hal_internal_vsync.o) - 0x00013330 0x00013330 0x00000088 Code RO 1976 i.app_MEMC_IRQn_Handler CVWL568.lib(drv_memc.o) - 0x000133b8 0x000133b8 0x00000298 Code RO 1746 i.app_MIPI_RX_IRQn_Handler CVWL568.lib(drv_dsi_rx.o) - 0x00013650 0x00013650 0x000000a0 Code RO 1804 i.app_MIPI_TX_IRQn_Handler CVWL568.lib(drv_dsi_tx.o) - 0x000136f0 0x000136f0 0x00000048 Code RO 2488 i.app_PWMDET_IRQn_Handler CVWL568.lib(drv_pwm.o) - 0x00013738 0x00013738 0x00000030 Code RO 1652 i.app_SPIM_IRQn_Handler CVWL568.lib(drv_spi_master.o) - 0x00013768 0x00013768 0x00000200 Code RO 2335 i.app_SPIS_IRQn_Handler CVWL568.lib(hal_spi_slave.o) - 0x00013968 0x00013968 0x00000020 Code RO 2553 i.app_SWIRE_IRQn_Handler CVWL568.lib(drv_swire.o) - 0x00013988 0x00013988 0x00000018 Code RO 1199 i.app_SysTick_Handler CVWL568.lib(drv_common.o) - 0x000139a0 0x000139a0 0x0000000a Code RO 2572 i.app_TIMER0_IRQn_Handler CVWL568.lib(drv_timer.o) - 0x000139aa 0x000139aa 0x0000000a Code RO 2573 i.app_TIMER1_IRQn_Handler CVWL568.lib(drv_timer.o) - 0x000139b4 0x000139b4 0x0000000a Code RO 2574 i.app_TIMER2_IRQn_Handler CVWL568.lib(drv_timer.o) - 0x000139be 0x000139be 0x0000000a Code RO 2575 i.app_TIMER3_IRQn_Handler CVWL568.lib(drv_timer.o) - 0x000139c8 0x000139c8 0x00000008 Code RO 2635 i.app_UART_IRQn_Handler CVWL568.lib(drv_uart.o) - 0x000139d0 0x000139d0 0x0000001c Code RO 2105 i.app_VIDC_IRQn_Handler CVWL568.lib(drv_vidc.o) - 0x000139ec 0x000139ec 0x0000001c Code RO 2035 i.app_VPRE_IRQn_Handler CVWL568.lib(drv_rxbr.o) - 0x00013a08 0x00013a08 0x00000038 Code RO 2694 i.app_WDG_IRQn_Handler CVWL568.lib(drv_wdg.o) - 0x00013a40 0x00013a40 0x00000010 Code RO 1313 i.app_dma_irq_handler CVWL568.lib(drv_dma.o) - 0x00013a50 0x00013a50 0x00000030 Code RO 2377 i.app_fls_ctrl_Handler CVWL568.lib(norflash.o) - 0x00013a80 0x00013a80 0x00000024 Code RO 542 i.board_Init board.o - 0x00013aa4 0x00013aa4 0x0000058c Code RO 1100 i.calc_framebuffer_setting CVWL568.lib(hal_internal_vsync.o) - 0x00014030 0x00014030 0x000000c8 Code RO 2729 i.ceil m_ps.l(ceil.o) - 0x000140f8 0x000140f8 0x0000002c Code RO 1101 i.check_mipi_rx_tx_video_info CVWL568.lib(hal_internal_vsync.o) - 0x00014124 0x00014124 0x00000084 Code RO 1102 i.check_pkt_buf_rev CVWL568.lib(hal_internal_vsync.o) - 0x000141a8 0x000141a8 0x00000058 Code RO 2717 i.dcs_packet_fifo_alloc CVWL568.lib(dcs_packet_fifo.o) - 0x00014200 0x00014200 0x00000018 Code RO 2718 i.dcs_packet_fifo_init CVWL568.lib(dcs_packet_fifo.o) - 0x00014218 0x00014218 0x00000044 Code RO 2719 i.dcs_packet_free_fifo_header CVWL568.lib(dcs_packet_fifo.o) - 0x0001425c 0x0001425c 0x00000024 Code RO 2720 i.dcs_packet_get_fifo_header CVWL568.lib(dcs_packet_fifo.o) - 0x00014280 0x00014280 0x0000002c Code RO 1103 i.dcs_sw_filter CVWL568.lib(hal_internal_vsync.o) - 0x000142ac 0x000142ac 0x00000018 Code RO 1061 i.delayMs CVWL568.lib(tau_delay.o) - 0x000142c4 0x000142c4 0x00000022 Code RO 1062 i.delayUs CVWL568.lib(tau_delay.o) - 0x000142e6 0x000142e6 0x00000002 PAD - 0x000142e8 0x000142e8 0x00000038 Code RO 1684 i.drv_ap_rst_trig_edge_detect CVWL568.lib(drv_sys_cfg.o) - 0x00014320 0x00014320 0x0000000c Code RO 2305 i.drv_chip_info_get_info CVWL568.lib(drv_chip_info.o) - 0x0001432c 0x0001432c 0x00000040 Code RO 2306 i.drv_chip_info_init CVWL568.lib(drv_chip_info.o) - 0x0001436c 0x0001436c 0x000000b0 Code RO 2307 i.drv_chip_rx_info_check CVWL568.lib(drv_chip_info.o) - 0x0001441c 0x0001441c 0x00000014 Code RO 2308 i.drv_chip_rx_init_done CVWL568.lib(drv_chip_info.o) - 0x00014430 0x00014430 0x00000058 Code RO 1201 i.drv_common_enable_systick CVWL568.lib(drv_common.o) - 0x00014488 0x00014488 0x00000008 Code RO 1204 i.drv_common_system_init CVWL568.lib(drv_common.o) - 0x00014490 0x00014490 0x00000010 Code RO 1226 i.drv_crgu_config_reset_modules CVWL568.lib(drv_crgu.o) - 0x000144a0 0x000144a0 0x00000014 Code RO 1239 i.drv_crgu_set_ahb_pre_div CVWL568.lib(drv_crgu.o) - 0x000144b4 0x000144b4 0x00000014 Code RO 1240 i.drv_crgu_set_ahb_src CVWL568.lib(drv_crgu.o) - 0x000144c8 0x000144c8 0x00000020 Code RO 1243 i.drv_crgu_set_clock CVWL568.lib(drv_crgu.o) - 0x000144e8 0x000144e8 0x00000014 Code RO 1244 i.drv_crgu_set_dpi_mux_src CVWL568.lib(drv_crgu.o) - 0x000144fc 0x000144fc 0x00000018 Code RO 1245 i.drv_crgu_set_dpi_pre_div CVWL568.lib(drv_crgu.o) - 0x00014514 0x00014514 0x00000014 Code RO 1246 i.drv_crgu_set_dpi_pre_src CVWL568.lib(drv_crgu.o) - 0x00014528 0x00014528 0x00000014 Code RO 1247 i.drv_crgu_set_dsc_core_div CVWL568.lib(drv_crgu.o) - 0x0001453c 0x0001453c 0x00000014 Code RO 1248 i.drv_crgu_set_dsco_src CVWL568.lib(drv_crgu.o) - 0x00014550 0x00014550 0x00000014 Code RO 1249 i.drv_crgu_set_dsco_src_div CVWL568.lib(drv_crgu.o) - 0x00014564 0x00014564 0x00000014 Code RO 1250 i.drv_crgu_set_fb_div CVWL568.lib(drv_crgu.o) - 0x00014578 0x00014578 0x00000014 Code RO 1251 i.drv_crgu_set_fb_src CVWL568.lib(drv_crgu.o) - 0x0001458c 0x0001458c 0x00000014 Code RO 1254 i.drv_crgu_set_lcdc_div CVWL568.lib(drv_crgu.o) - 0x000145a0 0x000145a0 0x00000014 Code RO 1255 i.drv_crgu_set_lcdc_src CVWL568.lib(drv_crgu.o) - 0x000145b4 0x000145b4 0x00000014 Code RO 1256 i.drv_crgu_set_mipi_cfg_src CVWL568.lib(drv_crgu.o) - 0x000145c8 0x000145c8 0x00000018 Code RO 1257 i.drv_crgu_set_mipi_ref_src CVWL568.lib(drv_crgu.o) - 0x000145e0 0x000145e0 0x00000018 Code RO 1260 i.drv_crgu_set_reset CVWL568.lib(drv_crgu.o) - 0x000145f8 0x000145f8 0x00000014 Code RO 1261 i.drv_crgu_set_rxbr_div CVWL568.lib(drv_crgu.o) - 0x0001460c 0x0001460c 0x00000014 Code RO 1262 i.drv_crgu_set_rxbr_src CVWL568.lib(drv_crgu.o) - 0x00014620 0x00014620 0x00000014 Code RO 1264 i.drv_crgu_set_vidc_src CVWL568.lib(drv_crgu.o) - 0x00014634 0x00014634 0x00000018 Code RO 1317 i.drv_dma_clear_flag CVWL568.lib(drv_dma.o) - 0x0001464c 0x0001464c 0x0000000c Code RO 1325 i.drv_dma_get_channel_flag CVWL568.lib(drv_dma.o) - 0x00014658 0x00014658 0x00000090 Code RO 1328 i.drv_dma_irq_handler CVWL568.lib(drv_dma.o) - 0x000146e8 0x000146e8 0x00000036 Code RO 2318 i.drv_dsc_dec_convert_pps_rc_parameter CVWL568.lib(drv_dsc_dec.o) - 0x0001471e 0x0001471e 0x0000000c Code RO 2319 i.drv_dsc_dec_disable CVWL568.lib(drv_dsc_dec.o) - 0x0001472a 0x0001472a 0x00000002 PAD - 0x0001472c 0x0001472c 0x00000074 Code RO 2320 i.drv_dsc_dec_enable CVWL568.lib(drv_dsc_dec.o) - 0x000147a0 0x000147a0 0x0000000a Code RO 2321 i.drv_dsc_dec_get_nslc CVWL568.lib(drv_dsc_dec.o) - 0x000147aa 0x000147aa 0x00000028 Code RO 2323 i.drv_dsc_dec_set_u8_pps CVWL568.lib(drv_dsc_dec.o) - 0x000147d2 0x000147d2 0x00000002 PAD - 0x000147d4 0x000147d4 0x00000104 Code RO 1747 i.drv_dsi_rx_calc_ipi_tx_delay CVWL568.lib(drv_dsi_rx.o) - 0x000148d8 0x000148d8 0x00000040 Code RO 1748 i.drv_dsi_rx_enable_irq CVWL568.lib(drv_dsi_rx.o) - 0x00014918 0x00014918 0x0000000e Code RO 1749 i.drv_dsi_rx_get_bta_status CVWL568.lib(drv_dsi_rx.o) - 0x00014926 0x00014926 0x00000002 PAD - 0x00014928 0x00014928 0x00000050 Code RO 1750 i.drv_dsi_rx_get_color_bpp CVWL568.lib(drv_dsi_rx.o) - 0x00014978 0x00014978 0x0000001c Code RO 1751 i.drv_dsi_rx_get_color_pcc CVWL568.lib(drv_dsi_rx.o) - 0x00014994 0x00014994 0x00000008 Code RO 1752 i.drv_dsi_rx_get_compression_en CVWL568.lib(drv_dsi_rx.o) - 0x0001499c 0x0001499c 0x00000006 Code RO 1753 i.drv_dsi_rx_get_max_ret_size CVWL568.lib(drv_dsi_rx.o) - 0x000149a2 0x000149a2 0x0000000e Code RO 1757 i.drv_dsi_rx_power_up CVWL568.lib(drv_dsi_rx.o) - 0x000149b0 0x000149b0 0x00000020 Code RO 1758 i.drv_dsi_rx_set_ctrl_cfg CVWL568.lib(drv_dsi_rx.o) - 0x000149d0 0x000149d0 0x00000010 Code RO 1759 i.drv_dsi_rx_set_ddi_cfg CVWL568.lib(drv_dsi_rx.o) - 0x000149e0 0x000149e0 0x00000004 Code RO 1761 i.drv_dsi_rx_set_inten CVWL568.lib(drv_dsi_rx.o) - 0x000149e4 0x000149e4 0x00000010 Code RO 1762 i.drv_dsi_rx_set_ipi_cfg CVWL568.lib(drv_dsi_rx.o) - 0x000149f4 0x000149f4 0x00000046 Code RO 1764 i.drv_dsi_rx_set_lane_swap CVWL568.lib(drv_dsi_rx.o) - 0x00014a3a 0x00014a3a 0x00000026 Code RO 1765 i.drv_dsi_rx_set_resp_cnt CVWL568.lib(drv_dsi_rx.o) - 0x00014a60 0x00014a60 0x00000104 Code RO 1766 i.drv_dsi_rx_set_up_phy CVWL568.lib(drv_dsi_rx.o) - 0x00014b64 0x00014b64 0x0000000e Code RO 1767 i.drv_dsi_rx_shut_down CVWL568.lib(drv_dsi_rx.o) - 0x00014b72 0x00014b72 0x00000014 Code RO 1806 i.drv_dsi_tx_command_header CVWL568.lib(drv_dsi_tx.o) - 0x00014b86 0x00014b86 0x0000006c Code RO 1807 i.drv_dsi_tx_command_mode_cfg CVWL568.lib(drv_dsi_tx.o) - 0x00014bf2 0x00014bf2 0x00000004 Code RO 1808 i.drv_dsi_tx_command_put_payload CVWL568.lib(drv_dsi_tx.o) - 0x00014bf6 0x00014bf6 0x00000018 Code RO 1809 i.drv_dsi_tx_config_eotp CVWL568.lib(drv_dsi_tx.o) - 0x00014c0e 0x00014c0e 0x00000008 Code RO 1810 i.drv_dsi_tx_config_int CVWL568.lib(drv_dsi_tx.o) - 0x00014c16 0x00014c16 0x00000008 Code RO 1811 i.drv_dsi_tx_dpi_lpcmd_time CVWL568.lib(drv_dsi_tx.o) - 0x00014c1e 0x00014c1e 0x0000000a Code RO 1812 i.drv_dsi_tx_dpi_mode CVWL568.lib(drv_dsi_tx.o) - 0x00014c28 0x00014c28 0x00000024 Code RO 1813 i.drv_dsi_tx_dpi_polarity CVWL568.lib(drv_dsi_tx.o) - 0x00014c4c 0x00014c4c 0x00000004 Code RO 1814 i.drv_dsi_tx_edpi_cmd_size CVWL568.lib(drv_dsi_tx.o) - 0x00014c50 0x00014c50 0x00000004 Code RO 1816 i.drv_dsi_tx_get_cmd_status CVWL568.lib(drv_dsi_tx.o) - 0x00014c54 0x00014c54 0x00000004 Code RO 1818 i.drv_dsi_tx_mode CVWL568.lib(drv_dsi_tx.o) - 0x00014c58 0x00014c58 0x00000018 Code RO 1819 i.drv_dsi_tx_phy_clock_lane_auto_lp CVWL568.lib(drv_dsi_tx.o) - 0x00014c70 0x00014c70 0x0000001a Code RO 1820 i.drv_dsi_tx_phy_clock_lane_req_hs CVWL568.lib(drv_dsi_tx.o) - 0x00014c8a 0x00014c8a 0x0000000c Code RO 1822 i.drv_dsi_tx_phy_lane_mode CVWL568.lib(drv_dsi_tx.o) - 0x00014c96 0x00014c96 0x00000064 Code RO 1826 i.drv_dsi_tx_phy_status_ready CVWL568.lib(drv_dsi_tx.o) - 0x00014cfa 0x00014cfa 0x0000003e Code RO 1827 i.drv_dsi_tx_phy_status_stopstate CVWL568.lib(drv_dsi_tx.o) - 0x00014d38 0x00014d38 0x00000134 Code RO 1829 i.drv_dsi_tx_phy_test_setup CVWL568.lib(drv_dsi_tx.o) - 0x00014e6c 0x00014e6c 0x0000001e Code RO 1830 i.drv_dsi_tx_phy_time_cfg CVWL568.lib(drv_dsi_tx.o) - 0x00014e8a 0x00014e8a 0x00000008 Code RO 1834 i.drv_dsi_tx_powerup CVWL568.lib(drv_dsi_tx.o) - 0x00014e92 0x00014e92 0x0000001c Code RO 1835 i.drv_dsi_tx_response_mode CVWL568.lib(drv_dsi_tx.o) - 0x00014eae 0x00014eae 0x00000018 Code RO 1838 i.drv_dsi_tx_set_bta_ack CVWL568.lib(drv_dsi_tx.o) - 0x00014ec6 0x00014ec6 0x0000000c Code RO 1839 i.drv_dsi_tx_set_esc_div CVWL568.lib(drv_dsi_tx.o) - 0x00014ed2 0x00014ed2 0x00000002 PAD - 0x00014ed4 0x00014ed4 0x00000040 Code RO 1840 i.drv_dsi_tx_set_int CVWL568.lib(drv_dsi_tx.o) - 0x00014f14 0x00014f14 0x00000010 Code RO 1841 i.drv_dsi_tx_set_time_out_div CVWL568.lib(drv_dsi_tx.o) - 0x00014f24 0x00014f24 0x00000008 Code RO 1842 i.drv_dsi_tx_set_video_chunk CVWL568.lib(drv_dsi_tx.o) - 0x00014f2c 0x00014f2c 0x00000022 Code RO 1843 i.drv_dsi_tx_set_video_timing CVWL568.lib(drv_dsi_tx.o) - 0x00014f4e 0x00014f4e 0x00000008 Code RO 1845 i.drv_dsi_tx_shutdown CVWL568.lib(drv_dsi_tx.o) - 0x00014f56 0x00014f56 0x00000026 Code RO 1846 i.drv_dsi_tx_timeout_cfg CVWL568.lib(drv_dsi_tx.o) - 0x00014f7c 0x00014f7c 0x000000aa Code RO 1849 i.drv_dsi_tx_video_mode_cfg CVWL568.lib(drv_dsi_tx.o) - 0x00015026 0x00015026 0x00000016 Code RO 1850 i.drv_dsi_tx_video_mode_disable_hact_cmd CVWL568.lib(drv_dsi_tx.o) - 0x0001503c 0x0001503c 0x00000018 Code RO 1851 i.drv_dsi_tx_video_mode_set_lp_cmd CVWL568.lib(drv_dsi_tx.o) - 0x00015054 0x00015054 0x0000002e Code RO 2256 i.drv_efuse_enter_inactive CVWL568.lib(drv_efuse.o) - 0x00015082 0x00015082 0x0000000c Code RO 2259 i.drv_efuse_int_enable CVWL568.lib(drv_efuse.o) - 0x0001508e 0x0001508e 0x00000032 Code RO 2260 i.drv_efuse_read CVWL568.lib(drv_efuse.o) - 0x000150c0 0x000150c0 0x00000018 Code RO 2261 i.drv_efuse_read_req CVWL568.lib(drv_efuse.o) - 0x000150d8 0x000150d8 0x00000020 Code RO 1466 i.drv_gpio_set_ioe CVWL568.lib(drv_gpio.o) - 0x000150f8 0x000150f8 0x00000010 Code RO 1467 i.drv_gpio_set_mode0 CVWL568.lib(drv_gpio.o) - 0x00015108 0x00015108 0x00000010 Code RO 1468 i.drv_gpio_set_mode1 CVWL568.lib(drv_gpio.o) - 0x00015118 0x00015118 0x00000010 Code RO 1469 i.drv_gpio_set_mode2 CVWL568.lib(drv_gpio.o) - 0x00015128 0x00015128 0x00000010 Code RO 1470 i.drv_gpio_set_mode3 CVWL568.lib(drv_gpio.o) - 0x00015138 0x00015138 0x00000020 Code RO 902 i.drv_gpio_set_output_data CVWL568.lib(hal_gpio.o) - 0x00015158 0x00015158 0x00000018 Code RO 1918 i.drv_lcdc_config_bypass CVWL568.lib(drv_lcdc.o) - 0x00015170 0x00015170 0x00000030 Code RO 1919 i.drv_lcdc_config_ccm CVWL568.lib(drv_lcdc.o) - 0x000151a0 0x000151a0 0x00000016 Code RO 1920 i.drv_lcdc_config_disp_mode CVWL568.lib(drv_lcdc.o) - 0x000151b6 0x000151b6 0x00000024 Code RO 1921 i.drv_lcdc_config_dpi_polarity CVWL568.lib(drv_lcdc.o) - 0x000151da 0x000151da 0x00000026 Code RO 1922 i.drv_lcdc_config_dpi_timing CVWL568.lib(drv_lcdc.o) - 0x00015200 0x00015200 0x00000016 Code RO 1923 i.drv_lcdc_config_edpi_mode CVWL568.lib(drv_lcdc.o) - 0x00015216 0x00015216 0x00000016 Code RO 1924 i.drv_lcdc_config_endianness CVWL568.lib(drv_lcdc.o) - 0x0001522c 0x0001522c 0x0000000c Code RO 1925 i.drv_lcdc_config_input_size CVWL568.lib(drv_lcdc.o) - 0x00015238 0x00015238 0x0000001e Code RO 1926 i.drv_lcdc_config_int CVWL568.lib(drv_lcdc.o) - 0x00015256 0x00015256 0x00000022 Code RO 1927 i.drv_lcdc_config_int_single CVWL568.lib(drv_lcdc.o) - 0x00015278 0x00015278 0x00000022 Code RO 1928 i.drv_lcdc_config_overwrite CVWL568.lib(drv_lcdc.o) - 0x0001529a 0x0001529a 0x0000000c Code RO 1929 i.drv_lcdc_config_overwrite_rgb CVWL568.lib(drv_lcdc.o) - 0x000152a6 0x000152a6 0x0000001a Code RO 1930 i.drv_lcdc_config_partial_display_area CVWL568.lib(drv_lcdc.o) - 0x000152c0 0x000152c0 0x00000022 Code RO 1931 i.drv_lcdc_config_partial_display_enable CVWL568.lib(drv_lcdc.o) - 0x000152e2 0x000152e2 0x0000001a Code RO 1933 i.drv_lcdc_config_scale_up_coef CVWL568.lib(drv_lcdc.o) - 0x000152fc 0x000152fc 0x0000000c Code RO 1934 i.drv_lcdc_config_scale_up_step CVWL568.lib(drv_lcdc.o) - 0x00015308 0x00015308 0x0000004c Code RO 1935 i.drv_lcdc_config_src_parameter CVWL568.lib(drv_lcdc.o) - 0x00015354 0x00015354 0x00000006 Code RO 1936 i.drv_lcdc_config_thresh CVWL568.lib(drv_lcdc.o) - 0x0001535a 0x0001535a 0x00000012 Code RO 1937 i.drv_lcdc_ctrl_flow CVWL568.lib(drv_lcdc.o) - 0x0001536c 0x0001536c 0x00000020 Code RO 1939 i.drv_lcdc_enable_shadow_reg CVWL568.lib(drv_lcdc.o) - 0x0001538c 0x0001538c 0x00000040 Code RO 1940 i.drv_lcdc_set_int CVWL568.lib(drv_lcdc.o) - 0x000153cc 0x000153cc 0x00000018 Code RO 1941 i.drv_lcdc_set_prefetch CVWL568.lib(drv_lcdc.o) - 0x000153e4 0x000153e4 0x00000014 Code RO 1942 i.drv_lcdc_set_video_hw_mode CVWL568.lib(drv_lcdc.o) - 0x000153f8 0x000153f8 0x00000020 Code RO 1943 i.drv_lcdc_start CVWL568.lib(drv_lcdc.o) - 0x00015418 0x00015418 0x0000000c Code RO 1977 i.drv_memc_clear_status CVWL568.lib(drv_memc.o) - 0x00015424 0x00015424 0x00000040 Code RO 1978 i.drv_memc_enable_irq CVWL568.lib(drv_memc.o) - 0x00015464 0x00015464 0x0000000c Code RO 1979 i.drv_memc_gen_a_tear_signal CVWL568.lib(drv_memc.o) - 0x00015470 0x00015470 0x00000012 Code RO 1980 i.drv_memc_get_status CVWL568.lib(drv_memc.o) - 0x00015482 0x00015482 0x00000010 Code RO 1981 i.drv_memc_rate_transfer_sel CVWL568.lib(drv_memc.o) - 0x00015492 0x00015492 0x0000000e Code RO 1982 i.drv_memc_sel_vsync CVWL568.lib(drv_memc.o) - 0x000154a0 0x000154a0 0x00000014 Code RO 1983 i.drv_memc_set_active_height CVWL568.lib(drv_memc.o) - 0x000154b4 0x000154b4 0x0000000c Code RO 1984 i.drv_memc_set_data_mode CVWL568.lib(drv_memc.o) - 0x000154c0 0x000154c0 0x00000010 Code RO 1987 i.drv_memc_set_double_buffer CVWL568.lib(drv_memc.o) - 0x000154d0 0x000154d0 0x00000012 Code RO 1988 i.drv_memc_set_double_buffer_reverse CVWL568.lib(drv_memc.o) - 0x000154e2 0x000154e2 0x00000010 Code RO 1990 i.drv_memc_set_fs_en_conditions CVWL568.lib(drv_memc.o) - 0x000154f2 0x000154f2 0x00000014 Code RO 1991 i.drv_memc_set_inten CVWL568.lib(drv_memc.o) - 0x00015506 0x00015506 0x00000002 PAD - 0x00015508 0x00015508 0x00000018 Code RO 1992 i.drv_memc_set_lcdc_st_conditions CVWL568.lib(drv_memc.o) - 0x00015520 0x00015520 0x0000001a Code RO 1993 i.drv_memc_set_ltpo_mode CVWL568.lib(drv_memc.o) - 0x0001553a 0x0001553a 0x0000000e Code RO 1997 i.drv_memc_set_tear_mode CVWL568.lib(drv_memc.o) - 0x00015548 0x00015548 0x00000028 Code RO 1998 i.drv_memc_set_tear_waveform CVWL568.lib(drv_memc.o) - 0x00015570 0x00015570 0x0000000e Code RO 2000 i.drv_memc_set_vidc_sync_cnt CVWL568.lib(drv_memc.o) - 0x0001557e 0x0001557e 0x00000002 PAD - 0x00015580 0x00015580 0x00000008 Code RO 1589 i.drv_param_init_get_ccm CVWL568.lib(drv_param_init.o) - 0x00015588 0x00015588 0x00000014 Code RO 1590 i.drv_param_init_get_scld_filter_h CVWL568.lib(drv_param_init.o) - 0x0001559c 0x0001559c 0x00000014 Code RO 1591 i.drv_param_init_get_scld_filter_v CVWL568.lib(drv_param_init.o) - 0x000155b0 0x000155b0 0x00000008 Code RO 1592 i.drv_param_init_get_sclu_filter CVWL568.lib(drv_param_init.o) - 0x000155b8 0x000155b8 0x00000014 Code RO 1593 i.drv_param_init_set_ccm CVWL568.lib(drv_param_init.o) - 0x000155cc 0x000155cc 0x00000064 Code RO 1594 i.drv_param_init_set_scld_filter CVWL568.lib(drv_param_init.o) - 0x00015630 0x00015630 0x00000024 Code RO 1596 i.drv_param_p2r_filter_init CVWL568.lib(drv_param_init.o) - 0x00015654 0x00015654 0x00000010 Code RO 2277 i.drv_phy_enable_calibration CVWL568.lib(drv_phy_common.o) - 0x00015664 0x00015664 0x0000003c Code RO 2278 i.drv_phy_get_calibration CVWL568.lib(drv_phy_common.o) - 0x000156a0 0x000156a0 0x00000060 Code RO 2279 i.drv_phy_get_pll_para CVWL568.lib(drv_phy_common.o) - 0x00015700 0x00015700 0x00000054 Code RO 2280 i.drv_phy_get_rate_para CVWL568.lib(drv_phy_common.o) - 0x00015754 0x00015754 0x00000010 Code RO 2281 i.drv_phy_test_clear CVWL568.lib(drv_phy_common.o) - 0x00015764 0x00015764 0x00000018 Code RO 2282 i.drv_phy_test_lock CVWL568.lib(drv_phy_common.o) - 0x0001577c 0x0001577c 0x00000020 Code RO 2284 i.drv_phy_test_write_1_byte CVWL568.lib(drv_phy_common.o) - 0x0001579c 0x0001579c 0x00000026 Code RO 2285 i.drv_phy_test_write_2_byte CVWL568.lib(drv_phy_common.o) - 0x000157c2 0x000157c2 0x0000001e Code RO 2286 i.drv_phy_test_write_code CVWL568.lib(drv_phy_common.o) - 0x000157e0 0x000157e0 0x00000020 Code RO 2287 i.drv_phy_test_write_data CVWL568.lib(drv_phy_common.o) - 0x00015800 0x00015800 0x00000018 Code RO 1614 i.drv_pwr_set_pvd_mode CVWL568.lib(drv_pwr.o) - 0x00015818 0x00015818 0x00000038 Code RO 1615 i.drv_pwr_set_system_clk_src CVWL568.lib(drv_pwr.o) - 0x00015850 0x00015850 0x0000000c Code RO 1768 i.drv_rx_phy_test_clear CVWL568.lib(drv_dsi_rx.o) - 0x0001585c 0x0001585c 0x00000010 Code RO 1769 i.drv_rx_phy_test_lock CVWL568.lib(drv_dsi_rx.o) - 0x0001586c 0x0001586c 0x00000014 Code RO 1771 i.drv_rx_phy_test_write_1_byte CVWL568.lib(drv_dsi_rx.o) - 0x00015880 0x00015880 0x00000016 Code RO 1772 i.drv_rx_phy_test_write_2_byte CVWL568.lib(drv_dsi_rx.o) - 0x00015896 0x00015896 0x0000000a Code RO 2036 i.drv_rxbr_clear_pkt_buffer CVWL568.lib(drv_rxbr.o) - 0x000158a0 0x000158a0 0x00000004 Code RO 2037 i.drv_rxbr_clear_status0 CVWL568.lib(drv_rxbr.o) - 0x000158a4 0x000158a4 0x0000005a Code RO 2039 i.drv_rxbr_enable_irq CVWL568.lib(drv_rxbr.o) - 0x000158fe 0x000158fe 0x00000002 PAD - 0x00015900 0x00015900 0x00000014 Code RO 2040 i.drv_rxbr_frame_drop_cfg CVWL568.lib(drv_rxbr.o) - 0x00015914 0x00015914 0x00000064 Code RO 2041 i.drv_rxbr_get_clk CVWL568.lib(drv_rxbr.o) - 0x00015978 0x00015978 0x00000004 Code RO 2042 i.drv_rxbr_get_col_addr CVWL568.lib(drv_rxbr.o) - 0x0001597c 0x0001597c 0x00000012 Code RO 1104 i.drv_rxbr_get_int_source CVWL568.lib(hal_internal_vsync.o) - 0x0001598e 0x0001598e 0x00000004 Code RO 2045 i.drv_rxbr_get_page_addr CVWL568.lib(drv_rxbr.o) - 0x00015992 0x00015992 0x0000000c Code RO 2047 i.drv_rxbr_get_pkt_buf_error_status CVWL568.lib(drv_rxbr.o) - 0x0001599e 0x0001599e 0x00000012 Code RO 1105 i.drv_rxbr_get_status0 CVWL568.lib(hal_internal_vsync.o) - 0x000159b0 0x000159b0 0x00000016 Code RO 1106 i.drv_rxbr_get_status1 CVWL568.lib(hal_internal_vsync.o) - 0x000159c6 0x000159c6 0x0000000c Code RO 2048 i.drv_rxbr_hline_rcv0_cfg CVWL568.lib(drv_rxbr.o) - 0x000159d2 0x000159d2 0x0000000c Code RO 2049 i.drv_rxbr_hline_rcv1_cfg CVWL568.lib(drv_rxbr.o) - 0x000159de 0x000159de 0x00000008 Code RO 2050 i.drv_rxbr_hline_rcv_cfg CVWL568.lib(drv_rxbr.o) - 0x000159e6 0x000159e6 0x00000002 PAD - 0x000159e8 0x000159e8 0x0000000c Code RO 2051 i.drv_rxbr_register_irq0_callback CVWL568.lib(drv_rxbr.o) - 0x000159f4 0x000159f4 0x0000000c Code RO 2052 i.drv_rxbr_register_irq1_callback CVWL568.lib(drv_rxbr.o) - 0x00015a00 0x00015a00 0x00000014 Code RO 2053 i.drv_rxbr_set_ack_pkt_header CVWL568.lib(drv_rxbr.o) - 0x00015a14 0x00015a14 0x00000014 Code RO 2056 i.drv_rxbr_set_color_format CVWL568.lib(drv_rxbr.o) - 0x00015a28 0x00015a28 0x00000012 Code RO 2058 i.drv_rxbr_set_filter_regs CVWL568.lib(drv_rxbr.o) - 0x00015a3a 0x00015a3a 0x00000014 Code RO 2059 i.drv_rxbr_set_inten CVWL568.lib(drv_rxbr.o) - 0x00015a4e 0x00015a4e 0x00000010 Code RO 2060 i.drv_rxbr_set_ltpo_drop_th CVWL568.lib(drv_rxbr.o) - 0x00015a5e 0x00015a5e 0x00000026 Code RO 2062 i.drv_rxbr_set_usr_cfg CVWL568.lib(drv_rxbr.o) - 0x00015a84 0x00015a84 0x00000008 Code RO 2063 i.drv_rxbr_set_usr_col CVWL568.lib(drv_rxbr.o) - 0x00015a8c 0x00015a8c 0x00000008 Code RO 2064 i.drv_rxbr_set_usr_row CVWL568.lib(drv_rxbr.o) - 0x00015a94 0x00015a94 0x00000054 Code RO 2557 i.drv_swire_set_int CVWL568.lib(drv_swire.o) - 0x00015ae8 0x00015ae8 0x0000000c Code RO 1685 i.drv_sys_cfg_clear_all_int CVWL568.lib(drv_sys_cfg.o) - 0x00015af4 0x00015af4 0x00000028 Code RO 1686 i.drv_sys_cfg_clear_pending CVWL568.lib(drv_sys_cfg.o) - 0x00015b1c 0x00015b1c 0x00000018 Code RO 1689 i.drv_sys_cfg_sel_ap_rst_lvl_trig CVWL568.lib(drv_sys_cfg.o) - 0x00015b34 0x00015b34 0x00000024 Code RO 1696 i.drv_sys_cfg_set_int CVWL568.lib(drv_sys_cfg.o) - 0x00015b58 0x00015b58 0x0000001a Code RO 2576 i.drv_timer_clear_status_flags CVWL568.lib(drv_timer.o) - 0x00015b72 0x00015b72 0x00000020 Code RO 2577 i.drv_timer_enable CVWL568.lib(drv_timer.o) - 0x00015b92 0x00015b92 0x00000002 PAD - 0x00015b94 0x00015b94 0x00000010 Code RO 2578 i.drv_timer_get_instance CVWL568.lib(drv_timer.o) - 0x00015ba4 0x00015ba4 0x00000044 Code RO 2581 i.drv_timer_handle_interrupt CVWL568.lib(drv_timer.o) - 0x00015be8 0x00015be8 0x00000010 Code RO 2583 i.drv_timer_set_compare_val CVWL568.lib(drv_timer.o) - 0x00015bf8 0x00015bf8 0x00000054 Code RO 2584 i.drv_timer_set_int CVWL568.lib(drv_timer.o) - 0x00015c4c 0x00015c4c 0x0000000a Code RO 1852 i.drv_tx_phy_test_clear CVWL568.lib(drv_dsi_tx.o) - 0x00015c56 0x00015c56 0x0000001c Code RO 1853 i.drv_tx_phy_test_enter CVWL568.lib(drv_dsi_tx.o) - 0x00015c72 0x00015c72 0x0000001c Code RO 1854 i.drv_tx_phy_test_exit CVWL568.lib(drv_dsi_tx.o) - 0x00015c8e 0x00015c8e 0x00000012 Code RO 1856 i.drv_tx_phy_test_write_1_byte CVWL568.lib(drv_dsi_tx.o) - 0x00015ca0 0x00015ca0 0x00000014 Code RO 1857 i.drv_tx_phy_test_write_2_byte CVWL568.lib(drv_dsi_tx.o) - 0x00015cb4 0x00015cb4 0x00000010 Code RO 1858 i.drv_tx_phy_test_write_code CVWL568.lib(drv_dsi_tx.o) - 0x00015cc4 0x00015cc4 0x00000008 Code RO 2106 i.drv_vidc_clear_irq CVWL568.lib(drv_vidc.o) - 0x00015ccc 0x00015ccc 0x00000018 Code RO 2110 i.drv_vidc_enable CVWL568.lib(drv_vidc.o) - 0x00015ce4 0x00015ce4 0x00000040 Code RO 2111 i.drv_vidc_enable_irq CVWL568.lib(drv_vidc.o) - 0x00015d24 0x00015d24 0x00000012 Code RO 2113 i.drv_vidc_get_irq_status CVWL568.lib(drv_vidc.o) - 0x00015d36 0x00015d36 0x00000002 PAD - 0x00015d38 0x00015d38 0x00000028 Code RO 2117 i.drv_vidc_init_module_enable CVWL568.lib(drv_vidc.o) - 0x00015d60 0x00015d60 0x0000000c Code RO 2118 i.drv_vidc_register_callback CVWL568.lib(drv_vidc.o) - 0x00015d6c 0x00015d6c 0x00000006 Code RO 2119 i.drv_vidc_reset CVWL568.lib(drv_vidc.o) - 0x00015d72 0x00015d72 0x0000003c Code RO 2121 i.drv_vidc_set_dst_parameter CVWL568.lib(drv_vidc.o) - 0x00015dae 0x00015dae 0x00000014 Code RO 2125 i.drv_vidc_set_irqen CVWL568.lib(drv_vidc.o) - 0x00015dc2 0x00015dc2 0x00000010 Code RO 2126 i.drv_vidc_set_mirror CVWL568.lib(drv_vidc.o) - 0x00015dd2 0x00015dd2 0x00000008 Code RO 2129 i.drv_vidc_set_p2r_hcoef0 CVWL568.lib(drv_vidc.o) - 0x00015dda 0x00015dda 0x00000026 Code RO 2130 i.drv_vidc_set_p2r_hinitb CVWL568.lib(drv_vidc.o) - 0x00015e00 0x00015e00 0x00000026 Code RO 2131 i.drv_vidc_set_p2r_hinitr CVWL568.lib(drv_vidc.o) - 0x00015e26 0x00015e26 0x00000002 PAD - 0x00015e28 0x00015e28 0x00000018 Code RO 2132 i.drv_vidc_set_pentile_swap CVWL568.lib(drv_vidc.o) - 0x00015e40 0x00015e40 0x0000000a Code RO 2133 i.drv_vidc_set_pu_ctrl CVWL568.lib(drv_vidc.o) - 0x00015e4a 0x00015e4a 0x00000010 Code RO 2134 i.drv_vidc_set_rotation CVWL568.lib(drv_vidc.o) - 0x00015e5a 0x00015e5a 0x0000000a Code RO 2135 i.drv_vidc_set_scld_hcoef0 CVWL568.lib(drv_vidc.o) - 0x00015e64 0x00015e64 0x0000000a Code RO 2136 i.drv_vidc_set_scld_hcoef1 CVWL568.lib(drv_vidc.o) - 0x00015e6e 0x00015e6e 0x00000012 Code RO 2137 i.drv_vidc_set_scld_step CVWL568.lib(drv_vidc.o) - 0x00015e80 0x00015e80 0x0000000a Code RO 2138 i.drv_vidc_set_scld_vcoef0 CVWL568.lib(drv_vidc.o) - 0x00015e8a 0x00015e8a 0x0000000a Code RO 2139 i.drv_vidc_set_scld_vcoef1 CVWL568.lib(drv_vidc.o) - 0x00015e94 0x00015e94 0x00000016 Code RO 2140 i.drv_vidc_set_src_parameter CVWL568.lib(drv_vidc.o) - 0x00015eaa 0x00015eaa 0x00000002 PAD - 0x00015eac 0x00015eac 0x00000010 Code RO 2695 i.drv_wdg_clear_counter CVWL568.lib(drv_wdg.o) - 0x00015ebc 0x00015ebc 0x00000010 Code RO 2696 i.drv_wdg_clear_edge_flag CVWL568.lib(drv_wdg.o) - 0x00015ecc 0x00015ecc 0x00000010 Code RO 2699 i.drv_wdg_read_edge_flag CVWL568.lib(drv_wdg.o) - 0x00015edc 0x00015edc 0x00000040 Code RO 2702 i.drv_wdg_set_int CVWL568.lib(drv_wdg.o) - 0x00015f1c 0x00015f1c 0x0000000a Code RO 1372 i.fls_clr_interrupt_flag CVWL568.lib(drv_fls.o) - 0x00015f26 0x00015f26 0x00000014 Code RO 1071 i.fputc CVWL568.lib(tau_log.o) - 0x00015f3a 0x00015f3a 0x00000002 PAD - 0x00015f3c 0x00015f3c 0x00000050 Code RO 114 i.frame_start_cb ap_demo.o - 0x00015f8c 0x00015f8c 0x00000034 Code RO 701 i.hal_dsi_rx_ctrl_create_handle CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00015fc0 0x00015fc0 0x00000028 Code RO 705 i.hal_dsi_rx_ctrl_dsc_async_handler CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00015fe8 0x00015fe8 0x00000028 Code RO 707 i.hal_dsi_rx_ctrl_gen_a_tear_signal CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00016010 0x00016010 0x00000028 Code RO 709 i.hal_dsi_rx_ctrl_get_max_ret_size CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00016038 0x00016038 0x00000098 Code RO 711 i.hal_dsi_rx_ctrl_init CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x000160d0 0x000160d0 0x000001a4 Code RO 712 i.hal_dsi_rx_ctrl_init_clk CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00016274 0x00016274 0x000000d8 Code RO 713 i.hal_dsi_rx_ctrl_init_dsi_rx CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x0001634c 0x0001634c 0x00000160 Code RO 714 i.hal_dsi_rx_ctrl_init_memc CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x000164ac 0x000164ac 0x00000150 Code RO 715 i.hal_dsi_rx_ctrl_init_rxbr CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x000165fc 0x000165fc 0x0000022c Code RO 716 i.hal_dsi_rx_ctrl_init_vidc CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00016828 0x00016828 0x0000003c Code RO 717 i.hal_dsi_rx_ctrl_pre_init_pps CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00016864 0x00016864 0x00000050 Code RO 720 i.hal_dsi_rx_ctrl_restart CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x000168b4 0x000168b4 0x000000f0 Code RO 721 i.hal_dsi_rx_ctrl_send_ack_cmd CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x000169a4 0x000169a4 0x0000002c Code RO 723 i.hal_dsi_rx_ctrl_set_cus_esc_clk CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x000169d0 0x000169d0 0x0000006c Code RO 724 i.hal_dsi_rx_ctrl_set_cus_scld_filter CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00016a3c 0x00016a3c 0x00000034 Code RO 725 i.hal_dsi_rx_ctrl_set_cus_sync_line CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00016a70 0x00016a70 0x00000038 Code RO 729 i.hal_dsi_rx_ctrl_set_ipi_cfg CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00016aa8 0x00016aa8 0x00000072 Code RO 734 i.hal_dsi_rx_ctrl_set_rxbr_clk CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00016b1a 0x00016b1a 0x0000000e Code RO 737 i.hal_dsi_rx_ctrl_set_tear_mode_ex CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00016b28 0x00016b28 0x0000003c Code RO 738 i.hal_dsi_rx_ctrl_start CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00016b64 0x00016b64 0x00000020 Code RO 741 i.hal_dsi_rx_ctrl_toggle_resolution CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x00016b84 0x00016b84 0x00000190 Code RO 796 i.hal_dsi_tx_calc_video_chunks CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00016d14 0x00016d14 0x00000034 Code RO 797 i.hal_dsi_tx_config_params_for_lane_rate CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00016d48 0x00016d48 0x00000428 Code RO 798 i.hal_dsi_tx_count_lane_rate CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00017170 0x00017170 0x0000002c Code RO 801 i.hal_dsi_tx_ctrl_create_handle CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x0001719c 0x0001719c 0x0000004c Code RO 806 i.hal_dsi_tx_ctrl_enter_init_panel_mode CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x000171e8 0x000171e8 0x00000028 Code RO 808 i.hal_dsi_tx_ctrl_exit_init_panel_mode CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00017210 0x00017210 0x000000a4 Code RO 810 i.hal_dsi_tx_ctrl_init CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x000172b4 0x000172b4 0x00000024 Code RO 811 i.hal_dsi_tx_ctrl_init_clk CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x000172d8 0x000172d8 0x0000000c Code RO 812 i.hal_dsi_tx_ctrl_panel_reset_pin CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x000172e4 0x000172e4 0x00000020 Code RO 815 i.hal_dsi_tx_ctrl_set_ccm CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00017304 0x00017304 0x00000014 Code RO 821 i.hal_dsi_tx_ctrl_set_overwrite_rgb CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00017318 0x00017318 0x00000010 Code RO 822 i.hal_dsi_tx_ctrl_set_partial_disp CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00017328 0x00017328 0x00000024 Code RO 823 i.hal_dsi_tx_ctrl_set_partial_disp_area CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x0001734c 0x0001734c 0x000000a8 Code RO 826 i.hal_dsi_tx_ctrl_start CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x000173f4 0x000173f4 0x000000f0 Code RO 828 i.hal_dsi_tx_ctrl_write_array_cmd CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x000174e4 0x000174e4 0x000000cc Code RO 829 i.hal_dsi_tx_ctrl_write_cmd CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x000175b0 0x000175b0 0x00000044 Code RO 830 i.hal_dsi_tx_init_data_mode CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x000175f4 0x000175f4 0x00000030 Code RO 831 i.hal_dsi_tx_init_dpi_cfg CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00017624 0x00017624 0x00000020 Code RO 832 i.hal_dsi_tx_init_interrupt CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00017644 0x00017644 0x00000020 Code RO 833 i.hal_dsi_tx_init_phy_cfg CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00017664 0x00017664 0x00000094 Code RO 834 i.hal_dsi_tx_init_remains CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x000176f8 0x000176f8 0x00000058 Code RO 835 i.hal_dsi_tx_init_video_mode CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00017750 0x00017750 0x00000044 Code RO 836 i.hal_dsi_tx_send_cmd CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00017794 0x00017794 0x00000028 Code RO 909 i.hal_gpio_init_output CVWL568.lib(hal_gpio.o) - 0x000177bc 0x000177bc 0x00000060 Code RO 913 i.hal_gpio_set_mode CVWL568.lib(hal_gpio.o) - 0x0001781c 0x0001781c 0x00000008 Code RO 914 i.hal_gpio_set_output_data CVWL568.lib(hal_gpio.o) - 0x00017824 0x00017824 0x00000018 Code RO 1107 i.hal_internal_check_video_auto_sync CVWL568.lib(hal_internal_vsync.o) - 0x0001783c 0x0001783c 0x000000fc Code RO 1108 i.hal_internal_init_memc CVWL568.lib(hal_internal_vsync.o) - 0x00017938 0x00017938 0x0000002a Code RO 1109 i.hal_internal_rx_dcs_async_handler CVWL568.lib(hal_internal_vsync.o) - 0x00017962 0x00017962 0x00000002 PAD - 0x00017964 0x00017964 0x00000058 Code RO 1110 i.hal_internal_rx_dcs_polling CVWL568.lib(hal_internal_vsync.o) - 0x000179bc 0x000179bc 0x00000010 Code RO 1112 i.hal_internal_sync_get_fb_setting CVWL568.lib(hal_internal_vsync.o) - 0x000179cc 0x000179cc 0x00000010 Code RO 1113 i.hal_internal_sync_get_hight_performan_mode CVWL568.lib(hal_internal_vsync.o) - 0x000179dc 0x000179dc 0x0000022c Code RO 1114 i.hal_internal_sync_input_resolution_change CVWL568.lib(hal_internal_vsync.o) - 0x00017c08 0x00017c08 0x00000028 Code RO 1117 i.hal_internal_vsync_deinit CVWL568.lib(hal_internal_vsync.o) - 0x00017c30 0x00017c30 0x00000018 Code RO 1119 i.hal_internal_vsync_get_sync_line CVWL568.lib(hal_internal_vsync.o) - 0x00017c48 0x00017c48 0x0000000c Code RO 1120 i.hal_internal_vsync_get_tear_mode CVWL568.lib(hal_internal_vsync.o) - 0x00017c54 0x00017c54 0x0000000c Code RO 1121 i.hal_internal_vsync_get_tx_state CVWL568.lib(hal_internal_vsync.o) - 0x00017c60 0x00017c60 0x00000140 Code RO 1122 i.hal_internal_vsync_init_rx CVWL568.lib(hal_internal_vsync.o) - 0x00017da0 0x00017da0 0x000000b0 Code RO 1123 i.hal_internal_vsync_init_tx CVWL568.lib(hal_internal_vsync.o) - 0x00017e50 0x00017e50 0x00000090 Code RO 1125 i.hal_internal_vsync_set_auto_hw_filter CVWL568.lib(hal_internal_vsync.o) - 0x00017ee0 0x00017ee0 0x00000024 Code RO 1127 i.hal_internal_vsync_set_rx_state CVWL568.lib(hal_internal_vsync.o) - 0x00017f04 0x00017f04 0x00000044 Code RO 1128 i.hal_internal_vsync_set_sync_line CVWL568.lib(hal_internal_vsync.o) - 0x00017f48 0x00017f48 0x00000050 Code RO 1129 i.hal_internal_vsync_set_tear_mode CVWL568.lib(hal_internal_vsync.o) - 0x00017f98 0x00017f98 0x00000084 Code RO 1130 i.hal_internal_vsync_set_tx_state CVWL568.lib(hal_internal_vsync.o) - 0x0001801c 0x0001801c 0x00000010 Code RO 1716 i.hal_intl_svs_deinit_tx CVWL568.lib(hal_internal_soft_sync.o) - 0x0001802c 0x0001802c 0x00000024 Code RO 1717 i.hal_intl_svs_handle CVWL568.lib(hal_internal_soft_sync.o) - 0x00018050 0x00018050 0x00000078 Code RO 1718 i.hal_intl_svs_init_rx CVWL568.lib(hal_internal_soft_sync.o) - 0x000180c8 0x000180c8 0x00000014 Code RO 1719 i.hal_intl_svs_init_tx CVWL568.lib(hal_internal_soft_sync.o) - 0x000180dc 0x000180dc 0x0000000c Code RO 1721 i.hal_intl_svs_set_sync_coef CVWL568.lib(hal_internal_soft_sync.o) - 0x000180e8 0x000180e8 0x00000048 Code RO 1722 i.hal_intl_svs_update_rxbr_clk CVWL568.lib(hal_internal_soft_sync.o) - 0x00018130 0x00018130 0x00000024 Code RO 837 i.hal_lcdc_config_ccm CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00018154 0x00018154 0x00000064 Code RO 838 i.hal_lcdc_config_remains CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x000181b8 0x000181b8 0x00000014 Code RO 839 i.hal_lcdc_config_rgb_to_pentile CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x000181cc 0x000181cc 0x00000164 Code RO 840 i.hal_lcdc_config_upscaler CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00018330 0x00018330 0x00000054 Code RO 841 i.hal_lcdc_init_cfg CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00018384 0x00018384 0x000001cc Code RO 842 i.hal_lcdc_init_clk CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00018550 0x00018550 0x00000040 Code RO 843 i.hal_lcdc_init_interrupt CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00018590 0x00018590 0x00000008 Code RO 1028 i.hal_system_enable_systick CVWL568.lib(hal_system.o) - 0x00018598 0x00018598 0x00000088 Code RO 1032 i.hal_system_init CVWL568.lib(hal_system.o) - 0x00018620 0x00018620 0x0000001c Code RO 1033 i.hal_system_init_console CVWL568.lib(hal_system.o) - 0x0001863c 0x0001863c 0x00000008 Code RO 1036 i.hal_system_set_phy_calibration CVWL568.lib(hal_system.o) - 0x00018644 0x00018644 0x00000030 Code RO 844 i.hal_tx_frame_rate_adjust CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x00018674 0x00018674 0x0000008c Code RO 1082 i.hal_uart_init CVWL568.lib(hal_uart.o) - 0x00018700 0x00018700 0x00000010 Code RO 1085 i.hal_uart_transmit_blocking CVWL568.lib(hal_uart.o) - 0x00018710 0x00018710 0x00000110 Code RO 2216 i.handle_init CVWL568.lib(irq_redirect .o) - 0x00018820 0x00018820 0x0000006c Code RO 115 i.init_mipi_tx ap_demo.o - 0x0001888c 0x0001888c 0x000000a0 Code RO 116 i.init_panel ap_demo.o - 0x0001892c 0x0001892c 0x0000000a Code RO 3 i.main main.o - 0x00018936 0x00018936 0x00000002 PAD - 0x00018938 0x00018938 0x000000d4 Code RO 117 i.open_mipi_rx ap_demo.o - 0x00018a0c 0x00018a0c 0x0000009c Code RO 118 i.pps_update_handle ap_demo.o - 0x00018aa8 0x00018aa8 0x000003f4 Code RO 1134 i.rx_get_dcs_packet_data CVWL568.lib(hal_internal_vsync.o) - 0x00018e9c 0x00018e9c 0x0000016c Code RO 1135 i.rx_partial_update CVWL568.lib(hal_internal_vsync.o) - 0x00019008 0x00019008 0x0000008c Code RO 1136 i.rx_receive_packet CVWL568.lib(hal_internal_vsync.o) - 0x00019094 0x00019094 0x00000180 Code RO 1137 i.rx_receive_pps CVWL568.lib(hal_internal_vsync.o) - 0x00019214 0x00019214 0x000000cc Code RO 1138 i.rxbr_irq0_callback CVWL568.lib(hal_internal_vsync.o) - 0x000192e0 0x000192e0 0x00000244 Code RO 1139 i.rxbr_irq1_callback CVWL568.lib(hal_internal_vsync.o) - 0x00019524 0x00019524 0x000000c4 Code RO 1140 i.soft_gen_te CVWL568.lib(hal_internal_vsync.o) - 0x000195e8 0x000195e8 0x000000c0 Code RO 1141 i.soft_gen_te_double_buffer CVWL568.lib(hal_internal_vsync.o) - 0x000196a8 0x000196a8 0x00000048 Code RO 2733 i.sqrt m_ps.l(sqrt.o) - 0x000196f0 0x000196f0 0x000000ac Code RO 1723 i.svs_direct_mode_setting CVWL568.lib(hal_internal_soft_sync.o) - 0x0001979c 0x0001979c 0x0000001c Code RO 1724 i.svs_get_rel_intv CVWL568.lib(hal_internal_soft_sync.o) - 0x000197b8 0x000197b8 0x000000b0 Code RO 1725 i.svs_sync_handle CVWL568.lib(hal_internal_soft_sync.o) - 0x00019868 0x00019868 0x000000f4 Code RO 1726 i.svs_wait_start CVWL568.lib(hal_internal_soft_sync.o) - 0x0001995c 0x0001995c 0x000000d8 Code RO 1727 i.svs_waite_fr_stab CVWL568.lib(hal_internal_soft_sync.o) - 0x00019a34 0x00019a34 0x00000108 Code RO 1142 i.vidc_callback CVWL568.lib(hal_internal_vsync.o) - 0x00019b3c 0x00019b3c 0x000000d8 Code RO 1143 i.vpre_err_reset CVWL568.lib(hal_internal_vsync.o) - 0x00019c14 0x00019c14 0x000001cc Code RO 1144 i.vsync_set_te_mode CVWL568.lib(hal_internal_vsync.o) - 0x00019de0 0x00019de0 0x00001f74 Data RO 122 .constdata ap_demo.o - 0x0001bd54 0x0001bd54 0x000000d2 Data RO 919 .constdata CVWL568.lib(hal_gpio.o) - 0x0001be26 0x0001be26 0x00000002 PAD - 0x0001be28 0x0001be28 0x00000008 Data RO 1597 .constdata CVWL568.lib(drv_param_init.o) - 0x0001be30 0x0001be30 0x00000186 Data RO 2288 .constdata CVWL568.lib(drv_phy_common.o) - 0x0001bfb6 0x0001bfb6 0x00000002 PAD - 0x0001bfb8 0x0001bfb8 0x00000048 Data RO 744 .conststring CVWL568.lib(hal_dsi_rx_ctrl.o) - 0x0001c000 0x0001c000 0x00000043 Data RO 847 .conststring CVWL568.lib(hal_dsi_tx_ctrl.o) - 0x0001c043 0x0001c043 0x00000001 PAD - 0x0001c044 0x0001c044 0x00000178 Data RO 1146 .conststring CVWL568.lib(hal_internal_vsync.o) - 0x0001c1bc 0x0001c1bc 0x00000030 Data RO 3097 Region$$Table anon$$obj.o + 0x00012e68 0x00012e68 0x00000074 Code RO 107 i.ap_set_backlight_51 ap_demo.o + 0x00012edc 0x00012edc 0x00000044 Code RO 108 i.ap_set_display_off ap_demo.o + 0x00012f20 0x00012f20 0x00000038 Code RO 109 i.ap_set_display_on ap_demo.o + 0x00012f58 0x00012f58 0x00000080 Code RO 110 i.ap_set_enter_sleep_mode ap_demo.o + 0x00012fd8 0x00012fd8 0x00000070 Code RO 111 i.ap_set_exit_sleep_mode ap_demo.o + 0x00013048 0x00013048 0x00000030 Code RO 112 i.ap_set_hbm_53 ap_demo.o + 0x00013078 0x00013078 0x00000028 Code RO 113 i.ap_update_frame_rate ap_demo.o + 0x000130a0 0x000130a0 0x0000001c Code RO 2034 i.app_ADC_IRQn_Handler CVWL568.lib(drv_rxbr.o) + 0x000130bc 0x000130bc 0x00000024 Code RO 1451 i.app_AP_NRESET_IRQn_Handler CVWL568.lib(drv_gpio.o) + 0x000130e0 0x000130e0 0x0000001c Code RO 1452 i.app_EXTI_INT0_IRQn_Handler CVWL568.lib(drv_gpio.o) + 0x000130fc 0x000130fc 0x0000001c Code RO 1453 i.app_EXTI_INT1_IRQn_Handler CVWL568.lib(drv_gpio.o) + 0x00013118 0x00013118 0x0000001c Code RO 1454 i.app_EXTI_INT2_IRQn_Handler CVWL568.lib(drv_gpio.o) + 0x00013134 0x00013134 0x0000001c Code RO 1455 i.app_EXTI_INT3_IRQn_Handler CVWL568.lib(drv_gpio.o) + 0x00013150 0x00013150 0x0000001c Code RO 1456 i.app_EXTI_INT4_IRQn_Handler CVWL568.lib(drv_gpio.o) + 0x0001316c 0x0001316c 0x0000001c Code RO 1457 i.app_EXTI_INT5_IRQn_Handler CVWL568.lib(drv_gpio.o) + 0x00013188 0x00013188 0x0000001c Code RO 1458 i.app_EXTI_INT6_IRQn_Handler CVWL568.lib(drv_gpio.o) + 0x000131a4 0x000131a4 0x0000001c Code RO 1459 i.app_EXTI_INT7_IRQn_Handler CVWL568.lib(drv_gpio.o) + 0x000131c0 0x000131c0 0x00000048 Code RO 1198 i.app_HardFault_Handler CVWL568.lib(drv_common.o) + 0x00013208 0x00013208 0x00000018 Code RO 1562 i.app_I2C0_IRQn_Handler CVWL568.lib(drv_i2c_slave.o) + 0x00013220 0x00013220 0x00000010 Code RO 1528 i.app_I2C1_IRQn_Handler CVWL568.lib(drv_i2c_master.o) + 0x00013230 0x00013230 0x00000130 Code RO 1099 i.app_LCDC_IRQn_Handler CVWL568.lib(hal_internal_vsync.o) + 0x00013360 0x00013360 0x00000088 Code RO 1976 i.app_MEMC_IRQn_Handler CVWL568.lib(drv_memc.o) + 0x000133e8 0x000133e8 0x00000298 Code RO 1746 i.app_MIPI_RX_IRQn_Handler CVWL568.lib(drv_dsi_rx.o) + 0x00013680 0x00013680 0x000000a0 Code RO 1804 i.app_MIPI_TX_IRQn_Handler CVWL568.lib(drv_dsi_tx.o) + 0x00013720 0x00013720 0x00000048 Code RO 2488 i.app_PWMDET_IRQn_Handler CVWL568.lib(drv_pwm.o) + 0x00013768 0x00013768 0x00000030 Code RO 1652 i.app_SPIM_IRQn_Handler CVWL568.lib(drv_spi_master.o) + 0x00013798 0x00013798 0x00000200 Code RO 2335 i.app_SPIS_IRQn_Handler CVWL568.lib(hal_spi_slave.o) + 0x00013998 0x00013998 0x00000020 Code RO 2553 i.app_SWIRE_IRQn_Handler CVWL568.lib(drv_swire.o) + 0x000139b8 0x000139b8 0x00000018 Code RO 1199 i.app_SysTick_Handler CVWL568.lib(drv_common.o) + 0x000139d0 0x000139d0 0x0000000a Code RO 2572 i.app_TIMER0_IRQn_Handler CVWL568.lib(drv_timer.o) + 0x000139da 0x000139da 0x0000000a Code RO 2573 i.app_TIMER1_IRQn_Handler CVWL568.lib(drv_timer.o) + 0x000139e4 0x000139e4 0x0000000a Code RO 2574 i.app_TIMER2_IRQn_Handler CVWL568.lib(drv_timer.o) + 0x000139ee 0x000139ee 0x0000000a Code RO 2575 i.app_TIMER3_IRQn_Handler CVWL568.lib(drv_timer.o) + 0x000139f8 0x000139f8 0x00000008 Code RO 2635 i.app_UART_IRQn_Handler CVWL568.lib(drv_uart.o) + 0x00013a00 0x00013a00 0x0000001c Code RO 2105 i.app_VIDC_IRQn_Handler CVWL568.lib(drv_vidc.o) + 0x00013a1c 0x00013a1c 0x0000001c Code RO 2035 i.app_VPRE_IRQn_Handler CVWL568.lib(drv_rxbr.o) + 0x00013a38 0x00013a38 0x00000038 Code RO 2694 i.app_WDG_IRQn_Handler CVWL568.lib(drv_wdg.o) + 0x00013a70 0x00013a70 0x00000010 Code RO 1313 i.app_dma_irq_handler CVWL568.lib(drv_dma.o) + 0x00013a80 0x00013a80 0x00000030 Code RO 2377 i.app_fls_ctrl_Handler CVWL568.lib(norflash.o) + 0x00013ab0 0x00013ab0 0x00000024 Code RO 542 i.board_Init board.o + 0x00013ad4 0x00013ad4 0x0000058c Code RO 1100 i.calc_framebuffer_setting CVWL568.lib(hal_internal_vsync.o) + 0x00014060 0x00014060 0x000000c8 Code RO 2729 i.ceil m_ps.l(ceil.o) + 0x00014128 0x00014128 0x0000002c Code RO 1101 i.check_mipi_rx_tx_video_info CVWL568.lib(hal_internal_vsync.o) + 0x00014154 0x00014154 0x00000084 Code RO 1102 i.check_pkt_buf_rev CVWL568.lib(hal_internal_vsync.o) + 0x000141d8 0x000141d8 0x00000058 Code RO 2717 i.dcs_packet_fifo_alloc CVWL568.lib(dcs_packet_fifo.o) + 0x00014230 0x00014230 0x00000018 Code RO 2718 i.dcs_packet_fifo_init CVWL568.lib(dcs_packet_fifo.o) + 0x00014248 0x00014248 0x00000044 Code RO 2719 i.dcs_packet_free_fifo_header CVWL568.lib(dcs_packet_fifo.o) + 0x0001428c 0x0001428c 0x00000024 Code RO 2720 i.dcs_packet_get_fifo_header CVWL568.lib(dcs_packet_fifo.o) + 0x000142b0 0x000142b0 0x0000002c Code RO 1103 i.dcs_sw_filter CVWL568.lib(hal_internal_vsync.o) + 0x000142dc 0x000142dc 0x00000018 Code RO 1061 i.delayMs CVWL568.lib(tau_delay.o) + 0x000142f4 0x000142f4 0x00000022 Code RO 1062 i.delayUs CVWL568.lib(tau_delay.o) + 0x00014316 0x00014316 0x00000002 PAD + 0x00014318 0x00014318 0x00000038 Code RO 1684 i.drv_ap_rst_trig_edge_detect CVWL568.lib(drv_sys_cfg.o) + 0x00014350 0x00014350 0x0000000c Code RO 2305 i.drv_chip_info_get_info CVWL568.lib(drv_chip_info.o) + 0x0001435c 0x0001435c 0x00000040 Code RO 2306 i.drv_chip_info_init CVWL568.lib(drv_chip_info.o) + 0x0001439c 0x0001439c 0x000000b0 Code RO 2307 i.drv_chip_rx_info_check CVWL568.lib(drv_chip_info.o) + 0x0001444c 0x0001444c 0x00000014 Code RO 2308 i.drv_chip_rx_init_done CVWL568.lib(drv_chip_info.o) + 0x00014460 0x00014460 0x00000058 Code RO 1201 i.drv_common_enable_systick CVWL568.lib(drv_common.o) + 0x000144b8 0x000144b8 0x00000008 Code RO 1204 i.drv_common_system_init CVWL568.lib(drv_common.o) + 0x000144c0 0x000144c0 0x00000010 Code RO 1226 i.drv_crgu_config_reset_modules CVWL568.lib(drv_crgu.o) + 0x000144d0 0x000144d0 0x00000014 Code RO 1239 i.drv_crgu_set_ahb_pre_div CVWL568.lib(drv_crgu.o) + 0x000144e4 0x000144e4 0x00000014 Code RO 1240 i.drv_crgu_set_ahb_src CVWL568.lib(drv_crgu.o) + 0x000144f8 0x000144f8 0x00000020 Code RO 1243 i.drv_crgu_set_clock CVWL568.lib(drv_crgu.o) + 0x00014518 0x00014518 0x00000014 Code RO 1244 i.drv_crgu_set_dpi_mux_src CVWL568.lib(drv_crgu.o) + 0x0001452c 0x0001452c 0x00000018 Code RO 1245 i.drv_crgu_set_dpi_pre_div CVWL568.lib(drv_crgu.o) + 0x00014544 0x00014544 0x00000014 Code RO 1246 i.drv_crgu_set_dpi_pre_src CVWL568.lib(drv_crgu.o) + 0x00014558 0x00014558 0x00000014 Code RO 1247 i.drv_crgu_set_dsc_core_div CVWL568.lib(drv_crgu.o) + 0x0001456c 0x0001456c 0x00000014 Code RO 1248 i.drv_crgu_set_dsco_src CVWL568.lib(drv_crgu.o) + 0x00014580 0x00014580 0x00000014 Code RO 1249 i.drv_crgu_set_dsco_src_div CVWL568.lib(drv_crgu.o) + 0x00014594 0x00014594 0x00000014 Code RO 1250 i.drv_crgu_set_fb_div CVWL568.lib(drv_crgu.o) + 0x000145a8 0x000145a8 0x00000014 Code RO 1251 i.drv_crgu_set_fb_src CVWL568.lib(drv_crgu.o) + 0x000145bc 0x000145bc 0x00000014 Code RO 1254 i.drv_crgu_set_lcdc_div CVWL568.lib(drv_crgu.o) + 0x000145d0 0x000145d0 0x00000014 Code RO 1255 i.drv_crgu_set_lcdc_src CVWL568.lib(drv_crgu.o) + 0x000145e4 0x000145e4 0x00000014 Code RO 1256 i.drv_crgu_set_mipi_cfg_src CVWL568.lib(drv_crgu.o) + 0x000145f8 0x000145f8 0x00000018 Code RO 1257 i.drv_crgu_set_mipi_ref_src CVWL568.lib(drv_crgu.o) + 0x00014610 0x00014610 0x00000018 Code RO 1260 i.drv_crgu_set_reset CVWL568.lib(drv_crgu.o) + 0x00014628 0x00014628 0x00000014 Code RO 1261 i.drv_crgu_set_rxbr_div CVWL568.lib(drv_crgu.o) + 0x0001463c 0x0001463c 0x00000014 Code RO 1262 i.drv_crgu_set_rxbr_src CVWL568.lib(drv_crgu.o) + 0x00014650 0x00014650 0x00000014 Code RO 1264 i.drv_crgu_set_vidc_src CVWL568.lib(drv_crgu.o) + 0x00014664 0x00014664 0x00000018 Code RO 1317 i.drv_dma_clear_flag CVWL568.lib(drv_dma.o) + 0x0001467c 0x0001467c 0x0000000c Code RO 1325 i.drv_dma_get_channel_flag CVWL568.lib(drv_dma.o) + 0x00014688 0x00014688 0x00000090 Code RO 1328 i.drv_dma_irq_handler CVWL568.lib(drv_dma.o) + 0x00014718 0x00014718 0x00000036 Code RO 2318 i.drv_dsc_dec_convert_pps_rc_parameter CVWL568.lib(drv_dsc_dec.o) + 0x0001474e 0x0001474e 0x0000000c Code RO 2319 i.drv_dsc_dec_disable CVWL568.lib(drv_dsc_dec.o) + 0x0001475a 0x0001475a 0x00000002 PAD + 0x0001475c 0x0001475c 0x00000074 Code RO 2320 i.drv_dsc_dec_enable CVWL568.lib(drv_dsc_dec.o) + 0x000147d0 0x000147d0 0x0000000a Code RO 2321 i.drv_dsc_dec_get_nslc CVWL568.lib(drv_dsc_dec.o) + 0x000147da 0x000147da 0x00000028 Code RO 2323 i.drv_dsc_dec_set_u8_pps CVWL568.lib(drv_dsc_dec.o) + 0x00014802 0x00014802 0x00000002 PAD + 0x00014804 0x00014804 0x00000104 Code RO 1747 i.drv_dsi_rx_calc_ipi_tx_delay CVWL568.lib(drv_dsi_rx.o) + 0x00014908 0x00014908 0x00000040 Code RO 1748 i.drv_dsi_rx_enable_irq CVWL568.lib(drv_dsi_rx.o) + 0x00014948 0x00014948 0x0000000e Code RO 1749 i.drv_dsi_rx_get_bta_status CVWL568.lib(drv_dsi_rx.o) + 0x00014956 0x00014956 0x00000002 PAD + 0x00014958 0x00014958 0x00000050 Code RO 1750 i.drv_dsi_rx_get_color_bpp CVWL568.lib(drv_dsi_rx.o) + 0x000149a8 0x000149a8 0x0000001c Code RO 1751 i.drv_dsi_rx_get_color_pcc CVWL568.lib(drv_dsi_rx.o) + 0x000149c4 0x000149c4 0x00000008 Code RO 1752 i.drv_dsi_rx_get_compression_en CVWL568.lib(drv_dsi_rx.o) + 0x000149cc 0x000149cc 0x00000006 Code RO 1753 i.drv_dsi_rx_get_max_ret_size CVWL568.lib(drv_dsi_rx.o) + 0x000149d2 0x000149d2 0x0000000e Code RO 1757 i.drv_dsi_rx_power_up CVWL568.lib(drv_dsi_rx.o) + 0x000149e0 0x000149e0 0x00000020 Code RO 1758 i.drv_dsi_rx_set_ctrl_cfg CVWL568.lib(drv_dsi_rx.o) + 0x00014a00 0x00014a00 0x00000010 Code RO 1759 i.drv_dsi_rx_set_ddi_cfg CVWL568.lib(drv_dsi_rx.o) + 0x00014a10 0x00014a10 0x00000004 Code RO 1761 i.drv_dsi_rx_set_inten CVWL568.lib(drv_dsi_rx.o) + 0x00014a14 0x00014a14 0x00000010 Code RO 1762 i.drv_dsi_rx_set_ipi_cfg CVWL568.lib(drv_dsi_rx.o) + 0x00014a24 0x00014a24 0x00000046 Code RO 1764 i.drv_dsi_rx_set_lane_swap CVWL568.lib(drv_dsi_rx.o) + 0x00014a6a 0x00014a6a 0x00000026 Code RO 1765 i.drv_dsi_rx_set_resp_cnt CVWL568.lib(drv_dsi_rx.o) + 0x00014a90 0x00014a90 0x00000104 Code RO 1766 i.drv_dsi_rx_set_up_phy CVWL568.lib(drv_dsi_rx.o) + 0x00014b94 0x00014b94 0x0000000e Code RO 1767 i.drv_dsi_rx_shut_down CVWL568.lib(drv_dsi_rx.o) + 0x00014ba2 0x00014ba2 0x00000014 Code RO 1806 i.drv_dsi_tx_command_header CVWL568.lib(drv_dsi_tx.o) + 0x00014bb6 0x00014bb6 0x0000006c Code RO 1807 i.drv_dsi_tx_command_mode_cfg CVWL568.lib(drv_dsi_tx.o) + 0x00014c22 0x00014c22 0x00000004 Code RO 1808 i.drv_dsi_tx_command_put_payload CVWL568.lib(drv_dsi_tx.o) + 0x00014c26 0x00014c26 0x00000018 Code RO 1809 i.drv_dsi_tx_config_eotp CVWL568.lib(drv_dsi_tx.o) + 0x00014c3e 0x00014c3e 0x00000008 Code RO 1810 i.drv_dsi_tx_config_int CVWL568.lib(drv_dsi_tx.o) + 0x00014c46 0x00014c46 0x00000008 Code RO 1811 i.drv_dsi_tx_dpi_lpcmd_time CVWL568.lib(drv_dsi_tx.o) + 0x00014c4e 0x00014c4e 0x0000000a Code RO 1812 i.drv_dsi_tx_dpi_mode CVWL568.lib(drv_dsi_tx.o) + 0x00014c58 0x00014c58 0x00000024 Code RO 1813 i.drv_dsi_tx_dpi_polarity CVWL568.lib(drv_dsi_tx.o) + 0x00014c7c 0x00014c7c 0x00000004 Code RO 1814 i.drv_dsi_tx_edpi_cmd_size CVWL568.lib(drv_dsi_tx.o) + 0x00014c80 0x00014c80 0x00000004 Code RO 1816 i.drv_dsi_tx_get_cmd_status CVWL568.lib(drv_dsi_tx.o) + 0x00014c84 0x00014c84 0x00000004 Code RO 1818 i.drv_dsi_tx_mode CVWL568.lib(drv_dsi_tx.o) + 0x00014c88 0x00014c88 0x00000018 Code RO 1819 i.drv_dsi_tx_phy_clock_lane_auto_lp CVWL568.lib(drv_dsi_tx.o) + 0x00014ca0 0x00014ca0 0x0000001a Code RO 1820 i.drv_dsi_tx_phy_clock_lane_req_hs CVWL568.lib(drv_dsi_tx.o) + 0x00014cba 0x00014cba 0x0000000c Code RO 1822 i.drv_dsi_tx_phy_lane_mode CVWL568.lib(drv_dsi_tx.o) + 0x00014cc6 0x00014cc6 0x00000064 Code RO 1826 i.drv_dsi_tx_phy_status_ready CVWL568.lib(drv_dsi_tx.o) + 0x00014d2a 0x00014d2a 0x0000003e Code RO 1827 i.drv_dsi_tx_phy_status_stopstate CVWL568.lib(drv_dsi_tx.o) + 0x00014d68 0x00014d68 0x00000134 Code RO 1829 i.drv_dsi_tx_phy_test_setup CVWL568.lib(drv_dsi_tx.o) + 0x00014e9c 0x00014e9c 0x0000001e Code RO 1830 i.drv_dsi_tx_phy_time_cfg CVWL568.lib(drv_dsi_tx.o) + 0x00014eba 0x00014eba 0x00000008 Code RO 1834 i.drv_dsi_tx_powerup CVWL568.lib(drv_dsi_tx.o) + 0x00014ec2 0x00014ec2 0x0000001c Code RO 1835 i.drv_dsi_tx_response_mode CVWL568.lib(drv_dsi_tx.o) + 0x00014ede 0x00014ede 0x00000018 Code RO 1838 i.drv_dsi_tx_set_bta_ack CVWL568.lib(drv_dsi_tx.o) + 0x00014ef6 0x00014ef6 0x0000000c Code RO 1839 i.drv_dsi_tx_set_esc_div CVWL568.lib(drv_dsi_tx.o) + 0x00014f02 0x00014f02 0x00000002 PAD + 0x00014f04 0x00014f04 0x00000040 Code RO 1840 i.drv_dsi_tx_set_int CVWL568.lib(drv_dsi_tx.o) + 0x00014f44 0x00014f44 0x00000010 Code RO 1841 i.drv_dsi_tx_set_time_out_div CVWL568.lib(drv_dsi_tx.o) + 0x00014f54 0x00014f54 0x00000008 Code RO 1842 i.drv_dsi_tx_set_video_chunk CVWL568.lib(drv_dsi_tx.o) + 0x00014f5c 0x00014f5c 0x00000022 Code RO 1843 i.drv_dsi_tx_set_video_timing CVWL568.lib(drv_dsi_tx.o) + 0x00014f7e 0x00014f7e 0x00000008 Code RO 1845 i.drv_dsi_tx_shutdown CVWL568.lib(drv_dsi_tx.o) + 0x00014f86 0x00014f86 0x00000026 Code RO 1846 i.drv_dsi_tx_timeout_cfg CVWL568.lib(drv_dsi_tx.o) + 0x00014fac 0x00014fac 0x000000aa Code RO 1849 i.drv_dsi_tx_video_mode_cfg CVWL568.lib(drv_dsi_tx.o) + 0x00015056 0x00015056 0x00000016 Code RO 1850 i.drv_dsi_tx_video_mode_disable_hact_cmd CVWL568.lib(drv_dsi_tx.o) + 0x0001506c 0x0001506c 0x00000018 Code RO 1851 i.drv_dsi_tx_video_mode_set_lp_cmd CVWL568.lib(drv_dsi_tx.o) + 0x00015084 0x00015084 0x0000002e Code RO 2256 i.drv_efuse_enter_inactive CVWL568.lib(drv_efuse.o) + 0x000150b2 0x000150b2 0x0000000c Code RO 2259 i.drv_efuse_int_enable CVWL568.lib(drv_efuse.o) + 0x000150be 0x000150be 0x00000032 Code RO 2260 i.drv_efuse_read CVWL568.lib(drv_efuse.o) + 0x000150f0 0x000150f0 0x00000018 Code RO 2261 i.drv_efuse_read_req CVWL568.lib(drv_efuse.o) + 0x00015108 0x00015108 0x00000020 Code RO 1466 i.drv_gpio_set_ioe CVWL568.lib(drv_gpio.o) + 0x00015128 0x00015128 0x00000010 Code RO 1467 i.drv_gpio_set_mode0 CVWL568.lib(drv_gpio.o) + 0x00015138 0x00015138 0x00000010 Code RO 1468 i.drv_gpio_set_mode1 CVWL568.lib(drv_gpio.o) + 0x00015148 0x00015148 0x00000010 Code RO 1469 i.drv_gpio_set_mode2 CVWL568.lib(drv_gpio.o) + 0x00015158 0x00015158 0x00000010 Code RO 1470 i.drv_gpio_set_mode3 CVWL568.lib(drv_gpio.o) + 0x00015168 0x00015168 0x00000020 Code RO 902 i.drv_gpio_set_output_data CVWL568.lib(hal_gpio.o) + 0x00015188 0x00015188 0x00000018 Code RO 1918 i.drv_lcdc_config_bypass CVWL568.lib(drv_lcdc.o) + 0x000151a0 0x000151a0 0x00000030 Code RO 1919 i.drv_lcdc_config_ccm CVWL568.lib(drv_lcdc.o) + 0x000151d0 0x000151d0 0x00000016 Code RO 1920 i.drv_lcdc_config_disp_mode CVWL568.lib(drv_lcdc.o) + 0x000151e6 0x000151e6 0x00000024 Code RO 1921 i.drv_lcdc_config_dpi_polarity CVWL568.lib(drv_lcdc.o) + 0x0001520a 0x0001520a 0x00000026 Code RO 1922 i.drv_lcdc_config_dpi_timing CVWL568.lib(drv_lcdc.o) + 0x00015230 0x00015230 0x00000016 Code RO 1923 i.drv_lcdc_config_edpi_mode CVWL568.lib(drv_lcdc.o) + 0x00015246 0x00015246 0x00000016 Code RO 1924 i.drv_lcdc_config_endianness CVWL568.lib(drv_lcdc.o) + 0x0001525c 0x0001525c 0x0000000c Code RO 1925 i.drv_lcdc_config_input_size CVWL568.lib(drv_lcdc.o) + 0x00015268 0x00015268 0x0000001e Code RO 1926 i.drv_lcdc_config_int CVWL568.lib(drv_lcdc.o) + 0x00015286 0x00015286 0x00000022 Code RO 1927 i.drv_lcdc_config_int_single CVWL568.lib(drv_lcdc.o) + 0x000152a8 0x000152a8 0x00000022 Code RO 1928 i.drv_lcdc_config_overwrite CVWL568.lib(drv_lcdc.o) + 0x000152ca 0x000152ca 0x0000000c Code RO 1929 i.drv_lcdc_config_overwrite_rgb CVWL568.lib(drv_lcdc.o) + 0x000152d6 0x000152d6 0x0000001a Code RO 1930 i.drv_lcdc_config_partial_display_area CVWL568.lib(drv_lcdc.o) + 0x000152f0 0x000152f0 0x00000022 Code RO 1931 i.drv_lcdc_config_partial_display_enable CVWL568.lib(drv_lcdc.o) + 0x00015312 0x00015312 0x0000001a Code RO 1933 i.drv_lcdc_config_scale_up_coef CVWL568.lib(drv_lcdc.o) + 0x0001532c 0x0001532c 0x0000000c Code RO 1934 i.drv_lcdc_config_scale_up_step CVWL568.lib(drv_lcdc.o) + 0x00015338 0x00015338 0x0000004c Code RO 1935 i.drv_lcdc_config_src_parameter CVWL568.lib(drv_lcdc.o) + 0x00015384 0x00015384 0x00000006 Code RO 1936 i.drv_lcdc_config_thresh CVWL568.lib(drv_lcdc.o) + 0x0001538a 0x0001538a 0x00000012 Code RO 1937 i.drv_lcdc_ctrl_flow CVWL568.lib(drv_lcdc.o) + 0x0001539c 0x0001539c 0x00000020 Code RO 1939 i.drv_lcdc_enable_shadow_reg CVWL568.lib(drv_lcdc.o) + 0x000153bc 0x000153bc 0x00000040 Code RO 1940 i.drv_lcdc_set_int CVWL568.lib(drv_lcdc.o) + 0x000153fc 0x000153fc 0x00000018 Code RO 1941 i.drv_lcdc_set_prefetch CVWL568.lib(drv_lcdc.o) + 0x00015414 0x00015414 0x00000014 Code RO 1942 i.drv_lcdc_set_video_hw_mode CVWL568.lib(drv_lcdc.o) + 0x00015428 0x00015428 0x00000020 Code RO 1943 i.drv_lcdc_start CVWL568.lib(drv_lcdc.o) + 0x00015448 0x00015448 0x0000000c Code RO 1977 i.drv_memc_clear_status CVWL568.lib(drv_memc.o) + 0x00015454 0x00015454 0x00000040 Code RO 1978 i.drv_memc_enable_irq CVWL568.lib(drv_memc.o) + 0x00015494 0x00015494 0x0000000c Code RO 1979 i.drv_memc_gen_a_tear_signal CVWL568.lib(drv_memc.o) + 0x000154a0 0x000154a0 0x00000012 Code RO 1980 i.drv_memc_get_status CVWL568.lib(drv_memc.o) + 0x000154b2 0x000154b2 0x00000010 Code RO 1981 i.drv_memc_rate_transfer_sel CVWL568.lib(drv_memc.o) + 0x000154c2 0x000154c2 0x0000000e Code RO 1982 i.drv_memc_sel_vsync CVWL568.lib(drv_memc.o) + 0x000154d0 0x000154d0 0x00000014 Code RO 1983 i.drv_memc_set_active_height CVWL568.lib(drv_memc.o) + 0x000154e4 0x000154e4 0x0000000c Code RO 1984 i.drv_memc_set_data_mode CVWL568.lib(drv_memc.o) + 0x000154f0 0x000154f0 0x00000010 Code RO 1987 i.drv_memc_set_double_buffer CVWL568.lib(drv_memc.o) + 0x00015500 0x00015500 0x00000012 Code RO 1988 i.drv_memc_set_double_buffer_reverse CVWL568.lib(drv_memc.o) + 0x00015512 0x00015512 0x00000010 Code RO 1990 i.drv_memc_set_fs_en_conditions CVWL568.lib(drv_memc.o) + 0x00015522 0x00015522 0x00000014 Code RO 1991 i.drv_memc_set_inten CVWL568.lib(drv_memc.o) + 0x00015536 0x00015536 0x00000002 PAD + 0x00015538 0x00015538 0x00000018 Code RO 1992 i.drv_memc_set_lcdc_st_conditions CVWL568.lib(drv_memc.o) + 0x00015550 0x00015550 0x0000001a Code RO 1993 i.drv_memc_set_ltpo_mode CVWL568.lib(drv_memc.o) + 0x0001556a 0x0001556a 0x0000000e Code RO 1997 i.drv_memc_set_tear_mode CVWL568.lib(drv_memc.o) + 0x00015578 0x00015578 0x00000028 Code RO 1998 i.drv_memc_set_tear_waveform CVWL568.lib(drv_memc.o) + 0x000155a0 0x000155a0 0x0000000e Code RO 2000 i.drv_memc_set_vidc_sync_cnt CVWL568.lib(drv_memc.o) + 0x000155ae 0x000155ae 0x00000002 PAD + 0x000155b0 0x000155b0 0x00000008 Code RO 1589 i.drv_param_init_get_ccm CVWL568.lib(drv_param_init.o) + 0x000155b8 0x000155b8 0x00000014 Code RO 1590 i.drv_param_init_get_scld_filter_h CVWL568.lib(drv_param_init.o) + 0x000155cc 0x000155cc 0x00000014 Code RO 1591 i.drv_param_init_get_scld_filter_v CVWL568.lib(drv_param_init.o) + 0x000155e0 0x000155e0 0x00000008 Code RO 1592 i.drv_param_init_get_sclu_filter CVWL568.lib(drv_param_init.o) + 0x000155e8 0x000155e8 0x00000014 Code RO 1593 i.drv_param_init_set_ccm CVWL568.lib(drv_param_init.o) + 0x000155fc 0x000155fc 0x00000064 Code RO 1594 i.drv_param_init_set_scld_filter CVWL568.lib(drv_param_init.o) + 0x00015660 0x00015660 0x00000024 Code RO 1596 i.drv_param_p2r_filter_init CVWL568.lib(drv_param_init.o) + 0x00015684 0x00015684 0x00000010 Code RO 2277 i.drv_phy_enable_calibration CVWL568.lib(drv_phy_common.o) + 0x00015694 0x00015694 0x0000003c Code RO 2278 i.drv_phy_get_calibration CVWL568.lib(drv_phy_common.o) + 0x000156d0 0x000156d0 0x00000060 Code RO 2279 i.drv_phy_get_pll_para CVWL568.lib(drv_phy_common.o) + 0x00015730 0x00015730 0x00000054 Code RO 2280 i.drv_phy_get_rate_para CVWL568.lib(drv_phy_common.o) + 0x00015784 0x00015784 0x00000010 Code RO 2281 i.drv_phy_test_clear CVWL568.lib(drv_phy_common.o) + 0x00015794 0x00015794 0x00000018 Code RO 2282 i.drv_phy_test_lock CVWL568.lib(drv_phy_common.o) + 0x000157ac 0x000157ac 0x00000020 Code RO 2284 i.drv_phy_test_write_1_byte CVWL568.lib(drv_phy_common.o) + 0x000157cc 0x000157cc 0x00000026 Code RO 2285 i.drv_phy_test_write_2_byte CVWL568.lib(drv_phy_common.o) + 0x000157f2 0x000157f2 0x0000001e Code RO 2286 i.drv_phy_test_write_code CVWL568.lib(drv_phy_common.o) + 0x00015810 0x00015810 0x00000020 Code RO 2287 i.drv_phy_test_write_data CVWL568.lib(drv_phy_common.o) + 0x00015830 0x00015830 0x00000018 Code RO 1614 i.drv_pwr_set_pvd_mode CVWL568.lib(drv_pwr.o) + 0x00015848 0x00015848 0x00000038 Code RO 1615 i.drv_pwr_set_system_clk_src CVWL568.lib(drv_pwr.o) + 0x00015880 0x00015880 0x0000000c Code RO 1768 i.drv_rx_phy_test_clear CVWL568.lib(drv_dsi_rx.o) + 0x0001588c 0x0001588c 0x00000010 Code RO 1769 i.drv_rx_phy_test_lock CVWL568.lib(drv_dsi_rx.o) + 0x0001589c 0x0001589c 0x00000014 Code RO 1771 i.drv_rx_phy_test_write_1_byte CVWL568.lib(drv_dsi_rx.o) + 0x000158b0 0x000158b0 0x00000016 Code RO 1772 i.drv_rx_phy_test_write_2_byte CVWL568.lib(drv_dsi_rx.o) + 0x000158c6 0x000158c6 0x0000000a Code RO 2036 i.drv_rxbr_clear_pkt_buffer CVWL568.lib(drv_rxbr.o) + 0x000158d0 0x000158d0 0x00000004 Code RO 2037 i.drv_rxbr_clear_status0 CVWL568.lib(drv_rxbr.o) + 0x000158d4 0x000158d4 0x0000005a Code RO 2039 i.drv_rxbr_enable_irq CVWL568.lib(drv_rxbr.o) + 0x0001592e 0x0001592e 0x00000002 PAD + 0x00015930 0x00015930 0x00000014 Code RO 2040 i.drv_rxbr_frame_drop_cfg CVWL568.lib(drv_rxbr.o) + 0x00015944 0x00015944 0x00000064 Code RO 2041 i.drv_rxbr_get_clk CVWL568.lib(drv_rxbr.o) + 0x000159a8 0x000159a8 0x00000004 Code RO 2042 i.drv_rxbr_get_col_addr CVWL568.lib(drv_rxbr.o) + 0x000159ac 0x000159ac 0x00000012 Code RO 1104 i.drv_rxbr_get_int_source CVWL568.lib(hal_internal_vsync.o) + 0x000159be 0x000159be 0x00000004 Code RO 2045 i.drv_rxbr_get_page_addr CVWL568.lib(drv_rxbr.o) + 0x000159c2 0x000159c2 0x0000000c Code RO 2047 i.drv_rxbr_get_pkt_buf_error_status CVWL568.lib(drv_rxbr.o) + 0x000159ce 0x000159ce 0x00000012 Code RO 1105 i.drv_rxbr_get_status0 CVWL568.lib(hal_internal_vsync.o) + 0x000159e0 0x000159e0 0x00000016 Code RO 1106 i.drv_rxbr_get_status1 CVWL568.lib(hal_internal_vsync.o) + 0x000159f6 0x000159f6 0x0000000c Code RO 2048 i.drv_rxbr_hline_rcv0_cfg CVWL568.lib(drv_rxbr.o) + 0x00015a02 0x00015a02 0x0000000c Code RO 2049 i.drv_rxbr_hline_rcv1_cfg CVWL568.lib(drv_rxbr.o) + 0x00015a0e 0x00015a0e 0x00000008 Code RO 2050 i.drv_rxbr_hline_rcv_cfg CVWL568.lib(drv_rxbr.o) + 0x00015a16 0x00015a16 0x00000002 PAD + 0x00015a18 0x00015a18 0x0000000c Code RO 2051 i.drv_rxbr_register_irq0_callback CVWL568.lib(drv_rxbr.o) + 0x00015a24 0x00015a24 0x0000000c Code RO 2052 i.drv_rxbr_register_irq1_callback CVWL568.lib(drv_rxbr.o) + 0x00015a30 0x00015a30 0x00000014 Code RO 2053 i.drv_rxbr_set_ack_pkt_header CVWL568.lib(drv_rxbr.o) + 0x00015a44 0x00015a44 0x00000014 Code RO 2056 i.drv_rxbr_set_color_format CVWL568.lib(drv_rxbr.o) + 0x00015a58 0x00015a58 0x00000012 Code RO 2058 i.drv_rxbr_set_filter_regs CVWL568.lib(drv_rxbr.o) + 0x00015a6a 0x00015a6a 0x00000014 Code RO 2059 i.drv_rxbr_set_inten CVWL568.lib(drv_rxbr.o) + 0x00015a7e 0x00015a7e 0x00000010 Code RO 2060 i.drv_rxbr_set_ltpo_drop_th CVWL568.lib(drv_rxbr.o) + 0x00015a8e 0x00015a8e 0x00000026 Code RO 2062 i.drv_rxbr_set_usr_cfg CVWL568.lib(drv_rxbr.o) + 0x00015ab4 0x00015ab4 0x00000008 Code RO 2063 i.drv_rxbr_set_usr_col CVWL568.lib(drv_rxbr.o) + 0x00015abc 0x00015abc 0x00000008 Code RO 2064 i.drv_rxbr_set_usr_row CVWL568.lib(drv_rxbr.o) + 0x00015ac4 0x00015ac4 0x00000054 Code RO 2557 i.drv_swire_set_int CVWL568.lib(drv_swire.o) + 0x00015b18 0x00015b18 0x0000000c Code RO 1685 i.drv_sys_cfg_clear_all_int CVWL568.lib(drv_sys_cfg.o) + 0x00015b24 0x00015b24 0x00000028 Code RO 1686 i.drv_sys_cfg_clear_pending CVWL568.lib(drv_sys_cfg.o) + 0x00015b4c 0x00015b4c 0x00000018 Code RO 1689 i.drv_sys_cfg_sel_ap_rst_lvl_trig CVWL568.lib(drv_sys_cfg.o) + 0x00015b64 0x00015b64 0x00000024 Code RO 1696 i.drv_sys_cfg_set_int CVWL568.lib(drv_sys_cfg.o) + 0x00015b88 0x00015b88 0x0000001a Code RO 2576 i.drv_timer_clear_status_flags CVWL568.lib(drv_timer.o) + 0x00015ba2 0x00015ba2 0x00000020 Code RO 2577 i.drv_timer_enable CVWL568.lib(drv_timer.o) + 0x00015bc2 0x00015bc2 0x00000002 PAD + 0x00015bc4 0x00015bc4 0x00000010 Code RO 2578 i.drv_timer_get_instance CVWL568.lib(drv_timer.o) + 0x00015bd4 0x00015bd4 0x00000044 Code RO 2581 i.drv_timer_handle_interrupt CVWL568.lib(drv_timer.o) + 0x00015c18 0x00015c18 0x00000010 Code RO 2583 i.drv_timer_set_compare_val CVWL568.lib(drv_timer.o) + 0x00015c28 0x00015c28 0x00000054 Code RO 2584 i.drv_timer_set_int CVWL568.lib(drv_timer.o) + 0x00015c7c 0x00015c7c 0x0000000a Code RO 1852 i.drv_tx_phy_test_clear CVWL568.lib(drv_dsi_tx.o) + 0x00015c86 0x00015c86 0x0000001c Code RO 1853 i.drv_tx_phy_test_enter CVWL568.lib(drv_dsi_tx.o) + 0x00015ca2 0x00015ca2 0x0000001c Code RO 1854 i.drv_tx_phy_test_exit CVWL568.lib(drv_dsi_tx.o) + 0x00015cbe 0x00015cbe 0x00000012 Code RO 1856 i.drv_tx_phy_test_write_1_byte CVWL568.lib(drv_dsi_tx.o) + 0x00015cd0 0x00015cd0 0x00000014 Code RO 1857 i.drv_tx_phy_test_write_2_byte CVWL568.lib(drv_dsi_tx.o) + 0x00015ce4 0x00015ce4 0x00000010 Code RO 1858 i.drv_tx_phy_test_write_code CVWL568.lib(drv_dsi_tx.o) + 0x00015cf4 0x00015cf4 0x00000008 Code RO 2106 i.drv_vidc_clear_irq CVWL568.lib(drv_vidc.o) + 0x00015cfc 0x00015cfc 0x00000018 Code RO 2110 i.drv_vidc_enable CVWL568.lib(drv_vidc.o) + 0x00015d14 0x00015d14 0x00000040 Code RO 2111 i.drv_vidc_enable_irq CVWL568.lib(drv_vidc.o) + 0x00015d54 0x00015d54 0x00000012 Code RO 2113 i.drv_vidc_get_irq_status CVWL568.lib(drv_vidc.o) + 0x00015d66 0x00015d66 0x00000002 PAD + 0x00015d68 0x00015d68 0x00000028 Code RO 2117 i.drv_vidc_init_module_enable CVWL568.lib(drv_vidc.o) + 0x00015d90 0x00015d90 0x0000000c Code RO 2118 i.drv_vidc_register_callback CVWL568.lib(drv_vidc.o) + 0x00015d9c 0x00015d9c 0x00000006 Code RO 2119 i.drv_vidc_reset CVWL568.lib(drv_vidc.o) + 0x00015da2 0x00015da2 0x0000003c Code RO 2121 i.drv_vidc_set_dst_parameter CVWL568.lib(drv_vidc.o) + 0x00015dde 0x00015dde 0x00000014 Code RO 2125 i.drv_vidc_set_irqen CVWL568.lib(drv_vidc.o) + 0x00015df2 0x00015df2 0x00000010 Code RO 2126 i.drv_vidc_set_mirror CVWL568.lib(drv_vidc.o) + 0x00015e02 0x00015e02 0x00000008 Code RO 2129 i.drv_vidc_set_p2r_hcoef0 CVWL568.lib(drv_vidc.o) + 0x00015e0a 0x00015e0a 0x00000026 Code RO 2130 i.drv_vidc_set_p2r_hinitb CVWL568.lib(drv_vidc.o) + 0x00015e30 0x00015e30 0x00000026 Code RO 2131 i.drv_vidc_set_p2r_hinitr CVWL568.lib(drv_vidc.o) + 0x00015e56 0x00015e56 0x00000002 PAD + 0x00015e58 0x00015e58 0x00000018 Code RO 2132 i.drv_vidc_set_pentile_swap CVWL568.lib(drv_vidc.o) + 0x00015e70 0x00015e70 0x0000000a Code RO 2133 i.drv_vidc_set_pu_ctrl CVWL568.lib(drv_vidc.o) + 0x00015e7a 0x00015e7a 0x00000010 Code RO 2134 i.drv_vidc_set_rotation CVWL568.lib(drv_vidc.o) + 0x00015e8a 0x00015e8a 0x0000000a Code RO 2135 i.drv_vidc_set_scld_hcoef0 CVWL568.lib(drv_vidc.o) + 0x00015e94 0x00015e94 0x0000000a Code RO 2136 i.drv_vidc_set_scld_hcoef1 CVWL568.lib(drv_vidc.o) + 0x00015e9e 0x00015e9e 0x00000012 Code RO 2137 i.drv_vidc_set_scld_step CVWL568.lib(drv_vidc.o) + 0x00015eb0 0x00015eb0 0x0000000a Code RO 2138 i.drv_vidc_set_scld_vcoef0 CVWL568.lib(drv_vidc.o) + 0x00015eba 0x00015eba 0x0000000a Code RO 2139 i.drv_vidc_set_scld_vcoef1 CVWL568.lib(drv_vidc.o) + 0x00015ec4 0x00015ec4 0x00000016 Code RO 2140 i.drv_vidc_set_src_parameter CVWL568.lib(drv_vidc.o) + 0x00015eda 0x00015eda 0x00000002 PAD + 0x00015edc 0x00015edc 0x00000010 Code RO 2695 i.drv_wdg_clear_counter CVWL568.lib(drv_wdg.o) + 0x00015eec 0x00015eec 0x00000010 Code RO 2696 i.drv_wdg_clear_edge_flag CVWL568.lib(drv_wdg.o) + 0x00015efc 0x00015efc 0x00000010 Code RO 2699 i.drv_wdg_read_edge_flag CVWL568.lib(drv_wdg.o) + 0x00015f0c 0x00015f0c 0x00000040 Code RO 2702 i.drv_wdg_set_int CVWL568.lib(drv_wdg.o) + 0x00015f4c 0x00015f4c 0x0000000a Code RO 1372 i.fls_clr_interrupt_flag CVWL568.lib(drv_fls.o) + 0x00015f56 0x00015f56 0x00000014 Code RO 1071 i.fputc CVWL568.lib(tau_log.o) + 0x00015f6a 0x00015f6a 0x00000002 PAD + 0x00015f6c 0x00015f6c 0x00000050 Code RO 114 i.frame_start_cb ap_demo.o + 0x00015fbc 0x00015fbc 0x00000034 Code RO 701 i.hal_dsi_rx_ctrl_create_handle CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00015ff0 0x00015ff0 0x00000028 Code RO 705 i.hal_dsi_rx_ctrl_dsc_async_handler CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016018 0x00016018 0x00000028 Code RO 707 i.hal_dsi_rx_ctrl_gen_a_tear_signal CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016040 0x00016040 0x00000028 Code RO 709 i.hal_dsi_rx_ctrl_get_max_ret_size CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016068 0x00016068 0x00000098 Code RO 711 i.hal_dsi_rx_ctrl_init CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016100 0x00016100 0x000001a4 Code RO 712 i.hal_dsi_rx_ctrl_init_clk CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x000162a4 0x000162a4 0x000000d8 Code RO 713 i.hal_dsi_rx_ctrl_init_dsi_rx CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x0001637c 0x0001637c 0x00000160 Code RO 714 i.hal_dsi_rx_ctrl_init_memc CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x000164dc 0x000164dc 0x00000150 Code RO 715 i.hal_dsi_rx_ctrl_init_rxbr CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x0001662c 0x0001662c 0x0000022c Code RO 716 i.hal_dsi_rx_ctrl_init_vidc CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016858 0x00016858 0x0000003c Code RO 717 i.hal_dsi_rx_ctrl_pre_init_pps CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016894 0x00016894 0x00000050 Code RO 720 i.hal_dsi_rx_ctrl_restart CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x000168e4 0x000168e4 0x000000f0 Code RO 721 i.hal_dsi_rx_ctrl_send_ack_cmd CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x000169d4 0x000169d4 0x0000002c Code RO 723 i.hal_dsi_rx_ctrl_set_cus_esc_clk CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016a00 0x00016a00 0x0000006c Code RO 724 i.hal_dsi_rx_ctrl_set_cus_scld_filter CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016a6c 0x00016a6c 0x00000034 Code RO 725 i.hal_dsi_rx_ctrl_set_cus_sync_line CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016aa0 0x00016aa0 0x00000038 Code RO 729 i.hal_dsi_rx_ctrl_set_ipi_cfg CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016ad8 0x00016ad8 0x00000072 Code RO 734 i.hal_dsi_rx_ctrl_set_rxbr_clk CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016b4a 0x00016b4a 0x0000000e Code RO 737 i.hal_dsi_rx_ctrl_set_tear_mode_ex CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016b58 0x00016b58 0x0000003c Code RO 738 i.hal_dsi_rx_ctrl_start CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016b94 0x00016b94 0x00000020 Code RO 741 i.hal_dsi_rx_ctrl_toggle_resolution CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x00016bb4 0x00016bb4 0x00000190 Code RO 796 i.hal_dsi_tx_calc_video_chunks CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00016d44 0x00016d44 0x00000034 Code RO 797 i.hal_dsi_tx_config_params_for_lane_rate CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00016d78 0x00016d78 0x00000428 Code RO 798 i.hal_dsi_tx_count_lane_rate CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x000171a0 0x000171a0 0x0000002c Code RO 801 i.hal_dsi_tx_ctrl_create_handle CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x000171cc 0x000171cc 0x0000004c Code RO 806 i.hal_dsi_tx_ctrl_enter_init_panel_mode CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017218 0x00017218 0x00000028 Code RO 808 i.hal_dsi_tx_ctrl_exit_init_panel_mode CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017240 0x00017240 0x000000a4 Code RO 810 i.hal_dsi_tx_ctrl_init CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x000172e4 0x000172e4 0x00000024 Code RO 811 i.hal_dsi_tx_ctrl_init_clk CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017308 0x00017308 0x0000000c Code RO 812 i.hal_dsi_tx_ctrl_panel_reset_pin CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017314 0x00017314 0x00000020 Code RO 815 i.hal_dsi_tx_ctrl_set_ccm CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017334 0x00017334 0x00000014 Code RO 821 i.hal_dsi_tx_ctrl_set_overwrite_rgb CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017348 0x00017348 0x00000010 Code RO 822 i.hal_dsi_tx_ctrl_set_partial_disp CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017358 0x00017358 0x00000024 Code RO 823 i.hal_dsi_tx_ctrl_set_partial_disp_area CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x0001737c 0x0001737c 0x000000a8 Code RO 826 i.hal_dsi_tx_ctrl_start CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017424 0x00017424 0x000000f0 Code RO 828 i.hal_dsi_tx_ctrl_write_array_cmd CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017514 0x00017514 0x000000cc Code RO 829 i.hal_dsi_tx_ctrl_write_cmd CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x000175e0 0x000175e0 0x00000044 Code RO 830 i.hal_dsi_tx_init_data_mode CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017624 0x00017624 0x00000030 Code RO 831 i.hal_dsi_tx_init_dpi_cfg CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017654 0x00017654 0x00000020 Code RO 832 i.hal_dsi_tx_init_interrupt CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017674 0x00017674 0x00000020 Code RO 833 i.hal_dsi_tx_init_phy_cfg CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017694 0x00017694 0x00000094 Code RO 834 i.hal_dsi_tx_init_remains CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017728 0x00017728 0x00000058 Code RO 835 i.hal_dsi_tx_init_video_mode CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00017780 0x00017780 0x00000044 Code RO 836 i.hal_dsi_tx_send_cmd CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x000177c4 0x000177c4 0x00000028 Code RO 909 i.hal_gpio_init_output CVWL568.lib(hal_gpio.o) + 0x000177ec 0x000177ec 0x00000060 Code RO 913 i.hal_gpio_set_mode CVWL568.lib(hal_gpio.o) + 0x0001784c 0x0001784c 0x00000008 Code RO 914 i.hal_gpio_set_output_data CVWL568.lib(hal_gpio.o) + 0x00017854 0x00017854 0x00000018 Code RO 1107 i.hal_internal_check_video_auto_sync CVWL568.lib(hal_internal_vsync.o) + 0x0001786c 0x0001786c 0x000000fc Code RO 1108 i.hal_internal_init_memc CVWL568.lib(hal_internal_vsync.o) + 0x00017968 0x00017968 0x0000002a Code RO 1109 i.hal_internal_rx_dcs_async_handler CVWL568.lib(hal_internal_vsync.o) + 0x00017992 0x00017992 0x00000002 PAD + 0x00017994 0x00017994 0x00000058 Code RO 1110 i.hal_internal_rx_dcs_polling CVWL568.lib(hal_internal_vsync.o) + 0x000179ec 0x000179ec 0x00000010 Code RO 1112 i.hal_internal_sync_get_fb_setting CVWL568.lib(hal_internal_vsync.o) + 0x000179fc 0x000179fc 0x00000010 Code RO 1113 i.hal_internal_sync_get_hight_performan_mode CVWL568.lib(hal_internal_vsync.o) + 0x00017a0c 0x00017a0c 0x0000022c Code RO 1114 i.hal_internal_sync_input_resolution_change CVWL568.lib(hal_internal_vsync.o) + 0x00017c38 0x00017c38 0x00000028 Code RO 1117 i.hal_internal_vsync_deinit CVWL568.lib(hal_internal_vsync.o) + 0x00017c60 0x00017c60 0x00000018 Code RO 1119 i.hal_internal_vsync_get_sync_line CVWL568.lib(hal_internal_vsync.o) + 0x00017c78 0x00017c78 0x0000000c Code RO 1120 i.hal_internal_vsync_get_tear_mode CVWL568.lib(hal_internal_vsync.o) + 0x00017c84 0x00017c84 0x0000000c Code RO 1121 i.hal_internal_vsync_get_tx_state CVWL568.lib(hal_internal_vsync.o) + 0x00017c90 0x00017c90 0x00000140 Code RO 1122 i.hal_internal_vsync_init_rx CVWL568.lib(hal_internal_vsync.o) + 0x00017dd0 0x00017dd0 0x000000b0 Code RO 1123 i.hal_internal_vsync_init_tx CVWL568.lib(hal_internal_vsync.o) + 0x00017e80 0x00017e80 0x00000090 Code RO 1125 i.hal_internal_vsync_set_auto_hw_filter CVWL568.lib(hal_internal_vsync.o) + 0x00017f10 0x00017f10 0x00000024 Code RO 1127 i.hal_internal_vsync_set_rx_state CVWL568.lib(hal_internal_vsync.o) + 0x00017f34 0x00017f34 0x00000044 Code RO 1128 i.hal_internal_vsync_set_sync_line CVWL568.lib(hal_internal_vsync.o) + 0x00017f78 0x00017f78 0x00000050 Code RO 1129 i.hal_internal_vsync_set_tear_mode CVWL568.lib(hal_internal_vsync.o) + 0x00017fc8 0x00017fc8 0x00000084 Code RO 1130 i.hal_internal_vsync_set_tx_state CVWL568.lib(hal_internal_vsync.o) + 0x0001804c 0x0001804c 0x00000010 Code RO 1716 i.hal_intl_svs_deinit_tx CVWL568.lib(hal_internal_soft_sync.o) + 0x0001805c 0x0001805c 0x00000024 Code RO 1717 i.hal_intl_svs_handle CVWL568.lib(hal_internal_soft_sync.o) + 0x00018080 0x00018080 0x00000078 Code RO 1718 i.hal_intl_svs_init_rx CVWL568.lib(hal_internal_soft_sync.o) + 0x000180f8 0x000180f8 0x00000014 Code RO 1719 i.hal_intl_svs_init_tx CVWL568.lib(hal_internal_soft_sync.o) + 0x0001810c 0x0001810c 0x0000000c Code RO 1721 i.hal_intl_svs_set_sync_coef CVWL568.lib(hal_internal_soft_sync.o) + 0x00018118 0x00018118 0x00000048 Code RO 1722 i.hal_intl_svs_update_rxbr_clk CVWL568.lib(hal_internal_soft_sync.o) + 0x00018160 0x00018160 0x00000024 Code RO 837 i.hal_lcdc_config_ccm CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00018184 0x00018184 0x00000064 Code RO 838 i.hal_lcdc_config_remains CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x000181e8 0x000181e8 0x00000014 Code RO 839 i.hal_lcdc_config_rgb_to_pentile CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x000181fc 0x000181fc 0x00000164 Code RO 840 i.hal_lcdc_config_upscaler CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00018360 0x00018360 0x00000054 Code RO 841 i.hal_lcdc_init_cfg CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x000183b4 0x000183b4 0x000001cc Code RO 842 i.hal_lcdc_init_clk CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x00018580 0x00018580 0x00000040 Code RO 843 i.hal_lcdc_init_interrupt CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x000185c0 0x000185c0 0x00000008 Code RO 1028 i.hal_system_enable_systick CVWL568.lib(hal_system.o) + 0x000185c8 0x000185c8 0x00000088 Code RO 1032 i.hal_system_init CVWL568.lib(hal_system.o) + 0x00018650 0x00018650 0x0000001c Code RO 1033 i.hal_system_init_console CVWL568.lib(hal_system.o) + 0x0001866c 0x0001866c 0x00000008 Code RO 1036 i.hal_system_set_phy_calibration CVWL568.lib(hal_system.o) + 0x00018674 0x00018674 0x00000030 Code RO 844 i.hal_tx_frame_rate_adjust CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x000186a4 0x000186a4 0x0000008c Code RO 1082 i.hal_uart_init CVWL568.lib(hal_uart.o) + 0x00018730 0x00018730 0x00000010 Code RO 1085 i.hal_uart_transmit_blocking CVWL568.lib(hal_uart.o) + 0x00018740 0x00018740 0x00000110 Code RO 2216 i.handle_init CVWL568.lib(irq_redirect .o) + 0x00018850 0x00018850 0x0000006c Code RO 115 i.init_mipi_tx ap_demo.o + 0x000188bc 0x000188bc 0x000000a0 Code RO 116 i.init_panel ap_demo.o + 0x0001895c 0x0001895c 0x0000000a Code RO 3 i.main main.o + 0x00018966 0x00018966 0x00000002 PAD + 0x00018968 0x00018968 0x000000d4 Code RO 117 i.open_mipi_rx ap_demo.o + 0x00018a3c 0x00018a3c 0x0000009c Code RO 118 i.pps_update_handle ap_demo.o + 0x00018ad8 0x00018ad8 0x000003f4 Code RO 1134 i.rx_get_dcs_packet_data CVWL568.lib(hal_internal_vsync.o) + 0x00018ecc 0x00018ecc 0x0000016c Code RO 1135 i.rx_partial_update CVWL568.lib(hal_internal_vsync.o) + 0x00019038 0x00019038 0x0000008c Code RO 1136 i.rx_receive_packet CVWL568.lib(hal_internal_vsync.o) + 0x000190c4 0x000190c4 0x00000180 Code RO 1137 i.rx_receive_pps CVWL568.lib(hal_internal_vsync.o) + 0x00019244 0x00019244 0x000000cc Code RO 1138 i.rxbr_irq0_callback CVWL568.lib(hal_internal_vsync.o) + 0x00019310 0x00019310 0x00000244 Code RO 1139 i.rxbr_irq1_callback CVWL568.lib(hal_internal_vsync.o) + 0x00019554 0x00019554 0x000000c4 Code RO 1140 i.soft_gen_te CVWL568.lib(hal_internal_vsync.o) + 0x00019618 0x00019618 0x000000c0 Code RO 1141 i.soft_gen_te_double_buffer CVWL568.lib(hal_internal_vsync.o) + 0x000196d8 0x000196d8 0x00000048 Code RO 2733 i.sqrt m_ps.l(sqrt.o) + 0x00019720 0x00019720 0x000000ac Code RO 1723 i.svs_direct_mode_setting CVWL568.lib(hal_internal_soft_sync.o) + 0x000197cc 0x000197cc 0x0000001c Code RO 1724 i.svs_get_rel_intv CVWL568.lib(hal_internal_soft_sync.o) + 0x000197e8 0x000197e8 0x000000b0 Code RO 1725 i.svs_sync_handle CVWL568.lib(hal_internal_soft_sync.o) + 0x00019898 0x00019898 0x000000f4 Code RO 1726 i.svs_wait_start CVWL568.lib(hal_internal_soft_sync.o) + 0x0001998c 0x0001998c 0x000000d8 Code RO 1727 i.svs_waite_fr_stab CVWL568.lib(hal_internal_soft_sync.o) + 0x00019a64 0x00019a64 0x00000108 Code RO 1142 i.vidc_callback CVWL568.lib(hal_internal_vsync.o) + 0x00019b6c 0x00019b6c 0x000000d8 Code RO 1143 i.vpre_err_reset CVWL568.lib(hal_internal_vsync.o) + 0x00019c44 0x00019c44 0x000001cc Code RO 1144 i.vsync_set_te_mode CVWL568.lib(hal_internal_vsync.o) + 0x00019e10 0x00019e10 0x00001f74 Data RO 122 .constdata ap_demo.o + 0x0001bd84 0x0001bd84 0x000000d2 Data RO 919 .constdata CVWL568.lib(hal_gpio.o) + 0x0001be56 0x0001be56 0x00000002 PAD + 0x0001be58 0x0001be58 0x00000008 Data RO 1597 .constdata CVWL568.lib(drv_param_init.o) + 0x0001be60 0x0001be60 0x00000186 Data RO 2288 .constdata CVWL568.lib(drv_phy_common.o) + 0x0001bfe6 0x0001bfe6 0x00000002 PAD + 0x0001bfe8 0x0001bfe8 0x00000048 Data RO 744 .conststring CVWL568.lib(hal_dsi_rx_ctrl.o) + 0x0001c030 0x0001c030 0x00000043 Data RO 847 .conststring CVWL568.lib(hal_dsi_tx_ctrl.o) + 0x0001c073 0x0001c073 0x00000001 PAD + 0x0001c074 0x0001c074 0x00000178 Data RO 1146 .conststring CVWL568.lib(hal_internal_vsync.o) + 0x0001c1ec 0x0001c1ec 0x00000030 Data RO 3097 Region$$Table anon$$obj.o - Execution Region RW_RAM1 (Exec base: 0x00070000, Load base: 0x0001c1ec, Size: 0x00000000, Max: 0x000000f0, ABSOLUTE) + Execution Region RW_RAM1 (Exec base: 0x00070000, Load base: 0x0001c21c, Size: 0x00000000, Max: 0x000000f0, ABSOLUTE) **** No section assigned to this execution region **** - Execution Region RW_RAM2 (Exec base: 0x00070100, Load base: 0x0001c1ec, Size: 0x000000c0, Max: 0x000000d0, ABSOLUTE) + Execution Region RW_RAM2 (Exec base: 0x00070100, Load base: 0x0001c21c, Size: 0x000000c0, Max: 0x000000d0, ABSOLUTE) Exec Addr Load Addr Size Type Attr Idx E Section Name Object 0x00070100 - 0x000000c0 Zero RW 2217 .ARM.__AT_0x00070100 CVWL568.lib(irq_redirect .o) - Execution Region RW_RAM3 (Exec base: 0x000701d0, Load base: 0x0001c1ec, Size: 0x00003650, Max: 0x00007e30, ABSOLUTE, COMPRESSED[0x0000052c]) + Execution Region RW_RAM3 (Exec base: 0x000701d0, Load base: 0x0001c21c, Size: 0x00003650, Max: 0x00007e30, ABSOLUTE, COMPRESSED[0x0000052c]) Exec Addr Load Addr Size Type Attr Idx E Section Name Object @@ -5018,14 +5020,14 @@ Image component sizes Code (inc. data) RO Data RW Data ZI Data Debug Object Name - 5894 652 8052 560 36 28315 ap_demo.o + 5942 656 8052 560 36 28371 ap_demo.o 32 4 0 59 0 4580 app_tp_st_touch.o 36 6 0 0 0 565 board.o 10 0 0 0 0 5715 main.o 120 18 192 0 4096 2124 startup_armcm0.o ---------------------------------------------------------------------- - 6096 680 8292 620 4132 41299 Object Totals + 6144 684 8292 620 4132 41355 Object Totals 0 0 48 0 0 0 (incl. Generated) 4 0 0 1 0 0 (incl. Padding) @@ -5146,15 +5148,15 @@ Image component sizes Code (inc. data) RO Data RW Data ZI Data Debug - 40200 5126 9444 2280 11816 67438 Grand Totals - 40200 5126 9444 1324 11816 67438 ELF Image Totals (compressed) - 40200 5126 9444 1324 0 0 ROM Totals + 40248 5130 9444 2280 11816 67494 Grand Totals + 40248 5130 9444 1324 11816 67494 ELF Image Totals (compressed) + 40248 5130 9444 1324 0 0 ROM Totals ============================================================================== - Total RO Size (Code + RO Data) 49644 ( 48.48kB) + Total RO Size (Code + RO Data) 49692 ( 48.53kB) Total RW Size (RW Data + ZI Data) 14096 ( 13.77kB) - Total ROM Size (Code + RO Data + RW Data) 50968 ( 49.77kB) + Total ROM Size (Code + RO Data + RW Data) 51016 ( 49.82kB) ============================================================================== diff --git a/project/Objects/WL568_S21_NT37701_V100_20230907.bin b/project/Objects/WL568_S21_NT37701_V100_20230907.bin index edf6db0..c3a4e94 100644 Binary files a/project/Objects/WL568_S21_NT37701_V100_20230907.bin and b/project/Objects/WL568_S21_NT37701_V100_20230907.bin differ diff --git a/project/RTE/_ISP568/RTE_Components.h b/project/RTE/_ISP568/RTE_Components.h new file mode 100644 index 0000000..364e30e --- /dev/null +++ b/project/RTE/_ISP568/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'ISP568' + * Target: 'ISP568' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/src/app/demo/ap_demo.c b/src/app/demo/ap_demo.c index 9cc058b..d482a18 100644 --- a/src/app/demo/ap_demo.c +++ b/src/app/demo/ap_demo.c @@ -1544,7 +1544,7 @@ static bool ap_set_backlight_51(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packe cmd_data[0] = dcs_packet->packet_param[0]; cmd_data[1] = dcs_packet->packet_param[1]; -/* + if( (s_in_aod_mode_flag)&&(cmd_data[0]==0x00 && cmd_data[1]==0x08) ) { hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, 0x00, 0x50); @@ -1553,7 +1553,7 @@ static bool ap_set_backlight_51(hal_dsi_rx_ctrl_handle_t *handler, hal_dcs_packe { hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, cmd_data[0], cmd_data[1]); } -*/ + TAU_LOGD("51:[%x]", (cmd_data[0]<<8)|cmd_data[1]); return true; }