diff --git a/src/code/core_main.c b/src/code/core_main.c
index 7f87b68..0fbc640 100644
--- a/src/code/core_main.c
+++ b/src/code/core_main.c
@@ -1,33 +1,196 @@
 #include "la_config.h"
+#include "hal_edp_rx.h"
 
-void blackligth_pwm_ctrl(void);
+RX_CB_Handle rx_cb_handle = {0};
 
-void main(void)
+/* SDP更新回调，用于获取second data packet */
+void ap_set_backlight(SDP_Info sdp_info)
 {
-//------------------------------w818 && ddic initial...
-		ini();
-		ini_dprx();//DPCD
-		gpio_init();
-		Sys_Matchine_Init();
-//------------------------------interrupt initial....
-		ir_init();	
-		aux_irq_set_irq13();		   //选择aux中断回调函数为aux_irq_handler，而不是isr_aux()
-		//aux_read_sink_set();		 //设置aux读时，可保存sink回复的数据
-//---------------------------------ulog initial....	
-		UartStdOutInit();									  //GPIO_ID22,GPIO_ID23串口初始化,波特率: 19200  
-		log_init(uart_output, LOG_LEVEL_INFO); // 初始化日志系统，使用UART输出，默认日志级别为INFO
-		sys_clk_get();
-		//sys_boot_getstatus();
-		log_set_level(LOG_LEVEL_DEBUG);
-		LOG_INFO("MCU Start Run On %s %s", __DATE__, __TIME__);
 
-		while(1)	
-		{ 
-			Sys_Power_Handler();
-			Oled_Diming_Process();
-		};
 }
 
+/* 休眠回调，当基板通过AUX往DPCD寄存器600H写02时触发 */
+void ap_set_display_off(void)
+{
+
+}
+
+/* 唤醒回调，当基板reset脚拉高触发 */
+void ap_set_display_on(void)
+{
+
+}
+
+RX_CB_Handle rx_cb_tabel = 
+{
+	{ap_set_backlight ,false},
+	{ap_set_display_off ,false},
+	{ap_set_display_on ,false},
+};
+
+const DPCD_Packet dpcd_packet_table[] =
+{
+	//dprx_DPCD_16PM
+	{0x0000 ,0x14},
+	{0x0001 ,0x0F},
+	{0x0002 ,0xC4},
+	{0x0003 ,0x00},
+	{0x0004 ,0x00},
+	{0x0005 ,0x00},
+	{0x0006 ,0x01},
+	{0x0007 ,0xC0},
+	{0x0008 ,0x02},
+	{0x0009 ,0x01},
+	{0x000A ,0x00},
+	{0x000B ,0x00},
+	{0x000C ,0x00},
+	{0x000D ,0x01},
+	{0x000E ,0x00},
+	{0x000F ,0x00},
+	{0x002E ,0x00},	//ALPM OFF
+	// {0x002E ,0x01},	//ALPM ON
+
+	{0x0400, 0x00},
+	{0x0401, 0x10},
+	{0x0402, 0xFA},
+
+	{0x0500, 0x00},
+	{0x0501, 0x00},
+	{0x0502, 0x00},
+
+	{0x0403, 0x00},
+	{0x0404, 0x00},
+	{0x0405, 0x00},
+	{0x0406, 0x00},
+	{0x0407, 0x00},
+	{0x0408, 0x00},
+
+	{0x0503, 0x00},
+	{0x0504, 0x00},
+	{0x0505, 0x00},
+	{0x0506, 0x00},
+	{0x0507, 0x00},
+	{0x0508, 0x00},
+
+	{0x0090, 0x00},
+	{0x00B0, 0x00},
+
+	{0xE000D, 0x00}, //
+
+	{0x0060 , 0x00},
+	{0x0061 , 0x00},
+	{0x0062 , 0x00},
+	{0x0063 , 0x00},
+	{0x0064 , 0x00},
+	{0x0065 , 0x00},
+	{0x0066 , 0x00},
+	{0x0067 , 0x00},
+	{0x0068 , 0x00},
+	{0x0069 , 0x00},
+	{0x006A , 0x00},
+	{0x006B , 0x00},
+	{0x006C , 0x00},
+	{0x006D , 0x00},
+	{0x006E , 0x00},
+	{0x006F , 0x00},
+
+	{0x0470, 0x31},
+	{0x0471, 0x03},
+	{0x0472, 0x01},
+
+	{0x0328, 0x00},
+
+	{0x0116, 0x01},
+
+	{0x3030, 0x00},
+
+	{0x0430, 0xA0},
+	{0x0431, 0xEE},
+	{0x0432, 0x61},
+	{0x0433, 0x42},
+
+	{0x0450, 0x03},
+	{0x0451, 0x81},
+	{0x0452, 0x00},
+	{0x0453, 0x00},
+	{0x0454, 0x00},
+	{0x0455, 0x00},
+	{0x0456, 0x00},
+	{0x0457, 0x00},
+	{0x0458, 0x00},
+	{0x0459, 0x00},
+	{0x045A, 0x00},
+	{0x045B, 0x00},
+	{0x045C, 0x66},
+	{0x045D, 0x66},
+	{0x045E, 0x06},
+	{0x045F, 0x00},
+
+	//{0x04F0, 0x00},  //原彩数据，不在此处回
+	//{0x04F1, 0x00},
+	//{0x04F2, 0x00},
+	//{0x04F3, 0x00},
+	//{0x04F4, 0x00},
+	//{0x04F5, 0x00},
+	//{0x04F6, 0x00},
+	//{0x04F7, 0x00},
+	//{0x04F8, 0x04},
+	//{0x04F9, 0x03},
+	//{0x04FA, 0x00},
+	//{0x04FB, 0x06},
+	//{0x04FC, 0x00},
+	//{0x04FD, 0x46},
+	//{0x04FE, 0x58},
+	//{0x04FF, 0x54},
+
+	{0x010A, 0x00},
+	{0x0101 ,0x82},
+	//{0x0102 ,0x21},
+	//{0x0103 ,0x00},
+	//{0x0104 ,0x00},
+	//{0x0105 ,0x00},
+
+	{0x0210, 0x00},
+	{0x0211, 0x80},
+	{0x0212, 0x00},
+	{0x0213, 0x80},
+	{0x0214, 0x00},
+	{0x0215, 0x80},
+	{0x0216, 0x00},
+	{0x0217, 0x00},
+
+	{0x0347, 0x00},
+	{0x0348, 0x00},
+	{0x0349, 0x00},
+	{0x034A, 0x00},
+	{0x034B, 0x00},
+	{0x034C, 0x00},
+	{0x034D, 0x00},
+	{0x034E, 0x00},
+
+
+	{0x0200, 0x77},
+	{0x0201, 0x77},
+	{0x0202 ,0x77},
+	{0x0203 ,0x07},
+	{0x0204 ,0x81},
+
+	//{0x0206 ,0x00},
+	//{0x0207 ,0x00},
+
+
+	//{0x0470 ,0x2C},
+	//{0x0471 ,0x03},
+	//{0x0472 ,0x01},
+
+	{0x0600 ,0x01},
+
+	//{0x3000 ,0x00},
+
+	{0x032F ,0x00},
+	{0x0330 ,0x00},
+};
+
 void blackligth_pwm_ctrl(void)
 {
 	//控制pwm产生
@@ -57,3 +220,30 @@ void blackligth_pwm_ctrl(void)
 	//wr_cfgreg(0xe002, 0xde);	
 	//wr_cfgreg(0xc100, 0x81);
 }
+
+void main(void)
+{
+//------------------------------w818 && ddic initial...
+		ini();
+		hal_edp_rx_dpcd_init(dpcd_packet_table, sizeof(dpcd_packet_table));
+		hal_edp_rx_cb_init(&rx_cb_tabel);
+		gpio_init();
+		Sys_Matchine_Init();
+//------------------------------interrupt initial....
+		ir_init();	
+		aux_irq_set_irq13();		   //选择aux中断回调函数为aux_irq_handler，而不是isr_aux()
+		//aux_read_sink_set();		 //设置aux读时，可保存sink回复的数据
+//---------------------------------ulog initial....	
+		UartStdOutInit();									  //GPIO_ID22,GPIO_ID23串口初始化,波特率: 19200  
+		log_init(uart_output, LOG_LEVEL_INFO); // 初始化日志系统，使用UART输出，默认日志级别为INFO
+		sys_clk_get();
+		//sys_boot_getstatus();
+		log_set_level(LOG_LEVEL_DEBUG);
+		LOG_INFO("MCU Start Run On %s %s", __DATE__, __TIME__);
+
+		while(1)	
+		{ 
+			Sys_Power_Handler();
+			Oled_Diming_Process();
+		};
+}
diff --git a/src/code/project_case/RM692H5_120HZ_DSC3_1/dprx.c b/src/code/project_case/RM692H5_120HZ_DSC3_1/dprx.c
index 2c13258..66664b1 100644
--- a/src/code/project_case/RM692H5_120HZ_DSC3_1/dprx.c
+++ b/src/code/project_case/RM692H5_120HZ_DSC3_1/dprx.c
@@ -2,169 +2,169 @@
 #include "define.h"
 
 void dprx_load_edp_bit_rate_cco(void);
-void ini_dprx()
-{
-	//dprx_DPCD_16PM
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0000 ,0x14);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0001 ,0x0F);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0002 ,0xC4);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0003 ,0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0004 ,0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0005 ,0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0006 ,0x01);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0007 ,0xC0);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0008 ,0x02);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0009 ,0x01);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x000A ,0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x000B ,0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x000C ,0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x000D ,0x01);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x000E ,0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x000F ,0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x002E ,0x00);	//ALPM OFF
-	// write_addr_UINT8(BASE_ADDR_DPCD + 0x002E ,0x01);	//ALPM ON
+// void ini_dprx()
+// {
+// 	//dprx_DPCD_16PM
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0000 ,0x14);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0001 ,0x0F);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0002 ,0xC4);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0003 ,0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0004 ,0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0005 ,0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0006 ,0x01);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0007 ,0xC0);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0008 ,0x02);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0009 ,0x01);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x000A ,0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x000B ,0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x000C ,0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x000D ,0x01);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x000E ,0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x000F ,0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x002E ,0x00);	//ALPM OFF
+// 	// write_addr_UINT8(BASE_ADDR_DPCD + 0x002E ,0x01);	//ALPM ON
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0400, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0401, 0x10);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0402, 0xFA);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0400, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0401, 0x10);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0402, 0xFA);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0500, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0501, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0502, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0500, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0501, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0502, 0x00);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0403, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0404, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0405, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0406, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0407, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0408, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0403, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0404, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0405, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0406, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0407, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0408, 0x00);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0503, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0504, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0505, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0506, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0507, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0508, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0503, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0504, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0505, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0506, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0507, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0508, 0x00);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0090, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x00B0, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0090, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x00B0, 0x00);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0xE000D, 0x00); //
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0xE000D, 0x00); //
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0060 , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0061 , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0062 , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0063 , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0064 , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0065 , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0066 , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0067 , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0068 , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0069 , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x006A , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x006B , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x006C , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x006D , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x006E , 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x006F , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0060 , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0061 , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0062 , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0063 , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0064 , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0065 , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0066 , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0067 , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0068 , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0069 , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x006A , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x006B , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x006C , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x006D , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x006E , 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x006F , 0x00);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0470, 0x31);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0471, 0x03);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0472, 0x01);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0470, 0x31);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0471, 0x03);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0472, 0x01);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0328, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0328, 0x00);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0116, 0x01);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0116, 0x01);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x3030, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x3030, 0x00);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0430, 0xA0);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0431, 0xEE);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0432, 0x61);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0433, 0x42);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0430, 0xA0);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0431, 0xEE);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0432, 0x61);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0433, 0x42);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0450, 0x03);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0451, 0x81);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0452, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0453, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0454, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0455, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0456, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0457, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0458, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0459, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x045A, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x045B, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x045C, 0x66);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x045D, 0x66);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x045E, 0x06);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x045F, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0450, 0x03);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0451, 0x81);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0452, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0453, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0454, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0455, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0456, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0457, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0458, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0459, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x045A, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x045B, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x045C, 0x66);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x045D, 0x66);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x045E, 0x06);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x045F, 0x00);
 
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F0, 0x00);  //原彩数据，不在此处回
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F1, 0x00);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F2, 0x00);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F3, 0x00);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F4, 0x00);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F5, 0x00);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F6, 0x00);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F7, 0x00);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F8, 0x04);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F9, 0x03);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FA, 0x00);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FB, 0x06);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FC, 0x00);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FD, 0x46);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FE, 0x58);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FF, 0x54);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F0, 0x00);  //原彩数据，不在此处回
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F1, 0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F2, 0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F3, 0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F4, 0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F5, 0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F6, 0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F7, 0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F8, 0x04);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F9, 0x03);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FA, 0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FB, 0x06);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FC, 0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FD, 0x46);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FE, 0x58);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FF, 0x54);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x010A, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0101 ,0x82);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0102 ,0x21);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0103 ,0x00);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0104 ,0x00);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0105 ,0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x010A, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0101 ,0x82);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0102 ,0x21);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0103 ,0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0104 ,0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0105 ,0x00);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0210, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0211, 0x80);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0212, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0213, 0x80);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0214, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0215, 0x80);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0216, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0217, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0210, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0211, 0x80);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0212, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0213, 0x80);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0214, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0215, 0x80);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0216, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0217, 0x00);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0347, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0348, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0349, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x034A, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x034B, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x034C, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x034D, 0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x034E, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0347, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0348, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0349, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x034A, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x034B, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x034C, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x034D, 0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x034E, 0x00);
 
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0200, 0x77);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0201, 0x77);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0202 ,0x77);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0203 ,0x07);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0204 ,0x81);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0200, 0x77);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0201, 0x77);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0202 ,0x77);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0203 ,0x07);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0204 ,0x81);
 
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0206 ,0x00);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0207 ,0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0206 ,0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0207 ,0x00);
 
 
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0470 ,0x2C);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0471 ,0x03);
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0472 ,0x01);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0470 ,0x2C);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0471 ,0x03);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x0472 ,0x01);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0600 ,0x01);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0600 ,0x01);
 
-	//write_addr_UINT8(BASE_ADDR_DPCD + 0x3000 ,0x00);
+// 	//write_addr_UINT8(BASE_ADDR_DPCD + 0x3000 ,0x00);
 
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x032F ,0x00);
-	write_addr_UINT8(BASE_ADDR_DPCD + 0x0330 ,0x00);
-	dprx_load_edp_bit_rate_cco();
-}
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x032F ,0x00);
+// 	write_addr_UINT8(BASE_ADDR_DPCD + 0x0330 ,0x00);
+// 	dprx_load_edp_bit_rate_cco();
+// }
 
 
 #define EDP_INPUT_3_51Gbps //EDP_INPUT_3_51Gbps
diff --git a/src/code/project_case/RM692H5_120HZ_DSC3_1/power_seq.c b/src/code/project_case/RM692H5_120HZ_DSC3_1/power_seq.c
index f42ba13..f3c3a86 100644
--- a/src/code/project_case/RM692H5_120HZ_DSC3_1/power_seq.c
+++ b/src/code/project_case/RM692H5_120HZ_DSC3_1/power_seq.c
@@ -1741,6 +1741,9 @@ void power_on_seq(void)
 	delay_ms(123);
 	SWIRE_EN();
 	delay_ms(46);
+	unsigned char data = 0;
+	hal_dsi_tx_ctrl_read_cmd(0x06,0,0x0A,1,&data);
+	LOG_DEBUG("r%d\n",data);
 	hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x29);
 	delay_ms(46);
 	hal_dsi_tx_ctrl_start();
@@ -1781,6 +1784,9 @@ void wake_up_seq(void)
 	delay_ms(123);
 	SWIRE_EN();
 	delay_ms(46);
+	// unsigned char data = 0;
+	// hal_dsi_tx_ctrl_read_cmd(0x06,0,0x0A,1,&data);
+	// LOG_DEBUG("r%d\n",data);
 	hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x29);
 	delay_ms(46);
 	hal_dsi_tx_ctrl_start();
diff --git a/src/driver/include/drv_mipi_tx.h b/src/driver/include/drv_mipi_tx.h
new file mode 100644
index 0000000..eea7881
--- /dev/null
+++ b/src/driver/include/drv_mipi_tx.h
@@ -0,0 +1,151 @@
+/*******************************************************************************
+* File:         drv_mipi_tx.h
+* Description:  mipi tx椹卞姩灞�
+* Version:      V1.0
+* Date:         2026-1-23
+* Author:       lyp
+ *******************************************************************************/
+
+#ifndef __DRV_MIPI_TX_H__
+#define __DRV_MIPI_TX_H__
+
+#include "typedef.h"
+#include "define.h"
+#include <stdarg.h>
+#include "la_config.h"
+
+#ifndef MIPI_TX_PORT0_BASE
+#define  MIPI_TX_PORT0_BASE               (0x80010000)
+#endif
+
+#define MIPI_TX_PORT0 ((MIPI_TX_PORT0_REG *)MIPI_TX_PORT0_BASE)
+
+typedef struct _MIPI_TX_PORT0_REG
+{
+    __O  uint32_t       write_data        ;
+    __IO uint8_t        tx_enable         ;
+    __IO uint8_t        tx_control_L      ;
+    __IO uint8_t        tx_control_H      ;
+    __I  uint8_t        tx_state          ;
+    __IO uint32_t       rd_lp_rx_data     ;
+    __IO uint32_t       rd_lp_rx_ecc      ;
+    __O  uint32_t       fifo_set          ;
+    __I  uint32_t       ISR               ;
+    __IO uint32_t       IMR               ;
+    __O  uint32_t       ICR               ;
+
+}MIPI_TX_PORT0_REG;
+
+/*!
+ * @brief MIPI鍙戦�佹ā寮�
+ * @note
+ */
+typedef enum _TX_MODE
+{
+    LP_MODE = 0,
+    HS_MODE,
+}TX_MODE;
+
+/**
+* @brief  鍚憁ipi妯″潡鍙戝嚭鍐欐暟鎹厤缃敵璇凤紝鍚庣画鎵嶈兘鍚憁ipi妯″潡閰嶇疆闇�瑕佸啓鐨勬暟鎹�
+* @param  none
+* @retval none
+*/
+static inline void drv_mipi_tx_write_configure_enable()
+{
+    MIPI_TX_PORT0->tx_enable = 0x01;
+}
+
+/**
+* @brief  鍏抽棴mipi妯″潡鍐欐暟鎹厤缃敵璇�
+* @param  none
+* @retval none
+*/
+static inline void drv_mipi_tx_write_configure_disable()
+{
+    MIPI_TX_PORT0->tx_enable = 0x00;
+}
+
+/**
+* @brief  鍚憁ipi妯″潡鍙戝嚭璇绘暟鎹厤缃敵璇凤紝鍚庣画鎵嶈兘鍚憁ipi妯″潡閰嶇疆闇�瑕佽鐨勬暟鎹�
+* @param  none
+* @retval none
+*/
+static inline void drv_mipi_tx_read_configure_enable()
+{
+    MIPI_TX_PORT0->tx_enable = 0x41;
+}
+
+/**
+* @brief  鍏抽棴mipi妯″潡璇绘暟鎹厤缃敵璇�
+* @param  none
+* @retval none
+*/
+static inline void drv_mipi_tx_read_configure_disable()
+{
+    MIPI_TX_PORT0->tx_enable = 0x40;
+}
+
+/**
+* @brief  鎺у埗mipi妯″潡鎸夌収璁惧畾鐨勯厤缃紑濮嬪伐浣�
+* @param  none
+* @retval none
+*/
+static inline bool drv_mipi_tx_work()
+{
+    MIPI_TX_PORT0->tx_control_L = 0x03;
+}
+
+/**
+* @brief  鑾峰彇mipi tx busy鐘舵��
+* @param  none
+* @retval true: MIPI TX妯″潡澶勭悊涓�, false:MIPI TX妯″潡澶勭悊瀹屾垚
+*/
+static inline bool drv_mipi_tx_get_busy()
+{
+    return TAU_BIT_CHECK_ZERO(MIPI_TX_PORT0->tx_state, 0);
+}
+
+/**
+* @brief  鑾峰彇mipi tx read鐨勫��
+* @param  none
+* @retval mipi璇诲彇鐨勫��
+*/
+static inline uint32_t drv_mipi_tx_get_read_result()
+{
+    return MIPI_TX_PORT0->rd_lp_rx_data;
+}
+
+/**
+* @brief  鎺у埗mipi妯″潡鍐欐暟鎹�
+* @param  data: 鏁版嵁buffer
+* @param  cmd_count: 鏁版嵁闀垮害
+* @param  tx_mode: 鍙戦�佹ā寮� 1锛欻S 0:LP
+* @retval none
+*/
+void drv_mipi_tx_write_data(const uint8_t *cmd, uint8_t cmd_count, TX_MODE tx_mode);
+
+/**
+* @brief  鎺у埗mipi妯″潡娓呯┖lp read
+* @param  none
+* @retval none
+*/
+void drv_mipi_tx_lprd_clear();
+
+/**
+* @brief  鎺у埗mipi妯″潡鍙戦�乻et max size鍛戒护
+* @param  data: 鏁版嵁buffer
+* @param  cmd_count: 鏁版嵁闀垮害
+* @param  tx_mode: 鍙戦�佹ā寮� 1锛欻S 0:LP
+* @retval none
+*/
+void drv_mipi_tx_set_max_size(uint8_t max_size);
+
+/**
+* @brief  鎺у埗mipi妯″潡鍙戦�佽鍛戒护
+* @param  cmd: 闇�瑕佸洖璇荤殑瀵勫瓨鍣ㄥ湴鍧�
+* @retval none
+*/
+void drv_mipi_tx_read_data(uint8_t cmd);
+
+#endif
\ No newline at end of file
diff --git a/src/driver/source/drv_mipi_tx.c b/src/driver/source/drv_mipi_tx.c
new file mode 100644
index 0000000..4f4ac16
--- /dev/null
+++ b/src/driver/source/drv_mipi_tx.c
@@ -0,0 +1,125 @@
+#include "drv_mipi_tx.h"
+
+/** \brief 璁剧疆mipi妯″潡鍙戦�佹ā寮�
+ * tx_mode鍙傝�冩灇涓綯X_MODE锛�1涓洪珮閫熷彂閫侊紝0涓轰綆閫熷彂閫�
+ */
+#define SET_MIPI_MODE(tx_mode) (write_addr_UINT8(mipi_tx_lp_hs_mode, tx_mode))
+
+/** \brief 璁剧疆mipi妯″潡鍙戦�佺殑鏁版嵁
+ * data涓哄叿浣撴暟鎹�
+ */
+#define SET_MIPI_DATA(data) (write_addr_UINT32(mipi_tx_send_data, data))
+
+/**
+* @brief  鎺у埗mipi妯″潡鍐欐暟鎹�
+* @param  cmd: 鏁版嵁buffer
+* @param  cmd_count: 鏁版嵁闀垮害
+* @param  tx_mode: 鍙戦�佹ā寮� 1锛欻S 0:LP
+* @retval none
+*/
+void drv_mipi_tx_write_data(const uint8_t *cmd, uint8_t cmd_count, TX_MODE tx_mode)
+{
+    if(cmd_count > 1)
+    {
+        SET_MIPI_MODE(tx_mode);
+
+        /*閰嶇疆mipi妯″潡瑕佸啓鐨勬暟鎹�*/
+        drv_mipi_tx_write_configure_enable();
+        SET_MIPI_DATA((cmd[0] << 24) + (cmd_count << 8) + 0x39 + (0x3 << 6));
+        for (uint8_t i = 0; i < ((cmd_count - 1) >> 2); i++)
+        {
+            SET_MIPI_DATA((cmd[4 + (i << 2)] << 24) + (cmd[3 + (i << 2)] << 16) + (cmd[2 + (i << 2)] << 8) + (cmd[1 + (i << 2)]));
+        }
+        switch ((cmd_count - 1) % 4)
+        {
+        case 1:
+            SET_MIPI_DATA(cmd[cmd_count - 1]);
+            break;
+
+        case 2:
+            SET_MIPI_DATA((cmd[cmd_count - 1] << 8) + cmd[cmd_count - 2]);
+            break;
+
+        case 3:
+            SET_MIPI_DATA((cmd[cmd_count - 1] << 16) + (cmd[cmd_count - 2] << 8) + cmd[cmd_count - 3]);
+            break;
+        
+        default:
+            break;
+        }
+        drv_mipi_tx_write_configure_disable();
+
+        /*鎺у埗mipi妯″潡寮�濮嬪伐浣滐紝骞剁瓑寰卪ipi妯″潡宸ヤ綔缁撴潫*/
+        drv_mipi_tx_work();
+        while (true == drv_mipi_tx_get_busy());
+    }
+    else
+    {
+        SET_MIPI_MODE(tx_mode);
+
+        /*閰嶇疆mipi妯″潡瑕佸啓鐨勬暟鎹�*/
+        drv_mipi_tx_write_configure_enable();
+        SET_MIPI_DATA(0x05 + (cmd[0] << 8));
+        drv_mipi_tx_write_configure_disable();
+
+        /*鎺у埗mipi妯″潡寮�濮嬪伐浣滐紝骞剁瓑寰卪ipi妯″潡宸ヤ綔缁撴潫*/
+        drv_mipi_tx_work();
+        while (true == drv_mipi_tx_get_busy());
+    }
+}
+
+/**
+* @brief  鎺у埗mipi妯″潡娓呯┖lp read
+* @param  none
+* @retval none
+*/
+void drv_mipi_tx_lprd_clear()
+{
+    MIPI_TX_PORT0->tx_enable = 0;
+    MIPI_TX_PORT0->tx_enable = 8;
+    MIPI_TX_PORT0->tx_enable = 0;
+}
+
+/**
+* @brief  鎺у埗mipi妯″潡鍙戦�乻et max size鍛戒护
+* @param  data: 鏁版嵁buffer
+* @param  cmd_count: 鏁版嵁闀垮害
+* @param  tx_mode: 鍙戦�佹ā寮� 1锛欻S 0:LP
+* @retval none
+*/
+void drv_mipi_tx_set_max_size(uint8_t max_size)
+{
+	SET_MIPI_MODE(LP_MODE);
+
+    /*閰嶇疆mipi妯″潡瑕佸啓鐨勬暟鎹�*/
+	drv_mipi_tx_write_configure_enable();
+	SET_MIPI_DATA(0x00003C00 + max_size);
+	drv_mipi_tx_write_configure_disable();
+
+    /*鎺у埗mipi妯″潡寮�濮嬪伐浣滐紝骞剁瓑寰卪ipi妯″潡宸ヤ綔缁撴潫*/
+    drv_mipi_tx_work();
+    while (true == drv_mipi_tx_get_busy());
+}
+
+/**
+* @brief  鎺у埗mipi妯″潡鍙戦�佽鍛戒护
+* @param  cmd: 闇�瑕佸洖璇荤殑瀵勫瓨鍣ㄥ湴鍧�
+* @retval none
+*/
+void drv_mipi_tx_read_data(uint8_t cmd)
+{
+    drv_mipi_tx_read_configure_disable();
+	SET_MIPI_MODE(LP_MODE);
+
+    /*閰嶇疆mipi妯″潡瑕佸啓鐨勬暟鎹�*/
+    drv_mipi_tx_read_configure_enable();
+	SET_MIPI_DATA(0x00000086 + (cmd << 8));		// mipi tx鍙戦�佺殑鏁版嵁
+    drv_mipi_tx_read_configure_disable();
+
+    /*鎺у埗mipi妯″潡寮�濮嬪伐浣滐紝骞剁瓑寰卪ipi妯″潡宸ヤ綔缁撴潫*/
+    drv_mipi_tx_work();
+    while (true == drv_mipi_tx_get_busy());
+}
+
+
+
diff --git a/src/driver/source/hal_edp_rx.c b/src/driver/source/hal_edp_rx.c
new file mode 100644
index 0000000..6381255
--- /dev/null
+++ b/src/driver/source/hal_edp_rx.c
@@ -0,0 +1,205 @@
+/*******************************************************************************
+* File:         hal_edp_rx.h
+* Description:  edp rx妯″潡鎺ュ彛
+* Version:      V1.0
+* Date:         2026-2-27
+* Author:       lyp
+ *******************************************************************************/
+
+#include "hal_edp_rx.h"
+#include "typedef.h"
+#include "define.h"
+
+#define EDP_INPUT_3_51Gbps //EDP_INPUT_3_51Gbps
+#define EDP_TRAIN_BY_TPS1   //濡傛灉TPS1 澶т簬15us,鍚敤姝ゅ畯锛屼竴鑸墜鏈哄簲鐢ㄥ惎鍔紝ipad搴旂敤涓嶅惎鐢�
+
+static void dprx_load_edp_bit_rate_cco(void)
+{
+	uint8  freg =0; 
+	uint8  edp_cdr_prediv =0;
+	uint8  xtal_en = 0;								//澶栭儴鏅舵尟鏄惁璧锋尟
+	uint8  edp_cdr_ext_xtal_en = 0;		//cdr鎭㈠鏄惁鐢ㄥ閮ㄦ櫠鎸�
+	uint8  edp_clkrdy = 0;
+	uint8  val = 0;
+
+	//access flash: write L1 key
+	uint32	tmp32 = 0x2f83631a;
+	uint32  addr32 = 0x80081058;
+	write_addr_UINT32(addr32, tmp32);
+
+#if defined EDP_INPUT_1_62Gbps
+		freg = 0;
+		edp_cdr_prediv =0;
+		edp_clkrdy =6;
+#endif
+
+#if defined EDP_INPUT_1_89Gbps   ||  defined IPAD_MINI6 
+		freg = 1;
+		edp_cdr_prediv = 0;
+		edp_clkrdy = 7;
+#endif
+
+#if defined EDP_INPUT_2_16Gbps  
+		freg = 2;
+		edp_cdr_prediv = 0;
+		edp_clkrdy = 7;
+#endif
+
+#if defined EDP_INPUT_2_43Gbps
+		freg = 3;
+		edp_cdr_prediv = 0;
+		edp_clkrdy = 7;
+#endif
+
+#if defined EDP_INPUT_2_7Gbps
+		freg = 4;
+		edp_cdr_prediv = 0;
+		edp_clkrdy = 8;
+#endif
+
+#if defined EDP_INPUT_2_97Gbps
+		freg = 5;
+		edp_cdr_prediv = 0;
+		edp_clkrdy = 8;
+#endif
+
+#if defined EDP_INPUT_3_24Gbps
+		freg = 6;
+		edp_cdr_prediv = 0;
+		edp_clkrdy = 8;
+#endif
+
+#if defined EDP_INPUT_3_51Gbps  ||  defined IP_16PM  
+		freg = 7;
+		edp_cdr_prediv = 0;
+		edp_clkrdy = 9;
+#endif
+
+#if defined EDP_INPUT_3_78Gbps
+		freg = 8;
+		edp_cdr_prediv = 0;
+		edp_clkrdy = 9;
+#endif
+
+#if defined EDP_INPUT_4_05Gbps
+		freg = 9;
+		edp_cdr_prediv = 1;
+		edp_clkrdy = 7;
+#endif
+
+#if defined EDP_INPUT_4_32Gbps
+		freg = 10;
+		edp_cdr_prediv = 1;
+		edp_clkrdy = 7;
+#endif
+
+#if defined EDP_INPUT_4_59Gbps
+		freg = 11;
+		edp_cdr_prediv = 1;
+		edp_clkrdy = 7;
+#endif
+
+#if defined EDP_INPUT_4_86Gbps
+		freg = 12;
+		edp_cdr_prediv = 1;
+		edp_clkrdy = 7;
+#endif
+
+#if defined EDP_INPUT_5_13Gbps
+		freg = 13;
+		edp_cdr_prediv = 1;
+		edp_clkrdy = =8;
+#endif
+
+#if defined EDP_INPUT_5_4Gbps
+		freg = 14;
+		edp_cdr_prediv = 1;
+		edp_clkrdy = = 8;
+#endif
+
+#if defined EDP_INPUT_5_67Gbps
+		freg = 15;
+		edp_cdr_prediv = 1;
+		edp_clkrdy = = 8;
+#endif
+
+#if defined EDP_INPUT_5_94Gbps
+		freg = 16;
+		edp_cdr_prediv = 1;
+		edp_clkrdy = = 8;
+#endif
+
+#if defined EDP_INPUT_6_21Gbps
+		freg = 17;
+		edp_cdr_prediv = 1;
+		edp_clkrdy = = 8;
+#endif
+
+
+#if defined EDP_INPUT_6_48Gbps
+		freg = 18;
+		edp_cdr_prediv = 1;
+		edp_clkrdy = = 8;
+#endif
+
+#if defined EDP_INPUT_6_75Gbps
+		freg = 19;
+		edp_cdr_prediv = 1;
+		edp_clkrdy = = 9;
+#endif
+
+	tmp32  = 0x8040c004 + freg * 7 * 4;
+	addr32 = 0x80000114;
+	for (uint8 i = 0; i < 8; i++)
+	{
+		write_addr_UINT32(addr32 + 4*i, read_addr_UINT32(tmp32 + 4 * i));
+	}
+	
+#if defined EDP_TRAIN_BY_TPS1   //鏈�15us浠ヤ笂鐨凾PS1锛屽垯鑷仮澶岰RD锛屼笉闇�瑕侀潬澶栭儴EDP鏅舵尟
+	 xtal_en =0;
+	 edp_cdr_ext_xtal_en =0;
+#else														//娌℃湁15us浠ヤ笂鐨凾PS1锛屽惎鐢ㄥ閮ㄦ櫠鎸仛鏃堕挓鎭㈠
+	xtal_en = 1;
+	edp_cdr_ext_xtal_en = 1;
+#endif
+	val = read_addr_UINT8(BASE_ADDR_CFG + 0xba42);    //#page 1  xtal_en
+	val &= ~(3<<4);
+	val = val | (xtal_en <<5) | (edp_cdr_prediv << 4);
+	wr_cfgreg(0xba42, val);
+
+	val = read_addr_UINT8(BASE_ADDR_CFG + 0xba44);   //#page 1  xtal_sclk_sel/edp_cco_ext_xtal_en
+	val &= ~(1 << 1);
+	val = val | (edp_cdr_ext_xtal_en << 1) ;
+	wr_cfgreg(0xba44, val);   //榛樿璧版棤婧愭櫠鎸�
+
+	val = (edp_clkrdy <<4) | 0x06;
+	wr_cfgreg(0xba47, val);   //榛樿璧版棤婧愭櫠鎸�
+}
+
+/**
+* @brief  娉ㄥ唽rx鐩稿叧鍥炶皟
+* @param  RX_CB_Handle: rx鍥炶皟鍙傛暟缁撴瀯浣�
+* @retval true-娉ㄥ唽鎴愬姛锛沠alse-娉ㄥ唽澶辫触
+*/
+bool hal_edp_rx_cb_init(RX_CB_Handle *rx_cb_handle)
+{
+	
+}
+
+bool hal_edp_rx_dpcd_init(const DPCD_Packet *table_address, uint32_t table_size)
+{
+    /*楠岃瘉鍙傛暟鏈夋晥鎬�*/
+    if((NULL == table_address) || (0 == table_size))
+    {
+        return false;
+    }
+
+    for(uint32_t i = 0; i < (table_size / sizeof(DPCD_Packet)); i++)
+    {
+        write_addr_UINT8(BASE_ADDR_DPCD + table_address[i].dpcd_address, table_address[i].dpcd_value);
+    }
+
+    dprx_load_edp_bit_rate_cco();
+
+    return true;
+}
\ No newline at end of file
diff --git a/src/driver/source/hal_mipi_tx.c b/src/driver/source/hal_mipi_tx.c
index 451b418..934a9a7 100644
--- a/src/driver/source/hal_mipi_tx.c
+++ b/src/driver/source/hal_mipi_tx.c
@@ -6,19 +6,10 @@
 * Author:       lyp
  *******************************************************************************/
 
-#include "hal_mipi_tx.h"
 #include "typedef.h"
 #include "define.h"
-
-/*!
- * @brief MIPI鍙戦�佹ā寮�
- * @note
- */
-typedef enum _TX_MODE
-{
-    LP_MODE = 0,
-    HS_MODE,
-}TX_MODE;
+#include "drv_mipi_tx.h"
+#include "hal_mipi_tx.h"
 
 static TX_MODE mipi_state = LP_MODE;
 
@@ -70,46 +61,7 @@ bool hal_dsi_tx_ctrl_write_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd_count,
     }
     va_end(args);
 
-    /*鎺у埗mipi ip鍙戦�佹暟鎹�*/
-    if(cmd_count > 1)
-    {
-        write_addr_UINT8(mipi_tx_lp_hs_mode, mipi_state);
-        write_addr_UINT8(mipi_tx_send_requset, 0x01);
-        write_addr_UINT32(mipi_tx_send_data, (cmd[0] << 24) + (cmd_count << 8) + data_type + (0x3 << 6));
-        for (uint8_t i = 0; i < ((cmd_count - 1) >> 2); i++)
-        {
-            write_addr_UINT32(mipi_tx_send_data, (cmd[4 + (i << 2)] << 24) + (cmd[3 + (i << 2)] << 16) + (cmd[2 + (i << 2)] << 8) + cmd[1 + (i << 2)]);
-        }
-        switch ((cmd_count - 1) % 4)
-        {
-        case 1:
-            write_addr_UINT32(mipi_tx_send_data, cmd[cmd_count - 1]);
-            break;
-
-        case 2:
-            write_addr_UINT32(mipi_tx_send_data, (cmd[cmd_count - 1] << 8) + cmd[cmd_count - 2]);
-            break;
-
-        case 3:
-            write_addr_UINT32(mipi_tx_send_data, (cmd[cmd_count - 1] << 16) + (cmd[cmd_count - 2] << 8) + cmd[cmd_count - 3]);
-            break;
-        
-        default:
-            break;
-        }
-        write_addr_UINT8(mipi_tx_send_requset,0x00);
-        write_addr_UINT8(mipi_tx_trigger_pulse,0x03);
-        while (0 == (read_addr_UINT8(mipi_tx_send_done) & mipi_tx_send_done_mask));
-    }
-    else
-    {
-        write_addr_UINT8(mipi_tx_lp_hs_mode, mipi_state);               // mipi tx lp send cmd enable
-        write_addr_UINT8(mipi_tx_send_requset, 0x01);                   // 鍚憁ipi tx鍙戝嚭鐢宠锛屾媺楂�
-        write_addr_UINT32(mipi_tx_send_data, (0x05 + (cmd[0] << 8)));   // mipi tx鍙戦�佺殑鏁版嵁
-        write_addr_UINT8(mipi_tx_send_requset, 0x00);                   // 瀹屾垚鏁版嵁鍙戦�佸悗锛屾媺浣巜rqst
-        write_addr_UINT8(mipi_tx_trigger_pulse, 0x03);                  // 闅忓悗鍙憈riiger pulse锛岃Е鍙憁ipi tx宸ヤ綔
-        while (0 == (read_addr_UINT8(mipi_tx_send_done) & mipi_tx_send_done_mask));
-    }
+    drv_mipi_tx_write_data(cmd, cmd_count, mipi_state);
 
     return true;
 }
@@ -130,46 +82,7 @@ bool hal_dsi_tx_ctrl_write_array_cmd(uint8_t data_type, uint8_t vc, uint8_t size
         return false;
     }
 
-    /*鎺у埗mipi ip鍙戦�佹暟鎹�*/
-    if(size > 1)
-    {
-        write_addr_UINT8(mipi_tx_lp_hs_mode, mipi_state);
-        write_addr_UINT8(mipi_tx_send_requset, 0x01);
-        write_addr_UINT32(mipi_tx_send_data, (data[0] << 24) + (size << 8) + data_type + (0x3 << 6));
-        for (uint8_t i = 0; i < ((size - 1) >> 2); i++)
-        {
-            write_addr_UINT32(mipi_tx_send_data, (data[4 + (i << 2)] << 24) + (data[3 + (i << 2)] << 16) + (data[2 + (i << 2)] << 8) + data[1 + (i << 2)]);
-        }
-        switch ((size - 1) % 4)
-        {
-        case 1:
-            write_addr_UINT32(mipi_tx_send_data, data[size - 1]);
-            break;
-
-        case 2:
-            write_addr_UINT32(mipi_tx_send_data, (data[size - 1] << 8) + data[size - 2]);
-            break;
-
-        case 3:
-            write_addr_UINT32(mipi_tx_send_data, (data[size - 1] << 16) + (data[size - 2] << 8) + data[size - 3]);
-            break;
-        
-        default:
-            break;
-        }
-        write_addr_UINT8(mipi_tx_send_requset,0x00);
-        write_addr_UINT8(mipi_tx_trigger_pulse,0x03);
-        while (0 == (read_addr_UINT8(mipi_tx_send_done) & mipi_tx_send_done_mask));
-    }
-    else
-    {
-        write_addr_UINT8(mipi_tx_lp_hs_mode, mipi_state);               // mipi tx lp send cmd enable
-        write_addr_UINT8(mipi_tx_send_requset, 0x01);                   // 鍚憁ipi tx鍙戝嚭鐢宠锛屾媺楂�
-        write_addr_UINT32(mipi_tx_send_data, (0x05 + (data[0] << 8)));   // mipi tx鍙戦�佺殑鏁版嵁
-        write_addr_UINT8(mipi_tx_send_requset, 0x00);                   // 瀹屾垚鏁版嵁鍙戦�佸悗锛屾媺浣巜rqst
-        write_addr_UINT8(mipi_tx_trigger_pulse, 0x03);                  // 闅忓悗鍙憈riiger pulse锛岃Е鍙憁ipi tx宸ヤ綔
-        while (0 == (read_addr_UINT8(mipi_tx_send_done) & mipi_tx_send_done_mask));
-    }
+    drv_mipi_tx_write_data(data, size, mipi_state);
 
     return true;
 }
@@ -210,5 +123,16 @@ bool hal_dsi_tx_ctrl_read_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd, uint8_
         return false;
     }
 
+    drv_mipi_tx_lprd_clear();
+    drv_mipi_tx_set_max_size(size);
+    delay_ms(100);
+    drv_mipi_tx_read_data(cmd);
+
+    uint32_t result = drv_mipi_tx_get_read_result();
+    for(int i = 0; i < size; i++)
+    {
+        data[i] = ((result >> i) & 0xFF);
+    }
+
     return true;
 }
\ No newline at end of file
diff --git a/src/include/hal_edp_rx.h b/src/include/hal_edp_rx.h
new file mode 100644
index 0000000..9f4d803
--- /dev/null
+++ b/src/include/hal_edp_rx.h
@@ -0,0 +1,106 @@
+/*******************************************************************************
+* File:         hal_edp_rx.h
+* Description:  edp rx妯″潡鎺ュ彛
+* Version:      V1.0
+* Date:         2026-2-27
+* Author:       lyp
+ *******************************************************************************/
+
+#ifndef __HAL_EDP_RX_H__
+#define __HAL_EDP_RX_H__
+
+#include <stdarg.h>
+#include "la_config.h"
+
+/**
+ * @brief SDP鏁版嵁
+ * @note
+ */
+typedef struct _SDP_Info
+{
+	uint8_t SDP_HB[4];
+	uint8_t SDP_DB[32];
+	uint8_t SDP_ERR_FLAG[4];
+}SDP_Info;
+
+/**
+ * @brief DPCD鍦板潃鍙婂搴旀暟鎹�
+ * @note dpcd_address鏄疍PCD鍦板潃
+ *       dpcd_value鏄疍PCD鍦板潃閲屽搴旂殑鏁板��
+ */
+typedef struct _DPCD_Packet
+{
+    uint32_t dpcd_address;
+    uint8_t dpcd_value;
+}DPCD_Packet;
+
+/* SDP鏇存柊鍥炶皟锛岀敤浜庤幏鍙杝econd data packet */
+typedef void (*hal_edp_rx_sdp_cb)(SDP_Info sdp_info);
+
+/* 浼戠湢鍥炶皟锛屽綋鍩烘澘閫氳繃AUX寰�DPCD瀵勫瓨鍣�600H鍐�02鏃惰Е鍙� */
+typedef void (*hal_edp_rx_sleep_cb)(void);
+
+/* 鍞ら啋鍥炶皟锛屽綋鍩烘澘reset鑴氭媺楂樿Е鍙� */
+typedef void (*hal_edp_rx_wake_cb)(void);
+
+/**
+ * @brief SDP鏇存柊鍥炶皟娉ㄥ唽
+ * @note sleep_cb鏄敜閱掑洖璋冨湴鍧�
+ *       execute_mode鏄墽琛屾柟寮忥細true-鍦ㄤ腑鏂噷绔嬪嵆鎵ц,false-鍔犲叆闃熷垪寮傛鎵ц
+ */
+typedef struct _SDP_Handle
+{
+    hal_edp_rx_sdp_cb sdp_cb;
+    bool execute_mode;
+}SDP_Handle;
+
+/**
+ * @brief 浼戠湢鍥炶皟娉ㄥ唽
+ * @note sleep_cb鏄敜閱掑洖璋冨湴鍧�
+ *       execute_mode鏄墽琛屾柟寮忥細true-鍦ㄤ腑鏂噷绔嬪嵆鎵ц,false-鍔犲叆闃熷垪寮傛鎵ц
+ */
+typedef struct _Sleep_Handle
+{
+    hal_edp_rx_sleep_cb sleep_cb;
+    bool execute_mode;
+}Sleep_Handle;
+
+/**
+ * @brief 鍞ら啋鍥炶皟娉ㄥ唽
+ * @note wake_cb鏄敜閱掑洖璋冨湴鍧�
+ *       execute_mode鏄墽琛屾柟寮忥細true-鍦ㄤ腑鏂噷绔嬪嵆鎵ц,false-鍔犲叆闃熷垪寮傛鎵ц
+ *       闇�鍦ㄤ笂浣嶆満璁剧疆鍩烘澘reset鑴氭帴鍦ㄨ姱鐗囧叿浣撶鑴�
+ */
+typedef struct _WAKE_Handle
+{
+    hal_edp_rx_wake_cb wake_cb;
+    bool execute_mode;
+}WAKE_Handle;
+
+/**
+ * @brief rx鐩稿叧鍔熻兘鍥炶皟
+ * @note
+ */
+typedef struct _RX_CB_Handle
+{
+    SDP_Handle sdp_handle;
+    Sleep_Handle sleep_handle;
+    WAKE_Handle wake_handle;
+}RX_CB_Handle;
+
+/**
+* @brief  娉ㄥ唽rx鐩稿叧鍥炶皟
+* @param  RX_CB_Handle: rx鍥炶皟鍙傛暟缁撴瀯浣�
+* @retval true-娉ㄥ唽鎴愬姛锛沠alse-娉ㄥ唽澶辫触
+*/
+bool hal_edp_rx_cb_init(RX_CB_Handle *rx_cb_handle);
+
+/**
+* @brief  鍒濆鍖朌PCD瀵勫瓨鍣�
+* @param  table_address: DPCD鏁版嵁琛ㄥ湴鍧�
+* @param  table_size: DPCD鏁版嵁琛ㄥぇ灏�
+* @retval true-鍒濆鍖栨甯革紱false-鍒濆鍖栧紓甯�
+*/
+bool hal_edp_rx_dpcd_init(const DPCD_Packet *table_address, uint32_t table_size);
+
+#endif
\ No newline at end of file
diff --git a/src/include/typedef.h b/src/include/typedef.h
index 44e6638..878ee92 100644
--- a/src/include/typedef.h
+++ b/src/include/typedef.h
@@ -43,6 +43,101 @@ typedef uint32	uint32_t;
 
 #define NULL ((void *)0)
 
+/************************************************************************閫氱敤鎿嶄綔*****************************************************************/
+/** \brief bit绉讳綅
+ * TAU_BIT(2) is 0x4
+ */
+#define TAU_BIT(bit)                  (1u << (bit))
+
+/** \brief 鍊肩Щ浣�
+ * TAU_SBF(0xFF, 8) is 0xff00
+ */
+#define TAU_SBF(value, field)         ((value) << (field))
+
+/** \brief bit缃綅
+ * TAU_BIT_SET(0, 8) is 0x100
+ */
+#define TAU_BIT_SET(data, bit)        ((data) |= TAU_BIT(bit))
+
+/** \brief bit娓呴浂
+ * TAU_BIT_CLR(0xFF, 2) is 0xfb
+ */
+#define TAU_BIT_CLR(data, bit)        ((data) &= ~TAU_BIT(bit))
+
+/** \brief bit缃綅, 鏍规嵁 mask 鎸囧畾鐨勪綅
+ * TAU_BIT_SET_MASK(0xF0F0, 0xF00) is 0xfff0
+ */
+#define TAU_BIT_SET_MASK(data, mask)  ((data) |= (mask))
+
+/** \brief bit娓呴浂, 鏍规嵁 mask 鎸囧畾鐨勪綅
+ * TAU_BIT_CLR_MASK(0xFFFF, 0xFF00) is 0xff
+ */
+#define TAU_BIT_CLR_MASK(data, mask)  ((data) &= ~(mask))
+
+/** \brief bit缈昏浆
+ * TAU_BIT_TOGGLE(0xFFFF, 0) is 0xfffe
+ * TAU_BIT_TOGGLE(0x0000, 1) is 0x2
+ */
+#define TAU_BIT_TOGGLE(data, bit)     ((data) ^= TAU_BIT(bit))
+
+/** \brief bit淇敼
+ * TAU_BIT_MODIFY(0, 8, 1) is 0x100
+ * TAU_BIT_MODIFY(0xFFFF, 1, 0) is 0xfffd
+ */
+#define TAU_BIT_MODIFY(data, bit, value) \
+    ((value) ? TAU_BIT_SET(data, bit) : TAU_BIT_CLR(data, bit))
+
+/** \brief 娴嬭瘯bit鏄惁缃綅
+ * TAU_BIT_ISSET(0xF0F1, 1) is 0
+ * TAU_BIT_ISSET(0xF0F2, 1) is 2
+ */
+#define TAU_BIT_ISSET(data, bit)      ((data) & TAU_BIT(bit))
+
+/** \brief 鑾峰彇bit鍊�
+ * TAU_BIT_GET(0xF0F1, 1) is 0
+ * TAU_BIT_GET(0xF0F2, 1) is 1
+ */
+#define TAU_BIT_GET(data, bit)        (TAU_BIT_ISSET(data, bit) ? 1 : 0)
+
+/** \brief 妫�娴媌it鍊兼槸鍚︿负闆�
+ * TAU_BIT_CHECK(0xF5FF, 4) is false(0)
+ */
+#define TAU_BIT_CHECK_ZERO(data, bit)  \
+    (((data) & TAU_BIT(bit)) ? 0 : 1)
+
+/** \brief 鑾峰彇 n bits 鎺╃爜鍊�
+ * TAU_BITS_MASK(2) is 0x3
+ */
+#define TAU_BITS_MASK(n)              (~((~0u) << (n)))
+
+/** \brief 鑾峰彇浣嶆鍊�
+ * TAU_BITS_GET(0xF5FF, 0x0F00, 8) is 0x5
+ */
+#define TAU_BITS_GET(data, mask, pos)  \
+    (((data) & (mask)) >> (pos))
+
+/** \brief 鑾峰彇浣嶆鍊�
+ * TAU_BITS_CHECK(0xF5FF, 0x0F00) is 1
+ */
+#define TAU_BITS_CHECK(data, mask)  \
+    (((data) & (mask)) ? 1 : 0)
+
+/** \brief 淇敼浣嶆鍊�
+ * TAU_BITS_MODIFY(0xF5FF, 0x0FF0, 0x8A0) is 0xF8AF
+*/
+#define TAU_BITS_MODIFY(data, clear_mask, set_mask) \
+    (data) = (((data) & (~(clear_mask))) | (set_mask))
+
+/** \brief 璁剧疆浣嶆鍊�
+ * TAU_WRITE_REG32(0x05FF, 0xFFFA) is 0xFFFA
+*/
+#define TAU_WRITE_REG32(data, value) ((data) = (value))
+
+/** \brief 璁剧疆浣嶆鍊�
+ * TAU_RAED_REG32(0x05FF) is 0x05FF
+*/
+#define TAU_RAED_REG32(data) (data)
+
 #define REG32(addr)                  (*(volatile uint32_t *)(uint32_t)(addr))
 #define REG16(addr)                  (*(volatile uint16_t *)(uint32_t)(addr))
 #define REG8(addr)                   (*(volatile uint8_t *)(uint32_t)(addr))