commit f52191065445b031749170739875735de6b9b61a Author: liyuanpeng Date: Mon Jan 26 15:48:44 2026 +0800 初次提交，仅写了mipi tx部分 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..d73c455 --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +/pgm +/compile +/fw2flash +/link +/output diff --git a/coding_rule.txt b/coding_rule.txt new file mode 100644 index 0000000..fff5293 --- /dev/null +++ b/coding_rule.txt @@ -0,0 +1,23 @@ +1、SDK变量命名延续原SDK的下划线命名法，不使用驼峰命名法 +2、编码格式使用UTF-8 +3、if判断相等时变量放在右值 +4、对外接口必须检测入口参数 +5、单一语句需内联 +6、硬件操作相关变量定义需防优化 + +WL818_SDK +├─compile +├─fw2flash +├─link +├─output +├─pgm +└─src + ├─.vs + ├─code //用户app + │ └─project_case + │ └─RM692H5_120HZ_DSC3_1 + ├─driver //驱动层，对内封装寄存器地址 + │ ├─include + │ ├─source + │ └─ulog + └─include //对外头文件hal和common定义 \ No newline at end of file diff --git a/src/.vs/ProjectSettings.json b/src/.vs/ProjectSettings.json new file mode 100644 index 0000000..e257ff9 --- /dev/null +++ b/src/.vs/ProjectSettings.json @@ -0,0 +1,3 @@ +{ + "CurrentProjectSetting": "无配置" +} \ No newline at end of file diff --git a/src/.vs/VSWorkspaceState.json b/src/.vs/VSWorkspaceState.json new file mode 100644 index 0000000..d76e7e8 --- /dev/null +++ b/src/.vs/VSWorkspaceState.json @@ -0,0 +1,15 @@ +{ + "ExpandedNodes": [ + "", + "\\code", + "\\code\\project_case", + "\\code\\project_case\\RM692H5_120HZ_DSC3_1", + "\\driver", + "\\driver\\include", + "\\driver\\source", + "\\driver\\ulog", + "\\include" + ], + "SelectedNode": "\\driver\\include\\la_uart.h", + "PreviewInSolutionExplorer": false +} \ No newline at end of file diff --git a/src/.vs/slnx.sqlite b/src/.vs/slnx.sqlite new file mode 100644 index 0000000..7778bfa Binary files /dev/null and b/src/.vs/slnx.sqlite differ diff --git a/src/.vs/src/v16/.suo b/src/.vs/src/v16/.suo new file mode 100644 index 0000000..324ab73 Binary files /dev/null and b/src/.vs/src/v16/.suo differ diff --git a/src/.vs/src/v16/Browse.VC.db b/src/.vs/src/v16/Browse.VC.db new file mode 100644 index 0000000..47c0512 Binary files /dev/null and b/src/.vs/src/v16/Browse.VC.db differ diff --git a/src/.vs/src/v16/Browse.VC.db-shm b/src/.vs/src/v16/Browse.VC.db-shm new file mode 100644 index 0000000..12f3be4 Binary files /dev/null and b/src/.vs/src/v16/Browse.VC.db-shm differ diff --git a/src/.vs/src/v16/Browse.VC.db-wal b/src/.vs/src/v16/Browse.VC.db-wal new file mode 100644 index 0000000..e69de29 diff --git a/src/.vs/src/v16/Browse.VC.opendb b/src/.vs/src/v16/Browse.VC.opendb new file mode 100644 index 0000000..fe5e9e4 Binary files /dev/null and b/src/.vs/src/v16/Browse.VC.opendb differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/105507fe74c08bbd/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/105507fe74c08bbd/INI.ipch new file mode 100644 index 0000000..800ecfd Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/105507fe74c08bbd/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/11ca8b865dfd79b/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/11ca8b865dfd79b/INI.ipch new file mode 100644 index 0000000..659d7a7 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/11ca8b865dfd79b/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/154ab03b47ed86b2/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/154ab03b47ed86b2/MIPI_TX.ipch new file mode 100644 index 0000000..c0f708d Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/154ab03b47ed86b2/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/1641d9ad41779a78/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/1641d9ad41779a78/MIPI_TX.ipch new file mode 100644 index 0000000..7d69881 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/1641d9ad41779a78/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/1742b4fafddb2da3/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/1742b4fafddb2da3/MIPI_TX.ipch new file mode 100644 index 0000000..06a6272 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/1742b4fafddb2da3/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/199c7c14dcd2d42d/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/199c7c14dcd2d42d/INI.ipch new file mode 100644 index 0000000..1013d4d Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/199c7c14dcd2d42d/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/1d1b195880cccf5a/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/1d1b195880cccf5a/INI.ipch new file mode 100644 index 0000000..adf9167 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/1d1b195880cccf5a/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/25322750d42a3acd/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/25322750d42a3acd/MIPI_TX.ipch new file mode 100644 index 0000000..2662e1b Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/25322750d42a3acd/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/2f761713c9e8b34b/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/2f761713c9e8b34b/INI.ipch new file mode 100644 index 0000000..8acee04 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/2f761713c9e8b34b/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/3188dfcfd3a5ae65/LA_DPRX.ipch b/src/.vs/src/v16/ipch/AutoPCH/3188dfcfd3a5ae65/LA_DPRX.ipch new file mode 100644 index 0000000..8974b54 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/3188dfcfd3a5ae65/LA_DPRX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/3368f744642bd89b/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/3368f744642bd89b/INI.ipch new file mode 100644 index 0000000..c8e844b Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/3368f744642bd89b/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/365ffff64997d65a/DPRX.ipch b/src/.vs/src/v16/ipch/AutoPCH/365ffff64997d65a/DPRX.ipch new file mode 100644 index 0000000..e6cf515 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/365ffff64997d65a/DPRX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/36655fa40299a770/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/36655fa40299a770/MIPI_TX.ipch new file mode 100644 index 0000000..ae6dc25 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/36655fa40299a770/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/36902d39c2c13f62/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/36902d39c2c13f62/MIPI_TX.ipch new file mode 100644 index 0000000..b7ef203 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/36902d39c2c13f62/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/397726c1862ec260/PERIP_TEST.ipch b/src/.vs/src/v16/ipch/AutoPCH/397726c1862ec260/PERIP_TEST.ipch new file mode 100644 index 0000000..4b132ba Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/397726c1862ec260/PERIP_TEST.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/39cdab4161e9d75e/COMMON.ipch b/src/.vs/src/v16/ipch/AutoPCH/39cdab4161e9d75e/COMMON.ipch new file mode 100644 index 0000000..a76bbf8 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/39cdab4161e9d75e/COMMON.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/3e9bd62afb70076d/LA_DMA.ipch b/src/.vs/src/v16/ipch/AutoPCH/3e9bd62afb70076d/LA_DMA.ipch new file mode 100644 index 0000000..87e060f Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/3e9bd62afb70076d/LA_DMA.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/3fe7d949a886e7e4/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/3fe7d949a886e7e4/INI.ipch new file mode 100644 index 0000000..fad6679 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/3fe7d949a886e7e4/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/44ef3a17e1fb23ca/COMMON.ipch b/src/.vs/src/v16/ipch/AutoPCH/44ef3a17e1fb23ca/COMMON.ipch new file mode 100644 index 0000000..19842d1 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/44ef3a17e1fb23ca/COMMON.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/4502472fb34ae17c/PERIP_TEST.ipch b/src/.vs/src/v16/ipch/AutoPCH/4502472fb34ae17c/PERIP_TEST.ipch new file mode 100644 index 0000000..2ac0990 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/4502472fb34ae17c/PERIP_TEST.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/48c7376281330c57/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/48c7376281330c57/MIPI_TX.ipch new file mode 100644 index 0000000..811bcad Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/48c7376281330c57/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/4cd2d2565ac67fa6/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/4cd2d2565ac67fa6/INI.ipch new file mode 100644 index 0000000..8c1cea0 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/4cd2d2565ac67fa6/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/54b7626182e6b143/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/54b7626182e6b143/MIPI_TX.ipch new file mode 100644 index 0000000..06a7cbf Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/54b7626182e6b143/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/5a256940f59917bd/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/5a256940f59917bd/MIPI_TX.ipch new file mode 100644 index 0000000..9cf288e Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/5a256940f59917bd/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/5cee7978ad75634d/DPRX.ipch b/src/.vs/src/v16/ipch/AutoPCH/5cee7978ad75634d/DPRX.ipch new file mode 100644 index 0000000..c4eb56e Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/5cee7978ad75634d/DPRX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/5f276382e508c6d/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/5f276382e508c6d/INI.ipch new file mode 100644 index 0000000..8a77042 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/5f276382e508c6d/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/6210a4f02e7b9dfd/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/6210a4f02e7b9dfd/MIPI_TX.ipch new file mode 100644 index 0000000..0ebbd21 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/6210a4f02e7b9dfd/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/6647498e6eb05143/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/6647498e6eb05143/MIPI_TX.ipch new file mode 100644 index 0000000..d2b2e93 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/6647498e6eb05143/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/683bb8335a374ff4/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/683bb8335a374ff4/INI.ipch new file mode 100644 index 0000000..de90938 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/683bb8335a374ff4/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/741f84994313d6b6/CORE_MAIN.ipch b/src/.vs/src/v16/ipch/AutoPCH/741f84994313d6b6/CORE_MAIN.ipch new file mode 100644 index 0000000..4cee238 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/741f84994313d6b6/CORE_MAIN.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/7829165cc8c0e6bf/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/7829165cc8c0e6bf/INI.ipch new file mode 100644 index 0000000..60e865f Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/7829165cc8c0e6bf/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/7e20b6bb51fc84e2/CORE_MAIN.ipch b/src/.vs/src/v16/ipch/AutoPCH/7e20b6bb51fc84e2/CORE_MAIN.ipch new file mode 100644 index 0000000..1d590be Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/7e20b6bb51fc84e2/CORE_MAIN.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/7fc9531edf62a3e/LA_TIMER.ipch b/src/.vs/src/v16/ipch/AutoPCH/7fc9531edf62a3e/LA_TIMER.ipch new file mode 100644 index 0000000..294a22b Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/7fc9531edf62a3e/LA_TIMER.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/83bd019514e67573/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/83bd019514e67573/MIPI_TX.ipch new file mode 100644 index 0000000..9274bf4 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/83bd019514e67573/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/83cd7229398e5720/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/83cd7229398e5720/INI.ipch new file mode 100644 index 0000000..57fb605 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/83cd7229398e5720/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/863be4e672b1db31/LA_DMA.ipch b/src/.vs/src/v16/ipch/AutoPCH/863be4e672b1db31/LA_DMA.ipch new file mode 100644 index 0000000..9e3b88b Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/863be4e672b1db31/LA_DMA.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/88fa3296cea8d7f6/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/88fa3296cea8d7f6/INI.ipch new file mode 100644 index 0000000..5b0b191 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/88fa3296cea8d7f6/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/8a4baeea5cc40fe2/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/8a4baeea5cc40fe2/INI.ipch new file mode 100644 index 0000000..f35e064 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/8a4baeea5cc40fe2/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/95966ca2edb10349/LA_DPRX.ipch b/src/.vs/src/v16/ipch/AutoPCH/95966ca2edb10349/LA_DPRX.ipch new file mode 100644 index 0000000..cd6f54d Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/95966ca2edb10349/LA_DPRX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/9c71a51020ac2d2a/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/9c71a51020ac2d2a/MIPI_TX.ipch new file mode 100644 index 0000000..d657848 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/9c71a51020ac2d2a/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/a0e4bc72ca0e8c5e/DPRX.ipch b/src/.vs/src/v16/ipch/AutoPCH/a0e4bc72ca0e8c5e/DPRX.ipch new file mode 100644 index 0000000..721f280 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/a0e4bc72ca0e8c5e/DPRX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/a6298843f9ef4f3f/LA_I2C.ipch b/src/.vs/src/v16/ipch/AutoPCH/a6298843f9ef4f3f/LA_I2C.ipch new file mode 100644 index 0000000..072389c Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/a6298843f9ef4f3f/LA_I2C.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/a99d49caff589ae6/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/a99d49caff589ae6/MIPI_TX.ipch new file mode 100644 index 0000000..9e98377 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/a99d49caff589ae6/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/ac84574576a1ce15/ISR.ipch b/src/.vs/src/v16/ipch/AutoPCH/ac84574576a1ce15/ISR.ipch new file mode 100644 index 0000000..2f40142 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/ac84574576a1ce15/ISR.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/b602516e76b13d7b/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/b602516e76b13d7b/INI.ipch new file mode 100644 index 0000000..d00f93c Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/b602516e76b13d7b/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/b81c9bf3a15cfacb/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/b81c9bf3a15cfacb/INI.ipch new file mode 100644 index 0000000..664e601 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/b81c9bf3a15cfacb/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/baf839d30f99dcdb/LA_UART.ipch b/src/.vs/src/v16/ipch/AutoPCH/baf839d30f99dcdb/LA_UART.ipch new file mode 100644 index 0000000..cb423c4 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/baf839d30f99dcdb/LA_UART.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/bcf4a5647e37abea/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/bcf4a5647e37abea/INI.ipch new file mode 100644 index 0000000..f54f0ce Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/bcf4a5647e37abea/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/bd51af4d97cadf97/EE_PRINTF.ipch b/src/.vs/src/v16/ipch/AutoPCH/bd51af4d97cadf97/EE_PRINTF.ipch new file mode 100644 index 0000000..c44ad44 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/bd51af4d97cadf97/EE_PRINTF.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/be0d02438e3af751/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/be0d02438e3af751/INI.ipch new file mode 100644 index 0000000..590b1b1 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/be0d02438e3af751/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/c2c583e5ba02e5b9/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/c2c583e5ba02e5b9/INI.ipch new file mode 100644 index 0000000..937f801 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/c2c583e5ba02e5b9/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/c2ff3767f758c533/LA_WDG.ipch b/src/.vs/src/v16/ipch/AutoPCH/c2ff3767f758c533/LA_WDG.ipch new file mode 100644 index 0000000..8824fef Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/c2ff3767f758c533/LA_WDG.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/ca8120bbdebf53c9/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/ca8120bbdebf53c9/MIPI_TX.ipch new file mode 100644 index 0000000..0880f3a Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/ca8120bbdebf53c9/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/ccddaeae2284f14c/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/ccddaeae2284f14c/INI.ipch new file mode 100644 index 0000000..a732b52 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/ccddaeae2284f14c/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/d0de57262ede4f7c/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/d0de57262ede4f7c/MIPI_TX.ipch new file mode 100644 index 0000000..91c0801 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/d0de57262ede4f7c/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/d570a963ec183dbb/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/d570a963ec183dbb/MIPI_TX.ipch new file mode 100644 index 0000000..50ec7a0 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/d570a963ec183dbb/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/d7c3540cefe41f14/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/d7c3540cefe41f14/INI.ipch new file mode 100644 index 0000000..9fa7af4 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/d7c3540cefe41f14/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/d8aa646bf0deacba/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/d8aa646bf0deacba/INI.ipch new file mode 100644 index 0000000..6b4933a Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/d8aa646bf0deacba/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/d95c3cede5eb8ada/CORE_MAIN.ipch b/src/.vs/src/v16/ipch/AutoPCH/d95c3cede5eb8ada/CORE_MAIN.ipch new file mode 100644 index 0000000..d0d482b Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/d95c3cede5eb8ada/CORE_MAIN.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/dc5445cef88016be/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/dc5445cef88016be/MIPI_TX.ipch new file mode 100644 index 0000000..fa1bef1 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/dc5445cef88016be/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/dce28b0a0e257c9c/LA_GPIO.ipch b/src/.vs/src/v16/ipch/AutoPCH/dce28b0a0e257c9c/LA_GPIO.ipch new file mode 100644 index 0000000..1501435 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/dce28b0a0e257c9c/LA_GPIO.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/eec635cf0a48d980/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/eec635cf0a48d980/INI.ipch new file mode 100644 index 0000000..325806e Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/eec635cf0a48d980/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/f072757ada07f5f3/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/f072757ada07f5f3/MIPI_TX.ipch new file mode 100644 index 0000000..071d22d Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/f072757ada07f5f3/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/f194075e0f4542e8/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/f194075e0f4542e8/MIPI_TX.ipch new file mode 100644 index 0000000..f42199d Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/f194075e0f4542e8/MIPI_TX.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/f206f5405a2aabed/LA_SPI.ipch b/src/.vs/src/v16/ipch/AutoPCH/f206f5405a2aabed/LA_SPI.ipch new file mode 100644 index 0000000..b90e00d Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/f206f5405a2aabed/LA_SPI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/f40e1d5f87e42773/INI.ipch b/src/.vs/src/v16/ipch/AutoPCH/f40e1d5f87e42773/INI.ipch new file mode 100644 index 0000000..c1ab5bd Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/f40e1d5f87e42773/INI.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/f53081490300c2d2/IT.ipch b/src/.vs/src/v16/ipch/AutoPCH/f53081490300c2d2/IT.ipch new file mode 100644 index 0000000..5475060 Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/f53081490300c2d2/IT.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/f6a9eb6e8f2c0271/ISR.ipch b/src/.vs/src/v16/ipch/AutoPCH/f6a9eb6e8f2c0271/ISR.ipch new file mode 100644 index 0000000..949f20a Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/f6a9eb6e8f2c0271/ISR.ipch differ diff --git a/src/.vs/src/v16/ipch/AutoPCH/ff2932dc3dccdcd6/MIPI_TX.ipch b/src/.vs/src/v16/ipch/AutoPCH/ff2932dc3dccdcd6/MIPI_TX.ipch new file mode 100644 index 0000000..72e15ea Binary files /dev/null and b/src/.vs/src/v16/ipch/AutoPCH/ff2932dc3dccdcd6/MIPI_TX.ipch differ diff --git a/src/.vs/src/v17/.wsuo b/src/.vs/src/v17/.wsuo new file mode 100644 index 0000000..0898aa2 Binary files /dev/null and b/src/.vs/src/v17/.wsuo differ diff --git a/src/.vs/src/v17/DocumentLayout.backup.json b/src/.vs/src/v17/DocumentLayout.backup.json new file mode 100644 index 0000000..ca2389c --- /dev/null +++ b/src/.vs/src/v17/DocumentLayout.backup.json @@ -0,0 +1,78 @@ +{ + "Version": 1, + "WorkspaceRootPath": "D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\", + "Documents": [ + { + "AbsoluteMoniker": "D:0:0:{A2FE74E1-B743-11D0-AE1A-00A0C90FFFC3}|\u003CMiscFiles\u003E|D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\mipi_tx.c||{D0E1A5C6-B359-4E41-9B60-3365922C2A22}", + "RelativeMoniker": "D:0:0:{A2FE74E1-B743-11D0-AE1A-00A0C90FFFC3}|\u003CMiscFiles\u003E|solutionrelative:code\\project_case\\RM692H5_120HZ_DSC3_1\\mipi_tx.c||{D0E1A5C6-B359-4E41-9B60-3365922C2A22}" + }, + { + "AbsoluteMoniker": "D:0:0:{A2FE74E1-B743-11D0-AE1A-00A0C90FFFC3}|\u003CMiscFiles\u003E|D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\ini.c||{D0E1A5C6-B359-4E41-9B60-3365922C2A22}", + "RelativeMoniker": "D:0:0:{A2FE74E1-B743-11D0-AE1A-00A0C90FFFC3}|\u003CMiscFiles\u003E|solutionrelative:code\\project_case\\RM692H5_120HZ_DSC3_1\\ini.c||{D0E1A5C6-B359-4E41-9B60-3365922C2A22}" + }, + { + "AbsoluteMoniker": "D:0:0:{A2FE74E1-B743-11D0-AE1A-00A0C90FFFC3}|\u003CMiscFiles\u003E|D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\pmic.c||{D0E1A5C6-B359-4E41-9B60-3365922C2A22}", + "RelativeMoniker": "D:0:0:{A2FE74E1-B743-11D0-AE1A-00A0C90FFFC3}|\u003CMiscFiles\u003E|solutionrelative:code\\project_case\\RM692H5_120HZ_DSC3_1\\pmic.c||{D0E1A5C6-B359-4E41-9B60-3365922C2A22}" + } + ], + "DocumentGroupContainers": [ + { + "Orientation": 0, + "VerticalTabListWidth": 256, + "DocumentGroups": [ + { + "DockedWidth": 200, + "SelectedChildIndex": 4, + "Children": [ + { + "$type": "Bookmark", + "Name": "ST:0:0:{3ae79031-e1bc-11d0-8f78-00a0c9110057}" + }, + { + "$type": "Bookmark", + "Name": "ST:0:0:{1c64b9c2-e352-428e-a56d-0ace190b99a6}" + }, + { + "$type": "Document", + "DocumentIndex": 1, + "Title": "ini.c", + "DocumentMoniker": "D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\ini.c", + "RelativeDocumentMoniker": "code\\project_case\\RM692H5_120HZ_DSC3_1\\ini.c", + "ToolTip": "D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\ini.c", + "RelativeToolTip": "code\\project_case\\RM692H5_120HZ_DSC3_1\\ini.c", + "ViewState": "AgIAABkAAAAAAAAAAAAAwCwAAAAXAAAAAAAAAA==", + "Icon": "ae27a6b0-e345-4288-96df-5eaf394ee369.000423|", + "WhenOpened": "2025-11-28T05:59:36.166Z", + "EditorCaption": "" + }, + { + "$type": "Document", + "DocumentIndex": 2, + "Title": "pmic.c", + "DocumentMoniker": "D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\pmic.c", + "RelativeDocumentMoniker": "code\\project_case\\RM692H5_120HZ_DSC3_1\\pmic.c", + "ToolTip": "D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\pmic.c", + "RelativeToolTip": "code\\project_case\\RM692H5_120HZ_DSC3_1\\pmic.c", + "ViewState": "AgIAAAAAAAAAAAAAAADwvwAAAAAAAAAAAAAAAA==", + "Icon": "ae27a6b0-e345-4288-96df-5eaf394ee369.000423|", + "WhenOpened": "2025-11-28T05:51:18.653Z" + }, + { + "$type": "Document", + "DocumentIndex": 0, + "Title": "mipi_tx.c", + "DocumentMoniker": "D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\mipi_tx.c", + "RelativeDocumentMoniker": "code\\project_case\\RM692H5_120HZ_DSC3_1\\mipi_tx.c", + "ToolTip": "D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\mipi_tx.c", + "RelativeToolTip": "code\\project_case\\RM692H5_120HZ_DSC3_1\\mipi_tx.c", + "ViewState": "AgIAAAYFAAAAAAAAAAAAACMFAAAeAAAAAAAAAA==", + "Icon": "ae27a6b0-e345-4288-96df-5eaf394ee369.000423|", + "WhenOpened": "2025-11-28T04:16:19.696Z", + "EditorCaption": "" + } + ] + } + ] + } + ] +} \ No newline at end of file diff --git a/src/.vs/src/v17/DocumentLayout.json b/src/.vs/src/v17/DocumentLayout.json new file mode 100644 index 0000000..e0e9ca6 --- /dev/null +++ b/src/.vs/src/v17/DocumentLayout.json @@ -0,0 +1,62 @@ +{ + "Version": 1, + "WorkspaceRootPath": "D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\", + "Documents": [ + { + "AbsoluteMoniker": "D:0:0:{A2FE74E1-B743-11D0-AE1A-00A0C90FFFC3}|\u003CMiscFiles\u003E|D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\ini.c||{D0E1A5C6-B359-4E41-9B60-3365922C2A22}", + "RelativeMoniker": "D:0:0:{A2FE74E1-B743-11D0-AE1A-00A0C90FFFC3}|\u003CMiscFiles\u003E|solutionrelative:code\\project_case\\RM692H5_120HZ_DSC3_1\\ini.c||{D0E1A5C6-B359-4E41-9B60-3365922C2A22}" + }, + { + "AbsoluteMoniker": "D:0:0:{A2FE74E1-B743-11D0-AE1A-00A0C90FFFC3}|\u003CMiscFiles\u003E|D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\mipi_tx.c||{D0E1A5C6-B359-4E41-9B60-3365922C2A22}", + "RelativeMoniker": "D:0:0:{A2FE74E1-B743-11D0-AE1A-00A0C90FFFC3}|\u003CMiscFiles\u003E|solutionrelative:code\\project_case\\RM692H5_120HZ_DSC3_1\\mipi_tx.c||{D0E1A5C6-B359-4E41-9B60-3365922C2A22}" + } + ], + "DocumentGroupContainers": [ + { + "Orientation": 0, + "VerticalTabListWidth": 256, + "DocumentGroups": [ + { + "DockedWidth": 200, + "SelectedChildIndex": 3, + "Children": [ + { + "$type": "Bookmark", + "Name": "ST:0:0:{3ae79031-e1bc-11d0-8f78-00a0c9110057}" + }, + { + "$type": "Bookmark", + "Name": "ST:0:0:{1c64b9c2-e352-428e-a56d-0ace190b99a6}" + }, + { + "$type": "Document", + "DocumentIndex": 1, + "Title": "mipi_tx.c", + "DocumentMoniker": "D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\mipi_tx.c", + "RelativeDocumentMoniker": "code\\project_case\\RM692H5_120HZ_DSC3_1\\mipi_tx.c", + "ToolTip": "D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\mipi_tx.c", + "RelativeToolTip": "code\\project_case\\RM692H5_120HZ_DSC3_1\\mipi_tx.c", + "ViewState": "AgIAABIFAAAAAAAAAAAAACQFAAAUAAAAAAAAAA==", + "Icon": "ae27a6b0-e345-4288-96df-5eaf394ee369.000423|", + "WhenOpened": "2025-12-04T08:25:27.208Z", + "EditorCaption": "" + }, + { + "$type": "Document", + "DocumentIndex": 0, + "Title": "ini.c", + "DocumentMoniker": "D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\ini.c", + "RelativeDocumentMoniker": "code\\project_case\\RM692H5_120HZ_DSC3_1\\ini.c", + "ToolTip": "D:\\__work\\__2025\\Los angeles\\IC_Phase\\09_workspace\\cob_16pm\\ip_16pm_6.8inch_edp_to_mipi_20251127\\src\\code\\project_case\\RM692H5_120HZ_DSC3_1\\ini.c", + "RelativeToolTip": "code\\project_case\\RM692H5_120HZ_DSC3_1\\ini.c", + "ViewState": "AgIAAMcAAAAAAAAAAAAAAN0AAAAeAAAAAAAAAA==", + "Icon": "ae27a6b0-e345-4288-96df-5eaf394ee369.000423|", + "WhenOpened": "2025-12-04T08:25:10.142Z", + "EditorCaption": "" + } + ] + } + ] + } + ] +} \ No newline at end of file diff --git a/src/.vs/src/v17/ipch/AutoPCH/15f5abd7c76c37b4/PERIP_TEST.ipch b/src/.vs/src/v17/ipch/AutoPCH/15f5abd7c76c37b4/PERIP_TEST.ipch new file mode 100644 index 0000000..c6d8e80 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/15f5abd7c76c37b4/PERIP_TEST.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/166b271f456873fc/PERIP_TEST.ipch b/src/.vs/src/v17/ipch/AutoPCH/166b271f456873fc/PERIP_TEST.ipch new file mode 100644 index 0000000..5abd6f4 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/166b271f456873fc/PERIP_TEST.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/18a377d5f605e5d6/DPRX.ipch b/src/.vs/src/v17/ipch/AutoPCH/18a377d5f605e5d6/DPRX.ipch new file mode 100644 index 0000000..2ca5889 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/18a377d5f605e5d6/DPRX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/199c7f4ff9e3713a/DPRX.ipch b/src/.vs/src/v17/ipch/AutoPCH/199c7f4ff9e3713a/DPRX.ipch new file mode 100644 index 0000000..d8066a1 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/199c7f4ff9e3713a/DPRX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/1d630794a966939d/SUB_I2C.ipch b/src/.vs/src/v17/ipch/AutoPCH/1d630794a966939d/SUB_I2C.ipch new file mode 100644 index 0000000..bc5d322 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/1d630794a966939d/SUB_I2C.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/297312fefb032eca/INI.ipch b/src/.vs/src/v17/ipch/AutoPCH/297312fefb032eca/INI.ipch new file mode 100644 index 0000000..5874c1d Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/297312fefb032eca/INI.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/29d0bab62d0c4840/DPRX.ipch b/src/.vs/src/v17/ipch/AutoPCH/29d0bab62d0c4840/DPRX.ipch new file mode 100644 index 0000000..e16aadb Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/29d0bab62d0c4840/DPRX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/2c95a5943c49eb7e/COMMON.ipch b/src/.vs/src/v17/ipch/AutoPCH/2c95a5943c49eb7e/COMMON.ipch new file mode 100644 index 0000000..65fb08b Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/2c95a5943c49eb7e/COMMON.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/2ca641a060f5e0e2/ISR.ipch b/src/.vs/src/v17/ipch/AutoPCH/2ca641a060f5e0e2/ISR.ipch new file mode 100644 index 0000000..845f404 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/2ca641a060f5e0e2/ISR.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/2cad5bcd7c8ed356/LA_TIMER.ipch b/src/.vs/src/v17/ipch/AutoPCH/2cad5bcd7c8ed356/LA_TIMER.ipch new file mode 100644 index 0000000..16b289b Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/2cad5bcd7c8ed356/LA_TIMER.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/3163962336d0b33c/PMIC_SOFT_I2C.ipch b/src/.vs/src/v17/ipch/AutoPCH/3163962336d0b33c/PMIC_SOFT_I2C.ipch new file mode 100644 index 0000000..338708e Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/3163962336d0b33c/PMIC_SOFT_I2C.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/31a111f084ad867d/LA_DPRX.ipch b/src/.vs/src/v17/ipch/AutoPCH/31a111f084ad867d/LA_DPRX.ipch new file mode 100644 index 0000000..4f1188b Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/31a111f084ad867d/LA_DPRX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/31d5031a6b6d4293/EE_PRINTF.ipch b/src/.vs/src/v17/ipch/AutoPCH/31d5031a6b6d4293/EE_PRINTF.ipch new file mode 100644 index 0000000..8ece0c6 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/31d5031a6b6d4293/EE_PRINTF.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/338d63d812b5e846/MIPI_TX.ipch b/src/.vs/src/v17/ipch/AutoPCH/338d63d812b5e846/MIPI_TX.ipch new file mode 100644 index 0000000..d92a14f Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/338d63d812b5e846/MIPI_TX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/33ab808867e32c0e/INI.ipch b/src/.vs/src/v17/ipch/AutoPCH/33ab808867e32c0e/INI.ipch new file mode 100644 index 0000000..ead5c99 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/33ab808867e32c0e/INI.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/3578029294045995/LA_I2C.ipch b/src/.vs/src/v17/ipch/AutoPCH/3578029294045995/LA_I2C.ipch new file mode 100644 index 0000000..8cebd1d Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/3578029294045995/LA_I2C.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/3720e8d882b781e/INI.ipch b/src/.vs/src/v17/ipch/AutoPCH/3720e8d882b781e/INI.ipch new file mode 100644 index 0000000..8f4e826 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/3720e8d882b781e/INI.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/3ad2ccf9939753e6/CORE_MAIN.ipch b/src/.vs/src/v17/ipch/AutoPCH/3ad2ccf9939753e6/CORE_MAIN.ipch new file mode 100644 index 0000000..67eae20 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/3ad2ccf9939753e6/CORE_MAIN.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/3fe4c33f1ed0d5ca/ULOG.ipch b/src/.vs/src/v17/ipch/AutoPCH/3fe4c33f1ed0d5ca/ULOG.ipch new file mode 100644 index 0000000..196d464 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/3fe4c33f1ed0d5ca/ULOG.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/41021983556799c8/INI.ipch b/src/.vs/src/v17/ipch/AutoPCH/41021983556799c8/INI.ipch new file mode 100644 index 0000000..ae1f090 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/41021983556799c8/INI.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/46f504d50b7ae79e/INI.ipch b/src/.vs/src/v17/ipch/AutoPCH/46f504d50b7ae79e/INI.ipch new file mode 100644 index 0000000..72db6d0 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/46f504d50b7ae79e/INI.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/4bcf0716b44beb75/LA_DPRX.ipch b/src/.vs/src/v17/ipch/AutoPCH/4bcf0716b44beb75/LA_DPRX.ipch new file mode 100644 index 0000000..e967e2b Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/4bcf0716b44beb75/LA_DPRX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/580315b9f749eaae/MIPI_TX.ipch b/src/.vs/src/v17/ipch/AutoPCH/580315b9f749eaae/MIPI_TX.ipch new file mode 100644 index 0000000..6efa780 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/580315b9f749eaae/MIPI_TX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/587b07d4cbeed8af/LA_I2C.ipch b/src/.vs/src/v17/ipch/AutoPCH/587b07d4cbeed8af/LA_I2C.ipch new file mode 100644 index 0000000..ab7163f Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/587b07d4cbeed8af/LA_I2C.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/58b50db65876b507/LA_SPI.ipch b/src/.vs/src/v17/ipch/AutoPCH/58b50db65876b507/LA_SPI.ipch new file mode 100644 index 0000000..04de523 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/58b50db65876b507/LA_SPI.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/5d1fb96c8f51fab1/LA_UART.ipch b/src/.vs/src/v17/ipch/AutoPCH/5d1fb96c8f51fab1/LA_UART.ipch new file mode 100644 index 0000000..7367844 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/5d1fb96c8f51fab1/LA_UART.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/5e463a72005f8260/LA_GPIO.ipch b/src/.vs/src/v17/ipch/AutoPCH/5e463a72005f8260/LA_GPIO.ipch new file mode 100644 index 0000000..20d1a34 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/5e463a72005f8260/LA_GPIO.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/5f91d4c487b9090e/ISR.ipch b/src/.vs/src/v17/ipch/AutoPCH/5f91d4c487b9090e/ISR.ipch new file mode 100644 index 0000000..a4d83a8 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/5f91d4c487b9090e/ISR.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/637a697826673bf6/LA_GPIO.ipch b/src/.vs/src/v17/ipch/AutoPCH/637a697826673bf6/LA_GPIO.ipch new file mode 100644 index 0000000..f54a13f Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/637a697826673bf6/LA_GPIO.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/683bb8335a374ff4/INI.ipch b/src/.vs/src/v17/ipch/AutoPCH/683bb8335a374ff4/INI.ipch new file mode 100644 index 0000000..4b34732 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/683bb8335a374ff4/INI.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/6c40c4c5b42603b5/IT.ipch b/src/.vs/src/v17/ipch/AutoPCH/6c40c4c5b42603b5/IT.ipch new file mode 100644 index 0000000..ea3a8d9 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/6c40c4c5b42603b5/IT.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/6d78f1edaf49072b/LA_DPRX.ipch b/src/.vs/src/v17/ipch/AutoPCH/6d78f1edaf49072b/LA_DPRX.ipch new file mode 100644 index 0000000..3956244 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/6d78f1edaf49072b/LA_DPRX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/76153f5f6f14b2b3/MIPI_TX.ipch b/src/.vs/src/v17/ipch/AutoPCH/76153f5f6f14b2b3/MIPI_TX.ipch new file mode 100644 index 0000000..a5f1a92 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/76153f5f6f14b2b3/MIPI_TX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/77b3dd6608f4df60/SUB_I2C.ipch b/src/.vs/src/v17/ipch/AutoPCH/77b3dd6608f4df60/SUB_I2C.ipch new file mode 100644 index 0000000..fe5effb Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/77b3dd6608f4df60/SUB_I2C.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/7977ea246311d886/CORE_MAIN.ipch b/src/.vs/src/v17/ipch/AutoPCH/7977ea246311d886/CORE_MAIN.ipch new file mode 100644 index 0000000..c95a8e9 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/7977ea246311d886/CORE_MAIN.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/7de276f9bcd0945b/LA_UART.ipch b/src/.vs/src/v17/ipch/AutoPCH/7de276f9bcd0945b/LA_UART.ipch new file mode 100644 index 0000000..da19a0f Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/7de276f9bcd0945b/LA_UART.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/7e5a86181232c4dd/SOFT_I2C.ipch b/src/.vs/src/v17/ipch/AutoPCH/7e5a86181232c4dd/SOFT_I2C.ipch new file mode 100644 index 0000000..a25ff41 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/7e5a86181232c4dd/SOFT_I2C.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/7f177cee05f58992/CORE_MAIN.ipch b/src/.vs/src/v17/ipch/AutoPCH/7f177cee05f58992/CORE_MAIN.ipch new file mode 100644 index 0000000..c794cbe Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/7f177cee05f58992/CORE_MAIN.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/83e7b0d3288a62ca/INI.ipch b/src/.vs/src/v17/ipch/AutoPCH/83e7b0d3288a62ca/INI.ipch new file mode 100644 index 0000000..d4cff31 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/83e7b0d3288a62ca/INI.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/85d90148a1c66143/LA_UART.ipch b/src/.vs/src/v17/ipch/AutoPCH/85d90148a1c66143/LA_UART.ipch new file mode 100644 index 0000000..3c9adff Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/85d90148a1c66143/LA_UART.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/862675dc53b40fbf/IT.ipch b/src/.vs/src/v17/ipch/AutoPCH/862675dc53b40fbf/IT.ipch new file mode 100644 index 0000000..9089b93 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/862675dc53b40fbf/IT.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/871adf748e7d14e2/ISR.ipch b/src/.vs/src/v17/ipch/AutoPCH/871adf748e7d14e2/ISR.ipch new file mode 100644 index 0000000..1be7084 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/871adf748e7d14e2/ISR.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/8777db644e099ca4/LA_GPIO.ipch b/src/.vs/src/v17/ipch/AutoPCH/8777db644e099ca4/LA_GPIO.ipch new file mode 100644 index 0000000..d8eb926 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/8777db644e099ca4/LA_GPIO.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/8805685b78ee4958/ISR.ipch b/src/.vs/src/v17/ipch/AutoPCH/8805685b78ee4958/ISR.ipch new file mode 100644 index 0000000..7e1082a Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/8805685b78ee4958/ISR.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/8954c369ed0a1274/CORE_MAIN.ipch b/src/.vs/src/v17/ipch/AutoPCH/8954c369ed0a1274/CORE_MAIN.ipch new file mode 100644 index 0000000..52c8f27 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/8954c369ed0a1274/CORE_MAIN.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/8cb02b0b6528298e/CORE_MAIN.ipch b/src/.vs/src/v17/ipch/AutoPCH/8cb02b0b6528298e/CORE_MAIN.ipch new file mode 100644 index 0000000..89d512f Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/8cb02b0b6528298e/CORE_MAIN.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/8dbfd2c26d658a40/PERIP_TEST.ipch b/src/.vs/src/v17/ipch/AutoPCH/8dbfd2c26d658a40/PERIP_TEST.ipch new file mode 100644 index 0000000..66d75a2 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/8dbfd2c26d658a40/PERIP_TEST.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/8ecc4f5b5e8712d1/IT.ipch b/src/.vs/src/v17/ipch/AutoPCH/8ecc4f5b5e8712d1/IT.ipch new file mode 100644 index 0000000..773c984 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/8ecc4f5b5e8712d1/IT.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/920e044a0fb83d03/ISR.ipch b/src/.vs/src/v17/ipch/AutoPCH/920e044a0fb83d03/ISR.ipch new file mode 100644 index 0000000..ec8f8ba Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/920e044a0fb83d03/ISR.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/953462a963a8b0d5/LA_SPI.ipch b/src/.vs/src/v17/ipch/AutoPCH/953462a963a8b0d5/LA_SPI.ipch new file mode 100644 index 0000000..04dab06 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/953462a963a8b0d5/LA_SPI.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/9a2f6e35d7ea8127/IT.ipch b/src/.vs/src/v17/ipch/AutoPCH/9a2f6e35d7ea8127/IT.ipch new file mode 100644 index 0000000..fa47e9f Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/9a2f6e35d7ea8127/IT.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/9ad885174a98d01c/DPRX.ipch b/src/.vs/src/v17/ipch/AutoPCH/9ad885174a98d01c/DPRX.ipch new file mode 100644 index 0000000..987cef0 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/9ad885174a98d01c/DPRX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/9fccc830bb5c341c/LA_GPIO.ipch b/src/.vs/src/v17/ipch/AutoPCH/9fccc830bb5c341c/LA_GPIO.ipch new file mode 100644 index 0000000..f49605b Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/9fccc830bb5c341c/LA_GPIO.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/a00c760cf3760b8e/LA_TIMER.ipch b/src/.vs/src/v17/ipch/AutoPCH/a00c760cf3760b8e/LA_TIMER.ipch new file mode 100644 index 0000000..b5aa60d Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/a00c760cf3760b8e/LA_TIMER.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/a1d0809b6a93469c/DPRX.ipch b/src/.vs/src/v17/ipch/AutoPCH/a1d0809b6a93469c/DPRX.ipch new file mode 100644 index 0000000..f655c64 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/a1d0809b6a93469c/DPRX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/a248219e796605c0/LA_TIMER.ipch b/src/.vs/src/v17/ipch/AutoPCH/a248219e796605c0/LA_TIMER.ipch new file mode 100644 index 0000000..c77b9d9 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/a248219e796605c0/LA_TIMER.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/a517c872b7e73a4a/CORE_MAIN.ipch b/src/.vs/src/v17/ipch/AutoPCH/a517c872b7e73a4a/CORE_MAIN.ipch new file mode 100644 index 0000000..621c2fb Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/a517c872b7e73a4a/CORE_MAIN.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/a63256e2706a4080/LA_GPIO.ipch b/src/.vs/src/v17/ipch/AutoPCH/a63256e2706a4080/LA_GPIO.ipch new file mode 100644 index 0000000..6ad9c28 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/a63256e2706a4080/LA_GPIO.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/aafb8f4f772763a/MIPI_TX.ipch b/src/.vs/src/v17/ipch/AutoPCH/aafb8f4f772763a/MIPI_TX.ipch new file mode 100644 index 0000000..090a3ee Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/aafb8f4f772763a/MIPI_TX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/ac13f3948f9dc1c6/SUB_I2C.ipch b/src/.vs/src/v17/ipch/AutoPCH/ac13f3948f9dc1c6/SUB_I2C.ipch new file mode 100644 index 0000000..9ced9b3 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/ac13f3948f9dc1c6/SUB_I2C.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/afd62f53055e8320/PERIP_TEST.ipch b/src/.vs/src/v17/ipch/AutoPCH/afd62f53055e8320/PERIP_TEST.ipch new file mode 100644 index 0000000..a21f269 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/afd62f53055e8320/PERIP_TEST.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/b14ea79f8ad58165/PMIC.ipch b/src/.vs/src/v17/ipch/AutoPCH/b14ea79f8ad58165/PMIC.ipch new file mode 100644 index 0000000..86b6a7a Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/b14ea79f8ad58165/PMIC.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/b1fa4a0c33811f8a/LA_IT.ipch b/src/.vs/src/v17/ipch/AutoPCH/b1fa4a0c33811f8a/LA_IT.ipch new file mode 100644 index 0000000..dea83af Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/b1fa4a0c33811f8a/LA_IT.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/b27ec4eeb142eb3c/INI.ipch b/src/.vs/src/v17/ipch/AutoPCH/b27ec4eeb142eb3c/INI.ipch new file mode 100644 index 0000000..15add0b Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/b27ec4eeb142eb3c/INI.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/b280ff688988681e/MIPI_TX.ipch b/src/.vs/src/v17/ipch/AutoPCH/b280ff688988681e/MIPI_TX.ipch new file mode 100644 index 0000000..38267fa Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/b280ff688988681e/MIPI_TX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/b3977ee3f642d6d/POWER_SEQ.ipch b/src/.vs/src/v17/ipch/AutoPCH/b3977ee3f642d6d/POWER_SEQ.ipch new file mode 100644 index 0000000..b2ff994 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/b3977ee3f642d6d/POWER_SEQ.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/b52813613a80f2ac/LA_GPIO.ipch b/src/.vs/src/v17/ipch/AutoPCH/b52813613a80f2ac/LA_GPIO.ipch new file mode 100644 index 0000000..c6cc50b Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/b52813613a80f2ac/LA_GPIO.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/bf1c38fe4fca6b4a/DPRX.ipch b/src/.vs/src/v17/ipch/AutoPCH/bf1c38fe4fca6b4a/DPRX.ipch new file mode 100644 index 0000000..52c9130 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/bf1c38fe4fca6b4a/DPRX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/c003e939330be692/INI.ipch b/src/.vs/src/v17/ipch/AutoPCH/c003e939330be692/INI.ipch new file mode 100644 index 0000000..c041736 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/c003e939330be692/INI.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/c1555b1e2c124eba/MIPI_TX.ipch b/src/.vs/src/v17/ipch/AutoPCH/c1555b1e2c124eba/MIPI_TX.ipch new file mode 100644 index 0000000..5d92e57 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/c1555b1e2c124eba/MIPI_TX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/c4e667c50c2ad7cc/ISR.ipch b/src/.vs/src/v17/ipch/AutoPCH/c4e667c50c2ad7cc/ISR.ipch new file mode 100644 index 0000000..5279137 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/c4e667c50c2ad7cc/ISR.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/c4f72ee649ec0535/LA_DMA.ipch b/src/.vs/src/v17/ipch/AutoPCH/c4f72ee649ec0535/LA_DMA.ipch new file mode 100644 index 0000000..df32dd1 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/c4f72ee649ec0535/LA_DMA.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/c6152f22d6839d10/COMMON.ipch b/src/.vs/src/v17/ipch/AutoPCH/c6152f22d6839d10/COMMON.ipch new file mode 100644 index 0000000..5ace3f8 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/c6152f22d6839d10/COMMON.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/c7cc7d6ab30e5b7e/MIPI_TX.ipch b/src/.vs/src/v17/ipch/AutoPCH/c7cc7d6ab30e5b7e/MIPI_TX.ipch new file mode 100644 index 0000000..ab4c02b Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/c7cc7d6ab30e5b7e/MIPI_TX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/ce49ea9fa0fdcc4c/LA_IT.ipch b/src/.vs/src/v17/ipch/AutoPCH/ce49ea9fa0fdcc4c/LA_IT.ipch new file mode 100644 index 0000000..4838914 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/ce49ea9fa0fdcc4c/LA_IT.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/d0287e2554e3078/DPRX.ipch b/src/.vs/src/v17/ipch/AutoPCH/d0287e2554e3078/DPRX.ipch new file mode 100644 index 0000000..8ff5f37 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/d0287e2554e3078/DPRX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/d120d1b0eeed30c2/PERIP_TEST.ipch b/src/.vs/src/v17/ipch/AutoPCH/d120d1b0eeed30c2/PERIP_TEST.ipch new file mode 100644 index 0000000..a93b82f Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/d120d1b0eeed30c2/PERIP_TEST.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/d252f1c722c98a54/IR_INIT.ipch b/src/.vs/src/v17/ipch/AutoPCH/d252f1c722c98a54/IR_INIT.ipch new file mode 100644 index 0000000..2cb0cca Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/d252f1c722c98a54/IR_INIT.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/d73b6b083c7bf203/LA_DMA.ipch b/src/.vs/src/v17/ipch/AutoPCH/d73b6b083c7bf203/LA_DMA.ipch new file mode 100644 index 0000000..e94c5a0 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/d73b6b083c7bf203/LA_DMA.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/dd3a14e5a2ed915a/COMMON.ipch b/src/.vs/src/v17/ipch/AutoPCH/dd3a14e5a2ed915a/COMMON.ipch new file mode 100644 index 0000000..a997162 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/dd3a14e5a2ed915a/COMMON.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/dd4e6e246181f9fc/CORE_MAIN.ipch b/src/.vs/src/v17/ipch/AutoPCH/dd4e6e246181f9fc/CORE_MAIN.ipch new file mode 100644 index 0000000..baa36e7 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/dd4e6e246181f9fc/CORE_MAIN.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/de2f8e1c4eeb387a/ISR.ipch b/src/.vs/src/v17/ipch/AutoPCH/de2f8e1c4eeb387a/ISR.ipch new file mode 100644 index 0000000..d2244d2 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/de2f8e1c4eeb387a/ISR.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/e2ad1cd78ab560fa/LA_IT.ipch b/src/.vs/src/v17/ipch/AutoPCH/e2ad1cd78ab560fa/LA_IT.ipch new file mode 100644 index 0000000..214cf07 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/e2ad1cd78ab560fa/LA_IT.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/e2d40e2d0c243f23/IT.ipch b/src/.vs/src/v17/ipch/AutoPCH/e2d40e2d0c243f23/IT.ipch new file mode 100644 index 0000000..2261995 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/e2d40e2d0c243f23/IT.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/e2d955a91c36acd8/INI.ipch b/src/.vs/src/v17/ipch/AutoPCH/e2d955a91c36acd8/INI.ipch new file mode 100644 index 0000000..e254318 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/e2d955a91c36acd8/INI.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/eaefb3734e1b3d0b/INI.ipch b/src/.vs/src/v17/ipch/AutoPCH/eaefb3734e1b3d0b/INI.ipch new file mode 100644 index 0000000..562cca0 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/eaefb3734e1b3d0b/INI.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/ee748b2cd04eec40/DPRX.ipch b/src/.vs/src/v17/ipch/AutoPCH/ee748b2cd04eec40/DPRX.ipch new file mode 100644 index 0000000..ec0b79b Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/ee748b2cd04eec40/DPRX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/ee7d13922cbd50d3/DPRX.ipch b/src/.vs/src/v17/ipch/AutoPCH/ee7d13922cbd50d3/DPRX.ipch new file mode 100644 index 0000000..d584c7d Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/ee7d13922cbd50d3/DPRX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/eeff66edd6ff7b20/SOFT_I2C.ipch b/src/.vs/src/v17/ipch/AutoPCH/eeff66edd6ff7b20/SOFT_I2C.ipch new file mode 100644 index 0000000..90b6ffd Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/eeff66edd6ff7b20/SOFT_I2C.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/f2013470586223a4/MIPI_TX.ipch b/src/.vs/src/v17/ipch/AutoPCH/f2013470586223a4/MIPI_TX.ipch new file mode 100644 index 0000000..5e6b6e9 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/f2013470586223a4/MIPI_TX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/f4b3be58b849284c/PERIP_TEST.ipch b/src/.vs/src/v17/ipch/AutoPCH/f4b3be58b849284c/PERIP_TEST.ipch new file mode 100644 index 0000000..07c2fe6 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/f4b3be58b849284c/PERIP_TEST.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/f599553746bbaaa7/LA_I2C.ipch b/src/.vs/src/v17/ipch/AutoPCH/f599553746bbaaa7/LA_I2C.ipch new file mode 100644 index 0000000..87a98c4 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/f599553746bbaaa7/LA_I2C.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/f717bb540de589ba/IT.ipch b/src/.vs/src/v17/ipch/AutoPCH/f717bb540de589ba/IT.ipch new file mode 100644 index 0000000..5ed216b Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/f717bb540de589ba/IT.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/f76cf5884d9aa442/CORE_MAIN.ipch b/src/.vs/src/v17/ipch/AutoPCH/f76cf5884d9aa442/CORE_MAIN.ipch new file mode 100644 index 0000000..e5a0149 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/f76cf5884d9aa442/CORE_MAIN.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/f79ccb70539c356b/LA_WDG.ipch b/src/.vs/src/v17/ipch/AutoPCH/f79ccb70539c356b/LA_WDG.ipch new file mode 100644 index 0000000..24bbba0 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/f79ccb70539c356b/LA_WDG.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/f80e3dcbcdb761eb/LA_UART.ipch b/src/.vs/src/v17/ipch/AutoPCH/f80e3dcbcdb761eb/LA_UART.ipch new file mode 100644 index 0000000..6c0e539 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/f80e3dcbcdb761eb/LA_UART.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/f8e5475a6d3694aa/ISR.ipch b/src/.vs/src/v17/ipch/AutoPCH/f8e5475a6d3694aa/ISR.ipch new file mode 100644 index 0000000..66d85e8 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/f8e5475a6d3694aa/ISR.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/fb7a80c9d8c6e546/MIPI_TX.ipch b/src/.vs/src/v17/ipch/AutoPCH/fb7a80c9d8c6e546/MIPI_TX.ipch new file mode 100644 index 0000000..6a6584b Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/fb7a80c9d8c6e546/MIPI_TX.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/fbf5b3c59eeab1ae/COMMON.ipch b/src/.vs/src/v17/ipch/AutoPCH/fbf5b3c59eeab1ae/COMMON.ipch new file mode 100644 index 0000000..f95945d Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/fbf5b3c59eeab1ae/COMMON.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/fcd8cff0da528544/LA_SYS.ipch b/src/.vs/src/v17/ipch/AutoPCH/fcd8cff0da528544/LA_SYS.ipch new file mode 100644 index 0000000..b501525 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/fcd8cff0da528544/LA_SYS.ipch differ diff --git a/src/.vs/src/v17/ipch/AutoPCH/fe257979eece48b2/LA_IT.ipch b/src/.vs/src/v17/ipch/AutoPCH/fe257979eece48b2/LA_IT.ipch new file mode 100644 index 0000000..ad4f310 Binary files /dev/null and b/src/.vs/src/v17/ipch/AutoPCH/fe257979eece48b2/LA_IT.ipch differ diff --git a/src/code/a_set_project_case.cc b/src/code/a_set_project_case.cc new file mode 100644 index 0000000..ff189aa --- /dev/null +++ b/src/code/a_set_project_case.cc @@ -0,0 +1,52 @@ +// ===== ===== ===== ===== ==== ===== ===== ===== ===== // +// ===== 机型平台选择一 ===== // +// ===== ipad11_pro_m4 ===== // +// ===== ===== // +// ===== ===== ===== ===== ==== ===== ===== ===== ===== // +//#define ipadpro11_2420x1668_rgb_sdvc_rotation_to_1280x1840_rgb_dsc + + +// ===== ===== ===== ===== ==== ===== ===== ===== ===== // +// ===== 机型平台选择二 ===== // +// ===== ipad_mini6 ===== // +// ===== ===== // +// ===== ===== ===== ===== ==== ===== ===== ===== ===== // +//#define ap_ipadmini6_2266x1488__to__8.3inch_1132x744rgb + + + +// ===== ===== ===== ===== ==== ===== ===== ===== ===== // +// ===== 机型平台选择三 ===== // +// ===== 14promax/15promax ===== // +// ===== ===== // +// ===== ===== ===== ===== ==== ===== ===== ===== ===== // +//#define ili7807s_120hz_dsc2_1 +//#define ili7807s_120hz_dsc3_1 +#define RM692H5_120HZ_DSC3_1 + +// ===== ===== ===== ===== ==== ===== ===== ===== ===== // +// ===== 机型平台选择四 ===== // +// ===== ipad13 ===== // +// ===== ===== // +// ===== ===== ===== ===== ==== ===== ===== ===== ===== // +//#define ap_ipad13_2064x2752__to__8d3_1132x744rgb + + + +// ===== ===== ===== ===== ==== ===== ===== ===== ===== // +// ===== 机型平台选择五 ===== // +// ===== pc ===== // +// ===== ===== // +// ===== ===== ===== ===== ==== ===== ===== ===== ===== // + + + //#define test_test +// ===== ===== ===== ===== ==== ===== ===== ===== ===== // +// ===== ===== // +// ===== Test Code ===== // +// ===== ===== // +// ===== ===== ===== ===== ==== ===== ===== ===== ===== // + +// #define _SOCKET_ +// #define _SOCKET_14P_HJC61_832x1804_ILIP6F88_ +//#define pre_bist_566x372_sdvc__to__1132x744_rgb_8d3_r3785 \ No newline at end of file diff --git a/src/code/common.c b/src/code/common.c new file mode 100644 index 0000000..8cbd506 --- /dev/null +++ b/src/code/common.c @@ -0,0 +1,363 @@ +#include "la_config.h" + +//core_perip_rw +void wr_core_perip_byte(int addr, char dat) +{ + volatile char *core_perip_addr; + core_perip_addr = (volatile char *)(BASE_ADDR_CORE_PERIP + addr); + *core_perip_addr = dat; +} + +void wr_core_perip_int(int addr, int dat) +{ + int addr_mask = addr & 0xfffffffc; + volatile int *core_perip_addr; + core_perip_addr = (volatile int *)(BASE_ADDR_CORE_PERIP + addr_mask); + *core_perip_addr = dat; +} + +int rd_core_perip(int addr) +{ + int addr_mask = addr & 0xfffffffc; + volatile int *core_perip_addr; + core_perip_addr = (volatile int *)(BASE_ADDR_CORE_PERIP + addr_mask); + return(*core_perip_addr); +} + + +//ir_rw irq12 +void wr_irreg(int addr, int dat) +{ + int addr_mask = addr & 0xfffffffc; + int *cmd_addr = (int*)(BASE_ADDR_IR+addr_mask); + *cmd_addr = dat; +} + +int rd_irreg(int addr) +{ + int addr_mask = addr & 0xfffffffc; + int *cmd_addr = (int*)(BASE_ADDR_IR+addr_mask); + return(*cmd_addr); +} + +void wr_bit_irreg(int addr,char bit_loc,char bit_dat)// addr -- offset address ;bit_loc--0~31,bit location; bit_dat--0/1,ie clr/set +{ + int tmp_rd_dat=0; + tmp_rd_dat = rd_irreg(addr); + + int pro_dat=0; + int low_dat=0; + pro_dat = (bit_dat)? 0x00000001 : 0xfffffffe; + pro_dat = pro_dat << bit_loc; + low_dat = 0xffffffff >> (32-bit_loc); + low_dat = (bit_dat)? 0x00000000 : low_dat; + pro_dat = pro_dat + low_dat; + tmp_rd_dat = (bit_dat)? tmp_rd_dat| pro_dat : tmp_rd_dat & pro_dat; + wr_irreg(addr,tmp_rd_dat); +} + + +//irq13 +void wr_irreg_irq13(int addr, int dat) +{ + int addr_mask = addr & 0xfffffffc; + int* cmd_addr = (int*)(BASE_ADDR_EXTER_IR + addr_mask); + *cmd_addr = dat; +} + + +int rd_irreg_irq13(int addr) +{ + int addr_mask = addr & 0xfffffffc; + int* cmd_addr = (int*)(BASE_ADDR_EXTER_IR + addr_mask); + return(*cmd_addr); +} + + + +int rd_cfgreg(int addr) +{ + int addr_mask = addr & 0xfffffffc; + int *cmd_addr = (int*)(BASE_ADDR_CFG+addr_mask); + return(*cmd_addr); +} + +//cfgreg rw + +void wr_cfgreg(uint32 addr, uint8 dat) { + volatile uint8* reg_addr = (volatile uint8*)(BASE_ADDR_CFG + addr); + *reg_addr = dat; // ȫ8λд8λĴ +} + +//void wr_cfgreg(int addr, char dat) +//{ +// volatile char *cfgset_cmd_addr; +// cfgset_cmd_addr = (volatile char *)(BASE_ADDR_CFG + addr); +// *cfgset_cmd_addr = dat; +//} + + +//mipi_rx rw +//void wr_mipirx(int offset_addr, char dat) +//{ +// char *cmd_addr = (char*)(BASE_ADDR_MIPIRX+offset_addr); +// *cmd_addr = dat; +//} +// +//void wr_mipirx_int(int offset_addr, int dat) +//{ +// int offset_addr_mask = offset_addr & 0xfffffffc; +// int *cmd_addr = (int*)(BASE_ADDR_MIPIRX+offset_addr_mask); +// *cmd_addr = dat; +//} +// +//int rd_mipirx(int offset_addr) +//{ +// int offset_addr_mask = offset_addr & 0xfffffffc; +// int *cmd_addr = (int*)(BASE_ADDR_MIPIRX+offset_addr_mask); +// return(*cmd_addr); +//} +// + + +//spii2c + + + + + + + + +//spii2c + + + + +//dprx sdp 0x80090000 +void wr_dprx_sdp(int offset_addr, char dat) +{ + char *cmd_addr = (char*)(BASE_ADDR_DPRX_SDP+offset_addr); + *cmd_addr = dat; +} + +int rd_dprx_sdp(int offset_addr) +{ + int offset_addr_mask = offset_addr & 0xfffffffc; + int *cmd_addr = (int*)(BASE_ADDR_DPRX_SDP+offset_addr_mask); + return(*cmd_addr); +} + + + +//for gpio----------------------------------------------------------- + +int rd_gpioin00() +{ + #define UPDATE_EN1 1 + #define DIR_OE1 0 + #define OUT_VAL1 1 + #define BYTE_WR1 OUT_VAL1*4+DIR_OE1*2+UPDATE_EN1 + wr_core_perip_byte(0x0204,BYTE_WR1); + + int gpio_in; + gpio_in = rd_core_perip(0x0218); + return (gpio_in); +} + +void tiehigh_gpio00() +{ + #define UPDATE_EN2 1 + #define DIR_OE2 1 + #define OUT_VAL2 1 + #define BYTE_WR2 OUT_VAL2*4+DIR_OE2*2+UPDATE_EN2 + wr_core_perip_byte(0x0204,BYTE_WR2); +} + +void tielow_gpio00() +{ + #define UPDATE_EN3 1 + #define DIR_OE3 1 + #define OUT_VAL3 0 + #define BYTE_WR3 OUT_VAL3*4+DIR_OE3*2+UPDATE_EN3 + wr_core_perip_byte(0x0204,BYTE_WR3); +} + +void ctrl_gpio00() +{ + wr_core_perip_byte(0x0200,0xff);//enable + rd_gpioin00(); + tiehigh_gpio00(); + tielow_gpio00(); +} + + + + +void pwr_on_seq() +{ + wr_cfgreg(0xb905,0x55);//dvdd_tpvcc on, mvdd_tx on + wr_cfgreg(0xb410,0x01);//mvdd tphy on + wr_cfgreg(0xb902,0xbb); + wr_cfgreg(0xb903,0x55); +} + +void pwr_off_seq() +{ +wr_cfgreg(0xb902,0xaa); +wr_cfgreg(0xb903,0x44); +} + + + +char read_usrcmd() +{ + volatile char *cmd_addr; + int cmd; + cmd= 0x6f06; + cmd_addr = (volatile char *)(0x80080000 + cmd); + return *cmd_addr; + +} +void write_usrcmd() +{ + volatile char *cfgset_cmd_addr; + int cmd; + cmd= 0x1300; + cfgset_cmd_addr =(volatile char *)(0x80080000 + cmd); + *cfgset_cmd_addr = 0x00; +} +void i2c_master_send() +{ +} + + +//sram read write test +volatile void sram_1kb_write_read_test (void) +{ + // write data to ahb sram1k + volatile uint32 *sram_ptr = (uint32 *)0x80800000; + uint32 data = 0x12345678; + int count=10; + + for(int i=0;i + wr_cfgreg(0xF001, 0x0F); // + wr_cfgreg(0xF002, 0xF0); // + + wr_cfgreg(0xF908, 0xEF); // + + // SMT + //wr_cfgreg(0xB405, 0x9B); //----V2I + wr_cfgreg(0xB402, 0x01); //----osc���� + //SRAM LOOP + wr_cfgreg(0xBF01, 0x83); + // wr_cfgreg(0xBA28,0x44); // phy_training_mode[1:0] = 0 OR 1 + wr_cfgreg(0xBA12, 0x01); // time_window_period_25m__1[15:8] 0 + wr_cfgreg(0xBA13, 0xDB); // time_window_period_25m__0[7:0] C5 + wr_cfgreg(0xBA12, 0x01); // time_window_period_27m__1[15:8] 0 + wr_cfgreg(0xBA13, 0xDB); // time_window_period_27m__0[7:0] F0 + wr_cfgreg(0xBA24, 0x01); // cr_clk_var__0 CA + wr_cfgreg(0xBA25, 0xDB); // cr_clk_var__1 02 + +// dvdd---�垫�浠�VCI/VCC涓��戒��ㄥ���垫�锛��朵���浠�澶�渚�1.2V涓��� + wr_cfgreg(0xB102, 0x3f); // + wr_cfgreg(0xB103, 0x33); // + wr_cfgreg(0xB104, 0x73); // + wr_cfgreg(0xB109, 0x08); // + wr_cfgreg(0xB10A, 0x0A); // + + // PLL1 PLL2 PLL3 PLL4 mipi + // 180 130 200 170 1200 + wr_cfgreg(0xB000, 0x10); // + wr_cfgreg(0xB002, 0x1F); // + wr_cfgreg(0xB004, 0x14); // + wr_cfgreg(0xB005, 0x08); // + wr_cfgreg(0xB006, 0x10); // + wr_cfgreg(0xB009, 0x13); // + wr_cfgreg(0xB00A, 0x08); // + wr_cfgreg(0xB00B, 0x0B); // + wr_cfgreg(0xB00E, 0x16); // + wr_cfgreg(0xB00F, 0x08); // + wr_cfgreg(0xB010, 0x12); // + wr_cfgreg(0xB013, 0x14); // + wr_cfgreg(0xB014, 0x08); // + wr_cfgreg(0xB015, 0x0F); // + wr_cfgreg(0xB018, 0x90); // + wr_cfgreg(0xB019, 0x14); // + wr_cfgreg(0xB01A, 0x13); // + wr_cfgreg(0xB01B, 0x1C); // + wr_cfgreg(0xB01C, 0x80); // + wr_cfgreg(0xB01D, 0x00); // + + wr_cfgreg(0xB047, 0xF7); // + wr_cfgreg(0xB048, 0x89); // + wr_cfgreg(0xB049, 0xD0); // + wr_cfgreg(0xB04A, 0xCE); // + + +//---16pm + wr_cfgreg(0xBA03, 0x78); // + wr_cfgreg(0xBA04, 0x08); // + wr_cfgreg(0xBA0A, 0x03); // + wr_cfgreg(0xBA0B, 0xFE); // + wr_cfgreg(0xBA0C, 0x01); // + wr_cfgreg(0xBA0E, 0x41); // + wr_cfgreg(0xBA0F, 0x00); // + wr_cfgreg(0xBA10, 0x00); // time_window_period_25m__1[15:8] 0 + wr_cfgreg(0xBA11, 0xEB); // time_window_period_25m__0[7:0] C5 + wr_cfgreg(0xBA12, 0x00); // time_window_period_27m__1[15:8] 0 + wr_cfgreg(0xBA13, 0xFF); // time_window_period_27m__0[7:0] F0 + wr_cfgreg(0xBA24, 0xD7); // cr_clk_var__0 CA + wr_cfgreg(0xBA25, 0x12); // cr_clk_var__1 02 + wr_cfgreg(0xBA28, 0x44); // + wr_cfgreg(0xBA29, 0x45); // + +//pre-proch + wr_cfgreg(0xE800, 0x0c); // + wr_cfgreg(0xE801, 0x01); // + wr_cfgreg(0xE802, 0x05); // + wr_cfgreg(0xE803, 0x28); // + wr_cfgreg(0xE804, 0x00); // + wr_cfgreg(0xE805, 0x9f); // + wr_cfgreg(0xE806, 0x00); // + wr_cfgreg(0xE807, 0x29); // + wr_cfgreg(0xE808, 0x0B); // + wr_cfgreg(0xE809, 0x34); // + wr_cfgreg(0xE80A, 0x00); // + wr_cfgreg(0xE80B, 0x33); // + wr_cfgreg(0xE80C, 0x00); // + wr_cfgreg(0xE80D, 0xC3); // + + //frambuff-porch + + wr_cfgreg(0xE81C,0x05); // + wr_cfgreg(0xE81D,0x28); // + wr_cfgreg(0xE81E,0x0B); // + wr_cfgreg(0xE81F,0x34); // + wr_cfgreg(0xE820,0x00); // + wr_cfgreg(0xE821,0x48); // + wr_cfgreg(0xE822,0x00); // + wr_cfgreg(0xE823,0x0A); // + wr_cfgreg(0xE824,0x00); // + wr_cfgreg(0xE825,0x60); // + wr_cfgreg(0xE826,0x00); // + wr_cfgreg(0xE827,0x20); // + wr_cfgreg(0xE828,0x02); // + wr_cfgreg(0xE829,0x14); // +//--scaler-porch + wr_cfgreg(0xE80E,0x05); // + wr_cfgreg(0xE80F,0x00); // + wr_cfgreg(0xE810,0x0A); // + wr_cfgreg(0xE811,0xF0); // + wr_cfgreg(0xE812,0x14); // + wr_cfgreg(0xE813,0x00); // + wr_cfgreg(0xE814,0x20); // + wr_cfgreg(0xE815,0x00); // + wr_cfgreg(0xE816,0xA8); // + wr_cfgreg(0xE817,0x02); // + wr_cfgreg(0xE818,0x00); // + wr_cfgreg(0xE819,0x0A); // + wr_cfgreg(0xE81A,0x00); // + wr_cfgreg(0xE81B,0x46); // + + wr_cfgreg(0xE82A, 0x05); // + wr_cfgreg(0xE82B, 0x28); // + wr_cfgreg(0xE82C, 0x0B); // + wr_cfgreg(0xE82D, 0x34); // + + wr_cfgreg(0xe82e, 0x05);//hact after pixelmap + wr_cfgreg(0xe82f, 0x00); + +//scaler: 1320*2868 --> 1280*2800 + wr_cfgreg(0xC01D,0xF7); // + wr_cfgreg(0xC01E,0x42); // + wr_cfgreg(0xC01F,0x00); // + wr_cfgreg(0xC020,0x25); // + wr_cfgreg(0xC021,0x01); // + wr_cfgreg(0xC022,0x00); // + wr_cfgreg(0xC023,0x00); // + wr_cfgreg(0xC024,0x4D); // + wr_cfgreg(0xC025,0x07); // + wr_cfgreg(0xC026,0x00); // + wr_cfgreg(0xC027,0x00); // + wr_cfgreg(0xC028,0x00); // + wr_cfgreg(0xC029,0x84); // + wr_cfgreg(0xC02A,0x1B); // + wr_cfgreg(0xC02B,0x83); // + wr_cfgreg(0xC02C,0x00); // + wr_cfgreg(0xC02D,0x21); // + wr_cfgreg(0xC02E,0x21); // + wr_cfgreg(0xC02F,0x02); // + wr_cfgreg(0xC030,0x00); // + wr_cfgreg(0xC031,0x80); // + wr_cfgreg(0xC032,0x80); // + wr_cfgreg(0xC033,0x6F); // + wr_cfgreg(0xC034,0x01); // + wr_cfgreg(0xC035,0x00); // + wr_cfgreg(0xC036,0x00); // + + + + // 1320RGBG -- scaler -- 1280RGB(RGBG2RGB) -- dscenc(3:1 2slice) -- TX(A4) + // datapath + wr_cfgreg(0xE000, 0x51); // 0 + // 1 + // 0 + // 1 + // 0 + // 1 + // 0 + // 1 + + wr_cfgreg(0xE001, 0x7f); // 0 + // 1 + // 1 + // 1 + // 1 + // 1 + // 1 + // 1 + + wr_cfgreg(0xE002, 0x5b); // 0 + // 1 + // 0 + // 1 + // 1 + // 0 + // 1 + // 1 + wr_cfgreg(0xE003, 0x80); // 1 + // 0 + // 0 + // 0 + // 00 + // 0 + // 0 + +//mipitx delay + wr_cfgreg(0xBB19, 0x00); // + wr_cfgreg(0xBB1A, 0xB0); // + wr_cfgreg(0xBB03, 0x32); // + wr_cfgreg(0xBB1B, 0xA4); /*:rgbg=24 rgb= 94 dsc=a4 + + + + */ + +//fb_tegn + wr_cfgreg(0xE300, 0x0A); // + +//sdvc: 0x43����RGB,0x47_RGBG + wr_cfgreg(0xC900, 0x47); // + + // dsc + // dscenc config + wr_cfgreg(0xD100, 0x16); /* 0x16 + + + + 0: 1 slice, 1 : 2 slices ,�规��PPS�ヨ�惧�� + + */ + wr_cfgreg(0xD101, 0x00); // + wr_cfgreg(0xD102, 0x00); // + wr_cfgreg(0xD103, 0xC0); // + wr_cfgreg(0xD104, 0x00); // + wr_cfgreg(0xD105, 0x30); // + wr_cfgreg(0xD106, 0x0C); // + wr_cfgreg(0xD107, 0x0A); // + + //pps 6.8 dsc1:3 + wr_cfgreg(0xD000, 0x11); // 11 + wr_cfgreg(0xD001, 0x00); // 00 + wr_cfgreg(0xD002, 0x00); // 00 + wr_cfgreg(0xD003, 0x89); // 89 + wr_cfgreg(0xD004, 0x30); // 30 + wr_cfgreg(0xD005, 0x80); // c0 + wr_cfgreg(0xD006, 0x0a); // 0a --pic height:2800 + wr_cfgreg(0xD007, 0xf0); // ec + wr_cfgreg(0xD008, 0x05); // 04 --pic width:1280 + wr_cfgreg(0xD009, 0x00); // 38 + wr_cfgreg(0xD00A, 0x00); // 00 + wr_cfgreg(0xD00B, 0x14); // 0c --slice heigh:20 + wr_cfgreg(0xD00C, 0x02); // 04 --slice: 2 slice + wr_cfgreg(0xD00D, 0x80); // 38 + wr_cfgreg(0xD00E, 0x02); // 06 + wr_cfgreg(0xD00F, 0x80); // 54 + wr_cfgreg(0xD010, 0x02); // 01 + wr_cfgreg(0xD011, 0x00); // 55 + wr_cfgreg(0xD012, 0x02); // 03 + wr_cfgreg(0xD013, 0x41); // c2 + wr_cfgreg(0xD014, 0x00); // 00 + wr_cfgreg(0xD015, 0x20); // 0a + wr_cfgreg(0xD016, 0x02); // 00 + wr_cfgreg(0xD017, 0x12); // be + wr_cfgreg(0xD018, 0x00); // 00 + wr_cfgreg(0xD019, 0x08); // b4 + wr_cfgreg(0xD01A, 0x00); // 00 + wr_cfgreg(0xD01B, 0x0c); // 0f + wr_cfgreg(0xD01C, 0x05); // 0a + wr_cfgreg(0xD01D, 0x0e); // e9 + wr_cfgreg(0xD01E, 0x04); // 0b + wr_cfgreg(0xD01F, 0x38); // d3 + wr_cfgreg(0xD020, 0x18); // 08 + wr_cfgreg(0xD021, 0x00); // 00 + wr_cfgreg(0xD022, 0x10); // 10 + wr_cfgreg(0xD023, 0xd0); // f4 + wr_cfgreg(0xD024, 0x03); // 03 + wr_cfgreg(0xD025, 0x0c); // 0c + wr_cfgreg(0xD026, 0x20); // 20 + wr_cfgreg(0xD027, 0x00); // 00 + wr_cfgreg(0xD028, 0x06); // 06 + wr_cfgreg(0xD029, 0x0b); // 0b + wr_cfgreg(0xD02A, 0x0b); // 0b + wr_cfgreg(0xD02B, 0x33); // 33 + wr_cfgreg(0xD02C, 0x0e); // 0e + wr_cfgreg(0xD02D, 0x1c); // 1c + wr_cfgreg(0xD02E, 0x2a); // 2a + wr_cfgreg(0xD02F, 0x38); // 38 + wr_cfgreg(0xD030, 0x46); // 46 + wr_cfgreg(0xD031, 0x54); // 54 + wr_cfgreg(0xD032, 0x62); // 62 + wr_cfgreg(0xD033, 0x69); // 69 + wr_cfgreg(0xD034, 0x70); // 70 + wr_cfgreg(0xD035, 0x77); // 77 + wr_cfgreg(0xD036, 0x79); // 79 + wr_cfgreg(0xD037, 0x7b); // 7b + wr_cfgreg(0xD038, 0x7d); // 7d + wr_cfgreg(0xD039, 0x7e); // 7e + wr_cfgreg(0xD03A, 0x01); // 00 + wr_cfgreg(0xD03B, 0x02); // 82 + wr_cfgreg(0xD040, 0x01); // 01 + wr_cfgreg(0xD041, 0x00); // 00 + wr_cfgreg(0xD042, 0x09); // 09 + wr_cfgreg(0xD043, 0x40); // 40 + wr_cfgreg(0xD044, 0x09); // 09 + wr_cfgreg(0xD045, 0xbe); // be + wr_cfgreg(0xD046, 0x19); // 19 + wr_cfgreg(0xD047, 0xfc); // fc + wr_cfgreg(0xD048, 0x19); // 19 + wr_cfgreg(0xD049, 0xfa); // fa + wr_cfgreg(0xD04A, 0x19); // 19 + wr_cfgreg(0xD04B, 0xf8); // f8 + wr_cfgreg(0xD04C, 0x1a); // 1a + wr_cfgreg(0xD04D, 0x38); // 38 + wr_cfgreg(0xD04E, 0x1a); // 1a + wr_cfgreg(0xD04F, 0x78); // 78 + wr_cfgreg(0xD050, 0x1a); // 1a + wr_cfgreg(0xD051, 0xb6); // b6 + wr_cfgreg(0xD052, 0x2a); // 2a + wr_cfgreg(0xD053, 0xf6); // f6 + wr_cfgreg(0xD054, 0x2b); // 2b + wr_cfgreg(0xD055, 0x34); // 34 + wr_cfgreg(0xD056, 0x2b); // 2b + wr_cfgreg(0xD057, 0x74); // 74 + wr_cfgreg(0xD058, 0x3b); // 3b + wr_cfgreg(0xD059, 0x74); // 74 + wr_cfgreg(0xD05A, 0x6b); // 6b + wr_cfgreg(0xD05B, 0xf4); // f4 + wr_cfgreg(0xD05C, 0x00); // 00 + wr_cfgreg(0xD05D, 0x00); // 00 + wr_cfgreg(0xD05E, 0x00); // 00 + wr_cfgreg(0xD05F, 0x00); // 00 + wr_cfgreg(0xD060, 0x00); // 00 + wr_cfgreg(0xD061, 0x00); // 00 + wr_cfgreg(0xD062, 0x00); // 00 + wr_cfgreg(0xD063, 0x00); // 00 + + +//---follow + //48-60-120Hz +// wr_cfgreg(0xE34F, 0x02); // +// wr_cfgreg(0xE353, 0x00); // +// wr_cfgreg(0xE354, 0x84); // +// wr_cfgreg(0xE355, 0x81); // +// wr_cfgreg(0xE356, 0x9D); // +// wr_cfgreg(0xE357, 0x83); // +// wr_cfgreg(0xE358, 0x05); // +// wr_cfgreg(0xE359, 0x05); // +// wr_cfgreg(0xE35A, 0x05); // +// wr_cfgreg(0xE35B, 0x83); // +// wr_cfgreg(0xE35C, 0x0B); // +// wr_cfgreg(0xE35D, 0x0B); // +// wr_cfgreg(0xE35E, 0x0B); // +// wr_cfgreg(0xE35F, 0x17); // +// wr_cfgreg(0xE360, 0x17); // +// wr_cfgreg(0xE361, 0x17); // +// wr_cfgreg(0xE362, 0x0B); // +// wr_cfgreg(0xE363, 0x31); // +// wr_cfgreg(0xE364, 0x63); // +// wr_cfgreg(0xE365, 0x6C); // +// wr_cfgreg(0xE366, 0x0B); // +// wr_cfgreg(0xE367, 0x20); // +// wr_cfgreg(0xE368, 0xC9); // +// wr_cfgreg(0xE369, 0x1C); // +// wr_cfgreg(0xE36A, 0x10); // +// wr_cfgreg(0xE36B, 0x49); // +// wr_cfgreg(0xE36C, 0x65); // +// wr_cfgreg(0xE36D, 0x05); // +// wr_cfgreg(0xE36E, 0x15); // +// wr_cfgreg(0xE375, 0x00); // + +//120Hz + wr_cfgreg(0xE34F,0x02); // + wr_cfgreg(0xE353,0x00); // + wr_cfgreg(0xE354,0x84); // + wr_cfgreg(0xE355,0x81); // + wr_cfgreg(0xE356,0x9D); // + wr_cfgreg(0xE357,0x83); // + wr_cfgreg(0xE358,0x83); // + wr_cfgreg(0xE359,0x83); // + wr_cfgreg(0xE35A,0x9B); // + wr_cfgreg(0xE35B,0x83); // + wr_cfgreg(0xE35C,0x0B); // + wr_cfgreg(0xE35D,0x0B); // + wr_cfgreg(0xE35E,0x0B); // + wr_cfgreg(0xE35F,0x0B); // + wr_cfgreg(0xE360,0x0B); // + wr_cfgreg(0xE361,0x0B); // + wr_cfgreg(0xE362,0x0B); // + wr_cfgreg(0xE363,0x31); // + wr_cfgreg(0xE364,0x63); // + wr_cfgreg(0xE365,0x6C); // + wr_cfgreg(0xE366,0x0B); // + wr_cfgreg(0xE367,0x00); // + wr_cfgreg(0xE368,0xC9); // + wr_cfgreg(0xE369,0x1C); // + wr_cfgreg(0xE36A,0x10); // + wr_cfgreg(0xE36B,0x49); // + wr_cfgreg(0xE36C,0x65); // + wr_cfgreg(0xE36D,0x05); // + wr_cfgreg(0xE36E,0x15); // + wr_cfgreg(0xE375,0x00); // + + //wr_cfgreg(0xF900, 0x69); + //wr_cfgreg(0xF9C1, 0x00); + wr_cfgreg(0xB907, 0xA0); //mvdd_edp_en=0.power off 不关闭mvdd_edp + +//省功耗对策 + wr_cfgreg(0xB906, 0xB0); // + wr_cfgreg(0xBB01, 0x72); // mipi txb phy close +//------grp clk:节省功耗 + wr_cfgreg(0xb047, 0xf7); // + wr_cfgreg(0xb048, 0x8B); // + wr_cfgreg(0xb049, 0x90); // + wr_cfgreg(0xb04a, 0xce); +//------- + wr_cfgreg(0xB109, 0x00); // + wr_cfgreg(0xB10A, 0x00); // + +} diff --git a/src/code/project_case/RM692H5_120HZ_DSC3_1/isr.c b/src/code/project_case/RM692H5_120HZ_DSC3_1/isr.c new file mode 100644 index 0000000..2c3a0e0 --- /dev/null +++ b/src/code/project_case/RM692H5_120HZ_DSC3_1/isr.c @@ -0,0 +1,322 @@ +#include "la_config.h" + +void ir_init() +{ + //ie_first: 0-disable 1-enable + //is_first: 0-fall edge 1-rise edge 2-low level 3-high level + //ie_second:0-disable 1-enable + //is_second:high level + //priority ie_first is_first ie_second is_second +char ir_mem_irq12[NUM_ALL_IR12][5]= {{ 0, 0, 0, 0, 0 }, //Reserve + { 39, 0, 1, 0, 1 }, //WDG + { 2, 0, 1, 0, 1 }, //GPIO0_COMBO + { 3, 0, 1, 0, 1 }, //GPIO1_COMBO + { 4, 0, 1, 0, 1 }, //GPIO2_COMBO + { 5, 0, 1, 0, 1 }, //GPIO3_COMBO + { 6, 0, 1, 0, 1 }, //GPIO4_COMBO + { 7, 0, 1, 0, 1 }, //GPIO5_COMBO + { 8, 0, 0, 0, 0 }, //GPIO6_COMBO + { 9, 0, 1, 0, 1 }, //GPIO7_COMBO + { 10, 0, 1, 0, 1 }, //GPIO8_COMBO + { 11, 0, 1, 0, 1 }, //GPIO9_COMBO + { 12, 0, 1, 0, 1 }, //GPIO_00 + { 13, 0, 1, 0, 1 }, //GPIO_01 + { 14, 0, 1, 0, 1 }, //GPIO_02 + { 15, 0, 1, 0, 1 }, //GPIO_03 + { 16, 0, 1, 0, 1 }, //GPIO_04 + { 17, 0, 1, 0, 1 }, //GPIO_05 + { 18, 0, 1, 0, 1 }, //GPIO_06 + { 19, 0, 1, 0, 1 }, //GPIO_07 + { 20, 0, 1, 0, 1 }, //GPIO_08 + { 21, 0, 1, 0, 1 }, //GPIO_09 + { 22, 0, 1, 0, 1 }, //GPIO_10 + { 23, 0, 3, 0, 1 }, //GPIO_11 + { 24, 0, 1, 0, 1 }, //GPIO_12 + { 25, 0, 1, 0, 1 }, //GPIO_13 + { 26, 0, 3, 0, 1 }, //GPIO_14 + { 27, 0, 3, 0, 1 }, //GPIO_15 + { 28, 0, 1, 0, 1 }, //GPIO_16 + { 29, 0, 1, 0, 1 }, //GPIO_17 + { 30, 0, 1, 0, 1 }, //GPIO_18 + { 31, 0, 1, 0, 1 }, //GPIO_19 + { 32, 0, 1, 0, 1 }, //GPIO_V33 + { 33, 1, 0, 1, 0 }, //GPI0 + { 34, 0, 1, 0, 1 }, //GPI1 + { 35, 0, 1, 0, 1 }, //GPI2 + { 36, 1, 1, 1, 1 }, //GPI3 + { 37, 0, 1, 0, 1 }, //GPI4 + { 38, 0, 1, 0, 1 }}; //GPI5 + + //priority ie_first is_first ie_second is_second +char ir_mem_irq13[NUM_ALL_IR13][5] = { { 0, 0, 0, 0, 0 }, //Reserve + { 1, 0, 1, 0, 1 }, //UART + { 2, 1, 1, 1, 1 }, //I2C2_S + { 3, 0, 1, 0, 1 }, //I2C0_M0 + { 4, 0, 1, 0, 1 }, //I2C1_M1 + { 5, 0, 1, 0, 1 }, //QSPI_M + { 6, 0, 1, 0, 1 }, //MBIST + { 7, 0, 1, 0, 1 }, //GPTM0 + { 8, 0, 1, 0, 1 }, //GPTM1 + { 9, 0, 1, 0, 1 }, //GPTM2 + { 10, 0, 1, 0, 1 }, //GPTM3 + { 11, 0, 1, 0, 1 }, //GPTM4 + { 12, 0, 1, 0, 1 }, //GPTM5 + { 13, 0, 1, 0, 1 }, //GPTM6 + { 14, 0, 1, 0, 1 }, //GPTM7 + { 15, 0, 1, 0, 1 }, //GPTM8 + { 16, 0, 1, 0, 1 }, //GPTM9 + { 17, 0, 1, 0, 1 }, //GPTM10 + { 18, 0, 1, 0, 1 }, //GPTM11 + { 19, 0, 1, 0, 1 }, //CFGSET + { 20, 0, 1, 0, 1 }, //SSPI_TCH + { 21, 0, 1, 0, 1 }, //SSPI_AP + { 22, 0, 1, 1, 1 }, //FLASH_IF + { 23, 1, 1, 1, 1 }, //dma_tfr + { 24, 1, 1, 1, 1 }, //dma_block + { 25, 1, 1, 1, 1 }, //dma_srctran + { 26, 1, 1, 1, 1 }, //dma_dsttran + { 27, 1, 1, 1, 1 }, //dma_err + { 28, 1, 1, 1, 1 }, //MCU_EXT_IRQ00 IRQ00 + { 29, 1, 1, 1, 1 }, //SDP_IRQ + { 30, 0, 1, 0, 1 }, //ALPM_PHY_SLEEP_IRQ + { 31, 0, 1, 0, 1 }, //ALPM_PHY_STANDBY_IRQ + { 32, 1, 1, 1, 1 }, //POWER_SAVE_IND_IRQ + { 33, 0, 1, 0, 1 }, //POWER_UP_IRQ + { 34, 0, 1, 0, 1 }, //WAKE_UP_IRQ + { 35, 0, 1, 0, 1 }, //WAKE_F_CHANGE_IRQ + { 36, 0, 1, 0, 1 }, //HPD_OUT + { 37, 0, 1, 0, 1 }, //NORMAL_MODE_INDICATOR + { 38, 0, 1, 0, 1 }, //VCI_PRON_RDY_AFT_FLASH + { 39, 0, 1, 0, 1 }, //SSLPINA + { 40, 0, 1, 0, 1 }, //SSLPIN + { 41, 0, 1, 0, 1 }, //SDSPON + { 42, 0, 1, 0, 1 }, //vit_vs_out + { 43, 0, 1, 0, 1 }, //vit_hs_out + { 44, 0, 1, 0, 1 }, //fb_vs_out + { 45, 0, 1, 0, 1 }, //dt_lock_det_valid + { 46, 0, 1, 0, 1 }, //dt_lock_flag + { 47, 0, 1, 0, 1 }, //INTEG_RPD + { 48, 0, 1, 0, 1 }, //INTEG_MRD + { 49, 0, 1, 0, 1 }, //flag_set_line + { 50, 0, 1, 0, 1 }, //flag_ram0_rd_end + { 51, 0, 1, 0, 1 }, //flag_ram0_wr_end + { 52, 0, 1, 0, 1 }, //flag_ram0_rd_reach_wr + { 53, 0, 1, 0, 1 }, //flag_dscenc0_busy + { 54, 0, 1, 0, 1 }, //mipitx_p0_tx_vfp_area + { 55, 0, 1, 0, 1 },//te_out + { 56, 0, 1, 0, 1 }, + { 57, 0, 1, 0, 1 }, + { 58, 0, 1, 0, 1 }, + { 59, 0, 1, 0, 1 }, + { 60, 1, 1, 1, 1 },//fb_vs_out + { 61, 0, 1, 0, 1 }, + { 62, 0, 1, 0, 1 }, + { 63, 1, 1, 1, 1 }}; + + char ir_offset; + int config_int_fs = 0; + int config_int_ss = 0; + + char temp,div; + + //IRQ12 ڲжϵıȽȼ + wr_irreg(ADDR_TGET_TH, IR_PR_THOD); + + //ʹIQR12ж + temp = NUM_ALL_IR12 / 32; + div = NUM_ALL_IR12 % 32; + ir_offset =0; + if(div !=0) + { + for(unsigned char i =0;i < temp ; i++) + { + config_int_fs = 0; + config_int_ss = 0; + for (unsigned char j = 0; j < 32; j++) + { + config_int_fs = config_int_fs * 2 + ir_mem_irq12[i * 32 + 31 - j][1]; + config_int_ss = config_int_ss * 2 + ir_mem_irq12[i * 32 + 31 - j][3]; + } + wr_irreg(BASE_ADDR_IE_SS + ((int)(ir_offset)), config_int_ss); + wr_irreg(BASE_ADDR_IE_FS + ((int)(ir_offset)), config_int_fs); + ir_offset = ir_offset + 4; + } + + config_int_fs = 0; + config_int_ss = 0; + for (unsigned char j = 0; j < div; j++) + { + config_int_fs = config_int_fs * 2 + ir_mem_irq12[temp * 32 + div-1-j][1]; + config_int_ss = config_int_ss * 2 + ir_mem_irq12[temp * 32 + div-1-j][3]; + } + wr_irreg(BASE_ADDR_IE_SS + ((int)(ir_offset)), config_int_ss); + wr_irreg(BASE_ADDR_IE_FS + ((int)(ir_offset)), config_int_fs); + }else + { + for (unsigned char i = 0; i < temp; i++) + { + config_int_fs = 0; + config_int_ss = 0; + for (unsigned char j = 0; j < 32; j++) + { + config_int_fs = config_int_fs * 2 + ir_mem_irq12[i * 32 + 31 - j][1]; + config_int_ss = config_int_ss * 2 + ir_mem_irq12[i * 32 + 31 - j][3]; + } + wr_irreg(BASE_ADDR_IE_SS + ((int)(ir_offset)), config_int_ss); + wr_irreg(BASE_ADDR_IE_FS + ((int)(ir_offset)), config_int_fs); + ir_offset = ir_offset + 4; + } + } + + //irq12ж״̬ + temp = NUM_ALL_IR12 / 16; + div = NUM_ALL_IR12 % 16; + ir_offset =0; + if (div != 0) + { + for (unsigned char i = 0; i < temp; i++) + { + config_int_fs = 0; + config_int_ss = 0; + for (unsigned char j = 0; j < 16; j++) + { + config_int_fs = config_int_fs * 4 + ir_mem_irq12[i * 16 + 15 - j][2]; + config_int_ss = config_int_ss * 4 + ir_mem_irq12[i * 16 + 15 - j][4]; + } + wr_irreg(BASE_ADDR_IS_FS + ((int)(ir_offset)), config_int_ss); + wr_irreg(BASE_ADDR_IS_SS + ((int)(ir_offset)), config_int_fs); + ir_offset = ir_offset + 4; + } + + config_int_fs = 0; + config_int_ss = 0; + for (unsigned char j = 0; j < div; j++) + { + config_int_fs = config_int_fs * 2 + ir_mem_irq12[temp * 16 + div - 1 - j][2]; + config_int_ss = config_int_ss * 2 + ir_mem_irq12[temp * 16 + div - 1 - j][4]; + } + wr_irreg(BASE_ADDR_IS_FS + ((int)(ir_offset)), config_int_ss); + wr_irreg(BASE_ADDR_IS_SS + ((int)(ir_offset)), config_int_fs); + } + else + { + for (unsigned char i = 0; i < temp; i++) + { + config_int_fs = 0; + config_int_ss = 0; + for (unsigned char j = 0; j < 16; j++) + { + config_int_fs = config_int_fs * 4 + ir_mem_irq12[i * 16 + 15 - j][2]; + config_int_ss = config_int_ss * 4 + ir_mem_irq12[i * 16 + 15 - j][4]; + } + wr_irreg(BASE_ADDR_IS_FS + ((int)(ir_offset)), config_int_ss); + wr_irreg(BASE_ADDR_IS_SS + ((int)(ir_offset)), config_int_fs); + ir_offset = ir_offset + 4; + } + } + + //irq13 ڲжϵıȽȼ + wr_irreg_irq13(ADDR_TGET_TH, IR_PR_THOD); + + //ʹIQR13ж + temp = NUM_ALL_IR13 / 32; + div = NUM_ALL_IR13 % 32; + ir_offset=0; + if (div != 0) + { + for (unsigned char i = 0; i < temp; i++) + { + config_int_fs = 0; + config_int_ss = 0; + for (unsigned char j = 0; j < 32; j++) + { + config_int_fs = config_int_fs * 2 + ir_mem_irq13[i * 32 + 31 - j][1]; + config_int_ss = config_int_ss * 2 + ir_mem_irq13[i * 32 + 31 - j][3]; + } + wr_irreg_irq13(BASE_ADDR_IE_SS + ((int)(ir_offset)), config_int_ss); + wr_irreg_irq13(BASE_ADDR_IE_FS + ((int)(ir_offset)), config_int_fs); + ir_offset = ir_offset + 4; + } + + config_int_fs = 0; + config_int_ss = 0; + for (unsigned char j = 0; j < div; j++) + { + config_int_fs = config_int_fs * 2 + ir_mem_irq13[temp * 32 + div - 1 - j][1]; + config_int_ss = config_int_ss * 2 + ir_mem_irq13[temp * 32 + div - 1 - j][3]; + } + wr_irreg_irq13(BASE_ADDR_IE_SS + ((int)(ir_offset)), config_int_ss); + wr_irreg_irq13(BASE_ADDR_IE_FS + ((int)(ir_offset)), config_int_fs); + } + else + { + for (unsigned char i = 0; i < temp; i++) + { + config_int_fs = 0; + config_int_ss = 0; + for (unsigned char j = 0; j < 32; j++) + { + config_int_fs = config_int_fs * 2 + ir_mem_irq13[i * 32 + 31 - j][1]; + config_int_ss = config_int_ss * 2 + ir_mem_irq13[i * 32 + 31 - j][3]; + } + wr_irreg_irq13(BASE_ADDR_IE_SS + ((int)(ir_offset)), config_int_ss); + wr_irreg_irq13(BASE_ADDR_IE_FS + ((int)(ir_offset)), config_int_fs); + ir_offset = ir_offset + 4; + } + } + + //irq13ж״̬ + temp = NUM_ALL_IR13 / 16; + div = NUM_ALL_IR13 % 16; + ir_offset = 0; + if (div != 0) + { + for (unsigned char i = 0; i < temp; i++) + { + config_int_fs = 0; + config_int_ss = 0; + for (unsigned char j = 0; j < 16; j++) + { + config_int_fs = config_int_fs * 4 + ir_mem_irq13[i * 16 + 15 - j][2]; + config_int_ss = config_int_ss * 4 + ir_mem_irq13[i * 16 + 15 - j][4]; + } + wr_irreg_irq13(BASE_ADDR_IS_FS + ((int)(ir_offset)), config_int_ss); + wr_irreg_irq13(BASE_ADDR_IS_SS + ((int)(ir_offset)), config_int_fs); + ir_offset = ir_offset + 4; + } + + config_int_fs = 0; + config_int_ss = 0; + for (unsigned char j = 0; j < div; j++) + { + config_int_fs = config_int_fs * 2 + ir_mem_irq13[temp * 16 + div - 1 - j][2]; + config_int_ss = config_int_ss * 2 + ir_mem_irq13[temp * 16 + div - 1 - j][4]; + } + wr_irreg_irq13(BASE_ADDR_IS_FS + ((int)(ir_offset)), config_int_ss); + wr_irreg_irq13(BASE_ADDR_IS_SS + ((int)(ir_offset)), config_int_fs); + } + else + { + for (unsigned char i = 0; i < temp; i++) + { + config_int_fs = 0; + config_int_ss = 0; + for (unsigned char j = 0; j < 16; j++) + { + config_int_fs = config_int_fs * 4 + ir_mem_irq13[i * 16 + 15 - j][2]; + config_int_ss = config_int_ss * 4 + ir_mem_irq13[i * 16 + 15 - j][4]; + } + wr_irreg_irq13(BASE_ADDR_IS_FS + ((int)(ir_offset)), config_int_ss); + wr_irreg_irq13(BASE_ADDR_IS_SS + ((int)(ir_offset)), config_int_fs); + ir_offset = ir_offset + 4; + } + } +} + + + + + + + + diff --git a/src/code/project_case/RM692H5_120HZ_DSC3_1/it.c b/src/code/project_case/RM692H5_120HZ_DSC3_1/it.c new file mode 100644 index 0000000..7dccbf7 --- /dev/null +++ b/src/code/project_case/RM692H5_120HZ_DSC3_1/it.c @@ -0,0 +1,131 @@ +#include "la_config.h" +// +//------------void (*irq_callback)(void)------------------ +// +//sdp handler +extern uint8 sdp_reflash; +extern volatile uint16 sdp51; +void sdp_exter_irq_handler(void) +{ + Sdp_TypeDef sdp; + sdp_packet_read(&sdp); + if ((sdp.SDP_HB[1] == 0x08) && (sdp.SDP_DB[4] == 0xFF)) + { + sdp_reflash = 1; + //bl_state = SDP_DIMMING; + } + sdp51 = (sdp.SDP_DB[6] << 8) | (sdp.SDP_DB[5] << 0); +// LOG_DEBUG("type=%x LLm=%x DBV0=%x DBV1=%x\r\n", sdp.SDP_HB[1], sdp.SDP_DB[4], sdp.SDP_DB[5], sdp.SDP_DB[6]); +} + +void aux_irq_handler(void) +{ + static uint8 aux51_flag = 0; + uint8 aux_data3 = 0; + uint8 aux_data2 = 0; + uint8 aux_data1 = 0; + uint8 aux_data0 = 0; + + uint8 aux_len; + uint8 aux_rw; + uint16 aux_addr; + + aux_rw = AuxPack0Reg >> 28; // 8 rw + aux_addr = (AuxPack0Reg & 0x0FFFFF00) >> 8; // 004E0 addr + aux_len = AuxPack0Reg & 0x000000FF; // 00 len + + aux_data0 = AuxPack1Reg >> 24; + aux_data1 = AuxPack1Reg >> 16; + aux_data2 = AuxPack1Reg >> 8; + aux_data3 = AuxPack1Reg >> 0; + +//----51ֵ + if (aux51_flag == 1) //last command is: Write 004E0h=51 00 + { + if ((aux_rw == 8) && (aux_len == 2) && (aux_addr == 0x004F4) && (aux_data0 == 0xFF)) + { + //bl_state = AUX_DIMMING; + sdp51 = (aux_data2 << 8) + aux_data1; + } + aux51_flag = 0; + } + else + { + if ((aux_rw == 8) && (aux_len == 1) && (aux_addr == 0x004E0) && (aux_data0 == 0x51) && (aux_data1 == 0x00)) + { + aux51_flag = 1; + } + else + { + aux51_flag = 0; + } + } +} + +//ap_spi handler +void sspi_ap_irq_handler(void) +{ + if (spi_get_it_flag(IT_CS_END)) + { + spi_clear_rx_cnt(); + spi_clear_rx_fifo(); //˴ֻRX FIFO + spi_clear_it_flag(IT_CS_END); //DMA_IT_RX_NOEMPTY DMA_IT_CS_END + } +} + +void dma_err_irq_handler(void) +{ + if (dma_get_itflag(DMA_CH3, DMA_IT_ERR)) + { + dam_clear_itflag(DMA_CH3, DMA_IT_ERR); + } +} + +void dma_dst_tran_complete_irq_handler(void) +{ + if (dma_get_itflag(DMA_CH3, DMA_IT_DST)) + { + dam_clear_itflag(DMA_CH3, DMA_IT_DST); + } +} + +void dma_src_tran_complete_irq_handler(void) +{ + if (dma_get_itflag(DMA_CH3, DMA_IT_SRC)) + { + dam_clear_itflag(DMA_CH3, DMA_IT_SRC); + } +} + +void dma_block_tran_complete_irq_handler(void) +{ + if (dma_get_itflag(DMA_CH3, DMA_IT_BLOCK)) + { + dam_clear_itflag(DMA_CH3, DMA_IT_BLOCK); + } +} + +void dma_dma_tfr_complete_irq_handler(void) +{ + if (dma_get_itflag(DMA_CH3, DMA_IT_TFR)) + { + dam_clear_itflag(DMA_CH3, DMA_IT_TFR); + } +} + +/*!< GPI3жϣڼ⸴λAP_RST ʱ*/ +void gpi3_exter_irq_handler(void) +{ + //Sys_Power_Executed_State(btrue); + delay_ms(10); + if(gpix_func_read(3)==1) + { + Sys_Power_Executed_State(btrue); + } +} + +/*!< ʱж*/ +void pwr_save_irq_handler(void) +{ + Sys_Sleep_Executed_State(btrue); +} diff --git a/src/code/project_case/RM692H5_120HZ_DSC3_1/mipi_tx.c b/src/code/project_case/RM692H5_120HZ_DSC3_1/mipi_tx.c new file mode 100644 index 0000000..e477133 --- /dev/null +++ b/src/code/project_case/RM692H5_120HZ_DSC3_1/mipi_tx.c @@ -0,0 +1,1325 @@ +/********************* +/ Panel: RM692H5 +/ Purpose: +/ Ver1.0 1st version +/ Ver1.1 BC Updata；解决熄屏闪 +/ Ver2.0 BC Updata 3组Gamma; 解决三分层；解决唤醒熄屏闪 +/ Power: AVDD 7.6V ELVDD 2.8V ELVSS -4.2V +*********************/ + +#include "typedef.h" +#include "define.h" + +void ini_mptx() +{ + mipitx_send_packet_type39(); +} + +const uint8 init_data_type_h39[] = { //cmd_byte_length,cmd,data.... + 2, 0xFE,0xA0, + 2, 0x90,0x10, + 2, 0x98,0x94, + 2, 0x99,0x94, + 2, 0x9C,0xF0, + 2, 0x9D,0x00, + 2, 0xFE,0x42, + 2, 0x18,0x76, + 2, 0xFE,0x40, + 2, 0xBF,0xBA, + 2, 0xFE,0x98, + 2, 0x2F,0x00, + 2, 0xFE,0x40, + 2, 0xBE,0x99, + 2, 0xFE,0x42, + 2, 0x1A,0x80, + 2, 0x19,0x00, + 2, 0x3B,0x65, + 2, 0x3D,0x00, + 2, 0x3F,0x00, + 2, 0x41,0x70, + 2, 0x43,0x00, + 2, 0x44,0x04, + 2, 0xFE,0x40, + 2, 0x0C,0x0C, + 2, 0x08,0x0C, + 2, 0x09,0x00, + 2, 0x0D,0x2C, + 2, 0x10,0x00, + 2, 0x15,0x24, + 2, 0x17,0x00, + 2, 0x18,0x00, + 2, 0x0E,0x2C, + 2, 0x16,0x24, + 2, 0x19,0x00, + 2, 0x0F,0x2C, + 2, 0x11,0x00, + 2, 0x1A,0x24, + 2, 0x1D,0x00, + 2, 0x1F,0x00, + 2, 0x1B,0x24, + 2, 0x20,0x00, + 2, 0x1C,0x24, + 2, 0x1E,0x00, + 2, 0x21,0x00, + 2, 0x64,0xF0, + 2, 0x65,0x0A, + 2, 0x01,0x07, + 2, 0xFE,0xD0, + 2, 0x86,0x14, + 2, 0x84,0x14, + 2, 0x85,0x01, + 2, 0xFE,0x40, + 2, 0x6F,0xB4, + 2, 0x71,0x01, + 2, 0x70,0xB4, + 2, 0x72,0x01, + 2, 0x73,0xB4, + 2, 0x76,0x11, + 2, 0x74,0xB4, + 2, 0x75,0xB4, + 2, 0x77,0x10, + 2, 0xB6,0x12, + 2, 0xB8,0x02, + 2, 0xFE,0xD0, + 2, 0x90,0x80, + 2, 0x91,0x0A, + 2, 0xFE,0xD4, + 2, 0x05,0x00, + 2, 0xFE,0xD6, + 2, 0x17,0x00, + 2, 0x00,0x00, + 2, 0x09,0x00, + 2, 0x01,0x00, + 2, 0x02,0x82, + 2, 0x05,0x22, + 2, 0x03,0x04, + 2, 0x04,0x02, + 2, 0x06,0x82, + 2, 0x07,0x04, + 2, 0x08,0x00, + 2, 0xFE,0x28, + 2, 0x05,0x01, + 2, 0x06,0x40, + 2, 0xFE,0x97, + 2, 0x40,0x01, + 2, 0x3D,0x05, + 2, 0x3F,0x00, + 2, 0xFE,0x1A, + 2, 0x54,0x01, + 2, 0xFE,0x49, + 2, 0x5D,0x00, + 2, 0x54,0x17, + 2, 0xFE,0x1A, + 2, 0x6D,0x90, + 2, 0x36,0x6B, + 2, 0x38,0x00, + 2, 0x6E,0x01, + 2, 0x6F,0x02, + 2, 0x46,0x0F, + 2, 0x4C,0x00, + 2, 0x47,0x00, + 2, 0x4D,0x00, + 2, 0x48,0x00, + 2, 0x4E,0x00, + 2, 0x43,0x00, + 2, 0x49,0x00, + 2, 0x44,0x00, + 2, 0x4A,0x0F, + 2, 0x45,0x00, + 2, 0x4B,0x00, + 2, 0x14,0x00, + 2, 0x15,0x6A, + 2, 0xFE,0x98, + 2, 0x10,0xA2, + 2, 0xCE,0x00, + 2, 0xCF,0x1E, + 2, 0xFE,0x49, + 2, 0x63,0x03, + 2, 0x64,0x00, + 2, 0x68,0x14, + 2, 0x6E,0x00, + 2, 0x72,0xDA, + 2, 0xFE,0xD4, + 2, 0x9D,0x80, + 2, 0xFE,0x99, + 2, 0x1E,0x00, + 2, 0x1F,0x00, + 2, 0xFE,0x98, + 2, 0x0F,0x40, + 2, 0xFE,0xD0, + 2, 0xC7,0x00, + 2, 0xC8,0x00, + 2, 0xFE,0x98, + 2, 0x11,0xFF, + 2, 0xFE,0x1A, + 2, 0x71,0x00, + 2, 0xFE,0x98, + 2, 0x13,0x08, + 2, 0xFE,0x72, + 2, 0x9B,0x00, + 2, 0xFE,0x58, + 2, 0xC5,0x00, + 2, 0xFE,0x98, + 2, 0x20,0x03, + 2, 0xFE,0x99, + 2, 0x1B,0x14, + 2, 0xFE,0x40, + 2, 0x03,0x03, + 2, 0xFE,0x49, + 2, 0x80,0x55, + 2, 0x81,0x05, + 2, 0x88,0x50, + 2, 0x7b,0xF7, + 2, 0x7C,0xF7, + 2, 0x7D,0xF7, + 2, 0x7E,0xF7, + 2, 0x7F,0xC4, + 2, 0xFE,0xA0, + 2, 0x97,0x00, + 2, 0xFE,0x49, + 2, 0x68,0x09, + 2, 0x0F,0x09, + 2, 0xFE,0xA0, + 2, 0x45,0x00, + 2, 0x5a,0x00, + 2, 0x5F,0xA0, + 2, 0x61,0x80, + 2, 0xFE,0x49, + 2, 0x62,0x02, + 2, 0x72,0xFF, + 2, 0x6E,0x21, + 2, 0x14,0xFF, + 2, 0x08,0x00, + 2, 0x1B,0x00, + 2, 0x1F,0x00, + 2, 0x0E,0x02, + 2, 0xFE,0x40, + 2, 0xBD,0x80, + 2, 0xFE,0x1A, + 2, 0x0D,0x82, + 2, 0x31,0x82, + 2, 0xFE,0xA0, + 2, 0x5D,0x37, + 2, 0xFE,0x49, + 2, 0x25,0x37, + 2, 0xFE,0x9B, + 2, 0x23,0x02, + 2, 0x25,0x03, + 2, 0x28,0x0F, + 2, 0x39,0x10, + 2, 0x00,0x13, + 2, 0x01,0x13, + 2, 0x02,0x13, + 2, 0x03,0x13, + 2, 0x04,0x13, + 2, 0x05,0x13, + 2, 0x06,0x4B, + 2, 0x07,0x4B, + 2, 0x08,0x4B, + 2, 0x09,0x4B, + 2, 0x0A,0x4B, + 2, 0x38,0x00, + 2, 0x33,0x04, + 2, 0x34,0xC8, + 2, 0x35,0x70, + 2, 0x32,0x08, + 2, 0x27,0x22, + 2, 0xFE,0x49, + 2, 0x55,0x54, + 2, 0xFE,0x40, + 2, 0x98,0x41, + 2, 0x99,0x41, + 2, 0xFE,0x62, + 2, 0x4D,0xC0, + 2, 0x4E,0x00, + 2, 0x4F,0xB2, + 2, 0x50,0x2A, + 2, 0xFE,0x60, + 2, 0xF9,0xAA, + 2, 0xFE,0xD0, + 2, 0x16,0x55, + 2, 0x14,0xC8, + 2, 0x15,0x48, + 2, 0xFE,0x40, + 2, 0x97,0xA0, + 2, 0x44,0x00, + 2, 0x12,0x04, + 2, 0x13,0x04, + 2, 0x34,0x00, + 2, 0x32,0x8C, + 2, 0x33,0x8C, + 2, 0x2F,0x8C, + 2, 0x31,0x8C, + 2, 0x41,0x5D, + 2, 0x43,0x5D, + 2, 0x3D,0x5D, + 2, 0x3F,0x5D, + 2, 0xFE,0xD0, + 2, 0x17,0x91, + 2, 0xFE,0x40, + 2, 0x29,0x8C, + 2, 0x38,0x5D, + 2, 0x2A,0x8C, + 2, 0x3A,0x5D, + 2, 0x2B,0x8C, + 2, 0x3B,0x5D, + 2, 0x2D,0x00, + 2, 0x25,0x8C, + 2, 0x35,0x5D, + 2, 0x26,0x8C, + 2, 0x36,0x5D, + 2, 0x27,0x8C, + 2, 0x37,0x5D, + 2, 0x28,0x00, + 2, 0xFE,0xA0, + 2, 0x4F,0xA0, + 2, 0x4C,0x3A, + 2, 0xFE,0x53, + 2, 0xD5,0x00, + 2, 0xD6,0x00, + 2, 0xFE,0x53, + 2, 0x20,0x88, + 2, 0x21,0x30, + 2, 0x22,0x30, + 2, 0x23,0x88, + 2, 0x24,0x30, + 2, 0x25,0x30, + 2, 0x26,0x88, + 2, 0x27,0x30, + 2, 0x28,0x30, + 2, 0x29,0x88, + 2, 0x2A,0x30, + 2, 0x2B,0x30, + 2, 0x2D,0x88, + 2, 0x2F,0x30, + 2, 0x30,0x30, + 2, 0x31,0x88, + 2, 0x32,0x30, + 2, 0x33,0x30, + 2, 0x34,0x88, + 2, 0x35,0x30, + 2, 0x36,0x30, + 2, 0x37,0x88, + 2, 0x38,0x30, + 2, 0x39,0x30, + 2, 0x3D,0x80, + 2, 0x3F,0x30, + 2, 0x50,0x00, + 2, 0x51,0x2F, + 2, 0x52,0x2F, + 2, 0x53,0x00, + 2, 0x54,0x2F, + 2, 0x55,0x2F, + 2, 0x56,0x00, + 2, 0x58,0x2F, + 2, 0x59,0x2F, + 2, 0x5A,0x00, + 2, 0x5B,0x2F, + 2, 0x5C,0x2F, + 2, 0x5D,0x00, + 2, 0x5E,0x2F, + 2, 0x5F,0x2F, + 2, 0x60,0x00, + 2, 0x61,0x2F, + 2, 0x62,0x2F, + 2, 0x63,0x00, + 2, 0x64,0x2F, + 2, 0x65,0x2F, + 2, 0x66,0x00, + 2, 0x67,0x2F, + 2, 0x68,0x2F, + 2, 0x69,0x00, + 2, 0x6A,0x2F, + 2, 0x7B,0x44, + 2, 0x7C,0xB0, + 2, 0x7D,0xB0, + 2, 0x7E,0x44, + 2, 0x7F,0xB0, + 2, 0x80,0xB0, + 2, 0x81,0x44, + 2, 0x82,0xB0, + 2, 0x83,0xB0, + 2, 0x84,0x44, + 2, 0x85,0xB0, + 2, 0x86,0xB0, + 2, 0x87,0x44, + 2, 0x88,0xB0, + 2, 0x89,0xB0, + 2, 0x8A,0x44, + 2, 0x8B,0xB0, + 2, 0x8C,0xB0, + 2, 0x8D,0x44, + 2, 0x8E,0xB0, + 2, 0x8F,0xB0, + 2, 0x90,0x44, + 2, 0x91,0xB0, + 2, 0x92,0xB0, + 2, 0x93,0x40, + 2, 0x94,0xB0, + 2, 0xA6,0x44, + 2, 0xA7,0x70, + 2, 0xA9,0x70, + 2, 0xAA,0x44, + 2, 0xAB,0x70, + 2, 0xAC,0x70, + 2, 0xAD,0x44, + 2, 0xAE,0x70, + 2, 0xAF,0x70, + 2, 0xB0,0x44, + 2, 0xB1,0x70, + 2, 0xB2,0x70, + 2, 0xB3,0x44, + 2, 0xB4,0x70, + 2, 0xB5,0x70, + 2, 0xB6,0x44, + 2, 0xB7,0x70, + 2, 0xB8,0x70, + 2, 0xB9,0x44, + 2, 0xBA,0x70, + 2, 0xBB,0x70, + 2, 0xBC,0x44, + 2, 0xBD,0x70, + 2, 0xBE,0x70, + 2, 0xBF,0x40, + 2, 0xC0,0x70, + 2, 0xFE,0x72, + 2, 0x96,0x98, + 2, 0x33,0x03, + 2, 0xFE,0x53, + 2, 0xD7,0x41, + 2, 0xFE,0xD0, + 2, 0x5C,0x03, + 2, 0xFE,0x42, + 2, 0x96,0x16, + 2, 0xFE,0x40, + 2, 0xAC,0x38, + 2, 0xAE,0x00, + 2, 0xFE,0x70, + 2, 0x2A,0x04, + 2, 0xFE,0x76, + 2, 0x44,0x02, + 2, 0x45,0xC4, + 2, 0x46,0x06, + 2, 0x47,0xC0, + 2, 0x48,0x14, + 2, 0x49,0xE0, + 2, 0x4A,0x14, + 2, 0x4B,0xE0, + 2, 0x4C,0x14, + 2, 0x4D,0xE0, + 2, 0x4E,0x14, + 2, 0x4F,0xE0, + 2, 0x50,0x14, + 2, 0x51,0xE0, + 2, 0x52,0x14, + 2, 0x53,0xE0, + 2, 0x54,0x14, + 2, 0x55,0xE0, + 2, 0x56,0x14, + 2, 0x58,0xE0, + 2, 0x59,0x14, + 2, 0x5A,0xE0, + 2, 0x6F,0x1F, + 2, 0x70,0xFF, + 2, 0x26,0x07, + 2, 0x27,0x00, + 2, 0x29,0x01, + 2, 0x2A,0x01, + 2, 0x2B,0x02, + 2, 0x2D,0x0C, + 2, 0x2F,0x0C, + 2, 0x30,0x0C, + 2, 0x31,0x0C, + 2, 0x32,0x0C, + 2, 0x33,0x0C, + 2, 0x34,0x0C, + 2, 0x35,0x0C, + 2, 0x36,0x0C, + 2, 0x43,0x0C, + 2, 0x00,0x01, + 2, 0x01,0x00, + 2, 0x03,0xF0, + 2, 0x04,0x00, + 2, 0x05,0xFF, + 2, 0x06,0xFF, + 2, 0x07,0xFF, + 2, 0x08,0xFF, + 2, 0x09,0xFF, + 2, 0x0A,0xFF, + 2, 0x0B,0xFF, + 2, 0x0C,0xFF, + 2, 0x0D,0xFF, + 2, 0x0E,0xFF, + 2, 0x0F,0xFF, + 2, 0x10,0xFF, + 2, 0x11,0xFF, + 2, 0x12,0xFF, + 2, 0x13,0xFF, + 2, 0x14,0xFF, + 2, 0x24,0x0F, + 2, 0x25,0xFF, + 2, 0x97,0x07, + 2, 0x98,0x00, + 2, 0x9A,0xFF, + 2, 0x9B,0x69, + 2, 0x9C,0x69, + 2, 0x9D,0xFF, + 2, 0x9E,0x69, + 2, 0x9F,0x69, + 2, 0xA0,0xFF, + 2, 0xA2,0x69, + 2, 0xA3,0x69, + 2, 0xA4,0xFF, + 2, 0xA5,0x69, + 2, 0xA6,0x69, + 2, 0xA7,0xFF, + 2, 0xA9,0x69, + 2, 0xAA,0x69, + 2, 0xAB,0xFF, + 2, 0xAC,0x69, + 2, 0xAD,0x69, + 2, 0xBD,0x0F, + 2, 0xBE,0x69, + 2, 0x71,0x07, + 2, 0x72,0x00, + 2, 0x74,0xFF, + 2, 0x75,0xFF, + 2, 0x76,0xFF, + 2, 0x77,0xFF, + 2, 0x78,0xFF, + 2, 0x79,0xFF, + 2, 0x7A,0xFF, + 2, 0x7B,0xFF, + 2, 0x7C,0xFF, + 2, 0x7D,0xFF, + 2, 0x7E,0xFF, + 2, 0x7F,0xFF, + 2, 0x80,0xFF, + 2, 0x81,0xFF, + 2, 0x82,0xFF, + 2, 0x83,0xFF, + 2, 0x84,0xFF, + 2, 0x85,0xFF, + 2, 0x95,0x0F, + 2, 0x96,0xFF, + 2, 0xFE,0x53, + 2, 0x00,0x19, + 2, 0x01,0x01, + 2, 0x02,0x03, + 2, 0x03,0x07, + 2, 0x04,0x0F, + 2, 0x05,0x17, + 2, 0x06,0x1F, + 2, 0x07,0x27, + 2, 0x08,0x2F, + 2, 0x09,0x37, + 2, 0x0A,0x3F, + 2, 0x0B,0x47, + 2, 0x0C,0x4F, + 2, 0x0D,0x5F, + 2, 0x0E,0x6F, + 2, 0x0F,0x7F, + 2, 0x10,0x8F, + 2, 0x11,0x9F, + 2, 0x12,0xAF, + 2, 0x13,0xBF, + 2, 0x14,0xCF, + 2, 0x15,0xDF, + 2, 0x16,0xEF, + 2, 0x17,0xF7, + 2, 0x18,0xFF, + 2, 0xFE,0x60, + 2, 0xF3,0x78, + 2, 0xAC,0xF0, + 2, 0xFE,0x62, + 2, 0x51,0x23, + 2, 0xFE,0x72, + 2, 0x34,0x33, + 2, 0x35,0xFF, + 2, 0xF6,0x04, + 2, 0xF7,0x24, + 2, 0x52,0x0B, + 2, 0x53,0x40, + 2, 0x54,0x0B, + 2, 0x55,0x40, + 2, 0xFE,0x61, + 2, 0x0E,0x21, + 2, 0x02,0x00, + 2, 0x03,0x99, + 2, 0x04,0xE0, + 2, 0x05,0x5A, + 2, 0x06,0x5C, + 2, 0x07,0xBE, + 2, 0xFE,0x72, + 2, 0x32,0x62, + 2, 0xFE,0x61, + 2, 0x0D,0x22, + 2, 0xFE,0xD0, + 2, 0x4E,0x20, + 2, 0xFE,0x61, + 2, 0x0B,0x22, + 2, 0xFE,0x61, + 2, 0x0C,0x22, + 2, 0x08,0x22, + 2, 0xFE,0x61, + 2, 0x09,0x22, + 2, 0xFE,0x61, + 2, 0x0A,0x22, + 2, 0xFE,0x60, + 2, 0xB8,0xFF, + 2, 0xB9,0xFF, + 2, 0xBA,0xFF, + 2, 0xBB,0xFF, + 2, 0xBC,0xFF, + 2, 0xFE,0x62, + 2, 0xC0,0x02, + 2, 0xFE,0x98, + 2, 0x20,0x03, + 2, 0x21,0x08, + 2, 0xFE,0x62, + 2, 0x6C,0x08, + 2, 0x5B,0x40, + 2, 0x6D,0x01, + 2, 0x6F,0x02, + 2, 0x5D,0x01, + 2, 0x6A,0x10, + 2, 0x6B,0x01, + 2, 0x8A,0x02, + 2, 0xFE,0x60, + 2, 0xEE,0x01, + 2, 0xEF,0x10, + 2, 0xFE,0x60, + 2, 0xC6,0x49, + 2, 0xC7,0x4A, + 2, 0xC9,0x50, + 2, 0xCA,0x46, + 2, 0xCB,0x45, + 2, 0xCC,0x53, + 2, 0xCD,0x41, + 2, 0xCE,0x43, + 2, 0xD0,0x42, + 2, 0xD1,0x44, + 2, 0xD2,0x40, + 2, 0xD4,0x5D, + 2, 0xD5,0x5D, + 2, 0xD6,0x5D, + 2, 0xD7,0x5D, + 2, 0xDA,0x4A, + 2, 0xDB,0x49, + 2, 0xDD,0x47, + 2, 0xDE,0x46, + 2, 0xDF,0x45, + 2, 0xE0,0x55, + 2, 0xE1,0x41, + 2, 0xE2,0x43, + 2, 0xE4,0x42, + 2, 0xE5,0x44, + 2, 0xE6,0x40, + 2, 0xE8,0x5D, + 2, 0xE9,0x5D, + 2, 0xEA,0x5D, + 2, 0xEB,0x5D, + 2, 0xFE,0x62, + 2, 0x00,0x8C, + 2, 0x01,0x00, + 2, 0x02,0x00, + 2, 0x03,0x02, + 2, 0x04,0x00, + 2, 0x05,0x02, + 2, 0x06,0x48, + 2, 0x07,0x25, + 2, 0x08,0x00, + 2, 0xFE,0x60, + 2, 0x00,0xC0, + 2, 0x01,0x00, + 2, 0x02,0x04, + 2, 0x03,0x00, + 2, 0x04,0x00, + 2, 0x05,0x15, + 2, 0x06,0x1A, + 2, 0x07,0x5D, + 2, 0x08,0x00, + 2, 0x1B,0xC0, + 2, 0x1C,0x00, + 2, 0x1D,0x04, + 2, 0x1E,0x00, + 2, 0x1F,0x00, + 2, 0x20,0x14, + 2, 0x21,0x1A, + 2, 0x22,0x5D, + 2, 0x23,0x00, + 2, 0xFE,0x62, + 2, 0x2F,0x80, + 2, 0x30,0x13, + 2, 0x35,0x80, + 2, 0x36,0x12, + 2, 0xFE,0x60, + 2, 0x83,0xCA, + 2, 0x84,0x00, + 2, 0x85,0x00, + 2, 0x86,0x24, + 2, 0x87,0x00, + 2, 0x88,0x0F, + 2, 0x89,0x01, + 2, 0x8A,0x01, + 2, 0x8B,0x80, + 2, 0x55,0xC8, + 2, 0x56,0x00, + 2, 0x58,0x04, + 2, 0x59,0x01, + 2, 0x5A,0x00, + 2, 0x5B,0x12, + 2, 0x5C,0x01, + 2, 0x5D,0x24, + 2, 0x5E,0x00, + 2, 0xFE,0x62, + 2, 0x43,0x80, + 2, 0x44,0x14, + 2, 0x49,0x00, + 2, 0x87,0x00, + 2, 0x88,0x01, + 2, 0x89,0x24, + 2, 0xFE,0x63, + 2, 0x71,0x8A, + 2, 0x72,0x00, + 2, 0x73,0x00, + 2, 0x74,0x08, + 2, 0x75,0x00, + 2, 0x76,0x0D, + 2, 0x77,0x01, + 2, 0x78,0x01, + 2, 0x79,0x00, + 2, 0xFE,0x62, + 2, 0x3B,0x80, + 2, 0x3D,0x12, + 2, 0xFE,0x60, + 2, 0x38,0xC0, + 2, 0x39,0x00, + 2, 0x3A,0x04, + 2, 0x3B,0x01, + 2, 0x3D,0x00, + 2, 0x3F,0x14, + 2, 0x40,0x01, + 2, 0x41,0x24, + 2, 0x42,0x00, + 2, 0xFE,0x63, + 2, 0x4C,0x8A, + 2, 0x4D,0x00, + 2, 0x4E,0x00, + 2, 0x4F,0x0C, + 2, 0x50,0x00, + 2, 0x51,0x09, + 2, 0x52,0x01, + 2, 0x53,0x01, + 2, 0x54,0x00, + 2, 0x00,0x8D, + 2, 0x01,0x00, + 2, 0x02,0x00, + 2, 0x03,0x04, + 2, 0x04,0x00, + 2, 0x05,0x07, + 2, 0x06,0x01, + 2, 0x07,0x01, + 2, 0x08,0x00, + 2, 0x24,0xED, + 2, 0x25,0x03, + 2, 0x26,0xC0, + 2, 0x27,0x04, + 2, 0x28,0x03, + 2, 0x29,0xBB, + 2, 0x2A,0x12, + 2, 0x2B,0x12, + 2, 0xFE,0x62, + 2, 0x69,0x04, + 2, 0x77,0x02, + 2, 0xFE,0x90, + 2, 0x00,0x64, + 2, 0x01,0x64, + 2, 0x02,0x64, + 2, 0x03,0x46, + 2, 0x04,0x46, + 2, 0x05,0x46, + 2, 0xFE,0x42, + 2, 0x0B,0x00, + 2, 0xFE,0x72, + 2, 0x2F,0x01, + 2, 0xFE,0x72, + 2, 0x19,0x40, + 2, 0x1A,0x00, + 2, 0x1B,0x92, + 2, 0x1C,0x02, + 2, 0x1D,0x49, + 2, 0x1E,0xB6, + 2, 0x1F,0xDB, + 2, 0x20,0x6D, + 2, 0x21,0x09, + 2, 0x22,0x24, + 2, 0x23,0x4B, + 2, 0x24,0x6D, + 2, 0x25,0x92, + 2, 0x26,0x02, + 2, 0x27,0x49, + 2, 0x28,0x06, + 2, 0x29,0xDB, + 2, 0x2A,0x00, + 2, 0x2B,0x09, + 2, 0x2D,0x24, + 2, 0xFE,0x90, + 2, 0x77,0x27, + 2, 0x7A,0x00, + 2, 0x7B,0x02, + 2, 0x74,0x20, + 2, 0x19,0x00, + 2, 0xFE,0x28, + 2, 0x04,0x52, + 2, 0xFE,0x28, + 2, 0x2F,0x20, + 2, 0x30,0x20, + 2, 0x31,0x00, + 2, 0x32,0x20, + 2, 0x34,0x20, + 2, 0x35,0x00, + 2, 0x44,0x20, + 2, 0x45,0x20, + 2, 0x46,0x00, + 2, 0x36,0x00, + 2, 0x37,0x40, + 2, 0x38,0x00, + 2, 0x10,0x00, + 2, 0x11,0x40, + 2, 0x12,0x00, + 2, 0x39,0x00, + 2, 0x3A,0x40, + 2, 0x3B,0x00, + 2, 0x47,0x00, + 2, 0x48,0x20, + 2, 0x49,0x00, + 2, 0x3D,0x20, + 2, 0x3F,0x20, + 2, 0x40,0x00, + 2, 0x41,0x20, + 2, 0x42,0x20, + 2, 0x43,0x00, + 2, 0x4A,0x20, + 2, 0x4B,0x20, + 2, 0x4C,0x00, + 2, 0x4D,0x20, + 2, 0x4E,0x20, + 2, 0x4F,0x00, + 2, 0x50,0x20, + 2, 0x51,0x20, + 2, 0x52,0x00, + 2, 0x53,0x20, + 2, 0x54,0x20, + 2, 0x55,0x00, + 2, 0x60,0x20, + 2, 0x61,0x20, + 2, 0x62,0x00, + 2, 0x63,0x20, + 2, 0x64,0x20, + 2, 0x65,0x00, + 2, 0x66,0x20, + 2, 0x67,0x20, + 2, 0x68,0x00, + 2, 0x56,0x00, + 2, 0x58,0x40, + 2, 0x59,0x00, + 2, 0x13,0x00, + 2, 0x14,0x40, + 2, 0x15,0x00, + 2, 0x5A,0x00, + 2, 0x5B,0x40, + 2, 0x5C,0x00, + 2, 0x5D,0x00, + 2, 0x5E,0x20, + 2, 0x5F,0x00, + 2, 0xFE,0x90, + 2, 0xBE,0x20, + 2, 0xBF,0x20, + 2, 0xC0,0x00, + 2, 0x8C,0x20, + 2, 0x8D,0x20, + 2, 0x8E,0x00, + 2, 0xC2,0x20, + 2, 0xC3,0x20, + 2, 0xC4,0x00, + 2, 0xD6,0x20, + 2, 0xD7,0x20, + 2, 0xD8,0x00, + 2, 0x98,0x20, + 2, 0x99,0x20, + 2, 0x9A,0x00, + 2, 0xDA,0x20, + 2, 0xDB,0x20, + 2, 0xDC,0x00, + 2, 0xEE,0x20, + 2, 0xEF,0x20, + 2, 0xF0,0x00, + 2, 0xAA,0x20, + 2, 0xAB,0x20, + 2, 0xAC,0x00, + 2, 0xF3,0x20, + 2, 0xF4,0x20, + 2, 0xF5,0x00, + 2, 0xFE,0x28, + 2, 0xB6,0x20, + 2, 0xB7,0x20, + 2, 0xB8,0x00, + 2, 0xFE,0x90, + 2, 0xB6,0x20, + 2, 0xB7,0x20, + 2, 0xB8,0x00, + 2, 0xFE,0x28, + 2, 0xBA,0x20, + 2, 0xBB,0x20, + 2, 0xBC,0x00, + 2, 0xFE,0x90, + 2, 0xC6,0x00, + 2, 0xC7,0x40, + 2, 0xC8,0x00, + 2, 0x90,0x00, + 2, 0x91,0x40, + 2, 0x92,0x00, + 2, 0xCA,0x00, + 2, 0xCB,0x40, + 2, 0xCC,0x00, + 2, 0xDE,0x00, + 2, 0xDF,0x40, + 2, 0xE0,0x00, + 2, 0x9C,0x00, + 2, 0x9D,0x40, + 2, 0x9E,0x00, + 2, 0xE2,0x00, + 2, 0xE3,0x40, + 2, 0xE4,0x00, + 2, 0xF7,0x00, + 2, 0xF8,0x40, + 2, 0xFE,0x28, + 2, 0xA7,0x00, + 2, 0xFE,0x90, + 2, 0xAE,0x00, + 2, 0xAF,0x40, + 2, 0xB0,0x00, + 2, 0xFE,0x28, + 2, 0xAA,0x00, + 2, 0xAB,0x40, + 2, 0xAC,0x00, + 2, 0xBE,0x00, + 2, 0xBF,0x40, + 2, 0xC0,0x00, + 2, 0xFE,0x90, + 2, 0xBA,0x00, + 2, 0xBB,0x40, + 2, 0xBC,0x00, + 2, 0xFE,0x28, + 2, 0xC2,0x00, + 2, 0xC3,0x40, + 2, 0xC4,0x00, + 2, 0xFE,0x90, + 2, 0xCE,0x20, + 2, 0xCF,0x20, + 2, 0xD0,0x00, + 2, 0x94,0x20, + 2, 0x95,0x20, + 2, 0x96,0x00, + 2, 0xD2,0x20, + 2, 0xD3,0x20, + 2, 0xD4,0x00, + 2, 0xE6,0x20, + 2, 0xE7,0x20, + 2, 0xE8,0x00, + 2, 0xA0,0x20, + 2, 0xA2,0x20, + 2, 0xA3,0x00, + 2, 0xEA,0x20, + 2, 0xEB,0x20, + 2, 0xEC,0x00, + 2, 0xFE,0x28, + 2, 0xAE,0x20, + 2, 0xAF,0x20, + 2, 0xB0,0x00, + 2, 0xFE,0x90, + 2, 0xA5,0x20, + 2, 0xA6,0x20, + 2, 0xA7,0x00, + 2, 0xFE,0x28, + 2, 0xB2,0x20, + 2, 0xB3,0x20, + 2, 0xB4,0x00, + 2, 0xC6,0x20, + 2, 0xC7,0x20, + 2, 0xC8,0x00, + 2, 0xFE,0x90, + 2, 0xB2,0x20, + 2, 0xB3,0x20, + 2, 0xB4,0x00, + 2, 0xFE,0x28, + 2, 0xCA,0x20, + 2, 0xCB,0x20, + 2, 0xCC,0x00, + 2, 0xFE,0x90, + 2, 0x59,0x08, + 2, 0x52,0x10, + 2, 0x4C,0x08, + 2, 0x5A,0x08, + 2, 0x53,0x10, + 2, 0x4D,0x08, + 2, 0x2A,0x08, + 2, 0x24,0x10, + 2, 0x1E,0x08, + 2, 0x2B,0x08, + 2, 0x25,0x10, + 2, 0x1F,0x08, + 2, 0x0A,0x08, + 2, 0x08,0x0A, + 2, 0x06,0x08, + 2, 0x0B,0x08, + 2, 0x09,0x0A, + 2, 0x07,0x08, + 2, 0x70,0x08, + 2, 0x55,0x08, + 2, 0x45,0x00, + 2, 0x6C,0x00, + 2, 0x4F,0x10, + 2, 0x41,0x00, + 2, 0x68,0x08, + 2, 0x49,0x08, + 2, 0x3B,0x00, + 2, 0x72,0x08, + 2, 0x58,0x08, + 2, 0x47,0x00, + 2, 0x6E,0x00, + 2, 0x51,0x10, + 2, 0x43,0x00, + 2, 0x6A,0x08, + 2, 0x4B,0x08, + 2, 0x3F,0x00, + 2, 0x64,0x08, + 2, 0x27,0x08, + 2, 0x37,0x00, + 2, 0x60,0x00, + 2, 0x21,0x10, + 2, 0x33,0x00, + 2, 0x5C,0x08, + 2, 0x1B,0x08, + 2, 0x2F,0x00, + 2, 0x66,0x08, + 2, 0x29,0x08, + 2, 0x39,0x00, + 2, 0x62,0x00, + 2, 0x23,0x10, + 2, 0x35,0x00, + 2, 0x5E,0x08, + 2, 0x1D,0x08, + 2, 0x31,0x00, + 2, 0xFE,0x28, + 2, 0xD1,0x12, + 2, 0xCE,0x24, + 2, 0xCF,0x00, + 2, 0xD0,0x24, + 2, 0xfe,0x90, + 2, 0x79,0xD8, + 2, 0x80,0x1A, + 2, 0xfe,0x90, + 2, 0x81,0x00, + 2, 0x82,0x04, + 2, 0x83,0x04, + 2, 0x84,0xFC, + 2, 0x85,0x00, + 2, 0x86,0x04, + 2, 0x87,0x0A, + 2, 0x88,0xEC, + 2, 0xfe,0x90, + 2, 0x0C,0xC0, + 2, 0x0D,0x04, + 2, 0x0E,0x00, + 2, 0x0F,0xFE, + 2, 0xFE,0x40, + 2, 0x7E,0x11, + 2, 0xFE,0x40, + 2, 0x80,0x6C, + 2, 0xFE,0xA0, + 2, 0x10,0x04, + 2, 0x02,0x36, + 2, 0xFE,0xD0, + 2, 0x2A,0x10, + 2, 0x2B,0x10, + 2, 0x2D,0x10, + 2, 0x2F,0x10, + 2, 0x30,0x10, + 2, 0x31,0x10, + 2, 0xFE,0xD4, + 2, 0x61,0x08, + 2, 0xFE,0x40, + 2, 0x58,0x00, + 2, 0x49,0x0A, + 2, 0x60,0x0D, + 2, 0xC4,0x00, + 2, 0x5E,0xD7, + 2, 0x5F,0xD7, + 2, 0x51,0x77, + 2, 0x66,0x01, + 2, 0xCC,0x1F, + 2, 0xC9,0x15, + 2, 0x52,0x05, + 2, 0x55,0x05, + 2, 0x67,0xA8, + 2, 0x53,0x1F, + 2, 0x56,0x1F, + 2, 0x68,0x55, + 2, 0xFE,0x1A, + 2, 0x6D,0x80, + 2, 0x6E,0x00, + 2, 0x6F,0x00, + 2, 0x13,0x01, + 2, 0x15,0x6A, + 2, 0x36,0xA0, + 2, 0x38,0x00, + 2, 0x90,0xA2, + 2, 0x91,0x3F, + 2, 0x92,0x00, + 2, 0x93,0x01, + 2, 0x94,0x54, + 2, 0x95,0x00, + 2, 0xA2,0x00, + 2, 0xA0,0x00, + 2, 0x96,0x6B, + 2, 0xA4,0x6B, + 2, 0x43,0x00, + 2, 0x44,0x00, + 2, 0x45,0x00, + 2, 0x46,0x00, + 2, 0x47,0x00, + 2, 0x48,0x00, + 2, 0x49,0x00, + 2, 0x4A,0x00, + 2, 0x4B,0x00, + 2, 0x4C,0x00, + 2, 0x4D,0x00, + 2, 0x4E,0x00, + 2, 0xFE,0x42, + 2, 0x16,0x01, + 2, 0xFE,0x16, + 2, 0x72,0x00, + 2, 0x73,0x00, + 2, 0x74,0x00, + 2, 0x79,0x08, + 2, 0x7A,0x40, + 2, 0xFE,0x00, + 129, 0x77,0x89,0xC0,0x04,0x22,0x0A,0x01,0x90,0xA6,0x0A,0x43,0xA1,0x2A,0x0A,0x85,0xB1,0xAD,0x0A,0xC7,0x3E,0x10,0x0B,0x08,0xCA,0x53,0x0B,0x49,0xD2,0x95,0x0B,0x8A,0xDA,0xD7,0x0B,0xCB,0xDF,0x18,0x0C,0x0C,0x67,0x39,0x0C,0x4D,0x6B,0x5B,0x0C,0x8D,0xEF,0x7C,0x0C,0xCE,0x73,0x9C,0x0D,0x0E,0xF7,0xBD,0x0D,0x4E,0xFB,0xDE,0x0D,0x8F,0x7B,0xFF,0x89,0x20,0x04,0x43,0x09,0x62,0x9D,0x0B,0x09,0xA6,0xBE,0x33,0x09,0xEA,0xDA,0xF9,0x0A,0x2D,0x6B,0x7C,0x0A,0x6E,0x77,0xBD,0x0A,0xAE,0xFB,0xDE,0x88,0xA0,0x04,0x64,0x08,0xE3,0xA5,0x90,0x09,0x29,0x56,0xF9,0x09,0x6D,0xF3,0xBD,0x09,0xAF,0x7B,0xFF,0x88,0x30,0x04,0x66,0x08,0x74,0xB2,0x14,0x08,0xBB,0xE7,0x7C,0x08,0xFE,0xFB,0xFF, + 129, 0x78,0x87,0xD0,0x04,0x87,0x08,0x15,0xBE,0x97,0x08,0x5D,0x73,0xDF,0x87,0x80,0x08,0xA9,0x07,0xC7,0xD3,0x1B,0x08,0x0E,0xFF,0xFF,0x87,0x30,0x04,0xA9,0x07,0x77,0xD7,0x3C,0x07,0xBF,0x7F,0xFF,0x86,0xF0,0x04,0xCC,0x07,0x39,0xE3,0x9E,0x86,0xC0,0x11,0x52,0x07,0x0C,0x73,0xFF,0x86,0x80,0x04,0xCE,0x06,0xCB,0x6F,0xDF,0x86,0x50,0x08,0xF0,0x06,0x9C,0x77,0xFF,0x86,0x20,0x08,0xF0,0x06,0x6C,0x77,0xFF,0x86,0x00,0x19,0xF8,0x06,0x4E,0xFF,0xFF,0x85,0xD0,0x0D,0x75,0x06,0x1E,0x7F,0xFF,0x85,0xA0,0x04,0xF1,0x05,0xED,0x7F,0xFF,0x85,0x80,0x09,0x75,0x05,0xCE,0xFF,0xFF,0x85,0x60,0x11,0xF9,0x05,0xAF,0x7F,0xFF,0x85,0x40,0x16,0x3A,0x85,0x20,0x1E,0x7C,0x85,0x00,0x1E,0x9D, + 129, 0x78,0x84,0xE0,0x1E,0x9D,0x84,0xC0,0x1A,0x5C,0x84,0xA0,0x12,0x1C,0x84,0x80,0x09,0xBA,0x84,0x70,0x26,0xFF,0x84,0x50,0x12,0x7D,0x84,0x30,0x05,0xBA,0x84,0x20,0x1E,0xDE,0x84,0x00,0x09,0xDC,0x83,0xF0,0x1E,0xDF,0x83,0xD0,0x05,0xBC,0x83,0xC0,0x12,0x9E,0x83,0xB0,0x27,0x3F,0x83,0x90,0x09,0xFD,0x83,0x80,0x12,0xBF,0x83,0x70,0x23,0x3F,0x83,0x60,0x33,0x9F,0x83,0x40,0x0A,0x3D,0x83,0x30,0x0E,0x9F,0x83,0x20,0x16,0xFF,0x83,0x10,0x1F,0x3F,0x83,0x00,0x23,0x5F,0x82,0xF0,0x2F,0x9F,0x82,0xE0,0x2F,0x9F,0x82,0xD0,0x2F,0x9F,0x82,0xC0,0x2F,0x9F,0x82,0xB0,0x2F,0x9F,0x82,0xA0,0x2F,0x9F,0x82,0x90,0x2F,0x9F,0x82,0x80,0x23,0x9F,0x82,0x70,0x1F,0x5F,0x82,0x60,0x17,0x3F, + // 129, 0x78,0x82,0x50,0x0E,0xFF,0x82,0x40,0x0A,0x9F,0x82,0x40,0x43,0xFF,0x82,0x30,0x33,0xBF,0x82,0x20,0x23,0x7F,0x82,0x10,0x13,0x3F,0x82,0x00,0x06,0xBF,0x82,0x00,0x3F,0xFF,0x81,0xF0,0x27,0xBF,0x81,0xE0,0x13,0x3F,0x81,0xD0,0x06,0x9F,0x81,0xD0,0x33,0xDF,0x81,0xC0,0x1B,0x7F,0x81,0xB0,0x0A,0xDF,0x81,0xB0,0x3B,0xFF,0x81,0xA0,0x1B,0x7F,0x81,0x90,0x06,0x9F,0x81,0x90,0x33,0xDF,0x81,0x80,0x13,0x5F,0x81,0x80,0x4B,0xFF,0x81,0x70,0x23,0xBF,0x81,0x60,0x0A,0xDF,0x81,0x60,0x33,0xDF,0x81,0x50,0x0F,0x3F,0x81,0x50,0x3F,0xFF,0x81,0x40,0x17,0x7F,0x81,0x40,0x47,0xFF,0x81,0x30,0x17,0x7F,0x81,0x30,0x47,0xFF,0x81,0x20,0x17,0x7F,0x81,0x20,0x47,0xFF,0x81,0x10,0x17,0x7F, + // 129, 0x78,0x81,0x10,0x47,0xFF,0x81,0x00,0x13,0x7F,0x81,0x00,0x3F,0xFF,0x80,0xF0,0x0F,0x5F,0x80,0xF0,0x33,0xFF,0x80,0xE0,0x0B,0x1F,0x80,0xE0,0x27,0xDF,0x80,0xE0,0x53,0xFF,0x80,0xD0,0x17,0x9F,0x80,0xD0,0x3F,0xFF,0x80,0xC0,0x0B,0x1F,0x80,0xC0,0x27,0xDF,0x80,0xC0,0x53,0xFF,0x80,0xB0,0x13,0x7F,0x80,0xB0,0x37,0xFF,0x80,0xA0,0x06,0xFF,0x80,0xA0,0x1B,0x9F,0x80,0xA0,0x3B,0xFF,0x80,0x90,0x06,0xFF,0x80,0x90,0x1B,0x9F,0x80,0x90,0x3B,0xFF,0x80,0x80,0x06,0xFF,0x80,0x80,0x17,0x9F,0x80,0x80,0x33,0xFF,0x80,0x80,0x57,0xFF,0x80,0x70,0x0F,0x5F,0x80,0x70,0x27,0xDF,0x80,0x70,0x47,0xFF,0x80,0x60,0x07,0x1F,0x80,0x60,0x17,0x9F,0x80,0x60,0x2F,0xFF,0x80,0x60,0x4B,0xFF, + // 129, 0x78,0x80,0x50,0x07,0x1F,0x80,0x50,0x13,0x9F,0x80,0x50,0x27,0xDF,0x80,0x50,0x3F,0xFF,0x80,0x50,0x57,0xFF,0x80,0x40,0x0B,0x5F,0x80,0x40,0x1B,0xBF,0x80,0x40,0x2B,0xFF,0x80,0x40,0x3F,0xFF,0x80,0x40,0x53,0xFF,0x80,0x30,0x0B,0x3F,0x80,0x30,0x13,0x7F,0x80,0x30,0x1F,0xBF,0x80,0x30,0x2F,0xFF,0x80,0x30,0x43,0xFF,0x80,0x30,0x57,0xFF,0x80,0x20,0x0B,0x3F,0x80,0x20,0x0F,0x7F,0x80,0x20,0x1F,0xBF,0x80,0x20,0x2B,0xFF,0x80,0x20,0x3B,0xFF,0x80,0x20,0x4B,0xFF,0x80,0x20,0x5B,0xFF,0x80,0x10,0x0B,0x3F,0x80,0x10,0x0F,0x7F,0x80,0x10,0x17,0xBF,0x80,0x10,0x23,0xDF,0x80,0x10,0x2F,0xFF,0x80,0x10,0x3F,0xFF,0x80,0x10,0x4B,0xFF,0x80,0x10,0x57,0xFF,0x80,0x00,0x0B,0x1F, + // 129, 0x78,0x80,0x00,0x0F,0x5F,0x80,0x00,0x17,0x9F,0x80,0x00,0x1F,0xBF,0x80,0x00,0x27,0xDF,0x80,0x00,0x33,0xDF,0x80,0x00,0x3B,0xFF,0x80,0x00,0x47,0xFF,0x80,0x00,0x4F,0xFF,0x80,0x00,0xD7,0xFF,0x80,0x00,0xDF,0xFF,0x80,0x01,0xE3,0xFF,0x80,0x02,0x6B,0xFF,0x80,0x02,0xEB,0xFF,0x80,0x03,0x6F,0xFF,0x80,0x03,0xF3,0xFF,0x80,0x04,0xF3,0xFF,0x80,0x05,0x77,0xFF,0x80,0x05,0xF7,0xFF,0x80,0x06,0x77,0xFF,0x80,0x06,0xFB,0xFF,0x80,0x07,0x7B,0xFF,0x80,0x07,0xFB,0xFF,0x80,0x07,0xFB,0xFF,0x80,0x08,0x7F,0xFF,0x80,0x08,0xFF,0xFF,0x80,0x08,0xFF,0xFF,0x80,0x09,0x7F,0xFF,0x80,0x09,0x7F,0xFF,0x80,0x09,0xFF,0xFF,0x80,0x09,0xFF,0xFF,0x80,0x0A,0x7F,0xFF,0x80,0x0A,0x7F,0xFF, + // 129, 0x78,0x80,0x0A,0xFF,0xFF,0x80,0x0A,0xFF,0xFF,0x80,0x0B,0x7F,0xFF,0x80,0x0B,0x7F,0xFF,0x80,0x0B,0xFF,0xFF,0x80,0x0B,0xFF,0xFF,0x80,0x0B,0xFF,0xFF,0x80,0x0B,0xFF,0xFF,0x80,0x0C,0x7F,0xFF,0x80,0x0C,0x7F,0xFF,0x80,0x0C,0x7F,0xFF,0x80,0x0C,0xFF,0xFF,0x80,0x0C,0xFF,0xFF,0x80,0x0C,0xFF,0xFF,0x80,0x0D,0x7F,0xFF,0x80,0x0D,0x7F,0xFF,0x80,0x0D,0x7F,0xFF,0x80,0x0D,0xFF,0xFF,0x80,0x0D,0xFF,0xFF,0x80,0x0D,0xFF,0xFF,0x80,0x0D,0xFF,0xFF,0x80,0x0D,0xFF,0xFF,0x80,0x0E,0x7F,0xFF,0x80,0x0E,0x7F,0xFF,0x80,0x0E,0x7F,0xFF,0x80,0x0E,0x7F,0xFF,0x80,0x0E,0xFF,0xFF,0x80,0x0E,0xFF,0xFF,0x80,0x0E,0xFF,0xFF,0x80,0x0E,0xFF,0xFF,0x80,0x0E,0xFF,0xFF,0x80,0x0E,0xFF,0xFF, + // 129, 0x78,0x80,0x0F,0x7F,0xFF,0x80,0x0F,0x7F,0xFF,0x80,0x0F,0x7F,0xFF,0x80,0x0F,0x7F,0xFF,0x80,0x0F,0x7F,0xFF,0xFF,0xF0,0x09,0x46,0x80,0x0F,0x7F,0xFF,0x80,0x0F,0x7F,0xFF,0x80,0x0F,0x7F,0xFF,0x80,0x0F,0x7F,0xFF,0x80,0x0F,0x7F,0xFF,0x80,0x0E,0xFF,0xFF,0x80,0x0E,0xFF,0xFF,0x80,0x0E,0xFF,0xFF,0x80,0x0E,0xFF,0xFF,0x80,0x0E,0xFF,0xFF,0x80,0x0E,0xFF,0xFF,0x80,0x0E,0x7F,0xFF,0x80,0x0E,0x7F,0xFF,0x80,0x0E,0x7F,0xFF,0x80,0x0E,0x7F,0xFF,0x80,0x0D,0xFF,0xFF,0x80,0x0D,0xFF,0xFF,0x80,0x0D,0xFF,0xFF,0x80,0x0D,0xFF,0xFF,0x80,0x0D,0x7F,0xFF,0x80,0x0D,0x7F,0xFF,0x80,0x0D,0x7F,0xFF,0x80,0x0D,0x7F,0xFF,0x80,0x0C,0xFF,0xFF,0x80,0x0C,0xFF,0xFF,0x80,0x0C,0xFF,0xFF, + // 129, 0x78,0x80,0x0C,0x7F,0xFF,0x80,0x0C,0x7F,0xFF,0x80,0x0C,0x7F,0xFF,0x80,0x0B,0xFF,0xFF,0x80,0x0B,0xFF,0xFF,0x80,0x0B,0xFF,0xFF,0x80,0x0B,0x7F,0xFF,0x80,0x0B,0x7F,0xFF,0x80,0x0A,0xFF,0xFF,0x80,0x0A,0xFF,0xFF,0x80,0x0A,0x7F,0xFF,0x80,0x0A,0x7F,0xFF,0x80,0x09,0xFF,0xFF,0x80,0x09,0xFF,0xFF,0x80,0x09,0x7F,0xFF,0x80,0x09,0x7F,0xFF,0x80,0x08,0xFF,0xFF,0x80,0x08,0xFF,0xFF,0x80,0x08,0x7F,0xFF,0x80,0x07,0xFB,0xFF,0x80,0x07,0x7B,0xFF,0x80,0x07,0x7B,0xFF,0x80,0x06,0xFB,0xFF,0x80,0x06,0x77,0xFF,0x80,0x05,0xF7,0xFF,0x80,0x04,0xF7,0xFF,0x80,0x04,0x73,0xFF,0x80,0x03,0xF3,0xFF,0x80,0x03,0x6F,0xFF,0x80,0x02,0x6B,0xFF,0x80,0x01,0xE7,0xFF,0x80,0x01,0x5F,0xFF, + // 129, 0x78,0x80,0x00,0xDF,0xFF,0x80,0x00,0x53,0xFF,0x80,0x00,0x4F,0xFF,0x80,0x00,0x3F,0xFF,0x80,0x00,0x37,0xFF,0x80,0x00,0x2B,0xDF,0x80,0x00,0x23,0xBF,0x80,0x00,0x17,0x9F,0x80,0x00,0x13,0x7F,0x80,0x00,0x0B,0x3F,0x80,0x00,0x06,0xFF,0x80,0x10,0x57,0xFF,0x80,0x10,0x47,0xFF,0x80,0x10,0x3B,0xFF,0x80,0x10,0x2B,0xFF,0x80,0x10,0x1F,0xBF,0x80,0x10,0x17,0x9F,0x80,0x10,0x0B,0x5F,0x80,0x10,0x06,0xFF,0x80,0x20,0x57,0xFF,0x80,0x20,0x43,0xFF,0x80,0x20,0x33,0xFF,0x80,0x20,0x27,0xDF,0x80,0x20,0x17,0x9F,0x80,0x20,0x0B,0x5F,0x80,0x20,0x06,0xFF,0x80,0x30,0x4F,0xFF,0x80,0x30,0x3B,0xFF,0x80,0x30,0x2B,0xFF,0x80,0x30,0x1B,0xBF,0x80,0x30,0x0F,0x5F,0x80,0x40,0x5F,0xFF, + // 129, 0x78,0x80,0x40,0x4B,0xFF,0x80,0x40,0x33,0xFF,0x80,0x40,0x1F,0xBF,0x80,0x40,0x0F,0x7F,0x80,0x40,0x06,0xFF,0x80,0x50,0x4B,0xFF,0x80,0x50,0x33,0xFF,0x80,0x50,0x1B,0xBF,0x80,0x50,0x0F,0x5F,0x80,0x60,0x57,0xFF,0x80,0x60,0x3B,0xFF,0x80,0x60,0x1F,0xBF,0x80,0x60,0x0F,0x5F,0x80,0x70,0x53,0xFF,0x80,0x70,0x33,0xFF,0x80,0x70,0x17,0x9F,0x80,0x70,0x06,0xFF,0x80,0x80,0x3F,0xFF,0x80,0x80,0x1F,0xBF,0x80,0x80,0x0B,0x1F,0x80,0x90,0x43,0xFF,0x80,0x90,0x1F,0xBF,0x80,0x90,0x0B,0x1F,0x80,0xA0,0x43,0xFF,0x80,0xA0,0x1F,0xBF,0x80,0xA0,0x06,0xFF,0x80,0xB0,0x3B,0xFF,0x80,0xB0,0x17,0x9F,0x80,0xC0,0x53,0xFF,0x80,0xC0,0x2B,0xDF,0x80,0xC0,0x0B,0x3F,0x80,0xD0,0x3F,0xFF, + // 129, 0x78,0x80,0xD0,0x17,0x9F,0x80,0xE0,0x53,0xFF,0x80,0xE0,0x23,0xBF,0x80,0xE0,0x06,0xDF,0x80,0xF0,0x2B,0xDF,0x80,0xF0,0x0B,0x1F,0x81,0x00,0x33,0xDF,0x81,0x00,0x0F,0x3F,0x81,0x10,0x3F,0xFF,0x81,0x10,0x0F,0x5F,0x81,0x20,0x3B,0xFF,0x81,0x20,0x0F,0x1F,0x81,0x30,0x33,0xDF,0x81,0x30,0x0B,0x1F,0x81,0x40,0x2B,0xBF,0x81,0x40,0x06,0xBF,0x81,0x50,0x1F,0xBF,0x81,0x60,0x4B,0xFF,0x81,0x60,0x13,0x5F,0x81,0x70,0x33,0xDF,0x81,0x70,0x06,0xBF,0x81,0x80,0x1F,0x7F,0x81,0x90,0x3F,0xFF,0x81,0x90,0x0A,0xFF,0x81,0xA0,0x23,0x9F,0x81,0xB0,0x3B,0xFF,0x81,0xB0,0x0A,0xDF,0x81,0xC0,0x1B,0x7F,0x81,0xD0,0x2F,0xBF,0x81,0xE0,0x47,0xFF,0x81,0xE0,0x0E,0xFF,0x81,0xF0,0x1B,0x5F, + // 129, 0x78,0x82,0x00,0x2B,0xBF,0x82,0x10,0x3F,0xFF,0x82,0x10,0x06,0x9F,0x82,0x20,0x0E,0xFF,0x82,0x30,0x17,0x3F,0x82,0x40,0x1F,0x7F,0x82,0x50,0x2F,0x9F,0x82,0x60,0x2F,0xBF,0x82,0x70,0x3F,0xDF,0x82,0x70,0x05,0xFE,0x82,0x80,0x05,0xFE,0x82,0x90,0x05,0xFE,0x82,0xA0,0x05,0xFE,0x82,0xB0,0x05,0xFE,0x82,0xC0,0x05,0xDC,0x82,0xE0,0x2F,0x9F,0x82,0xF0,0x2B,0x7F,0x83,0x00,0x1F,0x3F,0x83,0x10,0x16,0xFF,0x83,0x20,0x0E,0x7E,0x83,0x30,0x05,0xFD,0x83,0x50,0x2B,0x5F,0x83,0x60,0x1A,0xFF,0x83,0x70,0x0E,0x3D,0x83,0x90,0x2F,0x5F,0x83,0xA0,0x16,0xBF,0x83,0xB0,0x09,0xDC,0x83,0xD0,0x1E,0xDF,0x83,0xE0,0x09,0xDC,0x84,0x00,0x1E,0xBE,0x84,0x10,0x05,0x9A,0x84,0x30,0x12,0x3C, + // 129, 0x78,0x84,0x50,0x1E,0xBE,0x84,0x60,0x05,0x57,0x84,0x80,0x09,0x99,0x84,0xA0,0x09,0x98,0x84,0xC0,0x09,0x98,0x84,0xE0,0x09,0x98,0x85,0x00,0x09,0x76,0x05,0x4E,0xFF,0xFF,0x85,0x20,0x05,0x14,0x05,0x6E,0x7F,0xFF,0x85,0x50,0x15,0xF9,0x85,0x70,0x0D,0x75,0x05,0xBE,0x7F,0xFF,0x85,0xA0,0x15,0xF8,0x05,0xEE,0xFF,0xFF,0x85,0xC0,0x08,0xF1,0x06,0x0C,0xFB,0xFF,0x85,0xF0,0x0D,0x32,0x06,0x3C,0xF7,0xFF,0x86,0x20,0x09,0x10,0x06,0x6C,0x73,0xFF,0x86,0x50,0x04,0xCC,0x06,0x9A,0x6B,0xDF,0x86,0x90,0x0D,0x0F,0x06,0xDA,0xEB,0xBF,0x86,0xD0,0x08,0xEC,0x07,0x19,0x5F,0x7D,0x87,0x10,0x04,0x88,0x07,0x56,0x46,0xDA,0x07,0x9E,0x7B,0xFF,0x87,0x60,0x04,0x66,0x07,0xA4,0xB6,0x56, + // 129, 0x78,0x07,0xEC,0xF3,0xBE,0x87,0xC0,0x04,0x45,0x08,0x04,0x2D,0xF2,0x08,0x4B,0x63,0x5C,0x08,0x8E,0xFB,0xFF,0x88,0x30,0x04,0x44,0x08,0x73,0x25,0x8F,0x08,0xB9,0x52,0xF9,0x08,0xFD,0x73,0xBD,0x09,0x3F,0x7B,0xFF,0x88,0xC0,0x04,0x64,0x09,0x03,0x21,0x4C,0x09,0x47,0xC2,0x74,0x09,0x8B,0x5F,0x19,0x09,0xCD,0x6F,0x9C,0x0A,0x0E,0xF7,0xBD,0x0A,0x4F,0x7B,0xDF,0x89,0x60,0x04,0x42,0x09,0xA2,0x14,0xC7,0x09,0xE3,0xA1,0x2B,0x0A,0x26,0x31,0xAE,0x0A,0x67,0xC2,0x11,0x0A,0xA9,0x4A,0x73,0x0A,0xEA,0x52,0xB5,0x0B,0x2B,0x5A,0xF7,0x0B,0x6B,0xE3,0x19,0x0B,0xAC,0xE7,0x5A,0x0B,0xED,0x6B,0x7B,0x0C,0x2D,0xF3,0x9C,0x0C,0x6E,0x73,0xBD,0x0C,0xAE,0xF7,0xBE,0x0C,0xEF,0x7B,0xDE, + // 65, 0x78,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00, + // 2, 0xFE,0x42, + // 2, 0x16,0x00, + // 2, 0xFE,0x16, + // 2, 0x6E,0x10, + // 2, 0xFE,0x6D, + // 2, 0x60,0x01, + // 2, 0x61,0x25, + // 2, 0x62,0x25, + // 2, 0x63,0x17, + // 2, 0x64,0x55, + // 2, 0x65,0x12, + // 2, 0x66,0x00, + // 2, 0x67,0xFF, + // 2, 0x68,0x02, + // 2, 0x69,0x30, + // 2, 0x6A,0x02, + // 2, 0x6B,0xD2, + // 2, 0x70,0x00, + // 2, 0x71,0x00, + // 2, 0x72,0x00, + // 2, 0x73,0x00, + // 2, 0x74,0x00, + // 2, 0x75,0x00, + // 2, 0x76,0x00, + // 2, 0x77,0x00, + // 2, 0x78,0x00, + // 2, 0x79,0x00, + // 2, 0x7A,0x00, + // 2, 0x7B,0x00, + // 2, 0x80,0x00, + // 2, 0x81,0x00, + // 2, 0x82,0x00, + // 2, 0x83,0x00, + // 2, 0x84,0x00, + // 2, 0x85,0x00, + // 2, 0x86,0x00, + // 2, 0x87,0x00, + // 2, 0x88,0x00, + // 2, 0x89,0x00, + // 2, 0x8A,0x00, + // 2, 0x8B,0x00, + // 2, 0x90,0x80, + // 2, 0x91,0x80, + // 2, 0x92,0x00, + // 2, 0xfe,0x16, + // 2, 0x41,0xFF, + // 2, 0x42,0xFF, + // 2, 0x43,0xFF, + // 2, 0xFE,0x00, + // 2, 0xFA,0x01, + // 2, 0xFE,0xD2, + // 2, 0x97,0x08, + // 2, 0x36,0x11, + // 2, 0x39,0x89, + // 2, 0x3A,0x30, + // 2, 0x3B,0x80, + // 2, 0x3D,0x0a, + // 2, 0x3F,0xf0, + // 2, 0x40,0x05, + // 2, 0x41,0x00, + // 2, 0x42,0x00, + // 2, 0x43,0x14, + // 2, 0x44,0x02, //-----0x02 + // 2, 0x45,0x80, //-----0x80 + // 2, 0x46,0x02, //----- + // 2, 0x47,0x80, //----- + // 2, 0x48,0x02, + // 2, 0x49,0x00, + // 2, 0x4A,0x02, + // 2, 0x4B,0x41, + // 2, 0x4D,0x20, + // 2, 0x4E,0x02, + // 2, 0x4F,0x12, + // 2, 0x50,0x00, + // 2, 0x51,0x08, + // 2, 0x53,0x0c, + // 2, 0x54,0x05, + // 2, 0x55,0x0e, + // 2, 0x56,0x04, + // 2, 0x58,0x38, + // 2, 0x59,0x18, + // 2, 0x5A,0x00, + // 2, 0x5B,0x10, + // 2, 0x5C,0xd0, + // 2, 0x5D,0x03, + // 2, 0x5E,0x0c, + // 2, 0x5F,0x20, + // 2, 0x60,0x00, + // 2, 0x61,0x06, + // 2, 0x62,0x0b, + // 2, 0x63,0x0b, + // 2, 0x64,0x33, + // 2, 0x65,0x0e, + // 2, 0x66,0x1c, + // 2, 0x67,0x2a, + // 2, 0x68,0x38, + // 2, 0x69,0x46, + // 2, 0x6A,0x54, + // 2, 0x6B,0x62, + // 2, 0x6C,0x69, + // 2, 0x6D,0x70, + // 2, 0x6E,0x77, + // 2, 0x6F,0x79, + // 2, 0x70,0x7b, + // 2, 0x71,0x7d, + // 2, 0x72,0x7e, + // 2, 0x73,0x01, + // 2, 0x74,0x02, + // 2, 0x75,0x01, + // 2, 0x76,0x00, + // 2, 0x77,0x09, + // 2, 0x78,0x40, + // 2, 0x79,0x09, + // 2, 0x7A,0xbe, + // 2, 0x7B,0x19, + // 2, 0x7C,0xfc, + // 2, 0x7D,0x19, + // 2, 0x7E,0xfa, + // 2, 0x7F,0x19, + // 2, 0x80,0xf8, + // 2, 0x81,0x1a, + // 2, 0x82,0x38, + // 2, 0x83,0x1a, + // 2, 0x84,0x78, + // 2, 0x85,0x1a, + // 2, 0x86,0xb6, + // 2, 0x87,0x2a, + // 2, 0x88,0xf6, + // 2, 0x89,0x2b, + // 2, 0x8A,0x34, + // 2, 0x8B,0x2b, + // 2, 0x8C,0x74, + // 2, 0x8D,0x3b, + // 2, 0x8E,0x74, + // 2, 0x8F,0x6b, + // 2, 0x90,0xf4, + // 2, 0x91,0x00, + // 2, 0x92,0x00, + // 2, 0x93,0x00, + // 2, 0x94,0x00, + // 2, 0x95,0x00, + // 2, 0x96,0x00, + // 2, 0xFE,0xD4, + // 2, 0x0D,0x00, + // 2, 0xFE,0xA1, + // 2, 0x75,0xA7, + // 2, 0xFE,0x42, + // 2, 0x17,0x02, + // 2, 0xFE,0x6A, + // 2, 0x03,0x10, + // 2, 0xFE,0x60, + // 2, 0x00,0xC8, + // 2, 0x1B,0xC8, + // 2, 0x55,0xC0, + // 2, 0xFE,0x00, + // 2, 0x53,0x20, + // 2, 0xFA,0x01, + // 2, 0xC2,0x03, //video-03 cmd 08 + // 2, 0x35,0x00, + // 3, 0x51,0x00,0x00,//0x51,0x05,0x38, + //2, 0xFE,0x97, //--bist + //2, 0x33,0x03, +}; +uint16 cmd_num_type_h39 = 1267 - 160 - 14;//1269; 1267 + +void mipitx_send_packet_type39() +{ + uint16 r,c; + uint16 byte_cnt = 0; + uint8 cmd_byte_length; + uint8 addr; + uint16 cnt_four_byte; + uint8 remain; + write_addr_UINT8(mipi_tx_lp_hs_mode,0x00); //mipi tx lp send cmd enable bit0: 0--lp mode ;1--hs mode + for(r=0;r 0) //send data + { + for(c=0;c= MaxIn) { + return MaxOut; + } + + // 뷶ΧС + unsigned int inRange = (unsigned int)MaxIn - MinIn; + unsigned int xRelative = (unsigned int)(X - MinIn); + + // ΧķȺͷ + unsigned int outRangeMagnitude; + int isIncreasing; + + if (MaxOut >= MinOut) { + outRangeMagnitude = (unsigned int)MaxOut - MinOut; + isIncreasing = 1; + } else { + outRangeMagnitude = (unsigned int)MinOut - MaxOut; + isIncreasing = 0; + } + + // ļ㣺ȳ˺ + unsigned int temp = (xRelative * outRangeMagnitude) / inRange; + + // ݷս + if (isIncreasing) { + return (unsigned int)((unsigned int)MinOut + temp); + } else { + return (unsigned int)((unsigned int)MinOut - temp); + } +} + +void Oled_Diming_Process() +{ + uint16 sdp_min = 0x00B1; + uint16 sdp_max = 0x05C4; //0x05C4 + uint16 dbv_min = 0x0020; //0076 + uint16 dbv_max = 0x00FF; //7EE + uint16 us_DrvIC51WrData = 0; + uint16 dbv_cal = 0; + uint8 mipi_tx_cmd_send_done = 0; + mipi_tx_cmd_send_done = read_addr_UINT8(mipi_tx_send_done) & 0x01; + if ((mipi_tx_cmd_send_done == 1) && (sdp_reflash == 1)) + { + if (sdp51 == 0x0000) { + dbv_cal = 0x0000; +// avdd_on(); //ֻAVDDصELVDD_ELVSSԽʡ + } + else if(sdp51 <= 1199) + { + dbv_cal = LineMap( sdp51, 177, 1199, 0x50, 0xAF ); + } + else + { + dbv_cal = LineMap( sdp51, 1200, 1476, 0xB0, 0xf5 ); + } + // LOG_DEBUG("i%d\n",sdp51);//177-1476 + // LOG_DEBUG("o%d\n",dbv_cal); + hal_dsi_tx_ctrl_write_cmd(0x39, 0, 3, 0x51, dbv_cal >> 8, dbv_cal & 0xFF); + wr_cfgreg(0xF905, (us_DrvIC51WrData >> 8) & 0xFF); + wr_cfgreg(0xF906, us_DrvIC51WrData & 0xFF); + sdp_reflash = 0; + } +} + + +//----״̬ʼ +void Sys_Matchine_Init() +{ + ucPowerState = STATE_TX_POWER_ON; + ucPowerOnExecuted = bfalse; +} + +//-----״̬л +void Sys_Power_State_Change(EnumPowerState newState) +{ + ucPowerState = newState; +} + +//---ϵ绽жִ +void Sys_Power_Executed_State(Enumbool newState) +{ + ucPowerOnExecuted = newState; +} + +//---жִ +void Sys_Sleep_Executed_State(Enumbool newState) +{ + ucSleepExecuted = newState; +} + +//״̬ȡ +EnumPowerState Current_Status_Get(void) +{ + return ucPowerState; +} + +// ״̬ĵȣѭã +void Sys_Power_Handler() +{ + switch (ucPowerState) + { + case STATE_TX_POWER_ON: + if(btrue == ucPowerOnExecuted) + { + power_on_seq(); + Sys_Power_Executed_State(bfalse); + Sys_Sleep_Executed_State(bfalse); + Sys_Power_State_Change(STATE_TX_SLEEP_IN); + LOG_DEBUG("Power On"); + } + break; + case STATE_TX_WAKE_UP: + if (btrue ==ucPowerOnExecuted) + { + wake_up_seq(); + Sys_Power_Executed_State(bfalse); + Sys_Sleep_Executed_State(bfalse); + Sys_Power_State_Change(STATE_TX_SLEEP_IN); + LOG_DEBUG("WAKE up"); + } + break; + case STATE_TX_SLEEP_IN: + if (btrue ==ucSleepExecuted) + { + sleep_in_seq(); + Sys_Sleep_Executed_State(bfalse); + Sys_Power_Executed_State(bfalse); + Sys_Power_State_Change(STATE_TX_WAKE_UP); + LOG_DEBUG("SLEEP IN"); + } + break; + default: + break; + } +} diff --git a/src/code/sub_i2c.c b/src/code/sub_i2c.c new file mode 100644 index 0000000..c89f353 --- /dev/null +++ b/src/code/sub_i2c.c @@ -0,0 +1,402 @@ +#include "la_config.h" + + +//#define AVDD_VOL_VALUE 760 //7.6v +//#define ELVDD_VOL_VALUE 280 //2.8v +//#define ELVSS_VOL_VALUE 460 //-4.6v + + +#if 1 //IO ģI2C + +#define IIC_WADDR 0xA0 + +#define PINID_PMIC_SCL 18 +#define PINID_PMIC_SDA 19 + +#define IO_OUT_H GPIO_HIGH +#define IO_OUT_L GPIO_LOW + +#define gpio_write(pin,status) gpiox_func_write(pin,status) +#define gpio_read_config(pin) gpiox_func_input(pin) +#define gpio_read_status(pin) gpiox_func_read(pin) +void i2c0_master_init() +{ + gpiox_output_high(18); + gpiox_output_high(19); + delay_ms(1); +} + +static void iic_start(void) +{ + gpio_write(PINID_PMIC_SDA, IO_OUT_H); + gpio_write(PINID_PMIC_SCL, IO_OUT_H); + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + gpio_write(PINID_PMIC_SDA, IO_OUT_L); + delay_1us(); + gpio_write(PINID_PMIC_SCL, IO_OUT_L); +} + +static void iic_stop(void) +{ + gpio_write(PINID_PMIC_SCL, IO_OUT_L); + gpio_write(PINID_PMIC_SDA, IO_OUT_L); + delay_1us(); + gpio_write(PINID_PMIC_SCL, IO_OUT_H); + delay_1us(); + gpio_write(PINID_PMIC_SDA, IO_OUT_H); + delay_1us(); +} + +static void iic_ack(void) +{ + gpio_write(PINID_PMIC_SCL, IO_OUT_L); + gpio_write(PINID_PMIC_SDA, IO_OUT_L); + delay_1us(); + delay_1us(); + delay_1us(); + gpio_write(PINID_PMIC_SCL, IO_OUT_H); + delay_1us(); + gpio_write(PINID_PMIC_SCL, IO_OUT_L); +} + +static void iic_noack(void) +{ + gpio_write(PINID_PMIC_SCL, IO_OUT_L); + gpio_write(PINID_PMIC_SDA, IO_OUT_H); + delay_1us(); + delay_1us(); + delay_1us(); + gpio_write(PINID_PMIC_SCL, IO_OUT_H); + delay_1us(); + gpio_write(PINID_PMIC_SCL, IO_OUT_L); +} + +static uint8 iic_read_ack(void) +{ + uint8 ucErrTime = 0; + //PIN_SDA_IN(); + gpio_read_config(PINID_PMIC_SDA); + delay_1us(); + gpio_write(PINID_PMIC_SCL, IO_OUT_H); + delay_1us(); + + while (gpio_read_status(PINID_PMIC_SDA)) + { + ucErrTime++; + if (ucErrTime > 100) //5000 + { + iic_stop(); + return 1; + } + } + gpio_write(PINID_PMIC_SCL, IO_OUT_L); + return 0; +} + +void iic_write_byte(uint8 value) +{ + uint8 i; + gpio_write(PINID_PMIC_SCL, IO_OUT_L); + + for (i = 0; i < 8; i++) + { + if ((value & 0x80) >> 7) + gpio_write(PINID_PMIC_SDA, IO_OUT_H); + else + gpio_write(PINID_PMIC_SDA, IO_OUT_L); + value <<= 1; + delay_1us(); + gpio_write(PINID_PMIC_SCL, IO_OUT_H); + delay_1us(); + gpio_write(PINID_PMIC_SCL, IO_OUT_L); + } +} + +uint8 iic_read_byte(void) +{ + uint8 i = 0; + uint8 dataa = 0; + int gpio_in = 0; + + gpio_write(PINID_PMIC_SDA, IO_OUT_H); + gpio_read_config(PINID_PMIC_SDA); + for (i = 0; i < 8; i++) + { + gpio_write(PINID_PMIC_SCL, IO_OUT_L); + delay_1us(); + delay_1us(); + delay_1us(); + gpio_write(PINID_PMIC_SCL, IO_OUT_H); + dataa <<= 1; + if (gpio_read_status(PINID_PMIC_SDA)) dataa++; //GPIO 2-SDA 0000 0100 + delay_1us(); + } + return dataa; +} + + +void Hiic_WR_Reg(uint8 addr_h, uint8 addr_l, uint8* buf, uint8 len) +{ + uint8 i; + + iic_start(); + + iic_write_byte(IIC_WADDR + 0); //w + if (iic_read_ack() == 1) goto error; +#ifdef ADDR_16 + iic_write_byte(addr_h); + if (iic_read_ack() == 1) goto error; +#endif + iic_write_byte(addr_l); + if (iic_read_ack() == 1) goto error; + + for (i = 0; i < len; i++) + { + iic_write_byte(buf[i]); + if (iic_read_ack() == 1) goto error; + } + + iic_stop(); + +error: + ; +} + +void Hiic_RD_Reg(uint8 addr_h, uint8 addr_l, uint8* buf, uint8 len) +{ + uint8 i; + + iic_start(); + + iic_write_byte(IIC_WADDR + 0); //w + iic_read_ack(); +#ifdef ADDR_16 + iic_write_byte(addr_h); + iic_read_ack(); +#endif + iic_write_byte(addr_l); + iic_read_ack(); + + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + delay_1us(); + + iic_start(); + + iic_write_byte(IIC_WADDR + 1); //r + iic_read_ack(); + + for (i = 0; i < len; i++) + { + buf[i] = iic_read_byte(); + if (i == len - 1) + iic_noack(); + else + iic_ack(); + } + iic_stop(); +} + +void avdd_power_set(uint16 val) +{ + // AVDD 0x00~0x0F 6.5V~8.0V Step=0.1V + uint8 iic_wbuf; + + if ((val >= 650) && (val <= 800)) + { + iic_wbuf = (val - 650) / 10; + } + Hiic_WR_Reg(0x00, 0x03, &iic_wbuf, 1); +} + +void elvdd_power_set(uint16 val) +{ + // ELVDD 0x07~0x0B 2.5V~2.8V Step=0.1V + uint8 iic_wbuf; + + if ((val >= 250) && (val <= 280)) + { + if (val < 260) iic_wbuf = 0x07; + else if (val < 266) iic_wbuf = 0x08; + else if (val < 276) iic_wbuf = 0x09; + else if (val < 280) iic_wbuf = 0x0A; + else iic_wbuf = 0x0B; + } + + Hiic_WR_Reg(0x00, 0x02, &iic_wbuf, 1); +} + +void elvss_power_set(uint16 val) +{ + //ELVSS 0x00~0xA0 -9.00V~-1.00V Step=-0.05V + uint8 iic_wbuf; + + if ((val >= 100) && (val <= 900)) + { + iic_wbuf = 0xA0 - (val - 100) / 5; + } + + Hiic_WR_Reg(0x00, 0x01, &iic_wbuf, 1); +} + +void avdd_on(void) +{ + uint8 iic_wbuf; + //AVDD ON +#ifdef PINID_AVDD_EN + gpio_write(PINID_AVDD_EN, IO_OUT_H); +#endif + iic_wbuf = 0x02; + Hiic_WR_Reg(0x00, 0x09, &iic_wbuf, 1); +} + +void avdd_off(void) +{ + uint8 iic_wbuf; + //AVDD ON +#ifdef PINID_AVDD_EN + gpio_write(PINID_AVDD_EN, IO_OUT_H); +#endif + iic_wbuf = 0x00; + Hiic_WR_Reg(0x00, 0x09, &iic_wbuf, 1); +} + +void elvdd_elvss_on(void) +{ + uint8 iic_wbuf; + #ifdef PINID_SWIRE + gpio_write(PINID_SWIRE, IO_OUT_H); + #endif + iic_wbuf = 0x03; + Hiic_WR_Reg(0x00, 0x09, &iic_wbuf, 1); +} + +void elvdd_elvss_off(void) +{ + uint8 iic_wbuf; + #ifdef PINID_SWIRE + gpio_write(PINID_SWIRE, IO_OUT_H); + #endif + iic_wbuf = 0x02; + Hiic_WR_Reg(0x00, 0x09, &iic_wbuf, 1); +} + +void all_off(void) +{ + uint8 iic_wbuf; +#ifdef PINID_AVDD_EN + gpio_write(PINID_AVDD_EN, IO_OUT_L); +#endif +#ifdef PINID_SWIRE + gpio_write(PINID_SWIRE, IO_OUT_L); +#endif + iic_wbuf = 0x00; + Hiic_WR_Reg(0x00, 0x09, &iic_wbuf, 1); +} + + +#else //------------------IO ʹӲI2C + + +void i2c0_master_init(void) +{ + //I2C0 IO PIN config + gpiox_func_sel(18, BRIDGE_MODE); //Ϊgpio18 ΪPMIC_MCL + gpiox_func_sel(19, BRIDGE_MODE); //Ϊgpio19 ΪPMIC_MDA + + //--------- + /*I2C ʼ*/ + i2c_deinit(I2C0); + i2c_cmd(I2C0, disable); + i2c_clear_allirq(I2C0); + + i2c_addrformat_addr_conifg(I2C0, I2C_MASTERADDR_7BITS, 0x50); //ôӻַַλ 7bit豸ַΪ0x50 + i2c_clock_config(I2C0, SPEED_STANDBT_MODE);//I2Cӻ SPEED_FAST_MODE SPEED_STANDBT_MODE + i2c_gen_restart(I2C0); + + i2c_set_rxthreshold(I2C0, 0x01); //rx_fifoյĸ1ʱRX_FULLж״̬ź + i2c_set_txthreshold(I2C0, 0x08); //tx_fifoʣĸС7ʱTX_EMPTYж״̬ź + i2c_cmd(I2C0, enable); +} + +void avdd_power_set(uint16 val) +{ + uint8_t buff[2] = { 0 }; + if (val < 650) + val = 650; + if (val > 800) + val = 800; + buff[0] = 0x03; + buff[1] = (val - 650) / 10; + i2c_send_poll(I2C0, buff, 2); +} + +void elvdd_power_set(uint16 val) +{ + uint8_t buff[2] = { 0 }; + if (val < 100) + val = 100; + if (val > 900) + val = 900; + buff[0] = 0x01; + buff[1] = 0xA0 - (val - 100) / 5; + i2c_send_poll(I2C0, buff, 2); +} + +void elvss_power_set(uint16 val) +{ + uint8_t buff[2] = { 0 }; + if (val < 250) + val = 250; + if (val > 280) + val = 280; + if (val < 260) + buff[1] = 0x07; + else if (val < 266) + buff[1] = 0x08; + else if (val < 276) + buff[1] = 0x09; + else if (val < 280) + buff[1] = 0x0A; + else + buff[1] = 0x0B; + buff[0] = 0x02; + i2c_send_poll(I2C0, buff, 2); +} + +void avdd_on(void) +{ + UNUSED(0); +} + +void elvdd_elvss_on(void) +{ + UNUSED(0); +} + +void all_off(void) +{ + UNUSED(0); +} + +#endif + + + + diff --git a/src/driver/include/la_config.h b/src/driver/include/la_config.h new file mode 100644 index 0000000..56977da --- /dev/null +++ b/src/driver/include/la_config.h @@ -0,0 +1,60 @@ +/* + *Copyright (c) 2024, sdmicro FAE Team + * + * + * Date Author Notes + * 2024-10-17 FAE first version + */ +#ifndef __LA_CONFIG_H__ +#define __LA_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#include "define.h" +#include "typedef.h" + +#include "la_gpio.h" +#include "la_uart.h" +#include "la_timer.h" +#include "la_wdg.h" +#include "la_dprx.h" +#include "la_spi.h" +#include "la_dma.h" +#include "la_i2c.h" +#include "la_it.h" +#include "la_sys.h" + +#include "ulog.h" + +//------------------------------------------ +#define I2C0_SCL_PIN 18 +#define I2C0_SDA_PIN 19 + +#define I2C1_SCL_PIN 20 +#define I2C1_SDA_PIN 21 + +#define I2C2_SCL_PIN 5 +#define I2C2_SDA_PIN 6 + +#define UNUSED(x) ((void)(x)) + + + +//----------------------W818 TEST FUNCTION +#define W818_TEST_MENU +#ifdef W818_TEST_MENU + +void show_menu(void); +void test_show_menu(void); + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/driver/include/la_dma.h b/src/driver/include/la_dma.h new file mode 100644 index 0000000..693344c --- /dev/null +++ b/src/driver/include/la_dma.h @@ -0,0 +1,403 @@ +/* + *Copyright (c) 2024, sdmicro FAE Team + * + * + * Date Author Notes + * 2024-10-17 FAE first version + */ +#ifndef __LA_DMA_H__ +#define __LA_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "typedef.h" + + +/* DMAC definitions */ +#define DMAC BASE_ADDR_GPDMA + + +/* DMACx(x=0,1,2,3,4..7) definitions */ +typedef enum +{ + DMA_CH0 = 0, /*!< DMA Channel0 */ + DMA_CH1, /*!< DMA Channel1 */ + DMA_CH2, /*!< DMA Channel2 */ + DMA_CH3, /*!< DMA Channel3 */ + DMA_CH4, /*!< DMA Channel4 */ + DMA_CH5, /*!< DMA Channel5 */ + DMA_CH6, /*!< DMA Channel6 */ + DMA_CH7, /*!< DMA Channel7 */ +}dma_channel_enum; + + +/* registers definitions */ +//global enable & crc enable +#define DMAC_CFGREG REG32((DMAC) + 0x00000398U) /*!< globalDMA ahb enable register */ +#define DMA_CHENREG REG32((DMAC) + 0x000003A0U) /*!< DMA chanel enable register */ + +#define CRC_ENREG REG32((DMAC) + 0x000003b8U) /*!< crc enable register */ +#define CRC_RESULTREG REG32((DMAC) + 0x000003c0U) /*!< crc result register */ + +//chanel register +#define DMAC_SAR(channel) REG32((DMAC) + 0x00U + 0x58U * (uint32_t)(channel)) /*!< dma source address transfer register */ +#define DMAC_DAR(channel) REG32((DMAC) + 0x08U + 0x58U * (uint32_t)(channel)) /*!< dma destin address transfer register */ +#define DMAC_LLP(channel) REG32((DMAC) + 0x10U + 0x58U * (uint32_t)(channel)) /*!< dma llp register */ +#define DMAC_CTLL(channel) REG32((DMAC) + 0x18U + 0x58U * (uint32_t)(channel)) /*!< dma ctl register */ +#define DMAC_CTLH(channel) REG32((DMAC) + 0x1CU + 0x58U * (uint32_t)(channel)) /*!< dma ctl register */ +#define DMAC_CFGL(channel) REG32((DMAC) + 0x40U + 0x58U * (uint32_t)(channel)) /*!< dma cfg register */ +#define DMAC_CFGH(channel) REG32((DMAC) + 0x44U + 0x58U * (uint32_t)(channel)) /*!< dma cfg register */ + +//interrupt register --befor mask 仲裁器之前的信号和状态 +#define DMAC_RAWTFR REG32((DMAC) + 0x000002C0U) /*!< dma transfer complete irq befor mask*/ +#define DMAC_RAWBLOCK REG32((DMAC) + 0x000002C8U) /*!< dma block transfer complete irq befor mask*/ +#define DMAC_RAWSRCTRF REG32((DMAC) + 0x000002d0U) /*!< dma src transfer complete irq befor mask*/ +#define DMAC_RAWDSTTFR REG32((DMAC) + 0x000002d8U) /*!< dma dst transfer complete irq befor mask*/ +#define DMAC_RAWERR REG32((DMAC) + 0x000002e0U) /*!< dma err irq befor mask*/ + +//interrupt register---after mask 仲裁器之后的信号和状态 +#define DMAC_STATUSTFR REG32((DMAC) + 0x000002e8U) /*!< dma transfer complete irq after mask*/ +#define DMAC_STATUSBLOCK REG32((DMAC) + 0x000002f0U) /*!< dma block transfer complete irq after mask*/ +#define DMAC_STATUSSRCTRAN REG32((DMAC) + 0x000002f8U) /*!< dma src transfer complete irq after mask*/ +#define DMAC_STATUSDSTTRAN REG32((DMAC) + 0x00000300U) /*!< dma dst transfer complete irq after mask*/ +#define DMAC_STATUSERR REG32((DMAC) + 0x00000308U) /*!< dma err irq after mask*/ + +//mask register--仲裁器 +#define DMAC_MASKTFR REG32((DMAC) + 0x00000310U) /*!< dma transfer complete irq mask*/ +#define DMAC_MASKBLOCK REG32((DMAC) + 0x00000318U) /*!< dma block transfer complete irq mask*/ +#define DMAC_MASKSRCTRAN REG32((DMAC) + 0x00000320U) /*!< dma src transfer complete irq mask*/ +#define DMAC_MASKDSTTRAN REG32((DMAC) + 0x00000328U) /*!< dma dst transfer complete irq mask*/ +#define DMAC_MASKERR REG32((DMAC) + 0x00000330U) /*!< dma err transfer complete irq mask*/ + +//clear register --清中断寄存器 +#define DMAC_CLEARTFR REG32((DMAC) + 0x00000338U) /*!< dma transfer complete clear irq mask*/ +#define DMAC_CLEARBLOCK REG32((DMAC) + 0x00000340U) /*!< dma block transfer complete clear irq mask*/ +#define DMAC_CLEARSRCTRAN REG32((DMAC) + 0x00000348U) /*!< dma src transfer complete clear irq mask*/ +#define DMAC_CLEARDSTTRAN REG32((DMAC) + 0x00000350U) /*!< dma dst transfer complete clear irq mask*/ +#define DMAC_CLEARERR REG32((DMAC) + 0x00000358U) /*!< dma err transfer complete clear irq mask*/ + +//interrupt register--- +#define DMAC_STATUSINT REG32((DMAC) + 0x00000360U) /*!< dma irq */ + + +//bit +#define dma_en BIT(0) +#define dma_ch_en BITS(0,7) +#define dma_ch_wr_en BITS(8,15) +#define dma_crc_en BIT(0) //crc计算，只有ch4,ch5有效，并且同一时间只能一个通道生效 + +/*statusint:0x360,5类中断状态寄存器*/ +#define dma_tfr BIT(0) +#define dma_block BIT(1) +#define dma_srct BIT(2) +#define dma_dstt BIT(3) +#define dma_err BIT(4) + + +#define ctlx_int_en BIT(0) //全局中断使能，总开关。如果这个bit设置为0，仲裁器之前的中断仍旧发生 + +#define llp_dst_en BIT(27) +#define llp_src_en BIT(28) + +#define ch_susp BIT(8) //暂停dma传输，与fifo_empty配合使用可以完全禁用通道 +#define fifo_empty BIT(9) + +#define hs_sel_dst BIT(10) //软件硬件握手请求 +#define hs_sel_src BIT(11) + +#define dst_hs_pol BIT(18) //极性选择 0：高电平有效，1：低电平有效--所有外设都是高电平有效。只能设0 +#define src_hs_pol BIT(19) + +#define reload_src BIT(30) //暂不用 +#define reload_dst BIT(31) + +#define fcmode BIT(0) //暂不用 +#define fifomode BIT(1) //为0，表示满一次burst传输数据量才会开始一次burst传输。为1，表示只要半满或半空就可以开始一次burst传输 + +//----define params +#define D_WIDTH_8 ((0ul&0x07)<<1) +#define D_WIDTH_16 ((1ul&0x07)<<1) +#define D_WIDTH_32 ((2ul&0x07)<<1) + +#define S_WIDTH_8 ((0ul&0x07)<<4) +#define S_WIDTH_16 ((1ul&0x07)<<4) +#define S_WIDTH_32 ((2ul&0x07)<<4) + +#define D_ADD_INC (0ul<<7) +#define D_ADD_DEINC (1ul<<7) +#define D_ADD_NO (1ul<<8) + +#define S_ADD_INC (0ul<<9) +#define S_ADD_DEINC (1ul<<9) +#define S_ADD_NO (1ul<<10) + +#define D_MSIZE_1 (0ul<<11) //每次传输的数据量：1字节 +#define D_MSIZE_4 (1ul<<11) //每次传输的数据量：4字节 +#define D_MSIZE_8 (2ul<<11) //每次传输的数据量：8字节 +#define D_MSIZE_16 (3ul<<11) //每次传输的数据量：16字节 +#define D_MSIZE_32 (4ul<<11) //每次传输的数据量：32字节 +#define D_MSIZE_64 (5ul<<11) //每次传输的数据量：64字节 + + +#define S_MSIZE_1 (0ul<<14) +#define S_MSIZE_4 (1ul<<14) +#define S_MSIZE_8 (2ul<<14) +#define S_MSIZE_16 (3ul<<14) +#define S_MSIZE_32 (4ul<<14) +#define S_MSIZE_64 (5ul<<14) + + +#define MEMORY_TO_MEMORY ((0ul&0x07)<<20) //DW_AHB_DMAC +#define MEMORY_TO_PERIP ((1ul&0x07)<<20) //DW_AHB_DMAC +#define PERIP_TO_MEMORY ((2ul&0x07)<<20) //DW_AHB_DMAC +#define PERIP_TO_PERIP ((3ul&0x07)<<20) //DW_AHB_DMAC +//#define PERIP_TO_MEMORY (4ul<<20) //Peripheral,暂不用 +//#define PERIP_TO_PERIP (5ul<<20) //source Peripheral，暂不用 +//#define MEMORY_TO_PERIP (6ul<<20) //Peripheral，暂不用 +//#define PERIP_TO_PERIP (7ul<<20) //Destination Peripheral，暂不用 + +#define DEST_MASTER_PERIP (0ul<<23) +#define DEST_MASTER_MEMORY (1ul<<23) + +#define SRC_MASTER_PERIP (0ul<<25) +#define SRC_MASTER_MEMORY (1ul<<25) + +#define LLP_D_EN (1ul<<27) +#define LLP_D_DIS (0ul<<27) +#define LLP_S_EN (1ul<<28) +#define LLP_S_DIS (0ul<<28) + +#define DONE (1ul<<17) // 启动dma完成中断 + +#define CH_SUSP (1ul<<8) +#define HS_HARD_DST (0ul<<10) +#define HS_HARD_SRC (0ul<<11) +#define DST_HS_POL_L (1ul<<18) +#define SRC_HS_POL_L (1ul<<19) + +#define S_RELOAD_EN (1ul<<30) +#define S_RELOAD_DIS (0ul<<30) + + +#define D_RELOAD_EN (1ul<<31) +#define D_RELOAD_DIS (0ul<<31) + +#define SINGLE_TRANSFER_WITH 0 +#define BEGGER_THAN_HALF 1 + + + +typedef struct +{ + uint32_t s_addr; + uint32_t d_addr; + uint32_t s_width; /**< Source Transfer Width , should be one of the following: + - S_WIDTH_8 + - S_WIDTH_16 + - S_WIDTH_32 + */ + uint32_t d_width; /**< Destination Transfer Width , should be one of the following: + - D_WIDTH_8 + - D_WIDTH_16 + - D_WIDTH_32 + */ + uint32_t s_addr_inc; /**< Source Address Increment , should be one of the following: + - S_ADD_INC + - S_ADD_DEINC + - S_ADD_NO + */ + uint32_t d_addr_inc;/**< Destination Address Increment , should be one of the following: + - D_ADD_INC + - D_ADD_DEINC + - D_ADD_NO + */ + uint32_t s_msize; /*should be one of the following: + - S_MSIZE_1 + - S_MSIZE_4 + - S_MSIZE_8 + - S_MSIZE_16 + - S_MSIZE_32 + - S_MSIZE_64 + */ + uint32_t d_mszie; /*should be one of the following: + - D_MSIZE_1 + - D_MSIZE_4 + - D_MSIZE_8 + - D_MSIZE_16 + - D_MSIZE_32 + - D_MSIZE_64 + */ + uint32_t transfer_type; /**< Transfer Type , should be one of the following: + - MEMORY_TO_MEMORY + - MEMORY_TO_PERIP + - PERIP_TO_MEMORY + - PERIP_TO_PERIP + */ + uint32_t d_master; /**< Transfer Type , should be one of the following: + - DEST_MASTER_PERIP + - DEST_MASTER_MEMORY + */ + + uint32_t s_master; /**< Transfer Type , should be one of the following: + - SRC_MASTER_PERIP + - SRC_MASTER_MEMORY + */ + uint32_t buff_size; /**< Length/Size of transfer，单位是s_width/8 + */ + + uint32_t llp; /**< Linker List Item structure data address,if there's no Linker List, set as '0' */ + uint32_t llp_d_en; + uint32_t llp_s_en; + uint32_t reload_s_addr; /**< Automatic Source Reload , should be one of the following: + - S_RELOAD_EN + - S_RELOAD_DIS + */ + uint32_t reload_d_addr; /**< Automatic Destination Reload , should be one of the following: + - D_RELOAD_EN + - D_RELOAD_DIS + */ + + uint32_t fifo_mode; // 0: single transfer width 1: >=half fifo depth + uint32_t s_interface; /**< Assigns a hardware handshaking interface for source peripheral , should be one of the following: + - 0,// + - 1,//, + - 2,//, + - 3,//, + - 4,//, + */ + uint32_t d_interface; /**< Assigns a hardware handshaking interface for destination peripheral , should be one of the following: + - 0,// + - 1,//, + - 2,//, + - 3,//, + - 4,//, + */ + +}DMA_InitTypeDef; + + +typedef struct { + uint32_t s_add; /**< Source Address */ + uint32_t d_add; /**< Destination address */ + uint32_t nextlli; /**< Next LLI address, otherwise set to '0' */ + uint32_t ctrl; /**< DMA Control of this LLI */ + uint32_t ctrh; +} DMA_lli_str; + + +typedef enum { + DMA_IT_BLOCK, //This interrupt is generated on DMA block transfer completion to the destination peripheral. + DMA_IT_DST, //Destination Transaction Complete Interrupt + DMA_IT_SRC, //Source Transaction Complete Interrupt + DMA_IT_ERR, //Error Interrupt + DMA_IT_TFR //DMA Transfer Complete Interrupt + +} DMA_IT_TYPE; + + + + +/************************************************ +* @func: dma 恢复默认状态 +* @param dma channel +* @retval None +*************************************************/ +void dma_deinit(dma_channel_enum channel); + + +/************************************************ +* @func: dma CRC使能 +* @param dma channel +* @retval None +*************************************************/ +void dma_crc_enable(dma_channel_enum channel); + + +/************************************************ +* @func: dma 获取CRC结果 +* @param dma channel +* @retval crc result +*************************************************/ +uint8 dma_get_crc_result(dma_channel_enum channel); + + +/************************************************ +* @func: dma IRQ +* @param dma channel +* @param status:enable/disable +* @retval crc result +*************************************************/ +void dma_itconfig(dma_channel_enum channel, funcstate state); + + +/************************************************ +* @func: dma IRQ +* @param dma channel +* @retval crc result +*************************************************/ +int dma_init(dma_channel_enum channel, DMA_InitTypeDef* p); + + +/************************************************ +* @func: dma 通道使能 +* @param channel +* @param status:enable/disable +* @retval None +*************************************************/ +void dma_cmd(dma_channel_enum channel, funcstate state); + + +/************************************************ +* @func: 获取dma中断类型 +* @param channel +* @param five irq type +* @retval 0/1 +*************************************************/ +intstatus dma_get_itflag(dma_channel_enum channel, DMA_IT_TYPE type); + + +/************************************************ +* @func: clear IRQ +* @param channel +* @param five irq type +* @retval NONE +*************************************************/ +void dam_clear_itflag(dma_channel_enum channel, DMA_IT_TYPE type); + + +/************************************************ +* @func: dma 传输数据 +* @param channel +* @param status:enable/disable +* @retval None +*************************************************/ +void dma_transfer(dma_channel_enum channel, uint32 len); + +/************************************************ +* @func: dma 传输数据 +* @param channel +* @param src addr +* @param dst addr +* @param lenth +* @retval None +*************************************************/ +void dma_m2m_xfer(dma_channel_enum channel, uint32 src_addr, uint32 dst_addr, uint32 len); + + +/************************************************ +* @func: dma 传输数据 +* @param channel +* @param src addr +* @param lenth +* @retval None +*************************************************/ +void dma_m2p_xfer(dma_channel_enum channel, uint32 src_addr, uint32 len); + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/driver/include/la_dprx.h b/src/driver/include/la_dprx.h new file mode 100644 index 0000000..c14a3f2 --- /dev/null +++ b/src/driver/include/la_dprx.h @@ -0,0 +1,133 @@ +/* + *Copyright (c) 2024, sdmicro FAE Team + * + * + * Date Author Notes + * 2024-10-17 FAE first version + */ +#ifndef __LA_DPRX_H__ +#define __LA_DPRX_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "typedef.h" +#include "define.h" + +typedef struct SdpInfo +{ + uint8 SDP_HB[4]; + uint8 SDP_DB[32]; + uint8 SDP_ERR_FLAG[4]; +} Sdp_TypeDef; + + +typedef struct AuxInfo +{ + uint32_t addr; + uint8_t len; + uint8_t cmd; + uint8_t data[16]; +}Aux_TypeDef; + + +/* definitions */ +#define DPCD BASE_ADDR_DPCD +#define SDP BASE_ADDR_DPRX_SDP +#define AUX BASE_ADDR_DPRX_SDP+0x40 +#define EDID BASE_ADDR_DPRX_SDP+0x60 +/*register define*/ +#define DPCDReg(x) REG8((DPCD) + x) + +#define SdPackHB0Reg REG32((SDP) + 0x00000000U) +#define SdPackDB0Reg REG32((SDP) + 0x00000004U) +#define SdPackDB4Reg REG32((SDP) + 0x00000008U) +#define SdPackDB8Reg REG32((SDP) + 0x0000000CU) +#define SdPackDB12Reg REG32((SDP) + 0x00000010U) +#define SdPackDB16Reg REG32((SDP) + 0x00000014U) +#define SdPackDB20Reg REG32((SDP) + 0x00000018U) +#define SdPackDB24Reg REG32((SDP) + 0x0000001CU) +#define SdPackDB28Reg REG32((SDP) + 0x00000020U) +#define SdPackErrReg REG32((SDP) + 0x00000024U) + +//#define aux packet +#define AuxPack0Reg REG32((AUX) + 0x00000000U) // +#define AuxPack1Reg REG32((AUX) + 0x00000004U) +#define AuxPack2Reg REG32((AUX) + 0x00000008U) +#define AuxPack3Reg REG32((AUX) + 0x0000000CU) +#define AuxPack4Reg REG32((AUX) + 0x00000010U) + +//#define edid +#define EdidData0Reg REG32((EDID) + 0x00000000U) // +#define EdidData1Reg REG32((EDID) + 0x00000004U) // +#define EdidData2Reg REG32((EDID) + 0x00000008U) // +#define EdidData3Reg REG32((EDID) + 0x0000000CU) // +#define EDIDACKReg REG32((EDID) + 0x00000010U) // + +//define aux read or write select reg +#define AuxwrReg REG32((SDP) + 0x00000080U) // + + +//IRQжϽ뵽IRQ11ģ飬ҪжϣIRQ13ģ飬Ҫ +//define aux irq clear +#define AuxIRQClearReg REG32((SDP) + 0x000000C0U) // +#define AuxIRQEnableReg REG32((SDP) + 0x000000C4U) // + + + +//************************************************************************ +/*@func:dpcd Ĵ + *@para1: dpcdַ + *@return :ص8bit +*/ +uint8 read_dpcd(uint32 offt); + +//************************************************************************ +/*@func:dpcd Ĵд + *@para1дdata + *@para2: dpcdַ +*/ +void write_dpcd(uint32 offt, uint8 data); + +//************************************************************************ +/*@func:sdp Ĵȥ + *@para1:ṹָ + *@return : +*/ +void sdp_packet_read(Sdp_TypeDef* p); + +//************************************************************************ +/*@func:ѡsinkصݴdata0~15Ĵ,ͿԶsinkصֵ + *@para: + *@return : +*/ +void aux_read_sink_set(void); + +//************************************************************************ +/*@func:ȡauxdata0~data15Ĵݣauxжʱ + * AuxwrReg =1ʱsinkݰȻֻsourceݰ + *@para:ṹָ + *@return : +*/ +void aux_packet_read(Aux_TypeDef* p); + +//************************************************************************ +/*@func:auxжϽ뵽 mcu_ext_irq00 жȥΪIRQ13ģһͨжϣΪרжϣռһж + *@para: mcu_ext1_ir_en=0 + *@return : +*/ +void aux_irq_set_irq13(void); + + + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/src/driver/include/la_gpio.h b/src/driver/include/la_gpio.h new file mode 100644 index 0000000..9cc5f01 --- /dev/null +++ b/src/driver/include/la_gpio.h @@ -0,0 +1,48 @@ +/* + *Copyright (c) 2024, sdmicro FAE Team + * + * + * Date Author Notes + * 2024-10-17 FAE first version + */ +#ifndef __LA_GPIO_H__ +#define __LA_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "typedef.h" + + +#define IO_MODE 00 //function0 +#define BRIDGE_MODE 01 //function1 +#define TCON_MODE 02 //function2 +#define DEBUG_MODE 03 //function3 + +#define ENABLE 1 +#define DISABLE 0 + + +#define GPIO_HIGH 0x07 +#define GPIO_LOW 0x03 + +void gpiox_func_sel(uint8 pin, uint8 mode); +void gpiox_set_power_level(void); +void gpiox_set_debug_signal(uint8 pin, uint16 bus, uint8 sel); +void gpiox_func_enable(uint8 pin, uint8 stat); +void gpiox_func_input(uint8 pin); +void gpiox_func_output(uint8 pin); +void gpiox_func_write(uint8 pin, uint8 stat); +uint8 gpiox_func_read(uint8 pin); +uint8 gpix_func_enable(uint8 pin, uint8 stat); +uint8 gpix_func_read(uint8 pin); + +void gpiox_output_high(uint8 pin); +void gpiox_output_low(uint8 pin); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/driver/include/la_i2c.h b/src/driver/include/la_i2c.h new file mode 100644 index 0000000..de34860 --- /dev/null +++ b/src/driver/include/la_i2c.h @@ -0,0 +1,421 @@ +/* + *Copyright (c) 2024, sdmicro FAE Team + * + * + * Date Author Notes + * 2024-10-17 FAE first version + */ +#ifndef __LA_I2C_H__ +#define __LA_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "typedef.h" +#include "define.h" + +#define I2C0 BASE_ADDR_I2C0_M //ӲIO map gpio8/9 +#define I2C1 BASE_ADDR_I2C1_M //ӲIO map gpio10/11 +#define I2C2 BASE_ADDR_I2C_S //ӲIO map gpio5_comb/gpio6_comb + + +/*i2c register define*/ +#define IC_CON(i2cx) REG32((i2cx) + 0x00000000U) //I2C CTRL +#define IC_TAR(i2cx) REG32((i2cx) + 0x00000004U) //master access slaver addr +#define IC_SAR(i2cx) REG32((i2cx) + 0x00000008U) //I2C CTRL +#define IC_DATA_CMD(i2cx) REG32((i2cx) + 0x00000010U) //the data to be transmitted or received on the I2C bus. +#define IC_SS_SCL_HCNT(i2cx) REG32((i2cx) + 0x00000014U) //master access slaver addr +#define IC_SS_SCL_LCNT(i2cx) REG32((i2cx) + 0x00000018U) //master access slaver addr +#define IC_FS_SCL_HCNT(i2cx) REG32((i2cx) + 0x0000001cU) //master access slaver addr +#define IC_FS_SCL_LCNT(i2cx) REG32((i2cx) + 0x00000020U) //master access slaver addr +#define IC_INTR_STAT(i2cx) REG32((i2cx) + 0x0000002CU) //master access slaver addr +#define IC_INTR_MASK(i2cx) REG32((i2cx) + 0x00000030U) //master access slaver addr +#define IC_RAW_INTR_STAT(i2cx) REG32((i2cx) + 0x00000034U) //master access slaver addr +#define IC_RX_TL(i2cx) REG32((i2cx) + 0x00000038U) //master access slaver addr +#define IC_TX_TL(i2cx) REG32((i2cx) + 0x0000003CU) //master access slaver addr +#define IC_CLR_INTR(i2cx) REG32((i2cx) + 0x00000040U) //master access slaver addr +#define IC_CLR_RX_UNDER(i2cx) REG32((i2cx) + 0x00000044U) //master access slaver addr +#define IC_CLR_RX_OVER(i2cx) REG32((i2cx) + 0x00000048U) //master access slaver addr +#define IC_CLR_TX_OVER(i2cx) REG32((i2cx) + 0x0000004CU) //master access slaver addr +#define IC_CLR_RD_REQ(i2cx) REG32((i2cx) + 0x00000050U) //master access slaver addr +#define IC_CLR_TX_ABRT(i2cx) REG32((i2cx) + 0x00000054U) //master access slaver addr +#define IC_CLR_RX_DONE(i2cx) REG32((i2cx) + 0x00000058U) //master access slaver addr +#define IC_CLR_ACTIVITY(i2cx) REG32((i2cx) + 0x0000005CU) //master access slaver addr +#define IC_CLR_STOP_DET(i2cx) REG32((i2cx) + 0x00000060U) //master access slaver addr +#define IC_CLR_START_DET(i2cx) REG32((i2cx) + 0x00000064U) //master access slaver addr +#define IC_CLR_GEN_CALL(i2cx) REG32((i2cx) + 0x00000068U) //master access slaver addr +#define IC_ENABLE(i2cx) REG32((i2cx) + 0x0000006CU) //master access slaver addr +#define IC_STATUS(i2cx) REG32((i2cx) + 0x00000070U) //master access slaver addr +#define IC_SDA_HLOD(i2cx) REG32((i2cx) + 0x0000007CU) //master access slaver addr +#define IC_DMA_CR(i2cx) REG32((i2cx) + 0x00000088U) //master access slaver addr +#define IC_DMA_TDLR(i2cx) REG32((i2cx) + 0x0000008CU) //master access slaver addr +#define IC_DMA_RDLR(i2cx) REG32((i2cx) + 0x00000090U) //master access slaver addr +#define IC_SDA_SETUP(i2cx) REG32((i2cx) + 0x00000094U) //master access slaver addr +#define IC_FS_SPKLEN(i2cx) REG32((i2cx) + 0x000000A0U) //master access slaver addr + + +/* bits definitions */ +/* I2Cx_CTL0 */ +#define MASTER_MODE BIT(0) /*!< master i2c enable */ +#define IC_10BITADDR_SLAVE BIT(3) +#define IC_10BITADDR_MASTER BIT(4) +#define IC_RESTART_EN BIT(5) +#define IC_SLAVE_DISABLE BIT(6) +#define STOP_DET_IFADDRESSED BIT(7) /*use in i2c slaver*/ + +#define I2C_DATA BITS(0,7) +#define I2C_READ_CMD BIT(8) +#define I2C_STOP BIT(9) /*WRITE ONLY*/ +#define I2C_RESTART BIT(10) /*WRITE ONLY*/ +#define FIRST_DATA_BYTE BIT(11) /*READ ONLY*/ + +#define CLR_INTR BIT(0) +#define CLR_RX_UNDER BIT(0) +#define CLR_RX_OVER BIT(0) +#define CLR_TX_OVER BIT(0) +#define CLR_RD_REQ BIT(0) +#define CLR_TX_ABRT BIT(0) +#define CLR_RX_DONE BIT(0) +#define CLR_ACTIVITY BIT(0) +#define CLR_STOP_DET BIT(0) +#define CLR_START_DET BIT(0) +#define CLR_GEN_CALL BIT(0) +#define CLR_TX_ABRT BIT(0) + +#define I2C_ENABLE BIT(0) + +#define TDMAE BIT(0) +#define RDMAE BIT(1) + +/*define params*/ +/*I2C master/slaver select */ +#define I2C_MASTER_ENABLE MASTER_MODE +//#define I2C_MASTER_DISABLE ((uint32_t)0x00000000U) +//#define I2C_SLAVER_DISABLE IC_SLAVE_DISABLE +#define I2C_SLAVER_ENABLE ((uint32_t)0x00000000U) + +/*i2c speed*/ +#define SPEED_STANDBT_MODE (0x02U ) /*!< standard mode (0 to 100 Kb/s) */ +#define SPEED_FAST_MODE (0x04U ) /*!< fast mode ( 400 Kb/s) or fast mode plus ( 1000 Kb/s) */ +//#define SPEED_HIGHT_MODE (0x03U << 1) /*!< high speed mode ( 3.4 Mb/s) */ + +/* address mode for the I2C slave */ +#define I2C_SLAVERADDR_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ +#define I2C_SLAVERADDR_10BITS IC_10BITADDR_SLAVE /*!< address:10 bits */ + + +/* address mode for the I2C master */ +#define I2C_MASTERADDR_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ +#define I2C_MASTERADDR_10BITS IC_10BITADDR_SLAVE /*!< address:10 bits */ + +/*i2c restart*/ +#define I2C_RESTART_DISABLE ((uint32_t)0x00000000U) /*!< disable */ +#define I2C_RESTART_ENABLE IC_RESTART_EN /*!< enable */ + +/*use in slave mode to */ +#define STOP_DET_IFADDRESSED_ONLY STOP_DET_IFADDRESSED /*issues the STOP_DET interrrupt only when it is addressed.*/ +#define STOP_DET_IFADDRESSED_WHETHER ((uint32_t)0x00000000U) /*issues the STOP_DET irrespective of whether its addressed or not.*/ + + +#define I2C_CLK 50000000 + +typedef enum{ + I2C_RX_UNDER =0, // Set if the processor attempts to read + // the receive FIFO when it is empty. + I2C_RX_OVER, // Set if the receive FIFO was + // completely filled and more data + // arrived. That data is lost. + I2C_RX_FULL, // Set when the transmit FIFO reaches or + // goes above the receive FIFO + // threshold. It is automatically + // cleared by hardware when the receive + // FIFO level goes below the threshold. + I2C_TX_OVER, // Set during transmit if the transmit + // FIFO is filled and the processor + // attempts to issue another I2C command + // (read request or write). + I2C_TX_EMPTY, // Set when the transmit FIFO is at or + // below the transmit FIFO threshold + // level. It is automatically cleared by + // hardware when the transmit FIFO level + // goes above the threshold. + I2C_RD_REQ, // Set when the I2C is acting as a slave + // and another I2C master is attempting + // to read data from the slave. + I2C_TX_ABRT, // In general, this is set when the I2C + // acting as a master is unable to + // complete a command that the processor + // has sent. + I2C_RX_DONE, // When the I2C is acting as a + // slave-transmitter, this is set if the + // master does not acknowledge a + // transmitted byte. This occurs on the + // last byte of the transmission, + // indicating that the transmission is + // done. + I2C_ACTIVITY, // This is set whenever the I2C is busy + // (reading from or writing to the I2C + // bus). + I2C_STOP_DET, // Indicates whether a stop condition + // has occurred on the I2C bus. + I2C_START_DET, // Indicates whether a start condition + // has occurred on the I2C bus. + I2C_GEN_CALL, // Indicates that a general call request + // was received. The I2C stores the + // received data in the receive FIFO. + I2C_RESTART_DET, //unsed + I2C_MST_ON_HOLD, //unsed +}I2C_IT_TYPE; + + +typedef enum { + ACTIVITY =0, //I2C Activity Status. + TFNF, //Transmit FIFO Not Full + TFE, //Transmit FIFO Completely Empty + RFNE, //Receive FIFO Not Empty + RFF, //Receive FIFO Completely Full + MST_ACTIVITY, //Master FSM Activity Status + SLV_ACTIVITY, //Slave FSM Activity Status + MST_HOLD_TX_FIFO_EMPTY, //masterһݣIC_CMD_DATA.stopδ1ʱbitߣʾmaster holdbus + MST_HOLD_RX_FIFO_FULL, //This bit indicates the BUS Hold in Master mode due to Rx FIFO isFull and additional byte has been received + SLV_HOLD_TX_FIFO_EMPTY,//This bit indicates the BUS Hold in Slave mode for the Read request when the Tx FIFO is empty. The Bus is in hold until the Tx FIFO has data to Transmit for the read request. + SLV_HOLD_RX_FIFO_FULL,//This bit indicates the BUS Hold in Slave mode for the Read request + //when the Tx FIFO is empty. +}I2C_STATUS; + +/* Slave Transmitter ---------------------------------------------------*/ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED 0x80 //ӻһֽڽж +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING 0x20 //ӻж +//#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED //ַƥж +/* Slave Receiver ------------------------------------------------------*/ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED 0x04 //ݽж +#define I2C_EVENT_SLAVE_STOP_DETECTED 0x200 //ֹͣʱһstopź +#define I2C_EVENT_SLAVE_START_DETECTED 0x400 //ʼʱһstartź + + +/* function declarations */ +/************************************************ +* @func: i2c deinit +* @param i2cx:(x=0,1,3) +* @retval NONE +*************************************************/ +void i2c_deinit(uint32_t i2cx); + + +/************************************************ +* @func: i2c_addrformat_addr_conifg +* @param i2cx:(x=0,1,3) +* @param addformat: +* I2C_MASTERADDR_7BITS/I2C_MASTERADDR_10BITS +* I2C_SLAVERADDR_7BITS/I2C_SLAVERADDR_10BITS +* @param addr: I2C slaver address +* @retval NONE +*************************************************/ +void i2c_addrformat_addr_conifg(uint32 i2cx, uint32 addformat, uint32 addr); + + +/************************************************ +* @func: i2c_clock_config +* @param i2cx:(I2Cx=0,1,2) +* @param speed: +* -SPEED_STANDBT_MODE +* -SPEED_FAST_MODE +* -SPEED_HIGHT_MODE +* @param addr: I2C slaver address +* @retval NONE +*************************************************/ +void i2c_clock_config(uint32 i2cx, uint32 speed); + + +/************************************************ +* @func: i2c_gen_restart +* @param i2cx:(I2Cx=0,1,2) +* @retval NONE +*************************************************/ +void i2c_gen_restart(uint32 i2cx); + + +/************************************************ +* @func: i2c_stop +* @param i2cx:(I2Cx=0,1,2) +* @retval NONE +*************************************************/ +void i2c_stop(uint32 i2cx); + + +/************************************************ +* @func: i2c_write +* @param i2cx:(I2Cx=0,1,2) +* @param byte: +* @retval NONE +*************************************************/ +void i2c_write(uint32 i2cx, uint32 byte); + + +/************************************************ +* @func: i2c_issue_read:i2c send a read signal +* @param i2cx:(I2Cx=0,1,2) +* @retval NONE +*************************************************/ +void i2c_issue_read(uint32 i2cx); + + +/************************************************ +* @func: i2c_read +* @param i2cx:(I2Cx=0,1,2) +* @retval NONE +*************************************************/ +uint8 i2c_read(uint32 i2cx); + + +/************************************************ +* @func: i2c_itconfig +* @param i2cx:(I2Cx=0,1,2) +* @param irq: I2C_IT_TYPE enum +* @param state: funcstate enum +* @retval NONE +*************************************************/ +void i2c_itconfig(uint32 i2cx, I2C_IT_TYPE irq, funcstate state); + + +/************************************************ +* @func: i2c_cmd +* @param i2cx:(I2Cx=0,1,2) +* @param state: funcstate enum +* @retval NONE +*************************************************/ +void i2c_cmd(uint32 i2cx, funcstate state); + + +/************************************************ +* @func: i2c_clear_irqflag,read bit will clear +* @param i2cx:(I2Cx=0,1,2) +* @param irq: I2C_IT_TYPE enum +* @retval NONE +*************************************************/ +void i2c_clear_irqflag(uint32 i2cx, I2C_IT_TYPE irq); + + +/************************************************ +* @func: i2c_clear_irqflag,read bit will clear I2C_IT_TYPE irq,but otherwise rx_full/tx_empty +* @param i2cx:(I2Cx=0,1,2) +* @param irq: I2C_IT_TYPE enum +* @retval NONE +*************************************************/ +void i2c_clear_allirq(uint32 i2cx); + + +/************************************************ +* @func: i2c_get_itflag,read I2C_IT_TYPE irqflag +* @param i2cx:(I2Cx=0,1,2) +* @param irq: I2C_IT_TYPE enum +* @retval NONE +*************************************************/ +intstatus i2c_get_itflag(uint32 i2cx, I2C_IT_TYPE type); + + +/************************************************ +* @func: i2c_get_itflag,read I2C_IT_TYPE irqflag +* @param i2cx:(I2Cx=0,1,2) +* @param irq: I2C_STATUS enum +* @retval NONE +*************************************************/ +intstatus i2c_get_status(uint32 i2cx, I2C_STATUS type); + + +/************************************************ +* @func: i2c_set_rxthreshold +* @param i2cx:(I2Cx=0,1,2) +* @param rxthreshold: 1byte val +* @retval NONE +*************************************************/ +intstatus i2c_set_rxthreshold(uint32 i2cx, uint8 rxthreshold); + + +/************************************************ +* @func: i2c_set_txthreshold +* @param i2cx:(I2Cx=0,1,2) +* @param txthreshold: 1byte val +* @retval NONE +*************************************************/ +intstatus i2c_set_txthreshold(uint32 i2cx, uint8 txthreshold); + + +/************************************************ +* @func: i2c_dma_req_config: + rx_fifoյݸDMARDLʱdmareqdma˽rx_fifoݰߣλޣΪFIFO 8߶3bit +* @param i2cx:(I2Cx=0,1,2) +* @param dmardl: +* @retval NONE +*************************************************/ +void i2c_rxdma_req_config(uint32 i2cx, uint8 dmardl); + + +/************************************************ +* @func: i2c_dma_req_config: + tx_fifoеָСDMATDLʱdmareqdmaݵi2cλޣΪFIFO 8߶3bit +* @param i2cx:(I2Cx=0,1,2) +* @param dmatdl: +* @retval NONE +*************************************************/ +void i2c_txdma_req_config(uint32 i2cx, uint8 dmatdl); + + +/* +* @param i2cx:(I2Cx=0,1,2) +1.Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. + 0 = Transmit DMA disabled + 1 = Transmit DMA enabled +*/ +void i2c_rxdma_enable(uint32 i2cx, funcstate state); + + +/* +*param i2cx:(I2Cx=0,1,2) +2.Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. + 0 = Receive DMA disabled + 1 = Receive DMA enabled +*/ +void i2c_txdma_enable(uint32 i2cx, funcstate state); + + +/************************************************ +* @func: i2c_dma_req_config: + 趨I2C_sdaı뽨ʱ +* @param i2cx:(I2Cx=0,1,2) +* @param rxhold: +* @param txhold: +* @param setup: +* @retval NONE +*************************************************/ +void i2c_set_sda_time(uint32 i2cx, uint8 rxhold, uint8 txhold, uint8 setup); + + + +/************************************************ +* @func: i2c_send_poll: + i2c poll write +* @param i2cx:(I2Cx=0,1,2) +* @param buf: +* @param len: +* @retval NONE +*************************************************/ +void i2c_send_poll(uint32 i2cx, uint8* buf, uint8 len); + + +/************************************************ +* @func: i2c_receive_poll: + i2c poll read +* @param i2cx:(I2Cx=0,1) +* @param buf: +* @param len: +* @retval NONE +*************************************************/ +void i2c_receive_poll(uint32 i2cx, uint8* buf, uint8 len); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/driver/include/la_it.h b/src/driver/include/la_it.h new file mode 100644 index 0000000..a979d3a --- /dev/null +++ b/src/driver/include/la_it.h @@ -0,0 +1,113 @@ +#ifndef __LA_IT_H__ +#define __LA_IT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +void wdg_exter_irq_handler(void); +void gpio0_comb_exter_irq_handler(void); +void gpio1_comb_exter_irq_handler(void); +void gpio2_comb_exter_irq_handler(void); +void gpio3_comb_exter_irq_handler(void); +void gpio4_comb_exter_irq_handler(void); +void gpio5_comb_exter_irq_handler(void); +void gpio6_comb_exter_irq_handler(void); +void gpio7_comb_exter_irq_handler(void); +void gpio8_comb_exter_irq_handler(void); +void gpio9_comb_exter_irq_handler(void); + +void gpio0_exter_irq_handler(void); +void gpio1_exter_irq_handler(void); +void gpio2_exter_irq_handler(void); +void gpio3_exter_irq_handler(void); +void gpio4_exter_irq_handler(void); +void gpio5_exter_irq_handler(void); +void gpio6_exter_irq_handler(void); +void gpio7_exter_irq_handler(void); +void gpio8_exter_irq_handler(void); +void gpio9_exter_irq_handler(void); +void gpio10_exter_irq_handler(void); +void gpio11_exter_irq_handler(void); +void gpio12_exter_irq_handler(void); +void gpio13_exter_irq_handler(void); +void gpio14_exter_irq_handler(void); +void gpio15_exter_irq_handler(void); +void gpio16_exter_irq_handler(void); +void gpio17_exter_irq_handler(void); +void gpio18_exter_irq_handler(void); +void gpio19_exter_irq_handler(void); + +void gpiov33_exter_irq_handler(void); +void gpi0_exter_irq_handler(void); +void gpi1_exter_irq_handler(void); +void gpi2_exter_irq_handler(void); +void gpi3_exter_irq_handler(void); +void gpi4_exter_irq_handler(void); +void gpi5_exter_irq_handler(void); + + +void uart_irq_handler(void); +void i2c_slave_irq_handler(void); +void i2c_master_irq_handler(void); +void i2c1_master_irq_handler(void); +void qspi_master_irq_handler(void); +void mbist_irq_handler(void); +void tim0_irq_handler(void); +void tim1_irq_handler(void); +void tim2_irq_handler(void); +void tim3_irq_handler(void); +void tim4_irq_handler(void); +void tim5_irq_handler(void); +void tim6_irq_handler(void); +void tim7_irq_handler(void); +void tim8_irq_handler(void); +void tim9_irq_handler(void); +void tim10_irq_handler(void); +void tim11_irq_handler(void); +void cfgset_irq_handler(void); +void sspi_tch_irq_handler(void); +void sspi_ap_irq_handler(void); +void flash_if_irq_handler(void); +void dma_err_irq_handler(void); +void dma_dst_tran_complete_irq_handler(void); +void dma_src_tran_complete_irq_handler(void); +void dma_block_tran_complete_irq_handler(void); +void dma_dma_tfr_complete_irq_handler(void); +void aux_irq_handler(void); +void sdp_exter_irq_handler(void); +void alpm_phy_sleep_irq_handler(void); +void alpm_phy_standby_irq_handler(void); +void pwr_save_irq_handler(void); +void power_up_irq_handler(void); +void wake_up_irq_handler(void); +void wake_f_change_irq_handler(void); +void hpd_out_irq_handler(void); +void normal_mode_indicator_irq_handler(void); +void vci_pon_rdy_aft_flash_irq_handler(void); +void sslpina_irq_handler(void); +void sslpin_irq_handler(void); +void sdsponorg_irq_handler(void); +void vit_vs_out_irq_handler(void); +void vit_hs_out_irq_handler(void); +void fb_vs_out_irq_handler(void); +void dt_lock_det_valid_irq_handler(void); +void dt_lock_flag_irq_handler(void); +void integ_prd_irq_handler(void); +void integ_mrd_irq_handler(void); +void flag_set_irq_handler(void); +void flag_ram0_wr_end_irq_handler(void); +void flag_ram0_rd_end_irq_handler(void); +void flag_ram0_rd_reach_wr_handler(void); +void flag_dscenc0_busy_handler(void); +void mipitx_p0_tx_vfp_area_irq_handler(void); +void te_out_irq_handler(void); +void DBG_IRQ_TEST(void); + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/driver/include/la_spi.h b/src/driver/include/la_spi.h new file mode 100644 index 0000000..ecf8d27 --- /dev/null +++ b/src/driver/include/la_spi.h @@ -0,0 +1,488 @@ +/* + *Copyright (c) 2024, sdmicro FAE Team + * + * + * Date Author Notes + * 2024-10-17 FAE first version + */ +#ifndef __LA_SPI_H__ +#define __LA_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "typedef.h" +#include "define.h" + +/* definitions */ +#define SPI_AP BASE_ADDR_SPI_AP +#define SPI_TCH BASE_ADDR_SPI_TCH + +/*spi ap register define*/ +#define AP_Byte REG32((SPI_AP) + 0x00000000U) //ýգֻSPIMCUCSʱõӲSPIõĻò +#define AP_Clinet REG32((SPI_AP) + 0x00000004U) //òͬĴӻشݵķʽһַʽ +#define AP_Ctrl0 REG32((SPI_AP) + 0x00000008U) //ôӻsckλͼԡ +#define AP_NoEmptyTh REG32((SPI_AP) + 0x0000000CU) //ôӻrx fifoյٸbyte֮жϡ +#define AP_Ctrl1 REG32((SPI_AP) + 0x00000010U) //SPIͨѶʽ +#define AP_Ftlr REG32((SPI_AP) + 0x00000014U) //òźźdmaֵ +#define AP_DMA REG32((SPI_AP) + 0x00000018U) //2dmaļʱ䡣 +#define AP_IRQ REG32((SPI_AP) + 0x0000001CU) //SPIĸжʹܡ +#define AP_ClrFIFO REG32((SPI_AP) + 0x00000020U) //SPIfifoá +#define AP_Cnt1 REG32((SPI_AP) + 0x00000024U) //ȡSPIĽռֵô +#define AP_Cnt2 REG32((SPI_AP) + 0x00000028U) //ȡSPIfifoռֵô +#define AP_SR REG32((SPI_AP) + 0x0000002cU) //ȡSPIĸ״̬ +#define AP_ISR REG32((SPI_AP) + 0x00000030U) //ȡSPIĸж״̬ +#define AP_Pulse0 REG32((SPI_AP) + 0x00000034U) //üô +#define AP_Pulse1 REG32((SPI_AP) + 0x00000038U) //üô +#define AP_IRQClr REG32((SPI_AP) + 0x0000003CU) //жϡ +#define AP_RXSRC REG32((SPI_AP) + 0x00001000U) //dmaʱrxԴַ +#define AP_TXSRC REG32((SPI_AP) + 0x00001200U) //dmaʱtxԴַ + +/*spi TCH register define*/ +#define TCH_CTRL REG32((SPI_TCH) + 0x00000000U) //ôСˣbusy״̬ģʽǷʹno_commandģʽ +#define TCH_FTLR REG32((SPI_TCH) + 0x00000004U) //tx_fifoֵDMA +#define TCH_DMA REG32((SPI_TCH) + 0x00000008U) //dma ackߺٷһreqǰĵȴcycle +#define TCH_CLR REG32((SPI_TCH) + 0x0000000CU) //fifoʹ +#define TCH_CMD90 REG32((SPI_TCH) + 0x00000010U) //Flash read manufacture id/device id instruction,default 90h +#define TCH_CMD92 REG32((SPI_TCH) + 0x00000014U) //Manufacturer/ Device ID by Dual I/O,default 92h +#define TCH_CMD94 REG32((SPI_TCH) + 0x00000018U) //Manufacturer/Device ID by Quad I/O,default 94h +#define TCH_CMDab REG32((SPI_TCH) + 0x0000001cU) //Release From Deep Power-Down, And Read Device ID,default abh +#define TCH_CMD9f REG32((SPI_TCH) + 0x00000020U) //Read Identification,default 9fh +#define TCH_CMD4b REG32((SPI_TCH) + 0x00000024U) //Read Unique ID +#define TCH_CMD48 REG32((SPI_TCH) + 0x00000028U) //Read Security Registers(8) +#define TCH_CMD5a REG32((SPI_TCH) + 0x0000002cU) //Read SFDP Register +#define TCH_CMD35 REG32((SPI_TCH) + 0x00000030U) //Read Status Register2 +#define TCH_CMD05 REG32((SPI_TCH) + 0x00000034U) //Read Status Register1 +#define TCH_CMD15 REG32((SPI_TCH) + 0x00000038U) //Read Status Register3 +#define TCH_CMDbb REG32((SPI_TCH) + 0x0000003cU) //Dual I/O Fast Read +#define TCH_NOCMDbb REG32((SPI_TCH) + 0x00000040U) // +#define TCH_CMDeb REG32((SPI_TCH) + 0x00000044U) //Quad I/O Fast Read +#define TCH_NOCMDeb REG32((SPI_TCH) + 0x00000048U) +#define TCH_CMD03 REG32((SPI_TCH) + 0x0000004cU) //Read Data +#define TCH_CMD0b REG32((SPI_TCH) + 0x00000050U) //Fast Read +#define TCH_CMD3b REG32((SPI_TCH) + 0x00000054U) //Dual Output Fast Read +#define TCH_CMD6b REG32((SPI_TCH) + 0x00000058U) //Quad Output Fast Read +#define TCH_CMD3d REG32((SPI_TCH) + 0x0000005cU) +#define TCH_CMD0c REG32((SPI_TCH) + 0x00000060U) +#define TCH_CMD25 REG32((SPI_TCH) + 0x00000064U) +#define TCH_SCLKCNTST REG32((SPI_TCH) + 0x00000068U) //Read statusʱ +#define TCH_CLKCNTPA REG32((SPI_TCH) + 0x0000006cU) //Read parameter/security reg ʱ +#define TCH_CMDJUDGECNT REG32((SPI_TCH) + 0x00000070U) //жcommandʱ +#define TCH_SR REG32((SPI_TCH) + 0x00000074U) +#define TCH_CMD REG32((SPI_TCH) + 0x00000078U) //drive ic͵command +#define TCH_POL REG32((SPI_TCH) + 0x0000007CU) //r_ap_sck_pol_selѡSCLļ + +#define TCH_ISR REG32((SPI_TCH) + 0x00000080U) //ж״̬Ĵ +#define TCH_IMR REG32((SPI_TCH) + 0x00000084U) //жʹܼĴ +#define TCH_ICR REG32((SPI_TCH) + 0x00000088U) //жĴ + +#define TCH_TXFIFO REG32((SPI_TCH) + 0x00002000U) //TX FIFOַ +//#bit +#define spi_i2c_rx_num_byte BITS(0,15) +#define spi_i2c_tx_num_byte BITS(16,31) +#define spi_ctrl_num BITS(0,7) +#define spi_equal_th BITS(8,15) +#define spi_and_th BITS(16,23) +#define spi_mask_th BITS(24,31) + +#define spi_tx_style BITS(0,1) +#define spi_tx_pos_adj BITS(8,12) +#define auto_clr_rxcnt BIT(24) +#define auto_clr_txcnt BIT(25) +#define auto_clr_rxbuffer BIT(26) +#define auto_clr_txbuffer BIT(27) +#define dma_rx_cycle_en BIT(28) +#define dma_tx_cycle_en BIT(29) + +#define r_spi_big_endian BIT(0) +#define r_spi_tx_hw_en BIT(1) +#define r_spi_rx_cs_over_en BIT(2) +#define r_spi_tx_cs_over_en BIT(3) +#define r_spi_sw_byte_align BIT(4) +#define r_spi_out_always_en BIT(5) +#define r_spi_out_default_val BIT(6) +#define r_ap_sck_pol_sel BIT(7) +#define r_tx_fifo_thres_leve BITS(0,3) +#define r_rx_fifo_thres_level BITS(8,11) +#define r_dma_tx_wait_cycle BITS(0,7) +#define r_dma_rx_wait_cycle BITS(8,15) + +#define txbuffer_empty_ie BIT(0) +#define txbuffer_half_empty_ie BIT(1) +#define rxbuffer_full_ie BIT(2) +#define rxbuffer_halffull_ie BIT(3) +#define rxbuffer_noempty_ie BIT(4) +#define tx_end_ie BIT(5) +#define tx_start_ie BIT(6) +#define rx_end_ie BIT(7) +#define rx_start_ie BIT(8) +#define end_ie BIT(9) +#define start_ie BIT(10) +#define tx_byte_ie BIT(11) +#define rx_byte_ie BIT(12) + + +#define clr_rxfifo BIT(0) +#define clr_txfifo BIT(8) + + +#define rx_cnt1 BITS(0,15) +#define tx_cnt1 BITS(16,31) +#define rx_cnt2 BITS(0,15) +#define tx_cnt2 BITS(16,31) + + +#define txbuffer_empty BIT(0) +#define txbuffer_half_empty BIT(1) +#define rxbuffer_full BIT(2) +#define rxbuffer_halffull BIT(3) +#define rxbuffer_noempty BIT(4) +#define tx_end BIT(5) +#define tx_start BIT(6) +#define rx_end BIT(7) +#define rx_start BIT(8) +#define end BIT(9) +#define start BIT(10) +#define tx_byte BIT(11) +#define rx_byte BIT(12) + + +#define txbuffer_empty_isr BIT(0) +#define txbuffer_half_empty_isr BIT(1) +#define rxbuffer_full_isr BIT(2) +#define rxbuffer_halffull_isr BIT(3) +#define rxbuffer_noempty_isr BIT(4) +#define tx_end_isr BIT(5) +#define tx_start_isr BIT(6) +#define rx_end_isr BIT(7) +#define rx_start_isr BIT(8) +#define end_isr BIT(9) +#define start_isr BIT(10) +#define tx_byte_isr BIT(11) +#define rx_byte_isr BIT(12) + +#define spi_tx_en BIT(0) +#define spi_ird_sw BIT(1) +#define clr_rxcnt BIT(8) +#define spi_clr_rx_nosck BIT(9) + +#define clr_txcnt BIT(16) +#define spi_clr_tx_nosck BIT(17) +#define clr_err_pfetch BIT(24) +#define pulse_spi_clr_pfetch_nosck BIT(25) + +#define clr_rxbuffer BIT(0) +#define clr_txbuffer BIT(8) + + +#define txbuffer_empty_iclr BIT(0) +#define txbuffer_half_empty_iclr BIT(1) +#define rxbuffer_full_iclr BIT(2) +#define rxbuffer_halffull_iclr BIT(3) +#define rxbuffer_noempty_iclr BIT(4) +#define tx_end_iclr BIT(5) +#define tx_start_iclr BIT(6) +#define rx_end_iclr BIT(7) +#define rx_start_iclr BIT(8) +#define end_iclr BIT(9) +#define start_iclr BIT(10) +#define tx_byte_iclr BIT(11) +#define rx_byte_iclr BIT(12) + + +//tch bit +#define r_endian_mode BIT(0) //1 0С +#define r_wip BIT(8) //1: slave busy 0:slave ready +#define r_nocmden BIT(16) //1: slave busy 0:slave ready + +#define spi_start_itclr BIT(0) +#define spi_end_itclr BIT(1) +#define command_end_itclr BIT(2) +#define txf_halfempty_itclr BIT(3) +#define tx_fifo_full_itclr BIT(4) + +#define r_clr BIT(0) +#define r_fifo_clr BIT(0) + + +//define struct +typedef struct +{ + //uint8 trans_mode; /*!< spi شݴʽmcuƣӲspiд*/ + uint8 endian; /*!< SPI big endian or little endian */ + uint8 clock_polarity_phase; /*!< SPI clock phase and polarity,@spi_mode */ + uint8 dummy_byte_num; /*!< SPI dummy */ + uint8 dummy_byte_val; /*!< SPI dummy ֵ */ + uint8 ctrl_byte_num; /*!< SPI ֵ */ + //uint8 tx_style; /*!< SPI شݵĴʽ*/ +}SPI_TypeDef; + + +typedef enum { + IT_TX_EMPTY, //txbuffer empty Interrupt. + IT_TX_HALFEMPTY, //txbuffer half empty Interrupt + IT_RX_FULL, //rxbuff full Interrupt + IT_RX_HALFULL, //rxbuff half full Interrupt + IT_RX_NOEMPTY, //rxbuff no empty Interrupt + IT_TX_END, //tx end Interrupt + IT_TX_START, //tx start Interrupt + IT_RX_END, //rx end Interrupt + IT_RX_START, //rx start Interrupt + IT_CS_END, //cs end Interrupt + IT_CS_START, //cs start Interrupt + IT_TX_BYTETFR, //tx byte Interrupt + IT_RX_BYTETFR, //rx byte Interrupt +} SPI_IT_TYPE; + + +typedef struct +{ + uint32 endian; /*!< SPI big endian or little endian + --SPI_BIG_ENDIAN + --SPI_LITTER_ENDIAN + */ + uint32 cmden; /*!< SPI is-enbale command + --TCH_NOCMD_ENABLE + --TCH_NOCMD_DIS + */ + + uint32 sckpol; /*!< SPI sck pol sel + --TCH_SCK_POL_H + --TCH_SCK_POL_L + */ + +}TCH_TypeDef; + + +typedef enum +{ + TCH_CS_STAR = 0, + TCH_CS_END, + TCH_CMD_END, + TCH_TX_HALF_EMPTY, + TCH_TX_FIFO_FULL, + TCH_DMA_TX_ACK, + TCH_READING, +}TCH_IT_TYPE; + + +#define SPI_BIG_ENDIAN r_spi_big_endian //ģʽ +#define SPI_LITTER_ENDIAN ((uint32)0x00U) //ģʽ + +//spi شʽ +#define SPI_TX_HW r_spi_tx_hw_en //SPI slaveжϴspiض +#define SPI_TX_MCU ((uint32)0x00U) //MCUspiض + +#define SPI_RX_CS_OVER_EN r_spi_rx_cs_over_en //SPIcsRXͨѶ +#define SPI_RX_CS_OVER_DIS ((uint32)0x00U) //MCUCSRXͨѶ,rx_num_byte + +#define SPI_TX_CS_OVER_EN r_spi_tx_cs_over_en //SPIcsTXͨѶ +#define SPI_TX_CS_OVER_DIS ((uint32)0x00U) //MCUCSTXͨѶ,tx_num_byte + +//mcuSPIشʱЧ +#define SPI_SW_BYTE_ALIGN_DELAY r_spi_sw_byte_align //شλbyte봦 +#define SPI_SW_BYTE_ALIGN ((uint32)0x00U) //شλþʹMCUpulseʼǷ + + +#define SPI_OUT_EN r_spi_out_always_en //һֱʹMISO +#define SPI_OUT_DIS ((uint32)0x00U) //شʱʹMISO + + +#define SPI_OUT_VAL_H r_spi_out_default_val //MISOʱĿ״̬һֱΪߵƽ +#define SPI_OUT_VAL_L ((uint32)0x00U) //MISOʱĿ״̬һֱΪ͵ƽ + + + +#define SPI_POL_VAL_H r_ap_sck_pol_sel //AP sckļԿʱΪߵƽ +#define SPI_POL_VAL_L ((uint32)0x00U) //AP sckļԿʱΪ͵ƽ + + +#define SPI_TX_EN spi_tx_en //mcuضʹ + + +#define TCH_NOCMD_ENABLE r_nocmden +#define TCH_NOCMD_DIS ((uint32)0x00U) + + +#define TCH_SCK_POL_H ((uint32)0x01U) +#define TCH_SCK_POL_L ((uint32)0x00U) + + +/************************************************ +* @func: spi deinit +* @param NONE +* @retval NONE +*************************************************/ +void spi_deinit(void); + + +/************************************************ +* @func: spi init +* @param NONE +* @retval NONE +*************************************************/ +void spi_init(void); + + +/************************************************ +* @func: SPI IRQ +* @param: 13 type irq +* @param: enbale/disable +* @retval NONE +*************************************************/ +void spi_it_config(SPI_IT_TYPE type, funcstate state); + + +/************************************************ +* @func: spi_get_it_flag +* @param 13 type irq +* @retval 0/1 +*************************************************/ +intstatus spi_get_it_flag(SPI_IT_TYPE type); + + +/************************************************ +* @func: spi_clear_it_flag +* @param NONE +* @retval NONE +*************************************************/ +void spi_clear_it_flag(SPI_IT_TYPE type); + + +/************************************************ +* @func: SPI dmc config +* @param1 tx fifofifoֵtx fifoڴֵʱźdma req +* @param2 rx fifofifoֵtx fifoڴֵʱźdma req +* @param3 tx dma_reqмҪȴcycle +* @param4 rx dma_reqмҪȴcycle +* @retval None +*************************************************/ +void spi_dma_config(uint8 txfifoth, uint8 rxfifoth, uint8 tx_wtime, uint8 rxx_wtime); + + +/************************************************ +* @func: SPI ǿжϵֵ,ǿжϴʹ +* @param 13 irq type +* @retval NONE +*************************************************/ +void spi_set_noempty_thres(uint16 val); + + +/************************************************ +* @func: SPI սռֵ rx/tx +* @param NONE +* @retval NONE +*************************************************/ +void spi_clear_rx_tx_cnt(void); +void spi_clear_rx_cnt(void); +void spi_clear_tx_cnt(void); +/************************************************ +* @func: SPI fifo rx/tx fifo +* @param NONE +* @retval NONE +*************************************************/ +void spi_clear_rx_tx_fifo(void); + + +/************************************************ +* @func: SPI սfifo +* @param NONE +* @retval NONE +*************************************************/ +void spi_clear_rx_fifo(void); + +/************************************************* +* @func: SPI շfifo +* @param NONE +* @retval NONE +*************************************************/ +void spi_clear_tx_fifo(void); + + +/************************************************ +* @func: MCU ֱSPI fifoдݣд16 +* @param 洢ݵĵַ +* @param ݵij +* * @retval NONE +*************************************************/ +void spi_transfer(uint8* data, uint8 len); + + +/************************************************ +* @func: MCU ֱӶȡSPI fifo +* @param 洢ݵĵַ +* @param ݵij +* @retval NONE +*************************************************/ +void spi_receive(uint8* data, uint8 len); + + +/************************************************ +* @func: spi tch_init: + spi tch register deinit +* @param NONE +* @retval NONE +*************************************************/ +void tch_init(TCH_TypeDef* p); + + +/* +* @func: SPI TCH IRQ +* @param: 5 irq type +* @param: enbale/disable +* @retval NONE +*/ +void tch_it_config(TCH_IT_TYPE type, funcstate state); + + +/* +* @func: TCH ж +* @param 5 irq type +* @retval NONE +*/ +void tch_clear_it_flag(TCH_IT_TYPE type); + + +/* +* @func: ȡspiж +* @param 5 irq type +* @retval 0/1 +*/ +intstatus tch_get_it_flag(TCH_IT_TYPE type); + + +/* +* @func: SPI tch fifo +* @param NONE +* @retval NONE +*/ +void tch_clear_tx_fifo(void); + + +/* +* @func: SPI tch tx fifo empty жֵ,λDWORD +* @param NONE +* @retval NONE +*/ +void tch_set_tx_fifo_thres(uint8 txfifoth); + + +/* +* @func: SPI tch tx fifo empty DMAֵȴʱ,λDWORDָ +* @param NONE +* @retval NONE +*/ +void tch_dma_config(uint8 txfifoth, uint8 waittime); + + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/src/driver/include/la_sys.h b/src/driver/include/la_sys.h new file mode 100644 index 0000000..6246d60 --- /dev/null +++ b/src/driver/include/la_sys.h @@ -0,0 +1,82 @@ +#ifndef __LA_SYS_H__ +#define __LA_SYS_H__ + +#include "typedef.h" +#include "define.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define TRIM_STAR REG32(BASE_ADDR_SYS_STATUS+0x00000000U) //---trim star address +#define TRIM_END REG32(BASE_ADDR_SYS_STATUS+0x00000004U) //---trim end address +#define CFGSET_PRE_STAR REG32(BASE_ADDR_SYS_STATUS+0x00000008U) //---cfg pre star address +#define CFGSET_PRE_END REG32(BASE_ADDR_SYS_STATUS+0x0000000CU) //---cfg pre end address +#define CFGSET_POST_STAR REG32(BASE_ADDR_SYS_STATUS+0x00000010U) //---cfg post star address +#define CFGSET_POST_END REG32(BASE_ADDR_SYS_STATUS+0x00000014U) //---cfg post star address + +#define DPCD_START REG32(BASE_ADDR_SYS_STATUS+0x00000018U) //---dpcd star address +#define DPCD_END REG32(BASE_ADDR_SYS_STATUS+0x0000001CU) //---dpcd end address + +#define MBIST_START REG32(BASE_ADDR_SYS_STATUS+0x00000020U) //---mbist star address +#define MBIST_END REG32(BASE_ADDR_SYS_STATUS+0x00000024U) //---mbist end address + +#define EDID_START REG32(BASE_ADDR_SYS_STATUS+0x00000028U) //---edid star address +#define EDID_END REG32(BASE_ADDR_SYS_STATUS+0x0000002CU) //---edid end address + +#define INSTON_START REG32(BASE_ADDR_SYS_STATUS+0x00000030U) //---inston star address +#define INSTON_END REG32(BASE_ADDR_SYS_STATUS+0x00000034U) //---inston end address + + +#define IRAM_START REG32(BASE_ADDR_SYS_STATUS+0x00000038U) //---iram star address +#define IRAM_END REG32(BASE_ADDR_SYS_STATUS+0x0000003CU) //---iram end address + +#define DRAM_START REG32(BASE_ADDR_SYS_STATUS+0x00000040U) //---dram star address +#define DRAM_END REG32(BASE_ADDR_SYS_STATUS+0x00000044U) //---dram end address + +#define TCHFW_START REG32(BASE_ADDR_SYS_STATUS+0x00000048U) //---tchfw start address +#define TCHFW_END REG32(BASE_ADDR_SYS_STATUS+0x0000004CU) //---tchfw end address + +#define CCOTABLE_START REG32(BASE_ADDR_SYS_STATUS+0x00000050U) //---cco table star address +#define CCOTABLE_END REG32(BASE_ADDR_SYS_STATUS+0x00000054U) //---cco table end address + +#define TRUETONE_START REG32(BASE_ADDR_SYS_STATUS+0x00000058U) //---truetone star address +#define TRUETONE_END REG32(BASE_ADDR_SYS_STATUS+0x0000005CU) //---truetone end address + +#define MANUINFO_START REG32(BASE_ADDR_SYS_STATUS+0x00000060U) //---manuinfo star address +#define MANUINFO_END REG32(BASE_ADDR_SYS_STATUS+0x00000064U) //---manuinfo end address + +#define FLASH_MID10 REG32(BASE_ADDR_SYS_STATUS+0x00000068U) //---flash mid10 address +#define FLASH_MID32 REG32(BASE_ADDR_SYS_STATUS+0x0000006CU) //---flash mid32 address + +#define USER_DEFINE0 REG32(BASE_ADDR_SYS_STATUS+0x00000070U) //---user defin0 address +#define USER_DEFINE1 REG32(BASE_ADDR_SYS_STATUS+0x00000074U) //---user defin1 address +#define USER_DEFINE2 REG32(BASE_ADDR_SYS_STATUS+0x00000078U) //---user defin2 address +#define USER_DEFINE3 REG32(BASE_ADDR_SYS_STATUS+0x0000007CU) //---user defin3 address +#define USER_DEFINE4 REG32(BASE_ADDR_SYS_STATUS+0x00000080U) //---user defin4 address +#define USER_DEFINE5 REG32(BASE_ADDR_SYS_STATUS+0x00000084U) //---user defin5 address +#define USER_DEFINE6 REG32(BASE_ADDR_SYS_STATUS+0x00000088U) //---user defin6 address +#define USER_DEFINE7 REG32(BASE_ADDR_SYS_STATUS+0x0000008CU) //---user defin7 address + +#define POSTBOOT_STATUS REG32(BASE_ADDR_SYS_STATUS+0x00000090U) //---post status +#define PREBOOT_KEY REG32(BASE_ADDR_SYS_STATUS+0x000000A0U) //---preboot key + +#define BOOT_PRINTF_ENABLE REG32(BASE_ADDR_SYS_STATUS+0x000000A4U) //---boot printf enable + +#define FLOW_TEST_ID REG32(BASE_ADDR_SYS_STATUS+0x000000A8U) //---flow test id +#define FLASH_TRAIN_STATUS REG32(BASE_ADDR_SYS_STATUS+0x000000ACU) //---flash train status +#define PREBOOT_DMA_CTRL REG32(BASE_ADDR_SYS_STATUS+0x000000B0U) //---pre boot dma ctrl +#define PREBOOT_STATUS REG32(BASE_ADDR_SYS_STATUS+0x000000B4U) //---pre boot status + +#define MCU_BIST_RESULT REG32(BASE_ADDR_SYS_STATUS+0x000000B8U) //---mcu bist result + + + + +void sys_boot_getstatus(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/driver/include/la_timer.h b/src/driver/include/la_timer.h new file mode 100644 index 0000000..a257252 --- /dev/null +++ b/src/driver/include/la_timer.h @@ -0,0 +1,233 @@ +/* + *Copyright (c) 2024, sdmicro FAE Team + * + * + * Date Author Notes + * 2024-10-17 FAE first version + */ +#ifndef __LA_GPTM_H__ +#define __LA_GPTM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "define.h" +#include "typedef.h" + +/* TIMERx(x=0,1,2,3,4..11) definitions */ +#define GPTM_CH0 (BASE_ADDR_GPTM+0x00000000U) +#define GPTM_CH1 (BASE_ADDR_GPTM+0x00000030U) +#define GPTM_CH2 (BASE_ADDR_GPTM+0x00000060U) +#define GPTM_CH3 (BASE_ADDR_GPTM+0x00000090U) +#define GPTM_CH4 (BASE_ADDR_GPTM+0x000000c0U) +#define GPTM_CH5 (BASE_ADDR_GPTM+0x000000f0U) +#define GPTM_CH6 (BASE_ADDR_GPTM+0x00000120U) +#define GPTM_CH7 (BASE_ADDR_GPTM+0x00000150U) +#define GPTM_CH8 (BASE_ADDR_GPTM+0x00000180U) +#define GPTM_CH9 (BASE_ADDR_GPTM+0x000001b0U) +#define GPTM_CH10 (BASE_ADDR_GPTM+0x000001e0U) +#define GPTM_CH11 (BASE_ADDR_GPTM+0x00000210U) + + +/* registers definitions */ +#define GPTM_ARR(timerx) REG32((timerx) + 0x00U) /*!< TIMER counter auto reload register */ +#define GPTM_PSC(timerx) REG32((timerx) + 0x04U) /*!< TIMER prescaler register */ +#define GPTM_CCR(timerx) REG32((timerx) + 0x08U) /*!< TIMER capture/compare value register */ +#define GPTM_INTR_CTRL(timerx) REG32((timerx) + 0x0CU) /*!< TIMER interrupt ctrl register */ +#define GPTM_INTR_STAT(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt status register */ +#define GPTM_CFG(timerx) REG32((timerx) + 0x14U) /*!< TIMER configuration register */ +#define GPTM_CNT(timerx) REG32((timerx) + 0x18U) /*!< TIMER counter register */ +#define GPTM_ENABLE(timerx) REG32((timerx) + 0x1CU) /*!< TIMER enable register */ +#define GPTM_TIMOUT(timerx) REG32((timerx) + 0x20U) /*!< TIMER timeout register */ +#define GPTM_PSCCCR(timerx) REG32((timerx) + 0x24U) /*!< TIMER PSCCCR register */ + +#define GPTM_DBG_SEL REG32(BASE_ADDR_GPTM+0x00000240U) /*!*/ + +/* bits definitions */ +/* TIMER_int_CTL */ +#define gptm_incap_iren BIT(0) /*!< TIMER input capture interrupt enable */ +#define gptm_outcomp_iren BIT(1) /*!< TIMER output compare interrupt enable */ +#define gptm_arr_iren BIT(2) /*!< TIMER counter arr register val generate interrupt enable*/ +#define gptm_overflow_iren BIT(3) /*!< TIMER counter overflow interrupt enable*/ +#define gptm_ch_out_iren BIT(4) /*!< TIMER output interrupt enable*/ + +/* TIMER_STAT */ +#define gptm_incap_ir BIT(0) /*!< TIMER input capture interrupt status,write 1 clear*/ +#define gptm_outcomp_ir BIT(1) /*!< TIMER output compare interrupt status,,write 1 clear */ +#define gptm_arr_ir BIT(2) /*!< TIMER counter arr val interrupt status,write 1 clear*/ +#define gptm_overflow_ir BIT(3) /*!< TIMER counter overflow interrupt status,write 1 clear*/ +#define gptm_ch_out_iren BIT(4) /*!< TIMER output interrupt status,write 1 clear*/ + + +/* TIMER_CFG */ +#define gptm_cnt_dir BIT(0) /*!< TIMER counter direction*/ +#define gptm_reload_mode BIT(1) /*!< TIMER counter auto reload mode*/ +#define gptm_edge_sel BITS(2,3) /*!< TIMER input capture edge selction*/ +#define gptm_deglitch_cnt BITS(4,6) /*!< TIMER counter filter*/ +#define gptm_capcomp_sel BIT(8) /*!< TIMER capture/compare input/output mode selction*/ +#define gptm_outcomp_mode BITS(9,11) /*!< TIMER compare output 8-mode selction */ +#define gptm_out_polar BIT(12) /*!< ȡ */ +#define gptm_arr_cntclr BIT(16) /*!< arrʱ */ +#define gptm_chin_cntclr BIT(17) /*!< źűػ*/ +#define gptm_dma_en BIT(18) /*!< DMA*/ +#define chin_edge_flag 19U /*!< ˫شʱbit1ʾ½أ0ʾ*/ + +/* TIMER_ENABLE */ +#define gptm_cnt_en BIT(0) /*!< ʹ*/ +#define gptm_ug_cntclr BIT(1) /*!< һźţ1Ӳ0,WO*/ + +/* paramter define */ +/* count direction */ +#define GPTM_COUNTER_UP ((uint32_t)0x00U) /*!< counter up direction */ +#define GPTM_COUNTER_DOWN ((uint32_t)gptm_cnt_dir) /*!< counter down direction */ + +/* auto reload preload*/ +#define GPTM_ARR_RELOAD_AUTO ((uint32_t)0x00U) /*!< װֵԶѭģʽ */ +#define GPTM_ARR_RELOAD_SIGNAL ((uint32_t)gptm_reload_mode) /*!< װֵģʽ */ + +/* capture selct edge*/ +#define GPTM_IC_RISING (0x00U <<2) /*!< input capture rising edge */ +#define GPTM_IC_FALLING (0x01U <<2) /*!< input capture falling edge*/ +#define GPTM_IC_BOTH_EDGE (0x02U <<2) /*!< input capture both edge */ + +/* TIMER_mode selct*/ +#define GPTM_OC_MODE ((uint32_t)0x00U) /*!< input capture*/ +#define GPTM_IC_MODE ((uint32_t)gptm_capcomp_sel) /*!< output compare*/ + +/* TIMER arr cnt clear*/ +#define GPTM_CNT_NCLR ((uint32_t)0x00U) +#define GPTM_CNT_CLR ((uint32_t)gptm_arr_cntclr) + +/*GPTM CHIN CNT CLEAR*/ +#define GPTM_CHIN_CNT_NCLR ((uint32_t)0x00U) +#define GPTM_CHIN_CNT_CLR ((uint32_t)gptm_chin_cntclr) + + +/* gptm_out_polar*/ +#define GPTM_OUT_POL gptm_out_polar +#define GPTM_OUT_NO_POL ((uint32_t)0x00U) + + +#define GPTM_OUTCOMP_MODE0 (0x00U <<9) +#define GPTM_OUTCOMP_MODE1 (0x01U <<9) +#define GPTM_OUTCOMP_MODE2 (0x02U <<9) +#define GPTM_OUTCOMP_MODE3 (0x03U <<9) +#define GPTM_OUTCOMP_MODE4 (0x04U <<9) +#define GPTM_OUTCOMP_MODE5 (0x05U <<9) +#define GPTM_OUTCOMP_MODE6 (0x06U <<9) +#define GPTM_OUTCOMP_MODE7 (0x07U <<9) + + +/*嶨ʱʼIJ*/ +typedef struct +{ + uint32 countmode; //ϼ¼ + uint32 autoreloadpreload; //װģʽװػѭԶװ + + uint32 autoreload; //Զװֵ + uint32 prescaler; //ԤƵϵֵ + uint32 count; //ʼֵ + + uint32 cntclr; //㣺װֵֵ壬input captureģʽ£ص +}GPTM_BaseParameter; + + +/*capture趨*/ +typedef struct +{ + uint32 icedge; /*input captureıѡ 00: 01:½ 10:˫ + --GPTM_IC_RISING + --GPTM_IC_FALLING + --GPTM_IC_BOTH_EDGE + */ + uint32 filter; //˲ϵ + uint32 timeout; //óʱʱ + uint32 iccntclr; /*òģʽʱ + --GPTM_CHIN_CNT_CLR + --GPTM_CHIN_CNT_NCLR + */ + //uint16 capture; //Ƶ +}GPTM_ICParameter; + + +/*compare趨*/ +typedef struct +{ + uint32 ocpolarity; /*ȡDzȡ + --GPTM_OUT_POL + --GPTM_OUT_NO_POL + */ + uint32 ocsubmode; /*ģʽ8֮һ + --GPTM_OUTCOMP_MODE0 + --GPTM_OUTCOMP_MODE1 + --GPTM_OUTCOMP_MODE2 + --GPTM_OUTCOMP_MODE3 + --GPTM_OUTCOMP_MODE4 + --GPTM_OUTCOMP_MODE5 + --GPTM_OUTCOMP_MODE6 //pwm + --GPTM_OUTCOMP_MODE7 //pwm + */ + uint32 compare; //Ƚֵ,ccr +}GPTM_OCParameter; + + +/*gptm ж*/ +typedef enum +{ + GPTM_INCAP_IR =0x01, //벶ж + GPTM_OUTCOMP_IR =0x02, //Ƚж + GPTM_ARR_IR =0x04, //ж + GPTM_OVER_FLOW_IR =0x08, //ж + GPTM_CH_OUT_IR =0x10, //ߵƽж + GPTM_ALL_IR =0x1F //ȫжϣ5֣ +}GPTM_IT_TYPE; + + + + + +/*@funciton: interrupt flag clear 0 + *@param[0] timerx:(GPTM_CHx=0,1,2...11) + *@param[1] irq:the timer interrupt bits +* only one parameter can be selected which is shown as below: +* +* +* +* +* +* +* @retval:NONE +*/ +void gtpm_clear_irqflag(uint32 timerx, GPTM_IT_TYPE irq); + + +/*@funciton: read interrupt flag +* @param[0] timerx:(GPTM_CHx=0,1,2...11) + *@param[1] irq:the timer interrupt bits +* only one parameter can be selected which is shown as below: +* +* +* +* +* +* +* @retval +*/ +FlagStatus gptm_get_itflag(uint32 timerx, GPTM_IT_TYPE irq); + + + + +void sys_clk_get(void); + +//------------------------case demo +//void gptm_case_test(void); +//void gptm1_case_pwm_test(void); +//void gptm2_case_pwm_test(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/driver/include/la_uart.h b/src/driver/include/la_uart.h new file mode 100644 index 0000000..9abc6a4 --- /dev/null +++ b/src/driver/include/la_uart.h @@ -0,0 +1,64 @@ +/* + *Copyright (c) 2024, sdmicro FAE Team + * + * + * Date Author Notes + * 2024-10-17 FAE first version + */ +#ifndef __LA_UART_H__ +#define __LA_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "typedef.h" +#include + +typedef struct +{ + __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */ + __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */ + __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */ + union { + __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */ + __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */ + }; + __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */ + +} CMSDK_UART_TypeDef; + +//#define CMSDK_UART0_BASE 0x88150000 +#define CMSDK_UART1_BASE 0x88140000 + +//#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE ) +#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE ) + + + + +extern void UartStdOutInit(void); +extern unsigned char UartPutc(unsigned char my_ch); +extern unsigned char UartGetc(void); +void uart_output(const char* message); +void uart_send_str(const char* str); +bool uart_has_data(void); + +// extern unsigned char UartEndSimulation(void); + +//void uart_ + + + + + + + + + + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/src/driver/include/la_wdg.h b/src/driver/include/la_wdg.h new file mode 100644 index 0000000..c1db3fe --- /dev/null +++ b/src/driver/include/la_wdg.h @@ -0,0 +1,74 @@ +/* + *Copyright (c) 2024, sdmicro FAE Team + * + * + * Date Author Notes + * 2024-10-17 FAE first version + */ +#ifndef __LA_WDG_H__ +#define __LA_WDG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "typedef.h" +#include "define.h" + +/* DWG definitions */ +#define WDG BASE_ADDR_WDT + +/* registers definitions */ +#define WDG_CFG REG32((WDG) + 0x00000300U) /*!< WWDGT configuration register */ +#define WDG_CNT_CMP REG32((WDG) + 0x00000304U) /*!< WWDGT configuration register */ + + +/* bits definitions */ +#define WDG_CFG_KEY BITS(0,7) +#define WDG_CFG_FEED BITS(8,15) +#define WDG_CFG_RSTEN BIT(16) +#define WDG_CFG_ZERO_CMP BIT(17) +#define WDG_CFG_EN BIT(18) +#define WDG_CFG_CLK_DIV BITS(24,31) + + +/*wdg enable*/ +#define WDG_DISABLE ((uint32)0x00U) +#define WDG_ENABLE ((uint32)WDG_CFG_EN) + +/*wdg zerocmp*/ +#define WDG_NO_ZEROCMP ((uint32)0x00U) +#define WDG_ZEROCMP ((uint32)WDG_CFG_ZERO_CMP) + + +/*wdg rst*/ +#define WDG_NO_RST ((uint32)0x00U) +#define WDG_RST ((uint32)WDG_CFG_RSTEN) + +/*key */ +#define WDG_KEY 0x5A +#define WDG_FEED 0xC3 + + +void wdg_deinit(void); +void wdg_feed(void); +void wdg_start(void); +void wdg_start_with_rst(void); +void wdg_start_with_zerocmp(void); +void wdg_start_with_zerocmp_and_rst(void); +void wdg_base_init(uint8 div, uint16 count, uint16 comp); + + +//------------------------case demo +void wgd_case_test(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/src/driver/source/hal_mipi_tx.c b/src/driver/source/hal_mipi_tx.c new file mode 100644 index 0000000..451b418 --- /dev/null +++ b/src/driver/source/hal_mipi_tx.c @@ -0,0 +1,214 @@ +/******************************************************************************* +* File: hal_mipi_tx.c +* Description: mipi发送模块接口 +* Version: V1.0 +* Date: 2026-1-23 +* Author: lyp + *******************************************************************************/ + +#include "hal_mipi_tx.h" +#include "typedef.h" +#include "define.h" + +/*! + * @brief MIPI发送模式 + * @note + */ +typedef enum _TX_MODE +{ + LP_MODE = 0, + HS_MODE, +}TX_MODE; + +static TX_MODE mipi_state = LP_MODE; + +/** +* @brief MIPI TX开始运行 +* @param tx_ctrl_handle: MIPI TX实例 +* @retval +*/ +void hal_dsi_tx_ctrl_start() +{ + wr_cfgreg(0x1100, 0x0F); + mipi_state = HS_MODE; +} + +/** +* @brief MIPI TX停止运行 +* @param tx_ctrl_handle: MIPI TX实例 +* @retval +*/ +void hal_dsi_tx_ctrl_stop() +{ + wr_cfgreg(0x1100, 0xF0); + mipi_state = LP_MODE; +} + +/** +* @brief MIPI TX发送命令 +* @param data_type: 数据类型 +* @param vc: 虚拟通道编号 +* @param cmd_count: 可变参数个数 +* @param ...: 可变参数 +* @retval true-command发送正常；false-TX当前状态不能发送command +*/ +bool hal_dsi_tx_ctrl_write_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd_count, ...) +{ + /*验证参数有效性*/ + if (cmd_count < 1) + { + return false; + } + + /*读取可变参数*/ + va_list args; + va_start(args, cmd_count); + uint8_t cmd[cmd_count]; + for (uint8_t i = 0; i < cmd_count; i++) + { + cmd[i] = (uint8_t)va_arg(args, int); + } + va_end(args); + + /*控制mipi ip发送数据*/ + if(cmd_count > 1) + { + write_addr_UINT8(mipi_tx_lp_hs_mode, mipi_state); + write_addr_UINT8(mipi_tx_send_requset, 0x01); + write_addr_UINT32(mipi_tx_send_data, (cmd[0] << 24) + (cmd_count << 8) + data_type + (0x3 << 6)); + for (uint8_t i = 0; i < ((cmd_count - 1) >> 2); i++) + { + write_addr_UINT32(mipi_tx_send_data, (cmd[4 + (i << 2)] << 24) + (cmd[3 + (i << 2)] << 16) + (cmd[2 + (i << 2)] << 8) + cmd[1 + (i << 2)]); + } + switch ((cmd_count - 1) % 4) + { + case 1: + write_addr_UINT32(mipi_tx_send_data, cmd[cmd_count - 1]); + break; + + case 2: + write_addr_UINT32(mipi_tx_send_data, (cmd[cmd_count - 1] << 8) + cmd[cmd_count - 2]); + break; + + case 3: + write_addr_UINT32(mipi_tx_send_data, (cmd[cmd_count - 1] << 16) + (cmd[cmd_count - 2] << 8) + cmd[cmd_count - 3]); + break; + + default: + break; + } + write_addr_UINT8(mipi_tx_send_requset,0x00); + write_addr_UINT8(mipi_tx_trigger_pulse,0x03); + while (0 == (read_addr_UINT8(mipi_tx_send_done) & mipi_tx_send_done_mask)); + } + else + { + write_addr_UINT8(mipi_tx_lp_hs_mode, mipi_state); // mipi tx lp send cmd enable + write_addr_UINT8(mipi_tx_send_requset, 0x01); // 向mipi tx发出申请，拉高 + write_addr_UINT32(mipi_tx_send_data, (0x05 + (cmd[0] << 8))); // mipi tx发送的数据 + write_addr_UINT8(mipi_tx_send_requset, 0x00); // 完成数据发送后，拉低wrqst + write_addr_UINT8(mipi_tx_trigger_pulse, 0x03); // 随后发triiger pulse，触发mipi tx工作 + while (0 == (read_addr_UINT8(mipi_tx_send_done) & mipi_tx_send_done_mask)); + } + + return true; +} + +/** +* @brief MIPI TX发送命令 +* @param data_type: 数据类型 +* @param vc: 虚拟通道编号 +* @param size: data个数 +* @param data: data数组 +* @retval true-command发送正常；false-TX当前状态不能发送command +*/ +bool hal_dsi_tx_ctrl_write_array_cmd(uint8_t data_type, uint8_t vc, uint8_t size, const uint8_t *data) +{ + /*验证参数有效性*/ + if ((size < 1) || (NULL == data)) + { + return false; + } + + /*控制mipi ip发送数据*/ + if(size > 1) + { + write_addr_UINT8(mipi_tx_lp_hs_mode, mipi_state); + write_addr_UINT8(mipi_tx_send_requset, 0x01); + write_addr_UINT32(mipi_tx_send_data, (data[0] << 24) + (size << 8) + data_type + (0x3 << 6)); + for (uint8_t i = 0; i < ((size - 1) >> 2); i++) + { + write_addr_UINT32(mipi_tx_send_data, (data[4 + (i << 2)] << 24) + (data[3 + (i << 2)] << 16) + (data[2 + (i << 2)] << 8) + data[1 + (i << 2)]); + } + switch ((size - 1) % 4) + { + case 1: + write_addr_UINT32(mipi_tx_send_data, data[size - 1]); + break; + + case 2: + write_addr_UINT32(mipi_tx_send_data, (data[size - 1] << 8) + data[size - 2]); + break; + + case 3: + write_addr_UINT32(mipi_tx_send_data, (data[size - 1] << 16) + (data[size - 2] << 8) + data[size - 3]); + break; + + default: + break; + } + write_addr_UINT8(mipi_tx_send_requset,0x00); + write_addr_UINT8(mipi_tx_trigger_pulse,0x03); + while (0 == (read_addr_UINT8(mipi_tx_send_done) & mipi_tx_send_done_mask)); + } + else + { + write_addr_UINT8(mipi_tx_lp_hs_mode, mipi_state); // mipi tx lp send cmd enable + write_addr_UINT8(mipi_tx_send_requset, 0x01); // 向mipi tx发出申请，拉高 + write_addr_UINT32(mipi_tx_send_data, (0x05 + (data[0] << 8))); // mipi tx发送的数据 + write_addr_UINT8(mipi_tx_send_requset, 0x00); // 完成数据发送后，拉低wrqst + write_addr_UINT8(mipi_tx_trigger_pulse, 0x03); // 随后发triiger pulse，触发mipi tx工作 + while (0 == (read_addr_UINT8(mipi_tx_send_done) & mipi_tx_send_done_mask)); + } + + return true; +} + +/** +* @brief 控制码片bist输出 +* @param bist_en: 使能bist +* @param bist_mode: bist的模式 +*/ +void hal_dsi_tx_ctrl_set_bist(bool bist_en, BIST_MODE bist_mode) +{ + if (PRE_VIDEO_BIST == bist_mode) + { + wr_cfgreg(0xF9C1,bist_en ? 0xA0 : 0x20); //0x20关闭pre bist ， 0xA0开启pre bist + wr_cfgreg(0xF900,0x88); + } + else if (POST_VIDEO_BIST == bist_mode) + { + wr_cfgreg(0xF91A,bist_en ? 0x01 : 0x00); //0x00关闭post bist ， 0x01开启post bist + wr_cfgreg(0xF900,0x7A); + } +} + +/** +* @brief MIPI TX接收命令 +* @param data_type: 数据类型 +* @param vc: 虚拟通道编号 +* @param cmd: DCS指令 +* @param size: 读取数据长度 +* @param data: 数据存放地址 +* @retval true-回读正常；false-当前状态不能回读 +*/ +bool hal_dsi_tx_ctrl_read_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd, uint8_t size, uint8_t *data) +{ + /*验证参数有效性*/ + if ((size < 1) || (NULL == data)) + { + return false; + } + + return true; +} \ No newline at end of file diff --git a/src/driver/source/la_dma.c b/src/driver/source/la_dma.c new file mode 100644 index 0000000..3f3ffe6 --- /dev/null +++ b/src/driver/source/la_dma.c @@ -0,0 +1,300 @@ + + +#include "la_config.h" + + +/* +* @func: dma ָĬ״̬ +* @param dma channel +* @retval None +*/ +void dma_deinit(dma_channel_enum channel) +{ + /* disable DMA a channel */ + DMAC_CFGREG &=~(uint8)dma_en; + DMA_CHENREG &=~(uint16)(dma_ch_en | dma_ch_wr_en); + CRC_ENREG &= ~(uint8)dma_crc_en; + /* reset DMA channel registers */ + DMAC_SAR(channel) = (uint32_t)0x00000000U; + DMAC_DAR(channel) = (uint32_t)0x00000000U; + DMAC_LLP(channel) = (uint32_t)0x00000000U; + DMAC_CTLL(channel) = (uint32_t)0x00000000U; + DMAC_CTLH(channel) = (uint32_t)0x00000000U; + DMAC_CFGL(channel) = (uint32_t)0x00000000U; + DMAC_CFGH(channel) = (uint32_t)0x00000000U; +} + + +/* +* @func: dma CRCʹ +* @param dma channel +* @retval None +*/ + +void dma_crc_enable(dma_channel_enum channel) +{ + if(DMA_CH4 ==channel || DMA_CH5 == channel) + { + CRC_ENREG = dma_crc_en; + }else + { + /*ʾchannel ֧crc*/ + return; + } +} + +/* +* @func: dma ȡCRC +* @param dma channel +* @retval crc result +*/ + +uint8 dma_get_crc_result(dma_channel_enum channel) +{ + uint8 temp8; + if (DMA_CH4 == channel || DMA_CH5 == channel) + { + temp8 =(uint8)CRC_RESULTREG; + } + else + { + temp8 =0; + } + return temp8; +} + +/* +* @func: dma IRQ +* @param dma channel +* @retval crc result +*/ +void dma_itconfig(dma_channel_enum channel, funcstate state) +{ + if (enable == state) + { + DMAC_CTLL(channel) |= ctlx_int_en; //ͨȫж + DMAC_MASKTFR = (1 << channel) | (1 << (channel + 8)); //ٲ + DMAC_MASKBLOCK = (1 << channel) | (1 << (channel + 8)); + DMAC_MASKSRCTRAN = (1 << channel) | (1 << (channel + 8)); + DMAC_MASKDSTTRAN = (1 << channel) | (1 << (channel + 8)); + DMAC_MASKERR = (1 << channel) | (1 << (channel + 8)); + }else + { + DMAC_CTLL(channel) = ~(uint32)ctlx_int_en; //ͨȫж + } +} + + +/* +* @func: dma óʼ +* @param None +* @retval None +*/ +int dma_init(dma_channel_enum channel,DMA_InitTypeDef *p) +{ + dma_deinit(channel); + /*!< clear interrupt*/ + DMAC_CLEARTFR = (1 << channel) & 0xff; + DMAC_CLEARBLOCK = (1 << channel) & 0xff; + DMAC_CLEARSRCTRAN = (1 << channel) & 0xff; + DMAC_CLEARDSTTRAN = (1 << channel) & 0xff; + DMAC_CLEARERR = (1 << channel) & 0xff; + + /*жûȫ0򷵻err*/ + if(DMAC_RAWTFR & (1 << channel) || DMAC_RAWBLOCK & (1 << channel) || DMAC_RAWSRCTRF & (1 << channel) || DMAC_RAWDSTTFR & (1 << channel) || DMAC_RAWERR & (1 << channel)) + { + /*err Ϣ*/ + LOG_ERROR("dma clear irq err!\r\n"); + return -1; + } + + //LLPãʱûõ + // DMAC_LLP(channel) =; + //--------------------------------- + + DMAC_SAR(channel) = p->s_addr; // source address + DMAC_DAR(channel) = p->d_addr; // dest address + + DMAC_CTLH(channel) = (p->buff_size) ; + DMAC_CTLL(channel) = p->d_width | p->s_width | p->d_addr_inc | p->s_addr_inc | p->d_mszie | p->s_msize | p->transfer_type | p->d_master | p->s_master | p->llp_d_en | p->llp_s_en; + + + DMAC_CFGL(channel) |= (uint32_t)(HS_HARD_DST | HS_HARD_SRC | p->reload_s_addr | p->reload_d_addr) | ((~channel & 0x07) << 5); + DMAC_CFGH(channel) = ((p->s_interface) << 7) | ((p->d_interface) << 11) | ((p->fifo_mode) << 1); + + return 0; + } + + +/* +* @func: dma ͨʹ +* @param channel +* @param status:enable/disable +* @retval None +*/ +void dma_cmd(dma_channel_enum channel,funcstate state) +{ + if(enable ==state) + { + /*!SDP_HB[0] = (SdPackHB0Reg & 0xff); + p->SDP_HB[1] = (SdPackHB0Reg >> 8) & 0xff; + p->SDP_HB[2] = (SdPackHB0Reg >> 16) & 0xff; //SDP Type = 08h + p->SDP_HB[3] = (SdPackHB0Reg >> 24) & 0xff; //SDP ID = 00h + + p->SDP_DB[0] = (SdPackDB0Reg & 0xff); + p->SDP_DB[1] = (SdPackDB0Reg >> 8) & 0xff; + p->SDP_DB[2] = (SdPackDB0Reg >> 16) & 0xff; + p->SDP_DB[3] = (SdPackDB0Reg >> 24) & 0xff; + + + p->SDP_DB[4] = (SdPackDB4Reg & 0xff); // FFhEnable DBV update with DB5 and DB6 value + p->SDP_DB[5] = (SdPackDB4Reg >> 8) & 0xff; // DBV : Display Brightness Value. + p->SDP_DB[6] = (SdPackDB4Reg >> 16) & 0xff; // {5h00,DBV[10:8]} + p->SDP_DB[7] = (SdPackDB4Reg >> 24) & 0xff; + + + p->SDP_DB[8] = (SdPackDB8Reg & 0xff); + p->SDP_DB[9] = (SdPackDB8Reg >> 8) & 0xff; + p->SDP_DB[10] = (SdPackDB8Reg >> 16) & 0xff; + p->SDP_DB[11] = (SdPackDB8Reg >> 24) & 0xff; + + p->SDP_DB[12] = (SdPackDB12Reg & 0xff); + p->SDP_DB[13] = (SdPackDB12Reg >> 8) & 0xff; + p->SDP_DB[14] = (SdPackDB12Reg >> 16) & 0xff; + p->SDP_DB[15] = (SdPackDB12Reg >> 24) & 0xff; + + + p->SDP_DB[16] = (SdPackDB16Reg & 0xff); + p->SDP_DB[17] = (SdPackDB16Reg >> 8) & 0xff; + p->SDP_DB[18] = (SdPackDB16Reg >> 16) & 0xff; + p->SDP_DB[19] = (SdPackDB16Reg >> 24) & 0xff; + + p->SDP_DB[20] = (SdPackDB20Reg & 0xff); + p->SDP_DB[21] = (SdPackDB20Reg >> 8) & 0xff; + p->SDP_DB[22] = (SdPackDB20Reg >> 16) & 0xff; + p->SDP_DB[23] = (SdPackDB20Reg >> 24) & 0xff; + + p->SDP_DB[24] = (SdPackDB24Reg & 0xff); + p->SDP_DB[25] = (SdPackDB24Reg >> 8) & 0xff; + p->SDP_DB[26] = (SdPackDB24Reg >> 16) & 0xff; + p->SDP_DB[27] = (SdPackDB24Reg >> 24) & 0xff; + + p->SDP_DB[28] = (SdPackDB28Reg & 0xff); + p->SDP_DB[29] = (SdPackDB28Reg >> 8) & 0xff; + p->SDP_DB[30] = (SdPackDB28Reg >> 16) & 0xff; + p->SDP_DB[31] = (SdPackDB28Reg >> 24) & 0xff; + + p->SDP_ERR_FLAG[0] = (SdPackErrReg & 0xff); + p->SDP_ERR_FLAG[1] = (SdPackErrReg >> 8) & 0xff; +} + +/*@func:ѡsinkصݴdata0~15Ĵ,ͿԶsinkصֵ + *@para: + *@return : +*/ +void aux_read_sink_set(void) +{ + AuxwrReg = 1; +} + +/*@func:ȡauxdata0~data15Ĵݣauxжʱ + * AuxwrReg =1ʱsinkݰȻֻsourceݰ + *@para: + *@return : +*/ +void aux_packet_read(Aux_TypeDef *p) +{ + p->len = (AuxPack0Reg & 0xff); + p->addr = ((AuxPack0Reg & 0x0fffff00) >> 8); + p->cmd = ((AuxPack0Reg & 0xf0000000) >> 28); + p->data[3] = (AuxPack1Reg & 0xff); + p->data[2] = ((AuxPack1Reg >> 8) & 0xff); + p->data[1] = ((AuxPack1Reg >> 16) & 0xff); + p->data[0] = ((AuxPack1Reg >> 24) & 0xff); + + p->data[7] = (AuxPack2Reg & 0xff); + p->data[6] = ((AuxPack2Reg >> 8) & 0xff); + p->data[5] = ((AuxPack2Reg >> 16) & 0xff); + p->data[4] = ((AuxPack2Reg >> 24) & 0xff); + + + p->data[11] = (AuxPack3Reg & 0xff); + p->data[10] = ((AuxPack3Reg >> 8) & 0xff); + p->data[9] = ((AuxPack3Reg >> 16) & 0xff); + p->data[8] = ((AuxPack3Reg >> 24) & 0xff); + + p->data[15] = (AuxPack4Reg & 0xff); + p->data[14] = ((AuxPack4Reg >> 8) & 0xff); + p->data[13] = ((AuxPack4Reg >> 16) & 0xff); + p->data[12] = ((AuxPack4Reg >> 24) & 0xff); +} + +/*@func:auxжϽ뵽 mcu_ext_irq00 жȥΪIRQ13ģһͨжϣΪרжϣռһж + *@para: mcu_ext1_ir_en=0 + *@return : +*/ +void aux_irq_set_irq13(void) +{ + uint8 temp8; + temp8 = REG8(BASE_ADDR_CFG+0xB309); + temp8 &= ~(1<<7); + wr_cfgreg(0xB309, temp8); +} + + diff --git a/src/driver/source/la_gpio.c b/src/driver/source/la_gpio.c new file mode 100644 index 0000000..145e562 --- /dev/null +++ b/src/driver/source/la_gpio.c @@ -0,0 +1,175 @@ + +#include "la_config.h" + +/* @function:PINŵӦù + * @pin:gpiox(x=0~30) + * @mode: 00- gpio function @IO_MODE +* 01- brideg hal @ +* 10- Tcon @ +* 11- debug @DEBUG_MODE +*/ + +void gpiox_func_sel(uint8 pin, uint8 mode) +{ + uint32 val=0; + uint8 shift=0; + if(pin < 15) + { + val = read_addr_UINT32(BASE_ADDR_CFG+0xb300); + shift =2*pin; + val &= ~(3 << (2 * pin)); + val |= mode << (2 * pin); + write_addr_UINT32(BASE_ADDR_CFG+0xb300, val); + }else + { + val = read_addr_UINT32(BASE_ADDR_CFG + 0xb304); + shift = 2 * (pin-16); + val &= ~(3 << shift); + val |= mode << shift; + write_addr_UINT32(BASE_ADDR_CFG + 0xb304, val); + } +} + + +/* @function:PINŵĵѹģʽ +* +*/ +void gpiox_set_power_level(void) +{ + +} + + +/* @function:PINŵdebugź +* @pin: GPIOx_COMBO:(x=0 ~ 9) +* +*/ +void gpiox_set_debug_signal(uint8 pin, uint16 bus, uint8 sel) +{ + uint8 bus_H = bus >> 8; + uint8 bus_L = bus & 0xff; + + uint8 temp1 = pin / 2; + uint8 temp2 = pin % 2; + uint8 temp3; + wr_cfgreg(0xed00, 0x03); + wr_cfgreg(0xed01 + pin, bus_L); + temp3 =read_addr_UINT8(0xed0b + temp1); + wr_cfgreg(0xed0b + temp1, temp3 | sel << (4* temp2)); + + temp1 = pin / 4; + temp2 = pin % 4; + + temp3 = read_addr_UINT8(0xed10 + temp1); + wr_cfgreg(0xed10 + temp1, temp3 | bus_H << (2*temp2)); + + gpiox_func_sel(pin, DEBUG_MODE); +} + +/* @function:IOģʽʹ,Ƿgpio + * @pin:gpiox(x=0~30) +* @statENABLE/DISABLE +*/ +void gpiox_func_enable(uint8 pin, uint8 stat) +{ + uint32 temp; + temp =read_addr_UINT32(BASE_ADDR_GPIO+0x00); //gpio_en + temp &=(~(1<< pin)); + temp |= stat<< pin; + write_addr_UINT32(BASE_ADDR_GPIO + 0x00, temp); +} + +/* @function:IOΪģʽ + * @pin:gpiox(x=0~30) +* +*/ +void gpiox_func_input(uint8 pin) +{ + gpiox_func_sel(pin, IO_MODE); //Ϊgpioģʽ + gpiox_func_enable(pin, ENABLE);//gpio + write_addr_UINT8(BASE_ADDR_GPIO + 0x04 +pin,0x01); //gpio_dout_en +} + +/* @function:IOΪģʽ + * @pin:gpiox(x=0~30) +* +*/ +void gpiox_func_output(uint8 pin) +{ + gpiox_func_sel(pin, IO_MODE); //Ϊgpioģʽ + gpiox_func_enable(pin, ENABLE);//gpio + write_addr_UINT8(BASE_ADDR_GPIO + 0x04 + pin, 0x03); //gpio_dout_en,Ĭ͵ƽ +} + +/* @function:IOƽ״̬ + * @pin:gpiox(x=0~30) +* @stat:GPIO_HIGH/GPIO_LOW +*/ +void gpiox_func_write(uint8 pin, uint8 stat) +{ + write_addr_UINT8(BASE_ADDR_GPIO + 0x04 + pin, stat); //gpio_dout_en +} + + + +/* @function:ȡIOƽ״̬ + * @pin:gpiox(x=0~30) +* +*/ +uint8 gpiox_func_read(uint8 pin) +{ + uint32 temp; + temp = read_addr_UINT32(BASE_ADDR_GPIO + 0x24); //gpio_din + temp = (temp >> pin) & 0x01; + return temp; +} + + +/* @function:gpiĹܣ̶Ϊģʽ + * @pin:gpiox(x=0~5) +* +*/ +uint8 gpix_func_enable(uint8 pin, uint8 stat) +{ + uint32 temp; + temp = read_addr_UINT32(BASE_ADDR_GPIO + 0x28); //gpi_en + temp &= (~(1 << pin)); + temp |= stat << pin; + write_addr_UINT32(BASE_ADDR_GPIO + 0x28, temp); +} + + +/* @function:ȡgpiֵ + * @pin:gpiox(x=0~5) + * + */ +uint8 gpix_func_read(uint8 pin) +{ + uint32 temp; + temp = read_addr_UINT32(BASE_ADDR_GPIO + 0x2c); //gpi_din + temp = (temp >> pin) & 0x01; + return temp; +} + + +/* @function:IOߵƽ + * @pin:gpiox(x=0~30) +* +*/ +void gpiox_output_high(uint8 pin) +{ + gpiox_func_sel(pin, IO_MODE); //Ϊgpioģʽ + gpiox_func_enable(pin, ENABLE);//gpio + gpiox_func_write(pin, GPIO_HIGH); //ߵƽ +} + +/* @function:IO͵ƽ + * @pin:gpiox(x=0~30) +* +*/ +void gpiox_output_low(uint8 pin) +{ + gpiox_func_sel(pin, IO_MODE); //Ϊgpioģʽ + gpiox_func_enable(pin, ENABLE);//gpio + gpiox_func_write(pin, GPIO_LOW); //ߵƽ +} \ No newline at end of file diff --git a/src/driver/source/la_i2c.c b/src/driver/source/la_i2c.c new file mode 100644 index 0000000..f0bfb88 --- /dev/null +++ b/src/driver/source/la_i2c.c @@ -0,0 +1,390 @@ +#include "la_config.h" + + +/************************************************ +* @func: i2c deinit +* @param i2cx:(x=0,1,3) +* @retval NONE +*************************************************/ +void i2c_deinit(uint32_t i2cx) +{ + IC_CON(i2cx) = 0x00; // i2c ctrl + IC_INTR_MASK(i2cx) = 0x00; // irq all disable +} + + +/************************************************ +* @func: i2c_addrformat_addr_conifg +* @param i2cx:(x=0,1,3) +* @param addformat: +* I2C_MASTERADDR_7BITS/I2C_MASTERADDR_10BITS +* I2C_SLAVERADDR_7BITS/I2C_SLAVERADDR_10BITS +* @param addr: I2C slaver address: 7bit address +* @retval NONE +*************************************************/ +void i2c_addrformat_addr_conifg(uint32 i2cx, uint32 addformat, uint32 addr) +{ + if (i2cx != I2C2) + { + IC_CON(i2cx) |= (IC_SLAVE_DISABLE | I2C_MASTER_ENABLE | addformat); //diasble slaver enable master + IC_TAR(i2cx) = addr & 0x3ff; + } + else + { + IC_CON(i2cx) &= ~(IC_SLAVE_DISABLE | I2C_MASTER_ENABLE | IC_10BITADDR_SLAVE); //diasble master enable slaver + IC_CON(i2cx) |= (I2C_SLAVER_ENABLE | addformat); + IC_SAR(i2cx) = addr & 0x3ff; + } +} + + +/************************************************ +* @func: i2c_clock_config +* @param i2cx:(I2Cx=0,1,2) +* @param speed: +* -SPEED_STANDBT_MODE +* -SPEED_FAST_MODE +* -SPEED_HIGHT_MODE +* @param addr: I2C slaver address +* @retval NONE +*************************************************/ +void i2c_clock_config(uint32 i2cx, uint32 speed) +{ + uint32 temp32; + + temp32= IC_CON(i2cx); + temp32 &= ~(3 << 1); + IC_CON(i2cx) =(temp32 | speed); + if (speed == SPEED_STANDBT_MODE) + { + IC_SS_SCL_HCNT(i2cx) = 0x10;(I2C_CLK / 1000000) * 5; + IC_SS_SCL_LCNT(i2cx) = 0x10;(I2C_CLK / 1000000) * 5; + //IC_FS_SPKLEN(i2cx) = 0x00; //ģʽµ˲ϵ + } + else + { + IC_FS_SCL_HCNT(i2cx) = (I2C_CLK / 1000000) * 1; + IC_FS_SCL_LCNT(i2cx) = (I2C_CLK / 1000000) * 2; + } +} + + +/************************************************ +* @func: i2c_gen_restart +* @param i2cx:(I2Cx=0,1,2) +* @retval NONE +*************************************************/ +void i2c_gen_restart(uint32 i2cx) +{ + IC_CON(i2cx) |= IC_RESTART_EN; +} + +/************************************************ +* @func: i2c_stop +* @param i2cx:(I2Cx=0,1,2) +* @retval NONE +*************************************************/ +void i2c_stop(uint32 i2cx) +{ + IC_DATA_CMD(i2cx) = I2C_STOP; +} + + +/************************************************ +* @func: i2c_write +* @param i2cx:(I2Cx=0,1,2) +* @param byte: +* @retval NONE +*************************************************/ +void i2c_write(uint32 i2cx, uint32 byte) +{ + IC_DATA_CMD(i2cx) = byte; +} + +/************************************************ +* @func: i2c_issue_read:i2c send a read signal +* @param i2cx:(I2Cx=0,1,2) +* @retval NONE +*************************************************/ +void i2c_issue_read(uint32 i2cx) +{ + IC_DATA_CMD(i2cx) = I2C_READ_CMD; +} + + +/************************************************ +* @func: i2c_read +* @param i2cx:(I2Cx=0,1,2) +* @retval NONE +*************************************************/ +uint8 i2c_read(uint32 i2cx) +{ + return IC_DATA_CMD(i2cx) & I2C_DATA; +} + + +/************************************************ +* @func: i2c_itconfig +* @param i2cx:(I2Cx=0,1,2) +* @param irq: I2C_IT_TYPE enum +* @param state: funcstate enum +* @retval NONE +*************************************************/ +void i2c_itconfig(uint32 i2cx, I2C_IT_TYPE irq, funcstate state) +{ + IC_INTR_MASK(i2cx) &= ~(1<> 8) & 0xff; + data[i * 4 + 2] = (temp32 >> 16) & 0xff; + data[i * 4 + 3] = (temp32 >> 24) & 0xff; + } + temp32 = AP_RXSRC; + if (len % 4 != 0) + { + temp4= (temp4 - 1) * 4; + for(uint8 i=0;i< len % 4;i++) + { + data[temp4 +i] = (temp32 >> (8*i)) & 0xff; + } + } + else + { + data[len - 4] = temp32 & 0xff; + data[len - 3] = (temp32 >> 8) & 0xff; + data[len - 2] = (temp32 >> 16) & 0xff; + data[len - 1] = (temp32 >> 24) & 0xff; + } +} + + + +/************************************************ +* @func: spi tch_init: + spi tch register deinit +* @param NONE +* @retval NONE +*************************************************/ +void tch_init(TCH_TypeDef *p) +{ + //clear irq + TCH_ICR = 0x07f; + TCH_CTRL = p->endian | p->cmden; + TCH_POL = p->sckpol; + + //TCH_CLR = r_fifo_clr; //fifo + //TCH_CLR = 0x00; +} + + +/* +* @func: SPI TCH IRQ +* @param: 5 irq type +* @param: enbale/disable +* @retval NONE +*/ +void tch_it_config(TCH_IT_TYPE type, funcstate state) +{ + TCH_IMR &= ~(1 << type); + TCH_IMR |= state << type; +} + + +/* +* @func: spi tch ж +* @param 5 irq type +* @retval NONE +*/ +void tch_clear_it_flag(TCH_IT_TYPE type) +{ + TCH_ICR = (1 << type); +} + + +/* +* @func: ȡspi tchж +* @param 5 irq type +* @retval 0/1 +*/ +intstatus tch_get_it_flag(TCH_IT_TYPE type) +{ + intstatus bit = reset; + if (TCH_ISR & (1ul << type)) + { + bit = set; + } + else + { + bit = reset; + } + return bit; +} + + +/* +* @func: SPI tch fifo +* @param NONE +* @retval NONE +*/ +void tch_clear_tx_fifo(void) +{ + TCH_CLR = r_fifo_clr; + TCH_CLR = 0x00; +} + +/* +* @func: SPI tch tx fifo empty жֵ,λDWORD +* @param NONE +* @retval NONE +*/ +void tch_set_tx_fifo_thres(uint8 txfifoth) +{ + TCH_FTLR = txfifoth & 0x0f; +} + + +/* +* @func: SPI tch tx fifo empty DMAֵȴʱ,λDWORDָ +* @param NONE +* @retval NONE +*/ +void tch_dma_config(uint8 txfifoth,uint8 waittime) +{ + TCH_FTLR = txfifoth & 0x0f; + TCH_DMA = waittime; +} \ No newline at end of file diff --git a/src/driver/source/la_sys.c b/src/driver/source/la_sys.c new file mode 100644 index 0000000..96f925b --- /dev/null +++ b/src/driver/source/la_sys.c @@ -0,0 +1,16 @@ + +#include "la_config.h" + + + +void sys_boot_getstatus(void) +{ + log_set_level(LOG_LEVEL_DEBUG); + LOG_DEBUG("define log level DEBUG,boot star debug log output..."); + LOG_DEBUG("boot printf enable:0x%x= 0x%x", &BOOT_PRINTF_ENABLE,BOOT_PRINTF_ENABLE); + LOG_DEBUG("flow test id:0x%x= 0x%x", &FLOW_TEST_ID,FLOW_TEST_ID); + LOG_DEBUG("flash train status:0x%x=0x%x",&FLASH_TRAIN_STATUS, FLASH_TRAIN_STATUS); + LOG_DEBUG("pre boot dma ctrl:0x%x=0x%x",&PREBOOT_DMA_CTRL, PREBOOT_DMA_CTRL); + LOG_DEBUG("pre boot status:0x%x=0x%x",&PREBOOT_STATUS, PREBOOT_STATUS); + log_set_level(LOG_LEVEL_INFO); +} \ No newline at end of file diff --git a/src/driver/source/la_timer.c b/src/driver/source/la_timer.c new file mode 100644 index 0000000..890cbe4 --- /dev/null +++ b/src/driver/source/la_timer.c @@ -0,0 +1,196 @@ +#include "la_config.h" + + +/* + * Tout = ARR * PSC / Tclk + * Tout:ʱ + * ARRԶװֵ + * PSCԤƵϵ + * TclkʱʱƵ +*/ + + +/*@funciton: deinit timer +* @param timerx:(GPTM_CHx=0,1,2...11) +* @retval NONE +*/ +void gptm_deinit(uint32 timerx) +{ + GPTM_ARR(timerx) = 0x00; + GPTM_PSC(timerx) = 0x00; + GPTM_CCR(timerx) = 0x00; + GPTM_INTR_CTRL(timerx) = 0x00; + GPTM_INTR_STAT(timerx) = 0x1f; + GPTM_CFG(timerx) = 0x00; + GPTM_CNT(timerx) = 0x00; + GPTM_ENABLE(timerx) = 0x00; + GPTM_TIMOUT(timerx) = 0x00; +} + + +/*@funciton: timer base init +* @param timerx:(GPTM_CHx=0,1,2...11) +* @param p: Timer_BaseParameter +* @retval NONE +*/ +void gptm_base_init(uint32 timerx, GPTM_BaseParameter *p) +{ + GPTM_ARR(timerx) = (uint16)p->autoreload; + GPTM_PSC(timerx) = (uint16)p->prescaler; + GPTM_CNT(timerx) = (uint16)p->count; + + GPTM_CFG(timerx) &= ~(uint32_t)(gptm_cnt_dir | gptm_reload_mode | gptm_arr_cntclr); + GPTM_CFG(timerx) |= (uint32_t)p->cntclr; + GPTM_CFG(timerx) |= (uint32_t)p->countmode; + GPTM_CFG(timerx) |= (uint32_t)p->autoreloadpreload; +} + + +/*@funciton: timer input capture base init + * صarr_cntclr +* @param timerx:(GPTM_CHx=0,1,2...11) +* @param p: Timer_BaseParameter +* @retval NONE +*/ +void gptm_incap_base_init(uint32 timerx, GPTM_ICParameter* p) +{ + GPTM_TIMOUT(timerx) =(uint16)p->timeout; + GPTM_CFG(timerx) &= ~(uint32_t)(gptm_edge_sel | gptm_capcomp_sel | gptm_arr_cntclr | gptm_chin_cntclr | gptm_deglitch_cnt); + GPTM_CFG(timerx) |= GPTM_IC_MODE; //Ƚģʽ + GPTM_CFG(timerx) |= (uint32_t)p->icedge; + GPTM_CFG(timerx) |= (uint32_t)p->iccntclr; + GPTM_CFG(timerx) |= (uint32_t)p->filter; +} + + +/*@funciton: timer output compare base init +* @param timerx:(GPTM_CHx=0,1,2...11) +* @param p: Timer_BaseParameter +* @retval NONE +*/ +void gptm_outcomp_base_init(uint32 timerx, GPTM_OCParameter* p) +{ + GPTM_CCR(timerx) = (uint16)p->compare; + GPTM_CFG(timerx) &= ~(uint32_t)(gptm_capcomp_sel | gptm_out_polar | gptm_outcomp_mode); + GPTM_CFG(timerx) |= GPTM_OC_MODE; //Ƚģʽ + GPTM_CFG(timerx) |= (uint32_t)p->ocsubmode; + GPTM_CFG(timerx) |= (uint32_t)p->ocpolarity; +} + +/*@funciton: enable timer +* @param timerx:(GPTM_CHx=0,1,2...11) +* @retval NONE +*/ +void gtpm_cmd(uint32 timerx,funcstate stat) +{ + GPTM_ENABLE(timerx) = stat; +} + + +/*@funciton: gptm_soft_clr0 + soft write 1 to clear count zero +* @param timerx:(GPTM_CHx=0,1,2...11) +* @retval NONE +*/ +void gptm_soft_clr0(uint32 timerx) +{ + GPTM_ENABLE(timerx) = gptm_ug_cntclr; +} + +/*@funciton: gptm_read_incap_egde + read input capture dual edge is rising or falling edge +* @param timerx:(GPTM_CHx=0,1,2...11) + *@retval: 1:½ 0: +*/ +FlagStatus gptm_read_incap_egde(uint32 timerx) +{ + intstatus bit = reset; + if (GPTM_CFG(timerx) & (1ul << chin_edge_flag)) + { + bit = set; + } + else + { + bit = reset; + } + return bit; +} + + +/*@funciton: read timer count +* @param timerx:(GPTM_CHx=0,1,2...11) + *@retval: ؼֵ +*/ +uint32_t gptm_get_count(uint32 timerx) +{ + uint32_t count_value = 0U; + count_value = GPTM_CNT(timerx); + return (count_value); +} + + +/*@funciton: read interrupt flag +* @param[0] timerx:(GPTM_CHx=0,1,2...11) + *@param[1] irq:the timer interrupt bits +* only one parameter can be selected which is shown as below: +* +* +* +* +* +* +* @retval +*/ +FlagStatus gptm_get_itflag(uint32 timerx, GPTM_IT_TYPE irq) +{ + intstatus bit = reset; + if (GPTM_INTR_STAT(timerx) & irq) + { + bit = set; //жϲ + } + else + { + bit = reset; //жϲ + } + return bit; +}; + + +/*@funciton: interrupt flag clear 0 + *@param[0] timerx:(GPTM_CHx=0,1,2...11) + *@param[1] irq:the timer interrupt bits +* only one parameter can be selected which is shown as below: +* +* +* +* +* +* +* @retval:NONE +*/ +void gtpm_clear_irqflag(uint32 timerx, GPTM_IT_TYPE irq) +{ + GPTM_INTR_STAT(timerx) =irq; +} + + +/*@funciton: interrupt enable +* @param timerx:(GPTM_CHx=0,1,2...11) + *@retval: NONE +*/ +uint32_t gptm_itconfig(uint32 timerx, GPTM_IT_TYPE irq) +{ + GPTM_INTR_CTRL(timerx) |= irq; +} + +void sys_clk_get(void) +{ + log_set_level(LOG_LEVEL_DEBUG); + LOG_DEBUG("define log level DEBUG,pll star debug log output..."); + LOG_DEBUG("sys_osc_clk: %d MHZ", 100); + LOG_DEBUG("pll1_clk: %d MHz", 140); + LOG_DEBUG("pll2_clk: %d MHz", 120); + LOG_DEBUG("pll3_clk: %d MHz", 200); + LOG_DEBUG("pll4_clk: %d MHz", 95); + log_set_level(LOG_LEVEL_INFO); +} \ No newline at end of file diff --git a/src/driver/source/la_uart.c b/src/driver/source/la_uart.c new file mode 100644 index 0000000..f127d41 --- /dev/null +++ b/src/driver/source/la_uart.c @@ -0,0 +1,61 @@ +#include "la_config.h" + + +void UartStdOutInit(void) +{ + gpiox_func_sel(22, BRIDGE_MODE); //Ϊbridgeģʽ, GPIO22Ϊuart rx pin + gpiox_func_sel(23, BRIDGE_MODE); //Ϊbridgeģʽ, GPIO23Ϊuart tx pin + //CMSDK_UART0->BAUDDIV = 16; + //CMSDK_UART0->CTRL = 0x41; // High speed test mode, TX only + CMSDK_UART1->BAUDDIV = 1302; + CMSDK_UART1->CTRL = 0x03; // High speed test mode, TX only + return; +} + +// Output a character---͵ַ +unsigned char UartPutc(unsigned char my_ch) +{ + while ((CMSDK_UART1->STATE & 1)); // Wait if Transmit Holding register is full + CMSDK_UART1->DATA = my_ch; // write to transmit holding register + return (my_ch); +} +// Get a character ---յַ +unsigned char UartGetc(void) +{ + while ((CMSDK_UART1->STATE & 2) == 0); // Wait if Receive Holding register is empty + return (CMSDK_UART1->DATA); +} + +// ʾͨUART־ +void uart_output(const char* message) { + // RISC-V ICUARTʵ + // ʵӦҪӲʵ + //volatile uint32_t* uart_base = (uint32_t*)0x10000000; // UARTַ + + while (*message != '\0') { + // ȴUART + //while ((*(uart_base + 1) & 0x2) == 0); + // һַ + //*uart_base = (uint32_t)*message++; + UartPutc(*message++); + } + + // ͻз + //while ((*(uart_base + 1) & 0x2) == 0); + //*uart_base = '\n'; + UartPutc('\n'); +} + + +// ַ +void uart_send_str(const char* str) { + while (*str) { + UartPutc(*str++); + } +} + +// Ƿݴ +bool uart_has_data(void) { + return (CMSDK_UART1->STATE & 2) != 0; +} + diff --git a/src/driver/source/la_wdg.c b/src/driver/source/la_wdg.c new file mode 100644 index 0000000..151855f --- /dev/null +++ b/src/driver/source/la_wdg.c @@ -0,0 +1,89 @@ +#include "la_config.h" + + +/* @fun: deinit watchdog + * + */ +void wdg_deinit(void) +{ + WDG_CFG |= WDG_KEY; + WDG_CFG =0x00; + WDG_CFG |= WDG_KEY; + WDG_CNT_CMP =0x00; +} + + +/* @fun: feed watchdog + * + */ +void wdg_feed(void) +{ + WDG_CFG |= WDG_KEY; + WDG_CFG |= WDG_FEED << 8 ; +} + + +/* @fun: start watchdog timer counter + * whithout zerocmp and rst + */ +void wdg_start(void) +{ + WDG_CFG |= WDG_KEY; + WDG_CFG &=(~(uint32)(WDG_CFG_ZERO_CMP | WDG_CFG_RSTEN)); + WDG_CFG |= WDG_KEY; + WDG_CFG |= WDG_CFG_EN; //ʹܿŹ +} + + +/* @fun: start watchdog timer counter + * whithout zerocmp + */ +void wdg_start_with_rst(void) +{ + WDG_CFG |= WDG_KEY; + WDG_CFG &= (~(uint32)(WDG_CFG_ZERO_CMP)); + WDG_CFG |= WDG_KEY; + WDG_CFG |= WDG_CFG_RSTEN; //ʹܲλ + WDG_CFG |= WDG_KEY; + WDG_CFG |= WDG_CFG_EN; //ʹܿŹ +} + +/* @fun: start watchdog timer counter + * whithout rst +* with zerocmp + */ +void wdg_start_with_zerocmp(void) +{ + WDG_CFG |= WDG_KEY; + WDG_CFG &= (~(uint32)(WDG_CFG_RSTEN)); + WDG_CFG |= WDG_KEY; + WDG_CFG |= WDG_CFG_EN; //ʹܿŹ + WDG_CFG |= WDG_KEY; + WDG_CFG |= WDG_CFG_ZERO_CMP; //ʹܼ +} + +/* @fun: start watchdog timer counter + * with zerocmp and rst + */ +void wdg_start_with_zerocmp_and_rst(void) +{ + WDG_CFG |= WDG_KEY; + WDG_CFG |= WDG_CFG_EN; //ʹܿŹ + WDG_CFG |= WDG_KEY; + WDG_CFG |= WDG_CFG_ZERO_CMP; //ʹܼ + WDG_CFG |= WDG_KEY; + WDG_CFG |= WDG_CFG_RSTEN; //ʹܲλ +} + +/* @fun: watchdog base init + * + */ +void wdg_base_init(uint8 div,uint16 count,uint16 comp) +{ + WDG_CFG |= WDG_KEY; + WDG_CFG |= div <<24; //ʱӷƵϵƵ + WDG_CFG |= WDG_KEY; + WDG_CNT_CMP |= count; // + WDG_CFG |= WDG_KEY; + WDG_CNT_CMP |= comp << 16; //Ƚֵֵж +} diff --git a/src/driver/source/perip_test.c b/src/driver/source/perip_test.c new file mode 100644 index 0000000..b2e14a9 --- /dev/null +++ b/src/driver/source/perip_test.c @@ -0,0 +1,407 @@ +// IJdemo ļ +#include "la_config.h" + +#ifdef W818_TEST_MENU +#include + +void gpio_output_high_low_test(void); +void gpio_input_read_test(void); +void spi_ap_init(void); + +//  +#define CMD_BUFFER_SIZE 64 +char g_cmd_buffer[CMD_BUFFER_SIZE]; +uint8_t g_cmd_len = 0; + +// ʾ˵ +void show_menu(void) { + uart_send_str("\n************* W818 PERIPHERAL TEST MENU CONFIG*************\n"); + uart_send_str("1. gpio output hight & low function test\n"); + uart_send_str("2. gpio input function test\n"); + uart_send_str("3. gpio bridge function test\n"); + uart_send_str("4. gpio Tcon function test\n"); + uart_send_str("5. gpio deubg function test\n"); + uart_send_str("6. wgd test\n"); + uart_send_str("7. spi slaver test\n"); + uart_send_str("8. i2c master test\n"); + uart_send_str("9. i2c slaver test\n"); + uart_send_str("10. dma test\n"); + uart_send_str("11. interrupt test\n"); + uart_send_str("12. cabc test\n"); + uart_send_str("13. gptm test\n"); + uart_send_str("h. return menu config\n"); + uart_send_str("q. quite test\n"); + uart_send_str("\nwaiting,please select number: "); +} + +// յ +void process_command(void) { + uart_send_str("\n"); // + if (g_cmd_len == 0) return; + switch (g_cmd_buffer[0]) { + case '1': + uart_send_str("Start gpio output test...\n"); + gpio_output_high_low_test(); + uart_send_str("gpio test ok...\n"); + break; + case '2': + uart_send_str("Start gpio input test...\n"); + gpio_input_read_test(); + uart_send_str("gpio test ok...\n"); + break; + case '3': + uart_send_str("Start gpio bridge test...\n"); + uart_send_str("gpio test ok...\n"); + break; + case '4': + uart_send_str("Start gpio tcon test...\n"); + uart_send_str("gpio test ok...\n"); + break; + case '5': + uart_send_str("Start gpio debug test...\n"); + uart_send_str("gpio test ok...\n"); + break; + case '6': + uart_send_str("Start wdg test...\n"); + uart_send_str("gpio test ok...\n"); + break; + case '7': + uart_send_str("Start ap spi slaver test...\n"); + spi_ap_init(); + uart_send_str("spi test ok...\n"); + break; + case '8': + uart_send_str("Start i2c slaver test...\n"); + break; + case '9': + uart_send_str("Start dma test...\n"); + break; + //case '10': + // uart_send_str("Start interrupt test...\n"); + // break; + //case '11': + // uart_send_str("Start cabc test...\n"); + // break; + //case '12': + // uart_send_str("Start gptm test...\n"); + // break; + case 'h': + case 'H': + show_menu(); // ʾʾ˵ + break; + case 'q': + case 'Q': + uart_send_str("peripher quite...\n"); + while(1); // ѭģ˳ + default: + uart_send_str("undefine cmd! please key 'h' for more help\n"); + } + + //  + memset(g_cmd_buffer, 0, CMD_BUFFER_SIZE); + g_cmd_len = 0; + uart_send_str("please key 'h', return menu config\n"); + // ɺ󷵻ز˵ + //show_menu(); +} + +void test_show_menu(void) +{ + char c; + if (uart_has_data()) { + c = UartGetc(); + // ַ + UartPutc(c); + + // س + if (c == '\r' || c == '\n') { + process_command(); + } + // ˸ + else if (c == '\b' && g_cmd_len > 0) { + g_cmd_len--; + g_cmd_buffer[g_cmd_len] = '\0'; + } + // ַ + else if (g_cmd_len < CMD_BUFFER_SIZE - 1) { + g_cmd_buffer[g_cmd_len++] = c; + g_cmd_buffer[g_cmd_len] = '\0'; + } + } +} + +//*******************************GPIO Ӧ +/*1.еIO PinΪGPIOܣΪģʽߵƽ*/ +void gpio_output_high_low_test(void) +{ + for (uint8 i = 0; i < 22; i++) + { + gpiox_func_sel(i, IO_MODE); //Ϊgpioģʽ + gpiox_func_enable(i, ENABLE);//gpio + //gpiox_func_output(i); //Ϊģʽ + gpiox_func_write(i, GPIO_HIGH); //ߵƽ + gpiox_func_write(i, GPIO_LOW); //͵ƽ + gpiox_func_write(i, GPIO_HIGH); //ߵƽ + } + //22,23ΪRX,TXΪ˲ԣͲ22,23ΪIOģʽˡ + for (uint8 i = 24; i < 30; i++) + { + gpiox_func_sel(i, IO_MODE); //Ϊgpioģʽ + gpiox_func_enable(i, ENABLE);//gpio + //gpiox_func_output(i); //Ϊģʽ + gpiox_func_write(i, GPIO_HIGH); //ߵƽ + gpiox_func_write(i, GPIO_LOW); //͵ƽ + gpiox_func_write(i, GPIO_HIGH); //ߵƽ + } +} + +void gpio_input_read_test(void) +{ + gpiox_output_high(0); //GPIO0Ϊߵƽ + + for (uint8 i = 1; i < 22; i++) + { + gpiox_func_input(i); + if (gpiox_func_read(i) == 1) + { + LOG_INFO("gpio%d = 1",i); + } + } + //22,23ΪRX,TXΪ˲ԣͲ22,23ΪIOģʽˡ + for (uint8 i = 24; i < 30; i++) + { + gpiox_func_input(i); + if (gpiox_func_read(i) == 1) + { + LOG_INFO("gpio%d = 1", i); + } + } +} + +void gpio_bridge_test(void) +{ + //bridgeܣЩӲPIN ĸģʽúĹܣҪֲͬʹãap_spi/ap_i2c. + //˹ܲԣԡ + for (uint8 i = 0; i < 22; i++) + { + gpiox_func_sel(i, BRIDGE_MODE); //Ϊgpioģʽ + } + //22,23ΪRX,TXΪ˲ԣͲ22,23Ϊbridgeģʽˡ + for (uint8 i = 24; i < 30; i++) + { + gpiox_func_sel(i, BRIDGE_MODE); //Ϊgpioģʽ + } +} + +void gpio_tcon_test(void) +{ + +} + +void gpio_debug_test(void) +{ + +} + +//-------------------------------------------dma Ӧ +uint8 s_buff[] = { 0x62,0x88,0x62,0x88,0x01,0x02,0x01,0x01,0x01,0x01,0x01,0x01,0x00, + 0x47,0x39,0x4C,0x48,0x37,0x43,0x30,0x30,0x35,0x58,0x38,0x30,0x30,0x30,0x30,0x38, + 0x37,0x4C,0x42,0x58,0x58,0x58,0x4B,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30, + 0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30, + 0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30, + 0x30,0x30,0x37,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30, + 0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30, + 0x30,0x43,0x34,0x33,0x48,0x36,0x52,0x5A,0x5A,0x53,0x31,0x35,0x30,0x30,0x30,0x30, + 0x31,0x35,0x36,0x2B,0x41,0x2B,0x31,0x32,0x30,0x4C,0x4C,0x31,0x48,0x35,0x58,0x33, + 0x31,0x33,0x45,0x4C,0x30,0x30,0x30,0x30,0x31,0x35,0x38,0x2B,0x41,0x47,0x4A,0x36, + 0x48,0x36,0x38,0x30,0x33,0x34,0x4E,0x36,0x30,0x30,0x30,0x30,0x43,0x45,0x38,0x47, + 0x4A,0x36,0x48,0x35,0x38,0x30,0x32,0x48,0x47,0x50,0x30,0x30,0x30,0x30,0x31,0x35, + 0x41,0x47,0x4B,0x4B,0x48,0x35,0x45,0x32,0x4E,0x53,0x30,0x39,0x30,0x30,0x30,0x30, + 0x37,0x5A,0x50,0x38,0x4D,0x31,0x31,0x32,0x32,0x32,0x32,0x32,0x32,0x34,0x36,0x37, + 0x41,0x4E,0x4A,0x48,0x36,0x52,0x30,0x30,0x4C,0x32,0x48,0x30,0x30,0x30,0x30,0x50, + 0x56,0x31,0x41,0x36,0x41,0x58,0x4A,0x34,0x32,0x32,0x31,0x32,0x34,0x30,0x35,0x31, + 0x36,0x32,0x30,0x34,0x36,0x30,0x32,0x30,0x31,0x33,0x36,0x35,0x4A,0x57,0x58,0x58, + 0x33,0x41,0x30,0x31,0x30,0x32,0x41,0x34,0x32,0x30,0x32 }; + +uint8 d_buff[100] = { 0 }; + + +static void fill_buff(uint8* data, uint8 len) +{ + for (unsigned char i = 0; i < len; i++) + { + data[i] = i + 1; + } + +} + +/*ڴ浽ڴIJ*/ +void dma_m2m_init(void) +{ + DMA_InitTypeDef dmax; + // ڴݻཻ ͨDMA s_buff copy d_buffȥ + fill_buff(s_buff, 100); + //1. رж + dma_itconfig(DMA_CH0, disable); + + //2. ʼز + dmax.s_addr = (uint32)&s_buff; //0x80440008 s_buff + dmax.d_addr = (uint32)&d_buff; + + dmax.s_width = S_WIDTH_32; + dmax.d_width = D_WIDTH_32; + + dmax.s_addr_inc = S_ADD_INC; + dmax.d_addr_inc = D_ADD_INC; + + + dmax.d_mszie = D_MSIZE_8; + dmax.s_msize = S_MSIZE_8; //S_MSIZE_8 + + dmax.transfer_type = MEMORY_TO_MEMORY; + dmax.s_master = SRC_MASTER_PERIP; //SRC_MASTER_PERIP SRC_MASTER_MEMORY + dmax.d_master = DEST_MASTER_MEMORY; + + + dmax.buff_size = 100; + + dmax.llp_d_en = LLP_D_DIS; + dmax.llp_s_en = LLP_S_DIS; + dmax.llp = 0; + dmax.reload_d_addr = D_RELOAD_DIS; + dmax.reload_s_addr = S_RELOAD_DIS; + + dmax.d_interface = 0; + dmax.s_interface = 0; + + dmax.fifo_mode = 1; + dma_init(DMA_CH0, &dmax); + + //3.ж + dma_itconfig(DMA_CH0, enable); + + //4.ʹDMA + dma_cmd(DMA_CH0, enable); + delay_1ms(); + //dma_register_test(DMA_CH0); + + for (uint8 i = 0; i < 100; i++) + LOG_INFO("d_buff: %x\r\n", d_buff[i]); +} + + +/*flashڴIJ*/ +void dma_m2m_flash_init(void) +{ + DMA_InitTypeDef dmax; + // ڴݻཻ ͨDMA s_buff copy d_buffȥ + //1. رж + dma_itconfig(DMA_CH0, disable); + + //2. ʼز + dmax.s_addr = (uint32)0x80440008; //0x80440008 s_buff + dmax.d_addr = (uint32)&d_buff; + + dmax.s_width = S_WIDTH_32; + dmax.d_width = D_WIDTH_32; + + dmax.s_addr_inc = S_ADD_INC; + dmax.d_addr_inc = D_ADD_INC; + + + dmax.s_msize = S_MSIZE_64; //S_MSIZE_8 + dmax.d_mszie = D_MSIZE_8; + + dmax.transfer_type = MEMORY_TO_MEMORY; + dmax.s_master = SRC_MASTER_PERIP; //SRC_MASTER_PERIP SRC_MASTER_MEMORY + dmax.d_master = DEST_MASTER_MEMORY; + + + dmax.buff_size = 100; + + dmax.llp_d_en = LLP_D_DIS; + dmax.llp_s_en = LLP_S_DIS; + dmax.llp = 0; + dmax.reload_d_addr = D_RELOAD_DIS; + dmax.reload_s_addr = S_RELOAD_DIS; + + dmax.d_interface = 0; + dmax.s_interface = 0; + + dmax.fifo_mode = 1; + dma_init(DMA_CH0, &dmax); + + //3.ж + dma_itconfig(DMA_CH0, enable); + + //4.ʹDMA + dma_cmd(DMA_CH0, enable); + delay_1ms(); + for (uint8 i = 0; i < 100; i++) + LOG_INFO("d_buff: %x\r\n", d_buff[i]); +} + +//ڴ浽 +void dma_m2spi_init(void) +{ + DMA_InitTypeDef dmax; + // ڴݻཻ ͨDMA ڴݿȥ + //1. رж + dma_itconfig(DMA_CH3, disable); + + //2. ʼز + dmax.s_addr = (uint32)&s_buff; + dmax.d_addr = (uint32)&AP_TXSRC; //spi ݻ + + dmax.s_width = S_WIDTH_32; + dmax.d_width = D_WIDTH_32; + + dmax.s_addr_inc = S_ADD_INC; + dmax.d_addr_inc = D_ADD_NO; + + dmax.d_mszie = D_MSIZE_8; + dmax.s_msize = D_MSIZE_8; + + dmax.transfer_type = MEMORY_TO_PERIP; + dmax.s_master = SRC_MASTER_MEMORY; + dmax.d_master = DEST_MASTER_PERIP; + + dmax.buff_size = sizeof(s_buff); + + dmax.llp_d_en = LLP_D_DIS; + dmax.llp_s_en = LLP_S_DIS; + dmax.llp = 0; + dmax.reload_d_addr = D_RELOAD_DIS; + dmax.reload_s_addr = S_RELOAD_DIS; + + dmax.s_interface = 0; //ڴ + dmax.d_interface = 3; //spi tx + + dmax.fifo_mode = 1;//1; + dma_init(DMA_CH3, &dmax); + + //3.ж + dma_itconfig(DMA_CH3, enable); + + //4.ʹDMA + dma_cmd(DMA_CH3, enable); +} + +//--------------------------------------------AP_SPI(SPI SLAVER) Ӧ+dma +void spi_ap_init(void) +{ + //IO PIN config + gpiox_func_sel(0, BRIDGE_MODE); //Ϊgpio0 ΪAP_SCSX + gpiox_func_sel(1, BRIDGE_MODE); //Ϊgpio1 ΪAP_SSCK + gpiox_func_sel(2, BRIDGE_MODE); //Ϊgpio2 ΪAP_SSDIӻ --ӵMOSI + gpiox_func_sel(3, BRIDGE_MODE); //Ϊgpio3 ΪAP_SSDOӻ --ӵMISO + + spi_init(); + + dma_m2spi_init(); //dmaڴ濽spi Ȳdma + spi_dma_config(0x08, 0x08, 0x20, 0x20); //spi dmaز, txfifoth/rxfifoth level DMAеMSIZEһ + spi_it_config(IT_CS_END, enable); //ʹcsжϡ +} + + +#endif \ No newline at end of file diff --git a/src/driver/ulog/ulog.c b/src/driver/ulog/ulog.c new file mode 100644 index 0000000..a7433ef --- /dev/null +++ b/src/driver/ulog/ulog.c @@ -0,0 +1,184 @@ +#include "ulog.h" +#include + +// ȫֱ浱ǰ־ +static LogLevel current_level = LOG_LEVEL_INFO; +static void (*log_output_func)(const char*) = NULL; + +// ־ַӳ +static const char* log_level_strings[] = { + "DEBUG", + "INFO", + "WARN", + "ERROR", + "FATAL" +}; + +// ʼ־ϵͳ +void log_init(void (*output_func)(const char*), LogLevel default_level) { + if (output_func != NULL) { + log_output_func = output_func; + } + current_level = default_level; +} + +// õǰ־ +void log_set_level(LogLevel level) { + current_level = level; +} + +// ȡǰ־ +LogLevel log_get_level(void) { + return current_level; +} + +// 򵥵תַ +static void itoa(int num, char* buffer, int base) { + int i = 0; + int is_negative = 0; + unsigned int n; + + // 0 + if (num == 0) { + buffer[i++] = '0'; + buffer[i] = '\0'; + return; + } + + // ֧ʮƣ + if (num < 0 && base == 10) { + is_negative = 1; + n = (unsigned int)(-num); + } + else { + n = (unsigned int)num; + } + + // ת + while (n != 0) { + int rem = n % base; + buffer[i++] = (rem > 9) ? (rem - 10) + 'a' : rem + '0'; + n = n / base; + } + + // Ӹ + if (is_negative) { + buffer[i++] = '-'; + } + + // ַ + buffer[i] = '\0'; + + // תַ + int len = i; + for (int j = 0; j < len / 2; j++) { + char temp = buffer[j]; + buffer[j] = buffer[len - j - 1]; + buffer[len - j - 1] = temp; + } +} + +// 򵥵ַʽ +static int simple_vsprintf(char* buffer, const char* format, va_list args) { + int buf_idx = 0; + int fmt_idx = 0; + char int_buf[32]; + + while (format[fmt_idx] != '\0') { + if (format[fmt_idx] != '%') { + buffer[buf_idx++] = format[fmt_idx++]; + continue; + } + + // ʽַ + fmt_idx++; + switch (format[fmt_idx]) { + case 'd': { + int num = va_arg(args, int); + itoa(num, int_buf, 10); + int len = strlen(int_buf); + memcpy(&buffer[buf_idx], int_buf, len); + buf_idx += len; + break; + } + case 'x': { + int num = va_arg(args, int); + itoa(num, int_buf, 16); + int len = strlen(int_buf); + memcpy(&buffer[buf_idx], int_buf, len); + buf_idx += len; + break; + } + case 's': { + const char* str = va_arg(args, const char*); + int len = strlen(str); + memcpy(&buffer[buf_idx], str, len); + buf_idx += len; + break; + } + case 'c': { + char c = (char)va_arg(args, int); + buffer[buf_idx++] = c; + break; + } + case '%': { + buffer[buf_idx++] = '%'; + break; + } + default: { + buffer[buf_idx++] = '%'; + buffer[buf_idx++] = format[fmt_idx]; + break; + } + } + fmt_idx++; + } + + buffer[buf_idx] = '\0'; + return buf_idx; +} + +// ͨ־ʵ +void log_write(LogLevel level, const char* format, ...) { + // ־ڵǰõļ + if (level < current_level || log_output_func == NULL) { + return; + } + + char log_buffer[256]; // ̶С־ + va_list args; + + va_start(args, format); + simple_vsprintf(log_buffer, format, args); + va_end(args); + + // ־ + log_output_func(log_buffer); +} + + +//-------------demo case: + +#if 0 + +int main() { + // ʼ־ϵͳʹUARTĬ־ΪINFO + log_init(uart_output, LOG_LEVEL_INFO); + + // ͬ־ + LOG_DEBUG("sys clk: %d Hz", 100000000); + LOG_INFO("boot start succeddFW ver: %s", "v1.0.0"); + LOG_WARN("interrupt warning: %dC", 85); + LOG_ERROR("SPI errerr code: %d", 0x03); + LOG_FATAL("power val : %d mV", 890); + + // ޸־ΪDEBUGʹϢҲ + log_set_level(LOG_LEVEL_DEBUG); + LOG_DEBUG("start debug..."); + + return 0; +} + + + +#endif \ No newline at end of file diff --git a/src/driver/ulog/ulog.h b/src/driver/ulog/ulog.h new file mode 100644 index 0000000..ffa4aeb --- /dev/null +++ b/src/driver/ulog/ulog.h @@ -0,0 +1,45 @@ +#ifndef _LOG_H_ +#define _LOG_H_ + +#include + +// ־ +typedef enum { + LOG_LEVEL_DEBUG, // Ϣڿ׶ + LOG_LEVEL_INFO, // һϢ״̬ʾ + LOG_LEVEL_WARN, // Ϣʾܴ⵫Ӱ + LOG_LEVEL_ERROR, // Ϣʾ˴ϵͳɼ + LOG_LEVEL_FATAL // ϵͳ޷ +} LogLevel; + +// ʼ־ϵͳ +// : +// output_func - ־ĺָ +// default_level - Ĭϵ־ +void log_init(void (*output_func)(const char*), LogLevel default_level); + +// õǰ־ +// : +// level - Ҫõ־ +void log_set_level(LogLevel level); + +// ȡǰ־ +// : +// ǰ־ +LogLevel log_get_level(void); + +// ͨ־ +// : +// level - ־ +// format - ʽַ +// ... - ɱб +void log_write(LogLevel level, const char* format, ...); + +// ־궨 +#define LOG_DEBUG(format, ...) log_write(LOG_LEVEL_DEBUG, "" format, ##__VA_ARGS__) +#define LOG_INFO(format, ...) log_write(LOG_LEVEL_INFO, "[INFO] " format, ##__VA_ARGS__) +#define LOG_WARN(format, ...) log_write(LOG_LEVEL_WARN, "[WARN] " format, ##__VA_ARGS__) +#define LOG_ERROR(format, ...) log_write(LOG_LEVEL_ERROR, "[ERROR] " format, ##__VA_ARGS__) +#define LOG_FATAL(format, ...) log_write(LOG_LEVEL_FATAL, "[FATAL] " format, ##__VA_ARGS__) + +#endif // _LOG_H diff --git a/src/include/define.h b/src/include/define.h new file mode 100644 index 0000000..3a46ec5 --- /dev/null +++ b/src/include/define.h @@ -0,0 +1,322 @@ +#ifndef DEFINE_H +#define DEFINE_H + + +#include "typedef.h" + +//MEMORY--ICB +#define BASE_ADDR_ROM 0x00000000 //128kb +#define BASE_ADDR_IRAM 0x00020000 //128kb +#define BASE_ADDR_DRAM 0x00100000 //40kb + +//INT--ICB +#define BASE_ADDR_EXTER_IR 0x00200000 //52涓�澶��ㄤ腑�� IRQ13 +#define BASE_ADDR_IR 0x00300000 //38涓����ㄤ腑�� IRQ12 +#define BASE_ADDR_GPIO 0x90000000 +#define BASE_ADDR_CORE_PERIP 0x90000000 +//AHB-- +#define BASE_ADDR_EDPRX 0x80000000 +#define BASE_ADDR_DPRX_SDP 0x80000000 +#define BASE_ADDR_MIPITX 0x80010000 +#define BASE_ADDR_ISPTX 0x80020000 +#define BASE_ADDR_SPI_AP 0x80030000 +#define BASE_ADDR_SPI_TCH 0x80050000 +#define BASE_ADDR_QSPI 0x80060000 +#define BASE_ADDR_GPDMA 0x80070000 +#define BASE_ADDR_FLASH_IF 0x80080000 +#define BASE_ADDR_VIDEO_SRAM 0x80090000 +#define BASE_ADDR_FLASH_ARRY 0x80400000 //512K +#define BASE_ADDR_SRAM1 0x80800000 //1K + +//APB +#define BASE_ADDR_CFG 0x88000000 +#define BASE_ADDR_WDT 0x88020000 +#define BASE_ADDR_GPTM 0x88030000 + +#define BASE_ADDR_MBIST 0x88060000 +#define BASE_ADDR_SYSCTRL 0x880F0000 +#define BASE_ADDR_I2C_S 0x88100000 +#define BASE_ADDR_I2C0_M 0x88120000 +#define BASE_ADDR_I2C1_M 0x88110000 +#define BASE_ADDR_UART 0x88140000 +#define BASE_ADDR_DPCD 0x88200000 + + +#define BASE_ADDR_SYS_STATUS 0x880f0000 + + + + + +//-------------------------------------------------------------------------------- +// Mipi_TX +//-------------------------------------------------------------------------------- + +#define mipi_tx_lp_hs_mode 0x8800BB02 //bit0:0--lp mode :1--hs mode +#define mipi_tx_send_data 0x80010000 // mipi tx�������版�� +#define mipi_tx_send_requset 0x80010004 // bit0 ,wrgst ���版������mipi tx���虹�宠�凤���楂� +#define mipi_tx_cmd_number 0x80010005 // bit4:bit1,cur cmd number-wrgst��楂����村���哄��cmd涓��� +#define mipi_tx_trigger_pulse 0x80010005 // bit0 ,mcu tx trigger-瀹����版��������锛���浣�wrgst锛�������triiger pulse锛�瑙���mipi tx宸ヤ� +//#define mipi_tx_int_enable 0x80010006 // mipi tx -enable +#define mipi_tx_buffer_full 0x80010007 // bitl,cmipi tx full--mipi tx瀛��炬�版����缂�瀛�婧㈠�烘��蹇� +#define mipi_tx_send_done 0x80010007 // bit0 ,mipi tx done--����trigger pulse��锛�绛�寰�mipi tx澶���瀹���锛�姝や俊�锋��瀹�����蹇� + + +#define mipi_tx_send_data_mipib 0x80010040 // mipi tx�������版�� +#define mipi_tx_send_requset_mipib 0x80010044 // bit0 ,wrgst ���版������mipi tx���虹�宠�凤���楂� +#define mipi_tx_cmd_number_mipib 0x80010045 // bit4:bit1,cur cmd number-wrgst��楂����村���哄��cmd涓��� +#define mipi_tx_trigger_pulse_mipib 0x80010045 // bit0 ,mcu tx trigger-瀹����版��������锛���浣�wrgst锛�������triiger pulse锛�瑙���mipi tx宸ヤ� +//#define mipi_tx_int_enable_mipib 0x80010016 // mipi tx -enable +#define mipi_tx_buffer_full_mipib 0x80010047 // bitl,cmipi tx full--mipi tx瀛��炬�版����缂�瀛�婧㈠�烘��蹇� +#define mipi_tx_send_done_mipib 0x80010047 // bit0 ,mipi tx done--����trigger pulse��锛�绛�寰�mipi tx澶���瀹���锛�姝や俊�锋��瀹�����蹇� + + + + +#define mipi_tx_send_done_mask 0x00000001 + +#define OFFSET_MIPITX_WRQST 0 +#define OFFSET_MIPITX_TRIG 1 +#define OFFSET_MIPITX_CMD_NUM 1 +#define OFFSET_MIPITX_INTR 2 + + +#define wr_cfg_int(addr,dat) do {*(volatile unsigned int*)((unsigned int)(BASE_ADDR_CFG+addr)) = (dat);} while(0); + +//#define wr_cfgreg(addr, dat) ( ( *( (volatile UINT8 *)(0x80080000+addr) ) ) = (UINT8)(dat) ) +#define write_addr_UINT32(reg, data) ( ( *( (volatile UINT32 *)(reg) ) ) = (UINT32)(data) ) +#define write_addr_UINT16(reg, data) ( ( *( (volatile UINT16 *)(reg) ) ) = (UINT16)(data) ) +#define write_addr_UINT8(reg, data) ( ( *( (volatile UINT8 *)(reg) ) ) = (UINT8 )(data) ) +#define read_addr_UINT32(reg) ( *( (volatile UINT32 *) (reg) ) ) +#define read_addr_UINT16(reg) ( *( (volatile UINT16 *) (reg) ) ) +#define read_addr_UINT8(reg) ( *( (volatile UINT8 *) (reg) ) ) + + +#define NUM_IRQ12_IR 38 +#define NUM_IRQ13_IR 63 +#define NUM_ALL_IR12 NUM_IRQ12_IR+1 +#define NUM_ALL_IR13 NUM_IRQ13_IR+1 + +//IRQ12 +#define IR_ID_WDG 1 +#define IR_ID_GPIO0_COMBO 2 +#define IR_ID_GPIO1_COMBO 3 +#define IR_ID_GPIO2_COMBO 4 +#define IR_ID_GPIO3_COMBO 5 +#define IR_ID_GPIO4_COMBO 6 +#define IR_ID_GPIO5_COMBO 7 +#define IR_ID_GPIO6_COMBO 8 +#define IR_ID_GPIO7_COMBO 9 +#define IR_ID_GPIO8_COMBO 10 +#define IR_ID_GPIO9_COMBO 11 +#define IR_ID_GPIO_00 12 +#define IR_ID_GPIO_01 13 +#define IR_ID_GPIO_02 14 +#define IR_ID_GPIO_03 15 +#define IR_ID_GPIO_04 16 +#define IR_ID_GPIO_05 17 +#define IR_ID_GPIO_06 18 +#define IR_ID_GPIO_07 19 +#define IR_ID_GPIO_08 20 +#define IR_ID_GPIO_09 21 +#define IR_ID_GPIO_10 22 +#define IR_ID_GPIO_11 23 +#define IR_ID_GPIO_12 24 +#define IR_ID_GPIO_13 25 +#define IR_ID_GPIO_14 26 +#define IR_ID_GPIO_15 27 +#define IR_ID_GPIO_16 28 +#define IR_ID_GPIO_17 29 +#define IR_ID_GPIO_18 30 +#define IR_ID_GPIO_19 31 +#define IR_ID_GPIO_V33 32 +#define IR_ID_GPI0 33 +#define IR_ID_GPI1 34 +#define IR_ID_GPI2 35 +#define IR_ID_GPI3 36 +#define IR_ID_GPI4 37 +#define IR_ID_GPI5 38 + +//IRQ13 +#define IR_ID_UART 1 +#define IR_ID_I2C_S 2 +#define IR_ID_I2C_M 3 +#define IR_ID_I2C_M1 4 +#define IR_ID_QSPI_M 5 +#define IR_ID_MBIST 6 +#define IR_ID_GPTM0 7 +#define IR_ID_GPTM1 8 +#define IR_ID_GPTM2 9 +#define IR_ID_GPTM3 10 +#define IR_ID_GPTM4 11 +#define IR_ID_GPTM5 12 +#define IR_ID_GPTM6 13 +#define IR_ID_GPTM7 14 +#define IR_ID_GPTM8 15 +#define IR_ID_GPTM9 16 +#define IR_ID_GPTM10 17 +#define IR_ID_GPTM11 18 +#define IR_ID_CFGSET 19 +#define IR_ID_SSPI_TCH 20 +#define IR_ID_SSPI_AP 21 +#define IR_ID_FLASH_IF 22 +#define IR_ID_DMA_TFR 23 //dma +#define IR_ID_DMA_BLOCK 24 +#define IR_ID_DMA_SRCTRAN 25 +#define IR_ID_DMA_DSTTRAN 26 +#define IR_ID_DMA_ERR 27 +#define IR_ID_MCU_EXT_IRQ00 28 +#define IR_ID_SDP_IRQ 29 +#define IR_ID_ALPM_PHY_SLEEP_IRQ 30 +#define IR_ID_ALPM_PHY_STANDBY_IRQ 31 +#define IR_ID_POWER_SAVE_IND_IRQ 32 +#define IR_ID_POWER_UP_IRQ 33 +#define IR_ID_WAKE_UP_IRQ 34 +#define IR_ID_WAKE_F_CHANGE_IRQ 35 +#define IR_ID_HPD_OUT 36 +#define IR_ID_NORMAL_MODE_INDICATOR 37 +#define IR_ID_VCI_PRON_RDY_AFT_FLASH 38 +#define IR_ID_SSLPINA 39 +#define IR_ID_SSLPIN 40 +#define IR_ID_SDSPONORG 41 +#define IR_ID_VIT_VS_OUT 42 +#define IR_ID_VIT_HS_OUT 43 +#define IR_ID_FB_VS_OUT 60 +#define IR_ID_DT_LOCK_DET_VALID 45 +#define IR_ID_DT_LOCK_FLAG 46 +#define IR_ID_INTEG_PRD 47 +#define IR_ID_INTEG_MRD 48 +#define IR_ID_FLAG_SET_LINE 49 +#define IR_ID_FLAG_RAM0_WR_END 50 +#define IR_ID_FLAG_RAM0_RD_END 51 +#define IR_ID_FLAG_RAM0_RD_REACH_WR 52 +#define IR_ID_FLAG_DSCENC0_BUSY 53 +#define IR_ID_MIPITX_P0_TX_VFP_AREA 54 +#define IR_ID_TE_OUT 55 +#define IR_ID_DBG_IRQ 63 + + +//涓����藉�� +#define IR_PR_THOD 1 + + +#define CLEAR_RX_INTR 0 + +#define BASE_ADDR_PR 0x8000 +#define BASE_ADDR_IE_FS 0x0000 +#define BASE_ADDR_IS_FS 0x1000 +#define BASE_ADDR_IE_SS 0xA000 +#define BASE_ADDR_IS_SS 0xB000 +#define ADDR_TGET_TH 0xF000 +#define ADDR_TARGET_CLAIM 0xF004 + + +/* +* @func:瀹�涔��芥�扮�舵�� +*/ +typedef enum +{ + disable = 0, + enable, +}funcstate; + + +/* +* @func:瀹�涔��芥�扮�舵�� +*/ +typedef enum +{ + reset = 0, + set, +}intstatus; + +typedef enum +{ + bfalse = 0, + btrue =1, +}Enumbool; + +typedef enum +{ + STATE_TX_POWER_IDLE = 0, + STATE_TX_POWER_ON = 1, // 涓��电�舵��锛�浠�棣�娆″��烘�ц�锛� + STATE_TX_SLEEP_IN = 2, // 浼����舵�� + STATE_TX_WAKE_UP = 3, // �ら���舵�� +}EnumPowerState; + + +//core_perip_rw +void wr_core_perip_byte(int addr, char dat); +void wr_core_perip_int (int addr, int dat); +int rd_core_perip (int addr); + +//ir_rw +void wr_irreg (int addr, int dat); +int rd_irreg (int addr); +void wr_bit_irreg(int addr,char bit_loc,char bit_dat); + +void wr_irreg_irq13(int addr, int dat); +int rd_irreg_irq13(int addr); + +//cfgreg rw +void wr_cfgreg(uint32 addr, uint8 dat); +int rd_cfgreg(int addr); + +//irq +void ir_init(); + +//mipi_tx rw +void ini_mptx (void); +void mipitx_send_11(void); +void mipitx_send_29(void); +void mipitx_send_10(void); +void mipitx_send_28(void); +void mipitx_send_packet_type39(void); + +void mipitx_send_packet_type29_0(void); +void mipitx_send_packet_type29_1(void); +void mipitx_send_packet_type29_2(void); +void mipitx_send_packet_type23(void); +void mipitx_send_packet_type0a(void); +//void mipi_tx_send(uint32 txdata); + +void mipitx_send_51(uint8 addr, uint16 dbv); + +//sram test +void sram_1kb_write_read_test (void); +void write_read_sram_word(uint32* address, uint32* data); + +void delay_us(__IO uint32 t); +void delay_ms(__IO uint32 t); +void delay_s(__IO uint32 t); +void delay_1us(void); +void delay_1ms(void); + +void ini(void); +void ini_dprx(void); + +//pmic +void ip_power_init(void); +void i2c0_master_init(void); +void avdd_power_set(uint16 val); +void elvdd_power_set(uint16 val); +void elvss_power_set(uint16 val); +void avdd_on(void); +void avdd_off(void); +void elvdd_elvss_on(void); +void elvdd_elvss_off(void); +void all_off(void); +void Oled_Diming_Process(); +void Lcd_Diming_Process(); +void gpio_init(void); + +void power_on_seq(void); + +void Sys_Power_Handler(void); +void Sys_Power_Executed_State(Enumbool newState); +void Sys_Sleep_Executed_State(Enumbool newState); +void Sys_Matchine_Init(); +EnumPowerState Current_Status_Get(void); + + +#endif diff --git a/src/include/hal_gpio.h b/src/include/hal_gpio.h new file mode 100644 index 0000000..ec06407 --- /dev/null +++ b/src/include/hal_gpio.h @@ -0,0 +1,14 @@ +/******************************************************************************* +* File: hal_gpio.h +* Description: GPIO hal层头文件 +* Version: V1.0 +* Date: 2026-1-26 +* Author: lyp + *******************************************************************************/ + +#ifndef __HAL_GPIO_H__ +#define __HAL_GPIO_H__ + + + +#endif \ No newline at end of file diff --git a/src/include/hal_mipi_tx.h b/src/include/hal_mipi_tx.h new file mode 100644 index 0000000..51d8f9d --- /dev/null +++ b/src/include/hal_mipi_tx.h @@ -0,0 +1,77 @@ +/******************************************************************************* +* File: hal_mipi_tx.h +* Description: mipi发送模块接口 +* Version: V1.0 +* Date: 2026-1-23 +* Author: lyp + *******************************************************************************/ + +#ifndef __HAL_MIPI_TX_H__ +#define __HAL_MIPI_TX_H__ + +#include +#include "la_config.h" + +/** + * @brief 码片bist模式 + * @note PRE_VIDEO_BIST是码片最前端发送的bist图像 + * POST_VIDEO_BIST是码片最后端发送的bist图像 + */ +typedef enum _BIST_MODE +{ + PRE_VIDEO_BIST = 0, + POST_VIDEO_BIST, +}BIST_MODE; + +/** +* @brief MIPI TX开始运行 +* @retval +*/ +void hal_dsi_tx_ctrl_start(); + +/** +* @brief MIPI TX停止运行 +* @retval +*/ +void hal_dsi_tx_ctrl_stop(); + +/** +* @brief MIPI TX发送命令 +* @param data_type: 数据类型 +* @param vc: 虚拟通道编号 +* @param cmd_count: 可变参数个数 +* @param ...: 可变参数 +* @retval true-command发送正常；false-TX当前状态不能发送command +*/ +bool hal_dsi_tx_ctrl_write_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd_count, ...); + +/** +* @brief MIPI TX发送命令 +* @param data_type: 数据类型 +* @param vc: 虚拟通道编号 +* @param size: data个数 +* @param data: data数组 +* @retval true-command发送正常；false-TX当前状态不能发送command +*/ +bool hal_dsi_tx_ctrl_write_array_cmd(uint8_t data_type, uint8_t vc, uint8_t size, const uint8_t *data); + +/** +* @brief 控制码片bist输出 +* @param bist_en: 使能bist +* @param BIST_MODE: bist的模式 +* @retval +*/ +void hal_dsi_tx_ctrl_set_bist(bool bist_en, BIST_MODE bist_mode); + +/** +* @brief MIPI TX接收命令 +* @param data_type: 数据类型 +* @param vc: 虚拟通道编号 +* @param cmd: DCS指令 +* @param size: 读取数据长度 +* @param data: 数据存放地址 +* @retval true-回读正常；false-当前状态不能回读 +*/ +bool hal_dsi_tx_ctrl_read_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd, uint8_t size, uint8_t *data); + +#endif \ No newline at end of file diff --git a/src/include/typedef.h b/src/include/typedef.h new file mode 100644 index 0000000..44e6638 --- /dev/null +++ b/src/include/typedef.h @@ -0,0 +1,61 @@ +//-------------------------------------------------------------------------------- +// File Name : +// Author : +// Created : 2023/7/16 +// Description : +// Notes : +//-------------------------------------------------------------------------------- +// Copyright Richroute +//-------------------------------------------------------------------------------- +#ifndef __Typedef_H__ +#define __Typedef_H__ + +typedef unsigned char uint8; +typedef unsigned char UINT8; +typedef char INT8; +typedef char int8; + +typedef unsigned int uint32; +typedef unsigned long UINT32; +typedef long INT32; +typedef char int8; + +typedef unsigned short UINT16; +typedef unsigned short uint16; +typedef short INT16; +typedef short int16; + +typedef unsigned long long UINT64; +typedef unsigned long long uint64; +typedef long long INT64; +typedef long long int64; + + + +typedef uint8 uint8_t; +typedef uint16 uint16_t; +typedef uint32 uint32_t; + + +#define __I volatile const +#define __O volatile +#define __IO volatile + +#define NULL ((void *)0) + +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) + + +typedef enum { RESET = 0, SET = 1 } FlagStatus; +typedef enum { DISABLE = 0, ENABLE = 1 } EventStatus, ControlStatus; + + + +#endif + + diff --git a/w818_riscv_v5.bat b/w818_riscv_v5.bat new file mode 100644 index 0000000..82b1b24 --- /dev/null +++ b/w818_riscv_v5.bat @@ -0,0 +1,125 @@ +setlocal enableExtensions + +@echo off +color 0B +set gcc_tool_dir=D:\tools\gcc\bin\ + +REM cc: all project case in one folder +for /f "delims=" %%i in ('findstr /V "\/\/" .\src\code\a_set_project_case.cc') do (set proj_folder=%%i) +set "proj_folder=%proj_folder: =%" +set "proj_folder=%proj_folder: =%" + +set code_list= ./src/code/init.S ^ + ./src/code/*.c ^ + ./src/code/project_case/%proj_folder:~7%/*.c ^ + ./src/driver/source/*.c ^ + ./src/driver/ulog/*.c +::start work +echo /***********************************************start***************************************************/ + +set inclue_path=./src/include ^ + -I ./src/driver/include ^ + -I ./src/driver/ulog +set proj_folder_inc_path=./src/code/project_case/%proj_folder:~7% +set link_file=./link/link.ld +set gcc=%gcc_tool_dir%riscv-none-embed-gcc +set objcopy=%gcc_tool_dir%riscv-none-embed-objcopy +set objdump=%gcc_tool_dir%riscv-none-embed-objdump +set compile_path=compile +set firmware_path=fw2flash + +echo /***************************print var***************************/ +REM echo code_list:%code_list% +echo inclue_path1:%inclue_path% +echo inclue_path2:%proj_folder_inc_path% +echo link_file:%link_file% +echo gcc:%gcc% +echo objcopy:%objcopy% +echo objdump:%objdump% +echo compile_path:%compile_path% +echo firmware_path:%firmware_path% + +echo /**************************print folder*************************/ +if exist %compile_path% ( + rd /s /Q %compile_path% + echo delete %compile_path% folder successfully +) else ( + echo no %compile_path% folder +) + +if exist %firmware_path% ( + rd /s /Q %firmware_path% + echo delete %firmware_path% folder successfully +) else ( + echo no %firmware_path% folder +) + +if exist error.txt ( + del error.txt +) + +md %compile_path% +echo newly built %compile_path% folder +md %firmware_path% +echo newly built %firmware_path% folder + +echo /*************** Current Project Case is ***************/ +echo; +echo ^>^>^>^> ^>^>^>^> %proj_folder:~7% ^<^<^<^< ^<^<^<^< +echo; +echo /****************************compile****************************/ +%gcc% %code_list% -I %inclue_path% -I %proj_folder_inc_path% -T %link_file% -nostdlib -o ./compile/test.elf -lc -lgcc -mtune=size -march=rv32i -mabi=ilp32 > error.txt 2>&1 + +@echo off +set "file=error.txt" +if exist "%file%" ( + for %%I in ("%file%") do if %%~zI GTR 0 ( + notepad error.txt + exit + ) else ( + echo; + ) +) else ( + echo; +) + + +%objcopy% -O ihex ./compile/test.elf ./compile/test.hex +%objdump% -D ./compile/test.elf > ./compile/test.objdump +python ./pgm/gen_mif_normal.py ./compile/test.hex 1000000 +::xcopy .\pgm\gen_code_i2c_debug.exe .\fw2flash +::xcopy .\pgm\gen_code_pgm_flash_i2c.exe .\fw2flash +::xcopy .\pgm\gen_i2c_encr_program_flash.exe .\fw2flash +::xcopy .\pgm\table_program.txt .\fw2flash +::xcopy .\pgm\table_data .\fw2flash +::xcopy .\pgm\LA_Gen_BinFile.exe .\fw2flash + +::cd .\fw2flash +::.\gen_code_i2c_debug.exe +::.\gen_code_pgm_flash_i2c.exe +::.\gen_i2c_encr_program_flash.exe +::.\LA_Gen_BinFile.exe + +echo /************************************************end****************************************************/ + + +::del .\gen_code_pgm_flash_i2c.exe +::del .\gen_code_i2c_debug.exe +::del .\gen_i2c_encr_program_flash.exe +::del .\LA_Gen_BinFile.exe + +@echo off +set "file=error.txt" +if exist "%file%" ( + for /f "delims=" %%i in ('type "%file%"') do set "line=%%i" + if defined line ( + pause + ) else ( + del error.txt + ) +) else ( + pause +) + +endlocal +