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Author SHA1 Message Date
liyuanpeng 1a6a76e6cd 新增coding规范，规范SDK编写框架 2026-03-12 19:43:04 +08:00
liyuanpeng cc93e854a8 1、把mipi tx模块进行hal和drv层分层 
2、粗略封装了一部分edp rx
 2026-03-12 17:29:08 +08:00
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90
WL818 SDK框架规则.pdf Normal file
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@ -0,0 +1,90 @@
WeilaiChip WL818 SDK 框架规则 蔚来芯研发部
R&D
产品应用手册 V1.0.0 Date: 2026/3/12
摘要说明
类别 内容
关键词 WL818 SDK
摘要 WL818 SDK 框架规则
修订历史
版本 修订人 时间 审核 备注
V1.0.0 李元鹏 2026/3/12 初次修订
深圳市蔚来芯科技有限公司
蔚来芯研发部 文件版本号：AN 1.0.0
目录
1. 适用范围和参考资料 ..................................................................................... 1
2. WL818 SDK 框架规则 .................................................................................. 2
2.1 WL818 SDK 分层架构 ............................................................................................. 2
2.2 hal 层封装规则 ......................................................................................................... 3
2.3 driver 层封装规则 .....................................................................................................3
3. 文档存放位置 ................................................................................................5
蔚来芯，显示领域的芯片专家 ©Shenzhen WeilaiChip Technology Co., Ltd.
1
蔚来芯研发部 文件版本号：AN 1.0.0
1. 适用范围和参考资料
本文档规格仅应用于蔚来芯研发部，作为 WL818 SDK 的编写框架指导。
蔚来芯，显示领域的芯片专家 ©Shenzhen WeilaiChip Technology Co., Ltd.
1
蔚来芯研发部 文件版本号：AN 1.0.0
2. WL818 SDK 框架规则
2.1 WL818 SDK 分层架构
架构分为 hal 层和 driver 层，hal 层为直接暴露给客户的接口，格式参考如下：
而其中的寄存器操作，统一封装到 driver 层，仅为内部使用，抽象寄存器操作增加代
码可读性，格式参考如下：
蔚来芯，显示领域的芯片专家 ©Shenzhen WeilaiChip Technology Co., Ltd.
2
蔚来芯研发部 文件版本号：AN 1.0.0
2.2 hal 层封装规则
由于 hal 层接口直接被用户使用，所以需要对入口参数进行检测，参考如下
2.3 driver 层封装规则
driver 层封装寄存器操作，让代码可读性更高，对于寄存器地址的抽象，如果是连续
地址，可抽象成结构体，后续操作通过结构体指针进行操作，参考如下：
蔚来芯，显示领域的芯片专家 ©Shenzhen WeilaiChip Technology Co., Ltd.
3
蔚来芯研发部 文件版本号：AN 1.0.0
对于一些高频操作，也可以宏定义的方式增加代码可读性，参考如下：
抽象封装增加代码可读性的同时，也需要注意运行效率，比如单一寄存器的操作需要
内联，参考如下：
蔚来芯，显示领域的芯片专家 ©Shenzhen WeilaiChip Technology Co., Ltd.
4
蔚来芯研发部 文件版本号：AN 1.0.0
3. 文档存放位置
已放置蔚来芯研发部“\\weilaichip\研发部\03_研发总结和积累\00_2025 年度研发总结
\李元鹏\【研发总结-李元鹏】WL818 SDK 框架规则”。
蔚来芯，显示领域的芯片专家 ©Shenzhen WeilaiChip Technology Co., Ltd.
5

31
coding_rule.txt
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@ -1,10 +1,21 @@
1、SDK变量命名延续原SDK的下划线命名法，不使用驼峰命名法
2、编码格式使用UTF-8
3、if判断相等时变量放在右值
4、对外接口必须检测入口参数
5、单一语句需内联
6、硬件操作相关变量定义需防优化
一、文本编码格式
编码格式使用UTF-8
二、编码规范
1、SDK变量命名延续原SDK的下划线命名法，不使用驼峰命名法
2、宏定义统一大写
3、宏定义时宏值需要加括号，防止编译器预处理替换之后不被视为一个整体处理
3、hal层函数命名统一hal开头
4、driver层函数命名统一drv开头
5、if判断相等时变量放在右值，防止编写失误导致赋值
6、对外接口必须检测入口参数，防止用户输入空指针等导致系统崩溃。
7、驱动层单一语句需强制内联，增加运行效率
8、寄存器需要防编译器优化，防止实际运行CPU没有对寄存器所在内存进行操作，建议根据寄存器的读写权限使用宏__IO
三、框架规则
编写框架指导详见《WL818 SDK框架规则》
四、文件系统
WL818_SDK
├─compile
├─fw2flash
@ -16,8 +27,8 @@ WL818_SDK
├─code //用户app
│ └─project_case
│ └─RM692H5_120HZ_DSC3_1
├─driver //驱动层，对内封装寄存器地址
│ ├─include
│ ├─source
├─driver //该文件夹负责放驱动层不对外暴露的文件，如，drv_mipi_tx和hal_mipi_tx.h
│ ├─include //放仅内部可见的驱动头文件，比如drv_mipi_tx.h
│ ├─source //放仅内部可见的驱动源文件，比如drv_mipi_tx.c和hal_mipi_tx.c
│ └─ulog
└─include //对外头文件hal和common定义
└─include //对外头文件hal和common定义，如hal_mipi_tx.h

236
src/code/core_main.c
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@ -1,33 +1,196 @@
#include "la_config.h"
#include "hal_edp_rx.h"
void blackligth_pwm_ctrl(void);
RX_CB_Handle rx_cb_handle = {0};
void main(void)
/* SDP更新回调，用于获取second data packet */
void ap_set_backlight(SDP_Info sdp_info)
{
//------------------------------w818 && ddic initial...
ini();
ini_dprx();//DPCD
gpio_init();
Sys_Matchine_Init();
//------------------------------interrupt initial....
ir_init();
aux_irq_set_irq13(); //选择aux中断回调函数为aux_irq_handler，而不是isr_aux()
//aux_read_sink_set(); //设置aux读时，可保存sink回复的数据
//---------------------------------ulog initial....
UartStdOutInit(); //GPIO_ID22,GPIO_ID23串口初始化,波特率: 19200
log_init(uart_output, LOG_LEVEL_INFO); // 初始化日志系统，使用UART输出，默认日志级别为INFO
sys_clk_get();
//sys_boot_getstatus();
log_set_level(LOG_LEVEL_DEBUG);
LOG_INFO("MCU Start Run On %s %s", __DATE__, __TIME__);
while(1)
{
Sys_Power_Handler();
Oled_Diming_Process();
};
}
/* 休眠回调，当基板通过AUX往DPCD寄存器600H写02时触发 */
void ap_set_display_off(void)
{
}
/* 唤醒回调，当基板reset脚拉高触发 */
void ap_set_display_on(void)
{
}
RX_CB_Handle rx_cb_tabel =
{
{ap_set_backlight ,false},
{ap_set_display_off ,false},
{ap_set_display_on ,false},
};
const DPCD_Packet dpcd_packet_table[] =
{
//dprx_DPCD_16PM
{0x0000 ,0x14},
{0x0001 ,0x0F},
{0x0002 ,0xC4},
{0x0003 ,0x00},
{0x0004 ,0x00},
{0x0005 ,0x00},
{0x0006 ,0x01},
{0x0007 ,0xC0},
{0x0008 ,0x02},
{0x0009 ,0x01},
{0x000A ,0x00},
{0x000B ,0x00},
{0x000C ,0x00},
{0x000D ,0x01},
{0x000E ,0x00},
{0x000F ,0x00},
{0x002E ,0x00}, //ALPM OFF
// {0x002E ,0x01}, //ALPM ON
{0x0400, 0x00},
{0x0401, 0x10},
{0x0402, 0xFA},
{0x0500, 0x00},
{0x0501, 0x00},
{0x0502, 0x00},
{0x0403, 0x00},
{0x0404, 0x00},
{0x0405, 0x00},
{0x0406, 0x00},
{0x0407, 0x00},
{0x0408, 0x00},
{0x0503, 0x00},
{0x0504, 0x00},
{0x0505, 0x00},
{0x0506, 0x00},
{0x0507, 0x00},
{0x0508, 0x00},
{0x0090, 0x00},
{0x00B0, 0x00},
{0xE000D, 0x00}, //
{0x0060 , 0x00},
{0x0061 , 0x00},
{0x0062 , 0x00},
{0x0063 , 0x00},
{0x0064 , 0x00},
{0x0065 , 0x00},
{0x0066 , 0x00},
{0x0067 , 0x00},
{0x0068 , 0x00},
{0x0069 , 0x00},
{0x006A , 0x00},
{0x006B , 0x00},
{0x006C , 0x00},
{0x006D , 0x00},
{0x006E , 0x00},
{0x006F , 0x00},
{0x0470, 0x31},
{0x0471, 0x03},
{0x0472, 0x01},
{0x0328, 0x00},
{0x0116, 0x01},
{0x3030, 0x00},
{0x0430, 0xA0},
{0x0431, 0xEE},
{0x0432, 0x61},
{0x0433, 0x42},
{0x0450, 0x03},
{0x0451, 0x81},
{0x0452, 0x00},
{0x0453, 0x00},
{0x0454, 0x00},
{0x0455, 0x00},
{0x0456, 0x00},
{0x0457, 0x00},
{0x0458, 0x00},
{0x0459, 0x00},
{0x045A, 0x00},
{0x045B, 0x00},
{0x045C, 0x66},
{0x045D, 0x66},
{0x045E, 0x06},
{0x045F, 0x00},
//{0x04F0, 0x00}, //原彩数据，不在此处回
//{0x04F1, 0x00},
//{0x04F2, 0x00},
//{0x04F3, 0x00},
//{0x04F4, 0x00},
//{0x04F5, 0x00},
//{0x04F6, 0x00},
//{0x04F7, 0x00},
//{0x04F8, 0x04},
//{0x04F9, 0x03},
//{0x04FA, 0x00},
//{0x04FB, 0x06},
//{0x04FC, 0x00},
//{0x04FD, 0x46},
//{0x04FE, 0x58},
//{0x04FF, 0x54},
{0x010A, 0x00},
{0x0101 ,0x82},
//{0x0102 ,0x21},
//{0x0103 ,0x00},
//{0x0104 ,0x00},
//{0x0105 ,0x00},
{0x0210, 0x00},
{0x0211, 0x80},
{0x0212, 0x00},
{0x0213, 0x80},
{0x0214, 0x00},
{0x0215, 0x80},
{0x0216, 0x00},
{0x0217, 0x00},
{0x0347, 0x00},
{0x0348, 0x00},
{0x0349, 0x00},
{0x034A, 0x00},
{0x034B, 0x00},
{0x034C, 0x00},
{0x034D, 0x00},
{0x034E, 0x00},
{0x0200, 0x77},
{0x0201, 0x77},
{0x0202 ,0x77},
{0x0203 ,0x07},
{0x0204 ,0x81},
//{0x0206 ,0x00},
//{0x0207 ,0x00},
//{0x0470 ,0x2C},
//{0x0471 ,0x03},
//{0x0472 ,0x01},
{0x0600 ,0x01},
//{0x3000 ,0x00},
{0x032F ,0x00},
{0x0330 ,0x00},
};
void blackligth_pwm_ctrl(void)
{
//控制pwm产生
@ -57,3 +220,30 @@ void blackligth_pwm_ctrl(void)
//wr_cfgreg(0xe002, 0xde);
//wr_cfgreg(0xc100, 0x81);
}
void main(void)
{
//------------------------------w818 && ddic initial...
ini();
hal_edp_rx_dpcd_init(dpcd_packet_table, sizeof(dpcd_packet_table));
hal_edp_rx_cb_init(&rx_cb_tabel);
gpio_init();
Sys_Matchine_Init();
//------------------------------interrupt initial....
ir_init();
aux_irq_set_irq13(); //选择aux中断回调函数为aux_irq_handler，而不是isr_aux()
//aux_read_sink_set(); //设置aux读时，可保存sink回复的数据
//---------------------------------ulog initial....
UartStdOutInit(); //GPIO_ID22,GPIO_ID23串口初始化,波特率: 19200
log_init(uart_output, LOG_LEVEL_INFO); // 初始化日志系统，使用UART输出，默认日志级别为INFO
sys_clk_get();
//sys_boot_getstatus();
log_set_level(LOG_LEVEL_DEBUG);
LOG_INFO("MCU Start Run On %s %s", __DATE__, __TIME__);
while(1)
{
Sys_Power_Handler();
Oled_Diming_Process();
};
}

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src/code/project_case/RM692H5_120HZ_DSC3_1/dprx.c
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@ -2,169 +2,169 @@
#include "define.h"
void dprx_load_edp_bit_rate_cco(void);
void ini_dprx()
{
//dprx_DPCD_16PM
write_addr_UINT8(BASE_ADDR_DPCD + 0x0000 ,0x14);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0001 ,0x0F);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0002 ,0xC4);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0003 ,0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0004 ,0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0005 ,0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0006 ,0x01);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0007 ,0xC0);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0008 ,0x02);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0009 ,0x01);
write_addr_UINT8(BASE_ADDR_DPCD + 0x000A ,0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x000B ,0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x000C ,0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x000D ,0x01);
write_addr_UINT8(BASE_ADDR_DPCD + 0x000E ,0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x000F ,0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x002E ,0x00); //ALPM OFF
// write_addr_UINT8(BASE_ADDR_DPCD + 0x002E ,0x01); //ALPM ON
// void ini_dprx()
// {
// //dprx_DPCD_16PM
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0000 ,0x14);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0001 ,0x0F);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0002 ,0xC4);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0003 ,0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0004 ,0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0005 ,0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0006 ,0x01);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0007 ,0xC0);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0008 ,0x02);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0009 ,0x01);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x000A ,0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x000B ,0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x000C ,0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x000D ,0x01);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x000E ,0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x000F ,0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x002E ,0x00); //ALPM OFF
// // write_addr_UINT8(BASE_ADDR_DPCD + 0x002E ,0x01); //ALPM ON
write_addr_UINT8(BASE_ADDR_DPCD + 0x0400, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0401, 0x10);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0402, 0xFA);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0400, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0401, 0x10);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0402, 0xFA);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0500, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0501, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0502, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0500, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0501, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0502, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0403, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0404, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0405, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0406, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0407, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0408, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0403, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0404, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0405, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0406, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0407, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0408, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0503, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0504, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0505, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0506, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0507, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0508, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0503, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0504, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0505, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0506, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0507, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0508, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0090, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x00B0, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0090, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x00B0, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0xE000D, 0x00); //
// write_addr_UINT8(BASE_ADDR_DPCD + 0xE000D, 0x00); //
write_addr_UINT8(BASE_ADDR_DPCD + 0x0060 , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0061 , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0062 , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0063 , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0064 , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0065 , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0066 , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0067 , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0068 , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0069 , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x006A , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x006B , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x006C , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x006D , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x006E , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x006F , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0060 , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0061 , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0062 , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0063 , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0064 , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0065 , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0066 , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0067 , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0068 , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0069 , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x006A , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x006B , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x006C , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x006D , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x006E , 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x006F , 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0470, 0x31);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0471, 0x03);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0472, 0x01);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0470, 0x31);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0471, 0x03);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0472, 0x01);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0328, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0328, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0116, 0x01);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0116, 0x01);
write_addr_UINT8(BASE_ADDR_DPCD + 0x3030, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x3030, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0430, 0xA0);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0431, 0xEE);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0432, 0x61);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0433, 0x42);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0430, 0xA0);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0431, 0xEE);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0432, 0x61);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0433, 0x42);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0450, 0x03);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0451, 0x81);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0452, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0453, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0454, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0455, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0456, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0457, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0458, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0459, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x045A, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x045B, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x045C, 0x66);
write_addr_UINT8(BASE_ADDR_DPCD + 0x045D, 0x66);
write_addr_UINT8(BASE_ADDR_DPCD + 0x045E, 0x06);
write_addr_UINT8(BASE_ADDR_DPCD + 0x045F, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0450, 0x03);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0451, 0x81);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0452, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0453, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0454, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0455, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0456, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0457, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0458, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0459, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x045A, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x045B, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x045C, 0x66);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x045D, 0x66);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x045E, 0x06);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x045F, 0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F0, 0x00); //Ô­²ÊÊý¾Ý£¬²»ÔÚ´Ë´¦»Ø
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F1, 0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F2, 0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F3, 0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F4, 0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F5, 0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F6, 0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F7, 0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F8, 0x04);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04F9, 0x03);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FA, 0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FB, 0x06);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FC, 0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FD, 0x46);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FE, 0x58);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x04FF, 0x54);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04F0, 0x00); //Ô­²ÊÊý¾Ý£¬²»ÔÚ´Ë´¦»Ø
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04F1, 0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04F2, 0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04F3, 0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04F4, 0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04F5, 0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04F6, 0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04F7, 0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04F8, 0x04);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04F9, 0x03);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04FA, 0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04FB, 0x06);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04FC, 0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04FD, 0x46);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04FE, 0x58);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x04FF, 0x54);
write_addr_UINT8(BASE_ADDR_DPCD + 0x010A, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0101 ,0x82);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x0102 ,0x21);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x0103 ,0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x0104 ,0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x0105 ,0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x010A, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0101 ,0x82);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x0102 ,0x21);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x0103 ,0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x0104 ,0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x0105 ,0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0210, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0211, 0x80);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0212, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0213, 0x80);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0214, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0215, 0x80);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0216, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0217, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0210, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0211, 0x80);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0212, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0213, 0x80);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0214, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0215, 0x80);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0216, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0217, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0347, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0348, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0349, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x034A, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x034B, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x034C, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x034D, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x034E, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0347, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0348, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0349, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x034A, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x034B, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x034C, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x034D, 0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x034E, 0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0200, 0x77);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0201, 0x77);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0202 ,0x77);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0203 ,0x07);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0204 ,0x81);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0200, 0x77);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0201, 0x77);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0202 ,0x77);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0203 ,0x07);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0204 ,0x81);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x0206 ,0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x0207 ,0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x0206 ,0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x0207 ,0x00);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x0470 ,0x2C);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x0471 ,0x03);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x0472 ,0x01);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x0470 ,0x2C);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x0471 ,0x03);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x0472 ,0x01);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0600 ,0x01);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0600 ,0x01);
//write_addr_UINT8(BASE_ADDR_DPCD + 0x3000 ,0x00);
// //write_addr_UINT8(BASE_ADDR_DPCD + 0x3000 ,0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x032F ,0x00);
write_addr_UINT8(BASE_ADDR_DPCD + 0x0330 ,0x00);
dprx_load_edp_bit_rate_cco();
}
// write_addr_UINT8(BASE_ADDR_DPCD + 0x032F ,0x00);
// write_addr_UINT8(BASE_ADDR_DPCD + 0x0330 ,0x00);
// dprx_load_edp_bit_rate_cco();
// }
#define EDP_INPUT_3_51Gbps //EDP_INPUT_3_51Gbps

6
src/code/project_case/RM692H5_120HZ_DSC3_1/power_seq.c
View File

@ -1741,6 +1741,9 @@ void power_on_seq(void)
delay_ms(123);
SWIRE_EN();
delay_ms(46);
unsigned char data = 0;
hal_dsi_tx_ctrl_read_cmd(0x06,0,0x0A,1,&data);
LOG_DEBUG("r%d\n",data);
hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x29);
delay_ms(46);
hal_dsi_tx_ctrl_start();
@ -1781,6 +1784,9 @@ void wake_up_seq(void)
delay_ms(123);
SWIRE_EN();
delay_ms(46);
// unsigned char data = 0;
// hal_dsi_tx_ctrl_read_cmd(0x06,0,0x0A,1,&data);
// LOG_DEBUG("r%d\n",data);
hal_dsi_tx_ctrl_write_cmd(0x05, 0, 1, 0x29);
delay_ms(46);
hal_dsi_tx_ctrl_start();

151
src/driver/include/drv_mipi_tx.h Normal file
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@ -0,0 +1,151 @@
/*******************************************************************************
* File: drv_mipi_tx.h
* Description: mipi tx驱动层
* Version: V1.0
* Date: 2026-1-23
* Author: lyp
*******************************************************************************/
#ifndef __DRV_MIPI_TX_H__
#define __DRV_MIPI_TX_H__
#include "typedef.h"
#include "define.h"
#include <stdarg.h>
#include "la_config.h"
#ifndef MIPI_TX_PORT0_BASE
#define MIPI_TX_PORT0_BASE (0x80010000)
#endif
#define MIPI_TX_PORT0 ((MIPI_TX_PORT0_REG *)MIPI_TX_PORT0_BASE)
typedef struct _MIPI_TX_PORT0_REG
{
__O uint32_t write_data ;
__IO uint8_t tx_enable ;
__IO uint8_t tx_control_L ;
__IO uint8_t tx_control_H ;
__I uint8_t tx_state ;
__IO uint32_t rd_lp_rx_data ;
__IO uint32_t rd_lp_rx_ecc ;
__O uint32_t fifo_set ;
__I uint32_t ISR ;
__IO uint32_t IMR ;
__O uint32_t ICR ;
}MIPI_TX_PORT0_REG;
/*!
* @brief MIPI发送模式
* @note
*/
typedef enum _TX_MODE
{
LP_MODE = 0,
HS_MODE,
}TX_MODE;
/**
* @brief 向mipi模块发出写数据配置申请，后续才能向mipi模块配置需要写的数据
* @param none
* @retval none
*/
static inline void drv_mipi_tx_write_configure_enable()
{
MIPI_TX_PORT0->tx_enable = 0x01;
}
/**
* @brief 关闭mipi模块写数据配置申请
* @param none
* @retval none
*/
static inline void drv_mipi_tx_write_configure_disable()
{
MIPI_TX_PORT0->tx_enable = 0x00;
}
/**
* @brief 向mipi模块发出读数据配置申请，后续才能向mipi模块配置需要读的数据
* @param none
* @retval none
*/
static inline void drv_mipi_tx_read_configure_enable()
{
MIPI_TX_PORT0->tx_enable = 0x41;
}
/**
* @brief 关闭mipi模块读数据配置申请
* @param none
* @retval none
*/
static inline void drv_mipi_tx_read_configure_disable()
{
MIPI_TX_PORT0->tx_enable = 0x40;
}
/**
* @brief 控制mipi模块按照设定的配置开始工作
* @param none
* @retval none
*/
static inline bool drv_mipi_tx_work()
{
MIPI_TX_PORT0->tx_control_L = 0x03;
}
/**
* @brief 获取mipi tx busy状态
* @param none
* @retval true: MIPI TX模块处理中, false:MIPI TX模块处理完成
*/
static inline bool drv_mipi_tx_get_busy()
{
return TAU_BIT_CHECK_ZERO(MIPI_TX_PORT0->tx_state, 0);
}
/**
* @brief 获取mipi tx read的值
* @param none
* @retval mipi读取的值
*/
static inline uint32_t drv_mipi_tx_get_read_result()
{
return MIPI_TX_PORT0->rd_lp_rx_data;
}
/**
* @brief 控制mipi模块写数据
* @param data: 数据buffer
* @param cmd_count: 数据长度
* @param tx_mode: 发送模式 1：HS 0:LP
* @retval none
*/
void drv_mipi_tx_write_data(const uint8_t *cmd, uint8_t cmd_count, TX_MODE tx_mode);
/**
* @brief 控制mipi模块清空lp read
* @param none
* @retval none
*/
void drv_mipi_tx_lprd_clear();
/**
* @brief 控制mipi模块发送set max size命令
* @param data: 数据buffer
* @param cmd_count: 数据长度
* @param tx_mode: 发送模式 1：HS 0:LP
* @retval none
*/
void drv_mipi_tx_set_max_size(uint8_t max_size);
/**
* @brief 控制mipi模块发送读命令
* @param cmd: 需要回读的寄存器地址
* @retval none
*/
void drv_mipi_tx_read_data(uint8_t cmd);
#endif

125
src/driver/source/drv_mipi_tx.c Normal file
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@ -0,0 +1,125 @@
#include "drv_mipi_tx.h"
/** \brief 设置mipi模块发送模式
* tx_mode参考枚举TX_MODE，1为高速发送，0为低速发送
*/
#define SET_MIPI_MODE(tx_mode) (write_addr_UINT8(mipi_tx_lp_hs_mode, tx_mode))
/** \brief 设置mipi模块发送的数据
* data为具体数据
*/
#define SET_MIPI_DATA(data) (write_addr_UINT32(mipi_tx_send_data, data))
/**
* @brief 控制mipi模块写数据
* @param cmd: 数据buffer
* @param cmd_count: 数据长度
* @param tx_mode: 发送模式 1：HS 0:LP
* @retval none
*/
void drv_mipi_tx_write_data(const uint8_t *cmd, uint8_t cmd_count, TX_MODE tx_mode)
{
if(cmd_count > 1)
{
SET_MIPI_MODE(tx_mode);
/*配置mipi模块要写的数据*/
drv_mipi_tx_write_configure_enable();
SET_MIPI_DATA((cmd[0] << 24) + (cmd_count << 8) + 0x39 + (0x3 << 6));
for (uint8_t i = 0; i < ((cmd_count - 1) >> 2); i++)
{
SET_MIPI_DATA((cmd[4 + (i << 2)] << 24) + (cmd[3 + (i << 2)] << 16) + (cmd[2 + (i << 2)] << 8) + (cmd[1 + (i << 2)]));
}
switch ((cmd_count - 1) % 4)
{
case 1:
SET_MIPI_DATA(cmd[cmd_count - 1]);
break;
case 2:
SET_MIPI_DATA((cmd[cmd_count - 1] << 8) + cmd[cmd_count - 2]);
break;
case 3:
SET_MIPI_DATA((cmd[cmd_count - 1] << 16) + (cmd[cmd_count - 2] << 8) + cmd[cmd_count - 3]);
break;
default:
break;
}
drv_mipi_tx_write_configure_disable();
/*控制mipi模块开始工作，并等待mipi模块工作结束*/
drv_mipi_tx_work();
while (true == drv_mipi_tx_get_busy());
}
else
{
SET_MIPI_MODE(tx_mode);
/*配置mipi模块要写的数据*/
drv_mipi_tx_write_configure_enable();
SET_MIPI_DATA(0x05 + (cmd[0] << 8));
drv_mipi_tx_write_configure_disable();
/*控制mipi模块开始工作，并等待mipi模块工作结束*/
drv_mipi_tx_work();
while (true == drv_mipi_tx_get_busy());
}
}
/**
* @brief 控制mipi模块清空lp read
* @param none
* @retval none
*/
void drv_mipi_tx_lprd_clear()
{
MIPI_TX_PORT0->tx_enable = 0;
MIPI_TX_PORT0->tx_enable = 8;
MIPI_TX_PORT0->tx_enable = 0;
}
/**
* @brief 控制mipi模块发送set max size命令
* @param data: 数据buffer
* @param cmd_count: 数据长度
* @param tx_mode: 发送模式 1：HS 0:LP
* @retval none
*/
void drv_mipi_tx_set_max_size(uint8_t max_size)
{
SET_MIPI_MODE(LP_MODE);
/*配置mipi模块要写的数据*/
drv_mipi_tx_write_configure_enable();
SET_MIPI_DATA(0x00003C00 + max_size);
drv_mipi_tx_write_configure_disable();
/*控制mipi模块开始工作，并等待mipi模块工作结束*/
drv_mipi_tx_work();
while (true == drv_mipi_tx_get_busy());
}
/**
* @brief 控制mipi模块发送读命令
* @param cmd: 需要回读的寄存器地址
* @retval none
*/
void drv_mipi_tx_read_data(uint8_t cmd)
{
drv_mipi_tx_read_configure_disable();
SET_MIPI_MODE(LP_MODE);
/*配置mipi模块要写的数据*/
drv_mipi_tx_read_configure_enable();
SET_MIPI_DATA(0x00000086 + (cmd << 8)); // mipi tx发送的数据
drv_mipi_tx_read_configure_disable();
/*控制mipi模块开始工作，并等待mipi模块工作结束*/
drv_mipi_tx_work();
while (true == drv_mipi_tx_get_busy());
}

205
src/driver/source/hal_edp_rx.c Normal file
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@ -0,0 +1,205 @@
/*******************************************************************************
* File: hal_edp_rx.h
* Description: edp rx模块接口
* Version: V1.0
* Date: 2026-2-27
* Author: lyp
*******************************************************************************/
#include "hal_edp_rx.h"
#include "typedef.h"
#include "define.h"
#define EDP_INPUT_3_51Gbps //EDP_INPUT_3_51Gbps
#define EDP_TRAIN_BY_TPS1 //如果TPS1 大于15us,启用此宏，一般手机应用启动，ipad应用不启用
static void dprx_load_edp_bit_rate_cco(void)
{
uint8 freg =0;
uint8 edp_cdr_prediv =0;
uint8 xtal_en = 0; //外部晶振是否起振
uint8 edp_cdr_ext_xtal_en = 0; //cdr恢复是否用外部晶振
uint8 edp_clkrdy = 0;
uint8 val = 0;
//access flash: write L1 key
uint32 tmp32 = 0x2f83631a;
uint32 addr32 = 0x80081058;
write_addr_UINT32(addr32, tmp32);
#if defined EDP_INPUT_1_62Gbps
freg = 0;
edp_cdr_prediv =0;
edp_clkrdy =6;
#endif
#if defined EDP_INPUT_1_89Gbps || defined IPAD_MINI6
freg = 1;
edp_cdr_prediv = 0;
edp_clkrdy = 7;
#endif
#if defined EDP_INPUT_2_16Gbps
freg = 2;
edp_cdr_prediv = 0;
edp_clkrdy = 7;
#endif
#if defined EDP_INPUT_2_43Gbps
freg = 3;
edp_cdr_prediv = 0;
edp_clkrdy = 7;
#endif
#if defined EDP_INPUT_2_7Gbps
freg = 4;
edp_cdr_prediv = 0;
edp_clkrdy = 8;
#endif
#if defined EDP_INPUT_2_97Gbps
freg = 5;
edp_cdr_prediv = 0;
edp_clkrdy = 8;
#endif
#if defined EDP_INPUT_3_24Gbps
freg = 6;
edp_cdr_prediv = 0;
edp_clkrdy = 8;
#endif
#if defined EDP_INPUT_3_51Gbps || defined IP_16PM
freg = 7;
edp_cdr_prediv = 0;
edp_clkrdy = 9;
#endif
#if defined EDP_INPUT_3_78Gbps
freg = 8;
edp_cdr_prediv = 0;
edp_clkrdy = 9;
#endif
#if defined EDP_INPUT_4_05Gbps
freg = 9;
edp_cdr_prediv = 1;
edp_clkrdy = 7;
#endif
#if defined EDP_INPUT_4_32Gbps
freg = 10;
edp_cdr_prediv = 1;
edp_clkrdy = 7;
#endif
#if defined EDP_INPUT_4_59Gbps
freg = 11;
edp_cdr_prediv = 1;
edp_clkrdy = 7;
#endif
#if defined EDP_INPUT_4_86Gbps
freg = 12;
edp_cdr_prediv = 1;
edp_clkrdy = 7;
#endif
#if defined EDP_INPUT_5_13Gbps
freg = 13;
edp_cdr_prediv = 1;
edp_clkrdy = =8;
#endif
#if defined EDP_INPUT_5_4Gbps
freg = 14;
edp_cdr_prediv = 1;
edp_clkrdy = = 8;
#endif
#if defined EDP_INPUT_5_67Gbps
freg = 15;
edp_cdr_prediv = 1;
edp_clkrdy = = 8;
#endif
#if defined EDP_INPUT_5_94Gbps
freg = 16;
edp_cdr_prediv = 1;
edp_clkrdy = = 8;
#endif
#if defined EDP_INPUT_6_21Gbps
freg = 17;
edp_cdr_prediv = 1;
edp_clkrdy = = 8;
#endif
#if defined EDP_INPUT_6_48Gbps
freg = 18;
edp_cdr_prediv = 1;
edp_clkrdy = = 8;
#endif
#if defined EDP_INPUT_6_75Gbps
freg = 19;
edp_cdr_prediv = 1;
edp_clkrdy = = 9;
#endif
tmp32 = 0x8040c004 + freg * 7 * 4;
addr32 = 0x80000114;
for (uint8 i = 0; i < 8; i++)
{
write_addr_UINT32(addr32 + 4*i, read_addr_UINT32(tmp32 + 4 * i));
}
#if defined EDP_TRAIN_BY_TPS1 //有15us以上的TPS1，则自恢复CRD，不需要靠外部EDP晶振
xtal_en =0;
edp_cdr_ext_xtal_en =0;
#else //没有15us以上的TPS1，启用外部晶振做时钟恢复
xtal_en = 1;
edp_cdr_ext_xtal_en = 1;
#endif
val = read_addr_UINT8(BASE_ADDR_CFG + 0xba42); //#page 1 xtal_en
val &= ~(3<<4);
val = val | (xtal_en <<5) | (edp_cdr_prediv << 4);
wr_cfgreg(0xba42, val);
val = read_addr_UINT8(BASE_ADDR_CFG + 0xba44); //#page 1 xtal_sclk_sel/edp_cco_ext_xtal_en
val &= ~(1 << 1);
val = val | (edp_cdr_ext_xtal_en << 1) ;
wr_cfgreg(0xba44, val); //默认走无源晶振
val = (edp_clkrdy <<4) | 0x06;
wr_cfgreg(0xba47, val); //默认走无源晶振
}
/**
* @brief 注册rx相关回调
* @param RX_CB_Handle: rx回调参数结构体
* @retval true-注册成功；false-注册失败
*/
bool hal_edp_rx_cb_init(RX_CB_Handle *rx_cb_handle)
{
}
bool hal_edp_rx_dpcd_init(const DPCD_Packet *table_address, uint32_t table_size)
{
/*验证参数有效性*/
if((NULL == table_address) || (0 == table_size))
{
return false;
}
for(uint32_t i = 0; i < (table_size / sizeof(DPCD_Packet)); i++)
{
write_addr_UINT8(BASE_ADDR_DPCD + table_address[i].dpcd_address, table_address[i].dpcd_value);
}
dprx_load_edp_bit_rate_cco();
return true;
}

106
src/driver/source/hal_mipi_tx.c
View File

@ -6,19 +6,10 @@
* Author: lyp
*******************************************************************************/
#include "hal_mipi_tx.h"
#include "typedef.h"
#include "define.h"
/*!
* @brief MIPI发送模式
* @note
*/
typedef enum _TX_MODE
{
LP_MODE = 0,
HS_MODE,
}TX_MODE;
#include "drv_mipi_tx.h"
#include "hal_mipi_tx.h"
static TX_MODE mipi_state = LP_MODE;
@ -70,46 +61,7 @@ bool hal_dsi_tx_ctrl_write_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd_count,
}
va_end(args);
/*控制mipi ip发送数据*/
if(cmd_count > 1)
{
write_addr_UINT8(mipi_tx_lp_hs_mode, mipi_state);
write_addr_UINT8(mipi_tx_send_requset, 0x01);
write_addr_UINT32(mipi_tx_send_data, (cmd[0] << 24) + (cmd_count << 8) + data_type + (0x3 << 6));
for (uint8_t i = 0; i < ((cmd_count - 1) >> 2); i++)
{
write_addr_UINT32(mipi_tx_send_data, (cmd[4 + (i << 2)] << 24) + (cmd[3 + (i << 2)] << 16) + (cmd[2 + (i << 2)] << 8) + cmd[1 + (i << 2)]);
}
switch ((cmd_count - 1) % 4)
{
case 1:
write_addr_UINT32(mipi_tx_send_data, cmd[cmd_count - 1]);
break;
case 2:
write_addr_UINT32(mipi_tx_send_data, (cmd[cmd_count - 1] << 8) + cmd[cmd_count - 2]);
break;
case 3:
write_addr_UINT32(mipi_tx_send_data, (cmd[cmd_count - 1] << 16) + (cmd[cmd_count - 2] << 8) + cmd[cmd_count - 3]);
break;
default:
break;
}
write_addr_UINT8(mipi_tx_send_requset,0x00);
write_addr_UINT8(mipi_tx_trigger_pulse,0x03);
while (0 == (read_addr_UINT8(mipi_tx_send_done) & mipi_tx_send_done_mask));
}
else
{
write_addr_UINT8(mipi_tx_lp_hs_mode, mipi_state); // mipi tx lp send cmd enable
write_addr_UINT8(mipi_tx_send_requset, 0x01); // 向mipi tx发出申请，拉高
write_addr_UINT32(mipi_tx_send_data, (0x05 + (cmd[0] << 8))); // mipi tx发送的数据
write_addr_UINT8(mipi_tx_send_requset, 0x00); // 完成数据发送后，拉低wrqst
write_addr_UINT8(mipi_tx_trigger_pulse, 0x03); // 随后发triiger pulse，触发mipi tx工作
while (0 == (read_addr_UINT8(mipi_tx_send_done) & mipi_tx_send_done_mask));
}
drv_mipi_tx_write_data(cmd, cmd_count, mipi_state);
return true;
}
@ -130,46 +82,7 @@ bool hal_dsi_tx_ctrl_write_array_cmd(uint8_t data_type, uint8_t vc, uint8_t size
return false;
}
/*控制mipi ip发送数据*/
if(size > 1)
{
write_addr_UINT8(mipi_tx_lp_hs_mode, mipi_state);
write_addr_UINT8(mipi_tx_send_requset, 0x01);
write_addr_UINT32(mipi_tx_send_data, (data[0] << 24) + (size << 8) + data_type + (0x3 << 6));
for (uint8_t i = 0; i < ((size - 1) >> 2); i++)
{
write_addr_UINT32(mipi_tx_send_data, (data[4 + (i << 2)] << 24) + (data[3 + (i << 2)] << 16) + (data[2 + (i << 2)] << 8) + data[1 + (i << 2)]);
}
switch ((size - 1) % 4)
{
case 1:
write_addr_UINT32(mipi_tx_send_data, data[size - 1]);
break;
case 2:
write_addr_UINT32(mipi_tx_send_data, (data[size - 1] << 8) + data[size - 2]);
break;
case 3:
write_addr_UINT32(mipi_tx_send_data, (data[size - 1] << 16) + (data[size - 2] << 8) + data[size - 3]);
break;
default:
break;
}
write_addr_UINT8(mipi_tx_send_requset,0x00);
write_addr_UINT8(mipi_tx_trigger_pulse,0x03);
while (0 == (read_addr_UINT8(mipi_tx_send_done) & mipi_tx_send_done_mask));
}
else
{
write_addr_UINT8(mipi_tx_lp_hs_mode, mipi_state); // mipi tx lp send cmd enable
write_addr_UINT8(mipi_tx_send_requset, 0x01); // 向mipi tx发出申请，拉高
write_addr_UINT32(mipi_tx_send_data, (0x05 + (data[0] << 8))); // mipi tx发送的数据
write_addr_UINT8(mipi_tx_send_requset, 0x00); // 完成数据发送后，拉低wrqst
write_addr_UINT8(mipi_tx_trigger_pulse, 0x03); // 随后发triiger pulse，触发mipi tx工作
while (0 == (read_addr_UINT8(mipi_tx_send_done) & mipi_tx_send_done_mask));
}
drv_mipi_tx_write_data(data, size, mipi_state);
return true;
}
@ -210,5 +123,16 @@ bool hal_dsi_tx_ctrl_read_cmd(uint8_t data_type, uint8_t vc, uint8_t cmd, uint8_
return false;
}
drv_mipi_tx_lprd_clear();
drv_mipi_tx_set_max_size(size);
delay_ms(100);
drv_mipi_tx_read_data(cmd);
uint32_t result = drv_mipi_tx_get_read_result();
for(int i = 0; i < size; i++)
{
data[i] = ((result >> i) & 0xFF);
}
return true;
}

106
src/include/hal_edp_rx.h Normal file
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@ -0,0 +1,106 @@
/*******************************************************************************
* File: hal_edp_rx.h
* Description: edp rx模块接口
* Version: V1.0
* Date: 2026-2-27
* Author: lyp
*******************************************************************************/
#ifndef __HAL_EDP_RX_H__
#define __HAL_EDP_RX_H__
#include <stdarg.h>
#include "la_config.h"
/**
* @brief SDP数据
* @note
*/
typedef struct _SDP_Info
{
uint8_t SDP_HB[4];
uint8_t SDP_DB[32];
uint8_t SDP_ERR_FLAG[4];
}SDP_Info;
/**
* @brief DPCD地址及对应数据
* @note dpcd_address是DPCD地址
* dpcd_value是DPCD地址里对应的数值
*/
typedef struct _DPCD_Packet
{
uint32_t dpcd_address;
uint8_t dpcd_value;
}DPCD_Packet;
/* SDP更新回调，用于获取second data packet */
typedef void (*hal_edp_rx_sdp_cb)(SDP_Info sdp_info);
/* 休眠回调，当基板通过AUX往DPCD寄存器600H写02时触发 */
typedef void (*hal_edp_rx_sleep_cb)(void);
/* 唤醒回调，当基板reset脚拉高触发 */
typedef void (*hal_edp_rx_wake_cb)(void);
/**
* @brief SDP更新回调注册
* @note sleep_cb是唤醒回调地址
* execute_mode是执行方式：true-在中断里立即执行,false-加入队列异步执行
*/
typedef struct _SDP_Handle
{
hal_edp_rx_sdp_cb sdp_cb;
bool execute_mode;
}SDP_Handle;
/**
* @brief 休眠回调注册
* @note sleep_cb是唤醒回调地址
* execute_mode是执行方式：true-在中断里立即执行,false-加入队列异步执行
*/
typedef struct _Sleep_Handle
{
hal_edp_rx_sleep_cb sleep_cb;
bool execute_mode;
}Sleep_Handle;
/**
* @brief 唤醒回调注册
* @note wake_cb是唤醒回调地址
* execute_mode是执行方式：true-在中断里立即执行,false-加入队列异步执行
* 需在上位机设置基板reset脚接在芯片具体管脚
*/
typedef struct _WAKE_Handle
{
hal_edp_rx_wake_cb wake_cb;
bool execute_mode;
}WAKE_Handle;
/**
* @brief rx相关功能回调
* @note
*/
typedef struct _RX_CB_Handle
{
SDP_Handle sdp_handle;
Sleep_Handle sleep_handle;
WAKE_Handle wake_handle;
}RX_CB_Handle;
/**
* @brief 注册rx相关回调
* @param RX_CB_Handle: rx回调参数结构体
* @retval true-注册成功；false-注册失败
*/
bool hal_edp_rx_cb_init(RX_CB_Handle *rx_cb_handle);
/**
* @brief 初始化DPCD寄存器
* @param table_address: DPCD数据表地址
* @param table_size: DPCD数据表大小
* @retval true-初始化正常；false-初始化异常
*/
bool hal_edp_rx_dpcd_init(const DPCD_Packet *table_address, uint32_t table_size);
#endif

95
src/include/typedef.h
View File

@ -43,6 +43,101 @@ typedef uint32 uint32_t;
#define NULL ((void *)0)
/************************************************************************通用操作*****************************************************************/
/** \brief bit移位
* TAU_BIT(2) is 0x4
*/
#define TAU_BIT(bit) (1u << (bit))
/** \brief 值移位
* TAU_SBF(0xFF, 8) is 0xff00
*/
#define TAU_SBF(value, field) ((value) << (field))
/** \brief bit置位
* TAU_BIT_SET(0, 8) is 0x100
*/
#define TAU_BIT_SET(data, bit) ((data) |= TAU_BIT(bit))
/** \brief bit清零
* TAU_BIT_CLR(0xFF, 2) is 0xfb
*/
#define TAU_BIT_CLR(data, bit) ((data) &= ~TAU_BIT(bit))
/** \brief bit置位, 根据 mask 指定的位
* TAU_BIT_SET_MASK(0xF0F0, 0xF00) is 0xfff0
*/
#define TAU_BIT_SET_MASK(data, mask) ((data) |= (mask))
/** \brief bit清零, 根据 mask 指定的位
* TAU_BIT_CLR_MASK(0xFFFF, 0xFF00) is 0xff
*/
#define TAU_BIT_CLR_MASK(data, mask) ((data) &= ~(mask))
/** \brief bit翻转
* TAU_BIT_TOGGLE(0xFFFF, 0) is 0xfffe
* TAU_BIT_TOGGLE(0x0000, 1) is 0x2
*/
#define TAU_BIT_TOGGLE(data, bit) ((data) ^= TAU_BIT(bit))
/** \brief bit修改
* TAU_BIT_MODIFY(0, 8, 1) is 0x100
* TAU_BIT_MODIFY(0xFFFF, 1, 0) is 0xfffd
*/
#define TAU_BIT_MODIFY(data, bit, value) \
((value) ? TAU_BIT_SET(data, bit) : TAU_BIT_CLR(data, bit))
/** \brief 测试bit是否置位
* TAU_BIT_ISSET(0xF0F1, 1) is 0
* TAU_BIT_ISSET(0xF0F2, 1) is 2
*/
#define TAU_BIT_ISSET(data, bit) ((data) & TAU_BIT(bit))
/** \brief 获取bit值
* TAU_BIT_GET(0xF0F1, 1) is 0
* TAU_BIT_GET(0xF0F2, 1) is 1
*/
#define TAU_BIT_GET(data, bit) (TAU_BIT_ISSET(data, bit) ? 1 : 0)
/** \brief 检测bit值是否为零
* TAU_BIT_CHECK(0xF5FF, 4) is false(0)
*/
#define TAU_BIT_CHECK_ZERO(data, bit) \
(((data) & TAU_BIT(bit)) ? 0 : 1)
/** \brief 获取 n bits 掩码值
* TAU_BITS_MASK(2) is 0x3
*/
#define TAU_BITS_MASK(n) (~((~0u) << (n)))
/** \brief 获取位段值
* TAU_BITS_GET(0xF5FF, 0x0F00, 8) is 0x5
*/
#define TAU_BITS_GET(data, mask, pos) \
(((data) & (mask)) >> (pos))
/** \brief 获取位段值
* TAU_BITS_CHECK(0xF5FF, 0x0F00) is 1
*/
#define TAU_BITS_CHECK(data, mask) \
(((data) & (mask)) ? 1 : 0)
/** \brief 修改位段值
* TAU_BITS_MODIFY(0xF5FF, 0x0FF0, 0x8A0) is 0xF8AF
*/
#define TAU_BITS_MODIFY(data, clear_mask, set_mask) \
(data) = (((data) & (~(clear_mask))) | (set_mask))
/** \brief 设置位段值
* TAU_WRITE_REG32(0x05FF, 0xFFFA) is 0xFFFA
*/
#define TAU_WRITE_REG32(data, value) ((data) = (value))
/** \brief 设置位段值
* TAU_RAED_REG32(0x05FF) is 0x05FF
*/
#define TAU_RAED_REG32(data) (data)
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))